sass stringlengths 231 30.8k | rdna stringlengths 69 28.4k | function_name stringlengths 1 85 | sass_tokens int64 90 14.4k ⌀ | rdna_tokens int64 11 14.5k ⌀ | source stringclasses 15 values |
|---|---|---|---|---|---|
// Demangled: exp(float*, float*)
Function : _Z3expPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans1;
HFMA2 R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ?trans1;
MOV R7, 0x437c0000 ?WAIT4_END_GROUP;
FFMA.SAT R0, R2, R5, 0.5 &req={2} ?WAIT4_END_GROUP;
FFMA.RM R0, R0, R7, 12582913 ?WAIT4_END_GROUP;
FADD R5, R0.reuse, -12583039 ?trans1;
SHF.L.U32 R0, R0, 0x17, RZ ?WAIT3_END_GROUP;
FFMA R5, R2, 1.4426950216293334961, -R5 ?WAIT4_END_GROUP;
FFMA R6, R2, 1.925963033500011079e-08, R5 ?trans2;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans2;
MUFU.EX2 R7, R6 &wr=0x1 ?trans2;
FMUL R7, R0, R7 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: exp(float*, float*)
_Z3expPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v0, 0x3fb8aa3b, s0
v_cmp_ngt_f32_e64 vcc_lo, 0xc2ce8ed0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v1, 0x3fb8aa3b, s0, -v0
v_rndne_f32_e32 v2, v0
v_dual_fmamk_f32 v1, s0, 0x32a5705f, v1 :: v_dual_sub_f32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v0, v1
v_cvt_i32_f32_e32 v1, v2
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_ldexp_f32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v1, 0 :: v_dual_cndmask_b32 v0, 0, v0
v_cmp_nlt_f32_e64 vcc_lo, 0x42b17218, s0
v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| exp | 545 | 514 | stackv2-00000-of-00015 |
// Demangled: mul(float*, float*, float*)
Function : _Z3mulPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans3;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
FMUL R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mul(float*, float*, float*)
_Z3mulPfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v1, s2, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mul | 324 | 191 | stackv2-00000-of-00015 |
// Demangled: pow(float*, float*, float*)
Function : _Z3powPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans2;
LDG.E R0, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans6;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans2;
LDG.E R3, desc[UR4][R2.64] &req={1} &rd=0x1 &wr=0x3 ?trans1;
HFMA2 R13, -RZ, RZ, 0.771484375, 0.21533203125 ?trans1;
FSETP.GEU.AND P0, PT, |R0|.reuse, 1.175494350822287508e-38, PT &req={2} ?trans1;
FMUL R7, |R0|, 16777216 ?WAIT4_END_GROUP;
FSEL R2, RZ, -24, P0 &req={1} ?trans1;
FSEL R7, R7, |R0|, !P0 ?WAIT5_END_GROUP;
IADD3 R6, PT, PT, R7, -0x3f3504f3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R6, R6, 0xff800000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
I2FP.F32.S32 R5, R6.reuse ?trans2;
IADD3 R7, PT, PT, R7, -R6, RZ ?WAIT3_END_GROUP;
FFMA R2, R5, 1.1920928955078125e-07, R2 ?trans2;
FADD R8, R7.reuse, 1 ?trans1;
FADD R7, R7, -1 ?WAIT4_END_GROUP;
FADD R9, R7, R7 ?trans1;
MUFU.RCP R8, R8 &wr=0x1 ?trans3;
FMUL R9, R8, R9 &req={1} ?WAIT4_END_GROUP;
FADD R5, R7, -R9 ?trans1;
FMUL R4, R9.reuse, R9 ?trans1;
FFMA R11, R9, 1.4426950216293334961, R2 ?trans2;
FADD R6, R5, R5 ?trans1;
FFMA R5, R4, R13, 0.0032181653659790754318 ?trans1;
FADD R2, R2, -R11 ?trans2;
FFMA R7, R7, -R9, R6 ?trans1;
FFMA R5, R4, R5, 0.018033718690276145935 ?trans1;
FFMA R2, R9, 1.4426950216293334961, R2 ?WAIT2_END_GROUP;
FMUL R7, R8, R7 ?trans1;
FFMA R5, R4, R5, 0.12022458761930465698 ?WAIT3_END_GROUP;
FFMA R2, R7, 1.4426950216293334961, R2 ?trans1;
FMUL R4, R4, R5 ?WAIT3_END_GROUP;
FFMA R2, R9, 1.9251366722983220825e-08, R2 ?trans1;
FMUL R5, R4, 3 ?WAIT4_END_GROUP;
FFMA R5, R7, R5, R2 ?WAIT4_END_GROUP;
FFMA R4, R9, R4, R5 ?trans1;
MOV R9, 0x391fcb8e ?WAIT3_END_GROUP;
FADD R2, R11, R4 ?WAIT4_END_GROUP;
FMUL R6, R3, R2 &req={3} ?trans1;
FADD R11, -R11, R2 ?WAIT3_END_GROUP;
FRND R7, R6 &wr=0x1 ?trans1;
FADD R4, R4, -R11 ?trans1;
FFMA R5, R3.reuse, R2, -R6 ?trans1;
FSETP.GT.AND P1, PT, |R6|.reuse, 152, PT ?trans1;
FSETP.GEU.AND P2, PT, R6.reuse, RZ, PT ?trans2;
FFMA R4, R3, R4, R5 ?trans1;
F2I.NTZ R2, R6 &wr=0x2 ?trans1;
FADD R5, R6, -R7 &req={1} ?trans1;
FSETP.GT.AND P0, PT, R7, RZ, PT ?WAIT3_END_GROUP;
FADD R4, R4, R5 ?trans2;
SEL R7, RZ, 0x83000000, P0 ?trans1;
FSETP.NEU.AND P0, PT, R3, RZ, PT ?trans1;
FFMA R5, R4, R9, 0.0013391353422775864601 ?WAIT3_END_GROUP;
IADD3 R8, PT, PT, R7, 0x7f000000, RZ ?trans1;
FFMA R5, R4, R5, 0.0096188392490148544312 ?trans1;
FSETP.EQ.OR P0, PT, R0, 1, !P0 ?trans1;
LEA R2, R2, -R7, 0x17 &req={2} ?trans2;
FFMA R5, R4, R5, 0.055503588169813156128 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, 0.24022644758224487305 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, 0.69314718246459960938 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, 1 ?WAIT4_END_GROUP;
FMUL R5, R5, R8 ?WAIT4_END_GROUP;
FMUL R2, R5, R2 ?trans1;
HFMA2 R5, -RZ, RZ, 1.875, 0 ?trans1;
@P1 FSEL R2, RZ, +INF , !P2 ?trans1;
@P0 BRA 0x5f0 &req={0} ?trans6;
FSETP.NAN.AND P0, PT, |R3|, |R3|, PT ?WAIT5_END_GROUP;
FSETP.NUM.AND P0, PT, |R0|, |R0|, !P0 ?WAIT13_END_GROUP;
@!P0 FADD R5, R0, R3 ?trans1;
@!P0 BRA 0x5f0 ?trans6;
FMUL R4, R3, 0.5 ?trans1;
FSETP.NEU.AND P0, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.AND P1, PT, R0, RZ, PT ?WAIT4_END_GROUP;
FRND.TRUNC R4, R4 &wr=0x0 ?trans2;
FADD R6, R4, R4 &req={0} ?WAIT4_END_GROUP;
FADD R6, R3, -R6 ?WAIT3_END_GROUP;
@P0 BRA P1, 0x550 ?trans5;
FSETP.GEU.AND P1, PT, R3, RZ, PT ?trans1;
FSETP.NEU.AND P0, PT, |R6|, 1, PT ?trans1;
FADD R5, R0, R0 ?WAIT11_END_GROUP;
@!P1 LOP3.LUT R5, R5, 0x7f800000, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
@P0 LOP3.LUT R5, R5, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
BRA 0x5f0 ?trans6;
FSETP.NEU.AND P0, PT, |R3|, +INF , PT ?trans1;
FSETP.EQ.AND P1, PT, R0, -1, PT ?WAIT13_END_GROUP;
@!P0 BRA P1, 0x5f0 ?trans5;
FSETP.GEU.AND P1, PT, R0, RZ, PT ?trans1;
MOV R5, R2 ?WAIT12_END_GROUP;
@!P1 FRND.FLOOR R0, R3 &wr=0x0 ?trans1;
@!P1 FSETP.NEU.AND P2, PT, |R6|, 1, PT ?trans1;
@!P1 FSETP.NEU.AND P0, PT, R3, R0, PT &req={0} ?WAIT4_END_GROUP;
@!P1 FSEL R0, R2, -R2, P2 ?WAIT5_END_GROUP;
@!P1 FSEL R5, R0, +QNAN , !P0 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans2;
STG.E desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x620;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: pow(float*, float*, float*)
_Z3powPfS_S_:
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[8:9], 0x0
s_load_b32 s1, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_neq_f32_e64 s2, s0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 1.0, s1, s2
v_cmp_neq_f32_e32 vcc_lo, 0, v0
v_cmp_neq_f32_e64 s3, v0, |v0|
v_cndmask_b32_e64 v1, 1.0, s0, vcc_lo
s_mov_b32 s0, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_frexp_mant_f32_e64 v2, |v1|
v_cmp_lt_f32_e64 s6, |v1|, 1.0
v_cmp_eq_f32_e64 s2, 0, v1
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s6
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_ldexp_f32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, -1.0, v2
v_add_f32_e32 v3, 1.0, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v6, v5, v4 :: v_dual_add_f32 v7, -1.0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v8, v3, v6
v_sub_f32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, v6, v3, -v8
v_fmac_f32_e32 v3, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v8, v3
v_dual_sub_f32 v7, v5, v2 :: v_dual_sub_f32 v8, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v8, v3
v_sub_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v5, v2
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v7, v2
v_mul_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v6, v2
v_mul_f32_e32 v5, v3, v3
v_sub_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v2, v2, v4
v_fma_f32 v4, v3, v3, -v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v2, v2
v_fmac_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v5, v4
v_fmaak_f32 v7, s0, v6, 0x3e91f4c4
v_sub_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v7, v6, v7, 0x3ecccdef :: v_dual_sub_f32 v4, v4, v5
v_mul_f32_e32 v8, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v6, v7, -v8
v_dual_fmac_f32 v5, v4, v7 :: v_dual_mul_f32 v10, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, v8, v5
v_fma_f32 v11, v6, v3, -v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v8, v7, v8 :: v_dual_fmac_f32 v11, v6, v2
v_add_f32_e32 v9, 0x3f2aaaaa, v7
v_ldexp_f32 v2, v2, 1
v_sub_f32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v4, v3
v_ldexp_f32 v3, v3, 1
v_add_f32_e32 v5, 0x31739010, v5
v_add_f32_e32 v8, 0xbf2aaaaa, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v8
v_add_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v9, v5
v_dual_add_f32 v6, v10, v11 :: v_dual_sub_f32 v7, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v8, v6, v4
v_sub_f32_e32 v9, v6, v10
v_add_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v7, v6, v4, -v8
v_sub_f32_e32 v9, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v6, v5
v_frexp_exp_i32_f32_e32 v5, v1
v_fmac_f32_e32 v7, v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
v_add_f32_e32 v5, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v4, v4
v_sub_f32_e32 v8, v5, v8
v_add_f32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v8
v_dual_mul_f32 v9, 0x3f317218, v4 :: v_dual_add_f32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, 0x3f317218, v4, -v9
v_dual_fmamk_f32 v4, v4, 0xb102e308, v8 :: v_dual_sub_f32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v5, v3
v_dual_add_f32 v2, v2, v3 :: v_dual_add_f32 v3, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v6, v2
v_sub_f32_e32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v4, v9
v_add_f32_e32 v7, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v7, v3
v_sub_f32_e32 v6, v5, v6
v_sub_f32_e32 v10, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v2, v2, v6 :: v_dual_sub_f32 v5, v5, v8
v_sub_f32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v4, v2 :: v_dual_add_f32 v3, v5, v3
v_sub_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v6, v3
v_sub_f32_e32 v6, v6, v5
v_sub_f32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v4, v4, v6
v_add_f32_e32 v8, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, v2, v4 :: v_dual_sub_f32 v5, v8, v7
v_sub_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
v_add_f32_e32 v3, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v3, v8 :: v_dual_mul_f32 v5, v0, v3
v_sub_f32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v3, v0, v3, -v5
v_cmp_class_f32_e64 vcc_lo, v5, 0x204
v_fmac_f32_e32 v3, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v5, v3
v_cndmask_b32_e32 v4, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
v_sub_f32_e32 v7, v4, v6
v_trunc_f32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x3fb8aa3b, v7
v_fma_f32 v9, 0x3fb8aa3b, v7, -v8
v_rndne_f32_e32 v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_fmamk_f32 v9, v7, 0x32a5705f, v9 :: v_dual_sub_f32 v8, v8, v10
v_sub_f32_e32 v2, v2, v5
v_cvt_i32_f32_e32 v5, v10
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v2, v3, v2
v_exp_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
v_add_f32_e32 v2, v6, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v8, v5
v_mul_f32_e32 v5, 0.5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
v_trunc_f32_e32 v8, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v4, v0
v_cmp_neq_f32_e64 s0, v8, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v2, v3, v2, v3
v_cmp_eq_f32_e64 s1, 0x7f800000, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, 1.0, v1, s0
v_cndmask_b32_e64 v2, v2, v3, s1
v_cmp_gt_f32_e64 s1, 0, v0
v_cndmask_b32_e64 v3, |v0|, 0, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v2, 0x7fffffff, v2, v4
s_xor_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0x7f800000, 0, s1
v_cmp_eq_f32_e64 s1, |v1|, 1.0
v_cndmask_b32_e32 v4, 0x7fc00000, v2, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, |v1|, s1
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cndmask_b32_e64 v4, 0, v1, s0
v_cmp_class_f32_e64 vcc_lo, v0, 0x204
v_cmp_class_f32_e64 s0, v1, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_bfi_b32 v3, 0x7fffffff, v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 vcc_lo, s2, s0
v_dual_cndmask_b32 v2, v2, v3 :: v_dual_mov_b32 v3, 0
v_cmp_o_f32_e32 vcc_lo, v1, v0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
global_store_b32 v3, v0, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| pow | 2,515 | 5,228 | stackv2-00000-of-00015 |
// Demangled: sub(float*, float*, float*)
Function : _Z3subPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans3;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
FADD R9, R2, -R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sub(float*, float*, float*)
_Z3subPfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s2, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sub | 325 | 191 | stackv2-00000-of-00015 |
// Demangled: kern(float*)
Function : _Z4kernPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R5, R5, UR6, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
FADD R5, R0, 3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kern(float*)
_Z4kernPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x40400000, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kern | 342 | 371 | stackv2-00000-of-00015 |
// Demangled: colorToGreyscaleConvertion(int*, int*, int, int)
Function : _Z26colorToGreyscaleConvertionPiS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x1 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R5, R2, UR5, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR7, PT &req={3} ?trans1;
IMAD R0, R3, UR4, R0 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R7, R5, UR6, R0 ?WAIT5_END_GROUP;
LEA R5, R7, R7, 0x1 ?WAIT5_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R4, desc[UR4][R2.64+0x4] &req={1} &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R2.64] &wr=0x3 ?trans4;
LDG.E R6, desc[UR4][R2.64+0x8] &wr=0x4 ?trans1;
I2FP.F32.U32 R8, R4 &req={2} ?trans2;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
I2FP.F32.U32 R0, R0 &req={3} ?WAIT2_END_GROUP;
FMUL R9, R8, 0.72000002861022949219 ?trans1;
I2FP.F32.U32 R11, R6 &req={4} ?WAIT3_END_GROUP;
FFMA R0, R0, 0.20999999344348907471, R9 ?WAIT4_END_GROUP;
FFMA R0, R11, 0.070000000298023223877, R0 ?WAIT4_END_GROUP;
F2I.TRUNC.NTZ R9, R0 &wr=0x1 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R9 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: colorToGreyscaleConvertion(int*, int*, int, int)
_Z26colorToGreyscaleConvertionPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, v3, 1, v3
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b96 v[0:2], v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v1, v1
v_cvt_f32_u32_e32 v0, v0
v_cvt_f32_u32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x3f3851ec, v1
v_fmamk_f32 v0, v0, 0x3e570a3d, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v2, v2, 0x3d8f5c29, v0
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| colorToGreyscaleConvertion | 910 | 1,047 | stackv2-00000-of-00015 |
// Demangled: cuda_matmul(float*, float*, float*, int, int, int)
Function : _Z11cuda_matmulPfS_S_iii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R17, c[0x0][0x3a0] &wr=0x1 ?trans1;
S2R R19, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
S2R R4, SR_TID.Y &wr=0x4 ?trans4;
LDC R0, c[0x0][0x360] &wr=0x2 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x4 ?trans1;
ISETP.GE.AND P0, PT, R17, -0xe, PT &req={1} ?WAIT7_END_GROUP;
LDC R5, c[0x0][0x364] &wr=0x4 ?trans1;
IMAD R3, R0, UR4, R19 &req={2} ?trans2;
IMAD R2, R5, UR5, R4 &req={4} ?WAIT3_END_GROUP;
@!P0 BRA 0x5f0 &req={3,0} ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R17, -0x1, RZ ?trans1;
LDCU UR7, c[0x0][0x39c] &wr=0x1 ?trans1;
MOV R9, RZ ?trans1;
IMAD R17, R2, R17, R19 ?trans1;
UMOV UR4, 0x400 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ?trans2;
LDC R16, c[0x0][0x39c] &wr=0x2 ?trans1;
LDCU UR11, c[0x0][0x3a0] &wr=0x3 ?trans1;
LEA.HI R5, R5, R0, RZ, 0x4 ?trans1;
MOV R0, R4 ?trans1;
LDCU UR10, c[0x0][0x398] &wr=0x4 ?trans2;
SHF.R.S32.HI R5, RZ, 0x4, R5 ?WAIT2_END_GROUP;
IMAD R21, R0, UR7, R3 &req={1} ?trans2;
IADD3 R24, PT, PT, -R5, RZ, RZ ?trans1;
ULEA UR6, UR5, UR4, 0x18 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x400, URZ ?WAIT4_END_GROUP;
ULEA UR4, UR5, UR4, 0x18 ?trans1;
LEA R18, R0, UR6, 0x6 ?WAIT4_END_GROUP;
LEA R22, R19.reuse, R18, 0x2 ?trans2;
LEA R23, R19, UR4, 0x2 ?WAIT4_END_GROUP;
LEA R20, R0, R23, 0x6 &req={4,3} ?WAIT7_END_GROUP;
ISETP.GE.AND P1, PT, R19, UR11, PT ?trans1;
ISETP.GE.AND P0, PT, R0, UR11, PT ?trans1;
MOV R25, RZ ?trans1;
HFMA2 R27, -RZ, RZ, 0, 0 ?trans2;
ISETP.GE.OR P1, PT, R2, UR10, P1 ?trans1;
ISETP.GE.OR P0, PT, R3, R16, P0 &req={2} ?WAIT12_END_GROUP;
@!P1 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans8;
@!P0 LDC.64 R10, c[0x0][0x388] &wr=0x1 ?trans1;
@!P1 IMAD.WIDE R4, R17, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
@!P1 LDG.E R25, desc[UR8][R4.64] &wr=0x2 ?trans1;
@!P0 IMAD.WIDE R10, R21, 0x4, R10 &req={1} ?WAIT5_END_GROUP;
@!P0 LDG.E R27, desc[UR8][R10.64] &wr=0x3 ?trans1;
IADD3 R24, PT, PT, R24, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R24, 0x1, PT ?trans1;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans2;
IADD3 R19, PT, PT, R19, 0x10, RZ ?trans2;
IADD3 R17, PT, PT, R17, 0x10, RZ ?trans2;
LEA R21, R16, R21, 0x4 ?trans1;
STS [R22], R25 &req={2} ?trans4;
STS [R20], R27 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R8, [R23] ?trans4;
LDS.128 R12, [R18] &wr=0x0 ?trans4;
LDS R29, [R23+0x40] &wr=0x1 ?trans4;
LDS R34, [R23+0x80] &wr=0x2 ?trans4;
LDS R32, [R23+0xc0] &wr=0x3 ?trans4;
LDS R31, [R23+0x100] ?trans4;
LDS.128 R4, [R18+0x10] &wr=0x4 ?trans4;
LDS R28, [R23+0x140] &wr=0x5 ?trans4;
LDS R25, [R23+0x180] &wr=0x5 ?trans4;
LDS R26, [R23+0x1c0] &wr=0x5 ?trans4;
LDS R27, [R23+0x200] ?trans1;
FFMA R12, R12, R8, R9 &req={0} ?WAIT3_END_GROUP;
LDS R30, [R23+0x240] ?trans4;
LDS.128 R8, [R18+0x20] &wr=0x0 ?trans1;
FFMA R13, R29, R13, R12 &req={1} ?WAIT3_END_GROUP;
LDS R29, [R23+0x280] &wr=0x1 ?trans1;
FFMA R13, R34, R14, R13 &req={2} ?WAIT4_END_GROUP;
FFMA R13, R32, R15, R13 &req={3} ?trans2;
LDS R32, [R23+0x2c0] &wr=0x2 ?trans2;
FFMA R33, R4, R31, R13 &req={4} ?trans2;
LDS R31, [R23+0x300] ?trans4;
LDS.128 R12, [R18+0x30] &wr=0x3 ?trans1;
FFMA R34, R28, R5, R33 &req={5} ?WAIT3_END_GROUP;
LDS R28, [R23+0x340] &wr=0x4 ?trans4;
LDS R5, [R23+0x380] &wr=0x5 ?trans4;
LDS R4, [R23+0x3c0] &wr=0x5 ?trans1;
FFMA R25, R25, R6, R34 ?WAIT4_END_GROUP;
FFMA R7, R26, R7, R25 ?WAIT4_END_GROUP;
FFMA R7, R8, R27, R7 &req={0} ?WAIT4_END_GROUP;
FFMA R30, R30, R9, R7 ?WAIT4_END_GROUP;
FFMA R29, R29, R10, R30 &req={1} ?WAIT4_END_GROUP;
FFMA R11, R32, R11, R29 &req={2} ?WAIT4_END_GROUP;
FFMA R11, R12, R31, R11 &req={3} ?WAIT4_END_GROUP;
FFMA R28, R28, R13, R11 &req={4} ?WAIT4_END_GROUP;
FFMA R5, R5, R14, R28 &req={5} ?WAIT4_END_GROUP;
FFMA R9, R4, R15, R5 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x240 ?trans5;
LDCU.64 UR4, c[0x0][0x398] &wr=0x0 ?trans2;
ISETP.GE.AND P0, PT, R2, UR4, PT &req={0} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R3, UR5, P0 ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R3, R2, UR5, R3 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x680;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cuda_matmul(float*, float*, float*, int, int, int)
_Z11cuda_matmulPfS_S_iii:
s_clause 0x3
s_load_b32 s12, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s12, 16
s_and_b32 s1, s12, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s15, s0, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s1, v[4:5]
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s6, -14
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_gt_i32_e64 s0, s5, v1
s_cbranch_scc1 .LBB0_14
v_lshlrev_b32_e32 v2, 2, v4
s_add_i32 s1, s6, -1
v_lshlrev_b32_e32 v5, 6, v3
s_ashr_i32 s7, s1, 31
v_mul_lo_u32 v7, v0, s6
v_add_nc_u32_e32 v6, 0x400, v2
s_lshr_b32 s7, s7, 28
v_add_nc_u32_e32 v8, v5, v2
v_mov_b32_e32 v2, 0
s_add_i32 s1, s1, s7
v_add_nc_u32_e32 v9, v6, v5
s_ashr_i32 s7, s1, 4
s_mov_b32 s12, 0
.LBB0_2:
v_mov_b32_e32 v10, 0
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v11, s12, 4, v4
v_mov_b32_e32 v10, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s6, v11
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v10, v11, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s8, v10
v_add_co_ci_u32_e64 v11, s1, s9, v11, s1
global_load_b32 v10, v[10:11], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v11, 0
s_waitcnt vmcnt(0)
ds_store_b32 v8, v10
s_and_saveexec_b32 s13, s0
s_cbranch_execz .LBB0_10
v_lshl_add_u32 v10, s12, 4, v3
v_mov_b32_e32 v11, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s6, v10
s_cbranch_execz .LBB0_9
v_mad_u64_u32 v[11:12], null, v10, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[10:11], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s10, v10
v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
global_load_b32 v11, v[10:11], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v10, v6
s_mov_b32 s1, 0
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v11, s1, v5
s_add_i32 s1, s1, 4
ds_load_b32 v12, v10
ds_load_b32 v11, v11
v_add_nc_u32_e32 v10, 64, v10
s_cmp_eq_u32 s1, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s1, s12, 1
s_cmp_eq_u32 s12, s7
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
s_mov_b32 s12, s1
s_branch .LBB0_2
.LBB0_14:
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_cmp_gt_i32_e64 s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_mad_u64_u32 v[3:4], null, v0, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| cuda_matmul | 2,610 | 2,061 | stackv2-00000-of-00015 |
// Demangled: trspta2(int*, int*, int, int)
Function : _Z7trspta2PiS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans1;
LDCU UR8, c[0x0][0x360] &wr=0x3 ?trans1;
S2R R8, SR_TID.X &wr=0x4 ?trans1;
LDCU UR9, c[0x0][0x364] &wr=0x2 ?trans5;
S2UR UR4, SR_CTAID.X &wr=0x3 ?trans1;
LDCU.64 UR10, c[0x0][0x390] &wr=0x5 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
UIMAD UR5, UR5, UR9, URZ &req={2} ?WAIT6_END_GROUP;
IADD3 R5, PT, PT, R9, UR5, RZ &req={1} ?trans1;
UIMAD UR4, UR4, UR8, URZ &req={3} ?WAIT4_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR10, PT &req={5} ?trans2;
IADD3 R0, PT, PT, R8, UR4, RZ &req={4} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR11, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
@!P0 IMAD R5, R5, UR11, R0 ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
@!P0 LDG.E R2, desc[UR6][R2.64] &req={0} &wr=0x2 ?trans1;
IMAD R0, R8.reuse, UR9, RZ ?trans1;
@!P0 MOV R4, 0x400 ?trans1;
IADD3 R7, PT, PT, R8, UR5, RZ ?trans1;
@!P0 S2R R5, SR_CgaCtaId &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R9, UR4, RZ ?trans2;
@!P0 IADD3 R0, PT, PT, R0, R9, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R7, UR10, PT ?WAIT5_END_GROUP;
ISETP.GE.U32.OR P1, PT, R6, UR11, P1 ?trans1;
@!P0 LEA R5, R5, R4, 0x18 &req={0} ?WAIT5_END_GROUP;
@!P0 IMAD R5, R0, 0x4, R5 ?trans2;
IMAD R0, R9, UR8, R8 ?WAIT3_END_GROUP;
@!P0 STS [R5], R2 &req={2} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R7, R6, UR10, R7 ?WAIT6_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R0, R0, UR4, 0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
LDS R5, [R0] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: trspta2(int*, int*, int, int)
_Z7trspta2PiS_ii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s8, 0xffff
s_lshr_b32 s8, s8, 16
s_mul_i32 s14, s14, s1
s_mul_i32 s15, s15, s8
v_add_nc_u32_e32 v0, s14, v1
v_add_nc_u32_e32 v3, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s0, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, vcc_lo, s0
s_and_saveexec_b32 s0, s9
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mul_u32_u24_e32 v3, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v3, v3, v2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, s14, v2
v_add_nc_u32_e32 v0, s15, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e32 vcc_lo, s3, v3
v_cmp_gt_u32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_4
v_mul_u32_u24_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_lshl_u32 v4, v2, v1, 2
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
v_mov_b32_e32 v2, 0
ds_load_b32 v3, v4
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| trspta2 | 1,111 | 1,105 | stackv2-00000-of-00015 |
// Demangled: update_nmb_infected_cells(int, float*, float*)
Function : _Z25update_nmb_infected_cellsiPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R5, 0x19, PT &req={1} ?WAIT13_END_GROUP;
@P0 BRA 0x9d0 &req={2} ?trans5;
LDC R12, c[0x0][0x380] &wr=0x1 ?trans1;
HFMA2 R3, -RZ, RZ, 0.000767230987548828125, 0.017852783203125 ?WAIT5_END_GROUP;
IMAD R0, R12.reuse, -0x49249249, R3 &req={1} ?trans1;
ISETP.GE.AND P1, PT, R12, 0x18, PT ?WAIT4_END_GROUP;
SHF.R.W.U32 R0, R0, 0x1, R0 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x12492492, PT ?WAIT13_END_GROUP;
@P0 BRA 0x150 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
LDG.E R0, desc[UR4][R2.64+0x64] &req={1} &wr=0x3 ?trans4;
LDG.E R7, desc[UR4][R4.64+0x64] &req={2} &wr=0x3 ?trans2;
FADD R7, -R0, R7 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x64], R7 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x64] &wr=0x2 ?trans2;
FMUL R9, R0, 22 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64+0x64], R9 &rd=0x1 ?trans2;
@!P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x390] &req={1} &wr=0x1 ?trans2;
LDG.E R0, desc[UR4][R2.64+0x64] &req={1} &wr=0x2 ?trans1;
I2F.F64.U32 R6, R12 &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3ee7012534fa9095 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R6, -UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3fe62e42fefa39ef ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R6, R4 &req={1} &rd=0x1 &wr=0x3 ?trans2;
MOV.64 R4, 0x3ff71547652b82fe &req={1} ?trans2;
FSETP.GEU.AND P0, PT, |R7|, 4.1917929649353027344, PT &req={3} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R6, R4, 6.75539944105574400000e+15 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R4, -6.75539944105574400000e+15 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, -UR6, R6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3c7abc9e3b39803f ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F64.F32 R12, R0 &req={2} &rd=0x2 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, -UR6, R10 &req={1} &rd=0x1 &wr=0x4 ?trans1;
UMOV.64 UR6, 0x3e5ade1569ce2bdf ?trans1;
MOV.64 R8, 0x3e928af3fca213ea &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, UR6, R8 &req={4} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3ec71dee62401315 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3efa01997c89eb71 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3f2a01a014761f65 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3f56c16c1852b7af ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3f81111111122322 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3fa55555555502a1 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3fc5555555555511 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3fe000000000000b ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, UR6 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, 1 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R8, 1 &req={1} &wr=0x1 ?trans2;
IMAD R11, R4, 0x100000, R9 &req={1} ?trans1;
MOV R10, R8 ?trans1;
@!P0 BRA 0x950 &req={3,2} ?trans6;
FSETP.GEU.AND P1, PT, |R7|, 4.2275390625, PT ?trans1;
DSETP.GEU.AND P0, PT, R6, RZ, PT ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, +INF &wr=0x1 ?trans2;
FSEL R10, R6, RZ, P0 &req={1} ?trans1;
FSEL R11, R7, RZ, P0 ?trans1;
@P1 BRA 0x950 ?trans6;
LEA.HI R0, R4, R4, RZ, 0x1 ?trans1;
MOV R10, RZ ?WAIT3_END_GROUP;
SHF.R.S32.HI R5, RZ, 0x1, R0 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R4, -R5, RZ ?trans1;
IMAD R9, R5, 0x100000, R9 ?WAIT3_END_GROUP;
LEA R11, R4, 0x3ff00000, 0x14 ?WAIT6_END_GROUP;
DMUL R10, R8, R10 &rd=0x1 &wr=0x2 ?trans2;
DMUL R12, R12, R10 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R13, R12 &req={2} &wr=0x2 ?trans2;
STG.E desc[UR4][R2.64+0x64], R13 &req={2} ?trans1;
EXIT ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans2;
FADD R5, RZ, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xa30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: update_nmb_infected_cells(int, float*, float*)
_Z25update_nmb_infected_cellsiPfS_:
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 25, v0
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, 0, v1
global_store_b32 v0, v1, s[4:5]
.LBB0_2:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s0, 0xb6db6db7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s1, 0x12492492
v_alignbit_b32 v0, s1, s1, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, 0x12492492, v0
s_cbranch_vccnz .LBB0_5
s_load_b32 s1, s[6:7], 0x64
s_load_b32 s2, s[4:5], 0x64
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s2, s1
global_store_b32 v0, v1, s[4:5] offset:100
global_load_b32 v1, v0, s[6:7] offset:100
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, 0x41b00000, v1
global_store_b32 v0, v1, s[6:7] offset:100
.LBB0_5:
s_cmp_lt_i32 s0, 24
s_cbranch_scc1 .LBB0_7
v_cvt_f64_i32_e32 v[0:1], s0
s_mov_b32 s0, 0x34fa9095
s_mov_b32 s1, 0xbee70125
s_mov_b32 s2, 0x6a5dcb37
s_mov_b32 s3, 0x3e5ade15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[0:1], s[0:1]
s_mov_b32 s0, 0x652b82fe
s_mov_b32 s1, 0x3ff71547
v_mul_f64 v[0:1], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[2:3], v[0:1], s[0:1]
s_mov_b32 s0, 0xfefa39ef
s_mov_b32 s1, 0xbfe62e42
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[0:1]
v_rndne_f64_e32 v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[2:3], s[0:1], v[0:1]
s_mov_b32 s0, 0x3b39803f
s_mov_b32 s1, 0xbc7abc9e
v_cvt_i32_f64_e32 v10, v[2:3]
v_fma_f64 v[4:5], v[2:3], s[0:1], v[4:5]
s_mov_b32 s0, 0xfca7ab0c
s_mov_b32 s1, 0x3e928af3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], s[2:3], s[0:1]
s_mov_b32 s0, 0x623fde64
s_mov_b32 s1, 0x3ec71dee
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 0x7c89e6b0
s_mov_b32 s1, 0x3efa0199
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 0x14761f6e
s_mov_b32 s1, 0x3f2a01a0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 0x1852b7b0
s_mov_b32 s1, 0x3f56c16c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 0x11122322
s_mov_b32 s1, 0x3f811111
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 0x555502a1
s_mov_b32 s1, 0x3fa55555
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 0x55555511
s_mov_b32 s1, 0x3fc55555
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
s_mov_b32 s0, 11
s_mov_b32 s1, 0x3fe00000
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[2:3], v[2:3], v10
v_dual_mov_b32 v8, 0 :: v_dual_cndmask_b32 v3, 0x7ff00000, v3
global_load_b32 v9, v8, s[6:7] offset:100
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cndmask_b32_e64 v3, 0, v3, s0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[2:3], v[0:1]
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v8, v0, s[6:7] offset:100
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| update_nmb_infected_cells | 3,120 | 2,418 | stackv2-00000-of-00015 |
// Demangled: force_aux0(long, double*, double*)
Function : _Z10force_aux0lPdS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R15, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR7, SR_CgaCtaId &wr=0x4 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x380] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R2, R15, 0x8, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R15, 0x8, R4 &req={3} ?trans2;
LDG.E.64 R2, desc[UR10][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR10][R4.64] &wr=0x3 ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x10, URZ ?trans1;
UIADD3 UR6, UPT, UPT, UR4, 0x1010, URZ ?trans1;
ULEA UR4, UR7, UR4, 0x18 &req={4} ?trans1;
MOV.64 R10, RZ ?WAIT2_END_GROUP;
ULEA UR5, UR7, UR5, 0x18 ?trans1;
ULEA UR6, UR7, UR6, 0x18 ?trans1;
ISETP.GE.S64.AND P0, PT, R12, 0x1, PT &req={5} ?trans2;
MOV.64 R8, RZ ?WAIT3_END_GROUP;
LEA R7, R15.reuse, UR5, 0x3 ?trans2;
LEA R15, R15, UR6, 0x3 ?WAIT3_END_GROUP;
STS.64 [R7], R2 &req={2} &rd=0x1 ?trans4;
STS.64 [R15], R4 &req={3} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
STS.128 [UR4], RZ ?trans1;
@!P0 BRA 0xdb0 &req={0} ?trans5;
LDC R0, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GE.U64.AND P1, PT, R12, 0x8, PT ?trans2;
HFMA2 R7, -RZ, RZ, 0, 0 &req={1} ?trans1;
MOV.64 R4, RZ ?trans2;
MOV.64 R10, RZ ?WAIT3_END_GROUP;
LOP3.LUT R6, R0, 0x7, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R6, RZ, PT ?trans2;
@!P1 BRA 0x850 ?WAIT12_END_GROUP;
LDCU UR7, c[0x0][0x384] &wr=0x0 ?trans1;
MOV.64 R4, RZ ?trans2;
MOV.64 R10, RZ ?trans2;
MOV.64 R8, RZ ?trans2;
UIADD3 UR8, UPT, UPT, UR5, 0x20, URZ ?trans1;
LOP3.LUT R2, R0, 0xfffffff8, RZ, 0xc0, !PT ?trans1;
UIADD3 UR9, UPT, UPT, UR6, 0x20, URZ ?trans1;
ULOP3.LUT UR7, UR7, 0x7fffffff, URZ, 0xc0, !UPT &req={0} ?WAIT12_END_GROUP;
LDS.128 R16, [UR8+-0x20] &wr=0x0 ?trans1;
MOV R3, UR7 ?trans1;
IADD.64 R4, R4, 0x8 ?trans2;
LDS.128 R12, [UR9+-0x20] &wr=0x1 ?trans1;
DADD R16, R16, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R12, R10 &req={1} &rd=0x1 &wr=0x2 ?trans2;
LDS.128 R8, [UR8+-0x10] &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R16, R18 &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R12, R14 &req={2} &rd=0x0 ?trans2;
LDS.128 R12, [UR9+-0x10] &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R16, R8 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R8, R10 &req={1} &rd=0x1 ?trans2;
LDS.128 R8, [UR8] &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R18, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R12, R14 &req={0} &rd=0x0 ?trans2;
LDS.128 R12, [UR9] &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R16, R8 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R8, R10 &req={1} &rd=0x1 ?trans2;
LDS.128 R8, [UR8+0x10] &req={1} &wr=0x1 ?trans1;
UIADD3 UR8, UPT, UPT, UR8, 0x40, URZ ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R18, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R12, R14 &req={0} &rd=0x0 ?trans2;
LDS.128 R12, [UR9+0x10] &req={0} &wr=0x0 ?trans1;
UIADD3 UR9, UPT, UPT, UR9, 0x40, URZ ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R16, R8 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R10 &req={1} &rd=0x1 ?trans2;
IADD.64 R10, R4, -R2 &req={1} ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P1, PT, R10, RZ, PT ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R18, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R12, R14 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P1 BRA 0x2b0 &req={1,0} ?trans5;
@!P0 BRA 0xda0 ?trans5;
ISETP.GE.U64.AND P0, PT, R6, 0x4, PT ?trans2;
MOV R3, RZ ?trans1;
LOP3.LUT R2, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P1, PT, R2, RZ, PT ?WAIT6_END_GROUP;
@!P0 BRA 0xb60 ?trans8;
LEA R6, R4.reuse, UR5, 0x3 ?trans2;
LEA R7, R4.reuse, UR6, 0x3 ?trans1;
IADD.64 R4, R4, 0x4 ?trans2;
LDS.128 R16, [R6] &wr=0x0 ?trans4;
LDS.128 R12, [R7] &wr=0x1 ?trans1;
DADD R16, R8, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R10, R12 &req={1} &rd=0x1 ?trans2;
LDS.128 R8, [R6+0x10] &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R16, R18 &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R16, R8 &req={1} &rd=0x0 ?trans2;
LDS.128 R16, [R7+0x10] &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R12, R14 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R12, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R10 &rd=0x1 &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R12, R18 &req={2,0} &rd=0x1 &wr=0x0 ?trans2;
@!P1 BRA 0xda0 ?trans5;
ISETP.NE.S64.AND P0, PT, R2, 0x1, PT ?trans2;
MOV R7, RZ ?trans1;
LOP3.LUT R6, R0, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U64.AND P1, PT, R6, 0x1, PT ?WAIT6_END_GROUP;
@!P0 BRA 0xd10 ?trans8;
LEA R12, R4.reuse, UR5, 0x3 &req={1} ?trans2;
LEA R16, R4.reuse, UR6, 0x3 ?trans1;
IADD.64 R4, R4, 0x2 ?WAIT3_END_GROUP;
LDS.128 R12, [R12] &wr=0x1 ?trans4;
LDS.128 R16, [R16] &wr=0x2 ?trans1;
DADD R8, R8, R12 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, R16 &req={2,0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R14 &req={1} &rd=0x2 &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, R18 &req={3,0} &rd=0x2 &wr=0x4 ?trans2;
@!P1 LEA R0, R4, UR5, 0x3 ?WAIT5_END_GROUP;
@!P1 LDS.64 R2, [R0] &wr=0x3 ?trans2;
@!P1 DADD R8, R8, R2 &req={3} &rd=0x3 &wr=0x1 ?trans2;
@!P1 LEA R2, R4, UR6, 0x3 &req={3} ?WAIT6_END_GROUP;
@!P1 LDS.64 R2, [R2] &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DADD R10, R10, R2 &req={4,3,1,0} &rd=0x3 &wr=0x4 ?trans2;
STS.128 [UR4], R8 &req={4,0} &rd=0x0 ?trans2;
LDC.64 R2, c[0x0][0x388] &req={3,1} &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x3 ?trans1;
STG.E.64 desc[UR10][R2.64], R8 &req={1} ?trans4;
STG.E.64 desc[UR10][R4.64], R10 &req={3} ?trans1;
EXIT ?trans5;
BRA 0xe00;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: force_aux0(long, double*, double*)
_Z10force_aux0lPdS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v4, 3, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[6:7]
global_load_b64 v[2:3], v4, s[0:1]
v_cmp_lt_i64_e64 s2, s[4:5], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b64 v4, v[0:1], v[2:3] offset1:8
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_3
s_mov_b32 s2, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s2
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_add_i32 s2, s2, 8
s_cmp_lg_u64 s[4:5], 0
ds_load_2addr_stride64_b64 v[4:7], v4 offset1:8
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], v[4:5], v[0:1]
v_add_f64 v[2:3], v[6:7], v[2:3]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
v_mov_b32_e32 v4, 0
s_clause 0x1
global_store_b64 v4, v[0:1], s[6:7]
global_store_b64 v4, v[2:3], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| force_aux0 | 4,068 | 608 | stackv2-00000-of-00015 |
// Demangled: maxPerRow(double*, int*, int)
Function : _Z9maxPerRowPdPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD R5, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={3} ?WAIT13_END_GROUP;
@P0 EXIT &req={2,0} ?trans5;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
IMAD.WIDE R2, R5, 0x8, R2 ?trans1;
S2R R6, SR_LANEID &wr=0x1 ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans4;
LDG.E.64 R2, desc[UR6][R2.64] &req={0} &wr=0x3 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans2;
UFLO.U32 UR4, UR4 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
ISETP.EQ.U32.AND P0, PT, R6, UR4, PT &req={1} ?trans1;
F2I.F64.TRUNC R0, R2 &req={3} &wr=0x0 ?trans2;
REDUX.MAX.S32 UR5, R0 &req={0} &wr=0x0 ?trans2;
MOV R7, UR5 &req={0} ?WAIT8_END_GROUP;
@P0 REDG.E.MAX.S32.STRONG.GPU desc[UR6][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: maxPerRow(double*, int*, int)
_Z9maxPerRowPdPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_brev_b32 s0, 1
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f64_e32 v0, v[0:1]
.LBB0_2:
s_ctz_i32_b32 s1, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s6, v0, s1
s_lshl_b32 s1, 1, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s5, s5, s1
s_max_i32 s0, s0, s6
s_cmp_lg_u32 s5, 0
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s5, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_5
s_lshl_b64 s[4:5], s[4:5], 2
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
s_add_u32 s0, s2, s4
s_addc_u32 s1, s3, s5
global_atomic_max_i32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| maxPerRow | 619 | 830 | stackv2-00000-of-00015 |
// Demangled: devmem_kernel()
Function : _Z13devmem_kernelv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_CTAID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x4][RZ] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans5;
LDC.64 R4, c[0x4][0x8] &wr=0x3 ?trans1;
IMAD R7, R7, UR6, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
FADD R9, R0, 1 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans2;
FADD R7, R9, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: devmem_kernel()
_Z13devmem_kernelv:
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, device_array0@rel32@lo+4
s_addc_u32 s1, s1, device_array0@rel32@hi+12
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, v0, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, device_array1@rel32@lo+4
s_addc_u32 s1, s1, device_array1@rel32@hi+12
v_add_co_u32 v0, vcc_lo, v0, s0
global_load_b32 v4, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, 1.0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v4, v5
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| devmem_kernel | 473 | 574 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R9, 0xfffff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LOP3.LUT R0, R9, 0x1, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans4;
ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x160 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, -R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x210;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 906 | 674 | stackv2-00000-of-00015 |
// Demangled: hello(char*)
Function : _Z5helloPc
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 4.291534423828125e-06 ?trans1;
MOV R4, 0x65 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 6.4373016357421875e-06 ?WAIT2_END_GROUP;
HFMA2 R6, -RZ, RZ, 0, 6.616115570068359375e-06 ?trans1;
STG.E.U8 desc[UR4][R2.64], R0 &req={0} ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1], R4 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2], R5 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x3], R5 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x5], RZ ?trans4;
STG.E.U8 desc[UR4][R2.64+0x4], R6 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: hello(char*)
_Z5helloPc:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0x6c6c6548
s_movk_i32 s3, 0x6f
s_mov_b64 s[4:5], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s6, s4, 3
s_lshr_b64 s[6:7], s[2:3], s6
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s0, s4
s_addc_u32 s9, s1, s5
v_mov_b32_e32 v1, s6
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 6
global_store_b8 v0, v1, s[8:9]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| hello | 446 | 313 | stackv2-00000-of-00015 |
// Demangled: void oob<128u>(int*, int)
Function : _Z3oobILj128EEvPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x388] &wr=0x2 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans2;
LEA R5, R0, R5, 0x7 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, UR4, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64+0x4], RZ &req={1} ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void oob<128u>(int*, int)
_ZL3oobILj128EEvPii:
s_load_b32 s2, s[0:1], 0x8
v_lshl_add_u32 v0, s15, 7, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off offset:4
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_oob_128u_ | 363 | 339 | stackv2-00000-of-00015 |
// Demangled: calculateNext(double*, double*, unsigned long long)
Function : _Z13calculateNextPdS_y
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans2;
IMAD R2, R2, 0x100, R3 &req={1} ?WAIT5_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
ISETP.GE.U64.AND P0, PT, R2, UR8, PT &req={2} ?WAIT14_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?WAIT12_END_GROUP;
@P0 BRA 0x170 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans2;
LDG.E.64 R4, desc[UR6][R2.64] &req={1,0} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R2.64+0x8] &wr=0x2 ?trans2;
DADD R4, R4, R6 &req={2} &rd=0x0 &wr=0x1 ?trans2;
LDC.64 R6, c[0x0][0x388] &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R4, 0.5 &req={1} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R6.64], R4 &req={0} ?trans1;
EXIT ?trans5;
UIADD3.64 UR4, UPT, UPT, UR8, -0x1, URZ ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P0, PT, R2, UR4, PT ?WAIT14_END_GROUP;
@P0 BRA 0x290 ?trans5;
LDCU.128 UR12, c[0x0][0x380] &wr=0x1 ?trans1;
SHF.L.U64.HI R3, R2.reuse, 0x3, R3 ?trans1;
IMAD.SHL.U32 R2, R2, 0x8, RZ ?WAIT5_END_GROUP;
IADD.64 R4, R2, UR12 &req={1} ?WAIT6_END_GROUP;
LDG.E.64 R6, desc[UR6][R4.64+-0x8] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R8, desc[UR6][R4.64] &wr=0x2 ?trans1;
IADD.64 R2, R2, UR14 ?trans2;
DADD R6, R6, R8 &req={2} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R6, R6, 0.5 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R2.64], R6 &req={0} ?trans1;
EXIT ?trans5;
LDCU.128 UR12, c[0x0][0x380] &wr=0x1 ?trans1;
SHF.L.U64.HI R7, R2.reuse, 0x3, R3 ?trans1;
IMAD.SHL.U32 R6, R2, 0x8, RZ ?WAIT5_END_GROUP;
IADD.64 R8, R6, UR12 &req={1} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR6][R8.64+-0x8] &req={0} &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR6][R8.64+0x8] &wr=0x2 ?trans1;
IADD.64 R6, R6, UR14 ?trans2;
DADD R2, R2, R4 &req={2} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, 0.5 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR6][R6.64], R2 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calculateNext(double*, double*, unsigned long long)
_Z13calculateNextPdS_y:
s_load_b64 s[4:5], s[0:1], 0x10
v_lshl_add_u32 v6, s15, 8, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[4:5], v[6:7]
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[6:7]
s_mov_b32 s6, exec_lo
v_cmpx_ne_u32_e32 0, v6
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_3
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[6:7]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_lshlrev_b32_e32 v6, 3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v4, -8
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_3:
s_and_not1_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_5
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, 8
s_addc_u32 s7, s1, 0
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0.5
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calculateNext | 1,316 | 966 | stackv2-00000-of-00015 |
// Demangled: initializeArray(double*, unsigned long long, int, unsigned long long const*, double const*)
Function : _Z15initializeArrayPdyiPKyPKd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x2 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans2;
IMAD R2, R2, 0x100, R3 &req={1} ?WAIT5_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
ISETP.GE.U64.AND P0, PT, R2, UR4, PT &req={2} ?WAIT14_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R0, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
LEA R4, P1, R2, UR6, 0x3 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R5, R2, UR7, R3, 0x3, P1 ?trans1;
ISETP.GE.AND P0, PT, R0, 0x1, PT &req={0} ?WAIT4_END_GROUP;
STG.E.64 desc[UR4][R4.64], RZ &req={2} &rd=0x0 ?trans9;
@!P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x398] &wr=0x0 ?trans8;
LDC.64 R10, c[0x0][0x398] &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x390] &wr=0x2 ?trans1;
LDG.E.64 R8, desc[UR4][R8.64] &req={0} &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x220 ?trans1;
MOV.64 R6, RZ ?WAIT2_END_GROUP;
ISETP.NE.S64.AND P0, PT, R8, R2, PT &req={3} ?WAIT14_END_GROUP;
@!P0 BRA 0x210 &req={2,1} ?trans5;
IADD3 R9, PT, PT, R6, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R9, UR8, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IMAD.WIDE.U32 R6, R9, 0x8, R10 ?WAIT6_END_GROUP;
LDG.E.64 R6, desc[UR4][R6.64] &wr=0x2 ?trans2;
ISETP.NE.S64.AND P0, PT, R6, R2, PT &req={2} ?trans2;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
MOV R6, R9 ?WAIT11_END_GROUP;
@P0 BRA 0x180 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR6, c[0x0][0x3a0] &wr=0x0 ?trans2;
LEA R2, P0, R6, UR6, 0x3 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R6, UR7, R7, 0x3, P0 ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &wr=0x2 ?trans4;
STG.E.64 desc[UR4][R4.64], R2 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x280;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: initializeArray(double*, unsigned long long, int, unsigned long long const*, double const*)
_Z15initializeArrayPdyiPKyPKd:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 8, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB1_8
s_load_b32 s8, s[0:1], 0x10
v_lshlrev_b64 v[2:3], 3, v[0:1]
v_mov_b32_e32 v4, 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v5, v4
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_store_b64 v[2:3], v[4:5], off
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB1_8
s_load_b128 s[0:3], s[0:1], 0x18
s_mov_b64 s[4:5], 0
.LBB1_3:
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[0:1], 0x0
s_or_b32 s11, s11, exec_lo
s_or_b32 s12, s12, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, s[6:7], v[0:1]
s_and_saveexec_b32 s13, vcc_lo
s_add_u32 s6, s4, 1
s_addc_u32 s7, s5, 0
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s8, s6
s_cselect_b32 s14, -1, 0
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s14, s14, exec_lo
s_and_not1_b32 s11, s11, exec_lo
s_or_b32 s12, s12, s14
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s13, exec_lo, s12
v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
s_or_b32 s9, s13, s9
s_and_not1_b32 s4, s10, exec_lo
s_and_b32 s5, s11, exec_lo
s_or_b32 s10, s4, s5
s_mov_b64 s[4:5], s[6:7]
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s9
s_and_saveexec_b32 s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB1_8
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[0:1], off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| initializeArray | 1,081 | 1,154 | stackv2-00000-of-00015 |
// Demangled: kernel(double*, double*, int)
Function : _Z6kernelPdS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x1f0 ?trans1;
PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x80 ?trans1;
S2R R6, SR_TID.Y &wr=0x2 ?trans5;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R2, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R9, c[0x0][0x364] &wr=0x2 ?trans1;
IMAD R5, R0, UR4, R5 &req={1} ?trans1;
LEA.HI R0, R2, R2, RZ, 0x1 &req={3} ?WAIT2_END_GROUP;
IADD3 R7, PT, PT, R2, -0x1, RZ ?trans2;
SHF.R.S32.HI R0, RZ, 0x1, R0 ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R5, R7, PT ?trans1;
IADD3 R4, PT, PT, R0, -0x1, RZ ?WAIT4_END_GROUP;
ISETP.GT.AND P0, PT, R5.reuse, RZ, !P0 ?trans1;
ISETP.EQ.AND P3, PT, R5, R4, PT ?trans1;
IMAD R6, R9, UR5, R6 &req={2} ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R6.reuse, R5, PT ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, P0 ?WAIT5_END_GROUP;
ISETP.LT.AND P0, PT, R6, R7, P0 ?WAIT7_END_GROUP;
@!P2 BRA P3, 0x1e0 &req={0} ?trans6;
ISETP.NE.AND P2, PT, R6, R4.reuse, PT ?trans1;
ISETP.NE.AND P3, PT, R5, R4, PT ?WAIT4_END_GROUP;
ISETP.EQ.AND P2, PT, R5, R0.reuse, !P2 ?trans1;
ISETP.EQ.AND P3, PT, R6, R0, !P3 ?WAIT5_END_GROUP;
PLOP3.LUT P2, PT, P2, P3, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@!P2 ISETP.NE.AND P3, PT, R6, R5, PT ?WAIT5_END_GROUP;
@!P2 ISETP.NE.OR P1, PT, R5, R0, P3 ?WAIT13_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
PLOP3.LUT P0, PT, P0, P1, PT, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R28, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R9, PT, PT, R5.reuse, -0x1, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R4, R5, R2.reuse, RZ ?trans2;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
IMAD R8, R9, R2.reuse, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
IADD3 R10, PT, PT, R4, R2, RZ ?trans2;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?WAIT2_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans2;
IADD3 R13, PT, PT, R6.reuse, R8, RZ ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans1;
IADD.64 R14, R6, R4 ?trans2;
IADD.64 R8, R8, R6 ?trans2;
IADD.64 R10, R6, R10 ?WAIT3_END_GROUP;
LEA R26, P0, R8, UR6, 0x3 &req={1} ?trans1;
IMAD.WIDE R28, R13, 0x8, R28 &req={0} ?trans1;
LEA R20, P1, R14, UR6, 0x3 ?trans1;
IADD.64 R12, R2, R2 ?WAIT3_END_GROUP;
LEA.HI.X R27, R8, UR7, R9, 0x3, P0 ?trans1;
IMAD.WIDE R8, R2, 0x8, R28 ?trans1;
LEA.HI.X R21, R14, UR7, R15, 0x3, P1 ?trans1;
LDG.E.64 R18, desc[UR4][R28.64] &req={2} &wr=0x2 ?trans1;
LEA R32, P1, R10, UR6, 0x3 ?trans2;
LEA R24, P2, R12, R28, 0x3 ?trans1;
LDG.E.64 R26, desc[UR4][R26.64+-0x8] &wr=0x2 ?trans1;
LEA.HI.X R33, R10, UR7, R11, 0x3, P1 ?trans2;
LEA.HI.X R25, R12, R29, R13, 0x3, P2 ?trans1;
LDG.E.64 R22, desc[UR4][R28.64+0x8] &rd=0x0 &wr=0x3 ?trans4;
LDG.E.64 R20, desc[UR4][R20.64+-0x8] &wr=0x4 ?trans4;
LDG.E.64 R16, desc[UR4][R8.64] &wr=0x5 ?trans4;
LDG.E.64 R14, desc[UR4][R8.64+0x8] &rd=0x1 &wr=0x3 ?trans4;
LDG.E.64 R12, desc[UR4][R32.64+-0x8] &wr=0x3 ?trans4;
LDG.E.64 R2, desc[UR4][R24.64] &wr=0x3 ?trans4;
LDG.E.64 R10, desc[UR4][R24.64+0x8] &wr=0x3 ?trans1;
MUFU.RCP64H R31, 9 &wr=0x0 ?trans1;
MOV.64 R34, 0x4022000000000000 ?WAIT2_END_GROUP;
HFMA2 R30, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT6_END_GROUP;
DFMA R28, R30, -R34, 1 &req={0} &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x9f0 ?trans1;
IADD3 R4, PT, PT, R6, R4, RZ ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R28, R28, R28, R28 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R28, R30, R28, R30 &req={0} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R28, -R34, 1 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R26, R18 &req={2} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R18, R22 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R18, R20 &req={4} &wr=0x5 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R18, R16 &req={5} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R16, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R14, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R2, R12, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R28, R8, R28 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R2, R10 &req={0} &wr=0x0 ?trans2;
FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R10, R8 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R2, -9, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R8, R12, R2 &req={0} &wr=0x0 ?trans2;
FFMA R0, RZ, 2.53125, R3 &req={0} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x9e0 ?trans5;
MOV R0, 0x9c0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xa30 ?trans5;
MOV R2, R12 ?trans1;
MOV R3, R13 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
IMAD.WIDE R4, R4, 0x8, R6 &req={0} ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R4.64], R2 ?trans1;
EXIT ?trans5;
MOV.64 R2, 0x3ff2000000000000 ?trans2;
FSETP.GEU.AND P1, PT, |R11|.reuse, 1.469367938527859385e-39, PT ?trans1;
LOP3.LUT R5, R11, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
HFMA2 R6, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
MUFU.RCP64H R7, R3 &wr=0x0 ?trans1;
MOV R17, 0x1ca00000 ?trans1;
HFMA2 R19, -RZ, RZ, 2.0625, 0 ?trans1;
ISETP.GE.U32.AND P0, PT, R5, 0x40200000, PT ?trans1;
MOV R16, R5 ?trans1;
BSSY.RECONVERGENT B1, 0x10f0 ?trans2;
IADD3 R20, PT, PT, R19, -0x1, RZ ?trans1;
SEL R17, R17, 0x63400000, !P0 ?trans1;
DFMA R8, R6, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R6, R8, R6 &req={0} &rd=0x0 ?trans2;
@!P1 LOP3.LUT R8, R17.reuse, 0x80000000, R11.reuse, 0xf8, !PT &req={0} ?trans2;
LOP3.LUT R7, R17, 0x800fffff, R11, 0xf8, !PT ?trans2;
@!P1 LOP3.LUT R9, R8, 0x100000, RZ, 0xfc, !PT ?trans1;
MOV R6, R10 ?trans1;
@!P1 MOV R8, RZ ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DFMA R6, R6, 2, -R8 &wr=0x0 ?trans2;
@!P1 LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?WAIT4_END_GROUP;
IADD3 R18, PT, PT, R16, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R18, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R12, -R2, 1 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R12, R14, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R14, R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R8, -R2, R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R14, R12, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xfe0 &req={1,0} ?trans5;
IADD3 R5, PT, PT, R5, -0x40200000, RZ ?WAIT5_END_GROUP;
VIMNMX.S32 R5, R5, -0x46a00000, !PT ?WAIT5_END_GROUP;
VIMNMX.S32 R10, R5, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R17, PT, PT, -R17, R10, RZ ?trans1;
MOV R10, RZ ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R17, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R12, R8, R10 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x10e0 ?trans5;
DFMA R2, R8, -R2, R6 &wr=0x0 ?trans1;
MOV R10, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R2, R3, 0x40220000, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
LOP3.LUT R5, R2, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R11, R5, R11, RZ, 0xfc, !PT ?WAIT4_END_GROUP;
@!P0 BRA 0x10e0 ?trans5;
IADD3 R3, PT, PT, -R17.reuse, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
IADD3 R17, PT, PT, -R17, -0x43300000, RZ ?WAIT5_END_GROUP;
DFMA R2, R12, -R2, R8 &wr=0x0 ?trans2;
FSETP.NEU.AND P0, PT, |R3|, R17, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL.RP R8, R8, R10 &wr=0x0 ?trans2;
LOP3.LUT R5, R9, R5, RZ, 0x3c, !PT &req={0} ?trans1;
FSEL R12, R8, R12, !P0 ?WAIT4_END_GROUP;
FSEL R13, R5, R13, !P0 ?trans1;
BRA 0x10e0 ?trans6;
DSETP.NAN.AND P0, PT, R10, R10, PT &wr=0x0 ?trans2;
@P0 BRA 0x10c0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R16, R19, PT ?trans1;
MOV.64 R12, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0x10e0 ?trans5;
ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ?trans1;
LOP3.LUT R10, R11, 0x40220000, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R19, RZ, !P0 ?trans1;
LOP3.LUT R13, R10, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R12, RZ ?trans1;
@P0 MOV R12, RZ ?WAIT3_END_GROUP;
@P0 MOV R13, R2 ?trans1;
BRA 0x10e0 ?trans6;
LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R12, R10 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R2, R0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 ?trans5;
BRA 0x1120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(double*, double*, int)
_Z6kernelPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_lshr_b32 s4, s5, 31
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s3, v[4:5]
s_add_i32 s2, s5, s4
s_mov_b32 s4, -1
s_ashr_i32 s6, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s6, -1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, s2, v0
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, -1
s_and_saveexec_b32 s7, s3
v_cmp_eq_u32_e64 s3, s6, v2
v_cmp_eq_u32_e64 s4, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 s6, vcc_lo, s3
s_and_b32 s2, s3, s2
s_and_b32 s3, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
s_or_not1_b32 s4, s2, exec_lo
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB0_5
s_add_i32 s3, s5, -1
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_cmp_le_i32_e64 s2, s3, v2
v_cmp_le_i32_e64 s3, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s2, s2, vcc_lo
s_or_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v1, -1, v2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v12, 31, v0
v_mul_lo_u32 v11, v2, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v1, s5
v_ashrrev_i32_e32 v2, 31, v11
v_add_nc_u32_e32 v7, v11, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v1
v_add_nc_u32_e32 v3, v1, v0
v_add_co_u32 v5, vcc_lo, v1, v0
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, v4, v12, vcc_lo
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v13, s5, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[17:18], 3, v[7:8]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_ashrrev_i32_e32 v14, 31, v13
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v0, v11
s_clause 0x1
global_load_b64 v[15:16], v[5:6], off offset:-8
global_load_b128 v[3:6], v[3:4], off
v_add_co_ci_u32_e32 v2, vcc_lo, v12, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v17
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v18, vcc_lo
global_load_b64 v[1:2], v[1:2], off offset:-8
v_add_co_u32 v11, vcc_lo, v13, v0
global_load_b128 v[7:10], v[7:8], off
v_add_co_ci_u32_e32 v12, vcc_lo, v14, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v11, vcc_lo, s0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
global_load_b64 v[19:20], v[11:12], off offset:-8
v_add_nc_u32_e32 v11, v13, v0
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v11, vcc_lo, s0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
global_load_b128 v[11:14], v[11:12], off
s_waitcnt vmcnt(4)
v_add_f64 v[3:4], v[15:16], v[3:4]
v_add_f64 v[3:4], v[3:4], v[5:6]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[3:4], v[1:2]
s_waitcnt vmcnt(2)
v_add_f64 v[0:1], v[0:1], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[9:10]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[0:1], v[19:20]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[11:12]
v_add_f64 v[0:1], v[0:1], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[2:3], null, 0x40220000, 0x40220000, v[0:1]
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_div_scale_f64 v[6:7], vcc_lo, v[0:1], 0x40220000, v[0:1]
v_mul_f64 v[8:9], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[2:3], 0x40220000, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v17
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v18, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 5,676 | 3,295 | stackv2-00000-of-00015 |
// Demangled: calc_w_const(unsigned int*, unsigned int*, unsigned int)
Function : _Z12calc_w_constPjS_j
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LOP3.LUT R0, R7, 0x1, RZ, 0xc0, !PT ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x150 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, RZ ?WAIT7_END_GROUP;
MOV R4, R2 ?trans1;
ISETP.GE.U32.AND P0, PT, R0, 0xa, PT ?trans1;
IADD.64 R2, R2, 0x8 ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R0, 0x2, RZ ?trans1;
LDC R4, c[0x3][R4] &wr=0x1 ?trans2;
IADD3 R9, PT, PT, R4, R9, RZ &req={1} ?WAIT6_END_GROUP;
@!P0 BRA 0xd0 ?trans5;
BSYNC.RECONVERGENT B0 &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
IMAD R7, R9, R4, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x1e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calc_w_const(unsigned int*, unsigned int*, unsigned int)
_Z12calc_w_constPjS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_lo_u16 v2, s15, s2
v_and_b32_e32 v0, 1, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_or_b32_e32 v7, -2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 1, v2
s_xor_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v0, 0, 1, s0
v_mov_b32_e32 v2, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, fib_const@rel32@lo+4
s_addc_u32 s1, s1, fib_const@rel32@hi+12
v_lshlrev_b32_e32 v5, 2, v0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v5, s0, v5, s0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
v_add_co_ci_u32_e64 v6, null, 0, s1, s0
s_mov_b32 s1, 0
.LBB0_2:
global_load_b32 v8, v[5:6], off
v_add_nc_u32_e32 v7, 2, v7
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 9, v7
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v8
global_store_b32 v[0:1], v2, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calc_w_const | 770 | 1,075 | stackv2-00000-of-00015 |
// Demangled: calc_w_gmem(unsigned int*, unsigned int*, unsigned int)
Function : _Z11calc_w_gmemPjS_j
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LOP3.LUT R11, R7.reuse, 0x1, RZ, 0xc0, !PT ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x190 ?trans4;
LDC.64 R4, c[0x4][RZ] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ &req={1} &rd=0x0 ?trans1;
IMAD.WIDE.U32 R4, R11, 0x4, R4 &req={2} ?WAIT7_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &req={1} &rd=0x1 &wr=0x2 ?trans1;
ISETP.GE.U32.AND P0, PT, R11.reuse, 0xa, PT ?trans1;
IADD3 R11, PT, PT, R11, 0x2, RZ ?trans1;
IADD.64 R4, R4, 0x8 &req={1} ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R0, R9, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x1 ?trans3;
@!P0 BRA 0x110 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x2 ?trans2;
LEA R4, P0, R7, UR6, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R5, R7, UR7, RZ, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
IMAD R9, R9, R4, RZ &req={2,1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calc_w_gmem(unsigned int*, unsigned int*, unsigned int)
_Z11calc_w_gmemPjS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_4
v_mul_lo_u16 v2, s15, s2
v_and_b32_e32 v0, 1, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL8fib_gmem@gotpcrel32@lo+4
s_addc_u32 s3, s3, _ZL8fib_gmem@gotpcrel32@hi+12
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v0
v_or_b32_e32 v7, -2, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 1, v2
s_xor_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
v_add_co_ci_u32_e64 v6, null, s3, 0, s0
global_store_b32 v[0:1], v2, off
.LBB1_2:
global_load_b32 v8, v[5:6], off
v_add_nc_u32_e32 v7, 2, v7
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 9, v7
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v8
global_store_b32 v[0:1], v2, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calc_w_gmem | 898 | 1,127 | stackv2-00000-of-00015 |
// Demangled: calc_w_shared(unsigned int*, unsigned int*, unsigned int const*, unsigned int)
Function : _Z13calc_w_sharedPjS_PKjj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R9, 0x1, PT ?trans1;
BSSY.RECONVERGENT B0, 0x3d0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R5, R9, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R5], R2 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x3c0 &req={0} ?trans5;
LDC R11, c[0x0][0x360] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R9, 0x2, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, R11, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x3c0 ?trans5;
LDS R4, [R5] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R11, -0x3, -R9 &req={1} ?trans1;
BSSY.RECONVERGENT B1, 0x280 ?trans3;
LEA.HI R3, R2, 0x1, RZ, 0x1f ?WAIT4_END_GROUP;
LOP3.LUT P0, R3, R3, 0x3, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x270 &req={0} ?trans5;
BSSY.RECONVERGENT B2, 0x260 ?trans1;
IADD3 R3, PT, PT, -R3, RZ, RZ ?trans2;
IADD3 R0, PT, PT, R5, 0x8, RZ ?trans1;
MOV R6, R9 ?WAIT7_END_GROUP;
LDS R7, [R0] &req={0} &rd=0x0 &wr=0x1 ?trans1;
IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
IADD3 R6, PT, PT, R6, 0x2, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ &req={0} ?trans2;
IADD3 R4, PT, PT, R7, R4, RZ &req={2,1} ?WAIT5_END_GROUP;
STS [R5], R4 &rd=0x0 ?trans5;
@P0 BRA 0x1d0 ?trans5;
BSYNC.RECONVERGENT B2 ?trans5;
IADD3 R0, PT, PT, R6, 0x2, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
ISETP.GE.U32.AND P0, PT, R2, 0x6, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x3c0 ?trans5;
LEA R2, R0, UR4, 0x2 ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R2, 0x10, RZ ?WAIT7_END_GROUP;
LDS R3, [R2+-0x10] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, R11, PT ?trans1;
IADD3 R6, PT, PT, R3, R4, RZ &req={2,1} ?WAIT5_END_GROUP;
STS [R5], R6 ?trans4;
LDS R3, [R2+-0x8] &wr=0x1 ?trans2;
IADD3 R8, PT, PT, R6, R3, RZ &req={1} ?WAIT5_END_GROUP;
STS [R5], R8 ?trans4;
LDS R3, [R2] &wr=0x1 ?trans2;
IADD3 R10, PT, PT, R8, R3, RZ &req={1} ?WAIT5_END_GROUP;
STS [R5], R10 ?trans4;
LDS R3, [R2+0x8] &rd=0x1 &wr=0x2 ?trans2;
IADD3 R2, PT, PT, R2, 0x20, RZ &req={1} ?trans2;
IADD3 R4, PT, PT, R10, R3, RZ &req={3,2,0} ?WAIT5_END_GROUP;
STS [R5], R4 &rd=0x3 ?trans1;
@!P0 BRA 0x2c0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR5, SR_CTAID.X &wr=0x4 ?trans1;
LDCU UR8, c[0x0][0x398] &wr=0x5 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x4 ?trans2;
IMAD R7, R0, UR5, R9 &req={4} ?WAIT6_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R7, UR8, PT &req={5} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &req={1} &wr=0x1 ?trans1;
IMAD.SHL.U32 R0, R7, 0x4, RZ ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &req={3,2,0} &wr=0x0 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans1;
LOP3.LUT R0, R0, 0x4, RZ, 0xc0, !PT ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
LDS R9, [R0+UR4] &wr=0x2 ?trans2;
IMAD R9, R2, R9, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x4f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calc_w_shared(unsigned int*, unsigned int*, unsigned int const*, unsigned int)
_Z13calc_w_sharedPjS_PKjj:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v3, s[2:3]
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_u32_e32 1, v0
s_xor_b32 s4, exec_lo, s4
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_or_saveexec_b32 s4, s4
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB2_7
s_load_b32 s5, s[0:1], 0x2c
v_or_b32_e32 v1, 2, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB2_6
ds_load_b32 v2, v3
v_lshl_add_u32 v4, v0, 2, 8
s_mov_b32 s7, 0
.LBB2_5:
ds_load_b32 v5, v4
v_add_nc_u32_e32 v1, 2, v1
v_add_nc_u32_e32 v4, 8, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_or_b32 s7, vcc_lo, s7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v2, v5
ds_store_b32 v3, v2
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB2_5
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s6
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_u16 v3, v[1:2], off offset:12
s_load_b32 s2, s[0:1], 0x18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, v3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_9
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calc_w_shared | 1,931 | 1,172 | stackv2-00000-of-00015 |
// Demangled: VectorAdd(int*, int*, int*, int)
Function : _Z9VectorAddPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R9, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?WAIT4_END_GROUP;
IMAD R9, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: VectorAdd(int*, int*, int*, int)
_Z9VectorAddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| VectorAdd | 507 | 271 | stackv2-00000-of-00015 |
// Demangled: fast_add(float*, float*, float*)
Function : _Z8fast_addPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: fast_add(float*, float*, float*)
_Z8fast_addPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| fast_add | 420 | 192 | stackv2-00000-of-00015 |
// Demangled: kernel1(int*, int*, int*, int*, int*, int*, int*, int*)
Function : _Z7kernel1PiS_S_S_S_S_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans2;
IMAD R7, R11, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R7, 0x3, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x3b0] &wr=0x2 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R11, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT &req={3} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R9, R0, !P0 &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR6, c[0x0][0x398] &wr=0x0 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R7 ?trans1;
STG.E desc[UR4][R4.64], R9 ?trans1;
LEA R2, P0, R7, UR6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R7, UR7, R0, 0x2, P0 ?trans2;
LDC.64 R6, c[0x0][0x3b8] &wr=0x0 ?trans4;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans1;
LEA R6, P0, R11, R6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R7, R11, R7, RZ, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x1c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel1(int*, int*, int*, int*, int*, int*, int*, int*)
_Z7kernel1PiS_S_S_S_S_S_S_:
s_load_b32 s2, s[0:1], 0x4c
s_mov_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s8, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 4, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[0:3], s[0:1], 0x30
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_lshl_b64 s[6:7], s[8:9], 2
s_add_u32 s8, s0, s6
global_load_b32 v2, v[2:3], off
s_addc_u32 s9, s1, s7
s_load_b32 s0, s[8:9], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v2
v_cmp_ne_u32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_3
v_add_co_u32 v0, vcc_lo, s4, v0
v_mov_b32_e32 v3, 0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_add_u32 s0, s2, s6
s_addc_u32 s1, s3, s7
global_store_b32 v3, v2, s[8:9]
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
global_store_b32 v3, v0, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel1 | 792 | 794 | stackv2-00000-of-00015 |
// Demangled: kernel2(int*, int*, int*)
Function : _Z7kernel2PiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans2;
LDG.E R0, desc[UR8][R2.64] &req={1} &wr=0x2 ?trans1;
S2R R11, SR_TID.X &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R11, R0, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR8][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R11, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR8][R4.64] &wr=0x3 ?trans1;
S2UR UR6, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
UIADD3 UR5, UPT, UPT, UR4, 0x80, URZ ?trans1;
ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={0} ?trans2;
ULEA UR5, UR6, UR5, 0x18 ?WAIT4_END_GROUP;
LEA R7, R11.reuse, UR4, 0x2 ?trans2;
LEA R9, R11, UR5, 0x2 ?WAIT3_END_GROUP;
STS [R7], R2 &req={2} &rd=0x0 ?trans4;
STS [R9], R4 &req={3} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x2b0 ?trans5;
MOV R5, R0 ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
BSSY.RECONVERGENT B0, 0x280 ?trans4;
ISETP.GE.U32.AND P0, PT, R11, R0, PT ?WAIT13_END_GROUP;
@P0 BRA 0x270 &req={1} ?trans5;
IMAD R2, R0, 0x4, R7 &req={0} ?trans1;
LDS R3, [R7] &wr=0x0 ?trans5;
LDS R2, [R2] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT &req={0} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R2, R3, !P0 &req={1} ?WAIT13_END_GROUP;
@!P0 IMAD R3, R0, 0x4, R9 ?trans1;
@!P0 STS [R7], R2 ?trans4;
@!P0 LDS R4, [R3] &wr=0x0 ?trans4;
@!P0 STS [R9], R4 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x3, PT ?WAIT13_END_GROUP;
@P0 BRA 0x190 ?trans5;
ISETP.NE.AND P0, PT, R11, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x390] &req={1} &wr=0x1 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?WAIT9_END_GROUP;
LDS R7, [UR4] &wr=0x0 ?trans4;
LDS R9, [UR4+0x80] &wr=0x1 ?trans4;
STG.E desc[UR8][R2.64], R7 &req={0} ?trans4;
STG.E desc[UR8][R4.64], R9 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x370;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel2(int*, int*, int*)
_Z7kernel2PiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB1_9
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s4, 2
global_load_b32 v2, v1, s[6:7]
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[2:3]
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v1, v3, v2 offset1:32
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
v_add_nc_u32_e32 v2, 0x80, v1
.LBB1_3:
s_mov_b32 s1, s4
s_lshr_b32 s4, s4, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_6
v_lshl_add_u32 v3, s4, 2, v2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v4
v_cmp_ne_u32_e64 s0, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_6
v_lshl_add_u32 v4, s4, 2, v1
ds_load_b32 v4, v4
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v1, v4
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s1, 3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_3
.LBB1_7:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v2, 0
ds_load_2addr_b32 v[0:1], v2 offset1:32
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v1, s[6:7]
global_store_b32 v2, v0, s[2:3]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel2 | 1,332 | 821 | stackv2-00000-of-00015 |
// Demangled: kernel3(int*, int*, int*, int*, int*, int*)
Function : _Z7kernel3PiS_S_S_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R8, c[0x0][0x3a0] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
LDG.E R0, desc[UR4][R8.64] &req={1} &wr=0x2 ?trans7;
LDC.64 R2, c[0x0][0x3a8] &wr=0x1 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE R10, R0, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R11, desc[UR4][R10.64+0x14] &rd=0x1 &wr=0x5 ?trans1;
ISETP.GE.AND P0, PT, R0, 0x1, PT ?trans1;
HFMA2 R6, -RZ, RZ, 0, 0 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R2 &req={3} ?WAIT11_END_GROUP;
@!P0 BRA 0x5e0 &req={1,0} ?trans5;
ISETP.GE.U32.AND P1, PT, R0.reuse, 0x10, PT ?trans1;
LOP3.LUT R28, R0, 0xf, RZ, 0xc0, !PT ?trans1;
MOV R3, RZ ?trans1;
MOV R6, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R28, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x340 ?trans6;
LOP3.LUT R10, R0, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
IADD.64 R8, R4, 0x28 ?trans2;
MOV R3, RZ ?trans1;
IADD3 R10, PT, PT, -R10, RZ, RZ ?WAIT7_END_GROUP;
LDG.E R13, desc[UR4][R8.64+-0x14] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R8.64+-0x10] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+-0xc] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R8.64+-0x8] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0x4] &wr=0x4 ?trans4;
LDG.E R16, desc[UR4][R8.64] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R8.64+0x4] &wr=0x4 ?trans4;
LDG.E R18, desc[UR4][R8.64+0x8] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R8.64+0xc] &wr=0x4 ?trans4;
LDG.E R20, desc[UR4][R8.64+0x10] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R8.64+0x14] &wr=0x4 ?trans4;
LDG.E R22, desc[UR4][R8.64+0x18] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R8.64+0x1c] &wr=0x4 ?trans4;
LDG.E R24, desc[UR4][R8.64+0x20] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R8.64+0x24] &wr=0x4 ?trans4;
LDG.E R26, desc[UR4][R8.64+0x28] &rd=0x0 &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R10, 0x10, RZ ?WAIT2_END_GROUP;
IADD3 R3, PT, PT, R3, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R10, RZ, PT ?trans1;
IADD.64 R8, R8, 0x40 &req={0} ?WAIT3_END_GROUP;
IADD3 R12, PT, PT, R12, R13, R6 &req={2} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R14, R15, R12 &req={3} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R16, R17, R12 &req={4} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R18, R19, R12 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R20, R21, R12 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R22, R23, R12 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R24, R25, R12 ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R26, R27, R12 ?trans1;
@P1 BRA 0x170 ?trans6;
@!P0 BRA 0x5e0 ?trans5;
ISETP.GE.U32.AND P0, PT, R28, 0x8, PT ?trans1;
LOP3.LUT R18, R0, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R18, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x470 ?trans6;
IMAD.WIDE.U32 R8, R3, 0x4, R4 ?WAIT5_END_GROUP;
LDG.E R13, desc[UR4][R8.64+0x14] &wr=0x2 ?trans4;
LDG.E R10, desc[UR4][R8.64+0x18] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x1c] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x20] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R8.64+0x24] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R8.64+0x28] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R8.64+0x2c] &wr=0x4 ?trans4;
LDG.E R16, desc[UR4][R8.64+0x30] &wr=0x4 ?trans1;
IADD3 R3, PT, PT, R3, 0x8, RZ ?WAIT2_END_GROUP;
IADD3 R10, PT, PT, R10, R13, R6 &req={2} ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R12, R15, R10 &req={3} ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R14, R17, R10 &req={4} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R16, R19, R10 ?WAIT7_END_GROUP;
@!P1 BRA 0x5e0 ?trans5;
ISETP.GE.U32.AND P0, PT, R18, 0x4, PT ?trans1;
LOP3.LUT R10, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R10, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x540 ?trans6;
IMAD.WIDE.U32 R8, R3, 0x4, R4 ?WAIT5_END_GROUP;
LDG.E R13, desc[UR4][R8.64+0x14] &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x18] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x1c] &wr=0x3 ?trans4;
LDG.E R14, desc[UR4][R8.64+0x20] &wr=0x3 ?trans1;
IADD3 R3, PT, PT, R3, 0x4, RZ ?WAIT2_END_GROUP;
IADD3 R6, PT, PT, R12, R13, R6 &req={2} ?WAIT4_END_GROUP;
IADD3 R6, PT, PT, R14, R15, R6 &req={3} ?WAIT7_END_GROUP;
@!P1 BRA 0x5e0 ?trans5;
IMAD.WIDE.U32 R4, R3, 0x4, R4 ?trans1;
IADD3 R10, PT, PT, -R10, RZ, RZ ?WAIT4_END_GROUP;
IADD.64 R4, R4, 0x14 ?WAIT8_END_GROUP;
LDG.E R3, desc[UR4][R4.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R10, RZ, PT ?trans1;
IADD.64 R4, R4, 0x4 &req={0} ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R3, R6, RZ &req={2} ?WAIT9_END_GROUP;
@P0 BRA 0x580 ?trans5;
S2R R3, SR_TID.X &wr=0x0 ?trans1;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans8;
LDC R4, c[0x0][0x360] &wr=0x0 ?trans2;
IMAD R3, R4, UR6, R3 &req={0} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, R3, PT ?WAIT5_END_GROUP;
ISETP.GT.OR P0, PT, R3, 0x4, !P0 ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R11, 0x1, P0 &req={5} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
IADD3 R4, PT, PT, R11, R6, RZ ?trans2;
IADD3 R5, PT, PT, R6, 0x1, RZ ?WAIT5_END_GROUP;
VIMNMX.S32 R19, R4, R5, !PT ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, R19, -R6, RZ ?WAIT4_END_GROUP;
LOP3.LUT P0, R18, R5, 0x3, RZ, 0xc0, !PT ?trans1;
MOV R5, R6 ?WAIT12_END_GROUP;
@!P0 BRA 0x850 ?trans5;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, -R18, RZ, RZ ?trans1;
MOV R5, R6 ?WAIT6_END_GROUP;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
LEA R10, P0, R2, R10, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R11, R2, R11, R7, 0x2, P0 ?WAIT9_END_GROUP;
IMAD.WIDE R12, R5, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
LDG.E R12, desc[UR4][R12.64] &wr=0x2 ?trans1;
IADD3 R18, PT, PT, R18, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x830 ?trans4;
ISETP.NE.AND P0, PT, R18, RZ, PT ?trans1;
ISETP.NE.AND P1, PT, R12, R3, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x820 ?trans5;
LDC.64 R12, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD.WIDE R16, R5, 0x4, R10 ?trans1;
LDG.E R7, desc[UR4][R12.64] &req={0} &wr=0x2 ?trans5;
LDG.E R16, desc[UR4][R16.64] &wr=0x2 ?trans2;
ISETP.GE.AND P1, PT, R16, R7, PT &req={2} ?WAIT13_END_GROUP;
@!P1 LDC.64 R14, c[0x0][0x390] &wr=0x0 ?trans1;
@!P1 STG.E desc[UR4][R12.64], R16 &rd=0x1 ?trans4;
@!P1 STG.E desc[UR4][R14.64], R0 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
@P0 BRA 0x730 ?trans6;
IADD3 R6, PT, PT, -R19, R6, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R6, -0x4, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
IADD.64 R6, R6, 0x8 &req={0} ?WAIT6_END_GROUP;
IMAD.WIDE R8, R2, 0x4, R6 ?WAIT7_END_GROUP;
IMAD.WIDE R10, R5, 0x4, R6 &req={4} ?WAIT5_END_GROUP;
LDG.E R2, desc[UR4][R10.64+-0x8] &req={2} &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x990 ?trans1;
IMAD.WIDE R12, R5, 0x4, R8 &req={1} ?trans1;
ISETP.NE.AND P0, PT, R2, R3, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x980 &req={3} ?trans5;
LDC.64 R14, c[0x0][0x398] &wr=0x0 ?trans1;
LDG.E R19, desc[UR4][R12.64+-0x8] &wr=0x2 ?trans4;
LDG.E R2, desc[UR4][R14.64] &req={0} &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R19, R2, PT &req={2} ?WAIT13_END_GROUP;
@!P0 LDC.64 R16, c[0x0][0x390] &wr=0x0 ?trans1;
@!P0 STG.E desc[UR4][R14.64], R19 &rd=0x1 ?trans4;
@!P0 STG.E desc[UR4][R16.64], R0 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDG.E R2, desc[UR4][R10.64+-0x4] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0xa50 ?trans1;
ISETP.NE.AND P0, PT, R2, R3, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0xa40 ?trans5;
LDC.64 R14, c[0x0][0x398] &req={1} &wr=0x0 ?trans1;
LDG.E R19, desc[UR4][R12.64+-0x4] &wr=0x2 ?trans4;
LDG.E R2, desc[UR4][R14.64] &req={0} &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R19, R2, PT &req={2} ?WAIT13_END_GROUP;
@!P0 LDC.64 R16, c[0x0][0x390] &wr=0x0 ?trans1;
@!P0 STG.E desc[UR4][R14.64], R19 &rd=0x2 ?trans4;
@!P0 STG.E desc[UR4][R16.64], R0 &req={0} &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDG.E R2, desc[UR4][R10.64] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0xb10 ?trans1;
ISETP.NE.AND P0, PT, R2, R3, PT &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0xb00 ?trans5;
LDC.64 R14, c[0x0][0x398] &req={2,1} &wr=0x0 ?trans1;
LDG.E R19, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E R2, desc[UR4][R14.64] &req={0} &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R19, R2, PT &req={2} ?WAIT13_END_GROUP;
@!P0 LDC.64 R16, c[0x0][0x390] &wr=0x0 ?trans1;
@!P0 STG.E desc[UR4][R14.64], R19 &rd=0x3 ?trans4;
@!P0 STG.E desc[UR4][R16.64], R0 &req={0} &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
LDG.E R10, desc[UR4][R10.64+0x4] &wr=0x4 ?trans1;
IADD3 R5, PT, PT, R5, 0x4, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xbf0 ?trans4;
ISETP.GE.AND P0, PT, R5, R4, PT ?trans1;
ISETP.NE.AND P1, PT, R10, R3, PT &req={4} ?WAIT13_END_GROUP;
@P1 BRA 0xbe0 ?trans5;
LDC.64 R10, c[0x0][0x398] &wr=0x0 ?trans1;
LDG.E R13, desc[UR4][R12.64+0x4] &wr=0x4 ?trans4;
LDG.E R2, desc[UR4][R10.64] &req={0} &wr=0x4 ?trans2;
ISETP.GE.AND P1, PT, R13, R2, PT &req={4} ?WAIT13_END_GROUP;
@!P1 LDC.64 R14, c[0x0][0x390] &req={3,2,1} &wr=0x0 ?trans1;
@!P1 STG.E desc[UR4][R10.64], R13 &rd=0x4 ?trans4;
@!P1 STG.E desc[UR4][R14.64], R0 &req={0} &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@!P0 BRA 0x8b0 ?trans5;
EXIT ?trans5;
BRA 0xc10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel3(int*, int*, int*, int*, int*, int*)
_Z7kernel3PiS_S_S_S_S_:
s_load_b128 s[16:19], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[16:17], 0x0
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i64_e64 s14, s[2:3], 1
s_lshl_b64 s[12:13], s[2:3], 2
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB2_3
s_add_u32 s16, s4, 20
s_addc_u32 s17, s5, 0
s_mov_b32 s4, 0
s_mov_b32 s3, s2
.LBB2_2:
s_load_b32 s5, s[16:17], 0x0
s_add_i32 s3, s3, -1
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_add_u32 s16, s16, 4
s_addc_u32 s17, s17, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
s_mov_b32 s4, 0
.LBB2_4:
s_load_b32 s14, s[18:19], 0x0
s_load_b32 s3, s[12:13], 0x14
s_load_b32 s0, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, 5, v1
v_cmp_ne_u32_e64 s0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_cmp_gt_i32 s3, 0
s_cselect_b32 s1, -1, 0
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_10
s_ashr_i32 s5, s4, 31
s_ashr_i32 s15, s14, 31
s_lshl_b64 s[12:13], s[4:5], 2
v_mov_b32_e32 v0, 0
s_add_i32 s3, s4, s3
s_lshl_b64 s[0:1], s[14:15], 2
s_add_u32 s6, s6, s12
s_addc_u32 s7, s7, s13
.LBB2_6:
global_load_b32 v2, v0, s[6:7]
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v2, v1
s_cbranch_execz .LBB2_9
s_add_u32 s12, s6, s0
s_addc_u32 s13, s7, s1
s_clause 0x1
global_load_b32 v2, v0, s[12:13]
global_load_b32 v3, v0, s[10:11]
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v2, v3
s_cbranch_vccnz .LBB2_9
v_mov_b32_e32 v3, s2
s_clause 0x1
global_store_b32 v0, v2, s[10:11]
global_store_b32 v0, v3, s[8:9]
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s4, s4, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_lt_i32 s4, s3
s_cbranch_scc1 .LBB2_6
.LBB2_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel3 | 5,331 | 1,312 | stackv2-00000-of-00015 |
// Demangled: getMin(float*, int*, int, float*, int*)
Function : _Z6getMinPfPiiS_S0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans6;
LDC R18, c[0x0][0x360] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x4e0 ?trans1;
S2R R3, SR_TID.X &wr=0x4 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x0 ?trans1;
MOV R11, 0x7f800000 ?trans1;
IMAD.SHL.U32 R2, R0, 0x400, RZ &req={1} ?WAIT5_END_GROUP;
LOP3.LUT R2, R2, R3, RZ, 0xfc, !PT &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR4, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x4d0 &req={3,0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R19, PT, PT, R2.reuse, 0x80, RZ ?trans2;
IADD3 R7, PT, PT, R2.reuse, 0x100, RZ ?trans1;
MOV R6, 0x7f800000 ?trans2;
ISETP.GE.U32.AND P0, PT, R19, UR4, PT ?trans2;
ISETP.GE.U32.AND P1, PT, R7, UR4, PT ?trans1;
IADD3 R16, PT, PT, R2.reuse, 0x180, RZ ?trans1;
MOV R8, 0x7f800000 ?trans1;
IMAD.WIDE.U32 R4, R2, 0x4, R4 &req={0} ?WAIT8_END_GROUP;
@!P0 LDG.E R6, desc[UR8][R4.64+0x200] &wr=0x2 ?trans4;
LDG.E R17, desc[UR8][R4.64] &wr=0x3 ?trans1;
ISETP.GE.U32.AND P0, PT, R16, UR4, PT ?trans1;
IADD3 R10, PT, PT, R2, 0x200, RZ ?trans2;
@!P1 LDG.E R8, desc[UR8][R4.64+0x400] &wr=0x4 ?trans1;
MOV R9, 0x7f800000 ?trans2;
ISETP.GE.U32.AND P1, PT, R10, UR4, PT ?trans1;
IADD3 R21, PT, PT, R2, 0x280, RZ ?trans1;
MOV R11, 0x7f800000 ?WAIT5_END_GROUP;
@!P0 LDG.E R9, desc[UR8][R4.64+0x600] &wr=0x5 ?trans1;
ISETP.GE.U32.AND P0, PT, R21, UR4, PT ?trans1;
IADD3 R13, PT, PT, R2, 0x300, RZ ?WAIT4_END_GROUP;
@!P1 LDG.E R11, desc[UR8][R4.64+0x800] &wr=0x5 ?trans1;
MOV R12, 0x7f800000 ?trans1;
ISETP.GE.U32.AND P1, PT, R13, UR4, PT ?trans1;
MOV R14, 0x7f800000 ?WAIT5_END_GROUP;
@!P0 LDG.E R12, desc[UR8][R4.64+0xa00] &wr=0x5 ?trans1;
IADD3 R20, PT, PT, R2, 0x380, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R20, UR4, PT ?trans1;
@!P1 LDG.E R14, desc[UR8][R4.64+0xc00] &wr=0x5 ?trans1;
MOV R15, 0x7f800000 ?WAIT11_END_GROUP;
@!P0 LDG.E R15, desc[UR8][R4.64+0xe00] &wr=0x5 ?trans1;
FSETP.NEU.AND P0, PT, R6, RZ, PT &req={2} ?trans1;
FSETP.NEU.AND P1, PT, R17, RZ, PT &req={3} ?WAIT4_END_GROUP;
FSEL R6, R6, +INF , P0 ?trans1;
FSETP.NEU.AND P0, PT, R8, RZ, PT &req={4} ?trans1;
FSEL R17, R17, +INF , P1 ?WAIT4_END_GROUP;
FSEL R8, R8, +INF , P0 ?trans1;
FSETP.GEU.AND P1, PT, R6, R17, PT ?trans1;
FSETP.NEU.AND P2, PT, R9, RZ, PT &req={5} ?WAIT4_END_GROUP;
FSEL R17, R6, R17, !P1 ?trans1;
FSEL R9, R9, +INF , P2 ?WAIT4_END_GROUP;
FSETP.GEU.AND P0, PT, R8, R17, PT ?trans1;
FSETP.NEU.AND P3, PT, R11, RZ, PT ?WAIT4_END_GROUP;
FSEL R8, R8, R17, !P0 ?trans1;
FSEL R11, R11, +INF , P3 ?trans1;
FSETP.NEU.AND P4, PT, R12, RZ, PT ?WAIT3_END_GROUP;
FSETP.GEU.AND P2, PT, R9, R8, PT ?trans2;
FSEL R12, R12, +INF , P4 ?trans1;
@P0 SEL R7, R19, R2, !P1 ?trans2;
FSEL R8, R9, R8, !P2 ?trans1;
FSETP.NEU.AND P5, PT, R14, RZ, PT ?WAIT4_END_GROUP;
FSETP.GEU.AND P3, PT, R11, R8, PT ?trans1;
FSEL R14, R14, +INF , P5 ?WAIT4_END_GROUP;
FSEL R11, R11, R8, !P3 ?trans1;
FSETP.NEU.AND P5, PT, R15, RZ, PT ?WAIT4_END_GROUP;
FSETP.GEU.AND P4, PT, R12, R11, PT ?WAIT3_END_GROUP;
@P3 SEL R10, R16, R7, !P2 ?trans2;
FSEL R5, R12, R11, !P4 ?trans1;
FSEL R11, R15, +INF , P5 ?WAIT4_END_GROUP;
FSETP.GEU.AND P6, PT, R14, R5, PT ?WAIT5_END_GROUP;
FSEL R14, R14, R5, !P6 ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R11, R14, PT ?WAIT3_END_GROUP;
@P6 SEL R13, R21, R10, !P4 ?trans2;
FSEL R11, R11, R14, !P0 ?WAIT3_END_GROUP;
SEL R2, R20, R13, !P0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR6, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R3.reuse, 0x1ff, PT ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x200, URZ ?trans1;
ISETP.GT.U32.AND P1, PT, R3.reuse, 0xff, PT ?trans1;
ISETP.GT.U32.AND P2, PT, R3.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P3, PT, R3.reuse, 0x3f, PT ?trans1;
ISETP.LT.U32.OR P0, PT, R18.reuse, 0x400, P0 ?trans1;
BSSY.RECONVERGENT B0, 0x6b0 ?trans1;
ISETP.LT.U32.OR P1, PT, R18.reuse, 0x200, P1 ?trans1;
ISETP.LT.U32.OR P2, PT, R18.reuse, 0x100, P2 ?trans1;
ISETP.LT.U32.OR P3, PT, R18, 0x80, P3 ?trans1;
ISETP.GT.U32.AND P4, PT, R3, 0x1f, PT ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={0} ?trans1;
ULEA UR5, UR6, UR5, 0x18 ?WAIT5_END_GROUP;
LEA R4, R3.reuse, UR4, 0x2 ?trans2;
LEA R5, R3, UR5, 0x2 ?WAIT3_END_GROUP;
STS [R4], R11 &rd=0x0 ?trans4;
STS [R5], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x6a0 ?trans5;
LDS R7, [R4+0x800] ?trans4;
LDS R6, [R4] &wr=0x1 ?trans2;
FSETP.GEU.AND P0, PT, R7, R6, PT &req={1} ?WAIT13_END_GROUP;
@!P0 STS [R4], R7 ?trans1;
@!P0 MOV R11, R7 &req={0} ?WAIT3_END_GROUP;
@!P0 LDS R2, [R5+0x800] &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x760 ?trans4;
@P1 BRA 0x750 ?trans5;
LDS R7, [R4+0x400] ?trans4;
LDS R6, [R4] &wr=0x2 ?trans2;
FSETP.GEU.AND P0, PT, R7, R6, PT &req={2} ?WAIT13_END_GROUP;
@!P0 STS [R4], R7 ?trans1;
@!P0 MOV R11, R7 &req={0} ?WAIT3_END_GROUP;
@!P0 LDS R2, [R5+0x400] &req={1} &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x810 ?trans4;
@P2 BRA 0x800 ?trans5;
LDS R7, [R4+0x200] ?trans4;
LDS R6, [R4] &wr=0x3 ?trans2;
FSETP.GEU.AND P0, PT, R7, R6, PT &req={3} ?WAIT13_END_GROUP;
@!P0 STS [R4], R7 ?trans1;
@!P0 MOV R11, R7 &req={0} ?WAIT3_END_GROUP;
@!P0 LDS R2, [R5+0x200] &req={2,1} &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x8c0 ?trans4;
@P3 BRA 0x8b0 ?trans5;
LDS R7, [R4+0x100] ?trans4;
LDS R6, [R4] &wr=0x4 ?trans2;
FSETP.GEU.AND P0, PT, R7, R6, PT &req={4} ?WAIT13_END_GROUP;
@!P0 STS [R4], R7 ?trans1;
@!P0 MOV R11, R7 &req={0} ?WAIT3_END_GROUP;
@!P0 LDS R2, [R5+0x100] &req={3,2,1} &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P4 EXIT ?trans5;
LDS R6, [R4+0x80] ?trans1;
ISETP.NE.AND P1, PT, R3, RZ, PT ?WAIT3_END_GROUP;
LDS R7, [R4] &wr=0x5 ?trans2;
FSETP.GEU.AND P0, PT, R6, R7, PT &req={5} ?WAIT13_END_GROUP;
@!P0 LDS R11, [R4+0x80] &req={0} &wr=0x0 ?trans4;
@!P0 STS [R4], R11 &req={0} ?trans4;
@!P0 LDS R2, [R5+0x80] &req={4,3,2,1} &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} ?trans4;
LDS R6, [R4+0x40] ?trans4;
LDS R7, [R4] &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, R6, R7, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDS R11, [R4+0x40] &wr=0x0 ?trans4;
@!P0 STS [R4], R11 &req={0} ?trans4;
@!P0 LDS R2, [R5+0x40] &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} ?trans4;
LDS R6, [R4+0x20] ?trans4;
LDS R7, [R4] &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, R6, R7, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDS R11, [R4+0x20] &wr=0x0 ?trans4;
@!P0 STS [R4], R11 &req={0} ?trans4;
@!P0 LDS R2, [R5+0x20] &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} ?trans4;
LDS R6, [R4+0x10] ?trans4;
LDS R7, [R4] &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, R6, R7, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDS R11, [R4+0x10] &wr=0x0 ?trans4;
@!P0 STS [R4], R11 &req={0} ?trans4;
@!P0 LDS R2, [R5+0x10] &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} ?trans4;
LDS R6, [R4+0x8] ?trans4;
LDS R7, [R4] &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, R6, R7, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDS R11, [R4+0x8] &wr=0x0 ?trans4;
@!P0 STS [R4], R11 &req={0} ?trans4;
@!P0 LDS R2, [R5+0x8] &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} ?trans4;
LDS R6, [R4+0x4] ?trans4;
LDS R7, [R4] &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, R6, R7, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDS R11, [R4+0x4] &wr=0x0 ?trans4;
@!P0 STS [R4], R11 &req={0} ?trans4;
@!P0 LDS R2, [R5+0x4] &wr=0x0 ?trans4;
@!P0 STS [R5], R2 &req={0} &rd=0x0 ?trans1;
@P1 EXIT ?trans5;
LDC.64 R4, c[0x0][0x398] &req={0} &wr=0x0 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x3a0] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R0, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR8][R4.64], R11 &rd=0x0 ?trans1;
ISETP.NE.S64.AND P0, PT, R8, RZ, PT &req={1} ?WAIT3_END_GROUP;
LEA R6, P1, R0, R6, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R7, R0, R7, RZ, 0x2, P1 ?WAIT7_END_GROUP;
@!P0 BRA 0xc50 &req={0} ?trans5;
IMAD.WIDE R2, R2, 0x4, R8 ?WAIT6_END_GROUP;
LDG.E R2, desc[UR8][R2.64] &rd=0x0 &wr=0x5 ?trans2;
STG.E desc[UR8][R6.64], R2 &req={5} ?trans1;
EXIT ?trans5;
BRA 0xc70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: getMin(float*, int*, int, float*, int*)
_Z6getMinPfPiiS_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s8, s15
v_mov_b32_e32 v7, 0x7f800000
v_lshl_or_b32 v1, s8, 10, v0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_16
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, 0x80, v1
v_dual_mov_b32 v5, 0x7f800000 :: v_dual_mov_b32 v8, 0x7f800000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v6, v[2:3], off
v_cmpx_gt_i32_e64 s2, v4
s_cbranch_execz .LBB0_3
global_load_b32 v8, v[2:3], off offset:512
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v7, 0x100, v1
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v7
s_cbranch_execz .LBB0_5
global_load_b32 v5, v[2:3], off offset:1024
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v9, 0x180, v1
v_mov_b32_e32 v10, 0x7f800000
v_mov_b32_e32 v12, 0x7f800000
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_gt_i32_e64 s2, v9
s_cbranch_execz .LBB0_7
global_load_b32 v12, v[2:3], off offset:1536
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v11, 0x200, v1
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v11
s_cbranch_execz .LBB0_9
global_load_b32 v10, v[2:3], off offset:2048
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v13, 0x280, v1
v_mov_b32_e32 v14, 0x7f800000
v_mov_b32_e32 v16, 0x7f800000
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_gt_i32_e64 s2, v13
s_cbranch_execz .LBB0_11
global_load_b32 v16, v[2:3], off offset:2560
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v15, 0x300, v1
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v15
s_cbranch_execz .LBB0_13
global_load_b32 v14, v[2:3], off offset:3072
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v17, 0x380, v1
v_mov_b32_e32 v18, 0x7f800000
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v17
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_15
global_load_b32 v18, v[2:3], off offset:3584
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v8
v_cmp_neq_f32_e64 s2, 0, v5
v_cndmask_b32_e32 v2, 0x7f800000, v8, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0x7f800000, v5, s2
v_cmp_neq_f32_e64 s2, 0, v12
v_cndmask_b32_e32 v3, 0x7f800000, v6, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, v2, v3
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, 0x7f800000, v12, s2
v_cmp_neq_f32_e64 s2, 0, v10
v_cmp_lt_f32_e32 vcc_lo, v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0x7f800000, v10, s2
v_cmp_neq_f32_e64 s2, 0, v16
v_dual_cndmask_b32 v1, v1, v7 :: v_dual_cndmask_b32 v2, v2, v5
v_cmp_lt_f32_e32 vcc_lo, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v2, v2, v3
v_cndmask_b32_e64 v3, 0x7f800000, v16, s2
v_cmp_neq_f32_e64 s2, 0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_lt_f32_e32 vcc_lo, v4, v2
v_dual_cndmask_b32 v1, v1, v11 :: v_dual_cndmask_b32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, 0x7f800000, v14, s2
v_cmp_neq_f32_e64 s2, 0, v18
v_cmp_lt_f32_e32 vcc_lo, v3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v1, v1, v13 :: v_dual_cndmask_b32 v2, v2, v3
v_cndmask_b32_e64 v3, 0x7f800000, v18, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_f32_e32 vcc_lo, v4, v2
v_dual_cndmask_b32 v1, v1, v15 :: v_dual_cndmask_b32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e32 vcc_lo, v3, v2
v_cndmask_b32_e32 v1, v1, v17, vcc_lo
v_cndmask_b32_e32 v7, v2, v3, vcc_lo
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v6, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
ds_store_2addr_stride64_b32 v6, v1, v7 offset1:2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x34
v_add_nc_u32_e32 v8, 0x200, v6
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmpk_gt_u32 s2, 0x3ff
s_cselect_b32 s3, -1, 0
s_and_b32 s4, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_20
ds_load_2addr_stride64_b32 v[2:3], v8 offset1:8
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v3, v2
s_cbranch_execz .LBB0_19
ds_load_b32 v1, v6 offset:2048
v_mov_b32_e32 v7, v3
ds_store_b32 v8, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v6, v1
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_cmpk_gt_u32 s2, 0x1ff
s_waitcnt lgkmcnt(0)
s_cselect_b32 s3, -1, 0
s_barrier
s_and_b32 s4, vcc_lo, s3
buffer_gl0_inv
s_and_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_24
ds_load_2addr_stride64_b32 v[2:3], v8 offset1:4
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v3, v2
s_cbranch_execz .LBB0_23
ds_load_b32 v1, v6 offset:1024
v_mov_b32_e32 v7, v3
ds_store_b32 v8, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v6, v1
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
s_cmpk_gt_u32 s2, 0xff
s_waitcnt lgkmcnt(0)
s_cselect_b32 s3, -1, 0
s_barrier
s_and_b32 s4, vcc_lo, s3
buffer_gl0_inv
s_and_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_28
ds_load_2addr_stride64_b32 v[2:3], v8 offset1:2
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v3, v2
s_cbranch_execz .LBB0_27
ds_store_b32 v8, v3
ds_load_b32 v1, v6 offset:512
v_mov_b32_e32 v7, v3
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v1
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_28:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e32 vcc_lo, 64, v0
s_cmpk_gt_u32 s2, 0x7f
s_waitcnt lgkmcnt(0)
s_cselect_b32 s2, -1, 0
s_barrier
s_and_b32 s3, vcc_lo, s2
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_32
ds_load_2addr_stride64_b32 v[2:3], v8 offset1:1
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v3, v2
s_cbranch_execz .LBB0_31
ds_load_b32 v1, v6 offset:256
v_mov_b32_e32 v7, v3
ds_store_b32 v8, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v6, v1
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_32:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_46
v_or_b32_e32 v9, 32, v0
s_mov_b64 s[2:3], src_shared_base
v_cmp_ne_u32_e64 s2, -1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, v9, 2, 0x200
v_cndmask_b32_e64 v3, 0, s3, s2
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_cndmask_b32_e32 v4, 0, v2, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_cndmask_b32_e64 v2, 0, v8, s2
s_mov_b32 s2, exec_lo
flat_load_b32 v10, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v10, v11
s_cbranch_execz .LBB0_35
flat_load_b32 v7, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v9
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v4, 0, v6, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, 64, v8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
flat_load_b32 v9, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v10, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v9, v10
s_cbranch_execz .LBB0_37
flat_load_b32 v7, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 64, v6
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v5, 0, s11, vcc_lo
v_cndmask_b32_e32 v4, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_37:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, 32, v8
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
flat_load_b32 v9, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v10, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v9, v10
s_cbranch_execz .LBB0_39
flat_load_b32 v7, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 32, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_cndmask_b32_e32 v4, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, 16, v8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
flat_load_b32 v9, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v10, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v9, v10
s_cbranch_execz .LBB0_41
flat_load_b32 v7, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 16, v6
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v5, 0, s11, vcc_lo
v_cndmask_b32_e32 v4, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_41:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, 8, v8
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
flat_load_b32 v9, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v10, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v9, v10
s_cbranch_execz .LBB0_43
flat_load_b32 v7, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 8, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
v_cndmask_b32_e32 v4, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v4, 4, v8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s3, vcc_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_45
flat_load_b32 v7, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 4, v6
s_mov_b64 s[10:11], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v6
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v7 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v3, 0, s11, vcc_lo
v_cndmask_b32_e32 v2, 0, v6, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_45:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_50
s_load_b128 s[0:3], s[0:1], 0x18
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[4:5], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_cmp_eq_u64 s[6:7], 0
global_store_b32 v0, v7, s[0:1]
s_cbranch_scc1 .LBB0_49
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
.LBB0_49:
s_add_u32 s0, s2, s4
s_addc_u32 s1, s3, s5
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_50:
s_endpgm
| getMin | 4,836 | 7,774 | stackv2-00000-of-00015 |
// Demangled: update(float*, int, int, int, int, int)
Function : _Z6updatePfiiiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R10, c[0x0][0x388] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans2;
IMAD R9, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R9, R11, PT &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R9, R10, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR4, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R9, UR4, PT &req={0} ?WAIT13_END_GROUP;
@!P0 LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
@!P0 IMAD R3, R11, R10, UR4 ?trans2;
@!P0 IMAD R7, R10, UR4, R11 ?trans2;
@!P0 IMAD.WIDE R2, R3, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R4, R7, 0x4, R4 ?trans1;
@!P0 STG.E desc[UR8][R2.64], RZ &req={1} &rd=0x0 ?trans4;
@!P0 STG.E desc[UR8][R4.64], RZ &rd=0x0 ?trans1;
@!P0 EXIT ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R5, R10, UR4, R9.reuse &req={0} ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R3, R11, R10, R9 ?trans1;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans1;
IMAD.WIDE R4, R5, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R3, 0x4, R6 ?trans1;
LDG.E R2, desc[UR8][R4.64] &wr=0x2 ?trans4;
LDG.E R0, desc[UR8][R6.64] &wr=0x3 ?trans1;
UIADD3 UR6, UPT, UPT, UR5, UR4, URZ &req={0} ?trans1;
UI2FP.F32.S32 UR5, UR5 ?trans1;
UI2FP.F32.S32 UR4, UR4 ?trans1;
BSSY.RECONVERGENT B0, 0x300 ?trans3;
I2FP.F32.S32 R11, UR6 ?WAIT4_END_GROUP;
MUFU.RCP R8, R11 &wr=0x0 ?trans2;
FFMA R13, -R11, R8, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R13, R8, R13, R8 ?trans1;
FMUL R3, R2, UR5 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R0, UR4, R3 &req={3} ?WAIT4_END_GROUP;
FCHK P0, R0, R11 &wr=0x0 ?trans1;
FFMA R2, R0, R13, RZ ?WAIT4_END_GROUP;
FFMA R3, -R11, R2, R0 ?WAIT4_END_GROUP;
FFMA R13, R13, R3, R2 ?trans1;
@!P0 BRA 0x2f0 &req={0} ?trans6;
MOV R2, 0x2e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x3c0 ?trans5;
MOV R13, R8 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans1;
STG.E desc[UR8][R6.64], R13 ?trans4;
STG.E desc[UR8][R4.64], RZ ?trans2;
LDC.64 R10, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R3, R9.reuse, R2.reuse, R3 &req={0} ?trans2;
IMAD R9, R9, R2, UR4 &req={1} ?WAIT2_END_GROUP;
IMAD.WIDE R2, R3, 0x4, R10 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R8, R9, 0x4, R10 ?trans1;
STG.E desc[UR8][R2.64], R13 ?trans4;
STG.E desc[UR8][R8.64], RZ ?trans1;
EXIT ?trans5;
SHF.R.U32.HI R8, RZ, 0x17, R11 ?trans1;
BSSY.RECONVERGENT B1, 0xa20 ?trans1;
SHF.R.U32.HI R3, RZ, 0x17, R0 ?trans2;
LOP3.LUT R10, R8, 0xff, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R8, R3, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R12, R0 ?trans1;
IADD3 R15, PT, PT, R10, -0x1, RZ ?trans2;
IADD3 R14, PT, PT, R8, -0x1, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R15, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R13, RZ ?trans1;
@!P0 BRA 0x600 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ?trans1;
MOV R3, R11 ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0xa00 ?trans5;
LOP3.LUT P0, RZ, R11, 0x7fffffff, R12, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x9e0 ?trans5;
FSETP.NEU.FTZ.AND P2, PT, |R0|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ?WAIT12_END_GROUP;
@!P1 BRA !P2, 0x9e0 ?trans5;
LOP3.LUT P2, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P1 BRA 0x9c0 ?trans5;
LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x990 ?trans5;
ISETP.GE.AND P0, PT, R14, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R15, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R13, RZ ?trans1;
@!P0 MOV R13, 0xffffffc0 ?trans1;
@!P0 FFMA R12, R0, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R11, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R13, PT, PT, R13, 0x40, RZ ?WAIT7_END_GROUP;
LEA R0, R10, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B2, 0x980 ?trans1;
IADD3 R3, PT, PT, R8, -0x7f, RZ ?trans2;
IADD3 R11, PT, PT, -R0, R11, RZ ?WAIT3_END_GROUP;
IMAD R0, R3.reuse, -0x800000, R12 ?trans1;
IADD3 R10, PT, PT, R3, 0x7f, -R10 ?trans1;
MUFU.RCP R14, R11 &wr=0x0 ?trans1;
FADD.FTZ R15, -R11, -RZ ?trans2;
IADD3 R13, PT, PT, R10, R13, RZ ?trans2;
FFMA R17, R14, R15, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R19, R14, R17, R14 ?WAIT4_END_GROUP;
FFMA R8, R0, R19, RZ ?WAIT4_END_GROUP;
FFMA R17, R15, R8, R0 ?WAIT4_END_GROUP;
FFMA R12, R19, R17, R8 ?WAIT4_END_GROUP;
FFMA R15, R15, R12, R0 ?WAIT4_END_GROUP;
FFMA R8, R19, R15, R12 ?WAIT5_END_GROUP;
SHF.R.U32.HI R0, RZ, 0x17, R8 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R14, PT, PT, R0, R13, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R14, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x960 ?trans5;
ISETP.GT.AND P0, PT, R14, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x930 ?trans5;
ISETP.GE.AND P0, PT, R14, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x970 ?trans5;
ISETP.GE.AND P0, PT, R14, -0x18, PT ?trans1;
LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x970 ?trans5;
FFMA.RZ R0, R19.reuse, R15.reuse, R12.reuse ?trans1;
IADD3 R11, PT, PT, R14.reuse, 0x20, RZ ?trans1;
FFMA.RM R3, R19, R15, R12 ?trans1;
ISETP.NE.AND P1, PT, R14.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R14, RZ, PT ?trans1;
LOP3.LUT R0, R0, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R10, R0, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R0, R19, R15, R12 ?trans1;
IADD3 R12, PT, PT, -R14, RZ, RZ ?trans2;
SHF.L.U32 R11, R10, R11, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R0, R3, PT ?trans1;
SEL R3, R12, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R11, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R3, RZ, R3, R10 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R11, RZ, 0x1, R3 ?WAIT3_END_GROUP;
SEL R0, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R0, R0, 0x1, R11, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, R3, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R11, R0, RZ ?WAIT4_END_GROUP;
LOP3.LUT R8, R11, R8, RZ, 0xfc, !PT ?trans1;
BRA 0x970 ?trans6;
LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x970 ?trans6;
IMAD R8, R13, 0x800000, R8 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
BRA 0xa10 ?trans5;
LOP3.LUT R8, R11, 0x80000000, R12, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0xa10 ?trans6;
LOP3.LUT R8, R11, 0x80000000, R12, 0x48, !PT ?trans1;
BRA 0xa10 ?trans6;
MUFU.RSQ R8, -QNAN &wr=0x0 ?trans1;
BRA 0xa10 ?trans5;
FADD.FTZ R8, R0, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R2 0x0 &req={0} ?trans5;
BRA 0xa40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: update(float*, int, int, int, int, int)
_Z6updatePfiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_cmp_ne_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_6
s_clause 0x1
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e64 s6, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_3
v_mad_u64_u32 v[2:3], null, s6, s4, v[1:2]
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v7, s3
v_cvt_f32_i32_e32 v8, s7
v_mul_lo_u32 v12, v1, s4
s_add_i32 s3, s3, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v9, s3
v_mad_u64_u32 v[4:5], null, s5, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, v0, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v8
v_div_scale_f32 v6, null, v9, v9, v7
v_div_scale_f32 v10, vcc_lo, v7, v9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v0, -v6, v8, 1.0
v_fmac_f32_e32 v8, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v8
v_fma_f32 v0, -v6, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v0, v8
v_add_nc_u32_e32 v0, s5, v12
v_fma_f32 v6, -v6, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_div_fmas_f32 v6, v6, v8, v11
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_div_fixup_f32 v9, v6, v9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_nc_u32_e32 v0, s6, v12
s_clause 0x2
global_store_b32 v[4:5], v9, off
global_store_b32 v[2:3], v8, off
global_store_b32 v[6:7], v9, off
.LBB1_3:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_5
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s3, s6
s_mul_i32 s3, s6, s4
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s0, s8
s_addc_u32 s7, s1, s9
s_add_i32 s3, s3, s5
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s3
global_store_b32 v1, v1, s[6:7]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| update | 4,072 | 2,074 | stackv2-00000-of-00015 |
// Demangled: getTotal(int, float*, float*)
Function : _Z8getTotaliPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?trans2;
LDG.E R7, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans4;
LDG.E R2, desc[UR4][R2.64] &wr=0x2 ?trans2;
FADD R7, R2, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: getTotal(int, float*, float*)
_Z8getTotaliPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_load_b32 s0, s[2:3], 0x0
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s0, v0
global_store_b32 v1, v0, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| getTotal | 484 | 480 | stackv2-00000-of-00015 |
// Demangled: getVariance(int, float*, float*, float*)
Function : _Z11getVarianceiPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R3, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans2;
LDG.E R7, desc[UR4][R6.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R4.64] &rd=0x0 &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x140 ?trans1;
MOV R4, 0x130 &req={0} ?trans1;
FADD R0, R0, -R7 &req={2} ?WAIT4_END_GROUP;
F2F.F64.F32 R2, R0 &rd=0x0 &wr=0x1 ?trans3;
CALL.REL.NOINC 0x360 &req={1,0} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R6, c[0x0][0x398] &wr=0x0 ?trans2;
LDG.E R8, desc[UR4][R6.64] &req={0} &wr=0x2 ?trans1;
DADD R4, R2, 2 &wr=0x0 ?trans1;
FSETP.NEU.AND P0, PT, R0.reuse, RZ, PT ?trans1;
LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?trans1;
BSSY.RECONVERGENT B0, 0x2c0 ?trans1;
MOV R5, R11 ?trans1;
FSETP.NEU.AND P1, PT, R0, 1, PT ?trans2;
ISETP.NE.AND P2, PT, R4, 0x7ff00000, PT ?trans1;
MOV R4, R10 ?WAIT6_END_GROUP;
@!P0 MOV.64 R4, RZ ?WAIT15_END_GROUP;
NOP ?WAIT5_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F64.F32 R8, R8 &req={2} &wr=0x0 ?trans2;
@P2 BRA 0x2b0 &req={0} ?trans5;
FSETP.NAN.AND P0, PT, R0, R0, PT ?WAIT13_END_GROUP;
@P0 DADD R4, R2, 2 &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x2b0 &req={1,0} ?trans5;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
LOP3.LUT R2, R3, 0x7fffffff, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ?WAIT13_END_GROUP;
@!P0 MOV.64 R4, 0x7ff0000000000000 ?WAIT8_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
FSEL R2, R4, RZ, P1 ?trans1;
FSEL R3, R5, 1.875, P1 ?WAIT6_END_GROUP;
DADD R8, R8, R2 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R9, R8 &req={0} &wr=0x0 ?trans2;
STG.E desc[UR4][R6.64], R9 &req={0} ?trans1;
EXIT ?trans5;
DADD R8, -RZ, |R2| &wr=0x0 ?trans1;
UMOV.64 UR6, 0x4330000080000000 ?trans1;
ISETP.GT.U32.AND P0, PT, R9, 0xfffff, PT &req={0} ?trans1;
MOV R5, R9 ?trans1;
MOV R6, R8 ?trans1;
UMOV.64 UR8, 0x3c7abc9e3b39803f ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P0 DMUL R14, R8, 1.80143985094819840000e+16 &wr=0x0 ?trans2;
@!P0 MOV R5, R15 &req={0} ?trans1;
@!P0 MOV R6, R14 ?trans1;
SHF.R.U32.HI R8, RZ, 0x14, R9 ?trans2;
@!P0 LEA.HI R8, R15, 0xffffffca, RZ, 0xc ?trans2;
LOP3.LUT R5, R5, 0x800fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R7, R5, 0x3ff00000, RZ, 0xfc, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R7, 0x3ff6a09f, PT ?WAIT13_END_GROUP;
@P1 IADD3 R5, PT, PT, R7, -0x100000, RZ ?WAIT5_END_GROUP;
@P1 MOV R7, R5 ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
DADD R12, R6, 1 &wr=0x0 ?trans2;
MUFU.RCP64H R9, R13 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R6, -1 &rd=0x1 ?trans2;
IADD3 R6, PT, PT, R8.reuse, -0x3ff, RZ &req={1} ?trans2;
@P1 IADD3 R6, PT, PT, R8, -0x3fe, RZ ?trans1;
MOV R8, RZ ?trans1;
HFMA2 R7, -RZ, RZ, 3.59375, 0 ?trans2;
LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, -R12, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R14, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R8, R14, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R10, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R14, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R10, -R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R16, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R18, R8, R8 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, -R8, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R14, R10 &req={0} &wr=0x0 ?trans2;
IADD3 R15, PT, PT, R11, 0x100000, RZ &req={0} ?trans1;
MOV R14, R10 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R8, R18 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R8, R18, -R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R8, R8, -R18 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R10, R18, R16 &req={0} &rd=0x0 ?trans2;
MOV.64 R18, 0x3ed0f5d241ad3b5a &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R6, -UR6 ?trans1;
UMOV.64 UR6, 0x3eb0f5ff7d2cafe2 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R8, R14, R20 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R8, R8 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, UR6, R18 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3ef3b20a75488a3f ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f1745cde4faecd5 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f3c71c7258a578b ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f6249249242b910 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f89999999999dfb ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R14, R18, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fb5555555555555 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R8, R20, R16 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R14, R18, UR6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, -R20, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3c46a4cb00b9e7b0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R14, R18, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R22, R22, -UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fe62e42fefa39ef ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R20, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, R20, -R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R20, R22, R20 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R18, R14, R12 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R22, R14, R12, -R18 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, R16, R22 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R20, R12, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R18, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R8, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R18, -R12 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, -R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R18, R16, R18 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R12, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R18, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R14, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R6, UR6, R10 &req={0} ?trans1;
UMOV.64 UR6, 0x3fe62e42fefa39ef ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R14, -R10 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R8, R14 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R6, -UR6, R12 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, -R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R14, -R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R6, UR8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R12, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R12, -R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R8, R12 &req={0} &rd=0x0 ?trans2;
MOV.64 R8, 0x3ff71547652b82fe &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R6, 2 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R6, 2, -R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, 2, R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R6, R10, R12 &req={0} &wr=0x0 ?trans2;
FSETP.GEU.AND P0, PT, |R7|, 4.1917929649353027344, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R10, -R6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R6, R8, 6.75539944105574400000e+15 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R12, R10 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R8, -6.75539944105574400000e+15 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R12, -UR6, R6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3c7abc9e3b39803f ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R12, -UR6, R14 &req={0} &rd=0x0 &wr=0x1 ?trans1;
UMOV.64 UR6, 0x3e5ade1569ce2bdf ?trans1;
MOV.64 R12, 0x3e928af3fca213ea &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, UR6, R12 &req={1} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3ec71dee62401315 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3efa01997c89eb71 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f2a01a014761f65 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f56c16c1852b7af ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3f81111111122322 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fa55555555502a1 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fc5555555555511 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?trans1;
UMOV.64 UR6, 0x3fe000000000000b ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, UR6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, R12, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R12, 1 &req={0} &wr=0x0 ?trans2;
IMAD R13, R8, 0x100000, R15 &req={0} ?trans1;
MOV R12, R14 ?trans1;
@!P0 BRA 0x1fb0 ?trans6;
FSETP.GEU.AND P1, PT, |R7|, 4.2275390625, PT ?trans1;
DSETP.GEU.AND P0, PT, R6, RZ, PT ?WAIT12_END_GROUP;
@!P1 LEA.HI R5, R8, R8, RZ, 0x1 ?WAIT4_END_GROUP;
@!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ?WAIT4_END_GROUP;
@!P1 IADD3 R8, PT, PT, R8, -R5, RZ ?WAIT4_END_GROUP;
@!P1 LEA R9, R8, 0x3ff00000, 0x14 ?trans1;
@!P1 MOV R8, RZ ?WAIT15_END_GROUP;
NOP ?WAIT9_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R6, +INF &wr=0x0 ?trans2;
FSEL R12, R12, RZ, P0 &req={0} ?trans1;
FSEL R13, R13, RZ, P0 ?trans1;
@!P1 IMAD R7, R5, 0x100000, R15 ?trans1;
@!P1 MOV R6, R14 ?WAIT15_END_GROUP;
NOP ?WAIT14_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DMUL R12, R6, R8 &rd=0x0 &wr=0x1 ?trans2;
LOP3.LUT R5, R13, 0x7fffffff, RZ, 0xc0, !PT &req={1} ?trans1;
DFMA R10, R10, R12, R12 &wr=0x1 ?trans1;
ISETP.NE.AND P1, PT, R12, RZ, PT ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R5, 0x7ff00000, PT ?trans2;
FSEL R5, R12, R10, !P1 &req={1} ?trans1;
FSEL R13, R13, R11, !P1 ?WAIT4_END_GROUP;
FSEL R10, R5, R10, !P0 ?trans1;
MOV R5, 0x0 ?trans1;
FSEL R11, R13, R11, !P0 ?WAIT3_END_GROUP;
RET.REL.NODEC R4 0x0 &req={0} ?trans5;
BRA 0x2050;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: getVariance(int, float*, float*, float*)
_Z11getVarianceiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_load_b32 s2, s[6:7], 0x0
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_subrev_f32_e32 v0, s2, v0
s_mov_b32 s2, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v1, |v0|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v1, v1, v2
v_add_f32_e32 v2, 1.0, v1
v_add_f32_e32 v4, -1.0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, -1.0, v2
v_sub_f32_e32 v1, v1, v6
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, v4, v3
v_cmp_neq_f32_e64 s3, 0x7f800000, |v0|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v2, v5
v_fma_f32 v2, v5, v2, -v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v5, v1
v_add_f32_e32 v1, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v4, v1 :: v_dual_sub_f32 v7, v1, v7
v_sub_f32_e32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v6
v_sub_f32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v2, v1
v_add_f32_e32 v1, v6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v3, v1
v_add_f32_e32 v2, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v2, v2
v_sub_f32_e32 v3, v2, v5
v_sub_f32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v2, v2, -v4
v_add_f32_e32 v5, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v5
v_add_f32_e32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmaak_f32 v6, s2, v5, 0x3e91f4c4
v_sub_f32_e32 v4, v5, v4
s_load_b32 s2, s[0:1], 0x0
v_dual_fmaak_f32 v6, v5, v6, 0x3ecccdef :: v_dual_sub_f32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v5, v6
v_fma_f32 v4, v5, v6, -v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v3, v6
v_add_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v6, v7 :: v_dual_add_f32 v8, 0x3f2aaaaa, v6
v_dual_mul_f32 v9, v2, v5 :: v_dual_sub_f32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v5, v2, -v9
v_add_f32_e32 v7, 0xbf2aaaaa, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, 0x31739010, v4
v_fmac_f32_e32 v10, v5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v6, v6, v7
v_ldexp_f32 v1, v1, 1
v_fmac_f32_e32 v10, v3, v2
v_ldexp_f32 v2, v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v9, v10
v_add_f32_e32 v4, v4, v6
v_add_f32_e32 v3, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v6, v8, v3
v_mul_f32_e32 v7, v5, v3
v_sub_f32_e32 v8, v5, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v4, v6
v_fma_f32 v6, v5, v3, -v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v10, v8
v_fmac_f32_e32 v6, v5, v4
v_frexp_exp_i32_f32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v8, v3
v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v7, v6
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v4, v7
v_dual_mul_f32 v8, 0x3f317218, v3 :: v_dual_add_f32 v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v7
v_fma_f32 v7, 0x3f317218, v3, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v1, v1, v6
v_dual_fmamk_f32 v3, v3, 0xb102e308, v7 :: v_dual_sub_f32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v4, v2
v_dual_add_f32 v1, v1, v2 :: v_dual_add_f32 v2, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v5, v1
v_dual_add_f32 v6, v2, v4 :: v_dual_sub_f32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v6, v2
v_dual_sub_f32 v8, v2, v8 :: v_dual_sub_f32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v6, v7
v_dual_sub_f32 v3, v3, v8 :: v_dual_sub_f32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v9
v_dual_add_f32 v5, v3, v1 :: v_dual_add_f32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v5, v3
v_add_f32_e32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v4
v_sub_f32_e32 v1, v1, v4
v_sub_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v2
v_dual_add_f32 v1, v1, v3 :: v_dual_sub_f32 v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v4
v_add_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v7, v1
v_sub_f32_e32 v3, v2, v7
v_add_f32_e32 v4, v2, v2
v_mul_f32_e32 v5, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v1, v1, v3
v_fma_f32 v2, v2, 2.0, -v4
v_cmp_class_f32_e64 vcc_lo, v4, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 2.0, v1
v_add_f32_e32 v1, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v4, v1
v_cndmask_b32_e32 v3, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e64 v5, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v3|
v_sub_f32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x3fb8aa3b, v6
v_fma_f32 v8, 0x3fb8aa3b, v6, -v7
v_rndne_f32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v8, v6, 0x32a5705f, v8 :: v_dual_sub_f32 v7, v7, v9
v_add_f32_e32 v7, v7, v8
v_sub_f32_e32 v2, v2, v4
v_cvt_i32_f32_e32 v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v7, v7
v_sub_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v7, v4
v_dual_add_f32 v1, v5, v1 :: v_dual_cndmask_b32 v2, 0, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
v_fma_f32 v1, v2, v1, v2
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v1, 0x7f800000, |v1|, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, 0, v1 :: v_dual_mov_b32 v1, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, s2, v0
global_store_b32 v1, v0, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| getVariance | 8,107 | 4,799 | stackv2-00000-of-00015 |
// Demangled: sobel_transform(unsigned char*, unsigned char*, unsigned int, unsigned int)
Function : _Z15sobel_transformPhS_jj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans1;
IMAD R3, R3, UR5, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R3, UR7, PT &req={3} ?trans1;
IMAD R0, R0, UR4, R5 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.U32.OR P0, PT, R0, UR6, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans1;
BSSY.RECONVERGENT B1, 0x290 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
BSSY.RELIABLE B0, 0x210 ?trans1;
ISETP.LT.OR P1, PT, R0, 0x1, !P0 ?WAIT13_END_GROUP;
@P1 BRA 0x1b0 ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R3, -0x1, RZ ?WAIT5_END_GROUP;
IMAD R5, R5, UR6, R0 ?WAIT5_END_GROUP;
IADD3 R4, PT, PT, R5, -0x1, RZ ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R4, R4, UR8 &req={1} ?WAIT6_END_GROUP;
LDG.E.U8 R2, desc[UR4][R4.64] &req={0} &rd=0x0 &wr=0x5 ?trans1;
BRA 0x200 ?trans5;
ISETP.GE.AND P1, PT, R0, 0x1, PT ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans1;
MOV R2, RZ ?WAIT11_END_GROUP;
@!P1 BREAK.RELIABLE B0 ?trans5;
@!P1 BRA 0x280 ?trans5;
BSYNC.RELIABLE B0 &req={0} ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD R4, R3, UR6, R0 ?trans1;
MOV R5, RZ ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R4, -0x1, RZ ?WAIT5_END_GROUP;
IADD.64 R4, R4, UR8 &req={0} ?WAIT7_END_GROUP;
LDG.E.U8 R4, desc[UR4][R4.64] &wr=0x2 ?trans2;
IMAD.U32 R13, R4, -0x2, RZ &req={2} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 &req={0} ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
IADD3 R5, PT, PT, R3, 0x1, RZ ?trans2;
IADD3 R12, PT, PT, R0, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R5, UR7, PT ?trans2;
ISETP.GE.U32.OR P0, PT, R12, UR6, !P0 ?WAIT3_END_GROUP;
ISETP.LT.OR P2, PT, R0, 0x1, P1 ?WAIT10_END_GROUP;
@!P0 LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans1;
@!P0 IADD3 R7, PT, PT, R3, -0x1, RZ ?trans2;
@!P2 IMAD R5, R5, UR6, R0 ?WAIT3_END_GROUP;
@!P0 IMAD R6, R7, UR6, R12 ?trans1;
@!P0 MOV R7, RZ ?trans1;
@!P2 LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
@!P2 IADD3 R4, PT, PT, R5, -0x1, RZ ?trans1;
@!P2 MOV R5, RZ ?trans2;
@!P0 IADD.64 R6, R6, R10 &req={0} ?trans2;
CS2R R10, SRZ ?trans1;
@!P2 IADD.64 R4, R4, R8 &req={1} ?trans2;
CS2R R8, SRZ ?WAIT3_END_GROUP;
@!P0 LDG.E.U8 R10, desc[UR4][R6.64] &rd=0x0 &wr=0x5 ?trans4;
@!P2 LDG.E.U8 R8, desc[UR4][R4.64] &rd=0x0 &wr=0x5 ?trans1;
ISETP.GE.U32.AND P0, PT, R12, UR6, PT ?trans1;
BSSY.RECONVERGENT B1, 0x4c0 ?WAIT12_END_GROUP;
@P0 BRA 0x4b0 &req={0} ?trans5;
LDCU.64 UR8, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD R4, R3, UR6, R12 ?trans2;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
@!P1 MOV R7, RZ ?trans2;
@!P1 IADD3 R6, PT, PT, R4.reuse, UR6, RZ ?trans2;
IADD.64 R4, R4, UR8 &req={0} ?WAIT3_END_GROUP;
@!P1 IADD.64 R6, R6, UR8 ?WAIT4_END_GROUP;
LDG.E.U8 R4, desc[UR4][R4.64] &wr=0x2 ?trans4;
@!P1 LDG.E.U8 R11, desc[UR4][R6.64] &rd=0x0 &wr=0x5 ?trans2;
IMAD.SHL.U32 R9, R4, 0x2, RZ &req={2,0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
LDCU.64 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R2, PT, PT, R13, -R2, -R8 &req={5} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R9, R2, R10 ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R2, R11, RZ ?trans1;
IMAD R2, R3, UR6, R0 ?trans2;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans2;
ISETP.GT.AND P0, PT, R11, 0x7f, PT ?WAIT3_END_GROUP;
IADD.64 R2, R2, UR8 &req={0} ?trans2;
SEL R5, RZ, 0xffffffff, !P0 ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x570;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sobel_transform(unsigned char*, unsigned char*, unsigned int, unsigned int)
_Z15sobel_transformPhS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s8, v0
v_cmp_gt_u32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -1, v0
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v7, -1, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s0, vcc_lo
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v7, s8, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_u8 v3, v5, s[6:7]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v1, s8, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_u8 v5, v5, s[6:7]
s_waitcnt vmcnt(0)
v_mul_i32_i24_e32 v5, -2, v5
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v6, 1, v1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v4, 0
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s9, v6
s_cbranch_execz .LBB0_8
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[8:9], null, v6, s8, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v8, s[6:7]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v2, 1, v0
v_mov_b32_e32 v8, 0
v_cmp_gt_u32_e64 s0, s8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s0, vcc_lo
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v7, s8, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_u8 v9, v9, s[6:7]
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_13
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v1, s8, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_u8 v7, v7, s[6:7]
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v8, 1, v7
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v7, 0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v7, 0
s_mov_b32 s0, exec_lo
v_cmpx_gt_u32_e64 s9, v6
s_cbranch_execz .LBB0_16
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v6, s8, v[2:3]
s_waitcnt lgkmcnt(0)
global_load_u8 v7, v10, s[6:7]
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v4
v_sub_nc_u32_e32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v9
v_add3_u32 v4, v2, v8, v7
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, 0x7f, v4
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v0, s[4:5]
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sobel_transform | 2,098 | 1,885 | stackv2-00000-of-00015 |
// Demangled: kernel_lap(int, int, int, float*, float*, float*, float*)
Function : _Z10kernel_lapiiiPfS_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans1;
LDCU.64 UR26, c[0x0][0x380] &wr=0x3 ?trans1;
S2R R3, SR_TID.X &wr=0x4 ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x5 ?trans5;
LDC R0, c[0x0][0x360] &wr=0x4 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x2 ?trans7;
S2UR UR8, SR_CTAID.X &wr=0x4 ?trans1;
ULEA.HI UR7, UR26, UR26, URZ, 0x1 &req={3} ?WAIT4_END_GROUP;
USHF.R.S32.HI UR7, URZ, 0x1, UR7 ?trans1;
UIMAD UR5, UR5, UR4, URZ &req={2} ?WAIT3_END_GROUP;
UIADD3 UR4, UPT, UPT, -UR7, UR27, URZ ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R4, UR5, RZ &req={1} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R2, UR7, RZ ?trans1;
IMAD R0, R0, UR8, R3 &req={4} ?trans1;
UIADD3 UR8, UPT, UPT, -UR7, UR6, URZ &req={5} ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R0, UR7, RZ ?trans2;
ISETP.GE.AND P0, PT, R12, UR8, PT ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R13, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.LE.AND P0, PT, RZ, UR26, PT ?trans1;
LDCU.64 UR28, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R25, -RZ, RZ, 0, 0 ?WAIT11_END_GROUP;
@!P0 BRA 0xfd0 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR26, 0x7, UPT ?trans1;
UIADD3 UR24, UPT, UPT, UR26, 0x1, URZ ?trans1;
UMOV UR4, URZ ?trans1;
CS2R R24, SRZ ?trans2;
ULOP3.LUT UR27, UR24, 0x7, URZ, 0xc0, !UPT ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, RZ, UR27, PT ?WAIT8_END_GROUP;
@!P0 BRA 0x900 ?trans5;
LDCU.128 UR20, c[0x0][0x3a0] &wr=0x1 ?trans1;
MOV R3, UR5 ?trans1;
HFMA2 R24, -RZ, RZ, 0, 0 ?trans2;
IMAD R15, R13, UR6, R2 ?trans1;
USHF.R.S32.HI UR13, URZ, 0x1f, UR6 ?trans2;
UMOV UR12, UR6 ?trans1;
IADD3 R3, PT, PT, R3, UR7, R4 ?trans1;
ULOP3.LUT UR4, UR24, 0xfffffff8, URZ, 0xc0, !UPT ?trans1;
UIADD3.64 UR14, UPT, UPT, UR12, UR12, URZ ?WAIT3_END_GROUP;
IMAD R14, R0, UR6, R3 ?trans1;
UIADD3.64 UR16, UPT, UPT, UR12, UR14, URZ ?trans1;
USHF.L.U64.HI UR25, UR14, 0x2, UR15 ?WAIT3_END_GROUP;
UIADD3.64 UR18, UPT, UPT, UR12, UR16, URZ ?trans1;
USHF.L.U64.HI UR17, UR16, 0x2, UR17 ?trans1;
UIADD3.64 UR10, UPT, UPT, UR20, 0x10, URZ &req={1} ?trans1;
UIADD3.64 UR8, UPT, UPT, UR22, 0x10, URZ ?trans1;
UIADD3.64 UR20, UPT, UPT, UR12, UR18, URZ ?trans1;
USHF.L.U32 UR23, UR14, 0x2, URZ ?trans1;
UIADD3 UR22, UPT, UPT, -UR4, URZ, URZ ?trans1;
USHF.L.U64.HI UR19, UR18, 0x2, UR19 ?trans1;
UIADD3.64 UR14, UPT, UPT, UR12, UR20, URZ ?trans1;
MOV.64 R2, UR8 ?trans2;
MOV.64 R4, UR10 ?WAIT2_END_GROUP;
USHF.L.U64.HI UR21, UR20, 0x2, UR21 ?trans1;
UIADD3.64 UR12, UPT, UPT, UR12, UR14, URZ ?trans1;
USHF.L.U64.HI UR15, UR14, 0x2, UR15 ?trans1;
USHF.L.U32 UR16, UR16, 0x2, URZ ?trans1;
USHF.L.U32 UR18, UR18, 0x2, URZ ?trans1;
USHF.L.U64.HI UR13, UR12, 0x2, UR13 ?trans1;
USHF.L.U32 UR20, UR20, 0x2, URZ ?trans1;
USHF.L.U32 UR14, UR14, 0x2, URZ ?trans1;
USHF.L.U32 UR12, UR12, 0x2, URZ ?trans1;
UMOV UR4, URZ ?WAIT11_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
MOV R31, UR6 ?trans1;
LDG.E.CONSTANT R8, desc[UR28][R2.64+-0x10] &req={0} &wr=0x2 ?trans4;
LDG.E.CONSTANT R10, desc[UR28][R2.64+-0xc] &wr=0x3 ?trans4;
LDG.E.CONSTANT R26, desc[UR28][R4.64+-0x10] &wr=0x4 ?trans4;
LDG.E.CONSTANT R27, desc[UR28][R4.64+-0xc] &wr=0x5 ?trans1;
UMOV UR8, UR23 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R29, desc[UR28][R2.64+-0x8] &wr=0x2 ?trans1;
UMOV UR9, UR25 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R16, desc[UR28][R4.64+-0x8] &wr=0x2 ?trans1;
IMAD.WIDE R22, R15, 0x4, R6.reuse &req={1} ?trans1;
UMOV UR10, UR18 ?trans1;
UMOV UR11, UR19 ?trans1;
LDG.E.CONSTANT R35, desc[UR28][R4.64+0x8] &wr=0x2 ?trans1;
IMAD.WIDE R6, R14, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R9, desc[UR28][R22.64] &wr=0x2 ?trans1;
IMAD.WIDE R30, R31, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R11, desc[UR28][R22.64+0x4] &wr=0x3 ?trans4;
LDG.E.CONSTANT R28, desc[UR28][R6.64] &wr=0x4 ?trans4;
LDG.E.CONSTANT R30, desc[UR28][R30.64] &rd=0x4 &wr=0x5 ?trans4;
LDG.E.CONSTANT R32, desc[UR28][R22.64+0x8] &wr=0x5 ?trans1;
IADD.64 R18, R6, UR8 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R17, desc[UR28][R22.64+0xc] &wr=0x5 ?trans4;
LDG.E.CONSTANT R19, desc[UR28][R18.64] &wr=0x5 ?trans1;
UMOV UR8, UR16 ?trans1;
UMOV UR9, UR17 ?trans2;
LDG.E.CONSTANT R20, desc[UR28][R22.64+0x10] &wr=0x5 ?trans4;
LDG.E.CONSTANT R21, desc[UR28][R22.64+0x14] &wr=0x5 ?trans4;
LDG.E.CONSTANT R18, desc[UR28][R22.64+0x18] &wr=0x5 ?trans4;
LDG.E.CONSTANT R37, desc[UR28][R2.64+0xc] &wr=0x5 ?trans1;
FFMA R8, R9, R8, R24 &req={2} ?WAIT3_END_GROUP;
LDG.E.CONSTANT R24, desc[UR28][R22.64+0x1c] &wr=0x2 ?trans1;
FFMA R33, R11, R10, R8 &req={3} ?trans1;
IADD.64 R8, R6, UR8 ?trans2;
FFMA R31, R28, R26, R25 &req={4} ?trans1;
IADD.64 R10, R6, UR10 ?trans2;
UMOV UR8, UR20 ?trans1;
FFMA R30, R30, R27, R31 &req={5} ?trans1;
UMOV UR9, UR21 ?trans1;
LDG.E.CONSTANT R25, desc[UR28][R8.64] &rd=0x0 &wr=0x3 ?trans1;
UMOV UR10, UR14 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R27, desc[UR28][R2.64+-0x4] &wr=0x4 ?trans1;
FFMA R28, R32, R29, R33 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R22, desc[UR28][R4.64+-0x4] &wr=0x3 ?trans1;
IADD.64 R8, R6.reuse, UR8 &req={0} ?trans2;
UMOV UR11, UR15 ?trans1;
LDG.E.CONSTANT R26, desc[UR28][R10.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E.CONSTANT R29, desc[UR28][R2.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R23, desc[UR28][R4.64] &wr=0x5 ?trans1;
IADD.64 R10, R6, UR10 &req={0} ?WAIT3_END_GROUP;
LDG.E.CONSTANT R32, desc[UR28][R2.64+0x4] &wr=0x5 ?trans1;
IADD.64 R6, R6, UR12 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R8, desc[UR28][R8.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R31, desc[UR28][R4.64+0x4] &wr=0x5 ?trans1;
FFMA R16, R19, R16, R30 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R10, desc[UR28][R10.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R33, desc[UR28][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E.CONSTANT R6, desc[UR28][R6.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E.CONSTANT R19, desc[UR28][R4.64+0xc] &rd=0x1 &wr=0x5 ?trans1;
UIADD3 UR22, UPT, UPT, UR22, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR22, PT ?trans1;
MOV R7, UR6 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD.64 R2, R2, 0x20 ?trans2;
IADD.64 R4, R4, 0x20 &req={1} ?trans2;
IMAD R14, R7, 0x8, R14 ?trans1;
IADD3 R15, PT, PT, R15, 0x8, RZ ?trans1;
FFMA R17, R17, R27, R28 &req={4} ?trans1;
FFMA R25, R25, R22, R16 &req={3} ?WAIT3_END_GROUP;
FFMA R20, R20, R29, R17 &req={2} ?trans1;
FFMA R23, R26, R23, R25 &req={5} ?WAIT3_END_GROUP;
FFMA R21, R21, R32, R20 ?trans1;
FFMA R23, R8, R31, R23 ?WAIT4_END_GROUP;
FFMA R23, R10, R35, R23 ?trans1;
FFMA R21, R18, R33, R21 ?WAIT4_END_GROUP;
FFMA R24, R24, R37, R21 ?trans1;
FFMA R25, R6, R19, R23 ?trans1;
@P0 BRA 0x420 ?trans6;
IMAD R14, R13, UR6, R12 ?trans1;
@!P1 BRA 0xfc0 ?trans6;
UISETP.GE.U32.AND UP0, UPT, UR27, 0x4, UPT ?trans1;
ULOP3.LUT UP1, UR24, UR24, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans2;
PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x8 ?WAIT11_END_GROUP;
@!P1 BRA 0xc70 ?trans5;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x1 ?trans1;
LDC.64 R8, c[0x0][0x390] &wr=0x2 ?trans1;
IADD3 R3, PT, PT, R0, UR4, RZ ?trans1;
MOV R19, UR7 ?trans1;
MOV R10, UR6 ?trans1;
UIMAD.WIDE.U32 UR8, UR4, 0x4, UR14 &req={1} ?WAIT6_END_GROUP;
MOV.64 R6, UR8 ?trans2;
USHF.R.S32.HI UR8, URZ, 0x1f, UR6 ?trans2;
IMAD R3, R3, UR6, R12 ?trans1;
IADD3 R19, PT, PT, R14, UR4, -R19 ?trans1;
MOV R17, UR6 ?trans1;
LDG.E.CONSTANT R23, desc[UR28][R6.64] &req={0} &wr=0x3 ?trans1;
MOV R11, UR8 ?trans1;
UIMAD.WIDE.U32 UR8, UR4, 0x4, UR12 ?trans1;
IMAD.WIDE R2, R3, 0x4, R8 &req={2} ?trans1;
LDG.E.CONSTANT R15, desc[UR28][R6.64+0x4] &wr=0x2 ?trans2;
IADD.64 R4, R10, R10 ?WAIT2_END_GROUP;
LDG.E.CONSTANT R22, desc[UR28][R6.64+0x8] &wr=0x4 ?trans1;
IMAD.WIDE R8, R19, 0x4, R8 ?trans1;
IADD.64 R10, R10, R4 ?trans2;
LDG.E.CONSTANT R26, desc[UR28][R6.64+0xc] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE R16, R17, 0x4, R2 ?trans1;
LEA R18, P1, R4, R2.reuse, 0x2 ?trans2;
LEA R20, P2, R10, R2, 0x2 ?trans1;
LDG.E.CONSTANT R27, desc[UR28][R8.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R30, desc[UR28][R8.64+0xc] &wr=0x5 ?trans1;
MOV.64 R6, UR8 &req={0} ?WAIT3_END_GROUP;
LEA.HI.X R19, R4, R3.reuse, R5, 0x2, P1 ?trans1;
LDG.E.CONSTANT R2, desc[UR28][R2.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R28, desc[UR28][R6.64] &wr=0x2 ?trans1;
LEA.HI.X R21, R10, R3, R11, 0x2, P2 ?WAIT3_END_GROUP;
LDG.E.CONSTANT R16, desc[UR28][R16.64] &wr=0x4 ?trans4;
LDG.E.CONSTANT R5, desc[UR28][R8.64+0x4] &wr=0x4 ?trans4;
LDG.E.CONSTANT R4, desc[UR28][R6.64+0x4] &wr=0x5 ?trans4;
LDG.E.CONSTANT R10, desc[UR28][R8.64+0x8] &wr=0x5 ?trans4;
LDG.E.CONSTANT R19, desc[UR28][R18.64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R11, desc[UR28][R6.64+0x8] &wr=0x5 ?trans4;
LDG.E.CONSTANT R17, desc[UR28][R6.64+0xc] &wr=0x5 ?trans4;
LDG.E.CONSTANT R21, desc[UR28][R20.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
FFMA R24, R27, R23, R24 &req={3} ?trans1;
FFMA R25, R2, R28, R25 &req={2} ?WAIT3_END_GROUP;
FFMA R5, R5, R15, R24 &req={4} ?trans1;
FFMA R4, R16, R4, R25 &req={5} ?WAIT3_END_GROUP;
FFMA R5, R10, R22, R5 ?WAIT4_END_GROUP;
FFMA R24, R30, R26, R5 ?trans1;
FFMA R4, R19, R11, R4 ?WAIT4_END_GROUP;
FFMA R25, R21, R17, R4 ?WAIT7_END_GROUP;
@!P0 BRA 0xfc0 ?trans5;
UISETP.NE.AND UP0, UPT, UR24, 0x1, UPT ?trans1;
ULOP3.LUT UR8, UR26, 0x1, URZ, 0xc0, !UPT ?WAIT4_END_GROUP;
UISETP.NE.U32.AND UP1, UPT, UR8, 0x1, UPT ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP1, 0x80, 0x8 ?WAIT8_END_GROUP;
@!P0 BRA 0xe90 ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.128 UR8, c[0x0][0x3a0] &wr=0x2 ?trans1;
IADD3 R3, PT, PT, R0, UR4, RZ ?trans1;
MOV R9, UR7 ?trans1;
MOV R15, UR6 ?WAIT3_END_GROUP;
IMAD R3, R3, UR6, R12 ?trans1;
IADD3 R9, PT, PT, R14, UR4, -R9 ?trans1;
UIMAD.WIDE.U32 UR12, UR4, 0x4, UR8 &req={2} ?trans1;
UIMAD.WIDE.U32 UR8, UR4, 0x4, UR10 ?trans1;
IMAD.WIDE R6, R3, 0x4, R4 &req={1} ?WAIT4_END_GROUP;
MOV.64 R10, UR12 ?trans2;
MOV.64 R2, UR8 ?trans2;
IMAD.WIDE R4, R9, 0x4, R4 ?trans1;
LDG.E.CONSTANT R18, desc[UR28][R6.64] &req={0} &wr=0x2 ?trans3;
IMAD.WIDE R8, R15, 0x4, R6 ?trans1;
LDG.E.CONSTANT R17, desc[UR28][R10.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R16, desc[UR28][R2.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R15, desc[UR28][R4.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R21, desc[UR28][R10.64+0x4] &wr=0x4 ?trans4;
LDG.E.CONSTANT R19, desc[UR28][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E.CONSTANT R8, desc[UR28][R8.64] &wr=0x4 ?trans4;
LDG.E.CONSTANT R20, desc[UR28][R4.64+0x4] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
FFMA R17, R18, R17, R25 &req={2} ?trans1;
FFMA R15, R15, R16, R24 &req={3} ?WAIT3_END_GROUP;
FFMA R25, R8, R21, R17 &req={4} ?trans1;
FFMA R24, R20, R19, R15 &req={5} ?WAIT7_END_GROUP;
@!P1 BRA 0xfc0 ?trans5;
LDC.64 R4, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.128 UR12, c[0x0][0x3a0] &wr=0x2 ?trans1;
MOV R3, UR7 ?trans1;
IADD3 R7, PT, PT, R0, UR4, RZ ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R14, UR4, -R3 ?trans1;
IMAD R11, R7, UR6, R12 ?trans1;
UIMAD.WIDE.U32 UR8, UR4, 0x4, UR14 &req={2} ?trans1;
UIMAD.WIDE.U32 UR10, UR4, 0x4, UR12 ?trans2;
IMAD.WIDE R2, R3, 0x4, R4 &req={1} ?WAIT3_END_GROUP;
MOV.64 R6, UR8 ?trans2;
MOV.64 R8, UR10 ?trans2;
IMAD.WIDE R4, R11, 0x4, R4 ?trans1;
LDG.E.CONSTANT R3, desc[UR28][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E.CONSTANT R6, desc[UR28][R6.64] &wr=0x2 ?trans4;
LDG.E.CONSTANT R8, desc[UR28][R8.64] &wr=0x3 ?trans4;
LDG.E.CONSTANT R4, desc[UR28][R4.64] &wr=0x3 ?trans1;
FFMA R24, R3, R6, R24 &req={2} ?trans1;
FFMA R25, R4, R8, R25 &req={3} ?WAIT7_END_GROUP;
FADD R25, R25, R24 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans1;
IMAD R13, R13, UR6, R12 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R13, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR28][R2.64], R25 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x1020;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel_lap(int, int, int, float*, float*, float*, float*)
_Z10kernel_lapiiiPfS_S_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x3c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 31
s_and_b32 s7, s2, 0xffff
s_add_i32 s3, s4, s3
s_lshr_b32 s2, s2, 16
s_ashr_i32 s3, s3, 1
s_mul_i32 s14, s14, s7
v_add_nc_u32_e32 v2, s3, v1
s_mul_i32 s15, s15, s2
v_add3_u32 v3, s14, s3, v0
s_sub_i32 s2, s5, s3
s_sub_i32 s3, s6, s3
v_add_nc_u32_e32 v4, s15, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v3
v_cmp_gt_i32_e64 s2, s3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x18
v_mul_lo_u32 v5, v3, s6
v_mov_b32_e32 v3, 0
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x20
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v0, s14, v0
v_mov_b32_e32 v6, 0
s_add_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s6, v0
v_add3_u32 v0, v1, v5, s15
v_add3_u32 v2, v2, v3, s15
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[0:1]
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
s_clause 0x1
global_load_b32 v1, v[8:9], off
global_load_b32 v3, v[10:11], off
s_load_b32 s5, s[2:3], 0x0
s_load_b32 s7, s[0:1], 0x0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_add_nc_u32_e32 v0, 1, v0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_fmac_f32 v6, s5, v1 :: v_dual_fmac_f32 v7, s7, v3
s_cbranch_scc0 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v7, v6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v5, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel_lap | 6,799 | 1,592 | stackv2-00000-of-00015 |
// Demangled: gpu(int*, int*, int*)
Function : _Z3gpuPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R7, R7, UR4, R6 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 &req={3} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={4} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R6.reuse, UR4, 0x2 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
IMAD R0, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
MOV R0, 0x40 &req={1} ?WAIT7_END_GROUP;
LDS.128 R24, [R0+UR4+-0x40] &wr=0x0 ?trans4;
LDS.128 R20, [R0+UR4+-0x30] &wr=0x1 ?trans4;
LDS.128 R4, [R0+UR4+-0x20] &wr=0x2 ?trans4;
LDS.128 R16, [R0+UR4+-0x10] &wr=0x3 ?trans4;
LDS.128 R12, [R0+UR4] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R25, R24, R9 &req={0} ?WAIT3_END_GROUP;
LDS.128 R8, [R0+UR4+0x10] &wr=0x0 ?trans1;
IADD3 R24, PT, PT, R27, R26, R24 ?WAIT4_END_GROUP;
IADD3 R20, PT, PT, R21, R20, R24 &req={1} ?trans2;
LDS.128 R24, [R0+UR4+0x20] &wr=0x1 ?trans2;
IADD3 R20, PT, PT, R23, R22, R20 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R5, R4, R20 &req={2} ?trans2;
LDS.128 R20, [R0+UR4+0x30] &rd=0x2 &wr=0x5 ?trans2;
IADD3 R4, PT, PT, R7, R6, R4 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R17, R16, R4 &req={3} ?trans2;
IADD3 R0, PT, PT, R0, 0x80, RZ &req={2} ?trans2;
IADD3 R4, PT, PT, R19, R18, R4 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R0, 0x1040, PT ?trans1;
IADD3 R4, PT, PT, R13, R12, R4 &req={4} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R15, R14, R4 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R9, R8, R4 &req={0} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R11, R10, R4 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R25, R24, R4 &req={1} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R27, R26, R4 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R21, R20, R4 &req={5} ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R23, R22, R4 ?trans1;
@P0 BRA 0x170 ?trans6;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans2;
REDG.E.ADD.STRONG.GPU desc[UR6][R2.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x350;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu(int*, int*, int*)
_Z3gpuPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v3
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x1000
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu | 1,447 | 867 | stackv2-00000-of-00015 |
// Demangled: mk_kernel(char*, unsigned long)
Function : _Z9mk_kernelPcm
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.NE.S64.AND P0, PT, RZ, UR8, PT &req={1} ?WAIT14_END_GROUP;
@!P0 EXIT ?trans5;
MOV.64 R2, RZ ?trans2;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x2 ?trans1;
UMOV UR4, URZ ?WAIT5_END_GROUP;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?trans1;
IADD.64 R4, R2, UR10 &req={2} ?trans2;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
MOV R2, UR4 ?trans1;
STG.E.U8 desc[UR6][R4.64], RZ &req={1} &rd=0x3 ?trans4;
ISETP.GE.U64.AND P0, PT, R2, UR8, PT ?WAIT14_END_GROUP;
@!P0 BRA 0x80 &req={3} ?trans5;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mk_kernel(char*, unsigned long)
_Z9mk_kernelPcm:
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b64 s[4:5], 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_3
v_mov_b32_e32 v0, 0
s_mov_b32 s7, 0
.LBB0_2:
s_add_u32 s8, s0, s4
s_addc_u32 s9, s1, s5
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_mov_b32 s6, s4
global_store_b8 v0, v0, s[8:9]
v_cmp_ge_u64_e64 s6, s[6:7], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mk_kernel | 429 | 297 | stackv2-00000-of-00015 |
// Demangled: K1()
Function : _Z2K1v
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
IADD3 R1, PT, PT, R1, -0x8, RZ &req={0} ?trans1;
LDCU UR4, c[0x0][0x2f8] &wr=0x0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
MOV R0, 0x0 ?trans1;
LDCU UR5, c[0x0][0x2fc] &wr=0x0 ?trans1;
MOV R2, R1 ?trans1;
LDCU.64 UR6, c[0x4][0x8] &wr=0x2 ?trans4;
IADD.64 R6, R2, UR4 &req={0} ?WAIT2_END_GROUP;
LDC.64 R2, c[0x4][R0] &rd=0x0 &wr=0x3 ?trans1;
MOV R4, UR6 &req={2} ?trans1;
MOV R5, UR7 ?trans1;
STL [R1], R8 &req={1} &rd=0x0 ?trans6;
LEPC R20, 0x100 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={3,0} ?trans5;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: K1()
_Z2K1v:
s_load_b64 s[18:19], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v39, -1, 0
v_mov_b32_e32 v6, 0
v_dual_mov_b32 v38, v0 :: v_dual_mov_b32 v7, 0
s_mov_b32 s32, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v39
v_readfirstlane_b32 s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, s2, v4
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[5:6], v0, s[18:19]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB1_5
s_mov_b32 s5, 0
.LBB1_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[10:11], v0, s[18:19]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s5
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[18:19] offset:40
global_load_b128 v[0:3], v5, s[18:19]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s3, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB1_8
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
s_add_i32 s10, s8, s3
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s9
v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v2, v6
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
v_mov_b32_e32 v6, v5
v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
s_clause 0x3
global_store_b128 v[8:9], v[4:7], off
global_store_b128 v[8:9], v[10:13], off offset:16
global_store_b128 v[8:9], v[10:13], off offset:32
global_store_b128 v[8:9], v[10:13], off offset:48
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB1_16
v_mov_b32_e32 v10, 0
s_mov_b32 s7, exec_lo
s_clause 0x1
global_load_b64 v[13:14], v10, s[18:19] offset:32 glc
global_load_b64 v[2:3], v10, s[18:19] offset:40
v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, s5, v3
v_and_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, 24
v_mul_hi_u32 v4, v2, 24
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
v_add_co_u32 v6, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
global_store_b64 v[6:7], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB1_12
s_mov_b32 s10, 0
.LBB1_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB1_11
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v5, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v4, s10, 0
global_load_b64 v[2:3], v5, s[18:19] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB1_14
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB1_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s3
v_add_co_u32 v0, vcc_lo, v0, s9
v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_17:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_19
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB1_19:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v2
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_21
s_mov_b32 s3, 0
s_sleep 1
s_branch .LBB1_22
.LBB1_21:
s_mov_b32 s3, -1
.LBB1_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_17
global_load_b64 v[0:1], v[8:9], off
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_27
v_mov_b32_e32 v8, 0
s_clause 0x2
global_load_b64 v[4:5], v8, s[18:19] offset:40
global_load_b64 v[9:10], v8, s[18:19] offset:24 glc
global_load_b64 v[6:7], v8, s[18:19]
s_waitcnt vmcnt(2)
v_add_co_u32 v11, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v11, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v2, v4
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v4, 24
v_mul_lo_u32 v4, v4, 24
v_add_nc_u32_e32 v5, v11, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v9
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v10
global_store_b64 v[6:7], v[9:10], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_27
s_mov_b32 s2, 0
.LBB1_26:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_26
.LBB1_27:
s_or_b32 exec_lo, exec_lo, s3
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, .str@rel32@lo+4
s_addc_u32 s3, s3, .str@rel32@hi+12
v_dual_mov_b32 v36, 0 :: v_dual_mov_b32 v5, 0
s_cmp_lg_u64 s[2:3], 0
v_mov_b32_e32 v6, 0
s_cselect_b32 s4, -1, 0
s_mov_b64 s[8:9], s[0:1]
v_cndmask_b32_e64 v2, 0, 1, s4
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, __ockl_printf_append_string_n@rel32@lo+4
s_addc_u32 s5, s5, __ockl_printf_append_string_n@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, s3 :: v_dual_lshlrev_b32 v4, 3, v2
v_mov_b32_e32 v2, s2
s_swappc_b64 s[30:31], s[4:5]
v_readfirstlane_b32 s0, v39
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v39
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_33
global_load_b64 v[3:4], v36, s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v36, s[18:19] offset:40
global_load_b64 v[5:6], v36, s[18:19]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v4
v_and_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v7, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v7, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v36, v[1:4], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[3:4]
s_cbranch_execz .LBB1_32
v_mov_b32_e32 v1, 0
s_mov_b32 s3, 0
.LBB1_30:
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[18:19] offset:40
global_load_b64 v[9:10], v1, s[18:19]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v2, 24, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, v5 :: v_dual_and_b32 v3, v3, v8
v_mad_u64_u32 v[5:6], null, v3, 24, v[2:3]
global_load_b64 v[5:6], v[4:5], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_30
s_or_b32 exec_lo, exec_lo, s3
.LBB1_32:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB1_33:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[7:8], v36, s[18:19] offset:40
global_load_b128 v[1:4], v36, s[18:19]
v_readfirstlane_b32 s2, v5
v_readfirstlane_b32 s3, v6
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s4, v7
v_readfirstlane_b32 s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[4:5], s[2:3], s[4:5]
s_mul_i32 s1, s5, 24
s_mul_hi_u32 s6, s4, 24
s_mul_i32 s7, s4, 24
s_and_saveexec_b32 s9, s0
s_cbranch_execz .LBB1_35
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, 0
s_add_i32 s8, s6, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v1, s7
v_add_co_ci_u32_e32 v10, vcc_lo, s8, v2, vcc_lo
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB1_35:
s_or_b32 exec_lo, exec_lo, s9
s_mov_b32 s8, 0
s_lshl_b64 s[4:5], s[4:5], 12
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_mov_b32_e32 v40, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 6, v[39:40]
v_and_or_b32 v36, 0xffffff1d, v0, 34
v_add_co_u32 v7, vcc_lo, v3, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, v4, v6, vcc_lo
v_mov_b32_e32 v3, s8
v_dual_mov_b32 v39, v40 :: v_dual_mov_b32 v4, s9
v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
s_clause 0x3
global_store_b128 v[7:8], v[36:39], off
global_store_b128 v[7:8], v[3:6], off offset:16
global_store_b128 v[7:8], v[3:6], off offset:32
global_store_b128 v[7:8], v[3:6], off offset:48
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB1_43
s_clause 0x1
global_load_b64 v[11:12], v40, s[18:19] offset:32 glc
global_load_b64 v[3:4], v40, s[18:19] offset:40
v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v10, s3
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v3
v_readfirstlane_b32 s9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[2:3]
s_mul_i32 s5, s9, 24
s_mul_hi_u32 s9, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s9, s9, s5
v_add_co_u32 v7, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
s_mov_b32 s5, exec_lo
global_store_b64 v[7:8], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v40, v[9:12], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[5:6], v[11:12]
s_cbranch_execz .LBB1_39
s_mov_b32 s8, 0
.LBB1_38:
v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v40, v[3:6], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_38
.LBB1_39:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v6, 0
s_mov_b32 s8, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v0, s8, 0
global_load_b64 v[3:4], v6, s[18:19] offset:16
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_41
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s8
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB1_41:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
global_load_b64 v[5:6], v[3:4], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_cbranch_vccnz .LBB1_43
global_load_b32 v3, v[3:4], off offset:24
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v3
s_waitcnt_vscnt null, 0x0
global_store_b64 v[5:6], v[3:4], off
s_and_b32 m0, s5, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_43:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s6, s6, s1
v_add_co_u32 v0, vcc_lo, v1, s7
v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_44:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_46
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB1_46:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB1_48
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB1_49
.LBB1_48:
s_mov_b32 s1, -1
.LBB1_49:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB1_44
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_54
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[18:19] offset:40
global_load_b64 v[7:8], v6, s[18:19] offset:24 glc
global_load_b64 v[4:5], v6, s[18:19]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_54
s_mov_b32 s0, 0
.LBB1_53:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_53
.LBB1_54:
s_endpgm
| K1 | 419 | 9,727 | stackv2-00000-of-00015 |
// Demangled: K2()
Function : _Z2K2v
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans1;
IADD3 R1, PT, PT, R1, -0x8, RZ &req={0} ?trans1;
LDCU UR4, c[0x0][0x2f8] &wr=0x0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
MOV R0, 0x0 ?trans1;
MOV R2, R1 ?WAIT4_END_GROUP;
LDCU UR5, c[0x0][0x2fc] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x4][0x10] &wr=0x2 ?trans1;
IADD.64 R6, R2, UR4 &req={0} ?trans2;
LDC.64 R2, c[0x4][R0] &rd=0x0 &wr=0x3 ?trans1;
STL [R1], R8 &req={1} &rd=0x0 ?trans1;
MOV R4, UR6 &req={2} ?trans1;
MOV R5, UR7 ?WAIT7_END_GROUP;
LEPC R20, 0x110 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={3,0} ?trans5;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: K2()
_Z2K2v:
s_barrier
buffer_gl0_inv
s_load_b64 s[18:19], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v39, -1, 0
v_mov_b32_e32 v6, 0
v_dual_mov_b32 v38, v0 :: v_dual_mov_b32 v7, 0
s_mov_b32 s32, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v39
v_readfirstlane_b32 s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, s2, v4
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[5:6], v0, s[18:19]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB2_5
s_mov_b32 s5, 0
.LBB2_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[18:19] offset:40
global_load_b64 v[10:11], v0, s[18:19]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB2_3
s_or_b32 exec_lo, exec_lo, s5
.LBB2_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB2_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[18:19] offset:40
global_load_b128 v[0:3], v5, s[18:19]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_mul_i32 s3, s7, 24
s_mul_hi_u32 s8, s6, 24
s_mul_i32 s9, s6, 24
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB2_8
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, v5
s_add_i32 s10, s8, s3
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s9
v_add_co_ci_u32_e32 v11, vcc_lo, s10, v1, vcc_lo
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b64 s[6:7], s[6:7], 12
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v2, v6
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
v_mov_b32_e32 v6, v5
v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
s_clause 0x3
global_store_b128 v[8:9], v[4:7], off
global_store_b128 v[8:9], v[10:13], off offset:16
global_store_b128 v[8:9], v[10:13], off offset:32
global_store_b128 v[8:9], v[10:13], off offset:48
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB2_16
v_mov_b32_e32 v10, 0
s_mov_b32 s7, exec_lo
s_clause 0x1
global_load_b64 v[13:14], v10, s[18:19] offset:32 glc
global_load_b64 v[2:3], v10, s[18:19] offset:40
v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, s5, v3
v_and_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, 24
v_mul_hi_u32 v4, v2, 24
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
v_add_co_u32 v6, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
global_store_b64 v[6:7], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB2_12
s_mov_b32 s10, 0
.LBB2_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB2_11
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v5, 0
s_mov_b32 s10, exec_lo
s_mov_b32 s7, exec_lo
v_mbcnt_lo_u32_b32 v4, s10, 0
global_load_b64 v[2:3], v5, s[18:19] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB2_14
s_bcnt1_i32_b32 s10, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s10
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB2_14:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB2_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s7, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s7, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_16:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s8, s8, s3
v_add_co_u32 v0, vcc_lo, v0, s9
v_add_co_ci_u32_e32 v1, vcc_lo, s8, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_17:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_19
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB2_19:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v2
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB2_21
s_mov_b32 s3, 0
s_sleep 1
s_branch .LBB2_22
.LBB2_21:
s_mov_b32 s3, -1
.LBB2_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB2_17
global_load_b64 v[0:1], v[8:9], off
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_27
v_mov_b32_e32 v8, 0
s_clause 0x2
global_load_b64 v[4:5], v8, s[18:19] offset:40
global_load_b64 v[9:10], v8, s[18:19] offset:24 glc
global_load_b64 v[6:7], v8, s[18:19]
s_waitcnt vmcnt(2)
v_add_co_u32 v11, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v11, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v2, v4
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v4, 24
v_mul_lo_u32 v4, v4, 24
v_add_nc_u32_e32 v5, v11, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v9
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v10
global_store_b64 v[6:7], v[9:10], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_27
s_mov_b32 s2, 0
.LBB2_26:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB2_26
.LBB2_27:
s_or_b32 exec_lo, exec_lo, s3
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, .str.1@rel32@lo+4
s_addc_u32 s3, s3, .str.1@rel32@hi+12
v_dual_mov_b32 v36, 0 :: v_dual_mov_b32 v5, 0
s_cmp_lg_u64 s[2:3], 0
v_mov_b32_e32 v6, 0
s_cselect_b32 s4, -1, 0
s_mov_b64 s[8:9], s[0:1]
v_cndmask_b32_e64 v2, 0, 1, s4
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, __ockl_printf_append_string_n@rel32@lo+4
s_addc_u32 s5, s5, __ockl_printf_append_string_n@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, s3 :: v_dual_lshlrev_b32 v4, 3, v2
v_mov_b32_e32 v2, s2
s_swappc_b64 s[30:31], s[4:5]
v_readfirstlane_b32 s0, v39
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v37, v1 :: v_dual_mov_b32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v39
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_33
global_load_b64 v[3:4], v36, s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v36, s[18:19] offset:40
global_load_b64 v[5:6], v36, s[18:19]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v4
v_and_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v7, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v7, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v36, v[1:4], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[3:4]
s_cbranch_execz .LBB2_32
v_mov_b32_e32 v1, 0
s_mov_b32 s3, 0
.LBB2_30:
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[18:19] offset:40
global_load_b64 v[9:10], v1, s[18:19]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v2, 24, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, v5 :: v_dual_and_b32 v3, v3, v8
v_mad_u64_u32 v[5:6], null, v3, 24, v[2:3]
global_load_b64 v[5:6], v[4:5], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB2_30
s_or_b32 exec_lo, exec_lo, s3
.LBB2_32:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB2_33:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[7:8], v36, s[18:19] offset:40
global_load_b128 v[1:4], v36, s[18:19]
v_readfirstlane_b32 s2, v5
v_readfirstlane_b32 s3, v6
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s4, v7
v_readfirstlane_b32 s5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[4:5], s[2:3], s[4:5]
s_mul_i32 s1, s5, 24
s_mul_hi_u32 s6, s4, 24
s_mul_i32 s7, s4, 24
s_and_saveexec_b32 s9, s0
s_cbranch_execz .LBB2_35
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, 0
s_add_i32 s8, s6, s1
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v1, s7
v_add_co_ci_u32_e32 v10, vcc_lo, s8, v2, vcc_lo
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB2_35:
s_or_b32 exec_lo, exec_lo, s9
s_mov_b32 s8, 0
s_lshl_b64 s[4:5], s[4:5], 12
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_mov_b32_e32 v40, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 6, v[39:40]
v_and_or_b32 v36, 0xffffff1d, v0, 34
v_add_co_u32 v7, vcc_lo, v3, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, v4, v6, vcc_lo
v_mov_b32_e32 v3, s8
v_dual_mov_b32 v39, v40 :: v_dual_mov_b32 v4, s9
v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
s_clause 0x3
global_store_b128 v[7:8], v[36:39], off
global_store_b128 v[7:8], v[3:6], off offset:16
global_store_b128 v[7:8], v[3:6], off offset:32
global_store_b128 v[7:8], v[3:6], off offset:48
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB2_43
s_clause 0x1
global_load_b64 v[11:12], v40, s[18:19] offset:32 glc
global_load_b64 v[3:4], v40, s[18:19] offset:40
v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v10, s3
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v3
v_readfirstlane_b32 s9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[2:3]
s_mul_i32 s5, s9, 24
s_mul_hi_u32 s9, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s9, s9, s5
v_add_co_u32 v7, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
s_mov_b32 s5, exec_lo
global_store_b64 v[7:8], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[5:6], v40, v[9:12], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[5:6], v[11:12]
s_cbranch_execz .LBB2_39
s_mov_b32 s8, 0
.LBB2_38:
v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3
s_sleep 1
global_store_b64 v[7:8], v[5:6], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[3:4], v40, v[3:6], s[18:19] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[5:6]
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB2_38
.LBB2_39:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v6, 0
s_mov_b32 s8, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v0, s8, 0
global_load_b64 v[3:4], v6, s[18:19] offset:16
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_41
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s8
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[3:4], v[5:6], off offset:8
.LBB2_41:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
global_load_b64 v[5:6], v[3:4], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_cbranch_vccnz .LBB2_43
global_load_b32 v3, v[3:4], off offset:24
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v3
s_waitcnt_vscnt null, 0x0
global_store_b64 v[5:6], v[3:4], off
s_and_b32 m0, s5, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_43:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s6, s6, s1
v_add_co_u32 v0, vcc_lo, v1, s7
v_add_co_ci_u32_e32 v1, vcc_lo, s6, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_44:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_46
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB2_46:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB2_48
s_mov_b32 s1, 0
s_sleep 1
s_branch .LBB2_49
.LBB2_48:
s_mov_b32 s1, -1
.LBB2_49:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB2_44
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_54
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[18:19] offset:40
global_load_b64 v[7:8], v6, s[18:19] offset:24 glc
global_load_b64 v[4:5], v6, s[18:19]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_54
s_mov_b32 s0, 0
.LBB2_53:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[18:19] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB2_53
.LBB2_54:
s_endpgm
| K2 | 437 | 9,739 | stackv2-00000-of-00015 |
// Demangled: K3()
Function : _Z2K3v
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x4][0x18] &wr=0x1 ?trans1;
MOV R2, 0x0 ?trans1;
CS2R R6, SRZ ?WAIT5_END_GROUP;
LDC.64 R2, c[0x4][R2] &wr=0x2 ?trans1;
MOV R4, UR4 &req={1} ?trans1;
MOV R5, UR5 ?WAIT7_END_GROUP;
LEPC R20, 0x90 ?WAIT7_END_GROUP;
CALL.ABS.NOINC R2 &req={2,0} ?trans5;
EXIT ?trans5;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: K3()
_Z2K3v:
s_load_b64 s[4:5], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s2, v4
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_mov_b32 s32, 0
v_cmp_eq_u32_e64 s2, s2, v4
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_6
v_mov_b32_e32 v0, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[4:5] offset:40
global_load_b64 v[5:6], v0, s[4:5]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB3_5
s_mov_b32 s7, 0
.LBB3_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[4:5] offset:40
global_load_b64 v[10:11], v0, s[4:5]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB3_3
s_or_b32 exec_lo, exec_lo, s7
.LBB3_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
.LBB3_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_mov_b32 s12, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[4:5] offset:40
global_load_b128 v[0:3], v5, s[4:5]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s8, v8
v_readfirstlane_b32 s9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[6:7], s[8:9]
s_mul_i32 s3, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s11, s8, 24
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB3_8
v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, v5
s_add_i32 s12, s10, s3
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s11
v_add_co_ci_u32_e32 v11, vcc_lo, s12, v1, vcc_lo
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB3_8:
s_or_b32 exec_lo, exec_lo, s13
s_lshl_b64 s[8:9], s[8:9], 12
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v2, v6
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
v_mov_b32_e32 v6, v5
v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
s_clause 0x3
global_store_b128 v[8:9], v[4:7], off
global_store_b128 v[8:9], v[10:13], off offset:16
global_store_b128 v[8:9], v[10:13], off offset:32
global_store_b128 v[8:9], v[10:13], off offset:48
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB3_15
v_mov_b32_e32 v10, 0
s_mov_b32 s9, exec_lo
s_clause 0x1
global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
global_load_b64 v[2:3], v10, s[4:5] offset:40
v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, s7, v3
v_and_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, 24
v_mul_hi_u32 v4, v2, 24
v_mul_lo_u32 v2, v2, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v4, v3
v_add_co_u32 v6, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
global_store_b64 v[6:7], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB3_11
.LBB3_10:
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[4:5] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB3_10
.LBB3_11:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v5, 0
s_mov_b32 s12, exec_lo
s_mov_b32 s9, exec_lo
v_mbcnt_lo_u32_b32 v4, s12, 0
global_load_b64 v[2:3], v5, s[4:5] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB3_13
s_bcnt1_i32_b32 s12, s12
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s12
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB3_13:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB3_15
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s9, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s9, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB3_15:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s10, s10, s3
v_add_co_u32 v0, vcc_lo, v0, s11
v_add_co_ci_u32_e32 v1, vcc_lo, s10, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB3_16:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_18
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
.LBB3_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v2
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB3_20
s_mov_b32 s3, 0
s_sleep 1
s_branch .LBB3_21
.LBB3_20:
s_mov_b32 s3, -1
.LBB3_21:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB3_16
global_load_b64 v[0:1], v[8:9], off
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_26
v_mov_b32_e32 v8, 0
s_clause 0x2
global_load_b64 v[4:5], v8, s[4:5] offset:40
global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
global_load_b64 v[6:7], v8, s[4:5]
s_waitcnt vmcnt(2)
v_add_co_u32 v11, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v11, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, v2, v4
v_mul_lo_u32 v5, v5, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v4, 24
v_mul_lo_u32 v4, v4, 24
v_add_nc_u32_e32 v5, v11, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v9
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v10
global_store_b64 v[6:7], v[9:10], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_26
s_mov_b32 s2, 0
.LBB3_25:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[4:5] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB3_25
.LBB3_26:
s_or_b32 exec_lo, exec_lo, s3
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, .str.2@rel32@lo+4
s_addc_u32 s3, s3, .str.2@rel32@hi+12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_cmp_lg_u64 s[2:3], 0
v_mov_b32_e32 v6, 1
s_cselect_b32 s6, 5, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s6
s_mov_b64 s[8:9], s[0:1]
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, __ockl_printf_append_string_n@rel32@lo+4
s_addc_u32 s5, s5, __ockl_printf_append_string_n@rel32@hi+12
s_delay_alu instid0(SALU_CYCLE_1)
s_swappc_b64 s[30:31], s[4:5]
s_endpgm
| K3 | 242 | 5,061 | stackv2-00000-of-00015 |
// Demangled: FindMaxCUDA(int*, int*, int)
Function : _Z11FindMaxCUDAPiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R4, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R5, R7, UR4, R4 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R7, 0x2, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R5, R4, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R5], R2 &req={2} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x240 ?trans5;
UMOV UR4, 0x1 ?WAIT5_END_GROUP;
MOV R2, UR4 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR4, URZ ?trans1;
BSSY.RECONVERGENT B0, 0x210 ?trans3;
UIADD3 UR5, UPT, UPT, UR4, -0x1, URZ ?WAIT6_END_GROUP;
LOP3.LUT P0, RZ, R4, UR5, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@P0 BRA 0x200 ?trans5;
IMAD R2, R2, 0x4, R5 ?trans1;
LDS R0, [R5] ?trans5;
LDS R2, [R2] &wr=0x0 ?trans2;
ISETP.GE.AND P0, PT, R0, R2, PT &req={0} ?WAIT13_END_GROUP;
@!P0 STS [R5], R2 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.LE.U32.AND P0, PT, R7, UR4, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x150 ?trans5;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT9_END_GROUP;
LDS R5, [UR4] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: FindMaxCUDA(int*, int*, int)
_Z11FindMaxCUDAPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_9
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s4, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s0, 1
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_mov_b32 s5, s0
s_lshl_b32 s0, s0, 1
s_add_i32 s1, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, s1, v0
s_mov_b32 s1, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, s5, 2, v1
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_ge_u32 s0, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_7:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| FindMaxCUDA | 1,049 | 929 | stackv2-00000-of-00015 |
// Demangled: addMatrix(int*, int*, int*)
Function : _Z9addMatrixPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.Y &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans6;
LDC.64 R4, c[0x0][0x390] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x4 ?trans1;
LEA R9, R9, R0, 0x4 &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={3} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: addMatrix(int*, int*, int*)
_Z9addMatrixPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshrrev_b32_e32 v1, 6, v0
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0x3ff0, v1
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| addMatrix | 485 | 292 | stackv2-00000-of-00015 |
// Demangled: square(float*)
Function : _Z6squarePf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R5, R5, UR6, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
FMUL R5, R0, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: square(float*)
_Z6squarePf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| square | 341 | 361 | stackv2-00000-of-00015 |
// Demangled: brevKernel(unsigned int*, unsigned int*)
Function : _Z10brevKernelPjS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={2} ?trans1;
BREV R7, R2 &req={3} &wr=0x0 ?trans4;
STG.E desc[UR4][R4.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: brevKernel(unsigned int*, unsigned int*)
_Z10brevKernelPjS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_bfrev_b32_e32 v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| brevKernel | 343 | 145 | stackv2-00000-of-00015 |
// Demangled: bytePermKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*)
Function : _Z14bytePermKernelPjS_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R11, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R8, c[0x0][0x398] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R11.reuse, 0x4, R2 &req={2} ?trans2;
LDG.E R6, desc[UR4][R6.64] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R11.reuse, 0x4, R4 &req={3} ?trans2;
LDG.E R2, desc[UR4][R2.64] &wr=0x3 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R8, R11, 0x4, R8 &req={4} ?trans1;
LOP3.LUT R0, R6, 0x7777, RZ, 0xc0, !PT &req={2} ?WAIT4_END_GROUP;
PRMT R11, R2, R0, R5 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R11 ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bytePermKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*)
_Z14bytePermKernelPjS_S_S_:
s_load_b256 s[4:11], s[2:3], 0x0
v_and_b32_e32 v3, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x4
v_bfe_u32 v6, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_load_b32 v5, v4, s[8:9]
global_load_b32 v1, v4, s[4:5]
global_load_b32 v2, v4, s[6:7]
s_lshr_b32 s0, s0, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s1
v_mul_lo_u32 v3, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v3, v6, s1, v3
v_add_lshl_u32 v0, v3, v0, 3
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v3, 4, v5
v_lshrrev_b32_e32 v6, 8, v5
v_lshrrev_b32_e32 v7, 12, v5
v_and_or_b32 v5, v5, 7, v0
s_waitcnt vmcnt(0)
ds_store_b64 v0, v[1:2]
v_and_or_b32 v3, v3, 7, v0
v_and_or_b32 v6, v6, 7, v0
v_and_or_b32 v7, v7, 7, v0
ds_load_u8 v0, v5
ds_load_u8 v1, v3
ds_load_u8 v2, v6
ds_load_u8 v3, v7
s_waitcnt lgkmcnt(2)
v_lshl_or_b32 v0, v1, 8, v0
s_waitcnt lgkmcnt(1)
v_lshlrev_b32_e32 v1, 16, v2
s_waitcnt lgkmcnt(0)
v_lshlrev_b32_e32 v2, 24, v3
s_delay_alu instid0(VALU_DEP_1)
v_or3_b32 v0, v0, v1, v2
global_store_b32 v4, v0, s[10:11]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bytePermKernel | 569 | 739 | stackv2-00000-of-00015 |
// Demangled: clzKernel(int*, int*)
Function : _Z9clzKernelPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?trans1;
FLO.U32 R0, R2 &req={3} &wr=0x0 ?trans2;
IADD3 R7, PT, PT, -R0, 0x1f, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: clzKernel(int*, int*)
_Z9clzKernelPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_clz_i32_u32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_min_u32_e32 v1, 32, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| clzKernel | 370 | 178 | stackv2-00000-of-00015 |
// Demangled: ffsKernel(int*, int*)
Function : _Z9ffsKernelPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?trans1;
BREV R0, R2 &req={3} &wr=0x0 ?trans2;
FLO.U32.SH R0, R0 &req={0} &wr=0x0 ?trans2;
IADD3 R7, PT, PT, R0, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: ffsKernel(int*, int*)
_Z9ffsKernelPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_ctz_i32_b32_e32 v2, v1
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 1, v2
v_cndmask_b32_e32 v1, 0, v2, vcc_lo
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| ffsKernel | 389 | 238 | stackv2-00000-of-00015 |
// Demangled: popcKernel(unsigned int*, unsigned int*)
Function : _Z10popcKernelPjS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={2} ?trans1;
POPC R7, R2 &req={3} &wr=0x0 ?trans4;
STG.E desc[UR4][R4.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: popcKernel(unsigned int*, unsigned int*)
_Z10popcKernelPjS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_bcnt_u32_b32 v1, v1, 0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| popcKernel | 343 | 147 | stackv2-00000-of-00015 |
// Demangled: multiply_matrices(float*, float*, float*, int)
Function : _Z17multiply_matricesPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x364] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R25, SR_TID.X &wr=0x3 ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={2} ?trans1;
IMAD R3, R0, UR6, R3 &req={1} ?WAIT5_END_GROUP;
IADD3 R0, PT, PT, R25, UR4, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R2, R3, R0, !PT ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R2, 0x3e7, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R2, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R16, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R18, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R3, R3, R2, RZ &req={0} ?trans1;
IADD3 R25, PT, PT, R2, UR4, R25 ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R3.reuse, 0x2, RZ ?trans2;
IADD3 R11, PT, PT, R3.reuse, 0x1, RZ ?trans2;
IADD3 R31, PT, PT, R3.reuse, 0x3, RZ ?trans1;
IMAD.WIDE.U32 R4, R3.reuse, 0x4, R16 &req={2} ?trans1;
IADD3 R33, PT, PT, R3, 0x4, RZ ?trans2;
IADD3 R9, PT, PT, R0.reuse, R2, R2 ?trans1;
IMAD.WIDE.U32 R12, R13, 0x4, R16 ?trans2;
LDG.E R4, desc[UR6][R4.64] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R22, R0, 0x4, R18 &req={3} ?WAIT2_END_GROUP;
LDG.E R24, desc[UR6][R12.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE.U32 R10, R11, 0x4, R16 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R20, R25, 0x4, R18 ?trans1;
LDG.E R5, desc[UR6][R22.64] &wr=0x2 ?trans3;
IMAD.WIDE.U32 R30, R31, 0x4, R16.reuse ?trans1;
LDG.E R6, desc[UR6][R10.64] &rd=0x1 &wr=0x4 ?trans1;
LEA R13, R2.reuse, R0, 0x2 &req={0} ?trans2;
IMAD.WIDE.U32 R32, R33, 0x4, R16 ?trans1;
LDG.E R27, desc[UR6][R20.64] &wr=0x4 ?trans3;
IMAD R8, R2, 0x3, R0 ?trans1;
LDG.E R7, desc[UR6][R30.64] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R14, R9, 0x4, R18 ?trans1;
IADD3 R29, PT, PT, R3, 0x5, RZ ?WAIT2_END_GROUP;
LDG.E R26, desc[UR6][R32.64] &rd=0x0 &wr=0x3 ?trans1;
IMAD.WIDE.U32 R10, R8, 0x4, R18 &req={1} ?WAIT3_END_GROUP;
LDG.E R31, desc[UR6][R14.64] &rd=0x1 &wr=0x3 ?trans1;
IMAD R12, R2, 0x5, R0 ?trans1;
IADD3 R33, PT, PT, R3, 0x6, RZ &req={0} ?trans2;
LDG.E R30, desc[UR6][R10.64] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE.U32 R28, R29, 0x4, R16 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R13, 0x4, R18 &req={1} ?trans1;
IADD3 R37, PT, PT, R3, 0x7, RZ ?trans1;
LDG.E R28, desc[UR6][R28.64] &wr=0x5 ?trans2;
IMAD.WIDE.U32 R22, R33, 0x4, R16 ?trans2;
LDG.E R33, desc[UR6][R14.64] &rd=0x1 &wr=0x5 ?trans2;
IMAD R11, R2.reuse, 0x6, R0.reuse &req={0} ?trans2;
IMAD R10, R2, 0x7, R0 ?trans1;
LDG.E R22, desc[UR6][R22.64] &wr=0x5 ?trans1;
IMAD.WIDE.U32 R20, R11, 0x4, R18 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R12, 0x4, R18.reuse &req={1} ?trans1;
LDG.E R35, desc[UR6][R20.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R29, desc[UR6][R14.64] &rd=0x1 &wr=0x5 ?trans1;
IMAD.WIDE.U32 R20, R10, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R37, 0x4, R16 &req={1} ?trans2;
LDG.E R37, desc[UR6][R20.64] &wr=0x5 ?trans4;
LDG.E R32, desc[UR6][R14.64] &wr=0x5 ?trans1;
LEA R25, R2.reuse, R25, 0x3 ?trans2;
LEA R9, R2.reuse, R9, 0x3 ?trans2;
LEA R8, R2, R8, 0x3 ?WAIT2_END_GROUP;
LEA R13, R2.reuse, R13, 0x3 ?trans2;
LEA R12, R2.reuse, R12, 0x3 ?trans2;
LEA R11, R2.reuse, R11, 0x3 ?trans2;
LEA R10, R2, R10, 0x3 ?trans1;
FFMA R5, R4, R5, RZ &req={2} ?WAIT4_END_GROUP;
FFMA R5, R6, R27, R5 &req={4} ?WAIT4_END_GROUP;
FFMA R24, R24, R31, R5 &req={3} ?WAIT4_END_GROUP;
FFMA R7, R7, R30, R24 &req={5} ?trans1;
HFMA2 R6, -RZ, RZ, 0, 8.94069671630859375e-07 ?WAIT3_END_GROUP;
FFMA R7, R26, R33, R7 ?trans1;
LEA R33, R2, R0, 0x3 ?trans2;
IADD3 R4, PT, PT, R3, 0xb, RZ ?trans1;
FFMA R7, R28, R29, R7 ?WAIT4_END_GROUP;
FFMA R7, R22, R35, R7 ?WAIT4_END_GROUP;
FFMA R7, R32, R37, R7 ?WAIT7_END_GROUP;
IADD3 R35, PT, PT, R4.reuse, -0x3, RZ ?trans1;
IMAD.WIDE.U32 R22, R33, 0x4, R18 ?trans1;
IADD3 R15, PT, PT, R4, -0x2, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R34, R35, 0x4, R16 ?trans1;
LDG.E R32, desc[UR6][R22.64] &rd=0x0 &wr=0x2 ?trans3;
IMAD.WIDE.U32 R20, R25, 0x4, R18 ?trans2;
LDG.E R34, desc[UR6][R34.64] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R14, R15, 0x4, R16.reuse ?trans2;
LDG.E R24, desc[UR6][R20.64] &wr=0x3 ?trans4;
LDG.E R31, desc[UR6][R14.64] &rd=0x1 &wr=0x3 ?trans1;
IADD3 R5, PT, PT, R4.reuse, -0x1, RZ ?trans1;
IMAD.WIDE.U32 R28, R4.reuse, 0x4, R16 ?trans1;
IADD3 R23, PT, PT, R4, 0x1, RZ &req={0} ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R26, R9, 0x4, R18 ?trans2;
LDG.E R28, desc[UR6][R28.64] &wr=0x4 ?trans2;
IMAD.WIDE.U32 R14, R5, 0x4, R16 &req={1} ?trans2;
LDG.E R26, desc[UR6][R26.64] &wr=0x5 ?trans2;
IMAD.WIDE.U32 R20, R8, 0x4, R18 ?trans2;
LDG.E R30, desc[UR6][R14.64] &rd=0x0 &wr=0x5 ?trans1;
IADD3 R35, PT, PT, R4, 0x2, RZ ?trans1;
IMAD.WIDE.U32 R22, R23, 0x4, R16 ?WAIT2_END_GROUP;
LDG.E R29, desc[UR6][R20.64] &rd=0x1 &wr=0x4 ?trans1;
IADD3 R37, PT, PT, R4, 0x3, RZ ?WAIT3_END_GROUP;
LDG.E R27, desc[UR6][R22.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE.U32 R14, R13, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R20, R12, 0x4, R18 &req={1} ?trans2;
LDG.E R15, desc[UR6][R14.64] &wr=0x4 ?trans2;
IMAD.WIDE.U32 R22, R35, 0x4, R16 ?trans2;
LDG.E R5, desc[UR6][R20.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R14, desc[UR6][R22.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE.U32 R20, R11, 0x4, R18 &req={0} ?trans1;
IADD3 R35, PT, PT, R4, 0x5, RZ ?WAIT2_END_GROUP;
LEA R33, R2, R33, 0x3 ?trans1;
IMAD.WIDE.U32 R22, R10, 0x4, R18 &req={1} ?WAIT4_END_GROUP;
FFMA R32, R34, R32, R7 &req={2} ?trans2;
LDG.E R7, desc[UR6][R20.64] &rd=0x0 &wr=0x2 ?trans2;
FFMA R24, R31, R24, R32 &req={3} ?trans2;
LDG.E R32, desc[UR6][R22.64] &rd=0x1 &wr=0x3 ?trans1;
IMAD.WIDE.U32 R20, R37, 0x4, R16 &req={0} ?trans1;
IADD3 R37, PT, PT, R4, 0x4, RZ ?WAIT4_END_GROUP;
LDG.E R31, desc[UR6][R20.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD.WIDE.U32 R22, R35, 0x4, R16 &req={1} ?WAIT6_END_GROUP;
LDG.E R22, desc[UR6][R22.64] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R20, R37, 0x4, R16 &req={0} ?WAIT5_END_GROUP;
LDG.E R34, desc[UR6][R20.64] &rd=0x0 &wr=0x3 ?trans2;
IMAD.WIDE.U32 R20, R33, 0x4, R18 &req={0} ?WAIT5_END_GROUP;
LDG.E R23, desc[UR6][R20.64] &rd=0x0 &wr=0x3 ?trans1;
FFMA R35, R30, R26, R24 &req={5} ?WAIT4_END_GROUP;
FFMA R28, R28, R29, R35 &req={4} ?trans1;
IADD3 R29, PT, PT, R4, 0x6, RZ ?trans2;
LEA R25, R2.reuse, R25, 0x3 ?trans1;
FFMA R15, R27, R15, R28 ?trans1;
LEA R24, R2, R9, 0x3 ?trans2;
IADD3 R35, PT, PT, R4.reuse, 0x7, RZ ?trans2;
IADD3 R9, PT, PT, R4, 0x8, RZ ?trans1;
IMAD.WIDE.U32 R26, R29, 0x4, R16 ?WAIT4_END_GROUP;
FFMA R30, R14, R5, R15 ?trans1;
LEA R5, R2.reuse, R8, 0x3 ?trans1;
IMAD.WIDE.U32 R28, R25, 0x4, R18 ?trans1;
LEA R13, R2, R13, 0x3 ?trans1;
LDG.E R26, desc[UR6][R26.64] &wr=0x4 ?trans2;
IMAD.WIDE.U32 R20, R35, 0x4, R16 &req={0} ?trans1;
IADD3 R35, PT, PT, R4, 0x9, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R8, R9, 0x4, R16 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R24, 0x4, R18 ?trans1;
LDG.E R27, desc[UR6][R28.64] &wr=0x4 ?trans1;
IADD3 R37, PT, PT, R4, 0xb, RZ ?trans2;
LEA R12, R2, R12, 0x3 ?trans1;
LDG.E R29, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R28, desc[UR6][R20.64] &rd=0x1 &wr=0x5 ?trans1;
IMAD.WIDE.U32 R8, R35, 0x4, R16 &req={0} ?trans1;
IADD3 R35, PT, PT, R4, 0xa, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R20, R5, 0x4, R18 &req={1} ?trans1;
LEA R11, R2.reuse, R11, 0x3 ?trans2;
LEA R10, R2, R10, 0x3 ?trans1;
FFMA R31, R31, R7, R30 &req={2} ?trans2;
LDG.E R7, desc[UR6][R14.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R30, desc[UR6][R20.64] &rd=0x1 &wr=0x2 ?trans1;
IMAD.WIDE.U32 R14, R13, 0x4, R18 &req={0} ?WAIT4_END_GROUP;
FFMA R34, R34, R32, R31 &req={3} ?trans2;
LDG.E R31, desc[UR6][R8.64] &rd=0x0 &wr=0x3 ?trans1;
IMAD.WIDE.U32 R20, R12, 0x4, R18 &req={1} ?WAIT3_END_GROUP;
LDG.E R32, desc[UR6][R14.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R20, desc[UR6][R20.64] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R8, R35, 0x4, R16 &req={0} ?trans1;
IADD3 R35, PT, PT, R4, 0xc, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R14, R37, 0x4, R16 &req={1} ?WAIT4_END_GROUP;
FFMA R22, R22, R23, R34 ?trans2;
LDG.E R23, desc[UR6][R8.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E R34, desc[UR6][R14.64] &rd=0x1 &wr=0x3 ?trans1;
IMAD.WIDE.U32 R8, R35, 0x4, R16 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R11, 0x4, R18.reuse &req={1} ?trans1;
LDG.E R36, desc[UR6][R8.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E R35, desc[UR6][R14.64] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R8, R10, 0x4, R18 &req={0} ?WAIT5_END_GROUP;
LDG.E R37, desc[UR6][R8.64] &rd=0x0 &wr=0x3 ?trans1;
FFMA R27, R26, R27, R22 &req={4} ?trans1;
IADD3 R6, PT, PT, R6, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R6, 0x3ef, PT ?trans1;
LEA R25, R2.reuse, R25, 0x3 ?trans2;
LEA R9, R2.reuse, R24, 0x3 &req={0} ?trans2;
LEA R8, R2.reuse, R5, 0x3 ?trans2;
LEA R13, R2.reuse, R13, 0x3 ?trans2;
LEA R12, R2.reuse, R12, 0x3 ?trans2;
LEA R11, R2, R11, 0x3 ?WAIT2_END_GROUP;
LEA R10, R2.reuse, R10, 0x3 ?trans2;
LEA R33, R2, R33, 0x3 ?trans2;
IADD3 R4, PT, PT, R4, 0x10, RZ ?trans1;
FFMA R28, R28, R7, R27 &req={5} ?WAIT4_END_GROUP;
FFMA R28, R29, R30, R28 &req={2} ?WAIT4_END_GROUP;
FFMA R28, R31, R32, R28 &req={3} ?WAIT4_END_GROUP;
FFMA R23, R23, R20, R28 ?WAIT4_END_GROUP;
FFMA R23, R34, R35, R23 ?WAIT4_END_GROUP;
FFMA R7, R36, R37, R23 ?trans1;
@P0 BRA 0x520 ?trans6;
LDC.64 R4, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R0, R3, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xca0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: multiply_matrices(float*, float*, float*, int)
_Z17multiply_matricesPfS_S_i:
s_load_b32 s2, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v1, v2, v0
v_cmpx_gt_u32_e32 0x3e8, v1
s_cbranch_execz .LBB0_4
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v5, 0
s_mov_b32 s3, 0
v_mov_b32_e32 v3, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v6, v2, s2
v_mov_b32_e32 v2, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v1, s3, v6
s_add_i32 s3, s3, 1
s_cmpk_eq_i32 s3, 0x3e8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v1, v[7:8], off
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v1, v4
s_cbranch_scc0 .LBB0_2
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| multiply_matrices | 5,673 | 1,019 | stackv2-00000-of-00015 |
// Demangled: multiply_matrices_shared_blocks(float*, float*, float*, int)
Function : _Z31multiply_matrices_shared_blocksPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R6, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x1 ?trans6;
S2UR UR6, SR_CgaCtaId &wr=0x2 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans1;
S2R R4, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x360] &wr=0x3 ?trans1;
S2R R20, SR_TID.X &wr=0x4 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x0 ?trans3;
LDC R5, c[0x0][0x398] &wr=0x4 ?trans1;
S2R R7, SR_CTAID.X &wr=0x3 ?trans1;
LDCU.128 UR12, c[0x0][0x380] &wr=0x0 ?trans6;
LDC.64 R24, c[0x0][0x390] &wr=0x5 ?trans1;
IMAD R0, R4, UR4, R6 &req={1} ?trans1;
UMOV UR4, 0x400 ?trans1;
IMAD R22, R6, R5, R20 &req={4} ?WAIT2_END_GROUP;
IMAD R2, R7.reuse, UR5, R20 &req={3} ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x400, URZ ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={2} ?trans1;
SHF.R.S32.HI R23, RZ, 0x1f, R22 ?trans1;
IMAD R3, R0, R5.reuse, R2 ?trans1;
ULEA UR5, UR6, UR5, 0x18 ?trans1;
IMAD R2, R4, R5, RZ ?trans1;
SHF.L.U32 R4, R7, 0x4, RZ ?trans1;
IMAD.WIDE.U32 R24, R3, 0x4, R24 &req={5} ?trans1;
LEA R21, R6, UR4, 0x6 ?trans2;
LEA R7, R20, UR5, 0x2 ?trans1;
MOV R3, RZ ?trans1;
SHF.L.U32 R2, R2, 0x4, RZ ?WAIT2_END_GROUP;
LEA R0, R5, R4, 0x4 ?trans2;
LEA R20, R20, R21, 0x2 ?trans2;
LEA R6, R6, R7, 0x6 &req={0} ?WAIT7_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R2 ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R4 ?trans1;
MOV R8, R2 ?trans1;
MOV R10, R4 ?WAIT4_END_GROUP;
IADD.64 R8, R22.reuse, R8 ?trans2;
IADD.64 R10, R22, R10 ?WAIT3_END_GROUP;
LEA R26, P0, R8, UR12, 0x2 ?trans2;
LEA R14, P1, R10, UR14, 0x2 ?trans2;
LEA.HI.X R27, R8, UR13, R9, 0x2, P0 ?trans2;
LEA.HI.X R15, R10, UR15, R11, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R29, desc[UR8][R26.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR8][R14.64] &wr=0x3 ?trans4;
STS [R20], R29 &req={2} ?trans4;
STS [R6], R15 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R12, [R7] ?trans4;
LDS.128 R16, [R21] &req={0} &wr=0x0 ?trans4;
LDS R31, [R7+0x40] &wr=0x1 ?trans4;
LDS R30, [R7+0x80] &wr=0x2 ?trans4;
LDS R34, [R7+0xc0] &wr=0x3 ?trans4;
LDS R35, [R7+0x100] ?trans4;
LDS.128 R8, [R21+0x10] &wr=0x4 ?trans4;
LDS R32, [R7+0x140] &wr=0x5 ?trans4;
LDS R29, [R7+0x180] &wr=0x5 ?trans4;
LDS R28, [R7+0x1c0] &wr=0x5 ?trans4;
LDS R33, [R7+0x280] ?trans1;
FFMA R12, R16, R12, R13 &req={0} ?WAIT4_END_GROUP;
FFMA R17, R31, R17, R12 &req={1} ?trans2;
LDS R31, [R7+0x200] ?trans2;
FFMA R17, R30, R18, R17 &req={2} ?trans2;
LDS.128 R12, [R21+0x20] &wr=0x0 ?trans2;
FFMA R17, R34, R19, R17 &req={3} ?trans2;
LDS R30, [R7+0x240] &wr=0x1 ?trans2;
FFMA R17, R8, R35, R17 &req={4} ?WAIT2_END_GROUP;
LDS R8, [R7+0x2c0] &wr=0x2 ?trans2;
FFMA R32, R32, R9, R17 &req={5} ?trans2;
LDS R35, [R7+0x300] ?trans2;
FFMA R9, R29, R10, R32 ?trans2;
LDS.128 R16, [R21+0x30] &wr=0x3 ?trans2;
FFMA R9, R28, R11, R9 ?WAIT2_END_GROUP;
LDS R32, [R7+0x340] &wr=0x4 ?trans4;
LDS R29, [R7+0x380] &wr=0x5 ?trans4;
LDS R10, [R7+0x3c0] &wr=0x5 ?trans1;
FFMA R9, R12, R31, R9 &req={0} ?WAIT4_END_GROUP;
FFMA R30, R30, R13, R9 &req={1} ?trans1;
SHF.R.S32.HI R9, RZ, 0x1f, R0 ?WAIT3_END_GROUP;
FFMA R33, R33, R14, R30 ?WAIT4_END_GROUP;
FFMA R15, R8, R15, R33 &req={2} ?trans1;
MOV R8, R0 ?WAIT5_END_GROUP;
IADD.64 R8, R22, R8 ?trans2;
FFMA R15, R16, R35, R15 &req={3} ?WAIT3_END_GROUP;
LEA R12, P0, R8, UR14, 0x2 ?trans1;
FFMA R32, R32, R17, R15 &req={4} ?WAIT3_END_GROUP;
LEA.HI.X R13, R8, UR15, R9, 0x2, P0 ?trans1;
FFMA R29, R29, R18, R32 &req={5} ?WAIT4_END_GROUP;
FFMA R29, R10, R19, R29 ?WAIT5_END_GROUP;
STG.E desc[UR8][R24.64], R29 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDG.E R27, desc[UR8][R26.64+0x40] &wr=0x2 ?trans4;
LDG.E R13, desc[UR8][R12.64] &wr=0x3 ?trans1;
IADD3 R3, PT, PT, R3, 0x2, RZ ?WAIT2_END_GROUP;
LEA R4, R5.reuse, R4, 0x5 ?trans2;
IADD3 R2, PT, PT, R2, 0x20, RZ ?trans2;
LEA R0, R5, R0, 0x5 ?trans1;
ISETP.NE.AND P0, PT, R3, 0x3e, PT ?trans1;
STS [R20], R27 &req={2} ?trans4;
STS [R6], R13 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R14, [R7] ?trans4;
LDS.128 R16, [R21] &wr=0x0 ?trans4;
LDS R15, [R7+0x40] &wr=0x1 ?trans4;
LDS R28, [R7+0x80] &wr=0x2 ?trans4;
LDS R32, [R7+0xc0] &wr=0x3 ?trans4;
LDS R31, [R7+0x100] ?trans4;
LDS.128 R8, [R21+0x10] &wr=0x4 ?trans4;
LDS R30, [R7+0x140] &wr=0x5 ?trans4;
LDS R27, [R7+0x180] &wr=0x5 ?trans4;
LDS R26, [R7+0x1c0] &wr=0x5 ?trans4;
LDS R33, [R7+0x280] ?trans1;
FFMA R14, R16, R14, R29 &req={0} ?WAIT3_END_GROUP;
LDS R29, [R7+0x200] ?trans1;
FFMA R17, R15, R17, R14 &req={1} ?WAIT3_END_GROUP;
LDS.128 R12, [R21+0x20] &wr=0x0 ?trans1;
FFMA R17, R28, R18, R17 &req={2} ?WAIT3_END_GROUP;
LDS R28, [R7+0x240] &wr=0x1 ?trans1;
FFMA R17, R32, R19, R17 &req={3} ?WAIT4_END_GROUP;
FFMA R17, R8, R31, R17 &req={4} ?trans2;
LDS R8, [R7+0x2c0] &wr=0x2 ?trans2;
FFMA R32, R30, R9, R17 &req={5} ?trans2;
LDS R9, [R7+0x300] ?trans2;
FFMA R31, R27, R10, R32 ?trans2;
LDS.128 R16, [R21+0x30] &wr=0x3 ?trans2;
FFMA R11, R26, R11, R31 ?WAIT2_END_GROUP;
LDS R30, [R7+0x340] &wr=0x4 ?trans4;
LDS R27, [R7+0x380] &wr=0x5 ?trans4;
LDS R10, [R7+0x3c0] &wr=0x5 ?trans1;
FFMA R11, R12, R29, R11 &req={0} ?WAIT4_END_GROUP;
FFMA R28, R28, R13, R11 &req={1} ?WAIT4_END_GROUP;
FFMA R33, R33, R14, R28 ?WAIT4_END_GROUP;
FFMA R15, R8, R15, R33 &req={2} ?WAIT4_END_GROUP;
FFMA R9, R16, R9, R15 &req={3} ?WAIT4_END_GROUP;
FFMA R30, R30, R17, R9 &req={4} ?WAIT4_END_GROUP;
FFMA R27, R27, R18, R30 &req={5} ?WAIT4_END_GROUP;
FFMA R13, R10, R19, R27 ?WAIT5_END_GROUP;
STG.E desc[UR8][R24.64], R13 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x200 ?trans5;
EXIT ?trans5;
BRA 0x8c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: multiply_matrices_shared_blocks(float*, float*, float*, int)
_Z31multiply_matrices_shared_blocksPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v4, 6, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s3, 16
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s3, s14, s3
v_mad_u64_u32 v[6:7], null, s15, s8, v[1:2]
v_mov_b32_e32 v1, 0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v7, 2, v0
s_mul_i32 s15, s15, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mul_lo_u32 v8, v6, s2
v_add_nc_u32_e32 v5, 0x400, v7
v_add_nc_u32_e32 v6, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v5, v4
v_add3_u32 v0, s3, v0, v8
v_add_co_u32 v8, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s3, 0
v_add_co_u32 v2, vcc_lo, s0, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v12, vcc_lo
s_lshl_b32 s0, s14, 4
s_lshl_b32 s1, s15, 4
.LBB1_1:
s_lshl_b32 s4, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s5, s4, s2
s_add_i32 s4, s4, s1
s_add_i32 s6, s5, s0
s_ashr_i32 s5, s4, 31
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v8, s4
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v9, vcc_lo
s_lshl_b64 s[4:5], s[6:7], 2
v_add_co_u32 v13, vcc_lo, v0, s4
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v10, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s4, 0
s_waitcnt vmcnt(1)
ds_store_b32 v6, v12
s_waitcnt vmcnt(0)
ds_store_b32 v7, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_2:
v_add_nc_u32_e32 v12, s4, v4
s_add_i32 s4, s4, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s4, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v12, v13
s_cbranch_scc0 .LBB1_2
s_add_i32 s3, s3, 1
global_store_b32 v[2:3], v1, off
s_cmp_eq_u32 s3, 62
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_1
s_endpgm
| multiply_matrices_shared_blocks | 3,406 | 1,469 | stackv2-00000-of-00015 |
// Demangled: histsPileUp(unsigned int*)
Function : _Z11histsPileUpPj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R16, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x80] &wr=0x2 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x100] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x180] &wr=0x3 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x200] &wr=0x3 ?trans4;
LDG.E R35, desc[UR4][R2.64+0x280] &wr=0x4 ?trans4;
LDG.E R32, desc[UR4][R2.64+0x300] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x380] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x400] &wr=0x5 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x480] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R2.64+0x500] &wr=0x5 ?trans4;
LDG.E R6, desc[UR4][R2.64+0x580] &wr=0x5 ?trans4;
LDG.E R5, desc[UR4][R2.64+0x600] &wr=0x5 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x680] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x700] &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R2.64+0x780] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x800] &wr=0x5 ?trans4;
LDG.E R30, desc[UR4][R2.64+0x880] &wr=0x5 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x900] &wr=0x5 ?trans4;
LDG.E R28, desc[UR4][R2.64+0x980] &wr=0x5 ?trans4;
LDG.E R31, desc[UR4][R2.64+0xa00] &wr=0x5 ?trans4;
LDG.E R26, desc[UR4][R2.64+0xa80] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R2.64+0xb00] &wr=0x5 ?trans4;
LDG.E R24, desc[UR4][R2.64+0xb80] &wr=0x5 ?trans4;
LDG.E R27, desc[UR4][R2.64+0xc00] &wr=0x5 ?trans4;
LDG.E R9, desc[UR4][R2.64+0xc80] &wr=0x5 ?trans4;
LDG.E R12, desc[UR4][R2.64+0xd00] &wr=0x5 ?trans4;
LDG.E R7, desc[UR4][R2.64+0xd80] &wr=0x5 ?trans4;
LDG.E R8, desc[UR4][R2.64+0xe00] &wr=0x5 ?trans4;
LDG.E R22, desc[UR4][R2.64+0xe80] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R2.64+0xf00] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x1000] &wr=0x5 ?trans1;
IADD3 R16, PT, PT, R18, R16, R19 &req={2} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x1080] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x1200] &wr=0x2 ?trans1;
IADD3 R16, PT, PT, R20, R16, R21 &req={3} ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0xf80] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x1100] &wr=0x2 ?trans1;
IADD3 R16, PT, PT, R32, R16, R35 &req={4} ?WAIT3_END_GROUP;
LDG.E R35, desc[UR4][R2.64+0x7d80] &wr=0x4 ?trans1;
IADD3 R14, PT, PT, R17, R16, R14 &req={5} ?WAIT3_END_GROUP;
LDG.E R16, desc[UR4][R2.64+0x1180] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x1300] &wr=0x4 ?trans1;
IADD3 R14, PT, PT, R15, R14, R0 ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x1280] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R2.64+0x1500] &wr=0x4 ?trans1;
IADD3 R14, PT, PT, R5, R14, R6 ?WAIT3_END_GROUP;
LDG.E R5, desc[UR4][R2.64+0x1380] &wr=0x4 ?trans4;
LDG.E R6, desc[UR4][R2.64+0x1400] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R13, R14, R4 ?WAIT3_END_GROUP;
LDG.E R4, desc[UR4][R2.64+0x1480] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x1580] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x1600] &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R11, R32, R10 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x1700] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R33, R10, R30 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR4][R2.64+0x1680] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x1800] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R31, R30, R28 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR4][R2.64+0x1780] &wr=0x4 ?trans4;
LDG.E R31, desc[UR4][R2.64+0x1900] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R29, R28, R26 ?WAIT3_END_GROUP;
LDG.E R28, desc[UR4][R2.64+0x1880] &wr=0x4 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x1a00] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R27, R26, R24 ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64+0x1980] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R2.64+0x1d00] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R12, R24, R9 ?WAIT3_END_GROUP;
LDG.E R9, desc[UR4][R2.64+0x1a80] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x1b00] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R8, R24, R7 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R2.64+0x1b80] &wr=0x4 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x1c00] &wr=0x4 ?trans1;
IADD3 R22, PT, PT, R25, R24, R22 ?WAIT3_END_GROUP;
LDG.E R24, desc[UR4][R2.64+0x1c80] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R2.64+0x1e00] &wr=0x4 ?trans1;
IADD3 R20, PT, PT, R23, R22, R20 &req={3} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R2.64+0x1d80] &wr=0x3 ?trans1;
IADD3 R18, PT, PT, R21, R20, R18 &req={2} ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0x1e80] &wr=0x2 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x1f00] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x2000] &wr=0x2 ?trans1;
IADD3 R16, PT, PT, R19, R18, R16 &req={5} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x1f80] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x2100] &wr=0x5 ?trans1;
IADD3 R16, PT, PT, R17, R16, R0 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x2080] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x2300] &wr=0x4 ?trans1;
IADD3 R16, PT, PT, R6, R16, R5 ?WAIT3_END_GROUP;
LDG.E R5, desc[UR4][R2.64+0x2180] &wr=0x4 ?trans1;
IADD3 R15, PT, PT, R15, R16, R4 ?WAIT3_END_GROUP;
LDG.E R6, desc[UR4][R2.64+0x2200] &wr=0x4 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x2280] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R14, R15, R13 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R2.64+0x2380] &wr=0x4 ?trans4;
LDG.E R16, desc[UR4][R2.64+0x2400] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x2480] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x2500] &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R11, R32, R10 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x2600] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R33, R10, R30 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR4][R2.64+0x2580] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R31, R30, R28 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR4][R2.64+0x2680] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x2700] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R29, R28, R26 ?WAIT3_END_GROUP;
LDG.E R28, desc[UR4][R2.64+0x2780] &wr=0x4 ?trans4;
LDG.E R31, desc[UR4][R2.64+0x2800] &wr=0x4 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x2b00] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R12, R26, R9 ?WAIT3_END_GROUP;
LDG.E R9, desc[UR4][R2.64+0x2880] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x2900] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R8, R26, R7 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R2.64+0x2980] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R27, R26, R24 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x2a00] &wr=0x4 ?trans4;
LDG.E R26, desc[UR4][R2.64+0x2a80] &wr=0x4 ?trans4;
LDG.E R27, desc[UR4][R2.64+0x2c00] &wr=0x4 ?trans1;
IADD3 R22, PT, PT, R25, R24, R22 &req={3} ?WAIT3_END_GROUP;
LDG.E R24, desc[UR4][R2.64+0x2b80] &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R2.64+0x2d00] &wr=0x3 ?trans1;
IADD3 R20, PT, PT, R23, R22, R20 &req={2} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R2.64+0x2c80] &wr=0x2 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x2e00] &wr=0x2 ?trans1;
IADD3 R18, PT, PT, R21, R20, R18 &req={5} ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0x2d80] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x2f00] &wr=0x5 ?trans1;
IADD3 R18, PT, PT, R19, R18, R0 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x2e80] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x3100] &wr=0x4 ?trans1;
IADD3 R18, PT, PT, R6, R18, R5 ?WAIT3_END_GROUP;
LDG.E R5, desc[UR4][R2.64+0x2f80] &wr=0x4 ?trans1;
IADD3 R17, PT, PT, R17, R18, R4 ?WAIT3_END_GROUP;
LDG.E R6, desc[UR4][R2.64+0x3000] &wr=0x4 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x3080] &wr=0x4 ?trans1;
IADD3 R15, PT, PT, R16, R17, R15 ?WAIT3_END_GROUP;
LDG.E R17, desc[UR4][R2.64+0x3180] &wr=0x4 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x3200] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R14, R15, R13 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R2.64+0x3280] &wr=0x4 ?trans4;
LDG.E R16, desc[UR4][R2.64+0x3300] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x3380] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x3400] &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R11, R32, R10 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x3500] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R33, R10, R30 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR4][R2.64+0x3480] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R31, R30, R28 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR4][R2.64+0x3580] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x3600] &wr=0x4 ?trans4;
LDG.E R31, desc[UR4][R2.64+0x3900] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R12, R28, R9 ?WAIT3_END_GROUP;
LDG.E R9, desc[UR4][R2.64+0x3680] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x3700] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R8, R28, R7 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R2.64+0x3780] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R29, R28, R26 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x3800] &wr=0x4 ?trans4;
LDG.E R28, desc[UR4][R2.64+0x3880] &wr=0x4 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x3a00] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R27, R26, R24 &req={3} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64+0x3980] &wr=0x3 ?trans4;
LDG.E R27, desc[UR4][R2.64+0x3b00] &wr=0x3 ?trans1;
IADD3 R22, PT, PT, R25, R24, R22 &req={2} ?WAIT3_END_GROUP;
LDG.E R24, desc[UR4][R2.64+0x3a80] &wr=0x2 ?trans4;
LDG.E R25, desc[UR4][R2.64+0x3c00] &wr=0x2 ?trans1;
IADD3 R20, PT, PT, R23, R22, R20 &req={5} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R2.64+0x3b80] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x3d00] &wr=0x5 ?trans1;
IADD3 R20, PT, PT, R21, R20, R0 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x3c80] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x3f00] &wr=0x4 ?trans1;
IADD3 R20, PT, PT, R6, R20, R5 ?WAIT3_END_GROUP;
LDG.E R5, desc[UR4][R2.64+0x3d80] &wr=0x4 ?trans1;
IADD3 R19, PT, PT, R19, R20, R4 ?WAIT3_END_GROUP;
LDG.E R6, desc[UR4][R2.64+0x3e00] &wr=0x4 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x3e80] &wr=0x4 ?trans1;
IADD3 R17, PT, PT, R18, R19, R17 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0x3f80] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x4000] &wr=0x4 ?trans1;
IADD3 R15, PT, PT, R16, R17, R15 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x4080] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x4100] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R14, R15, R13 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR4][R2.64+0x4180] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R2.64+0x4200] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x4280] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x4300] &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R11, R32, R10 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x4400] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R33, R10, R30 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR4][R2.64+0x4380] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x5100] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R12, R30, R9 ?WAIT3_END_GROUP;
LDG.E R12, desc[UR4][R2.64+0x4480] &wr=0x4 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x4500] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R8, R30, R7 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x4580] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R31, R30, R28 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R2.64+0x4600] &wr=0x4 ?trans4;
LDG.E R28, desc[UR4][R2.64+0x4680] &wr=0x4 ?trans4;
LDG.E R31, desc[UR4][R2.64+0x4700] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R29, R30, R26 &req={3} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64+0x4780] &wr=0x3 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x4800] &wr=0x3 ?trans1;
IADD3 R30, PT, PT, R27, R30, R24 &req={2} ?WAIT3_END_GROUP;
LDG.E R27, desc[UR4][R2.64+0x4880] &wr=0x2 ?trans4;
LDG.E R24, desc[UR4][R2.64+0x4900] &wr=0x2 ?trans1;
IADD3 R30, PT, PT, R25, R30, R22 &req={5} ?WAIT3_END_GROUP;
LDG.E R25, desc[UR4][R2.64+0x4980] &wr=0x5 ?trans4;
LDG.E R22, desc[UR4][R2.64+0x4a00] &wr=0x5 ?trans1;
IADD3 R30, PT, PT, R23, R30, R0 &req={4} ?WAIT3_END_GROUP;
LDG.E R23, desc[UR4][R2.64+0x4a80] &wr=0x4 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x4b00] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R6, R30, R5 ?WAIT3_END_GROUP;
LDG.E R6, desc[UR4][R2.64+0x4b80] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R21, R30, R4 ?WAIT3_END_GROUP;
LDG.E R5, desc[UR4][R2.64+0x4c00] &wr=0x4 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x4c80] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R19, R30, R20 ?WAIT3_END_GROUP;
LDG.E R21, desc[UR4][R2.64+0x4d00] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x4d80] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R17, R30, R18 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0x4e00] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x4e80] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R15, R30, R16 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x4f00] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R2.64+0x4f80] &wr=0x4 ?trans4;
LDG.E R16, desc[UR4][R2.64+0x5000] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R13, R30, R14 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR4][R2.64+0x5080] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x5180] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x5200] &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R11, R32, R10 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x5500] &wr=0x4 ?trans1;
IADD3 R12, PT, PT, R9, R10, R12 ?WAIT3_END_GROUP;
LDG.E R9, desc[UR4][R2.64+0x5280] &wr=0x4 ?trans4;
LDG.E R10, desc[UR4][R2.64+0x5300] &wr=0x4 ?trans1;
IADD3 R12, PT, PT, R7, R12, R8 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x5380] &wr=0x4 ?trans4;
LDG.E R7, desc[UR4][R2.64+0x5400] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R31, R12, R28 ?WAIT3_END_GROUP;
LDG.E R12, desc[UR4][R2.64+0x5480] &wr=0x4 ?trans4;
LDG.E R31, desc[UR4][R2.64+0x5e80] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R29, R28, R26 &req={3} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64+0x5580] &wr=0x3 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x5600] &wr=0x3 ?trans1;
IADD3 R28, PT, PT, R24, R28, R27 &req={2} ?WAIT3_END_GROUP;
LDG.E R24, desc[UR4][R2.64+0x5680] &wr=0x2 ?trans4;
LDG.E R27, desc[UR4][R2.64+0x5700] &wr=0x2 ?trans1;
IADD3 R28, PT, PT, R22, R28, R25 &req={5} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R2.64+0x5780] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R2.64+0x5800] &wr=0x5 ?trans1;
IADD3 R28, PT, PT, R0, R28, R23 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x5880] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x5900] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R5, R28, R6 ?WAIT3_END_GROUP;
LDG.E R6, desc[UR4][R2.64+0x5980] &wr=0x4 ?trans4;
LDG.E R5, desc[UR4][R2.64+0x5a00] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R21, R28, R4 ?WAIT3_END_GROUP;
LDG.E R21, desc[UR4][R2.64+0x5a80] &wr=0x4 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x5b00] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R20, R28, R19 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0x5b80] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x5c00] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R18, R28, R17 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x5c80] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x5d00] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R16, R28, R15 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR4][R2.64+0x5d80] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R33, R28, R30 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R2.64+0x5e00] &wr=0x4 ?trans4;
LDG.E R28, desc[UR4][R2.64+0x5f00] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R14, R30, R13 ?WAIT3_END_GROUP;
LDG.E R33, desc[UR4][R2.64+0x5f80] &wr=0x4 ?trans4;
LDG.E R30, desc[UR4][R2.64+0x6000] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x6080] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x6100] &wr=0x4 ?trans1;
IADD3 R9, PT, PT, R10, R32, R9 ?WAIT3_END_GROUP;
LDG.E R10, desc[UR4][R2.64+0x6280] &wr=0x4 ?trans1;
IADD3 R9, PT, PT, R7, R9, R8 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R2.64+0x6180] &wr=0x4 ?trans1;
IADD3 R11, PT, PT, R11, R9, R12 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x6200] &wr=0x4 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x6300] &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x6380] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R29, R11, R26 &req={3} ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x6400] &wr=0x3 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x6d00] &wr=0x3 ?trans1;
IADD3 R26, PT, PT, R27, R26, R24 &req={2} ?WAIT3_END_GROUP;
LDG.E R27, desc[UR4][R2.64+0x6480] &wr=0x2 ?trans4;
LDG.E R24, desc[UR4][R2.64+0x6500] &wr=0x2 ?trans1;
IADD3 R26, PT, PT, R25, R26, R22 &req={5} ?WAIT3_END_GROUP;
LDG.E R25, desc[UR4][R2.64+0x6580] &wr=0x5 ?trans4;
LDG.E R22, desc[UR4][R2.64+0x6600] &wr=0x5 ?trans1;
IADD3 R26, PT, PT, R23, R26, R0 &req={4} ?WAIT3_END_GROUP;
LDG.E R0, desc[UR4][R2.64+0x6680] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x6700] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R5, R26, R6 ?WAIT3_END_GROUP;
LDG.E R5, desc[UR4][R2.64+0x6780] &wr=0x4 ?trans4;
LDG.E R6, desc[UR4][R2.64+0x6800] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R4, R26, R21 ?WAIT3_END_GROUP;
LDG.E R4, desc[UR4][R2.64+0x6880] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x6900] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R19, R26, R20 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR4][R2.64+0x6980] &wr=0x4 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x6a00] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R17, R26, R18 ?WAIT3_END_GROUP;
LDG.E R17, desc[UR4][R2.64+0x6a80] &wr=0x4 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x6b00] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R15, R26, R16 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R2.64+0x6b80] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R28, R26, R31 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR4][R2.64+0x6c00] &wr=0x4 ?trans4;
LDG.E R26, desc[UR4][R2.64+0x6c80] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R30, R28, R33 ?WAIT3_END_GROUP;
LDG.E R28, desc[UR4][R2.64+0x6d80] &wr=0x4 ?trans4;
LDG.E R31, desc[UR4][R2.64+0x6e00] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R13, R30, R14 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR4][R2.64+0x6e80] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x6f00] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x6f80] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x7000] &wr=0x4 ?trans1;
IADD3 R7, PT, PT, R8, R32, R7 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR4][R2.64+0x7100] &wr=0x4 ?trans1;
IADD3 R9, PT, PT, R9, R7, R10 ?WAIT3_END_GROUP;
LDG.E R7, desc[UR4][R2.64+0x7080] &wr=0x4 ?trans4;
LDG.E R10, desc[UR4][R2.64+0x7200] &wr=0x4 ?trans1;
IADD3 R11, PT, PT, R11, R9, R12 &req={3} ?WAIT3_END_GROUP;
LDG.E R9, desc[UR4][R2.64+0x7180] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x7300] &wr=0x3 ?trans1;
IADD3 R24, PT, PT, R24, R11, R27 &req={2} ?WAIT3_END_GROUP;
LDG.E R11, desc[UR4][R2.64+0x7280] &wr=0x2 ?trans4;
LDG.E R27, desc[UR4][R2.64+0x7a80] &wr=0x2 ?trans1;
IADD3 R24, PT, PT, R22, R24, R25 &req={5} ?WAIT3_END_GROUP;
LDG.E R25, desc[UR4][R2.64+0x7380] &wr=0x5 ?trans4;
LDG.E R22, desc[UR4][R2.64+0x7400] &wr=0x5 ?trans1;
IADD3 R24, PT, PT, R23, R24, R0 &req={4} ?WAIT3_END_GROUP;
LDG.E R23, desc[UR4][R2.64+0x7480] &wr=0x4 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x7500] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R6, R24, R5 ?WAIT3_END_GROUP;
LDG.E R6, desc[UR4][R2.64+0x7580] &wr=0x4 ?trans4;
LDG.E R5, desc[UR4][R2.64+0x7600] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R21, R24, R4 ?WAIT3_END_GROUP;
LDG.E R21, desc[UR4][R2.64+0x7680] &wr=0x4 ?trans4;
LDG.E R4, desc[UR4][R2.64+0x7700] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R20, R24, R19 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R2.64+0x7780] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x7800] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R18, R24, R17 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x7880] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R2.64+0x7900] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R16, R24, R15 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR4][R2.64+0x7980] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R29, R24, R26 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R2.64+0x7a00] &wr=0x4 ?trans4;
LDG.E R24, desc[UR4][R2.64+0x7b00] &wr=0x4 ?trans1;
IADD3 R28, PT, PT, R31, R26, R28 ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64+0x7b80] &wr=0x4 ?trans4;
LDG.E R29, desc[UR4][R2.64+0x7c00] &wr=0x4 ?trans1;
IADD3 R30, PT, PT, R33, R28, R30 ?WAIT3_END_GROUP;
LDG.E R31, desc[UR4][R2.64+0x7c80] &wr=0x4 ?trans4;
LDG.E R28, desc[UR4][R2.64+0x7d00] &wr=0x4 ?trans1;
IADD3 R32, PT, PT, R14, R30, R13 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR4][R2.64+0x7e00] &wr=0x4 ?trans4;
LDG.E R33, desc[UR4][R2.64+0x7e80] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R2.64+0x7f00] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R2.64+0x7f80] &wr=0x4 ?trans1;
IADD3 R7, PT, PT, R8, R32, R7 ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R10, R7, R9 &req={3} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R12, R7, R11 &req={2} ?WAIT4_END_GROUP;
IADD3 R7, PT, PT, R22, R7, R25 &req={5} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, R7, R23 &req={4} ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R5, R0, R6 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R4, R0, R21 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R19, R0, R20 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R17, R0, R18 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R15, R0, R16 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R24, R0, R27 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R29, R0, R26 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R28, R0, R31 ?WAIT4_END_GROUP;
IADD3 R30, PT, PT, R30, R0, R35 ?WAIT4_END_GROUP;
IADD3 R14, PT, PT, R14, R30, R33 ?WAIT4_END_GROUP;
IADD3 R13, PT, PT, R14, R13, RZ ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 ?trans1;
EXIT ?trans5;
BRA 0x1870;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: histsPileUp(unsigned int*)
_Z11histsPileUpPj:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b64 s[0:1], 0x80
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v0, s[2:3]
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
.LBB2_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
s_add_u32 s0, s0, 0x80
s_addc_u32 s1, s1, 0
s_cmpk_eq_u32 s0, 0x8000
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
s_cbranch_scc0 .LBB2_1
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| histsPileUp | 12,745 | 385 | stackv2-00000-of-00015 |
// Demangled: setupExperiment(curandStateXORWOW*)
Function : _Z15setupExperimentP17curandStateXORWOW
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R8, SR_TID.X &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
HFMA2 R2, -RZ, RZ, 0.1748046875, -3.029296875 ?trans1;
MOV R3, 0x5efdb30c ?trans1;
HFMA2 R4, -RZ, RZ, 3.115234375, -0.127197265625 ?trans1;
MOV R5, 0xf8a42704 ?trans1;
HFMA2 R10, -RZ, RZ, -310, -36736 ?trans1;
MOV R11, 0x57fa2510 ?trans1;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0xe80 ?trans7;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R8, R9, UR6, R8 &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R8.reuse, RZ, PT ?trans1;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans1;
IMAD.WIDE R6, R8, 0x30, R6 &req={3} ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R6.64], R2 &req={2} &rd=0x1 ?trans4;
STG.E.64 desc[UR4][R6.64+0x8], R4 &rd=0x1 ?trans4;
STG.E.64 desc[UR4][R6.64+0x10], R10 &rd=0x1 ?trans1;
@!P0 BRA 0xe70 &req={0} ?trans5;
IADD.64 R10, R6, 0x4 &req={1} ?trans2;
MOV R18, RZ ?WAIT7_END_GROUP;
LOP3.LUT R12, R8, 0x3, RZ, 0xc0, !PT ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B1, 0xe00 ?trans4;
ISETP.NE.S64.AND P0, PT, R12, RZ, PT ?WAIT14_END_GROUP;
@!P0 BRA 0xdf0 ?trans5;
LDC.64 R14, c[0x4][RZ] &wr=0x0 ?trans1;
MOV R19, RZ ?trans1;
IMAD.WIDE.U32 R14, R18, 0xc80, R14 &req={0} ?WAIT7_END_GROUP;
HFMA2 R23, -RZ, RZ, 0, 0 ?trans1;
MOV R21, RZ &req={0} ?trans1;
CS2R R4, SRZ ?trans1;
CS2R R2, SRZ ?WAIT7_END_GROUP;
IMAD.WIDE.U32 R16, R23, 0x4, R10 ?WAIT5_END_GROUP;
LDG.E R25, desc[UR4][R16.64] &rd=0x0 &wr=0x5 ?trans1;
MOV R27, R23 ?trans1;
IADD3 R23, PT, PT, R23, 0x1, RZ ?trans1;
MOV R0, RZ ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R23, 0x5, PT ?WAIT5_END_GROUP;
P2R R28, PR, RZ, 0x1 &req={0} ?WAIT8_END_GROUP;
SHF.R.U32.HI R30, RZ, R0, R25 &req={5} ?trans1;
IMAD R16, R27, 0x20, R0 ?WAIT3_END_GROUP;
LOP3.LUT R17, R30, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R17, 0x1, PT ?trans1;
IMAD R17, R16, 0x5, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, R17, 0x4, R14 ?trans1;
R2P PR, R30, 0x7e ?WAIT7_END_GROUP;
@!P0 LDG.E R20, desc[UR4][R16.64] &wr=0x2 ?trans4;
@!P0 LDG.E R24, desc[UR4][R16.64+0x10] &wr=0x3 ?trans4;
@!P0 LDG.E R29, desc[UR4][R16.64+0x4] &wr=0x4 ?trans4;
@!P0 LDG.E R22, desc[UR4][R16.64+0x8] &wr=0x4 ?trans4;
@!P0 LDG.E R31, desc[UR4][R16.64+0xc] &wr=0x4 ?trans4;
@P1 LDG.E R32, desc[UR4][R16.64+0x14] &wr=0x4 ?trans4;
@P2 LDG.E R34, desc[UR4][R16.64+0x28] &wr=0x4 ?trans4;
@P5 LDG.E R36, desc[UR4][R16.64+0x64] &wr=0x4 ?trans4;
@P1 LDG.E R26, desc[UR4][R16.64+0x1c] &wr=0x4 ?trans4;
@P6 LDG.E R35, desc[UR4][R16.64+0x78] &wr=0x4 ?trans4;
@P2 LDG.E R33, desc[UR4][R16.64+0x2c] &wr=0x4 ?trans4;
@P4 LDG.E R37, desc[UR4][R16.64+0x5c] &wr=0x4 ?trans1;
@!P0 LOP3.LUT R21, R21, R20, RZ, 0x3c, !PT &req={2} ?WAIT3_END_GROUP;
@P3 LDG.E R20, desc[UR4][R16.64+0x3c] &wr=0x2 ?trans1;
@!P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT &req={3} ?WAIT3_END_GROUP;
@P4 LDG.E R24, desc[UR4][R16.64+0x50] &wr=0x3 ?trans1;
@!P0 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT &req={4} ?WAIT3_END_GROUP;
@P1 LDG.E R29, desc[UR4][R16.64+0x18] &wr=0x4 ?trans1;
@!P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P1 LDG.E R22, desc[UR4][R16.64+0x24] &wr=0x4 ?trans1;
@!P0 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P1 LDG.E R31, desc[UR4][R16.64+0x20] &wr=0x4 ?trans1;
@P1 LOP3.LUT R21, R21, R32, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P2 LDG.E R32, desc[UR4][R16.64+0x30] &wr=0x4 ?trans1;
@P2 LOP3.LUT R21, R21, R34, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P2 LDG.E R34, desc[UR4][R16.64+0x38] &wr=0x4 ?trans1;
LOP3.LUT P0, RZ, R30, 0x80, RZ, 0xc0, !PT ?trans2;
@P1 LOP3.LUT R3, R3, R26, RZ, 0x3c, !PT ?trans2;
@P4 LDG.E R26, desc[UR4][R16.64+0x60] &wr=0x4 ?trans1;
@P3 LOP3.LUT R21, R21, R20, RZ, 0x3c, !PT &req={2} ?WAIT3_END_GROUP;
@P3 LDG.E R20, desc[UR4][R16.64+0x44] &wr=0x2 ?trans1;
@P4 LOP3.LUT R21, R21, R24, RZ, 0x3c, !PT &req={3} ?WAIT3_END_GROUP;
@P4 LDG.E R24, desc[UR4][R16.64+0x58] &wr=0x3 ?trans1;
@P1 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT &req={4} ?trans2;
@P5 LOP3.LUT R21, R21, R36, RZ, 0x3c, !PT ?trans1;
@P2 LDG.E R29, desc[UR4][R16.64+0x34] &wr=0x4 ?trans1;
@P1 LOP3.LUT R5, R5, R22, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P3 LDG.E R22, desc[UR4][R16.64+0x4c] &wr=0x4 ?trans1;
@P1 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P3 LDG.E R31, desc[UR4][R16.64+0x40] &wr=0x4 ?trans1;
@P6 LOP3.LUT R21, R21, R35, RZ, 0x3c, !PT ?trans2;
@P2 LOP3.LUT R2, R2, R33, RZ, 0x3c, !PT ?trans1;
@P4 LDG.E R35, desc[UR4][R16.64+0x54] &wr=0x4 ?trans1;
@P2 LOP3.LUT R5, R5, R34, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P3 LDG.E R33, desc[UR4][R16.64+0x48] &wr=0x4 ?trans1;
@P2 LOP3.LUT R3, R3, R32, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P0 LDG.E R34, desc[UR4][R16.64+0x8c] &wr=0x4 ?trans4;
@P5 LDG.E R32, desc[UR4][R16.64+0x68] &wr=0x4 ?trans1;
@P3 LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT &req={2} ?WAIT3_END_GROUP;
@P5 LDG.E R20, desc[UR4][R16.64+0x6c] &wr=0x2 ?trans1;
@P4 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT &req={3} ?WAIT3_END_GROUP;
@P6 LDG.E R24, desc[UR4][R16.64+0x80] &wr=0x3 ?trans1;
@P2 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT &req={4} ?WAIT3_END_GROUP;
@P5 LDG.E R29, desc[UR4][R16.64+0x70] &wr=0x4 ?trans1;
@P3 LOP3.LUT R5, R5, R22, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P5 LDG.E R22, desc[UR4][R16.64+0x74] &wr=0x4 ?trans1;
@P3 LOP3.LUT R2, R2, R31, RZ, 0x3c, !PT ?trans2;
@P4 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ?trans1;
@P6 LDG.E R31, desc[UR4][R16.64+0x7c] &wr=0x4 ?trans1;
@P4 LOP3.LUT R2, R2, R35, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P6 LDG.E R26, desc[UR4][R16.64+0x88] &wr=0x4 ?trans1;
@P3 LOP3.LUT R4, R4, R33, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P6 LDG.E R33, desc[UR4][R16.64+0x84] &wr=0x4 ?trans1;
@P0 LOP3.LUT R21, R21, R34, RZ, 0x3c, !PT ?trans2;
@P4 LOP3.LUT R4, R4, R37, RZ, 0x3c, !PT ?trans1;
@P0 LDG.E R35, desc[UR4][R16.64+0x90] &wr=0x4 ?trans1;
@P5 LOP3.LUT R2, R2, R32, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P0 LDG.E R32, desc[UR4][R16.64+0x94] &wr=0x4 ?trans4;
@P0 LDG.E R37, desc[UR4][R16.64+0x98] &wr=0x4 ?trans4;
@P0 LDG.E R34, desc[UR4][R16.64+0x9c] &wr=0x4 ?trans1;
@P5 LOP3.LUT R3, R3, R20, RZ, 0x3c, !PT &req={2} ?WAIT4_END_GROUP;
@P6 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT &req={3} ?trans2;
@P5 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT &req={4} ?trans2;
@P5 LOP3.LUT R5, R5, R22, RZ, 0x3c, !PT ?trans2;
@P6 LOP3.LUT R2, R2, R31, RZ, 0x3c, !PT ?trans2;
@P6 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ?trans2;
@P6 LOP3.LUT R4, R4, R33, RZ, 0x3c, !PT ?WAIT2_END_GROUP;
@P0 LOP3.LUT R2, R2, R35, RZ, 0x3c, !PT ?trans2;
@P0 LOP3.LUT R3, R3, R32, RZ, 0x3c, !PT ?trans2;
@P0 LOP3.LUT R4, R4, R37, RZ, 0x3c, !PT ?trans2;
@P0 LOP3.LUT R5, R5, R34, RZ, 0x3c, !PT ?trans2;
R2P PR, R30.B1, 0x7f ?WAIT13_END_GROUP;
@P0 LDG.E R22, desc[UR4][R16.64+0xa8] &wr=0x2 ?trans4;
@P0 LDG.E R24, desc[UR4][R16.64+0xb0] &wr=0x3 ?trans4;
@P0 LDG.E R31, desc[UR4][R16.64+0xac] &wr=0x4 ?trans4;
@P0 LDG.E R29, desc[UR4][R16.64+0xa4] &wr=0x4 ?trans4;
@P0 LDG.E R20, desc[UR4][R16.64+0xa0] &wr=0x4 ?trans4;
@P2 LDG.E R32, desc[UR4][R16.64+0xc8] &wr=0x4 ?trans4;
@P3 LDG.E R34, desc[UR4][R16.64+0xdc] &wr=0x4 ?trans4;
@P4 LDG.E R36, desc[UR4][R16.64+0xf0] &wr=0x4 ?trans4;
@P5 LDG.E R33, desc[UR4][R16.64+0x104] &wr=0x4 ?trans4;
@P1 LDG.E R26, desc[UR4][R16.64+0xc4] &wr=0x4 ?trans4;
@P3 LDG.E R37, desc[UR4][R16.64+0xe8] &wr=0x4 ?trans4;
@P3 LDG.E R35, desc[UR4][R16.64+0xe0] &wr=0x4 ?trans1;
@P0 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT &req={2} ?WAIT3_END_GROUP;
@P1 LDG.E R22, desc[UR4][R16.64+0xb4] &wr=0x2 ?trans1;
@P0 LOP3.LUT R5, R5, R24, RZ, 0x3c, !PT &req={3} ?WAIT3_END_GROUP;
@P1 LDG.E R24, desc[UR4][R16.64+0xbc] &wr=0x3 ?trans1;
@P0 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT &req={4} ?WAIT3_END_GROUP;
@P1 LDG.E R31, desc[UR4][R16.64+0xc0] &wr=0x4 ?trans1;
@P0 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P1 LDG.E R29, desc[UR4][R16.64+0xb8] &wr=0x4 ?trans1;
@P0 LOP3.LUT R21, R21, R20, RZ, 0x3c, !PT ?trans2;
LOP3.LUT P0, RZ, R30, 0x8000, RZ, 0xc0, !PT ?trans1;
@P6 LDG.E R20, desc[UR4][R16.64+0x118] &wr=0x4 ?trans4;
@P3 LDG.E R30, desc[UR4][R16.64+0xe4] &wr=0x4 ?trans1;
@P1 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P2 LDG.E R26, desc[UR4][R16.64+0xd8] &wr=0x4 ?trans1;
@P1 LOP3.LUT R21, R21, R22, RZ, 0x3c, !PT &req={2} ?WAIT3_END_GROUP;
@P4 LDG.E R22, desc[UR4][R16.64+0xf8] &wr=0x2 ?trans1;
@P2 LOP3.LUT R21, R21, R32, RZ, 0x3c, !PT ?trans2;
@P1 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT &req={3} ?trans1;
@P3 LDG.E R32, desc[UR4][R16.64+0xec] &wr=0x3 ?trans1;
@P3 LOP3.LUT R21, R21, R34, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P2 LDG.E R24, desc[UR4][R16.64+0xd0] &wr=0x2 ?trans1;
@P4 LOP3.LUT R21, R21, R36, RZ, 0x3c, !PT ?trans2;
@P1 LOP3.LUT R4, R4, R31, RZ, 0x3c, !PT &req={4} ?trans1;
@P0 LDG.E R36, desc[UR4][R16.64+0x12c] &wr=0x4 ?trans1;
@P5 LOP3.LUT R21, R21, R33, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P2 LDG.E R33, desc[UR4][R16.64+0xd4] &wr=0x3 ?trans1;
@P1 LOP3.LUT R2, R2, R29, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P2 LDG.E R31, desc[UR4][R16.64+0xcc] &wr=0x4 ?trans4;
@P4 LDG.E R29, desc[UR4][R16.64+0xfc] &wr=0x4 ?trans4;
@P4 LDG.E R34, desc[UR4][R16.64+0xf4] &wr=0x4 ?trans1;
@P6 LOP3.LUT R21, R21, R20, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P4 LDG.E R20, desc[UR4][R16.64+0x100] &wr=0x4 ?trans1;
@P2 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P5 LDG.E R26, desc[UR4][R16.64+0x114] &wr=0x4 ?trans1;
@P2 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT &req={2} ?WAIT3_END_GROUP;
@P5 LDG.E R24, desc[UR4][R16.64+0x10c] &wr=0x2 ?trans1;
@P3 LOP3.LUT R3, R3, R30, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P6 LDG.E R30, desc[UR4][R16.64+0x128] &wr=0x2 ?trans1;
@P2 LOP3.LUT R4, R4, R33, RZ, 0x3c, !PT &req={3} ?WAIT3_END_GROUP;
@P5 LDG.E R33, desc[UR4][R16.64+0x110] &wr=0x3 ?trans1;
@P2 LOP3.LUT R2, R2, R31, RZ, 0x3c, !PT &req={4} ?trans2;
@P3 LOP3.LUT R4, R4, R37, RZ, 0x3c, !PT ?trans1;
@P5 LDG.E R31, desc[UR4][R16.64+0x108] &wr=0x4 ?trans1;
@P3 LOP3.LUT R2, R2, R35, RZ, 0x3c, !PT ?trans2;
@P4 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ?trans1;
@P6 LDG.E R35, desc[UR4][R16.64+0x11c] &wr=0x4 ?trans1;
@P4 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P6 LDG.E R22, desc[UR4][R16.64+0x120] &wr=0x4 ?trans1;
@P0 LOP3.LUT R21, R21, R36, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
@P6 LDG.E R29, desc[UR4][R16.64+0x124] &wr=0x4 ?trans1;
@P3 LOP3.LUT R5, R5, R32, RZ, 0x3c, !PT ?trans2;
@P4 LOP3.LUT R2, R2, R34, RZ, 0x3c, !PT ?trans1;
@P0 LDG.E R37, desc[UR4][R16.64+0x130] &wr=0x4 ?trans4;
@P0 LDG.E R32, desc[UR4][R16.64+0x134] &wr=0x4 ?trans4;
@P0 LDG.E R34, desc[UR4][R16.64+0x138] &wr=0x4 ?trans4;
@P0 LDG.E R36, desc[UR4][R16.64+0x13c] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R0, 0x10, RZ ?WAIT2_END_GROUP;
@P4 LOP3.LUT R5, R5, R20, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R0, 0x20, PT ?trans1;
@P5 LOP3.LUT R5, R5, R26, RZ, 0x3c, !PT ?trans2;
@P5 LOP3.LUT R3, R3, R24, RZ, 0x3c, !PT &req={2} ?trans2;
@P6 LOP3.LUT R5, R5, R30, RZ, 0x3c, !PT ?trans2;
@P5 LOP3.LUT R4, R4, R33, RZ, 0x3c, !PT &req={3} ?trans2;
@P5 LOP3.LUT R2, R2, R31, RZ, 0x3c, !PT &req={4} ?WAIT4_END_GROUP;
@P6 LOP3.LUT R2, R2, R35, RZ, 0x3c, !PT ?trans2;
@P6 LOP3.LUT R3, R3, R22, RZ, 0x3c, !PT ?trans2;
@P6 LOP3.LUT R4, R4, R29, RZ, 0x3c, !PT ?trans2;
@P0 LOP3.LUT R2, R2, R37, RZ, 0x3c, !PT ?trans2;
@P0 LOP3.LUT R3, R3, R32, RZ, 0x3c, !PT ?trans2;
@P0 LOP3.LUT R4, R4, R34, RZ, 0x3c, !PT ?WAIT2_END_GROUP;
@P0 LOP3.LUT R5, R5, R36, RZ, 0x3c, !PT ?trans1;
@P1 BRA 0x2a0 ?trans6;
ISETP.NE.AND P2, PT, R28, RZ, PT ?WAIT13_END_GROUP;
@P2 BRA 0x230 ?trans5;
STG.E.64 desc[UR4][R6.64+0x8], R2 &rd=0x0 ?trans1;
IADD3 R19, PT, PT, R19, 0x1, RZ ?WAIT3_END_GROUP;
STG.E.64 desc[UR4][R6.64+0x10], R4 &rd=0x0 ?trans2;
ISETP.GE.U32.AND P0, PT, R19, R12, PT ?trans2;
STG.E desc[UR4][R6.64+0x4], R21 &rd=0x0 ?trans11;
@!P0 BRA 0x1f0 ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R2, R8 &req={0} ?trans1;
MOV R3, R9 ?trans1;
SHF.R.U64 R8, R8, 0x2, R9.reuse ?trans2;
SHF.R.U32.HI R9, RZ, 0x2, R9 ?trans2;
ISETP.GT.U64.AND P0, PT, R2, 0x3, PT ?WAIT3_END_GROUP;
IADD3 R18, PT, PT, R18, 0x1, RZ ?WAIT11_END_GROUP;
@P0 BRA 0x170 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
STG.E.64 desc[UR4][R6.64+0x18], RZ ?trans4;
STG.E desc[UR4][R6.64+0x20], RZ ?trans4;
STG.E.64 desc[UR4][R6.64+0x28], RZ ?trans1;
EXIT ?trans5;
BRA 0xec0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: setupExperiment(hiprandState*)
_Z15setupExperimentP12hiprandState:
s_load_b64 s[0:1], s[0:1], 0x4
s_load_b32 s4, s[2:3], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_mov_b32 s7, 0
s_mov_b32 s18, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
v_mul_u32_u24_e32 v2, s1, v2
s_mul_i32 s0, s0, s1
s_and_b32 s4, s4, 0xffff
v_mul_lo_u32 v3, s0, v1
s_mov_b32 s0, 0xa96f9d04
v_mad_u64_u32 v[5:6], null, s15, s4, v[1:2]
s_mov_b32 s1, 0x8f14727c
s_mov_b32 s4, 0x99890de2
s_mov_b32 s5, 0x87b71528
v_mov_b32_e32 v7, 0x1cef92e5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add3_u32 v0, v3, v2, v0
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, 0x92857fe6
v_mov_b32_e32 v2, s0
v_ashrrev_i32_e32 v6, 31, v5
v_mul_lo_u32 v8, v0, 48
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
ds_store_2addr_b64 v8, v[0:1], v[2:3] offset0:3 offset1:4
ds_store_2addr_b32 v8, v7, v4 offset1:10
v_cmpx_ne_u32_e32 0, v5
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v7, v6
v_dual_mov_b32 v6, v5 :: v_dual_add_nc_u32 v9, 24, v8
s_mov_b32 s8, 0
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, _ZL31d_xorwow_sequence_jump_matrices@rel32@lo+4
s_addc_u32 s15, s15, _ZL31d_xorwow_sequence_jump_matrices@rel32@hi+12
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v10, 3, v6
s_mov_b32 s19, exec_lo
v_cmpx_ne_u32_e32 0, v10
s_cbranch_execz .LBB0_11
s_mov_b32 s20, 0
s_mov_b32 s21, 0
.LBB0_4:
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
s_mov_b32 s12, s8
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
v_mov_b32_e32 v4, s12
s_mov_b64 s[10:11], s[14:15]
s_mov_b32 s9, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b32 s0, s9, 3
s_mov_b64 s[12:13], 0
s_and_b32 s0, s0, 0x1ffffffc
s_mov_b64 s[16:17], s[10:11]
v_add_nc_u32_e32 v11, s0, v9
s_and_b32 s0, s9, 31
ds_load_b32 v11, v11
s_waitcnt lgkmcnt(0)
v_bfe_u32 v11, v11, s0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v11
.LBB0_6:
s_load_b32 s6, s[16:17], 0x0
s_cmp_eq_u32 s12, 1
s_cselect_b32 s0, -1, 0
s_cmp_eq_u32 s12, 2
v_cndmask_b32_e64 v11, v0, v1, s0
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s12, 3
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v11, v11, v2, s1
s_cmp_eq_u32 s12, 4
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s12, 0
v_cndmask_b32_e64 v11, v11, v3, s4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v11, v11, v4, s5
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v12, s6, 0, vcc_lo
s_cselect_b32 s6, -1, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_add_u32 s16, s16, 4
v_xor_b32_e32 v11, v12, v11
s_addc_u32 s17, s17, 0
s_cmp_eq_u32 s12, 5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v11, s5
v_cndmask_b32_e64 v3, v3, v11, s4
v_cndmask_b32_e64 v2, v2, v11, s1
v_cndmask_b32_e64 v1, v1, v11, s0
v_cndmask_b32_e64 v0, v0, v11, s6
s_cbranch_scc0 .LBB0_6
s_add_i32 s9, s9, 1
s_add_u32 s10, s10, 20
s_addc_u32 s11, s11, 0
s_cmpk_lg_i32 s9, 0xa0
s_cbranch_scc1 .LBB0_5
v_mov_b32_e32 v11, v9
s_mov_b64 s[0:1], 0
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
v_cndmask_b32_e32 v12, v0, v1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v12, v12, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 4
v_cndmask_b32_e32 v12, v12, v3, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 5
v_cndmask_b32_e32 v12, v12, v4, vcc_lo
ds_store_b32 v11, v12
v_add_nc_u32_e32 v11, 4, v11
s_cbranch_scc0 .LBB0_9
s_add_i32 s21, s21, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s21, v10
s_or_b32 s20, vcc_lo, s20
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s19
v_lshrrev_b64 v[0:1], 2, v[6:7]
v_cmp_gt_u64_e32 vcc_lo, 4, v[6:7]
s_add_u32 s14, s14, 0xc80
s_addc_u32 s15, s15, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v6, v0
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s18
s_load_b64 s[0:1], s[2:3], 0x0
v_mov_b32_e32 v4, 0
ds_load_2addr_b64 v[0:3], v8 offset0:4 offset1:5
ds_store_2addr_b32 v8, v4, v4 offset0:1 offset1:2
ds_load_2addr_b64 v[9:12], v8 offset0:2 offset1:3
ds_load_2addr_b64 v[13:16], v8 offset1:1
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[6:7], null, v5, 48, s[0:1]
s_clause 0x2
global_store_b128 v[6:7], v[0:3], off offset:32
global_store_b128 v[6:7], v[9:12], off offset:16
global_store_b128 v[6:7], v[13:16], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| setupExperiment | 7,739 | 2,884 | stackv2-00000-of-00015 |
// Demangled: smemAtomics(curandStateXORWOW*, unsigned int*)
Function : _Z11smemAtomicsP17curandStateXORWOWPj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R12, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R11, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R5, R11, UR4, R12 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x30, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E.64 R8, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR6][R2.64+0x10] &wr=0x3 ?trans4;
LDG.E.64 R4, desc[UR6][R2.64+0x8] &wr=0x4 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R12, 0x1f, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?trans1;
SHF.R.U32.HI R0, RZ, 0x2, R9 &req={2} ?WAIT2_END_GROUP;
IADD3 R8, PT, PT, R8, 0x587c5, RZ ?trans2;
LOP3.LUT R0, R0, R9, RZ, 0x3c, !PT ?trans1;
IMAD.SHL.U32 R9, R7, 0x10, RZ &req={3} ?trans1;
MOV R15, R6 ?trans1;
MOV R16, R7 ?trans1;
MOV R14, R5 &req={4} ?trans1;
IADD3 R10, PT, PT, R0, R0, RZ ?WAIT4_END_GROUP;
STG.E.64 desc[UR6][R2.64+0x8], R14 &rd=0x1 ?trans1;
LOP3.LUT R10, R0, R10, R9, 0x96, !PT ?trans1;
HFMA2 R9, -RZ, RZ, 0.1171875, 0 ?WAIT3_END_GROUP;
LOP3.LUT R17, R10, R7, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R17, R8, RZ ?trans1;
STG.E.64 desc[UR6][R2.64+0x10], R16 &rd=0x1 ?trans3;
I2FP.F32.U32 R0, R0 ?WAIT5_END_GROUP;
FFMA R0, R0, R9, 1.1641532182693481445e-10 ?trans1;
MOV R9, R4 ?WAIT3_END_GROUP;
FMUL R10, R0, 32 ?trans1;
LEA R0, R12, UR4, 0x2 ?trans1;
STG.E.64 desc[UR6][R2.64], R8 &rd=0x1 ?trans4;
F2I.U32.TRUNC.NTZ R10, R10 &wr=0x2 ?trans1;
@!P0 STS [R0], RZ &rd=0x1 ?trans1;
LEA R6, R10, UR4, 0x2 &req={2} ?WAIT5_END_GROUP;
ATOMS.POPC.INC.32 RZ, [R6+URZ] &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &req={1} &wr=0x0 ?trans1;
IMAD R5, R11, 0x20, R12 ?trans1;
LDS R0, [R0] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR6][R2.64] &wr=0x1 ?trans2;
IADD3 R5, PT, PT, R0, R5, RZ &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x310;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: smemAtomics(hiprandState*, unsigned int*)
_Z11smemAtomicsP12hiprandStatePj:
v_cmp_gt_u32_e32 vcc_lo, 32, v0
v_lshlrev_b32_e32 v1, 2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v2, 0
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mad_i64_i32 v[7:8], null, v2, 48, s[0:1]
s_clause 0x2
global_load_b128 v[2:5], v[7:8], off offset:24
global_load_b32 v6, v[7:8], off offset:40
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v10, 2, v2
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, 0x587c5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v10, v2
v_lshlrev_b32_e32 v10, 4, v6
v_lshlrev_b32_e32 v11, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v10, v11, v10
v_mov_b32_e32 v11, 1
v_xor3_b32 v2, v10, v2, v6
s_clause 0x2
global_store_b32 v[7:8], v2, off offset:40
global_store_b128 v[7:8], v[3:6], off offset:24
global_store_b32 v[7:8], v9, off
v_add_nc_u32_e32 v10, v9, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v10, v10
v_fmaak_f32 v10, 0x2f800000, v10, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x42000000, v10
v_cvt_u32_f32_e32 v10, v10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v10, 2, v10
ds_add_u32 v10, v11
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_4
v_lshl_or_b32 v2, s15, 5, v0
ds_load_b32 v1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| smemAtomics | 1,322 | 1,229 | stackv2-00000-of-00015 |
// Demangled: ReductionMax2(int*, int*, int)
Function : _Z13ReductionMax2PiS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x360] &wr=0x1 ?trans1;
HFMA2 R4, -RZ, RZ, -0.0 , 5.9604644775390625e-08 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R5, R7, UR8, R6 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, UR4, PT &req={2} ?WAIT13_END_GROUP;
@!P0 LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans2;
@!P0 IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
@!P0 LDG.E R4, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
MOV R0, UR8 ?trans1;
UMOV UR4, 0x400 ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R5, R6, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R5], R4 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x230 &req={0} ?trans5;
MOV R2, R0 &req={0} ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans3;
ISETP.GT.U32.AND P0, PT, R2, 0x3, PT ?trans1;
ISETP.GE.U32.AND P1, PT, R6, R0, PT ?trans2;
BSSY.RECONVERGENT B0, 0x220 ?trans11;
@P1 BRA 0x210 ?trans5;
IMAD R2, R0, 0x4, R5 ?trans1;
LDS R3, [R5] ?trans5;
LDS R2, [R2] &wr=0x0 ?trans2;
ISETP.GT.AND P1, PT, R2, R3, PT &req={0} ?WAIT13_END_GROUP;
@P1 STS [R5], R2 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@P0 BRA 0x150 ?trans5;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={2} ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT8_END_GROUP;
LDS R5, [UR4] &req={1} &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: ReductionMax2(int*, int*, int)
_Z13ReductionMax2PiS_i:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_mov_b32_e32 v2, 0x80000001
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s5, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_mov_b32 s0, s5
s_lshr_b32 s5, s5, 1
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, s5, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_u32 s0, 4
s_cbranch_scc0 .LBB0_3
.LBB0_7:
s_mov_b32 s5, 0
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| ReductionMax2 | 1,098 | 947 | stackv2-00000-of-00015 |
// Demangled: vector_addition(int, int*, int*, int*)
Function : _Z15vector_additioniPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vector_addition(int, int*, int*, int*)
_Z15vector_additioniPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vector_addition | 574 | 577 | stackv2-00000-of-00015 |
// Demangled: generateRandomMatrix(unsigned int*, float, int)
Function : _Z20generateRandomMatrixPjfi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x0 ?trans1;
NOP ?trans1;
CS2UR UR4, SR_CLOCKLO ?WAIT4_END_GROUP;
ULOP3.LUT UR4, UR4, 0xaad26b49, URZ, 0x3c, !UPT ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
ULOP3.LUT UR5, UR5, 0xf7dcefdd, URZ, 0x3c, !UPT ?trans1;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
UIMAD UR4, UR4, 0x4182bed5, URZ ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans3;
UIADD3 UR6, UPT, UPT, UR4, 0x75bcd15, URZ ?trans1;
UIADD3 UR7, UPT, UPT, UR4, 0x583f19, URZ ?trans1;
UIMAD UR5, UR5, -0x658354e5, UR4 ?WAIT2_END_GROUP;
USHF.R.U32.HI UR8, URZ, 0x2, UR6 ?WAIT4_END_GROUP;
ULOP3.LUT UR8, UR8, UR6, URZ, 0x3c, !UPT ?trans1;
USHF.L.U32 UR6, UR7, 0x4, URZ ?WAIT3_END_GROUP;
UIADD3 UR9, UPT, UPT, UR8, UR8, URZ ?WAIT4_END_GROUP;
ULOP3.LUT UR6, UR7, UR6, UR9, 0x96, !UPT ?trans1;
LDCU UR7, c[0x0][0x364] &wr=0x1 ?trans3;
ULOP3.LUT UR6, UR6, UR8, URZ, 0x3c, !UPT ?WAIT4_END_GROUP;
UIADD3 UR6, UPT, UPT, UR5, 0x6a788e, UR6 ?WAIT4_END_GROUP;
UIMAD.WIDE.U32 UR4, UR6, 0x51eb851f, URZ ?WAIT4_END_GROUP;
USHF.R.U32.HI UR5, URZ, 0x5, UR5 ?trans1;
IMAD R5, R5, UR7, R0 &req={1} ?WAIT3_END_GROUP;
UIMAD UR5, UR5, -0x64, UR6 ?trans1;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, R5, UR5, RZ ?WAIT5_END_GROUP;
STG.E desc[UR10][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x1d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: generateRandomMatrix(unsigned int*, float, int)
_Z20generateRandomMatrixPjfi:
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_load_b32 s3, s[0:1], 0x1c
s_xor_b32 s2, s2, 0x2c7f967f
s_mov_b32 s8, 0x7b99840d
s_mul_i32 s2, s2, 0x493c4aa1
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s4, s2, 0x75bcd15
s_add_i32 s6, s2, 0x583f19
s_lshr_b32 s5, s4, 2
v_and_b32_e32 v1, 0x3ff, v0
s_xor_b32 s4, s5, s4
s_lshl_b32 s5, s6, 4
s_lshl_b32 s7, s4, 1
v_bfe_u32 v0, v0, 10, 10
s_xor_b32 s5, s5, s7
s_mul_i32 s7, s8, 0xa03697cb
s_xor_b32 s5, s5, s6
s_add_i32 s2, s2, s7
s_xor_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s3, 16
s_add_i32 s2, s2, 0x6a788e
v_mad_u32_u24 v0, v1, s3, v0
s_mul_hi_u32 s4, s2, 0x51eb851f
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s4, s4, 5
s_mulk_i32 s4, 0x64
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s2, s4
v_add_nc_u32_e32 v1, s2, v0
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| generateRandomMatrix | 815 | 666 | stackv2-00000-of-00015 |
// Demangled: getminimum(unsigned int*, unsigned int*)
Function : _Z10getminimumPjS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x0 ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R5, R5, UR4, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
VOTEU.ANY UR4, UPT, PT ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
S2R R0, SR_LANEID &wr=0x1 ?trans1;
UFLO.U32 UR4, UR4 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P0, PT, R0, UR4, PT &req={1} ?trans1;
REDUX.MIN UR5, R2 &req={2} &wr=0x1 ?trans2;
MOV R7, UR5 &req={1} ?WAIT10_END_GROUP;
@P0 REDG.E.MIN.STRONG.GPU desc[UR6][R4.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x120;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: getminimum(unsigned int*, unsigned int*)
_Z10getminimumPjS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s5, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, s5, v1
v_add_lshl_u32 v0, v1, v0, 2
global_load_b32 v0, v0, s[0:1]
s_mov_b32 s0, -1
.LBB0_1:
s_ctz_i32_b32 s1, s4
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v0, s1
s_lshl_b32 s1, 1, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s4, s4, s1
s_min_u32 s0, s0, s5
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_atomic_min_u32 v0, v1, s[2:3]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| getminimum | 498 | 545 | stackv2-00000-of-00015 |
// Demangled: initializeResult(unsigned int*, unsigned int)
Function : _Z16initializeResultPjj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.NE.AND P0, PT, R4, RZ, PT &req={1} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R4.reuse, 0x10, PT ?trans1;
LOP3.LUT R6, R4, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x250 ?trans6;
LDCU.64 UR4, c[0x0][0x380] &wr=0x1 ?trans1;
LOP3.LUT R0, R4, 0xfffffff0, RZ, 0xc0, !PT ?trans1;
MOV R5, RZ ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x20, URZ &req={1} ?WAIT6_END_GROUP;
MOV.64 R2, UR4 ?WAIT8_END_GROUP;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans1;
STG.E desc[UR6][R2.64+-0x20], RZ &req={0} ?trans1;
IADD3 R5, PT, PT, R5, 0x10, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R0, RZ, PT ?trans1;
STG.E desc[UR6][R2.64+-0x1c], RZ ?trans4;
STG.E desc[UR6][R2.64+-0x18], RZ ?trans4;
STG.E desc[UR6][R2.64+-0x14], RZ ?trans4;
STG.E desc[UR6][R2.64+-0x10], RZ ?trans4;
STG.E desc[UR6][R2.64+-0xc], RZ ?trans4;
STG.E desc[UR6][R2.64+-0x8], RZ ?trans4;
STG.E desc[UR6][R2.64+-0x4], RZ ?trans4;
STG.E desc[UR6][R2.64], RZ ?trans4;
STG.E desc[UR6][R2.64+0x4], RZ ?trans4;
STG.E desc[UR6][R2.64+0x8], RZ ?trans4;
STG.E desc[UR6][R2.64+0xc], RZ ?trans4;
STG.E desc[UR6][R2.64+0x10], RZ ?trans4;
STG.E desc[UR6][R2.64+0x14], RZ ?trans4;
STG.E desc[UR6][R2.64+0x18], RZ ?trans4;
STG.E desc[UR6][R2.64+0x1c], RZ &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x40 &req={0} ?WAIT2_END_GROUP;
@P1 BRA 0x100 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P0, PT, R6, 0x8, PT ?trans1;
LOP3.LUT R7, R4, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R7, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x350 ?trans6;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R5.reuse, 0x4, R2 &req={0} ?trans1;
IADD3 R5, PT, PT, R5, 0x8, RZ ?WAIT4_END_GROUP;
STG.E desc[UR6][R2.64], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x4], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x8], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0xc], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x10], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x14], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x18], RZ &rd=0x0 ?trans4;
STG.E desc[UR6][R2.64+0x1c], RZ &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R7, 0x4, PT ?trans1;
LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x410 ?trans6;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE.U32 R2, R5.reuse, 0x4, R2 &req={0} ?trans1;
IADD3 R5, PT, PT, R5, 0x4, RZ ?WAIT4_END_GROUP;
STG.E desc[UR6][R2.64], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R2.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R2.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R2.64+0xc], RZ &rd=0x1 ?trans2;
@!P1 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &req={1,0} &wr=0x0 ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
STG.E desc[UR6][R2.64], RZ &rd=0x0 ?trans4;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT12_END_GROUP;
@P0 BRA 0x450 ?trans5;
EXIT ?trans5;
BRA 0x4b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: initializeResult(unsigned int*, unsigned int)
_Z16initializeResultPjj:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB4_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
.LBB4_2:
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB4_2
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| initializeResult | 1,950 | 231 | stackv2-00000-of-00015 |
// Demangled: makeMax(unsigned int*)
Function : _Z7makeMaxPj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R5, 0x7fffffff ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x60;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: makeMax(unsigned int*)
_Z7makeMaxPj:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
v_bfrev_b32_e32 v1, -2
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| makeMax | 186 | 110 | stackv2-00000-of-00015 |
// Demangled: square(unsigned int*, unsigned int*, unsigned int)
Function : _Z6squarePjS_j
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R5, c[0x0][0x390] &wr=0x1 ?trans2;
ISETP.NE.AND P0, PT, R5, RZ, PT &req={1} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
S2R R2, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x0 ?trans1;
LOP3.LUT R4, R5.reuse, 0xfffffff8, RZ, 0xc0, !PT ?trans1;
S2R R3, SR_TID.X &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R5, -0x1, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R4, PT, PT, -R4, RZ, RZ ?trans1;
IMAD R2, R3, UR4, R2 &req={0} ?trans1;
LOP3.LUT R3, R5, 0x7, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
IMAD R2, R2, R5, RZ ?trans2;
HFMA2 R5, -RZ, RZ, 0, 0 &req={1} ?WAIT7_END_GROUP;
LDC.64 R18, c[0x0][0x388] &req={4,3,2,0} &wr=0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R0, 0x7, PT ?trans1;
IADD3 R7, PT, PT, R2, R5, RZ ?trans1;
MOV R9, RZ ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R7, 0x4, R18 &req={0} ?WAIT5_END_GROUP;
LDG.E R37, desc[UR6][R18.64] &req={5} &rd=0x0 &wr=0x5 ?trans2;
@!P0 BRA 0x680 ?trans5;
LDC R8, c[0x0][0x390] &wr=0x1 ?trans1;
MOV R9, 0x3 ?trans1;
MOV R6, R4 ?trans1;
MOV R10, R2 ?trans1;
MOV R11, R5 ?WAIT4_END_GROUP;
LDC.64 R20, c[0x0][0x380] &wr=0x2 ?trans1;
IADD3 R7, PT, PT, R5.reuse, R8.reuse, RZ &req={1} ?trans2;
IADD3 R13, PT, PT, R5, R8, R8 ?trans1;
IMAD R15, R8.reuse, 0x3, R5.reuse ?trans1;
LEA R17, R8.reuse, R5, 0x2 ?trans1;
IMAD R31, R8.reuse, 0x5, R5.reuse ?trans2;
IMAD R33, R8.reuse, 0x6, R5.reuse ?trans2;
IMAD R35, R8, 0x7, R5 &req={2} ?WAIT7_END_GROUP;
IMAD.WIDE.U32 R22, R10, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R11, 0x4, R20.reuse ?trans2;
LDG.E R22, desc[UR6][R22.64] &req={2} &wr=0x2 ?trans4;
LDG.E R24, desc[UR6][R24.64] &wr=0x2 ?trans1;
IADD3 R27, PT, PT, R10, 0x1, RZ ?trans1;
IMAD.WIDE.U32 R28, R7, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R27, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R37, R22, R24, R37 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R37 &rd=0x1 ?trans4;
LDG.E R26, desc[UR6][R26.64] &wr=0x2 ?trans4;
LDG.E R28, desc[UR6][R28.64] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R10, 0x2, RZ ?trans1;
IMAD.WIDE.U32 R24, R13, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R14, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R12, R26, R28, R37 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R12 &rd=0x2 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x1 ?trans4;
LDG.E R24, desc[UR6][R24.64] &wr=0x1 ?trans1;
IADD3 R14, PT, PT, R10, 0x3, RZ ?trans1;
IMAD.WIDE.U32 R28, R15, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R14, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R37, R23, R24, R12 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R37 &rd=0x1 ?trans4;
LDG.E R26, desc[UR6][R26.64] &wr=0x2 ?trans4;
LDG.E R28, desc[UR6][R28.64] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R10, 0x4, RZ ?trans1;
IMAD.WIDE.U32 R24, R17, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R14, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R12, R26, R28, R37 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R12 &rd=0x2 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x1 ?trans4;
LDG.E R24, desc[UR6][R24.64] &wr=0x1 ?trans1;
IADD3 R14, PT, PT, R10, 0x5, RZ ?trans1;
IMAD.WIDE.U32 R28, R31, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R14, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R37, R23, R24, R12 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R37 &rd=0x1 ?trans4;
LDG.E R26, desc[UR6][R26.64] &wr=0x2 ?trans4;
LDG.E R28, desc[UR6][R28.64] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R10, 0x6, RZ ?trans1;
IMAD.WIDE.U32 R24, R33, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R14, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R12, R26, R28, R37 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R12 &rd=0x2 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x3 ?trans4;
LDG.E R24, desc[UR6][R24.64] &wr=0x3 ?trans1;
IADD3 R16, PT, PT, R10, 0x7, RZ ?trans1;
IMAD.WIDE.U32 R28, R35, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R16, 0x4, R20 ?WAIT4_END_GROUP;
IMAD R14, R23, R24, R12 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R14 &rd=0x2 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x1 ?trans4;
LDG.E R28, desc[UR6][R28.64] &wr=0x1 ?trans1;
IADD3 R6, PT, PT, R6, 0x8, RZ ?trans2;
IADD3 R9, PT, PT, R9, 0x8, RZ ?WAIT2_END_GROUP;
LEA R7, R8.reuse, R7, 0x3 ?trans2;
LEA R13, R8, R13, 0x3 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?trans1;
LEA R15, R8.reuse, R15, 0x3 ?trans2;
LEA R17, R8.reuse, R17, 0x3 ?trans2;
LEA R31, R8.reuse, R31, 0x3 ?trans2;
LEA R33, R8, R33, 0x3 ?WAIT2_END_GROUP;
LEA R35, R8.reuse, R35, 0x3 ?trans2;
LEA R11, R8, R11, 0x3 ?trans2;
IADD3 R10, PT, PT, R10, 0x8, RZ ?trans1;
IMAD R37, R27, R28, R14 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R37 &rd=0x2 ?trans1;
@P0 BRA 0x230 ?trans5;
IADD3 R9, PT, PT, R9, -0x3, RZ ?WAIT7_END_GROUP;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb00 ?trans5;
LDC R8, c[0x0][0x390] &wr=0x1 ?trans1;
IADD3 R6, PT, PT, R3, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ?trans1;
LOP3.LUT P1, R22, R8, 0x3, RZ, 0xc0, !PT &req={1} ?WAIT12_END_GROUP;
@!P0 BRA 0x920 ?trans5;
LDC R10, c[0x0][0x390] &wr=0x1 ?trans1;
IADD3 R11, PT, PT, R2, R9, RZ ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R17, R9, R10, R5 &req={1} ?trans2;
IMAD.WIDE.U32 R12, R11, 0x4, R6 &req={3,2} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R17, 0x4, R6 ?trans2;
LDG.E R12, desc[UR6][R12.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x2 ?trans1;
IADD3 R21, PT, PT, R11, 0x1, RZ ?trans2;
IADD3 R23, PT, PT, R17, R10, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R16, R21, 0x4, R6 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R20, R23, 0x4, R6 ?WAIT4_END_GROUP;
IMAD R37, R12, R14, R37 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R37 &rd=0x1 ?trans4;
LDG.E R16, desc[UR6][R16.64] &wr=0x2 ?trans4;
LDG.E R20, desc[UR6][R20.64] &wr=0x2 ?trans1;
IADD3 R25, PT, PT, R11, 0x2, RZ ?trans2;
IADD3 R27, PT, PT, R23, R10, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R12, R25, 0x4, R6 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R27, 0x4, R6 ?WAIT4_END_GROUP;
IMAD R23, R16, R20, R37 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R23 &rd=0x3 ?trans4;
LDG.E R12, desc[UR6][R12.64] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x2 ?trans1;
IADD3 R11, PT, PT, R11, 0x3, RZ ?trans2;
IADD3 R27, PT, PT, R27, R10, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R10, R11, 0x4, R6 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R27, 0x4, R6 ?WAIT4_END_GROUP;
IMAD R17, R12, R14, R23 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R17 &rd=0x3 ?trans4;
LDG.E R10, desc[UR6][R10.64] &wr=0x1 ?trans4;
LDG.E R6, desc[UR6][R6.64] &wr=0x1 ?trans1;
IADD3 R9, PT, PT, R9, 0x4, RZ ?trans1;
IMAD R37, R10, R6, R17 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R37 &rd=0x3 ?trans2;
@!P1 BRA 0xb00 ?trans5;
ISETP.NE.AND P0, PT, R22, 0x1, PT ?WAIT13_END_GROUP;
@P0 LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans1;
@P0 IADD3 R15, PT, PT, R2, R9, RZ ?trans1;
@P0 IMAD R17, R9, R8, R5 &req={3} ?WAIT4_END_GROUP;
@P0 IMAD.WIDE.U32 R10, R15, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
@P0 IMAD.WIDE.U32 R12, R17, 0x4, R6 &req={2} ?trans2;
@P0 LDG.E R10, desc[UR6][R10.64] &wr=0x2 ?trans4;
@P0 LDG.E R12, desc[UR6][R12.64] &wr=0x2 ?trans1;
@P0 IADD3 R15, PT, PT, R15, 0x1, RZ ?trans2;
@P0 IADD3 R17, PT, PT, R17, R8, RZ ?WAIT3_END_GROUP;
@P0 IMAD.WIDE.U32 R14, R15, 0x4, R6 ?WAIT4_END_GROUP;
@P0 IMAD.WIDE.U32 R16, R17, 0x4, R6 ?trans1;
LOP3.LUT P1, RZ, R8, 0x1, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
@P0 IMAD R21, R10, R12, R37 &req={5,2} ?WAIT10_END_GROUP;
@P1 LDC.64 R10, c[0x0][0x380] &wr=0x1 ?trans1;
@P0 STG.E desc[UR6][R18.64], R21 &rd=0x4 ?trans4;
@P0 LDG.E R14, desc[UR6][R14.64] &wr=0x2 ?trans4;
@P0 LDG.E R16, desc[UR6][R16.64] &wr=0x2 ?trans1;
@P0 IADD3 R9, PT, PT, R9, 0x2, RZ ?WAIT4_END_GROUP;
@P1 IADD3 R7, PT, PT, R2, R9, RZ ?trans1;
@P1 IMAD R9, R9, R8, R5 ?WAIT4_END_GROUP;
@P1 IMAD.WIDE.U32 R6, R7, 0x4, R10 &req={1} ?WAIT4_END_GROUP;
@P1 IMAD.WIDE.U32 R8, R9, 0x4, R10 ?WAIT4_END_GROUP;
@P0 IMAD R37, R14, R16, R21 &req={2} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR6][R18.64], R37 &rd=0x4 ?trans4;
@P1 LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans4;
@P1 LDG.E R8, desc[UR6][R8.64] &wr=0x2 ?trans2;
@P1 IMAD R11, R6, R8, R37 &req={2} ?WAIT5_END_GROUP;
@P1 STG.E desc[UR6][R18.64], R11 &rd=0x4 ?trans2;
LDCU UR4, c[0x0][0x390] &wr=0x1 ?trans1;
IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R5, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 BRA 0xf0 ?trans5;
EXIT ?trans5;
BRA 0xb50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: square(unsigned int*, unsigned int*, unsigned int)
_Z6squarePjS_j:
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB3_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v1, s4, v0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v5, v0, s6
.LBB3_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s7, v5
s_mov_b32 s8, 0
s_mov_b32 s4, s7
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
.LBB3_3:
v_add_nc_u32_e32 v0, s8, v5
s_lshl_b64 s[10:11], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_add_i32 s8, s8, 1
s_add_i32 s4, s4, s6
s_cmp_eq_u32 s6, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v8, v1, s[10:11]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v8, v0, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v6
global_store_b32 v[2:3], v6, off
s_cbranch_scc0 .LBB3_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_cbranch_scc0 .LBB3_2
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| square | 4,941 | 971 | stackv2-00000-of-00015 |
// Demangled: gpuMM(int*, int*, int*, int)
Function : _Z5gpuMMPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR18, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R3, SR_TID.Y &wr=0x2 ?trans6;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
HFMA2 R26, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR16, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R2, SR_TID.X &wr=0x4 ?trans5;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans8;
S2UR UR5, SR_CTAID.X &wr=0x4 ?trans1;
UISETP.GE.AND UP0, UPT, UR18, 0x1, UPT &req={1} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
LDC R25, c[0x0][0x360] &wr=0x4 ?trans1;
IMAD R0, R0, UR4, R3 &req={2} ?trans2;
IMAD R25, R25, UR5, R2 &req={4} ?WAIT9_END_GROUP;
@!P0 BRA 0xa30 &req={3,0} ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR18, 0x8, UPT ?trans1;
ULOP3.LUT UR7, UR18, 0x7, URZ, 0xc0, !UPT ?trans2;
IMAD R4, R0, UR18, RZ ?trans1;
MOV R24, RZ ?trans1;
MOV R26, RZ ?trans1;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P1, PT, RZ, UR7, PT ?WAIT12_END_GROUP;
@!P0 BRA 0x510 ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
USHF.L.U32 UR4, UR18, 0x1, URZ ?trans1;
ULOP3.LUT UR6, UR18, 0x7ffffff8, URZ, 0xc0, !UPT ?trans1;
MOV R24, RZ ?trans1;
MOV R27, R25 ?trans1;
UIMAD.WIDE.U32 UR4, UR4, 0x4, URZ ?trans1;
UIADD3 UR6, UPT, UPT, -UR6, URZ, URZ ?trans2;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
UIMAD.WIDE.U32 UR8, UR18, 0x14, UR4 ?trans1;
UIMAD.WIDE.U32 UR10, UR18, 0x10, UR4 ?trans1;
UIMAD.WIDE.U32 UR12, UR18, 0xc, UR4 ?trans1;
UIMAD.WIDE.U32 UR14, UR18, 0x8, UR4 ?trans1;
IMAD.WIDE.U32 R2, R4, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
IADD.64 R2, R2, 0x10 ?trans2;
IADD.64 R8, R6.reuse, UR8 &req={1} ?trans2;
IADD.64 R10, R6.reuse, UR10 ?trans2;
IADD.64 R12, R6.reuse, UR12 ?trans2;
IADD.64 R14, R6, UR14 ?WAIT8_END_GROUP;
IMAD.WIDE R20, R27, 0x4, R6 ?trans1;
MOV R17, UR18 ?trans1;
LDG.E R29, desc[UR16][R2.64+-0x10] &wr=0x2 ?trans4;
IMAD.WIDE.U32 R16, R17, 0x4, R20 ?trans1;
LDG.E R30, desc[UR16][R20.64] &wr=0x2 ?trans1;
IADD.64 R22, R20, UR4 ?WAIT3_END_GROUP;
LDG.E R31, desc[UR16][R16.64] &rd=0x0 &wr=0x3 ?trans1;
IADD.64 R36, R16, UR4 ?WAIT3_END_GROUP;
LDG.E R28, desc[UR16][R2.64+-0xc] &wr=0x3 ?trans4;
LDG.E R32, desc[UR16][R22.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R16, R27, 0x4, R14 &req={0} ?WAIT3_END_GROUP;
LDG.E R35, desc[UR16][R2.64+-0x8] &wr=0x4 ?trans1;
IMAD.WIDE R18, R27, 0x4, R12 ?WAIT3_END_GROUP;
LDG.E R34, desc[UR16][R36.64] &wr=0x5 ?trans4;
LDG.E R33, desc[UR16][R2.64+-0x4] &wr=0x5 ?trans1;
IMAD.WIDE R20, R27, 0x4, R10 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR16][R16.64] &wr=0x5 ?trans1;
IMAD.WIDE R22, R27, 0x4, R8 &req={1} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR16][R18.64] &wr=0x5 ?trans4;
LDG.E R37, desc[UR16][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E R17, desc[UR16][R2.64] &wr=0x5 ?trans4;
LDG.E R20, desc[UR16][R20.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR16][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R23, desc[UR16][R22.64] &wr=0x5 ?trans4;
LDG.E R36, desc[UR16][R2.64+0xc] &rd=0x0 &wr=0x5 ?trans1;
UIADD3 UR6, UPT, UPT, UR6, 0x8, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR6, PT ?trans1;
IADD3 R24, PT, PT, R24, 0x8, RZ ?trans1;
IADD.64 R2, R2, 0x20 &req={0} ?trans2;
IMAD R29, R29, R30, R26 &req={2} ?WAIT4_END_GROUP;
IMAD R28, R28, R31, R29 &req={3} ?WAIT4_END_GROUP;
IMAD R28, R35, R32, R28 &req={4} ?WAIT4_END_GROUP;
IMAD R28, R33, R34, R28 &req={5} ?WAIT4_END_GROUP;
IMAD R16, R17, R16, R28 ?WAIT4_END_GROUP;
IMAD R16, R37, R18, R16 ?trans1;
MOV R18, UR18 ?WAIT3_END_GROUP;
IMAD R16, R19, R20, R16 ?trans2;
IMAD R27, R18, 0x8, R27 ?trans2;
IMAD R26, R36, R23, R16 ?trans1;
@P0 BRA 0x290 ?trans6;
@!P1 BRA 0xa30 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR7, 0x4, UPT ?trans1;
ULOP3.LUT UR4, UR18, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR4, PT ?WAIT12_END_GROUP;
@!P1 BRA 0x7d0 ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
MOV R2, R24.reuse ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
UIADD3 UR5, UPT, UPT, UR18, UR18, URZ ?trans1;
IADD3 R11, PT, PT, R4, R24, RZ ?trans1;
IMAD R13, R24, UR18, R25 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x2 ?trans1;
IADD.64 R16, R4, R2 ?trans2;
MOV R10, UR18 ?trans1;
MOV R14, UR5 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R8, R11, 0x4, R8 &req={0} ?trans1;
MOV R11, RZ ?WAIT5_END_GROUP;
IADD.64 R14, R10, R14 ?trans2;
IMAD.WIDE R2, R13, 0x4, R6 &req={2} ?trans1;
MOV R13, UR18 ?trans1;
LEA R6, P1, R16.reuse, UR6, 0x2 &req={1} ?trans1;
LDG.E R9, desc[UR16][R8.64] &wr=0x2 ?trans1;
MOV R11, UR5 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R2 ?trans1;
LEA.HI.X R7, R16, UR7, R17, 0x2, P1 ?trans1;
LDG.E R18, desc[UR16][R2.64] &wr=0x2 ?trans1;
LEA R16, P1, R14, R2, 0x2 ?trans1;
IMAD.WIDE.U32 R10, R11, 0x4, R2 ?WAIT2_END_GROUP;
LDG.E R12, desc[UR16][R12.64] &wr=0x3 ?trans1;
LEA.HI.X R17, R14, R3, R15, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R20, desc[UR16][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E R10, desc[UR16][R10.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR16][R6.64+0x8] &wr=0x4 ?trans4;
LDG.E R22, desc[UR16][R6.64+0xc] &wr=0x5 ?trans4;
LDG.E R16, desc[UR16][R16.64] &wr=0x5 ?trans1;
IADD3 R24, PT, PT, R24, 0x4, RZ ?trans1;
IMAD R9, R9, R18, R26 &req={2} ?WAIT4_END_GROUP;
IMAD R9, R20, R12, R9 &req={3} ?WAIT4_END_GROUP;
IMAD R9, R14, R10, R9 &req={4} ?WAIT4_END_GROUP;
IMAD R26, R22, R16, R9 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0xa30 ?trans5;
MOV R2, UR4 ?trans1;
ULOP3.LUT UR4, UR18, 0x1, URZ, 0xc0, !UPT ?trans1;
LDC.64 R10, c[0x0][0x388] &wr=0x0 ?trans3;
ISETP.NE.AND P0, PT, R2, 0x1, PT ?trans1;
UISETP.NE.U32.AND UP0, UPT, UR4, 0x1, UPT ?WAIT4_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x1 ?trans2;
PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT5_END_GROUP;
@!UP0 LDCU.128 UR4, c[0x0][0x380] &wr=0x2 ?trans1;
@P0 LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
@P0 IADD3 R19, PT, PT, R4, R24.reuse, RZ ?trans1;
@P0 IMAD R21, R24.reuse, UR18, R25 ?trans1;
@P0 MOV R8, R24 ?trans1;
@P0 IADD3 R24, PT, PT, R24, 0x2, RZ ?trans1;
@P0 MOV R9, RZ ?trans1;
@P0 MOV R5, RZ ?trans1;
@P0 IMAD.WIDE R10, R21, 0x4, R10 &req={0} ?trans1;
@!P2 IADD3 R17, PT, PT, R4, R24, RZ ?WAIT3_END_GROUP;
@P0 IADD.64 R12, R4, R8 ?trans2;
@P0 IMAD.WIDE.U32 R8, R19, 0x4, R6 &req={1} ?trans1;
MOV.64 R14, UR4 &req={2} ?trans2;
MOV.64 R6, UR6 ?WAIT4_END_GROUP;
@!P2 IMAD.WIDE.U32 R4, R17, 0x4, R14 ?trans1;
MOV R17, UR18 ?trans1;
@P0 LEA R2, P1, R12, R2, 0x2 &req={3} ?trans1;
@P0 LDG.E R9, desc[UR16][R8.64] &wr=0x2 ?trans1;
@!P2 IMAD R15, R24, UR18, R25 ?trans2;
@P0 LEA.HI.X R3, R12, R3, R13, 0x2, P1 ?trans1;
@P0 IMAD.WIDE.U32 R12, R17, 0x4, R10 ?trans1;
@!P2 LDG.E R5, desc[UR16][R4.64] &wr=0x3 ?trans4;
@P0 LDG.E R10, desc[UR16][R10.64] &wr=0x2 ?trans1;
@!P2 IMAD.WIDE R6, R15, 0x4, R6 ?WAIT3_END_GROUP;
@P0 LDG.E R3, desc[UR16][R2.64+0x4] &wr=0x4 ?trans4;
@P0 LDG.E R12, desc[UR16][R12.64] &wr=0x4 ?trans4;
@!P2 LDG.E R6, desc[UR16][R6.64] &wr=0x3 ?trans1;
@P0 IMAD R14, R9, R10, R26 &req={2} ?WAIT4_END_GROUP;
@P0 IMAD R26, R3, R12, R14 &req={4} ?WAIT4_END_GROUP;
@!P2 IMAD R26, R5, R6, R26 &req={3} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R25, R0, UR18, R25 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R25, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR16][R2.64], R26 ?trans1;
EXIT ?trans5;
BRA 0xa80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpuMM(int*, int*, int*, int)
_Z5gpuMMPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
v_mul_lo_u32 v1, v2, s2
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpuMM | 4,381 | 1,179 | stackv2-00000-of-00015 |
// Demangled: threadWork(long*, int, unsigned long, unsigned int*, unsigned long*)
Function : _Z10threadWorkPlimPjPm
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x4][RZ] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x2 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x3 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x2 ?trans1;
LDG.E.64 R4, desc[UR4][R4.64] &req={1} &wr=0x4 ?trans7;
LDC R0, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD R2, R2, UR6, R3 &req={2} ?WAIT2_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR8 &req={3} ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R0.reuse, -0x1, RZ &req={1} ?trans1;
ISETP.GE.AND P0, PT, R0, 0x1, PT ?WAIT3_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans2;
LOP3.LUT R5, R5, R3, RZ, 0x3c, !PT &req={4} ?trans2;
LOP3.LUT R4, R4, R2, RZ, 0x3c, !PT ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R5, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GT.S64.OR P0, PT, R4, R6, P0 ?WAIT14_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x2a0 ?trans1;
MOV R0, R6 ?trans1;
MOV R11, RZ ?WAIT7_END_GROUP;
IADD3 R6, PT, PT, R0, -R11, RZ ?WAIT4_END_GROUP;
LEA.HI R6, R6, R6, RZ, 0x1 ?WAIT4_END_GROUP;
LEA.HI.SX32 R13, R6, R11, 0x1f ?WAIT5_END_GROUP;
IMAD.WIDE R6, R13, 0x8, R8 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R6, desc[UR4][R6.64] &wr=0x2 ?trans1;
BSSY.RELIABLE B1, 0x260 ?trans1;
ISETP.GT.S64.AND P0, PT, R6, R4, PT &req={2} ?WAIT14_END_GROUP;
@P0 IADD3 R0, PT, PT, R13, -0x1, RZ ?trans1;
@P0 BRA 0x250 ?trans6;
ISETP.GE.S64.AND P0, PT, R6, R4, PT ?WAIT14_END_GROUP;
@P0 BREAK.RELIABLE B1 ?trans5;
@P0 BRA 0x290 ?trans5;
IADD3 R11, PT, PT, R13, -0x1, RZ ?WAIT7_END_GROUP;
BSYNC.RELIABLE B1 ?trans5;
ISETP.GT.AND P0, PT, R11, R0, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
BRA 0x180 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
ISETP.NE.AND P0, PT, R13, -0x1, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
S2R R5, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R6, c[0x0][0x3a0] &wr=0x1 ?trans1;
FLO.U32 R0, UR6 &wr=0x0 ?trans1;
POPC R11, UR6 &wr=0x2 ?trans1;
ISETP.EQ.U32.AND P0, PT, R0, R5, PT &req={0} ?WAIT5_END_GROUP;
LDC.64 R4, c[0x0][0x398] &wr=0x2 ?trans8;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R5, desc[UR4][R4.64], R11 &req={2} &wr=0x2 ?trans1;
S2R R8, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R8, R8, UR6, RZ, 0xc0, !PT &req={0} ?WAIT6_END_GROUP;
POPC R8, R8 &wr=0x0 ?trans1;
SHFL.IDX PT, R9, R5, R0, 0x1f &req={2} &wr=0x0 ?trans2;
IADD3 R9, PT, PT, R9, R8, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R6, R9, 0x8, R6 &req={1} ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R6.64], R2 ?trans1;
EXIT ?trans5;
BRA 0x3e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: threadWork(long*, int, unsigned long, unsigned int*, unsigned long*)
_ZL10threadWorkPlimPjPm:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, hardcoded@rel32@lo+4
s_addc_u32 s3, s3, hardcoded@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b32 s9, s[0:1], 0x8
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_add_co_u32 v0, s4, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v1, null, 0, s5, s4
s_add_i32 s4, s9, -1
v_xor_b32_e32 v2, s2, v0
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, s3, v1
s_cmp_gt_i32 s9, 0
s_cselect_b32 s3, -1, 0
v_cmp_lt_i64_e32 vcc_lo, -1, v[2:3]
v_cmp_ge_i64_e64 s2, s[4:5], v[2:3]
s_mov_b32 s5, 0
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_15
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v8, s4
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v8, v7
s_mov_b32 s4, 0
s_mov_b32 s8, exec_lo
v_lshrrev_b32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_ashrrev_i32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v7
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_le_i64_e64 v[5:6], v[2:3]
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_6
s_mov_b32 s9, exec_lo
v_cmpx_lt_i64_e64 v[5:6], v[2:3]
s_xor_b32 s9, exec_lo, s9
s_mov_b32 s4, exec_lo
v_add_nc_u32_e32 v7, -1, v4
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s4, s4, exec_lo
.LBB0_6:
s_and_not1_saveexec_b32 s8, s8
v_add_nc_u32_e32 v8, -1, v4
s_or_b32 s4, s4, exec_lo
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s8, -1
s_and_saveexec_b32 s9, s4
v_cmp_gt_i32_e32 vcc_lo, v7, v8
v_mov_b32_e32 v4, -1
s_or_not1_b32 s8, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, exec_lo, s8
s_or_b32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_15
s_mov_b32 s1, exec_lo
s_mov_b32 s0, exec_lo
v_mbcnt_lo_u32_b32 v2, s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s1, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s1
global_atomic_add_u32 v3, v3, v4, s[6:7] glc
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s0, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| threadWork | 1,516 | 1,989 | stackv2-00000-of-00015 |
// Demangled: vDotProd_d(int*, int*, int*, int)
Function : _Z10vDotProd_dPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR5, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR4, PT &req={2} ?trans1;
ULEA.HI UR4, UR4, UR4, URZ, 0x1 ?WAIT12_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
USHF.R.S32.HI UR4, URZ, 0x1, UR4 ?trans1;
IMAD.HI R0, R9.reuse, 0x66666667, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x1d0 ?trans3;
ISETP.LT.AND P0, PT, R9, UR4, PT ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
SHF.R.U32.HI R7, RZ, 0x1f, R0 ?WAIT4_END_GROUP;
LEA.HI.SX32 R0, R0, R7, 0x1e ?WAIT5_END_GROUP;
IMAD R8, R0, -0xa, R9 ?trans2;
@P0 IADD3 R11, PT, PT, R9, 0x1, RZ ?WAIT3_END_GROUP;
IADD3 R13, PT, PT, R8, 0x1, RZ ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?trans1;
@P0 BRA 0x1c0 &req={1} ?trans6;
ISETP.LE.AND P0, PT, R9, UR4, PT ?trans1;
MOV R11, R9 ?WAIT12_END_GROUP;
@!P0 IADD3 R0, PT, PT, -R9, UR4, RZ ?WAIT4_END_GROUP;
@!P0 IADD3 R11, PT, PT, R9, R0, R0 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
STG.E desc[UR6][R2.64], R11 ?trans1;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans3;
STG.E desc[UR6][R4.64], R13 ?trans4;
LDG.E R15, desc[UR6][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
IMAD R15, R8, R15, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 ?trans1;
EXIT ?trans5;
BRA 0x250;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vDotProd_d(int*, int*, int*, int)
_Z10vDotProd_dPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_mov_b32_e32 v0, v1
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_8
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_ashr_i32 s3, s2, 1
s_mov_b32 s2, exec_lo
v_cmpx_le_i32_e64 s3, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_5
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e64 s3, v1
v_sub_nc_u32_e32 v0, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 1, v1
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_and_not1_saveexec_b32 s2, s2
v_add_nc_u32_e32 v0, 1, v1
s_or_b32 exec_lo, exec_lo, s2
v_mul_hi_i32 v2, 0x66666667, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v4, 2, v2
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mul_lo_u32 v6, v4, 10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v1, v6
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, 1, v1
global_store_b32 v[4:5], v0, off
global_store_b32 v[6:7], v1, off
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vDotProd_d | 959 | 1,111 | stackv2-00000-of-00015 |
// Demangled: apply_kernel(MscData, float const*, float*)
Function : _Z12apply_kernel7MscDataPKfPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?WAIT4_END_GROUP;
FFMA R7, R2, R8, R9 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xc0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: apply_kernel(MscData, float const*, float*)
_Z12apply_kernel7MscDataPKfPf:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[6:7]
s_waitcnt vmcnt(0)
v_fma_f32 v1, s4, v1, s5
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| apply_kernel | 377 | 174 | stackv2-00000-of-00015 |
// Demangled: convolution_tiling(float const*, float const*, float*)
Function : _Z18convolution_tilingPKfS0_Pf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.Y &wr=0x1 ?trans7;
S2UR UR8, SR_CTAID.X &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
S2R R7, SR_TID.Y &wr=0x1 ?trans2;
IMAD R0, R0, 0x72, R7 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R0.reuse, 0x20d, PT ?trans1;
VIMNMX.U32 R2, R0, 0x206, PT ?WAIT5_END_GROUP;
VIMNMX.U32 R2, R2, 0x7, !PT ?WAIT5_END_GROUP;
IADD3 R2, PT, PT, R2, -0x7, RZ ?trans2;
@!P1 LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans2;
@!P1 LEA R3, R2, UR8, 0x9 &req={2} ?WAIT5_END_GROUP;
@!P1 IMAD.WIDE.U32 R4, R3, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R5, desc[UR6][R4.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x206, PT ?trans1;
IADD3 R0, PT, PT, R7, -0x7, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R0, 0x71, P0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R10, R7, UR4, 0x2 ?WAIT5_END_GROUP;
@!P1 STS [R10], R5 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT &req={0} ?trans5;
LDC.64 R20, c[0x0][0x388] &wr=0x0 ?trans1;
LDS R0, [R10+-0x1c] &wr=0x2 ?trans4;
LDG.E R15, desc[UR6][R20.64] &req={0} &wr=0x2 ?trans4;
LDG.E R22, desc[UR6][R20.64+0x4] &wr=0x3 ?trans4;
LDG.E R23, desc[UR6][R20.64+0x8] &wr=0x4 ?trans4;
LDG.E R25, desc[UR6][R20.64+0xc] &wr=0x5 ?trans4;
LDG.E R27, desc[UR6][R20.64+0x10] &wr=0x5 ?trans4;
LDG.E R17, desc[UR6][R20.64+0x14] &wr=0x5 ?trans4;
LDG.E R13, desc[UR6][R20.64+0x18] &wr=0x5 ?trans4;
LDG.E R11, desc[UR6][R20.64+0x1c] &wr=0x5 ?trans4;
LDG.E R3, desc[UR6][R20.64+0x20] &wr=0x5 ?trans4;
LDG.E R9, desc[UR6][R20.64+0x24] &wr=0x5 ?trans4;
LDG.E R8, desc[UR6][R20.64+0x28] &wr=0x5 ?trans4;
LDG.E R7, desc[UR6][R20.64+0x2c] &wr=0x5 ?trans4;
LDG.E R6, desc[UR6][R20.64+0x30] &wr=0x5 ?trans4;
LDG.E R5, desc[UR6][R20.64+0x34] &req={1} &wr=0x5 ?trans4;
LDG.E R4, desc[UR6][R20.64+0x38] &rd=0x0 &wr=0x5 ?trans4;
LDS R19, [R10+-0x18] &wr=0x3 ?trans4;
LDS R24, [R10+-0x14] &wr=0x4 ?trans4;
LDS R26, [R10+-0x10] &wr=0x5 ?trans4;
LDS R28, [R10+-0xc] &wr=0x1 ?trans4;
LDS R29, [R10+-0x8] &wr=0x1 ?trans4;
LDS R18, [R10+-0x4] &wr=0x1 ?trans4;
LDS R16, [R10] &wr=0x1 ?trans4;
LDS R14, [R10+0x4] &wr=0x1 ?trans4;
LDS R12, [R10+0x8] &wr=0x1 ?trans4;
LDS R21, [R10+0x18] &req={0} ?trans4;
LDS R20, [R10+0x1c] ?trans1;
FFMA R0, R0, R15, RZ &req={2} ?WAIT3_END_GROUP;
LDS R15, [R10+0xc] &wr=0x0 ?trans1;
FFMA R19, R19, R22, R0 &req={3} ?WAIT3_END_GROUP;
LDS R0, [R10+0x10] &wr=0x2 ?trans1;
FFMA R23, R24, R23, R19 &req={4} ?WAIT3_END_GROUP;
LDS R19, [R10+0x14] &wr=0x3 ?trans1;
FFMA R23, R26, R25, R23 &req={5} ?WAIT4_END_GROUP;
FFMA R28, R28, R27, R23 &req={1} ?WAIT4_END_GROUP;
FFMA R17, R29, R17, R28 ?WAIT4_END_GROUP;
FFMA R13, R18, R13, R17 ?WAIT4_END_GROUP;
FFMA R11, R16, R11, R13 ?trans2;
LDC.64 R16, c[0x0][0x390] &wr=0x1 ?trans2;
FFMA R3, R14, R3, R11 ?WAIT4_END_GROUP;
FFMA R12, R12, R9, R3 ?trans1;
LEA R3, R2, UR8, 0x9 ?WAIT3_END_GROUP;
FFMA R15, R15, R8, R12 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, R7, R15 &req={2} ?WAIT4_END_GROUP;
FFMA R0, R19, R6, R0 &req={3} ?WAIT4_END_GROUP;
FFMA R5, R21, R5, R0 ?trans1;
IMAD.WIDE.U32 R16, R3, 0x4, R16 &req={1} ?WAIT4_END_GROUP;
FFMA R5, R20, R4, R5 ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x4b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: convolution_tiling(float const*, float const*, float*)
_Z18convolution_tilingPKfS0_Pf:
v_bfe_u32 v1, v0, 10, 10
s_mulk_i32 s15, 0x72
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s0, exec_lo
v_add3_u32 v2, v1, s15, -7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_i32_e32 v0, 0x1ff, v2
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_lshlrev_b32_e32 v0, 9, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cmpx_gt_i32_e32 0x207, v2
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s14, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_lt_u32_e32 6, v1
s_cbranch_execz .LBB0_7
v_cmp_gt_u32_e32 vcc_lo, 0x79, v1
v_cmp_gt_i32_e64 s0, 0x200, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v1
s_movk_i32 s0, 0xffe4
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s0, v2
s_load_b32 s1, s[6:7], 0x0
s_add_i32 s0, s0, 4
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
ds_load_b32 v3, v3
s_cmp_eq_u32 s0, 32
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, s1, v3
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v2, s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| convolution_tiling | 2,066 | 1,192 | stackv2-00000-of-00015 |
// Demangled: vectoradd(int, float const*, float const*, float*)
Function : _Z9vectoraddiPKfS0_Pf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R8, -RZ, RZ, 0, 0 ?trans2;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ &req={1} &rd=0x0 ?trans2;
LDC.64 R4, c[0x0][0x388] &req={1} &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD.WIDE R4, R0, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
LDG.E R9, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R6, R0, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R10, desc[UR4][R6.64] &wr=0x3 ?trans2;
FADD R9, R9, R10 &req={3} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R6.64] &wr=0x2 ?trans2;
FADD R11, R10, R11 &req={2} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R6.64] &wr=0x3 ?trans2;
FADD R13, R10, R13 &req={3} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R6.64] &wr=0x4 ?trans2;
FADD R15, R10, R15 &req={4} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x5 ?trans2;
FADD R13, R10, R13 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x5 ?trans2;
FADD R15, R10, R15 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x5 ?trans2;
FADD R13, R10, R13 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x5 ?trans2;
FADD R15, R10, R15 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x5 ?trans2;
FADD R13, R10, R13 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x5 ?trans2;
FADD R15, R10, R15 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x5 ?trans2;
FADD R13, R10, R13 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x5 ?trans2;
FADD R15, R10, R15 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x5 ?trans2;
FADD R13, R10, R13 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x5 ?trans2;
FADD R15, R10, R15 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x2 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x5 ?trans2;
FADD R13, R10, R13 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x3 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x5 ?trans2;
FADD R15, R10, R15 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x4 ?trans4;
LDG.E R9, desc[UR4][R4.64] &req={1} &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64] &wr=0x5 ?trans2;
FADD R9, R9, R10 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R9 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64] &req={2} &wr=0x5 ?trans2;
FADD R11, R10, R11 &req={5} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R11 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R6.64] &req={3} &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x20, RZ ?trans1;
FADD R13, R10, R13 &req={2} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R13 &rd=0x1 ?trans4;
LDG.E R10, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R6.64] &req={4} &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R8, 0x186a0, PT ?trans1;
FADD R15, R10, R15 &req={2} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR4][R2.64], R15 &rd=0x1 ?trans7;
@P0 BRA 0xd0 ?trans5;
EXIT ?trans5;
BRA 0x950;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vectoradd(int, float const*, float const*, float*)
_Z9vectoraddiPKfS0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mov_b32 s0, 0
global_store_b32 v[0:1], v6, off
.LBB0_2:
global_load_b32 v6, v[2:3], off
global_load_b32 v8, v[4:5], off
global_load_b32 v7, v[0:1], off
s_mov_b32 s1, 0
s_waitcnt vmcnt(1)
v_add_f32_e32 v8, v6, v8
.LBB0_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v7, v8
global_atomic_cmpswap_b32 v6, v[0:1], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0x186a0
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vectoradd | 4,539 | 889 | stackv2-00000-of-00015 |
// Demangled: calculateAreas(int, int, double, double*)
Function : _Z14calculateAreasiidPd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x380] &wr=0x1 ?trans2;
IADD3 R0, PT, PT, R0, UR4, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
I2F.F64 R2, R0 &wr=0x0 ?trans1;
MOV.64 R8, 0x3fd8000000000000 ?trans2;
BSSY.RECONVERGENT B0, 0x470 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR4 &req={0} &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, -R2, R2, 1 &req={0} &wr=0x0 ?trans2;
MUFU.RSQ64H R7, R3 &req={0} &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R3, -0x3500000, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R6, R6 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R2, -R4, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R4, R8, 0.5 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R6, R4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R4, R6 &req={0} &wr=0x0 ?trans2;
IADD3 R15, PT, PT, R9, -0x100000, RZ &req={0} ?trans1;
MOV R14, R8 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R2, R8 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R10, -R10, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R12, R14, R10 &req={0} &rd=0x0 &wr=0x2 ?trans2;
@!P0 BRA 0x460 &req={2,1,0} ?trans5;
MOV R4, 0x440 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x530 ?trans5;
MOV R4, R6 ?trans1;
MOV R5, R7 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x388] &wr=0x1 ?trans1;
DSETP.GEU.AND P0, PT, R2, 2.2204460492503130808e-16, PT &wr=0x2 ?trans2;
FSEL R2, R4, RZ, P0 &req={2} ?trans1;
FSEL R3, R5, RZ, P0 ?trans1;
IMAD.WIDE R4, R0, 0x8, R6 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R2, R2, UR6 &req={1} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R4.64], R2 &req={0} ?trans1;
EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R6, -0x3400000, PT ?trans1;
MOV R9, R15 ?trans1;
BSSY.RECONVERGENT B1, 0x9d0 ?trans11;
@P1 DFMA.RM R8, R12, R8, R10 &wr=0x0 ?trans2;
@P1 IADD.64 R6, R8, 0x1 &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@P1 DFMA.RP R10, -R8, R6, R2 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@P1 DSETP.GT.AND P0, PT, R10, RZ, PT &req={0} &wr=0x0 ?trans2;
@P1 FSEL R6, R6, R8, P0 &req={0} ?trans1;
@P1 FSEL R7, R7, R9, P0 ?trans1;
@P1 BRA 0x9c0 ?trans6;
DSETP.NE.AND P0, PT, R2, RZ, PT &wr=0x0 ?trans2;
@!P0 BRA 0x9b0 &req={0} ?trans5;
ISETP.GE.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@!P0 MOV.64 R6, 0xfff8000000000000 ?trans2;
@!P0 BRA 0x9c0 ?trans6;
ISETP.GT.AND P0, PT, R3, 0x7fefffff, PT ?WAIT13_END_GROUP;
@P0 BRA 0x9b0 ?trans5;
DMUL R6, R2, 8.11296384146066816958e+31 &wr=0x0 ?trans1;
MOV R8, RZ ?trans1;
MUFU.RSQ64H R9, R7 &req={0} &wr=0x0 ?trans1;
MOV.64 R12, 0x3fd8000000000000 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R6, -R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R10, R12, 0.5 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R8, R10 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R6, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
IADD3 R11, PT, PT, R11, -0x100000, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R8, -R8, R6 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R6, R10, R12, R8 &req={0} &wr=0x0 ?trans2;
IADD3 R7, PT, PT, R7, -0x3500000, RZ &req={0} ?trans1;
BRA 0x9c0 ?trans6;
DADD R6, R2, R2 &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R5, 0x0 ?WAIT4_END_GROUP;
RET.REL.NODEC R4 0x0 &req={1,0} ?trans5;
BRA 0x9f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: calculateAreas(int, int, double, double*)
_Z14calculateAreasiidPd:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[1:2], v0
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[1:2], v[1:2], s[0:1]
v_fma_f64 v[1:2], -v[1:2], v[1:2], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[1:2], v3
v_rsq_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_mul_f64 v[7:8], v[3:4], v[5:6]
v_mul_f64 v[5:6], v[5:6], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 0.5
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[5:6], v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[3:4]
v_fma_f64 v[7:8], v[9:10], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[3:4]
v_fma_f64 v[5:6], v[9:10], v[5:6], v[7:8]
v_cndmask_b32_e64 v7, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[5:6], v[5:6], v7
v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v3, v5, v3
v_cmp_ngt_f64_e32 vcc_lo, 0x3cb00000, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, 0, v4 :: v_dual_cndmask_b32 v1, 0, v3
v_mul_f64 v[2:3], v[1:2], s[0:1]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| calculateAreas | 2,679 | 1,258 | stackv2-00000-of-00015 |
// Demangled: summation_kernel(int, float*)
Function : _Z16summation_kerneliPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x1 ?trans7;
LDC R4, c[0x0][0x360] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x2270 ?trans1;
MOV R6, RZ ?trans1;
UI2F.U32.RP UR4, UR5 &req={1} ?WAIT2_END_GROUP;
ISETP.NE.U32.AND P2, PT, RZ, UR5, PT ?WAIT7_END_GROUP;
MUFU.RCP R0, UR4 &wr=0x1 ?trans2;
LDCU UR4, c[0x0][0x370] &wr=0x2 ?trans1;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={1} ?trans1;
IMAD R0, R4, UR4, RZ &req={2} ?trans1;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x2 &wr=0x3 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={2} ?trans1;
IADD3 R5, PT, PT, RZ, -R3, RZ &req={3} ?WAIT5_END_GROUP;
IMAD R5, R5, UR5, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R5, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R3, R0, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R5, UR5, R0 ?trans2;
S2R R5, SR_TID.X &wr=0x1 ?trans3;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT ?WAIT13_END_GROUP;
@P0 IADD3 R0, PT, PT, R0, -UR5, RZ ?trans2;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, UR5, PT ?trans1;
IMAD R0, R4, UR4, R5 &req={1} ?WAIT12_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R3, RZ, UR5, RZ, 0x33, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
IMAD R4, R0.reuse, R3.reuse, R3 ?trans2;
IMAD R2, R0, R3, RZ ?WAIT3_END_GROUP;
IADD3 R7, PT, PT, R4, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R7, R2, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x2260 &req={1,0} ?trans5;
MOV R3, R4 ?trans1;
IADD3 R4, PT, PT, R2, -0x1, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x990 ?trans3;
IADD3 R5, PT, PT, R3, -0x2, RZ ?WAIT5_END_GROUP;
VIMNMX.U32 R4, R4, R5, PT ?WAIT5_END_GROUP;
LOP3.LUT R6, RZ, R4.reuse, RZ, 0x33, !PT ?trans2;
IADD3 R5, PT, PT, R5, -R4, RZ ?trans2;
IADD3 R6, PT, PT, R3, R6, RZ ?WAIT4_END_GROUP;
LOP3.LUT P0, R8, R6, 0x3, RZ, 0xc0, !PT ?trans1;
MOV R6, RZ ?WAIT12_END_GROUP;
@!P0 BRA 0x980 ?trans5;
HFMA2 R6, -RZ, RZ, 0, 0 ?trans1;
IADD3 R4, PT, PT, -R8, RZ, RZ ?trans1;
MOV R14, R3 ?WAIT7_END_GROUP;
LOP3.LUT R3, R7, 0x1, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B3, 0x940 ?trans1;
IADD3 R4, PT, PT, R4, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.NE.U32.AND P1, PT, R3, 0x1, PT ?trans1;
MOV R3, R7 ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT11_END_GROUP;
@P1 BRA 0x680 ?trans5;
I2F.F64 R8, R3 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B4, 0x610 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R14, R8, 1 &req={0} &wr=0x0 ?trans2;
IADD3 R8, PT, PT, R15, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P1, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R15 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R14, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R14, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P1 BRA 0x600 &req={1,0} ?trans5;
LOP3.LUT R7, R15, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R14 ?trans1;
MOV R17, R15 ?trans1;
MOV R14, 0x600 ?trans1;
IADD3 R12, PT, PT, R7, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B4 ?trans5;
F2F.F64.F32 R6, R6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R6, -R10 &req={0} &rd=0x2 &wr=0x3 ?trans2;
BRA 0x930 &req={3,2} ?trans5;
I2F.F64 R14, R14 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B4, 0x8d0 ?trans1;
IADD3 R8, PT, PT, R15, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P1, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R15 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R14, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R14, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P1 BRA 0x8c0 &req={1,0} ?trans5;
LOP3.LUT R7, R15, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R14 ?trans1;
MOV R17, R15 ?trans1;
MOV R14, 0x8c0 ?trans1;
IADD3 R12, PT, PT, R7, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B4 ?trans5;
F2F.F64.F32 R6, R6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R6, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F32.F64 R6, R10 &req={1,0} &rd=0x0 &wr=0x1 ?trans1;
IADD3 R7, PT, PT, R3, -0x1, RZ ?trans1;
MOV R14, R3 ?trans1;
@P0 BRA 0x300 &req={1,0} ?trans6;
BSYNC.RECONVERGENT B2 ?trans5;
ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x2260 ?trans5;
LOP3.LUT R15, R7, 0x1, RZ, 0xc0, !PT ?WAIT7_END_GROUP;
ISETP.NE.AND P0, PT, R15, RZ, PT ?trans1;
BSSY.RECONVERGENT B2, 0x1000 ?WAIT12_END_GROUP;
@P0 BRA 0xcd0 &req={0} ?trans5;
I2F.F64 R12, R3 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B3, 0xc60 ?trans1;
IADD3 R4, PT, PT, R13, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R5, R13 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, -R12, R4, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R4, R8, R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R12, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R10, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xc50 &req={1,0} ?trans5;
LOP3.LUT R3, R13, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R12 ?trans1;
MOV R17, R13 ?trans1;
MOV R14, 0xc30 ?trans1;
IADD3 R12, PT, PT, R3, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
MOV R8, R10 ?trans1;
MOV R9, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R4, R6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R4, R8 &req={0} &rd=0x2 &wr=0x3 ?trans2;
BRA 0xff0 &req={3,2} ?trans5;
I2F.F64 R4, R7 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B3, 0xf90 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R12, R4, 1 &req={0} &wr=0x0 ?trans2;
IADD3 R4, PT, PT, R13, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R4|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R5, R13 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, -R12, R4, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R4, R8, R4 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R12, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R8, R10, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xf80 &req={1,0} ?trans5;
LOP3.LUT R3, R13, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R12 ?trans1;
MOV R17, R13 ?trans1;
MOV R14, 0xf60 ?trans1;
IADD3 R12, PT, PT, R3, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
MOV R4, R10 ?trans1;
MOV R5, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R8, R6 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R4, R8, -R4 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B2 ?trans5;
ISETP.NE.AND P0, PT, R15, RZ, PT ?trans1;
F2F.F32.F64 R4, R4 &req={1} &rd=0x1 &wr=0x2 ?trans1;
BSSY.RECONVERGENT B2, 0x1600 ?trans1;
IADD3 R3, PT, PT, R7, -0x1, RZ ?WAIT10_END_GROUP;
@P0 BRA 0x1350 &req={2,1} ?trans5;
I2F.F64 R8, R3 &req={0} &wr=0x0 ?trans1;
BSSY.RECONVERGENT B3, 0x12e0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R8, 1 &req={0} &wr=0x0 ?trans2;
IADD3 R8, PT, PT, R17, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R17 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R16, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R16, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x12d0 &req={1,0} ?trans5;
LOP3.LUT R5, R17, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R16 ?trans1;
MOV R14, 0x12d0 ?trans2;
IADD3 R12, PT, PT, R5, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R4, R4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R4, -R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BRA 0x15f0 &req={1,0} ?trans5;
I2F.F64 R16, R7 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B3, 0x1590 ?trans1;
IADD3 R8, PT, PT, R17, 0x300402, RZ &req={1,0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R17 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R16, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R16, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1580 &req={1,0} ?trans5;
LOP3.LUT R5, R17, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R16 ?trans1;
MOV R14, 0x1580 ?trans2;
IADD3 R12, PT, PT, R5, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R4, R4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R4, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B2 ?trans5;
ISETP.NE.AND P0, PT, R15, RZ, PT ?trans1;
F2F.F32.F64 R5, R10 &req={1,0} &rd=0x0 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B2, 0x1c20 ?trans1;
IADD3 R4, PT, PT, R7, -0x2, RZ ?WAIT10_END_GROUP;
@!P0 BRA 0x1950 &req={1,0} ?trans5;
I2F.F64 R8, R4 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B3, 0x18e0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R8, 1 &req={0} &wr=0x0 ?trans2;
IADD3 R8, PT, PT, R17, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R17 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R16, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R16, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x18d0 &req={1,0} ?trans5;
LOP3.LUT R3, R17, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R16 ?trans1;
MOV R14, 0x18d0 ?trans2;
IADD3 R12, PT, PT, R3, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R8, R5 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, -R10 &req={0} &rd=0x2 &wr=0x3 ?trans2;
BRA 0x1c10 &req={3,2} ?trans5;
I2F.F64 R16, R3 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B3, 0x1bb0 ?trans1;
IADD3 R8, PT, PT, R17, 0x300402, RZ &req={0} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R17 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R16, R8, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R16, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1ba0 &req={1,0} ?trans5;
LOP3.LUT R3, R17, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R16 ?trans1;
MOV R14, 0x1b80 ?trans2;
IADD3 R12, PT, PT, R3, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
MOV R8, R10 ?trans1;
MOV R9, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R10, R5 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R10, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B2 ?trans5;
ISETP.NE.AND P0, PT, R15, RZ, PT ?trans1;
F2F.F32.F64 R5, R8 &req={1} &rd=0x1 &wr=0x2 ?trans1;
BSSY.RECONVERGENT B2, 0x2220 ?trans1;
IADD3 R3, PT, PT, R7, -0x3, RZ ?WAIT10_END_GROUP;
@P0 BRA 0x1f70 &req={2,1} ?trans5;
I2F.F64 R8, R3 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B3, 0x1f00 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R16, R8, 1 &req={1} &wr=0x1 ?trans2;
IADD3 R8, PT, PT, R17, 0x300402, RZ &req={1} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R17 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R16, R8, 1 &req={1,0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R16, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x1ef0 &req={1,0} ?trans5;
LOP3.LUT R4, R17, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R16 ?trans1;
MOV R14, 0x1ef0 ?trans2;
IADD3 R12, PT, PT, R4, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R4, R5 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R4, -R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BRA 0x2210 &req={1,0} ?trans5;
I2F.F64 R16, R4 &wr=0x1 ?trans1;
BSSY.RECONVERGENT B3, 0x21b0 ?trans1;
IADD3 R8, PT, PT, R17, 0x300402, RZ &req={1} ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, |R8|, 5.8789094863358348022e-39, PT ?trans1;
MUFU.RCP64H R9, R17 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT11_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R16, R8, 1 &req={1,0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, R10, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R16, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R12, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0x21a0 &req={1,0} ?trans5;
LOP3.LUT R4, R17, 0x7fffffff, RZ, 0xc0, !PT ?trans1;
MOV R8, R16 ?trans1;
MOV R14, 0x21a0 ?trans2;
IADD3 R12, PT, PT, R4, -0x100000, RZ ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x22b0 ?trans5;
BSYNC.RECONVERGENT B3 ?trans5;
F2F.F64.F32 R4, R5 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R10, R4, R10 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BSYNC.RECONVERGENT B2 ?trans5;
IADD3 R7, PT, PT, R7, -0x4, RZ ?trans1;
F2F.F32.F64 R6, R10 &req={1} &rd=0x1 &wr=0x2 ?trans4;
ISETP.GE.U32.AND P0, PT, R7, R2, PT ?WAIT13_END_GROUP;
@P0 BRA 0x9c0 &req={2,1} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R6 ?trans1;
EXIT ?trans5;
MOV R9, R17 ?trans1;
BSSY.RECONVERGENT B1, 0x2890 ?trans5;
DSETP.GTU.AND P1, PT, |R8|, +INF , PT &wr=0x0 ?trans2;
@P1 BRA 0x2860 &req={0} ?trans5;
LOP3.LUT R13, R17, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R13, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R10, 0x7fefffff, PT ?WAIT13_END_GROUP;
@P1 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0x3c, !PT ?trans1;
@P1 MOV R10, RZ ?trans1;
@P1 BRA 0x2880 ?trans6;
ISETP.GE.U32.AND P1, PT, R13, 0x1000001, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x2640 ?trans5;
IADD3 R11, PT, PT, R9, -0x3fe00000, RZ ?trans1;
MOV R10, R8 ?WAIT3_END_GROUP;
MUFU.RCP64H R13, R11 &wr=0x0 ?trans3;
DFMA R16, -R10, R12, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R16, R16, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R12, R16, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R10, R16, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R16, R12, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R12, R12, 2.2250738585072013831e-308 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, -R8, R12, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, R8, R12 &req={0} &rd=0x0 &wr=0x1 ?trans2;
BRA 0x2880 &req={1,0} ?trans5;
DMUL R8, R8, 8.11296384146066816958e+31 &wr=0x0 ?trans1;
MOV R10, R12 ?trans1;
MUFU.RCP64H R11, R9 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, -R8, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R12, R12, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R10, R12, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, -R8, R12, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R12, R10, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R10, 8.11296384146066816958e+31 &req={0} &wr=0x0 ?trans2;
BRA 0x2880 &req={0} ?trans5;
LOP3.LUT R11, R9, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R10, R8 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R8, R14 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R8 0x0 ?trans5;
BRA 0x28c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: summation_kernel(int, float*)
_Z16summation_kerneliPf:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x1c
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s6, 0, s2
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s3, s3, s4
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s5, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s5
s_mul_hi_u32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s6
s_mul_hi_u32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s5, s2
s_sub_i32 s3, s3, s6
s_add_i32 s6, s5, 1
s_sub_i32 s7, s3, s2
s_cmp_ge_u32 s3, s2
s_cselect_b32 s4, s6, s5
s_cselect_b32 s3, s7, s3
s_add_i32 s5, s4, 1
s_cmp_ge_u32 s3, s2
s_mov_b32 s3, 0
s_cselect_b32 s2, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s2
v_add_nc_u32_e32 v6, s2, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -1, v6
v_cmpx_ge_u32_e64 v2, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v3, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v3
v_mov_b32_e32 v7, v6
v_add_nc_u32_e32 v6, -1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, 1, v6
v_cmp_eq_u32_e32 vcc_lo, 1, v4
s_and_saveexec_b32 s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_4
v_cvt_f64_i32_e32 v[4:5], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], 1.0
v_div_scale_f64 v[7:8], null, v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
v_div_fixup_f64 v[4:5], v[7:8], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[2:3], -v[4:5]
.LBB0_4:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_6
v_cvt_f64_i32_e32 v[4:5], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[7:8], null, v[4:5], v[4:5], 1.0
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[4:5], 1.0
v_mul_f64 v[13:14], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[7:8], v[4:5], 1.0
v_add_f64 v[4:5], v[4:5], v[2:3]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v3, v[4:5]
v_add_nc_u32_e32 v2, -1, v6
v_cmp_lt_u32_e32 vcc_lo, v2, v0
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| summation_kernel | 11,488 | 2,665 | stackv2-00000-of-00015 |
// Demangled: sumMatrixes(int*, int*, int*, int)
Function : _Z11sumMatrixesPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sumMatrixes(int*, int*, int*, int)
_Z11sumMatrixesPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sumMatrixes | 574 | 578 | stackv2-00000-of-00015 |
// Demangled: getMaxNum(long*, long, long, long*)
Function : _Z9getMaxNumPlllS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R10, SR_TID.X &wr=0x1 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R4, 0x8000000000000000 ?WAIT5_END_GROUP;
LDC R13, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R14, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD R2, R13, UR6, R10 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.S64.AND P0, PT, R2, UR4, PT &req={2} ?trans2;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?WAIT12_END_GROUP;
@!P0 LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans2;
@!P0 LEA R6, P1, R2, R6, 0x3 &req={2} ?WAIT4_END_GROUP;
@!P0 LEA.HI.X R7, R2, R7, RZ, 0x3, P1 ?trans2;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans3;
@!P0 LDG.E.64 R4, desc[UR4][R6.64] &req={1} &wr=0x4 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R8, R2, UR6, R10 &req={2} ?WAIT4_END_GROUP;
IMAD R0, R3, UR6, R9 ?trans1;
LEA R2, P0, R8, R14, 0x3 &req={3} ?WAIT4_END_GROUP;
LEA.HI.X R3, R8, R15, R0, 0x3, P0 ?trans1;
ISETP.GE.U32.AND P0, PT, R13, 0x2, PT ?WAIT4_END_GROUP;
STG.E.64 desc[UR4][R2.64], R4 &req={4} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
@!P0 BRA 0x2a0 &req={0} ?trans5;
MOV R0, R13 ?trans1;
SHF.R.U32.HI R13, RZ, 0x1, R13 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R10, R13, PT ?WAIT13_END_GROUP;
@P0 BRA 0x250 &req={0} ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
IMAD.WIDE.U32 R6, R13, 0x8, R2 ?WAIT6_END_GROUP;
LDG.E.64 R6, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E.64 R4, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
ISETP.GE.S64.AND P0, PT, R4, R6, PT &req={2} ?WAIT14_END_GROUP;
@!P0 STG.E.64 desc[UR4][R2.64], R6 &rd=0x0 ?trans2;
ISETP.GT.U32.AND P0, PT, R0, 0x3, PT ?trans1;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x190 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
EXIT ?trans5;
BRA 0x2c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: getMaxNum(long*, long, long, long*)
_Z9getMaxNumPlllS_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_mov_b32 s10, 0
s_brev_b32 s11, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s15, s8, v[0:1]
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s10
v_mov_b32_e32 v2, s11
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[3:4]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[1:2], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_mul_i32 s0, s15, s5
s_mul_hi_u32 s1, s15, s4
v_lshlrev_b32_e32 v3, 3, v0
s_add_i32 s1, s1, s0
s_mul_i32 s0, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 3
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_cmp_lt_u32 s8, 2
s_waitcnt vmcnt(0)
global_store_b64 v3, v[1:2], s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
v_add_co_u32 v1, s0, s0, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b32 s9, 0
.LBB0_4:
s_mov_b32 s0, s8
s_lshr_b32 s8, s8, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s8, v0
s_cbranch_execz .LBB0_7
s_lshl_b64 s[2:3], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v3, vcc_lo, v1, s2
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[5:6], v[1:2], off
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i64_e32 vcc_lo, v[5:6], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
global_store_b64 v[1:2], v[3:4], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_u32 s0, 4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_8:
s_barrier
buffer_gl0_inv
s_endpgm
| getMaxNum | 1,132 | 1,084 | stackv2-00000-of-00015 |
// Demangled: redukcja(int, float*)
Function : _Z8redukcjaiPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R2, SR_TID.X &wr=0x2 ?trans1;
IADD3 R0, PT, PT, RZ, -UR4, RZ &req={1} ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans3;
R2UR UR5, R0 ?WAIT13_END_GROUP;
UIMAD UR4, UR5, UR4, URZ &req={1} ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, R2, UR4, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R0, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R12, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.AND P0, PT, R0, RZ, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0x760 &req={1} ?trans5;
ISETP.GE.U32.AND P1, PT, R0.reuse, 0x10, PT ?trans1;
LOP3.LUT R20, R0, 0xf, RZ, 0xc0, !PT ?trans1;
MOV.64 R2, RZ ?trans2;
MOV R21, RZ ?trans1;
MOV R12, RZ ?WAIT4_END_GROUP;
ISETP.NE.S64.AND P0, PT, R20, RZ, PT ?WAIT4_END_GROUP;
@!P1 BRA 0x410 ?trans10;
LDCU.64 UR4, c[0x0][0x388] &wr=0x0 ?trans1;
MOV.64 R2, RZ ?trans2;
MOV R12, RZ ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ?trans2;
LOP3.LUT R4, R0, 0xfffffff0, RZ, 0xc0, !PT ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x20, URZ &req={0} ?WAIT6_END_GROUP;
MOV.64 R6, UR4 ?WAIT8_END_GROUP;
LDG.E R13, desc[UR6][R6.64+-0x20] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R6.64+-0x1c] &wr=0x3 ?trans4;
LDG.E R16, desc[UR6][R6.64+-0x18] &wr=0x4 ?trans4;
LDG.E R18, desc[UR6][R6.64+-0x14] &wr=0x5 ?trans4;
LDG.E R22, desc[UR6][R6.64+-0x10] &wr=0x5 ?trans4;
LDG.E R24, desc[UR6][R6.64+-0xc] &wr=0x5 ?trans4;
LDG.E R26, desc[UR6][R6.64+-0x8] &wr=0x5 ?trans4;
LDG.E R28, desc[UR6][R6.64+-0x4] &wr=0x5 ?trans4;
LDG.E R30, desc[UR6][R6.64] &wr=0x5 ?trans4;
LDG.E R32, desc[UR6][R6.64+0x4] &wr=0x5 ?trans4;
LDG.E R34, desc[UR6][R6.64+0x8] &wr=0x5 ?trans4;
LDG.E R36, desc[UR6][R6.64+0xc] &wr=0x5 ?trans4;
LDG.E R9, desc[UR6][R6.64+0x10] &wr=0x5 ?trans4;
LDG.E R10, desc[UR6][R6.64+0x14] &wr=0x5 ?trans4;
LDG.E R11, desc[UR6][R6.64+0x18] &wr=0x5 ?trans4;
LDG.E R8, desc[UR6][R6.64+0x1c] &rd=0x0 &wr=0x5 ?trans1;
IADD.64 R2, R2, 0x10 ?WAIT2_END_GROUP;
IADD.64 R6, R6, 0x40 &req={0} ?trans2;
FADD R13, R13, R12 &req={2} ?WAIT4_END_GROUP;
FADD R13, R13, R14 &req={3} ?WAIT4_END_GROUP;
FADD R13, R13, R16 &req={4} ?WAIT4_END_GROUP;
FADD R13, R13, R18 &req={5} ?WAIT4_END_GROUP;
FADD R13, R13, R22 ?WAIT4_END_GROUP;
FADD R13, R13, R24 ?WAIT4_END_GROUP;
FADD R13, R13, R26 ?WAIT4_END_GROUP;
FADD R13, R13, R28 ?WAIT4_END_GROUP;
FADD R13, R13, R30 ?WAIT4_END_GROUP;
FADD R13, R13, R32 ?WAIT4_END_GROUP;
FADD R13, R13, R34 ?WAIT4_END_GROUP;
FADD R36, R13, R36 ?trans1;
IADD.64 R12, R2, -R4 ?WAIT3_END_GROUP;
FADD R9, R36, R9 ?WAIT3_END_GROUP;
ISETP.NE.S64.AND P1, PT, R12, RZ, PT ?trans2;
FADD R10, R9, R10 ?WAIT4_END_GROUP;
FADD R11, R10, R11 ?WAIT4_END_GROUP;
FADD R12, R11, R8 ?WAIT4_END_GROUP;
@P1 BRA 0x1c0 ?trans5;
@!P0 BRA 0x760 ?trans5;
ISETP.GE.U64.AND P1, PT, R20, 0x8, PT ?trans2;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans1;
LOP3.LUT R16, R0, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R16, RZ, PT ?WAIT6_END_GROUP;
@!P1 BRA 0x5b0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans2;
LEA R4, P1, R2, R4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R5, R2, R5, R3, 0x2, P1 ?WAIT5_END_GROUP;
LDG.E R7, desc[UR6][R4.64] &wr=0x2 ?trans4;
LDG.E R6, desc[UR6][R4.64+0x4] &wr=0x3 ?trans4;
LDG.E R9, desc[UR6][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R11, desc[UR6][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R13, desc[UR6][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R15, desc[UR6][R4.64+0x14] &wr=0x5 ?trans4;
LDG.E R19, desc[UR6][R4.64+0x18] &wr=0x5 ?trans4;
LDG.E R21, desc[UR6][R4.64+0x1c] &wr=0x5 ?trans1;
IADD.64 R2, R2, 0x8 ?WAIT2_END_GROUP;
FADD R7, R12, R7 &req={2} ?WAIT4_END_GROUP;
FADD R6, R7, R6 &req={3} ?WAIT4_END_GROUP;
FADD R6, R6, R9 &req={4} ?WAIT4_END_GROUP;
FADD R6, R6, R11 &req={5} ?WAIT4_END_GROUP;
FADD R6, R6, R13 ?WAIT4_END_GROUP;
FADD R6, R6, R15 ?WAIT4_END_GROUP;
FADD R6, R6, R19 ?WAIT4_END_GROUP;
FADD R12, R6, R21 ?WAIT7_END_GROUP;
@!P0 BRA 0x760 ?trans5;
ISETP.GE.U64.AND P0, PT, R16, 0x4, PT ?WAIT14_END_GROUP;
@P0 LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
@P0 LEA R6, P1, R2, R6, 0x2 &req={0} ?WAIT4_END_GROUP;
@P0 LEA.HI.X R7, R2, R7, R3, 0x2, P1 ?WAIT5_END_GROUP;
@P0 LDG.E R5, desc[UR6][R6.64] &wr=0x2 ?trans4;
@P0 LDG.E R8, desc[UR6][R6.64+0x4] &wr=0x3 ?trans4;
@P0 LDG.E R9, desc[UR6][R6.64+0x8] &wr=0x4 ?trans4;
@P0 LDG.E R11, desc[UR6][R6.64+0xc] &wr=0x5 ?trans1;
LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ?trans1;
@P0 IADD.64 R2, R2, 0x4 ?WAIT2_END_GROUP;
@P0 FADD R5, R12, R5 &req={2} ?WAIT4_END_GROUP;
@P0 FADD R8, R5, R8 &req={3} ?trans1;
MOV R5, RZ ?WAIT3_END_GROUP;
@P0 FADD R8, R8, R9 &req={4} ?trans2;
ISETP.NE.S64.AND P1, PT, R4, RZ, PT ?trans2;
@P0 FADD R12, R8, R11 &req={5} ?WAIT12_END_GROUP;
@!P1 BRA 0x760 ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans2;
LEA R6, P0, R2, R6, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R7, R2, R7, R3, 0x2, P0 ?WAIT9_END_GROUP;
LDG.E R3, desc[UR6][R6.64] &rd=0x0 &wr=0x2 ?trans1;
IADD.64 R4, R4, -0x1 ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P0, PT, R4, RZ, PT ?trans2;
IADD.64 R6, R6, 0x4 &req={0} ?trans2;
FADD R12, R3, R12 &req={2} ?WAIT10_END_GROUP;
@P0 BRA 0x700 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans2;
STG.E desc[UR6][R2.64], R12 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x790;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: redukcja(int, float*)
_Z8redukcjaiPf:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_sub_i32 s2, 0, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_mov_b64 s[4:5], s[0:1]
.LBB0_3:
s_load_b32 s6, s[4:5], 0x0
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u64 s[2:3], 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, s6, v0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| redukcja | 3,089 | 515 | stackv2-00000-of-00015 |
// Demangled: hello(char*, int*)
Function : _Z5helloPcPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R3, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R2, R2, UR6, R3 &req={0} ?WAIT5_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
IMAD.WIDE R4, R2, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E.U8 R4, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans1;
IADD.64 R2, R2, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E.U8 R7, desc[UR4][R2.64] &wr=0x2 ?trans2;
IADD3 R7, PT, PT, R4, R7, RZ &req={2} ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: hello(char*, int*)
_Z5helloPcPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[3:4], off
global_load_u8 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v3, v2
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| hello | 473 | 421 | stackv2-00000-of-00015 |
// Demangled: add_val(float*, float*)
Function : _Z7add_valPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
LDG.E R2, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans2;
FADD R7, R2, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_val(float*, float*)
_Z7add_valPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s2, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_val | 292 | 161 | stackv2-00000-of-00015 |
// Demangled: iterate_grid(float, float, float, float, bool, bool*, float*, float*, int)
Function : _Z12iterate_gridffffbPbPfS0_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x3b0] &wr=0x1 ?trans6;
LDC.U8 R2, c[0x0][0x390] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, -178.125, -3742 ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x3 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x4 ?trans5;
LDC.64 R4, c[0x0][0x3a0] &wr=0x5 ?trans1;
LDCU UR10, c[0x0][0x380] &wr=0x0 ?trans7;
LDC.64 R6, c[0x0][0x3a8] &wr=0x0 ?trans1;
UFADD UR4, UR4, UR4 &req={3} ?trans1;
UFADD UR5, UR5, UR5 ?WAIT6_END_GROUP;
LDC R13, c[0x0][0x384] &wr=0x3 ?trans1;
PRMT R12, R2, 0x8880, RZ &req={2} ?trans2;
IADD3 R0, PT, PT, R9.reuse, UR8, RZ &req={1} ?trans2;
IADD3 R12, PT, PT, R12, R9, R9 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={5} ?trans1;
LDCU.64 UR8, c[0x0][0x398] &wr=0x1 ?trans1;
ISETP.GT.AND P0, PT, R0.reuse, -0x1, PT ?trans1;
LOP3.LUT R0, R0, 0xaad26b49, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
SEL R3, R3, 0x8bf16996, P0 ?trans1;
IMAD R0, R0, 0x4182bed5, RZ ?trans2;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={0} ?trans2;
LOP3.LUT R14, R3.reuse, 0x5491333, RZ, 0x3c, !PT ?trans2;
IADD3 R15, PT, PT, R3.reuse, 0x1f123bb5, RZ ?trans2;
IADD3 R16, PT, PT, R3, 0x6a788e, R0 ?trans2;
IADD3 R21, PT, PT, R0, 0x583f19, RZ ?WAIT2_END_GROUP;
LOP3.LUT R17, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ?trans2;
IADD3 R18, PT, PT, R0, 0x75bcd15, RZ &req={4,3,1} ?WAIT7_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R12 ?trans1;
BSSY.RECONVERGENT B0, 0x3d0 ?trans1;
MOV R19, R17 ?trans1;
MOV R17, R15 ?trans1;
LEA.HI R9, R11, R12, RZ, 0xe ?trans1;
MOV R15, R14 ?trans1;
MOV R14, R21 ?trans2;
SHF.R.S32.HI R3, RZ, 0xe, R9 ?WAIT4_END_GROUP;
LOP3.LUT R2, R3, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x310 ?trans5;
LOP3.LUT R9, R9, 0xc000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, -R9, R12, RZ ?WAIT4_END_GROUP;
PRMT R0, R9, 0x9910, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R0, RZ, 0xf, R0 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LEA.HI R9, R0, R9, RZ, 0x17 ?WAIT4_END_GROUP;
PRMT R0, R9, 0x9910, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R0, RZ, 0x7, R0 ?trans1;
BRA 0x3c0 ?trans6;
LOP3.LUT R9, R9, 0xc000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, -R9, R12, RZ ?WAIT4_END_GROUP;
PRMT R0, R9, 0x9910, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R0, RZ, 0xf, R0 ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LEA.HI R0, R0, R9, RZ, 0x17 ?WAIT4_END_GROUP;
PRMT R0, R0, 0x9910, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R0, RZ, 0x7, R0 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, RZ, -R0, RZ ?WAIT4_END_GROUP;
PRMT R0, R0, 0x7710, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, 0x7f, RZ ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
IADD3 R23, PT, PT, R3.reuse, 0x7f, RZ ?trans2;
PRMT R8, R0, 0x9910, RZ ?trans1;
IMAD.SHL.U32 R9, R3.reuse, 0x4000, RZ ?trans1;
ISETP.NE.AND P0, PT, R2.reuse, RZ, PT ?trans1;
IADD3 R25, PT, PT, R3, 0x1, RZ ?trans2;
LOP3.LUT R10, R23, 0x1, RZ, 0xc0, !PT ?trans2;
IADD3 R0, PT, PT, R3, R8, RZ ?trans1;
ISETP.NE.AND P4, PT, R2, RZ, PT ?trans1;
LOP3.LUT R9, R9, 0x1fc000, RZ, 0xc0, !PT ?trans1;
IMAD.SHL.U32 R2, R25, 0x4000, RZ ?trans1;
ISETP.NE.U32.AND P3, PT, R10, 0x1, PT ?trans1;
LOP3.LUT R24, R8, 0x7f, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
LOP3.LUT R10, R0, 0x1, RZ, 0xc0, !PT ?trans1;
IMAD.SHL.U32 R0, R23, 0x4000, RZ ?trans1;
LOP3.LUT R27, R2, 0x1fc000, RZ, 0xc0, !PT ?trans1;
@P0 IMAD R20, R24, -0x80, R9.reuse ?trans1;
IADD3 R26, PT, PT, R8, 0x7f, RZ ?trans1;
@!P0 IMAD R22, R24, 0x80, R9 ?trans1;
LOP3.LUT R21, R0, 0x1fc000, RZ, 0xc0, !PT ?trans1;
@P4 IMAD R0, R24, 0x80, R27.reuse ?trans1;
ISETP.NE.U32.AND P2, PT, R10, 0x1, PT ?trans1;
@P0 IADD3 R22, PT, PT, R20, 0x3f80, RZ ?trans2;
LEA.HI R20, R11, R12, RZ, 0x7 ?trans1;
@!P4 IMAD R11, R24, -0x80, R27 ?trans1;
ISETP.NE.AND P1, PT, R10, RZ, PT ?trans1;
@P3 IMAD R2, R24, 0x80, R21 ?trans1;
IADD3 R28, PT, PT, R8, 0x1, RZ ?trans1;
@P0 IMAD R27, R24.reuse, -0x80, R9 ?trans1;
@!P4 IADD3 R0, PT, PT, R11, 0x3f80, RZ ?trans1;
@!P3 IMAD R21, R24, -0x80, R21 ?WAIT2_END_GROUP;
@!P0 IMAD R10, R24, 0x80, R9 ?trans1;
IADD3 R24, PT, PT, R8.reuse, R23, RZ ?trans2;
IADD3 R23, PT, PT, R8, R25, RZ ?trans2;
LOP3.LUT R25, R20, 0xffffff80, RZ, 0xc0, !PT ?trans2;
@P0 IADD3 R10, PT, PT, R27, 0x3f80, RZ ?trans2;
IADD3 R27, PT, PT, R3, R26, RZ ?trans2;
LOP3.LUT R8, R26, 0x7f, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
IADD3 R3, PT, PT, R3, R28, RZ ?trans2;
LOP3.LUT R28, R28, 0x7f, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R29, R24, 0x1, RZ, 0xc0, !PT ?trans1;
@!P0 IMAD R20, R8.reuse, 0x80, R9.reuse ?trans1;
@P2 IADD3 R24, PT, PT, -R25.reuse, R12, RZ ?trans2;
@!P2 IADD3 R24, PT, PT, R25, 0x7f, -R12 ?trans1;
@P0 IMAD R26, R8, -0x80, R9.reuse ?trans1;
LOP3.LUT R27, R27, 0x1, RZ, 0xc0, !PT ?trans1;
@!P0 IMAD R8, R28.reuse, 0x80, R9.reuse ?trans1;
@!P3 IADD3 R2, PT, PT, R21, 0x3f80, RZ ?trans1;
@P0 IMAD R28, R28, -0x80, R9 ?trans1;
IADD3 R9, PT, PT, R24, -0x1, RZ ?WAIT2_END_GROUP;
IADD3 R11, PT, PT, R24.reuse, 0x1, RZ ?trans2;
LOP3.LUT R24, R24, 0x7f, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R3, R3, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R9, R9, 0x7f, RZ, 0xc0, !PT ?trans1;
ISETP.NE.U32.AND P3, PT, R27, 0x1, PT ?trans1;
LOP3.LUT R25, R24, 0x7f, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R23, R23, 0x1, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
@P1 LOP3.LUT R9, R9, 0x7f, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R11, R11, 0x7f, RZ, 0xc0, !PT ?trans1;
ISETP.NE.U32.AND P4, PT, R3, 0x1, PT ?trans1;
@P0 IADD3 R20, PT, PT, R26, 0x3f80, RZ ?trans1;
SEL R21, R25, R24, !P3 ?trans1;
ISETP.NE.U32.AND P5, PT, R23, 0x1, PT ?trans1;
@P1 LOP3.LUT R11, R11, 0x7f, RZ, 0x3c, !PT ?trans2;
IADD3 R22, PT, PT, R9, R22, RZ ?trans1;
MOV R23, RZ ?trans1;
@P0 IADD3 R8, PT, PT, R28, 0x3f80, RZ ?trans1;
SEL R9, R25, R24, !P4 ?trans1;
IADD3 R20, PT, PT, R21, R20, RZ ?WAIT2_END_GROUP;
IADD3 R10, PT, PT, R11, R10, RZ ?trans1;
HFMA2 R21, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.U32.AND P2, PT, R29, 0x1, PT ?trans1;
IADD.64 R22, R22, UR8 ?trans2;
MOV R11, RZ ?trans1;
IADD3 R8, PT, PT, R9, R8, RZ ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
IADD.64 R20, R20, UR8 ?trans2;
SEL R3, R25, R24, !P2 ?trans1;
IADD.64 R10, R10, UR8 ?WAIT2_END_GROUP;
LDG.E.U8 R22, desc[UR6][R22.64] &wr=0x2 ?trans1;
IADD.64 R26, R8, UR8 ?trans2;
SEL R25, R25, R24, !P5 ?trans1;
IADD3 R2, PT, PT, R3, R2, RZ ?trans1;
LDG.E.S8 R20, desc[UR6][R20.64] &wr=0x3 ?trans1;
MOV R3, RZ ?WAIT3_END_GROUP;
LDG.E.S8 R10, desc[UR6][R10.64] &wr=0x4 ?trans1;
IADD3 R24, PT, PT, R25, R0, RZ ?trans1;
HFMA2 R25, -RZ, RZ, 0, 0 ?trans1;
IADD.64 R28, R2, UR8 ?trans2;
LDG.E.S8 R26, desc[UR6][R26.64] &wr=0x5 ?trans2;
IADD.64 R24, R24, UR8 ?trans2;
MOV R2, R12 ?trans1;
LDG.E.S8 R28, desc[UR6][R28.64] &wr=0x5 ?trans1;
SHF.R.S32.HI R3, RZ, 0x1f, R12 ?WAIT3_END_GROUP;
LDG.E.S8 R24, desc[UR6][R24.64] &wr=0x5 ?trans2;
IADD.64 R8, R2, UR8 ?WAIT6_END_GROUP;
LDG.E.S8 R0, desc[UR6][R8.64] &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0xce0 ?trans1;
PRMT R3, R22, 0x8880, RZ &req={2} ?trans1;
I2F.S16 R20, R20 &req={3} &wr=0x0 ?trans3;
IADD3 R3, PT, PT, R10, R3, RZ &req={4} ?trans1;
I2F.S16 R26, R26 &req={5} &wr=0x1 ?trans3;
IADD3 R3, PT, PT, R3, -0x2, R3 ?WAIT4_END_GROUP;
I2FP.F32.S32 R3, R3 ?trans1;
I2F.S16 R28, R28 &wr=0x2 ?trans4;
FFMA R3, R20, UR4, R3 &req={0} ?trans1;
I2F.S16 R24, R24 &wr=0x0 ?trans3;
FFMA R3, R26, UR4, R3 &req={1} ?trans1;
IMAD.SHL.U32 R0, R0, 0x2, RZ ?WAIT3_END_GROUP;
FADD R3, R3, -UR4 ?trans2;
IADD3 R10, PT, PT, R0, R0, RZ ?trans2;
FFMA R3, R28, UR5, R3 &req={2} ?trans2;
IADD3 R2, PT, PT, R10, -0x2, RZ ?trans2;
FFMA R0, R24, UR5, R3 &req={0} ?WAIT4_END_GROUP;
FADD R0, R0, -UR5 ?trans1;
I2FP.F32.S32 R2, R2 ?WAIT3_END_GROUP;
FADD R3, R0, UR10 ?WAIT4_END_GROUP;
FMUL R0, R2, R3 ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R0, RZ, PT ?trans1;
HFMA2 R2, -RZ, RZ, 1.875, 0 ?trans1;
IADD3 R10, PT, PT, -R10, 0x2, RZ ?WAIT11_END_GROUP;
@!P0 BRA 0xcd0 ?trans5;
MUFU.RCP R2, R13 &wr=0x0 ?trans1;
BSSY.RECONVERGENT B1, 0xc30 ?trans1;
FCHK P0, -R0, R13 &wr=0x1 ?trans1;
FFMA R3, R2, -R13, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R3, R2, R3, R2 ?WAIT4_END_GROUP;
FFMA R2, -R0, R3, RZ ?WAIT4_END_GROUP;
FFMA R11, R2, -R13, -R0 ?WAIT4_END_GROUP;
FFMA R2, R3, R11, R2 ?trans1;
@!P0 BRA 0xc20 &req={1} ?trans6;
FADD R2, -R0, -RZ ?trans1;
MOV R20, 0xc20 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xeb0 ?trans5;
BSYNC.RECONVERGENT B1 ?trans5;
MOV R3, 0x3bbb989d ?trans1;
HFMA2 R20, -RZ, RZ, 3.7421875, 0 ?WAIT4_END_GROUP;
FFMA.SAT R3, R2, R3, 0.5 ?WAIT4_END_GROUP;
FFMA.RM R3, R3, R20, 12582913 ?WAIT4_END_GROUP;
FADD R11, R3, -12583039 ?WAIT4_END_GROUP;
FFMA R11, R2, 1.4426950216293334961, -R11 ?WAIT4_END_GROUP;
FFMA R11, R2, 1.925963033500011079e-08, R11 ?trans1;
IMAD.SHL.U32 R2, R3, 0x800000, RZ ?WAIT5_END_GROUP;
MUFU.EX2 R11, R11 &wr=0x0 ?trans2;
FMUL R2, R2, R11 &req={0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R3, RZ, 0x2, R18 ?trans1;
IMAD.SHL.U32 R11, R14, 0x10, RZ ?WAIT3_END_GROUP;
LOP3.LUT R3, R3, R18, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
IADD3 R18, PT, PT, R3, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R18, R14, R11, R18, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R21, R18, R3, RZ, 0x3c, !PT ?trans1;
MOV R18, 0x2f800000 ?WAIT3_END_GROUP;
IADD3 R3, PT, PT, R21, R16, RZ ?WAIT4_END_GROUP;
I2FP.F32.U32 R3, R3 ?WAIT5_END_GROUP;
FFMA R3, R3, R18, 1.1641532182693481445e-10 ?WAIT5_END_GROUP;
FSETP.GEU.AND P0, PT, R3, R2, PT ?WAIT13_END_GROUP;
@!P0 LDG.E R3, desc[UR6][R4.64] &wr=0x2 ?trans2;
@!P0 FADD R3, R0, R3 &req={2} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR6][R4.64], R3 &rd=0x0 ?trans4;
@!P0 LDG.E R0, desc[UR6][R6.64] &wr=0x2 ?trans1;
@!P0 I2FP.F32.S32 R11, R10 ?WAIT5_END_GROUP;
@!P0 FADD R11, R0, R11 &req={2} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR6][R6.64], R11 &rd=0x0 ?trans4;
@!P0 LDG.E.U8 R0, desc[UR6][R8.64] &wr=0x2 ?trans1;
MOV R18, R19 ?trans1;
IADD3 R16, PT, PT, R16, 0x587c5, RZ ?trans1;
@!P0 ISETP.NE.AND P1, PT, R0, RZ, PT &req={2} ?trans1;
IADD3 R0, PT, PT, R12, 0x400, RZ ?WAIT4_END_GROUP;
@!P0 SEL R23, RZ, 0x1, P1 ?WAIT5_END_GROUP;
@!P0 STG.E.U8 desc[UR6][R8.64], R23 &rd=0x0 ?trans1;
ISETP.GE.AND P0, PT, R12, 0x1ffc00, PT ?trans1;
MOV R12, R0 ?WAIT12_END_GROUP;
@!P0 BRA 0x1d0 &req={0} ?trans5;
EXIT ?trans5;
LDC R3, c[0x0][0x384] &wr=0x0 ?trans1;
SHF.R.U32.HI R11, RZ, 0x17, R2 ?trans1;
LDCU UR11, c[0x0][0x384] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B2, 0x1520 ?trans2;
LOP3.LUT R24, R11, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R25, PT, PT, R24, -0x1, RZ ?trans1;
MOV R23, UR11 &req={1} ?trans1;
SHF.R.U32.HI R21, RZ, 0x17, R3 &req={0} ?WAIT4_END_GROUP;
LOP3.LUT R21, R21, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R22, PT, PT, R21, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R22, 0xfd, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R25, 0xfd, P0 ?WAIT13_END_GROUP;
@!P0 MOV R11, RZ ?trans1;
@!P0 BRA 0x1100 ?trans6;
FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ?trans1;
FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ?WAIT5_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?WAIT13_END_GROUP;
@P0 BRA 0x1500 ?trans5;
LOP3.LUT P0, RZ, R23, 0x7fffffff, R2, 0xc8, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x14e0 ?trans5;
FSETP.NEU.FTZ.AND P1, PT, |R2|.reuse, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ?trans1;
FSETP.NEU.FTZ.AND P2, PT, |R2|, +INF , PT ?WAIT12_END_GROUP;
@!P0 BRA !P1, 0x14e0 ?trans5;
LOP3.LUT P1, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P0, P1, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x14c0 ?trans5;
LOP3.LUT P0, RZ, R23, 0x7fffffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P0, PT, P2, P0, PT, 0x2f, 0xf2 ?WAIT13_END_GROUP;
@P0 BRA 0x1490 ?trans5;
ISETP.GE.AND P0, PT, R25, RZ, PT ?trans1;
ISETP.GE.AND P1, PT, R22, RZ, PT ?WAIT12_END_GROUP;
@P0 MOV R11, RZ ?trans1;
@!P0 MOV R11, 0xffffffc0 ?trans1;
@!P0 FFMA R2, R2, 1.84467440737095516160e+19, RZ ?trans1;
@!P1 FFMA R23, R3, 1.84467440737095516160e+19, RZ ?WAIT3_END_GROUP;
@!P1 IADD3 R11, PT, PT, R11, 0x40, RZ ?WAIT7_END_GROUP;
LEA R22, R21, 0xc0800000, 0x17 ?trans1;
BSSY.RECONVERGENT B3, 0x1480 ?trans3;
IADD3 R23, PT, PT, -R22, R23, RZ ?trans2;
IADD3 R22, PT, PT, R24, -0x7f, RZ ?trans2;
MUFU.RCP R3, R23 &wr=0x0 ?trans1;
FADD.FTZ R25, -R23, -RZ ?trans2;
IMAD R2, R22.reuse, -0x800000, R2 ?trans1;
IADD3 R22, PT, PT, R22, 0x7f, -R21 ?WAIT4_END_GROUP;
IADD3 R22, PT, PT, R22, R11, RZ ?trans1;
FFMA R24, R3, R25, 1 &req={0} ?WAIT4_END_GROUP;
FFMA R3, R3, R24, R3 ?WAIT4_END_GROUP;
FFMA R24, R2, R3, RZ ?WAIT4_END_GROUP;
FFMA R26, R25, R24, R2 ?WAIT4_END_GROUP;
FFMA R26, R3, R26, R24 ?WAIT4_END_GROUP;
FFMA R25, R25, R26, R2 ?WAIT4_END_GROUP;
FFMA R2, R3, R25, R26 ?WAIT5_END_GROUP;
SHF.R.U32.HI R21, RZ, 0x17, R2 ?WAIT4_END_GROUP;
LOP3.LUT R21, R21, 0xff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R23, PT, PT, R21, R22, RZ ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, R23, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1460 ?trans5;
ISETP.GT.AND P0, PT, R23, 0xfe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1430 ?trans5;
ISETP.GE.AND P0, PT, R23, 0x1, PT ?WAIT13_END_GROUP;
@P0 BRA 0x1470 ?trans5;
ISETP.GE.AND P0, PT, R23, -0x18, PT ?trans1;
LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P0 BRA 0x1470 ?trans5;
FFMA.RZ R11, R3, R25.reuse, R26.reuse ?trans1;
IADD3 R24, PT, PT, R23, 0x20, RZ ?trans1;
FFMA.RM R22, R3, R25, R26 ?trans1;
ISETP.NE.AND P1, PT, R23.reuse, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R23, RZ, PT ?trans1;
LOP3.LUT R11, R11, 0x7fffff, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R21, R11, 0x800000, RZ, 0xfc, !PT ?trans1;
FFMA.RP R11, R3, R25, R26 ?trans1;
IADD3 R3, PT, PT, -R23, RZ, RZ ?trans2;
SHF.L.U32 R24, R21, R24, RZ ?trans2;
FSETP.NEU.FTZ.AND P0, PT, R11, R22, PT ?trans1;
SEL R22, R3, RZ, P2 ?trans2;
ISETP.NE.AND P1, PT, R24, RZ, P1 ?WAIT3_END_GROUP;
SHF.R.U32.HI R22, RZ, R22, R21 ?trans2;
PLOP3.LUT P0, PT, P0, P1, PT, 0xf8, 0x8f ?trans2;
SHF.R.U32.HI R24, RZ, 0x1, R22 ?WAIT3_END_GROUP;
SEL R3, RZ, 0x1, !P0 ?WAIT5_END_GROUP;
LOP3.LUT R3, R3, 0x1, R24, 0xf8, !PT ?WAIT4_END_GROUP;
LOP3.LUT R3, R3, R22, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R24, R3, RZ ?WAIT4_END_GROUP;
LOP3.LUT R2, R3, R2, RZ, 0xfc, !PT ?trans1;
BRA 0x1470 ?trans6;
LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1470 ?trans6;
IMAD R2, R22, 0x800000, R2 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B3 ?trans5;
BRA 0x1510 ?trans5;
LOP3.LUT R2, R23, 0x80000000, R2, 0x48, !PT ?WAIT4_END_GROUP;
LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ?trans1;
BRA 0x1510 ?trans6;
LOP3.LUT R2, R23, 0x80000000, R2, 0x48, !PT ?trans1;
BRA 0x1510 ?trans6;
MUFU.RSQ R2, -QNAN &wr=0x0 ?trans1;
BRA 0x1510 ?trans5;
FADD.FTZ R2, R2, R3 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
HFMA2 R21, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R20 0x0 &req={0} ?trans5;
BRA 0x1540;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: iterate_grid(float, float, float, float, bool, bool*, float*, float*, int)
_Z12iterate_gridffffbPbPfS0_i:
s_clause 0x4
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s3, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
v_dual_mov_b32 v2, 0x8a5d614f :: v_dual_lshlrev_b32 v1, 1, v0
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_bfe_u32 v7, v0, 6, 25
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s2, v0
v_and_or_b32 v8, s3, 1, v1
v_add_f32_e64 v9, s6, s6
v_add_co_u32 v0, s2, s10, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_xor_b32_e32 v5, 0x2c7f967f, v4
v_cmp_lt_i32_e32 vcc_lo, -1, v4
v_add_f32_e64 v10, s7, s7
v_add_co_ci_u32_e64 v1, null, s11, 0, s2
v_mul_lo_u32 v5, 0x493c4aa1, v5
v_cndmask_b32_e32 v4, 0xfa091aa4, v2, vcc_lo
v_add_co_u32 v2, s0, s0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, null, s1, 0, s0
v_xor_b32_e32 v11, 0x5491333, v4
v_add_nc_u32_e32 v12, 0x1f123bb5, v4
v_add_nc_u32_e32 v15, 0x583f19, v5
v_xor_b32_e32 v13, 0x159a55e5, v5
v_add_nc_u32_e32 v16, 0x75bcd15, v5
v_add3_u32 v14, v4, v5, 0x6a788e
s_mov_b32 s1, 0
.LBB1_1:
v_and_b32_e32 v5, 0x4000, v8
v_lshrrev_b32_e32 v18, 14, v8
v_and_b32_e32 v19, 0x7f, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_and_b32_e32 v4, 0x7f, v7
v_add_nc_u32_e32 v21, 1, v18
v_add_nc_u32_e32 v5, -1, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v17, 0x7f, v4
v_lshlrev_b32_e32 v26, 14, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v24, 14, v5
v_dual_cndmask_b32 v4, v17, v4 :: v_dual_and_b32 v25, 1, v5
v_xor_b32_e32 v17, 0x7f, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v24, 0x1fc000, v24
v_add_nc_u32_e32 v23, v4, v18
v_lshlrev_b32_e32 v27, 7, v4
v_add_nc_u32_e32 v28, -1, v4
v_add_nc_u32_e32 v29, 1, v4
v_add_nc_u32_e32 v5, v4, v5
v_and_b32_e32 v23, 1, v23
v_add_nc_u32_e32 v4, v4, v21
v_lshlrev_b32_e32 v31, 7, v28
v_add_nc_u32_e32 v28, v28, v18
v_lshlrev_b32_e32 v32, 7, v29
v_cmp_eq_u32_e64 s0, 0, v23
v_add_nc_u32_e32 v18, v29, v18
v_or_b32_e32 v29, v27, v24
v_and_b32_e32 v28, 1, v28
v_or_b32_e32 v24, 0x3f80, v24
v_cndmask_b32_e64 v17, v17, v19, s0
v_and_b32_e32 v19, 0x1fc000, v26
v_and_b32_e32 v18, 1, v18
v_and_b32_e32 v5, 1, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v26, -1, v17
v_or_b32_e32 v35, v27, v19
v_or_b32_e32 v19, 0x3f80, v19
v_add_nc_u32_e32 v30, 1, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v26, 0x7f, v26
v_sub_nc_u32_e32 v19, v19, v27
v_and_b32_e32 v20, 0x1fc000, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v30, 0x7f, v30
v_xor_b32_e32 v33, 0x7f, v26
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v19, v35, v19, vcc_lo
v_or_b32_e32 v22, 0x3f80, v20
v_or_b32_e32 v21, v27, v20
v_xor_b32_e32 v34, 0x7f, v30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v23, v22, v27
v_cndmask_b32_e32 v21, v23, v21, vcc_lo
v_cndmask_b32_e64 v23, v33, v26, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v26, v34, v30, s0
v_and_b32_e32 v30, 0x3f80, v31
v_cmp_eq_u32_e64 s0, 0, v28
v_or_b32_e32 v23, v23, v21
s_delay_alu instid0(VALU_DEP_4)
v_or_b32_e32 v21, v26, v21
v_and_b32_e32 v26, 0x3f80, v32
v_xor_b32_e32 v32, 0x7f, v17
s_clause 0x1
global_load_u8 v23, v23, s[8:9]
global_load_u8 v21, v21, s[8:9]
v_or_b32_e32 v31, v30, v20
v_sub_nc_u32_e32 v30, v22, v30
v_or_b32_e32 v20, v26, v20
v_sub_nc_u32_e32 v22, v22, v26
v_cndmask_b32_e64 v28, v32, v17, s0
v_cmp_eq_u32_e64 s0, 0, v18
v_cndmask_b32_e32 v26, v30, v31, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v20, v22, v20, vcc_lo
v_and_b32_e32 v22, 1, v4
v_cndmask_b32_e64 v18, v32, v17, s0
v_sub_nc_u32_e32 v4, v24, v27
v_cmp_eq_u32_e64 s0, 0, v25
v_or_b32_e32 v24, v28, v26
v_cmp_eq_u32_e32 vcc_lo, 0, v22
v_or_b32_e32 v18, v18, v20
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v20, v4, v29, s0
v_cmp_eq_u32_e64 s0, 0, v5
global_load_u8 v24, v24, s[8:9]
v_cndmask_b32_e32 v22, v32, v17, vcc_lo
v_cndmask_b32_e64 v25, v32, v17, s0
v_add_co_u32 v4, s0, s8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, s9, v6, s0
v_or_b32_e32 v20, v25, v20
v_or_b32_e32 v19, v22, v19
s_mov_b32 s0, exec_lo
s_clause 0x3
global_load_u8 v17, v[4:5], off
global_load_u8 v18, v18, s[8:9]
global_load_u8 v20, v20, s[8:9]
global_load_u8 v19, v19, s[8:9]
s_waitcnt vmcnt(5)
v_add_nc_u16 v21, v21, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b16 v21, 1, v21
v_and_b32_e32 v21, 0xfe, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v21, -2, v21
s_waitcnt vmcnt(4)
v_cvt_f32_ubyte0_e32 v22, v24
v_cvt_f32_i32_e32 v21, v21
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v21, v9, v22
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v18, v18
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v20, v20
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v22, v19
v_fmac_f32_e32 v21, v9, v18
v_lshlrev_b16 v18, 1, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v21, v21, v9 :: v_dual_and_b32 v18, 0xfe, v18
v_fmac_f32_e32 v21, v10, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v19, -1, v18
v_dual_fmac_f32 v21, v10, v22 :: v_dual_lshlrev_b32 v18, 1, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v20, v21, v10
v_cvt_f32_i32_e32 v18, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v21, 1.0 :: v_dual_add_f32 v20, s4, v20
v_mul_f32_e32 v20, v20, v18
v_mov_b32_e32 v18, v12
v_mov_b32_e32 v12, v11
v_mov_b32_e32 v11, v15
s_delay_alu instid0(VALU_DEP_4)
v_cmpx_ngt_f32_e32 0, v20
s_cbranch_execz .LBB1_3
v_div_scale_f32 v15, null, s5, s5, -v20
v_div_scale_f32 v23, vcc_lo, -v20, s5, -v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v21, v15
s_waitcnt_depctr 0xfff
v_fma_f32 v22, -v15, v21, 1.0
v_fmac_f32_e32 v21, v22, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v22, v23, v21
v_fma_f32 v24, -v15, v22, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v22, v24, v21
v_fma_f32 v15, -v15, v22, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v15, v15, v21, v22
v_div_fixup_f32 v15, v15, s5, -v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v21, 0x3fb8aa3b, v15
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
v_fma_f32 v22, 0x3fb8aa3b, v15, -v21
v_rndne_f32_e32 v23, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v22, 0x32a5705f, v15
v_sub_f32_e32 v21, v21, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v21, v21, v22
v_cvt_i32_f32_e32 v22, v23
v_exp_f32_e32 v21, v21
s_waitcnt_depctr 0xfff
v_ldexp_f32 v21, v21, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v21, 0, v21, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
v_cndmask_b32_e32 v21, 0x7f800000, v21, vcc_lo
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
v_lshrrev_b32_e32 v15, 2, v16
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v15, v15, v16
v_lshlrev_b32_e32 v16, 4, v11
v_lshlrev_b32_e32 v22, 1, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v16, v22, v16
v_xor3_b32 v15, v16, v15, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v16, v14, v15
v_cvt_f32_u32_e32 v16, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v16, 0x2f800000, v16, 0x2f800000
v_cmpx_lt_f32_e32 v16, v21
s_cbranch_execz .LBB1_5
global_load_b32 v16, v[0:1], off
v_mul_i32_i24_e32 v19, -2, v19
v_xor_b32_e32 v17, 1, v17
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v19, v19
s_waitcnt vmcnt(0)
v_add_f32_e32 v16, v20, v16
global_store_b32 v[0:1], v16, off
global_load_b32 v16, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v16, v16, v19
global_store_b32 v[2:3], v16, off
global_store_b8 v[4:5], v17, off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v8, vcc_lo, 0x400, v8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_dual_mov_b32 v16, v13 :: v_dual_add_nc_u32 v7, 8, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v13, v18 :: v_dual_add_nc_u32 v4, 0xfffffc00, v8
v_add_nc_u32_e32 v14, 0x587c5, v14
v_cmp_lt_u32_e32 vcc_lo, 0x1ffbff, v4
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| iterate_grid | 8,833 | 5,553 | stackv2-00000-of-00015 |
// Demangled: reset_vec(float*)
Function : _Z9reset_vecPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], RZ &req={1} ?trans1;
EXIT ?trans5;
BRA 0x70;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: reset_vec(float*)
_Z9reset_vecPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| reset_vec | 220 | 110 | stackv2-00000-of-00015 |
// Demangled: set_lattice(bool*)
Function : _Z11set_latticePb
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x240 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
SHF.R.U32.HI R0, RZ, 0x9, R7 &req={1} ?WAIT4_END_GROUP;
IADD3 R11, PT, PT, -R0, 0x1000, RZ ?WAIT4_END_GROUP;
LOP3.LUT R12, R11.reuse, 0xf, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R6, R11, 0x1ff0, RZ, 0xc0, !PT &req={3} ?WAIT7_END_GROUP;
MOV R2, R7.reuse &req={1} ?trans1;
MOV R3, RZ ?trans1;
MOV R8, 0x1 ?trans1;
IADD3 R9, PT, PT, R9, 0x10, RZ ?trans1;
MOV R10, R7 ?trans1;
IADD3 R7, PT, PT, R7, 0x2000, RZ ?trans1;
IADD.64 R2, R2, R4 &req={2} ?trans2;
ISETP.NE.AND P0, PT, R9, R6, PT ?WAIT4_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x200], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x400], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x600], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x800], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0xa00], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0xc00], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0xe00], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1000], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1200], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1400], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1600], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1800], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1a00], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1c00], R8 &rd=0x1 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1e00], R8 &rd=0x1 ?trans1;
@P0 BRA 0xa0 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
ISETP.NE.AND P0, PT, R12, RZ, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R12, 0x8, PT ?trans1;
LOP3.LUT R6, R11, 0x7, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B0, 0x350 ?trans4;
ISETP.NE.AND P1, PT, R6, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x340 ?trans6;
STG.E.U8 desc[UR4][R2.64+0x2000], R8 &rd=0x2 ?trans1;
IADD3 R7, PT, PT, R10, 0x3000, RZ ?WAIT3_END_GROUP;
STG.E.U8 desc[UR4][R2.64+0x2200], R8 &rd=0x2 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2400], R8 &rd=0x2 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2600], R8 &rd=0x2 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2800], R8 &rd=0x2 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2a00], R8 &rd=0x2 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2c00], R8 &rd=0x2 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2e00], R8 &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R6, 0x4, PT ?trans1;
LOP3.LUT P1, RZ, R11, 0x3, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@P0 MOV R2, R7 &req={2,1} ?trans1;
@P0 MOV R3, RZ ?trans1;
@P0 IADD3 R7, PT, PT, R7, 0x800, RZ ?WAIT4_END_GROUP;
@P0 IADD.64 R2, R2, R4 ?WAIT6_END_GROUP;
@P0 STG.E.U8 desc[UR4][R2.64], R8 &rd=0x1 ?trans4;
@P0 STG.E.U8 desc[UR4][R2.64+0x200], R8 &rd=0x1 ?trans4;
@P0 STG.E.U8 desc[UR4][R2.64+0x400], R8 &rd=0x1 ?trans4;
@P0 STG.E.U8 desc[UR4][R2.64+0x600], R8 &rd=0x1 ?trans1;
@!P1 EXIT ?trans5;
MOV R2, R7 &req={1} ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans2;
IMAD R0, R0, -0x3, RZ ?WAIT3_END_GROUP;
IADD.64 R2, R2, R4 ?WAIT8_END_GROUP;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
STG.E.U8 desc[UR4][R2.64], R8 &rd=0x1 ?trans4;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD.64 R2, R2, 0x200 &req={1} ?WAIT12_END_GROUP;
@P0 BRA 0x450 ?trans5;
EXIT ?trans5;
BRA 0x4b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: set_lattice(bool*)
_Z11set_latticePb:
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1
s_mov_b32 s1, 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v0
v_add_co_u32 v0, s0, 0x200, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
v_add_co_ci_u32_e64 v1, vcc_lo, 0, v1, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, 0xfffffe00, v0
global_store_b8 v[3:4], v2, off
v_cmp_lt_u32_e32 vcc_lo, 0x1ffdff, v5
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| set_lattice | 2,057 | 338 | stackv2-00000-of-00015 |
// Demangled: set_val(float*, float)
Function : _Z7set_valPff
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans8;
LDC R5, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
STG.E desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x60;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: set_val(float*, float)
_Z7set_valPff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| set_val | 198 | 130 | stackv2-00000-of-00015 |
// Demangled: vec_sum(float*, float*)
Function : _Z7vec_sumPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
BSSY.RECONVERGENT B0, 0x150 ?trans1;
ISETP.GT.U32.AND P6, PT, R7.reuse, 0xff, PT &req={1} ?trans1;
ISETP.GT.U32.AND P0, PT, R7.reuse, 0x3f, PT ?trans1;
ISETP.GT.U32.AND P5, PT, R7.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P4, PT, R7.reuse, 0x1f, PT ?trans1;
ISETP.GT.U32.AND P3, PT, R7.reuse, 0xf, PT ?trans1;
ISETP.GT.U32.AND P2, PT, R7.reuse, 0x7, PT ?trans1;
P2R R0, PR, RZ, 0x1 ?trans1;
IMAD.WIDE.U32 R2, R7.reuse, 0x4, R2 &req={2} ?trans1;
ISETP.GT.U32.AND P1, PT, R7.reuse, 0x3, PT ?trans1;
ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ?WAIT4_END_GROUP;
@P6 BRA 0x140 &req={3,0} ?trans9;
LDG.E R0, desc[UR4][R2.64+0x400] &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R2.64] &wr=0x2 ?trans2;
FADD R5, R0, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P6, PT, R7, RZ, PT ?WAIT5_END_GROUP;
BSSY.RECONVERGENT B0, 0x1e0 ?trans4;
@P5 BRA 0x1d0 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x200] &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans2;
FADD R5, R0, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P5, PT, R7, 0x3f, PT ?WAIT5_END_GROUP;
BSSY.RECONVERGENT B0, 0x270 ?trans8;
@P5 BRA 0x260 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x100] &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={1,0} &wr=0x2 ?trans2;
FADD R5, R0, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x2 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x2f0 ?trans4;
@P4 BRA 0x2e0 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x80] &wr=0x3 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={2,1,0} &wr=0x3 ?trans2;
FADD R5, R0, R5 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x3 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x370 ?trans4;
@P3 BRA 0x360 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x40] &wr=0x4 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={3,2,1,0} &wr=0x4 ?trans2;
FADD R5, R0, R5 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x4 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x3f0 ?trans4;
@P2 BRA 0x3e0 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x20] &wr=0x5 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={4,3,2,1,0} &wr=0x5 ?trans2;
FADD R5, R0, R5 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x470 ?trans4;
@P1 BRA 0x460 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={4,3,2,1,0} &wr=0x5 ?trans2;
FADD R5, R0, R5 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x4f0 ?trans4;
@P0 BRA 0x4e0 ?trans5;
LDG.E R0, desc[UR4][R2.64+0x8] &wr=0x5 ?trans4;
LDG.E R5, desc[UR4][R2.64] &req={4,3,2,1,0} &wr=0x5 ?trans2;
FADD R5, R0, R5 &req={5} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
BSSY.RECONVERGENT B0, 0x580 ?trans4;
@P6 BRA 0x570 ?trans5;
LDC.64 R4, c[0x0][0x380] &req={4,3,2,1,0} &wr=0x0 ?trans1;
LDG.E R7, desc[UR4][R2.64] &wr=0x2 ?trans4;
LDG.E R4, desc[UR4][R4.64+0x4] &req={0} &wr=0x2 ?trans2;
FADD R7, R4, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P6 EXIT ?trans5;
LDC.64 R4, c[0x0][0x380] &req={4,3,2,1,0} &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDG.E R4, desc[UR4][R4.64] &req={0} &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
FADD R7, R4, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x610;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vec_sum(float*, float*)
_Z7vec_sumPfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s4, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s4
s_movk_i32 s4, 0x100
.LBB3_1:
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB3_3
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[4:5], 2
v_add_co_u32 v3, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s5, s4, 1
s_cmp_gt_u32 s4, 1
s_mov_b32 s4, s5
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_1
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_6
v_mov_b32_e32 v0, 0
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
.LBB3_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vec_sum | 2,360 | 653 | stackv2-00000-of-00015 |
// Demangled: dot_product(int*, int*, int*)
Function : _Z11dot_productPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
LDC R0, c[0x3][RZ] &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x2 ?trans1;
BSSY.RECONVERGENT B0, 0x150 ?trans1;
ISETP.GE.U32.AND P0, PT, R7.reuse, R0, PT &req={1} ?trans1;
ISETP.NE.AND P1, PT, R7, RZ, PT ?WAIT12_END_GROUP;
@P0 BRA 0x140 &req={2,0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR8][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR8][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R7, R7, UR4, 0x2 ?trans1;
IMAD R6, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STS [R7], R6 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 EXIT ?trans5;
ISETP.GE.AND P0, PT, R0, 0x1, PT ?trans1;
HFMA2 R2, -RZ, RZ, 0, 0 ?WAIT12_END_GROUP;
@!P0 BRA 0x610 ?trans5;
ISETP.GE.U32.AND P1, PT, R0.reuse, 0x10, PT ?trans1;
LOP3.LUT R20, R0, 0xf, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R2, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R20, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x380 ?trans6;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
LOP3.LUT R3, R0, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
UMOV UR4, 0x400 ?WAIT3_END_GROUP;
IADD3 R3, PT, PT, -R3, RZ, RZ ?trans1;
ULEA UR5, UR5, UR4, 0x18 &req={1} ?WAIT3_END_GROUP;
UMOV UR4, URZ ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x20, URZ ?WAIT12_END_GROUP;
LDS.128 R16, [UR5+-0x20] &wr=0x1 ?trans1;
IADD3 R3, PT, PT, R3, 0x10, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans2;
LDS.128 R12, [UR5+-0x10] &wr=0x2 ?trans2;
ISETP.NE.AND P1, PT, R3, RZ, PT ?trans2;
LDS.128 R8, [UR5] &wr=0x3 ?trans4;
LDS.128 R4, [UR5+0x10] &req={0} &wr=0x0 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x40, URZ ?trans1;
IADD3 R16, PT, PT, R17, R16, R2 &req={1} ?WAIT4_END_GROUP;
IADD3 R16, PT, PT, R19, R18, R16 ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R13, R12, R16 &req={2} ?WAIT4_END_GROUP;
IADD3 R12, PT, PT, R15, R14, R12 ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R9, R8, R12 &req={3} ?WAIT4_END_GROUP;
IADD3 R8, PT, PT, R11, R10, R8 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R5, R4, R8 &req={0} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R7, R6, R4 ?trans1;
@P1 BRA 0x270 ?trans6;
@!P0 BRA 0x610 ?trans5;
ISETP.GE.U32.AND P0, PT, R20, 0x8, PT ?trans1;
LOP3.LUT R3, R0, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R3, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x480 ?trans6;
S2UR UR6, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR5, 0x400 ?trans2;
ULEA UR5, UR6, UR5, 0x18 &req={1} ?WAIT4_END_GROUP;
ULEA UR5, UR4, UR5, 0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?WAIT8_END_GROUP;
LDS.128 R4, [UR5] &req={0} &wr=0x0 ?trans4;
LDS.128 R8, [UR5+0x10] &wr=0x1 ?trans1;
IADD3 R4, PT, PT, R5, R4, R2 &req={0} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R7, R6, R4 ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R9, R8, R4 &req={1} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R11, R10, R4 ?WAIT7_END_GROUP;
@!P1 BRA 0x610 ?trans5;
ISETP.GE.U32.AND P0, PT, R3, 0x4, PT ?trans1;
LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0x550 ?trans6;
S2UR UR6, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR5, 0x400 ?trans2;
ULEA UR5, UR6, UR5, 0x18 &req={1} ?WAIT4_END_GROUP;
ULEA UR5, UR4, UR5, 0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT8_END_GROUP;
LDS.128 R4, [UR5] &req={0} &wr=0x0 ?trans2;
IADD3 R2, PT, PT, R5, R4, R2 &req={0} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R7, R6, R2 ?WAIT7_END_GROUP;
@!P1 BRA 0x610 ?trans5;
S2UR UR6, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR5, 0x400 ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
ULEA UR5, UR6, UR5, 0x18 &req={1} ?WAIT4_END_GROUP;
ULEA UR4, UR4, UR5, 0x2 ?WAIT12_END_GROUP;
LDS R3, [UR4] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R0, RZ, PT ?trans1;
IADD3 R2, PT, PT, R3, R2, RZ &req={1} ?WAIT12_END_GROUP;
@P0 BRA 0x5b0 ?trans5;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDC.64 R4, c[0x4][RZ] &wr=0x1 ?trans2;
IMAD.WIDE.U32 R4, R3.reuse, 0x4, R4 &req={1} ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT4_END_GROUP;
STG.E desc[UR8][R4.64], R2 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans8;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x4][RZ] &req={1} &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans1;
LDG.E R2, desc[UR8][R2.64] &req={1} &wr=0x3 ?trans4;
LDG.E R7, desc[UR8][R4.64] &req={2,0} &wr=0x3 ?trans2;
IADD3 R7, PT, PT, R2, R7, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR8][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x6f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: dot_product(int*, int*, int*)
_Z11dot_productPiS_S_:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, VECTOR_SIZE@rel32@lo+4
s_addc_u32 s5, s5, VECTOR_SIZE@rel32@hi+12
s_mov_b32 s2, s15
s_load_b32 s3, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5]
global_load_b32 v3, v1, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_6
s_mov_b32 s4, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s4
s_add_i32 s3, s3, -1
s_add_i32 s4, s4, 4
s_cmp_eq_u32 s3, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_5
.LBB0_6:
s_mov_b32 s3, 0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, blockSums@rel32@lo+4
s_addc_u32 s5, s5, blockSums@rel32@hi+12
s_lshl_b64 s[6:7], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s6, s6, s4
s_addc_u32 s7, s7, s5
s_cmp_eq_u32 s2, 0
global_store_b32 v1, v0, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_7:
s_endpgm
.LBB0_8:
s_clause 0x1
global_load_b32 v0, v1, s[4:5]
global_load_b32 v2, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| dot_product | 2,692 | 881 | stackv2-00000-of-00015 |
// Demangled: VecAdd(float*, float*, float*)
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans1;
IMAD R9, R0, UR6, R9 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: VecAdd(float*, float*, float*)
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| VecAdd | 495 | 496 | stackv2-00000-of-00015 |
// Demangled: SumArrays(float*, float*, float*, int)
Function : _Z9SumArraysPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: SumArrays(float*, float*, float*, int)
_Z9SumArraysPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| SumArrays | 567 | 576 | stackv2-00000-of-00015 |
// Demangled: conv(float*, float*, float*, int*, int*, int*)
Function : _Z4convPfS_S_PiS0_S0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x3a8] &wr=0x1 ?trans8;
LDC.64 R12, c[0x0][0x398] &wr=0x2 ?trans1;
LDG.E R3, desc[UR6][R2.64] &req={1} &wr=0x3 ?trans4;
LDG.E R0, desc[UR6][R12.64+0x4] &req={2} &wr=0x2 ?trans4;
LDG.E R7, desc[UR6][R12.64+0x8] &wr=0x4 ?trans1;
LDC.64 R14, c[0x0][0x3a0] &wr=0x1 ?trans3;
LDG.E R6, desc[UR6][R14.64+0xc] &req={1} &rd=0x1 &wr=0x5 ?trans4;
LDG.E R5, desc[UR6][R14.64+0x8] &rd=0x1 &wr=0x5 ?trans4;
LDG.E R10, desc[UR6][R14.64+0x4] &rd=0x1 &wr=0x5 ?trans1;
S2UR UR8, SR_CTAID.X &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x340 ?trans1;
S2R R4, SR_CTAID.Y &wr=0x3 ?trans1;
S2R R19, SR_TID.Y &wr=0x3 ?trans1;
S2R R17, SR_TID.X &wr=0x0 ?trans1;
S2R R8, SR_CTAID.Z &wr=0x0 ?trans1;
IADD3 R11, PT, PT, R19, R4, -R3 &req={3} ?WAIT2_END_GROUP;
IADD3 R16, PT, PT, R17, UR8, -R3 &req={0} ?trans2;
IADD3 R9, PT, PT, R3, R3, RZ ?trans1;
ISETP.GT.AND P0, PT, R0, R11, PT &req={2} ?WAIT5_END_GROUP;
ISETP.LE.OR P0, PT, R7, R16, !P0 &req={4} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R16, RZ, P0 ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R11, RZ, P0 ?WAIT13_END_GROUP;
@P0 BRA 0x300 &req={1} ?trans5;
S2R R20, SR_TID.Z &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R13, R5, R8, RZ &req={5} ?trans1;
LDCU.64 UR4, c[0x0][0x388] &wr=0x2 ?trans3;
IMAD R13, R6, R13, RZ ?WAIT4_END_GROUP;
IMAD R12, R10, R13, RZ ?trans2;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans2;
IMAD R15, R5, R20.reuse, RZ &req={0} ?trans2;
IMAD R18, R0, R20, RZ ?trans2;
IMAD R15, R6, R15, R17 ?trans2;
IMAD R18, R7, R18, R11 ?WAIT2_END_GROUP;
IMAD R14, R6, R19, R15 ?trans1;
MOV R15, RZ ?trans1;
IMAD R11, R7, R16, R18 ?WAIT4_END_GROUP;
IADD.64 R12, R12, R14 ?trans2;
IMAD.WIDE.U32 R2, R11, 0x4, R2 &req={1} ?WAIT3_END_GROUP;
LEA R14, P0, R12, UR4, 0x2 &req={2} ?WAIT3_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans1;
LEA.HI.X R15, R12, UR5, R13, 0x2, P0 ?WAIT6_END_GROUP;
LDG.E R15, desc[UR6][R14.64] &wr=0x2 ?trans1;
MOV R11, R20 ?trans1;
FMUL R12, R2, R15 &req={2} ?trans1;
BRA 0x330 ?trans6;
S2R R20, SR_TID.Z &wr=0x0 ?trans1;
HFMA2 R12, -RZ, RZ, 0, 0 ?trans1;
MOV R11, R20 &req={0} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
IMAD R3, R6.reuse, R19, R17 &req={5} ?trans1;
UMOV UR4, 0x400 ?trans1;
IADD3 R7, PT, PT, -R6, R7, R9 ?trans2;
IMAD R2, R10.reuse, R3.reuse, R11 ?trans2;
IMAD R3, R10, R3, R20 ?trans1;
LDC.64 R14, c[0x0][0x390] &wr=0x1 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R11, R2, UR4, 0x2 ?trans1;
IMAD R2, R7, R8, R8 ?trans1;
LEA R10, R3, UR4, 0x2 ?trans2;
IADD3 R3, PT, PT, -R5, R0, R9 ?trans1;
STS [R11], R12 ?trans1;
IADD3 R5, PT, PT, R7, 0x1, RZ ?WAIT3_END_GROUP;
LDS R13, [R10] &wr=0x0 ?trans1;
IMAD R2, R2, R3, R2 ?trans2;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans2;
IMAD R4, R5, UR8, R4 ?trans1;
MOV R5, RZ ?WAIT5_END_GROUP;
IADD.64 R2, R2, R4 ?WAIT5_END_GROUP;
LEA R4, P0, R2, R14, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R5, R2, R15, R3, 0x2, P0 ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R4.64], R13 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x4c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: conv(float*, float*, float*, int*, int*, int*)
_Z4convPfS_S_PiS0_S0_:
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_load_b32 s12, s[18:19], 0x0
s_load_b64 s[2:3], s[10:11], 0x4
s_load_b64 s[10:11], s[16:17], 0x4
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s0, s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s0, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v3
v_cmp_lt_i32_e64 s0, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_xor_b32 s1, s0, -1
s_and_saveexec_b32 s19, s0
s_sub_i32 s0, s14, s12
s_and_not1_b32 s1, s1, exec_lo
v_add_nc_u32_e32 v2, s0, v6
s_mov_b32 s18, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s0, 0, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s1, s1, s0
s_or_b32 exec_lo, exec_lo, s19
s_load_b32 s0, s[16:17], 0xc
v_bfe_u32 v0, v0, 20, 10
s_and_saveexec_b32 s17, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s1, exec_lo, s17
s_cbranch_execz .LBB0_4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[7:8], null, s0, v6, v[1:2]
s_mov_b32 s16, 0
s_and_not1_b32 s18, s18, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s10, v7, v[0:1]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, s16
s_and_saveexec_b32 s1, s18
s_cbranch_execz .LBB0_6
s_delay_alu instid0(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s2, v0, v[3:4]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[7:8], null, s0, v6, v[1:2]
s_mul_i32 s18, s11, s0
s_mov_b32 s17, 0
s_mul_i32 s16, s18, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_i32 s16, s16, s10
v_mad_u64_u32 v[5:6], null, v4, s3, v[2:3]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s18, v0, v[7:8]
s_lshl_b64 s[16:17], s[16:17], 2
v_mov_b32_e32 v2, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[5:6]
s_add_u32 s6, s6, s16
s_addc_u32 s7, s7, s17
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, s10, v7, v[0:1]
v_mul_f32_e32 v5, v3, v1
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v0, v4, 2, 0
v_bfrev_b32_e32 v2, 1
s_mov_b32 s1, exec_lo
ds_store_b32 v0, v5
.LBB0_7:
s_ctz_i32_b32 s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v5, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s1, s1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s1, 0
v_add_f32_e32 v2, s5, v2
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s1, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_11
s_lshl_b32 s4, s12, 1
v_mov_b32_e32 v3, 0
s_add_i32 s3, s3, s4
s_add_i32 s2, s2, s4
s_waitcnt lgkmcnt(0)
s_sub_i32 s0, s3, s0
s_sub_i32 s2, s2, s11
s_add_i32 s4, s0, 1
s_add_i32 s2, s2, 1
s_mul_i32 s0, s4, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s2
s_lshl_b64 s[2:3], s[0:1], 2
s_mul_i32 s0, s4, s13
s_add_u32 s4, s8, s2
s_addc_u32 s5, s9, s3
s_add_i32 s0, s0, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[0:1], 2
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s0, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s0
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_endpgm
| conv | 1,901 | 2,512 | stackv2-00000-of-00015 |
// Demangled: transposeCoalesced_RECTTILES(float*, float*, int)
Function : _Z28transposeCoalesced_RECTTILESPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
LDCU UR10, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R8, SR_TID.Y &wr=0x3 ?trans1;
LDCU UR11, c[0x0][0x364] &wr=0x4 ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x4 ?trans1;
LDCU UR12, c[0x0][0x390] &wr=0x5 ?trans1;
UIMAD UR4, UR10, UR4, URZ &req={2} ?WAIT6_END_GROUP;
IADD3 R0, PT, PT, R7, UR4, RZ &req={1} ?trans1;
UIMAD UR5, UR11, UR5, URZ &req={4} ?WAIT6_END_GROUP;
IADD3 R5, PT, PT, R8, UR5, RZ &req={3} ?WAIT5_END_GROUP;
VIMNMX.S32 R2, R0, R5, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR12, PT &req={5} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R5, R5, UR12, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R6, desc[UR8][R2.64] &req={1} &rd=0x0 &wr=0x2 ?trans1;
UI2F.U32.RP UR6, UR11 ?trans1;
S2UR UR7, SR_CgaCtaId &wr=0x1 ?trans1;
ISETP.NE.U32.AND P2, PT, RZ, UR11, PT ?WAIT7_END_GROUP;
MUFU.RCP R0, UR6 &wr=0x3 ?trans1;
UMOV UR6, 0x400 ?trans2;
ULEA UR6, UR7, UR6, 0x18 &req={1} ?trans1;
IADD3 R4, PT, PT, R0, 0xffffffe, RZ &req={3} ?trans1;
IMAD R0, R8, UR10, R7 ?WAIT3_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x1 &wr=0x3 ?trans2;
HFMA2 R4, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R9, PT, PT, RZ, -R5, RZ &req={3} ?WAIT5_END_GROUP;
IMAD R9, R9, UR11, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R9, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R5, R0, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R5, RZ, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R2, R3, UR11, R0 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, UR11, PT ?WAIT13_END_GROUP;
@P0 IADD3 R2, PT, PT, R2, -UR11, RZ ?trans2;
@P0 IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R2, UR11, PT ?trans1;
LEA R2, R8, UR6, 0x7 ?WAIT5_END_GROUP;
IMAD R7, R7, 0x4, R2 ?WAIT7_END_GROUP;
@P1 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R5, RZ, UR11, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R3, UR11, R0 ?trans2;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans3;
LEA R4, R0.reuse, UR6, 0x7 ?trans2;
IADD3 R0, PT, PT, R0, UR5, RZ ?WAIT3_END_GROUP;
IMAD R4, R5.reuse, 0x4, R4 ?trans1;
IADD3 R5, PT, PT, R5, UR4, RZ ?WAIT5_END_GROUP;
IMAD R5, R5, UR12, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?trans1;
STS [R7], R6 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R9, [R4] &wr=0x0 ?trans4;
STG.E desc[UR8][R2.64], R9 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x3a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transposeCoalesced_RECTTILES(float*, float*, int)
_Z28transposeCoalesced_RECTTILESPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s5, s2, 16
s_mul_i32 s14, s14, s6
s_mul_i32 s15, s15, s5
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v3, s15, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, v0, v3
v_cmpx_gt_i32_e64 s4, v4
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s4, v[0:1]
v_cvt_f32_u32_e32 v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v0, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_mad_u32_u24 v5, v1, s6, v2
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_sub_i32 s0, 0, s5
v_lshl_add_u32 v1, v1, 7, v2
global_load_b32 v3, v[3:4], off
v_mul_lo_u32 v4, s0, v0
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v4
v_mul_hi_u32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s5
v_add_nc_u32_e32 v6, 1, v0
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v7, s5, v4
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s5
v_add_nc_u32_e32 v6, s14, v0
v_lshlrev_b32_e32 v0, 2, v0
v_mul_lo_u32 v6, v6, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v5, v4
v_lshl_add_u32 v2, v4, 7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v0, v4, s15, v6
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transposeCoalesced_RECTTILES | 1,485 | 1,591 | stackv2-00000-of-00015 |
// Demangled: A_star_expand(int*, int*, float*, int*, float volatile*, int*, int*, int*, int*, int, int, int, int*, int*, float*, int*, int*)
Function : _Z13A_star_expandPiS_PfS_PVfS_S_S_S_iiiS_S_S0_S_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x3b0] &wr=0x1 ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, R2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x3a8] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x3c8] &wr=0x1 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDG.E R0, desc[UR6][R4.64] &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x3cc] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, -0x1, URZ &req={1} ?trans1;
MOV R2, UR5 &req={3} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0.reuse, UR4, PT &req={2} ?trans1;
IMAD.WIDE R6, R0, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R6.64] &wr=0x2 ?trans7;
@P0 LDG.E R2, desc[UR6][R6.64+0x4] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R3, R2, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR4, c[0x0][0x3a0] &wr=0x0 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R0 ?trans2;
LEA R4, P0, R0, UR4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R5, R0, UR5, R5, 0x2, P0 ?WAIT9_END_GROUP;
LDC.64 R6, c[0x0][0x388] &req={2,0} &wr=0x0 ?trans2;
IMAD.WIDE R6, R3, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E R17, desc[UR6][R6.64] &wr=0x2 ?trans1;
IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R3, R2, PT ?trans1;
ISETP.GE.AND P1, PT, R17, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P1 BRA 0x570 &req={5,4,3,1} ?trans5;
LDC.64 R12, c[0x0][0x3b8] &wr=0x0 ?trans8;
LDC.64 R14, c[0x0][0x3a0] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R12, R17, 0x4, R12 &req={0} ?WAIT7_END_GROUP;
LDC.64 R10, c[0x0][0x3c0] &wr=0x0 ?trans1;
IMAD.WIDE.U32 R14, R17, 0x4, R14 &req={1} ?WAIT7_END_GROUP;
HFMA2 R19, -RZ, RZ, 0, 5.9604644775390625e-08 &req={4} ?trans1;
MOV R18, RZ ?trans1;
YIELD ?trans5;
ATOMG.E.CAS.STRONG.GPU PT, R16, [R12], R18, R19 &wr=0x4 ?trans2;
ISETP.NE.AND P2, PT, R16.reuse, RZ, PT &req={4} ?trans1;
ISETP.NE.AND P1, PT, R16, RZ, PT ?WAIT12_END_GROUP;
@P2 BRA 0x530 &req={5,1} ?trans5;
IMAD.WIDE R20, R0, 0x4, R6.reuse &req={2} ?trans1;
LDG.E.STRONG.SYS R16, desc[UR6][R14.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R18, desc[UR6][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R22, R17, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E R21, desc[UR6][R20.64] &wr=0x4 ?trans4;
LDG.E R23, desc[UR6][R22.64] &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0x520 ?trans1;
FADD R18, R18, -R21 &req={4} ?WAIT4_END_GROUP;
FADD R18, R18, 1 ?WAIT4_END_GROUP;
FADD R19, R18, R23 &req={5} ?WAIT5_END_GROUP;
FSETP.GT.AND P2, PT, R16, R19, PT &req={2} ?trans1;
MOV R18, 0x1 ?trans1;
MOV R19, RZ ?WAIT11_END_GROUP;
@!P2 BRA 0x510 ?trans5;
LDG.E.STRONG.SYS R16, desc[UR6][R4.64] &wr=0x2 ?trans2;
FADD R16, -R21, R16 &req={2} ?WAIT4_END_GROUP;
FADD R16, R16, 1 ?WAIT4_END_GROUP;
FADD R21, R23, R16 ?WAIT5_END_GROUP;
STG.E.STRONG.SYS desc[UR6][R14.64], R21 &rd=0x1 ?trans1;
MEMBAR.SC.GPU ?trans6;
ERRBAR;
CGAERRBAR ?trans6;
CCTL.IVALL ?trans1;
IMAD.WIDE.U32 R20, R17, 0x4, R8 &req={3,1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R17, 0x4, R10 &req={0} ?trans1;
STG.E desc[UR6][R20.64], R0 &rd=0x1 ?trans5;
LDG.E R22, desc[UR6][R22.64] &wr=0x2 ?trans2;
ISETP.NE.AND P2, PT, R22, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P2 LDC.64 R24, c[0x0][0x3d8] &wr=0x0 ?trans1;
@!P2 MOV R27, 0x1 ?trans1;
@!P2 IMAD.WIDE.U32 R24, R17, 0x4, R24 &req={0} ?WAIT5_END_GROUP;
@!P2 STG.E desc[UR6][R24.64], R27 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
ATOMG.E.CAS.STRONG.GPU PT, RZ, [R12], R18, R19 &rd=0x4 &wr=0x5 ?trans2;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 BRA 0x2a0 ?trans5;
@P0 BRA 0x1c0 ?trans5;
EXIT ?trans5;
BRA 0x590;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: A_star_expand(int*, int*, float*, int*, float volatile*, int*, int*, int*, int*, int, int, int, int*, int*, float*, int*, int*)
_Z13A_star_expandPiS_PfS_PVfS_S_S_S_iiiS_S_S0_S_S_:
s_clause 0x1
s_load_b512 s[16:31], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x8c
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[28:29], 0x0
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_14
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[2:3], s[0:1], 0x48
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s26, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s27, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
v_mov_b32_e32 v21, s3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s16, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, s2, v0
global_load_b32 v1, v[2:3], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_3
global_load_b32 v21, v[2:3], off offset:4
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v21
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_14
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x40
s_load_b64 s[4:5], s[0:1], 0x58
v_add_co_u32 v3, vcc_lo, s24, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s25, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s20, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s21, v6, vcc_lo
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v7, 1
s_mov_b32 s1, 0
.LBB1_5:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_add_co_u32 v9, vcc_lo, s18, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 -1, v9
s_cbranch_execz .LBB1_13
v_mov_b32_e32 v10, v8
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[19:20], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s30, v19
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s31, v20, vcc_lo
v_add_co_u32 v11, vcc_lo, s24, v19
v_add_co_ci_u32_e32 v12, vcc_lo, s25, v20, vcc_lo
v_add_co_u32 v13, vcc_lo, s20, v19
v_add_co_ci_u32_e32 v14, vcc_lo, s21, v20, vcc_lo
v_add_co_u32 v15, vcc_lo, s22, v19
v_add_co_ci_u32_e32 v16, vcc_lo, s23, v20, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v17, vcc_lo, s2, v19
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v20, vcc_lo
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
.LBB1_7:
global_atomic_cmpswap_b32 v2, v[9:10], v[7:8], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB1_12
flat_load_b32 v23, v[11:12] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v24, v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v22, v[13:14], off
s_mov_b32 s9, exec_lo
s_waitcnt vmcnt(1) lgkmcnt(0)
v_sub_f32_e32 v24, v24, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v24, 1.0, v24
s_waitcnt vmcnt(0)
v_add_f32_e32 v24, v22, v24
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v23, v24
s_cbranch_execz .LBB1_11
flat_load_b32 v23, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v2, v23, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, 1.0, v2
v_add_f32_e32 v2, v22, v2
flat_store_b32 v[11:12], v2 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
global_store_b32 v[15:16], v0, off
global_load_b32 v2, v[17:18], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, -1, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_11
global_store_b32 v[19:20], v7, off
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s9
v_dual_mov_b32 v22, v8 :: v_dual_mov_b32 v23, v7
global_atomic_cmpswap_b32 v[9:10], v[22:23], off
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, vcc_lo
s_waitcnt_vscnt null, 0x0
s_or_b32 s7, s0, s7
s_barrier
buffer_gl0_inv
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_7
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v21
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_5
.LBB1_14:
s_endpgm
| A_star_expand | 2,329 | 2,578 | stackv2-00000-of-00015 |
// Demangled: extractMin(int*, int*, int*, float*, int*, int, int)
Function : _Z10extractMinPiS_S_PfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R8, c[0x0][0x3ac] &wr=0x2 ?trans1;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, R8, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R0, 0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IABS R13, R8 ?trans1;
LDC R11, c[0x0][0x3a8] &wr=0x0 ?trans3;
I2F.RP R7, R13 &wr=0x1 ?trans2;
MUFU.RCP R7, R7 &req={1} &wr=0x1 ?trans1;
IADD3 R6, PT, PT, R8, -0x1, R11 &req={0} ?WAIT4_END_GROUP;
IABS R12, R6 ?trans2;
LOP3.LUT R6, R6, R8, RZ, 0x3c, !PT ?trans2;
IADD3 R4, PT, PT, R7, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R4, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R10, PT, PT, RZ, -R5, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R11, R10, R13, RZ ?trans1;
MOV R10, R12 ?WAIT3_END_GROUP;
IMAD.HI.U32 R5, R5, R11, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R5, R10, RZ ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R13, R7, R10 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R4, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R4, PT, PT, R4, -R13.reuse, RZ ?trans2;
@!P0 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R6, RZ, PT ?trans2;
LDC.64 R6, c[0x4][RZ] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P1, PT, R4, R13, PT ?WAIT13_END_GROUP;
@P1 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R8, RZ, PT ?WAIT3_END_GROUP;
@!P0 IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT10_END_GROUP;
@!P1 LOP3.LUT R5, RZ, R8, RZ, 0x33, !PT ?WAIT5_END_GROUP;
IMAD R13, R9, R5, RZ ?WAIT4_END_GROUP;
IMAD.WIDE R4, R13.reuse, 0x4, R6 &req={0} ?trans1;
IADD3 R9, PT, PT, R13, -0x1, R0 ?WAIT4_END_GROUP;
LDG.E.STRONG.SYS R0, desc[UR4][R4.64] &rd=0x0 &wr=0x5 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 ?WAIT6_END_GROUP;
LDG.E.STRONG.SYS R7, desc[UR4][R6.64] &wr=0x2 ?trans4;
STG.E.STRONG.SYS desc[UR4][R4.64], R7 &req={2} &rd=0x0 ?trans4;
LDG.E R8, desc[UR4][R2.64] &wr=0x2 ?trans1;
BSSY B0, 0x8a0 ?trans1;
IADD3 R11, PT, PT, R8, -0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x0 ?trans1;
ISETP.GE.AND P0, PT, R8, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x890 &req={0} ?trans5;
LDC.64 R6, c[0x0][0x398] &wr=0x0 ?trans1;
MOV R12, R11 ?trans1;
IADD3 R10, PT, PT, R13, 0x1, RZ ?trans1;
MOV R15, RZ ?trans1;
MOV R11, 0x1 ?trans1;
MOV R21, RZ ?WAIT3_END_GROUP;
LDC.64 R8, c[0x4][RZ] &wr=0x1 ?trans4;
IADD3 R16, PT, PT, R15, 0x2, RZ ?trans1;
YIELD ?trans5;
ISETP.GE.AND P0, PT, R16, R12, PT ?trans1;
BSSY.RELIABLE B1, 0x840 ?WAIT12_END_GROUP;
@!P0 BRA 0x540 ?trans5;
IADD3 R19, PT, PT, R10, R15, RZ ?trans1;
IMAD.WIDE R16, R21, 0x4, R4 ?WAIT4_END_GROUP;
IMAD.WIDE R18, R19, 0x4, R8 &req={1} ?trans1;
LDG.E.STRONG.SYS R13, desc[UR4][R16.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R15, desc[UR4][R18.64] &wr=0x3 ?trans1;
IMAD.WIDE R12, R13, 0x4, R6 &req={2,0} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R6 &req={3} ?trans2;
LDG.E R12, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R14.64] &wr=0x2 ?trans2;
FSETP.GT.AND P0, PT, R12, R15, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BREAK.RELIABLE B1 ?trans5;
@!P0 BRA 0x890 ?trans5;
LDG.E.STRONG.SYS R13, desc[UR4][R18.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R15, desc[UR4][R16.64] &wr=0x3 ?trans1;
MOV R21, R11 ?WAIT3_END_GROUP;
STG.E.STRONG.SYS desc[UR4][R18.64], R15 &req={3} &rd=0x4 ?trans4;
STG.E.STRONG.SYS desc[UR4][R16.64], R13 &req={2} &rd=0x4 ?trans1;
BRA 0x830 ?trans5;
IMAD.WIDE R12, R21, 0x4, R4 ?WAIT4_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R4 ?trans1;
LDG.E.STRONG.SYS R19, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R21, desc[UR4][R14.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R18, R19, 0x4, R6 &req={2,0} ?WAIT4_END_GROUP;
IMAD.WIDE R20, R21, 0x4, R6 &req={3} ?trans2;
LDG.E R18, desc[UR4][R18.64] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans2;
FSETP.GT.AND P0, PT, R18, R21, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x6c0 ?trans5;
LDG.E.STRONG.SYS R19, desc[UR4][R14.64+0x4] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R21, desc[UR4][R14.64+0x8] &wr=0x3 ?trans1;
IMAD.WIDE R18, R19, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R20, R21, 0x4, R6 &req={3} ?trans2;
LDG.E R18, desc[UR4][R18.64] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans2;
FSETP.GTU.AND P0, PT, R18, R21, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x6c0 ?trans5;
LDG.E.STRONG.SYS R17, desc[UR4][R14.64+0x4] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R19, desc[UR4][R12.64] &wr=0x3 ?trans1;
MOV R21, R11 ?WAIT3_END_GROUP;
STG.E.STRONG.SYS desc[UR4][R14.64+0x4], R19 &req={3} &rd=0x3 ?trans4;
STG.E.STRONG.SYS desc[UR4][R12.64], R17 &req={2} &rd=0x3 ?trans1;
BRA 0x830 ?trans5;
LDG.E.STRONG.SYS R19, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R21, desc[UR4][R14.64+0x8] &wr=0x3 ?trans1;
IMAD.WIDE R18, R19, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R20, R21, 0x4, R6 &req={3} ?trans2;
LDG.E R18, desc[UR4][R18.64] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans2;
FSETP.GT.AND P0, PT, R18, R21, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BREAK.RELIABLE B1 ?trans5;
@!P0 BRA 0x890 ?trans5;
LDG.E.STRONG.SYS R19, desc[UR4][R14.64+0x8] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R21, desc[UR4][R14.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R18, R19, 0x4, R6 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R20, R21, 0x4, R6 &req={3} ?trans2;
LDG.E R18, desc[UR4][R18.64] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R20.64] &wr=0x2 ?trans2;
FSETP.GTU.AND P0, PT, R18, R21, PT &req={2} ?WAIT13_END_GROUP;
@P0 BREAK.RELIABLE B1 ?trans5;
@P0 BRA 0x890 ?trans5;
LDG.E.STRONG.SYS R11, desc[UR4][R14.64+0x8] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R17, desc[UR4][R12.64] &wr=0x3 ?trans1;
MOV R21, R16 ?WAIT3_END_GROUP;
STG.E.STRONG.SYS desc[UR4][R14.64+0x8], R17 &req={3} &rd=0x0 ?trans4;
STG.E.STRONG.SYS desc[UR4][R12.64], R11 &req={2} &rd=0x0 ?trans2;
BSYNC.RELIABLE B1 ?trans5;
LDG.E R12, desc[UR4][R2.64] &req={3,0} &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R21, R21, RZ &req={4} ?WAIT4_END_GROUP;
LOP3.LUT R11, R15, 0x1, RZ, 0xfc, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R11, R12, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x3d0 ?trans5;
BSYNC B0 ?trans5;
S2R R5, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R2, c[0x0][0x3a0] &wr=0x2 ?trans1;
FLO.U32 R8, UR6 &req={1} &wr=0x0 ?trans1;
MOV R13, 0xffffffff ?trans1;
S2R R10, SR_LTMASK &wr=0x1 ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x3 ?trans1;
POPC R11, UR6 &wr=0x4 ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={5,2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 ?trans1;
ISETP.EQ.U32.AND P0, PT, R8, R5, PT &req={0} ?trans2;
LDC.64 R4, c[0x0][0x390] &wr=0x4 ?trans11;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R5, desc[UR4][R4.64], R11 &req={4} &wr=0x2 ?trans1;
LOP3.LUT R10, R10, UR6, RZ, 0xc0, !PT &req={1} ?WAIT6_END_GROUP;
POPC R10, R10 &wr=0x0 ?trans1;
SHFL.IDX PT, R9, R5, R8, 0x1f &req={2} &wr=0x0 ?trans2;
IADD3 R9, PT, PT, R9, R10, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R0 ?trans1;
EXIT ?trans5;
BRA 0x9e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: extractMin(int*, int*, int*, float*, int*, int, int)
_Z10extractMinPiS_S_PfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_22
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_22
s_ashr_i32 s4, s3, 31
s_add_i32 s2, s2, s3
s_add_i32 s5, s3, s4
s_add_i32 s2, s2, -1
s_xor_b32 s5, s5, s4
s_ashr_i32 s13, s2, 31
v_cvt_f32_u32_e32 v3, s5
s_sub_i32 s12, 0, s5
s_add_i32 s2, s2, s13
s_xor_b32 s4, s13, s4
s_xor_b32 s2, s2, s13
v_rcp_iflag_f32_e32 v3, v3
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_readfirstlane_b32 s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s12, s3
s_mul_hi_u32 s12, s3, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s12
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s3, s5
s_sub_i32 s2, s2, s12
s_add_i32 s12, s3, 1
s_sub_i32 s13, s2, s5
s_cmp_ge_u32 s2, s5
s_cselect_b32 s3, s12, s3
s_cselect_b32 s2, s13, s2
s_add_i32 s12, s3, 1
s_cmp_ge_u32 s2, s5
s_cselect_b32 s2, s12, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s4
s_sub_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, PQ@rel32@lo+4
s_addc_u32 s3, s3, PQ@rel32@hi+12
v_add3_u32 v5, v4, v3, -1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_add_co_u32 v4, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v6, vcc_lo, v9, s2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v10, vcc_lo
s_mov_b32 s2, exec_lo
flat_load_b32 v2, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[6:7] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[4:5], v6 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v6, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, -1, v6
global_store_b32 v[0:1], v11, off
v_cmpx_lt_i32_e32 2, v6
s_cbranch_execz .LBB0_19
v_dual_mov_b32 v15, 1 :: v_dual_add_nc_u32 v14, 1, v3
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v6, 0
s_mov_b32 s3, 0
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_add_nc_u32_e32 v16, 2, v10
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v5, v7, vcc_lo
flat_load_b32 v8, v[6:7] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_load_b32 v17, v[8:9], off
v_cmpx_ge_i32_e64 v16, v11
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v8, v14, v10
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, PQ@rel32@lo+4
s_addc_u32 s13, s13, PQ@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v8, s12
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
flat_load_b32 v10, v[8:9] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s10, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v17, v10
s_and_b32 s4, vcc_lo, exec_lo
.LBB0_6:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_16
v_ashrrev_i32_e32 v11, 31, v10
s_mov_b32 s14, 0
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[10:11]
v_add_co_u32 v12, vcc_lo, v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v13, vcc_lo, v5, v9, vcc_lo
flat_load_b32 v8, v[12:13] offset:4 glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_load_b32 v8, v[8:9], off
v_add_nc_u32_e32 v9, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, 2, v9
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v17, v8
s_xor_b32 s12, exec_lo, s12
s_mov_b32 s14, exec_lo
s_or_saveexec_b32 s13, s12
v_add_co_u32 v8, vcc_lo, v12, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
s_mov_b32 s12, s4
s_xor_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_11
flat_load_b32 v17, v[12:13] offset:4 glc dlc
s_waitcnt vmcnt(0)
s_and_not1_b32 s14, s14, exec_lo
s_or_b32 s12, s4, exec_lo
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v17, vcc_lo, s10, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
global_load_b32 v17, v[17:18], off
flat_load_b32 v12, v[12:13] offset:8 glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s10, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
v_cmp_nle_f32_e32 vcc_lo, v17, v12
s_and_b32 s15, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s14, s15
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_15
flat_load_b32 v12, v[6:7] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, PQ@rel32@lo+4
s_addc_u32 s15, s15, PQ@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s10, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, s14
v_add_co_ci_u32_e32 v11, vcc_lo, s15, v11, vcc_lo
s_mov_b32 s15, 0
global_load_b32 v15, v[12:13], off
flat_load_b32 v12, v[10:11] glc dlc
s_waitcnt vmcnt(0)
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s10, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 v15, v12
s_cbranch_execz .LBB0_14
flat_load_b32 v12, v[10:11] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
global_load_b32 v12, v[12:13], off
flat_load_b32 v8, v[8:9] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, v12, v8
s_and_b32 s15, vcc_lo, exec_lo
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s14
v_dual_mov_b32 v15, v16 :: v_dual_mov_b32 v8, v10
v_mov_b32_e32 v9, v11
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s14, s15, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s12, s12, exec_lo
s_or_b32 s4, s4, s12
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s5, -1
s_and_saveexec_b32 s12, s4
s_cbranch_execz .LBB0_18
flat_load_b32 v10, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[6:7] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[8:9], v11 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[6:7], v10 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v11, v[0:1], off
v_lshlrev_b32_e32 v10, 1, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v12, 1, v10
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v12, v11
s_or_not1_b32 s5, vcc_lo, exec_lo
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s12
v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v15, v12
s_and_b32 s4, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s4, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_4
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s2
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s2, exec_lo
v_mov_b32_e32 v1, -1
v_mbcnt_lo_u32_b32 v0, s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s0, exec_lo
global_store_b32 v[3:4], v1, off
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_21
s_bcnt1_i32_b32 s1, s2
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v3, s1
global_atomic_add_u32 v1, v1, v3, s[8:9] glc
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s0, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| extractMin | 4,225 | 6,354 | stackv2-00000-of-00015 |
// Demangled: insertPQ(int*, int*, int*, float*, int, int, int*)
Function : _Z8insertPQPiS_S_PfiiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R9, c[0x0][0x3a0] &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, R9, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans8;
LDC R6, c[0x0][0x3a4] &wr=0x1 ?trans1;
LDG.E R3, desc[UR4][R2.64] &req={0} &rd=0x0 &wr=0x2 ?trans1;
IABS R11, R9 ?WAIT4_END_GROUP;
I2F.RP R7, R11 &wr=0x3 ?trans1;
IADD3 R6, PT, PT, R9, -0x1, R6 &req={1} ?WAIT4_END_GROUP;
IABS R2, R6 &req={0} ?trans2;
LOP3.LUT R6, R6, R9, RZ, 0x3c, !PT ?trans1;
MUFU.RCP R7, R7 &req={3} &wr=0x0 ?trans2;
IADD3 R4, PT, PT, R7, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R4 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R4, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R8, PT, PT, RZ, -R5, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R13, R8, R11, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R13, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R5, R2, RZ ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R2, R11, R7, R2 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R11, R2, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R2, PT, PT, R2, -R11, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, R11, PT ?trans1;
ISETP.GE.AND P2, PT, R0, R3, PT &req={2} ?WAIT13_END_GROUP;
@P2 EXIT ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
@!P1 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
ISETP.GE.AND P1, PT, R6, RZ, PT ?trans1;
MOV R4, R0 ?trans2;
@P0 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT ?WAIT9_END_GROUP;
@!P1 IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT4_END_GROUP;
@!P0 LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD R5, R0, R5, RZ ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans8;
LDC.64 R8, c[0x0][0x3a8] &wr=0x1 ?trans1;
IMAD.WIDE R10, R4, 0x4, R6 &req={3,0} ?WAIT5_END_GROUP;
LDG.E R15, desc[UR4][R10.64] &wr=0x1 ?trans2;
IMAD.WIDE R6, R15, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR4][R6.64] &wr=0x2 ?trans1;
BSSY B0, 0x5b0 ?trans1;
ISETP.NE.AND P0, PT, R6, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x5a0 ?trans5;
LDG.E R12, desc[UR4][R2.64] &wr=0x2 ?trans1;
LDC.64 R6, c[0x4][RZ] &wr=0x0 ?trans1;
IADD3 R13, PT, PT, R5, R12, RZ &req={2} ?WAIT5_END_GROUP;
IMAD.WIDE R6, R13, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
STG.E.STRONG.SYS desc[UR4][R6.64], R15 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R2.64] &wr=0x2 ?trans2;
IADD3 R13, PT, PT, R12, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R13 &rd=0x0 ?trans4;
LDG.E R11, desc[UR4][R10.64] &wr=0x2 ?trans2;
IMAD.WIDE R8, R11, 0x4, R8 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R0 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R2.64] &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R12, 0x2, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x5a0 &req={0} ?trans5;
LDC.64 R6, c[0x4][RZ] &wr=0x0 ?trans1;
IADD3 R12, PT, PT, R12, -0x1, RZ ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x398] &wr=0x1 ?trans2;
IADD3 R19, PT, PT, R12, -0x1, RZ ?trans2;
IADD3 R17, PT, PT, R5, R12, RZ &req={3} ?trans2;
SHF.R.U32.HI R18, RZ, 0x1, R19 ?WAIT3_END_GROUP;
IMAD.WIDE R16, R17, 0x4, R6 &req={0} ?trans1;
IADD3 R11, PT, PT, R5, R18, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R10, R11, 0x4, R6 ?WAIT5_END_GROUP;
LDG.E.STRONG.SYS R13, desc[UR4][R10.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R15, desc[UR4][R16.64] &wr=0x3 ?trans1;
IMAD.WIDE R12, R13, 0x4, R8 &req={2,1} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R8 &req={3} ?trans2;
LDG.E R12, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R14.64] &wr=0x2 ?trans1;
YIELD ?trans5;
FSETP.GT.AND P0, PT, R12, R15, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x5a0 ?trans5;
LDG.E.STRONG.SYS R13, desc[UR4][R16.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R15, desc[UR4][R10.64] &wr=0x3 ?trans1;
ISETP.GT.U32.AND P0, PT, R19, 0x1, PT ?trans1;
MOV R12, R18 ?trans2;
STG.E.STRONG.SYS desc[UR4][R16.64], R15 &req={3} &rd=0x3 ?trans4;
STG.E.STRONG.SYS desc[UR4][R10.64], R13 &req={2} &rd=0x3 ?trans6;
@P0 BRA 0x440 ?trans5;
BSYNC B0 ?trans5;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x3a0] &wr=0x1 ?trans1;
LDG.E R7, desc[UR4][R6.64] &req={0} &wr=0x2 ?trans1;
IADD3 R4, PT, PT, R4, UR6, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, R7, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x2a0 ?trans5;
EXIT ?trans5;
BRA 0x620;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: insertPQ(int*, int*, int*, float*, int, int, int*)
_Z8insertPQPiS_S_PfiiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB4_11
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s12, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s12, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_11
s_ashr_i32 s13, s2, 31
s_add_i32 s3, s2, s3
s_add_i32 s14, s2, s13
s_add_i32 s3, s3, -1
s_xor_b32 s14, s14, s13
s_ashr_i32 s17, s3, 31
v_cvt_f32_u32_e32 v0, s14
s_sub_i32 s16, 0, s14
s_add_i32 s3, s3, s17
s_xor_b32 s13, s17, s13
s_xor_b32 s3, s3, s17
v_rcp_iflag_f32_e32 v0, v0
s_load_b64 s[0:1], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v10, s12
v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_add_co_u32 v2, vcc_lo, s4, v2
v_cvt_u32_f32_e32 v0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s15, v0
s_mul_i32 s16, s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s16, s15, s16
s_add_i32 s15, s15, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s15, s3, s15
s_mul_i32 s16, s15, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s3, s3, s16
s_add_i32 s16, s15, 1
s_sub_i32 s17, s3, s14
s_cmp_ge_u32 s3, s14
s_cselect_b32 s15, s16, s15
s_cselect_b32 s3, s17, s3
s_add_i32 s16, s15, 1
s_cmp_ge_u32 s3, s14
s_cselect_b32 s3, s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s13
s_sub_i32 s3, s3, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v1
s_mov_b32 s3, 0
.LBB4_3:
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[11:12], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
global_load_b32 v8, v[11:12], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v8
s_cbranch_execz .LBB4_10
global_load_b32 v8, v[2:3], off
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, PQ@rel32@lo+4
s_addc_u32 s13, s13, PQ@rel32@hi+12
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v10, v8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v10, s12
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
flat_store_b32 v[10:11], v7 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
global_store_b32 v[2:3], v7, off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[5:6], v1, off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 1, v5
s_cbranch_execz .LBB4_9
v_add_nc_u32_e32 v7, -1, v5
s_mov_b32 s12, 0
.LBB4_6:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v11, -1, v7
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, PQ@rel32@lo+4
s_addc_u32 s15, s15, PQ@rel32@hi+12
v_add_nc_u32_e32 v7, v7, v0
s_or_b32 s13, s13, exec_lo
v_lshrrev_b32_e32 v10, 1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v5, v10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, v5, s14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
flat_load_b32 v12, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s10, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, s14
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
s_mov_b32 s14, exec_lo
global_load_b32 v14, v[12:13], off
flat_load_b32 v12, v[7:8] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s10, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
global_load_b32 v12, v[12:13], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 v14, v12
s_cbranch_execz .LBB4_8
flat_load_b32 v12, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, 2, v11
s_and_not1_b32 s13, s13, exec_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[7:8], v13 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[5:6], v12 dlc
s_waitcnt_vscnt null, 0x0
s_and_b32 s15, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s15
.LBB4_8:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v7, v10
s_and_b32 s14, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s12, s14, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB4_6
.LBB4_9:
s_or_b32 exec_lo, exec_lo, s5
global_load_b32 v10, v9, s[8:9]
.LBB4_10:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v4, s2, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v4, v10
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB4_3
.LBB4_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| insertPQ | 2,635 | 3,717 | stackv2-00000-of-00015 |
// Demangled: keepHeapPQ(int*, float*, int, int)
Function : _Z10keepHeapPQPiPfii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R5, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R6, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD R5, R5, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, R6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
ISETP.GE.AND P0, PT, R7, 0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
IABS R11, R6 ?trans1;
LDC R9, c[0x0][0x390] &wr=0x0 ?trans3;
I2F.RP R4, R11 &wr=0x1 ?trans2;
MUFU.RCP R4, R4 &req={1} &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R6, -0x1, R9 &req={0} ?trans2;
IADD3 R2, PT, PT, R4, 0xffffffe, RZ &req={1} ?trans2;
IABS R4, R0 ?WAIT2_END_GROUP;
LOP3.LUT R0, R0, R6, RZ, 0x3c, !PT ?trans1;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x0 &wr=0x1 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R8, PT, PT, RZ, -R3, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R9, R8, R11, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R9, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R3, R4, RZ ?WAIT5_END_GROUP;
IADD3 R8, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R2, R11, R8, R4 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R11, R2, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R2, PT, PT, R2, -R11.reuse, RZ ?trans2;
@!P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R0, RZ, PT ?trans2;
ISETP.GE.U32.AND P1, PT, R2, R11, PT ?WAIT13_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R6, RZ, PT ?WAIT3_END_GROUP;
@!P0 IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT10_END_GROUP;
@!P1 LOP3.LUT R3, RZ, R6, RZ, 0x33, !PT ?WAIT5_END_GROUP;
IMAD R0, R5, R3, RZ ?WAIT5_END_GROUP;
IADD3 R2, PT, PT, R7, R0.reuse, RZ ?trans1;
MOV R3, R0 ?WAIT7_END_GROUP;
IADD3 R5, PT, PT, R3, R3, RZ ?trans1;
BSSY B0, 0x890 ?trans3;
IADD3 R17, PT, PT, R5, 0x2, RZ &req={3} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R17, R2, PT ?WAIT13_END_GROUP;
@P0 BRA 0x600 ?trans5;
LDC.64 R6, c[0x4][RZ] &wr=0x0 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R6, R3, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R10, R3, 0x4, R6 ?trans2;
LDG.E.STRONG.SYS R7, desc[UR4][R6.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R13, desc[UR4][R10.64+0x4] &wr=0x1 ?trans4;
LDG.E.STRONG.SYS R15, desc[UR4][R10.64+0x8] &wr=0x3 ?trans1;
IMAD.WIDE R12, R13, 0x4, R8 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R14, R15, 0x4, R8.reuse &req={3} ?trans2;
LDG.E R12, desc[UR4][R12.64] &wr=0x3 ?trans2;
IMAD.WIDE R8, R7, 0x4, R8 &req={2} ?trans2;
LDG.E R14, desc[UR4][R14.64] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R8.64] &wr=0x4 ?trans1;
BSSY B1, 0x5f0 ?trans1;
F2I.TRUNC.NTZ R16, R12 &req={3} ?trans1;
F2I.TRUNC.NTZ R19, R14 &req={2} &wr=0x0 ?trans1;
F2I.TRUNC.NTZ R4, R8 &req={4} &wr=0x1 ?trans1;
VIMNMX.S32 R7, R16, R19, PT &req={0} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, R4, PT &req={1} ?WAIT13_END_GROUP;
@P0 BRA 0x5e0 ?trans5;
ISETP.GT.AND P0, PT, R16, R19, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R17, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R17, R0, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x5e0 ?trans5;
LDC.64 R4, c[0x4][RZ] &wr=0x0 ?trans8;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans2;
IADD3 R8, PT, PT, R17.reuse, -0x1, RZ ?trans1;
IMAD.WIDE R14, R17, 0x4, R4 &req={3,0} ?WAIT3_END_GROUP;
LEA.HI R8, R8, R8, RZ, 0x1 ?WAIT4_END_GROUP;
SHF.R.S32.HI R19, RZ, 0x1, R8 ?WAIT5_END_GROUP;
IMAD.WIDE R12, R19, 0x4, R4 ?WAIT5_END_GROUP;
LDG.E.STRONG.SYS R9, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R11, desc[UR4][R14.64] &wr=0x3 ?trans1;
IMAD.WIDE R8, R9, 0x4, R6 &req={2,1} ?WAIT4_END_GROUP;
IMAD.WIDE R10, R11, 0x4, R6 &req={3} ?trans2;
LDG.E R8, desc[UR4][R8.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R10.64] &wr=0x2 ?trans1;
YIELD ?trans5;
FSETP.GT.AND P0, PT, R8, R11, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x5e0 ?trans5;
LDG.E.STRONG.SYS R9, desc[UR4][R14.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R11, desc[UR4][R12.64] &wr=0x3 ?trans1;
ISETP.GT.AND P0, PT, R19, R0, PT ?trans1;
MOV R17, R19 ?trans2;
STG.E.STRONG.SYS desc[UR4][R14.64], R11 &req={3} &rd=0x3 ?trans4;
STG.E.STRONG.SYS desc[UR4][R12.64], R9 &req={2} &rd=0x3 ?trans6;
@P0 BRA 0x490 ?trans5;
BSYNC B1 ?trans5;
BRA 0x880 ?trans5;
IADD3 R15, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R15, R2, PT ?WAIT13_END_GROUP;
@P0 BRA 0x880 ?trans5;
LDC.64 R6, c[0x4][RZ] &wr=0x0 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
IMAD.WIDE R10, R3, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E.STRONG.SYS R7, desc[UR4][R10.64] &wr=0x1 ?trans1;
IMAD.WIDE R12, R3, 0x4, R10 ?WAIT6_END_GROUP;
LDG.E.STRONG.SYS R13, desc[UR4][R12.64+0x4] &wr=0x2 ?trans1;
IMAD.WIDE R6, R7, 0x4, R8 &req={1} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR4][R6.64] &wr=0x3 ?trans1;
IMAD.WIDE R8, R13, 0x4, R8 &req={2} ?WAIT6_END_GROUP;
LDG.E R9, desc[UR4][R8.64] &wr=0x3 ?trans1;
ISETP.GE.AND P0, PT, R5, R0, PT ?WAIT5_END_GROUP;
FSETP.LEU.OR P0, PT, R6, R9, !P0 &req={3} ?WAIT13_END_GROUP;
@P0 BRA 0x880 ?trans5;
LDC.64 R6, c[0x4][RZ] &wr=0x0 ?trans1;
MOV R9, R15 ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans2;
IADD3 R8, PT, PT, R9.reuse, -0x1, RZ ?trans1;
IMAD.WIDE R14, R9, 0x4, R6 &req={3,0} ?WAIT3_END_GROUP;
LEA.HI R8, R8, R8, RZ, 0x1 ?WAIT4_END_GROUP;
SHF.R.S32.HI R19, RZ, 0x1, R8 ?WAIT5_END_GROUP;
IMAD.WIDE R12, R19, 0x4, R6 ?WAIT5_END_GROUP;
LDG.E.STRONG.SYS R9, desc[UR4][R12.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R11, desc[UR4][R14.64] &wr=0x3 ?trans1;
IMAD.WIDE R8, R9, 0x4, R4 &req={2,1} ?WAIT4_END_GROUP;
IMAD.WIDE R10, R11, 0x4, R4 &req={3} ?trans2;
LDG.E R8, desc[UR4][R8.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R10.64] &wr=0x2 ?trans1;
YIELD ?trans5;
FSETP.GT.AND P0, PT, R8, R11, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x880 ?trans5;
LDG.E.STRONG.SYS R11, desc[UR4][R14.64] &wr=0x2 ?trans4;
LDG.E.STRONG.SYS R17, desc[UR4][R12.64] &wr=0x3 ?trans1;
ISETP.GT.AND P0, PT, R19, R0, PT ?trans1;
MOV R9, R19 ?trans2;
STG.E.STRONG.SYS desc[UR4][R14.64], R17 &req={3} &rd=0x3 ?trans4;
STG.E.STRONG.SYS desc[UR4][R12.64], R11 &req={2} &rd=0x3 ?trans6;
@P0 BRA 0x730 ?trans5;
BSYNC B0 ?trans5;
IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, R2, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x2a0 ?trans5;
EXIT ?trans5;
BRA 0x8d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: keepHeapPQ(int*, float*, int, int)
_Z10keepHeapPQPiPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB2_20
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s1, 0
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_20
s_ashr_i32 s0, s5, 31
s_add_i32 s4, s4, s5
s_add_i32 s6, s5, s0
s_add_i32 s4, s4, -1
s_xor_b32 s6, s6, s0
s_ashr_i32 s8, s4, 31
v_cvt_f32_u32_e32 v2, s6
s_sub_i32 s7, 0, s6
s_add_i32 s4, s4, s8
s_xor_b32 s0, s8, s0
s_xor_b32 s4, s4, s8
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s5
s_mul_hi_u32 s7, s5, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s7
s_mul_hi_u32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s5, s6
s_sub_i32 s4, s4, s7
s_add_i32 s7, s5, 1
s_sub_i32 s8, s4, s6
s_cmp_ge_u32 s4, s6
s_cselect_b32 s5, s7, s5
s_cselect_b32 s4, s8, s4
s_add_i32 s7, s5, 1
s_cmp_ge_u32 s4, s6
s_cselect_b32 s4, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s0
s_sub_i32 s0, s4, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, s0, v1
v_add_nc_u32_e32 v8, v7, v0
v_mov_b32_e32 v0, v7
.LBB2_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 1, v0
s_mov_b32 s0, exec_lo
v_add_nc_u32_e32 v2, 2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 v2, v8
s_xor_b32 s4, exec_lo, s0
s_cbranch_execz .LBB2_11
v_or_b32_e32 v2, 1, v3
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v2, v8
s_cbranch_execz .LBB2_10
v_ashrrev_i32_e32 v1, 31, v0
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, PQ@rel32@lo+4
s_addc_u32 s7, s7, PQ@rel32@hi+12
v_cmp_ge_i32_e64 s0, v3, v7
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v4, s6
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v5, vcc_lo
flat_load_b32 v11, v[9:10] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v4, vcc_lo, v9, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
global_load_b32 v1, v[11:12], off
flat_load_b32 v4, v[4:5] offset:4 glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v1, v4
s_and_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB2_10
s_mov_b32 s0, 0
.LBB2_7:
v_add_nc_u32_e32 v1, -1, v2
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, PQ@rel32@lo+4
s_addc_u32 s9, s9, PQ@rel32@hi+12
s_or_b32 s6, s6, exec_lo
s_mov_b32 s7, exec_lo
v_lshrrev_b32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v1, v3
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, v5, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
flat_load_b32 v9, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v3, v[9:10], off
flat_load_b32 v9, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 v3, v9
s_cbranch_execz .LBB2_9
flat_load_b32 v3, v[1:2] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v4, v7
s_and_not1_b32 s6, s6, exec_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[1:2], v9 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[5:6], v3 dlc
s_waitcnt_vscnt null, 0x0
s_and_b32 s8, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s6, s8
.LBB2_9:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v2, v4
s_and_b32 s7, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s7, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB2_7
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s5
.LBB2_11:
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB2_19
v_ashrrev_i32_e32 v1, 31, v0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, PQ@rel32@lo+4
s_addc_u32 s5, s5, PQ@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v9, vcc_lo, v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v5, vcc_lo
s_mov_b32 s4, exec_lo
flat_load_b32 v11, v[9:10] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v4, vcc_lo, v9, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
global_load_b32 v6, v[11:12], off
flat_load_b32 v9, v[4:5] offset:4 glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v1, v[9:10], off
flat_load_b32 v4, v[4:5] offset:8 glc dlc
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_cvt_i32_f32_e32 v5, v6
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
v_min_i32_e32 v6, v1, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v6, v5
s_cbranch_execz .LBB2_18
v_or_b32_e32 v3, 1, v3
v_cmp_gt_i32_e32 vcc_lo, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v3, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, v4, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_18
s_mov_b32 s5, 0
.LBB2_15:
v_add_nc_u32_e32 v1, -1, v4
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, PQ@rel32@lo+4
s_addc_u32 s9, s9, PQ@rel32@hi+12
v_ashrrev_i32_e32 v5, 31, v4
s_or_b32 s6, s6, exec_lo
s_mov_b32 s7, exec_lo
v_lshrrev_b32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, v2, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v6, v[9:10], off
flat_load_b32 v9, v[4:5] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 v6, v9
s_cbranch_execz .LBB2_17
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, v1, v7
s_and_not1_b32 s6, s6, exec_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v9 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
s_and_b32 s8, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s6, s8
.LBB2_17:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v4, v1
s_and_b32 s7, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s7, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB2_15
.LBB2_18:
s_or_b32 exec_lo, exec_lo, s4
.LBB2_19:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_3
.LBB2_20:
s_endpgm
| keepHeapPQ | 3,660 | 5,939 | stackv2-00000-of-00015 |
// Demangled: setNV(int*, int*, int*, int)
Function : _Z5setNVPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R2, 0x1, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R3, SR_LANEID &wr=0x0 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans1;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans1;
FLO.U32 R0, UR6 &wr=0x0 ?trans1;
POPC R11, UR6 &wr=0x2 ?trans1;
ISETP.EQ.U32.AND P0, PT, R0, R3, PT &req={0} ?WAIT5_END_GROUP;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans8;
@P0 ATOMG.E.ADD.STRONG.GPU PT, R3, desc[UR4][R2.64], R11 &req={2} &wr=0x2 ?trans1;
S2R R6, SR_LTMASK &wr=0x0 ?trans2;
LOP3.LUT R6, R6, UR6, RZ, 0xc0, !PT &req={0} ?WAIT6_END_GROUP;
POPC R6, R6 &wr=0x0 ?trans1;
SHFL.IDX PT, R9, R3, R0, 0x1f &req={2} &wr=0x0 ?trans2;
IADD3 R9, PT, PT, R9, R6, RZ &req={0} ?WAIT5_END_GROUP;
IMAD.WIDE R4, R9, 0x4, R4 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x1e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: setNV(int*, int*, int*, int)
_Z5setNVPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_5
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_5
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_mov_b32 s2, exec_lo
v_mbcnt_lo_u32_b32 v0, s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_4
s_bcnt1_i32_b32 s3, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v2, v2, v3, s[0:1] glc
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0) lgkmcnt(0)
v_readfirstlane_b32 s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s0, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| setNV | 815 | 907 | stackv2-00000-of-00015 |
// Demangled: packGraph_gpu(int*, int*, int*, int*, int*, int*, int*, int)
Function : _Z13packGraph_gpuPiS_S_S_S_S_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: packGraph_gpu(int*, int*, int*, int*, int*, int*, int*, int)
_Z13packGraph_gpuPiS_S_S_S_S_S_i:
s_endpgm
| packGraph_gpu | 101 | 21 | stackv2-00000-of-00015 |
// Demangled: vecAddGPU(double*, double*, double*, double)
Function : _Z9vecAddGPUPdS_S_d
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?trans1;
LDCU.64 UR4, c[0x0][0x398] &wr=0x1 ?trans3;
I2F.F64 R2, R7 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DSETP.GEU.AND P0, PT, R2, UR4, PT &req={1} &wr=0x1 ?trans2;
@P0 EXIT &req={1,0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R7, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R7, 0x8, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E.64 R4, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R7, 0x8, R8 &req={3} ?trans1;
DADD R6, R2, R4 &req={4} &wr=0x0 ?trans4;
STG.E.64 desc[UR4][R8.64], R6 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x190;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecAddGPU(double*, double*, double*, double)
_Z9vecAddGPUPdS_S_d:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
v_cvt_f64_i32_e32 v[2:3], v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[2:3]
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecAddGPU | 652 | 588 | stackv2-00000-of-00015 |
// Demangled: void doSomething<char>(mynamespace::Bar, mynamespace::Templated<char>, char*, int*)
Function : _Z11doSomethingIcEvN11mynamespace3BarENS0_9TemplatedIT_EEPS3_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans8;
LDC R7, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x398] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x3a0] &wr=0x2 ?trans8;
LDC R9, c[0x0][0x388] &wr=0x2 ?trans1;
PRMT R7, R7, 0x7770, RZ &req={0} ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R7 &req={1} ?trans4;
STG.E desc[UR4][R4.64], R9 &req={2} ?trans1;
EXIT ?trans5;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void doSomething<char>(mynamespace::Bar, mynamespace::Templated<char>, char*, int*)
_Z11doSomethingIcEvN11mynamespace3BarENS0_9TemplatedIT_EEPS3_Pi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x8
s_load_b128 s[0:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
v_mov_b32_e32 v2, s5
s_clause 0x1
global_store_b8 v0, v1, s[0:1]
global_store_b32 v0, v2, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_doSomething_char_ | 341 | 212 | stackv2-00000-of-00015 |
// Demangled: void doSomething<float>(mynamespace::Bar, mynamespace::Templated<float>, float*, int*)
Function : _Z11doSomethingIfEvN11mynamespace3BarENS0_9TemplatedIT_EEPS3_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans8;
LDC R7, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x3a0] &wr=0x1 ?trans8;
LDC R9, c[0x0][0x388] &wr=0x1 ?trans1;
STG.E desc[UR4][R2.64], R7 &req={0} ?trans4;
STG.E desc[UR4][R4.64], R9 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void doSomething<float>(mynamespace::Bar, mynamespace::Templated<float>, float*, int*)
_Z11doSomethingIfEvN11mynamespace3BarENS0_9TemplatedIT_EEPS3_Pi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x8
s_load_b128 s[0:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
v_mov_b32_e32 v2, s5
s_clause 0x1
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v2, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_doSomething_float_ | 312 | 212 | stackv2-00000-of-00015 |
// Demangled: void doSomething<int>(mynamespace::Bar, mynamespace::Templated<int>, int*, int*)
Function : _Z11doSomethingIiEvN11mynamespace3BarENS0_9TemplatedIT_EEPS3_Pi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans8;
LDC R7, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x3a0] &wr=0x1 ?trans8;
LDC R9, c[0x0][0x388] &wr=0x1 ?trans1;
STG.E desc[UR4][R2.64], R7 &req={0} ?trans4;
STG.E desc[UR4][R4.64], R9 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x90;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void doSomething<int>(mynamespace::Bar, mynamespace::Templated<int>, int*, int*)
_Z11doSomethingIiEvN11mynamespace3BarENS0_9TemplatedIT_EEPS3_Pi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x8
s_load_b128 s[0:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
v_mov_b32_e32 v2, s5
s_clause 0x1
global_store_b32 v0, v1, s[0:1]
global_store_b32 v0, v2, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| void_doSomething_int_ | 313 | 213 | stackv2-00000-of-00015 |
// Demangled: InitRandGen(int, curandStateXORWOW*)
Function : _Z11InitRandGeniP17curandStateXORWOW
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R5, SR_TID.Y &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT2_END_GROUP;
IMAD R3, R2, UR5, R5 &req={2} ?WAIT4_END_GROUP;
IMAD R5, R0, 0x20, R3 ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R5, 0x3ff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR4, c[0x0][0x380] &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
HFMA2 R7, -RZ, RZ, -178.125, -3742 ?trans1;
IADD3 R0, PT, PT, R5.reuse, UR4, RZ &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans4;
ISETP.GT.AND P0, PT, R0.reuse, -0x1, PT ?trans1;
LOP3.LUT R0, R0, 0xaad26b49, RZ, 0x3c, !PT ?trans1;
IMAD.WIDE R2, R5, 0x30, R2 &req={1} ?WAIT3_END_GROUP;
SEL R7, R7, 0x8bf16996, P0 ?trans1;
IMAD R0, R0, 0x4182bed5, RZ ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R7.reuse, 0x1f123bb5, RZ ?trans2;
IADD3 R5, PT, PT, R0.reuse, 0x75bcd15, RZ ?trans2;
IADD3 R4, PT, PT, R7.reuse, 0x64f0c9, R0 ?trans2;
LOP3.LUT R8, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ?trans1;
STG.E.64 desc[UR4][R2.64+0x18], RZ &req={0} ?trans1;
IADD3 R11, PT, PT, R0, 0x583f19, RZ ?trans2;
LOP3.LUT R10, R7, 0x5491333, RZ, 0x3c, !PT ?trans1;
STG.E.64 desc[UR4][R2.64], R4 ?trans4;
STG.E.64 desc[UR4][R2.64+0x8], R8 ?trans4;
STG.E desc[UR4][R2.64+0x20], RZ ?trans4;
STG.E.64 desc[UR4][R2.64+0x28], RZ ?trans4;
STG.E.64 desc[UR4][R2.64+0x10], R10 ?trans1;
EXIT ?trans5;
BRA 0x230;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: InitRandGen(int, hiprandState*)
_Z11InitRandGeniP12hiprandState:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add_lshl_u32 v1, s14, v1, 5
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, v0, v1
v_cmpx_gt_i32_e32 0x400, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v3, 0x8a5d614f :: v_dual_mov_b32 v6, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v0
v_mad_i64_i32 v[7:8], null, v0, 48, s[0:1]
v_xor_b32_e32 v2, 0x2c7f967f, v1
v_cmp_lt_i32_e32 vcc_lo, -1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, 0x493c4aa1, v2
v_cndmask_b32_e32 v1, 0xfa091aa4, v3, vcc_lo
v_add_nc_u32_e32 v2, 0x1f123bb5, v1
v_xor_b32_e32 v3, 0x5491333, v1
s_delay_alu instid0(VALU_DEP_4)
v_add3_u32 v4, v9, v1, 0x64f0c9
v_add_nc_u32_e32 v0, 0x75bcd15, v9
v_xor_b32_e32 v1, 0x159a55e5, v9
v_add_nc_u32_e32 v9, 0x583f19, v9
s_clause 0x2
global_store_b96 v[7:8], v[4:6], off
global_store_b128 v[7:8], v[0:3], off offset:24
global_store_b32 v[7:8], v9, off offset:40
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| InitRandGen | 1,012 | 849 | stackv2-00000-of-00015 |
// Demangled: RandGen(int*, curandStateXORWOW*)
Function : _Z7RandGenPiP17curandStateXORWOW
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
S2R R5, SR_TID.Y &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x2 ?trans1;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT2_END_GROUP;
IMAD R3, R2, UR5, R5 &req={2} ?WAIT4_END_GROUP;
IMAD R7, R0, 0x20, R3 ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R7, 0x3ff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R7, 0x30, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R4, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR4][R2.64+0x10] &wr=0x3 ?trans4;
LDG.E.64 R8, desc[UR4][R2.64+0x8] &wr=0x4 ?trans1;
SHF.R.U32.HI R0, RZ, 0x2, R5 &req={2} ?trans2;
IADD3 R12, PT, PT, R4, 0x587c5, RZ ?WAIT2_END_GROUP;
LOP3.LUT R0, R0, R5, RZ, 0x3c, !PT ?trans1;
IMAD.SHL.U32 R5, R11, 0x10, RZ &req={3} ?trans1;
MOV R17, R10 ?trans1;
MOV R18, R11 ?trans1;
MOV R16, R9 &req={4} ?trans1;
IADD3 R6, PT, PT, R0, R0, RZ ?WAIT4_END_GROUP;
STG.E.64 desc[UR4][R2.64+0x8], R16 ?trans1;
LOP3.LUT R6, R0, R6, R5, 0x96, !PT ?trans2;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans2;
LOP3.LUT R19, R6, R11, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R19, R12, RZ ?trans1;
STG.E.64 desc[UR4][R2.64+0x10], R18 ?trans4;
IMAD.HI.U32 R6, R0, 0x51eb851f, RZ ?WAIT5_END_GROUP;
SHF.R.U32.HI R13, RZ, 0x5, R6 ?WAIT5_END_GROUP;
IMAD R15, R13, -0x64, R0 ?trans1;
MOV R13, R8 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
STG.E.64 desc[UR4][R2.64], R12 ?trans4;
STG.E desc[UR4][R4.64], R15 ?trans1;
EXIT ?trans5;
BRA 0x280;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: RandGen(int*, hiprandState*)
_Z7RandGenPiP12hiprandState:
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add_lshl_u32 v1, s14, v1, 5
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, v0, v1
v_cmpx_gt_i32_e32 0x400, v0
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[6:7], null, v0, 48, s[2:3]
s_clause 0x2
global_load_b128 v[1:4], v[6:7], off offset:24
global_load_b32 v5, v[6:7], off offset:40
global_load_b32 v8, v[6:7], off
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v9, 2, v1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 0x587c5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v9, v1
v_lshlrev_b32_e32 v9, 4, v5
v_lshlrev_b32_e32 v10, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v9, v10, v9
v_xor3_b32 v9, v9, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, v8, v9
v_mul_hi_u32 v1, 0x51eb851f, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v11, 5, v1
v_ashrrev_i32_e32 v1, 31, v0
v_mul_lo_u32 v11, 0x64, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, v10, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_store_b32 v[6:7], v9, off offset:40
global_store_b128 v[6:7], v[2:5], off offset:24
global_store_b32 v[6:7], v8, off
global_store_b32 v[0:1], v10, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| RandGen | 1,079 | 1,054 | stackv2-00000-of-00015 |
// Demangled: convolve(int const*, int const*, int*, int, int, int, int, int, int, int)
Function : _Z8convolvePKiS0_Piiiiiiii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x3b0] &wr=0x2 ?trans1;
S2R R3, SR_TID.Y &wr=0x3 ?trans1;
LDCU.64 UR8, c[0x0][0x398] &wr=0x4 ?trans5;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R8, c[0x0][0x364] &wr=0x3 ?trans8;
LDC.64 R4, c[0x0][0x3a8] &wr=0x5 ?trans1;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR6, PT &req={2} ?trans2;
LDC.64 R10, c[0x0][0x3a0] &wr=0x1 ?trans1;
IMAD R8, R8, UR5, R3 &req={3} ?WAIT4_END_GROUP;
IMAD R7, R8.reuse, R4.reuse, RZ &req={5} ?trans1;
ISETP.GE.OR P0, PT, R8, R5, P0 ?trans1;
IMAD R6, R9, R4, RZ ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R7, R10, RZ &req={1} ?trans2;
IADD3 R2, PT, PT, R6, R11, RZ ?WAIT3_END_GROUP;
ISETP.GT.OR P0, PT, R0, UR8, P0 &req={4} ?WAIT5_END_GROUP;
ISETP.GT.OR P0, PT, R2, UR9, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
VIMNMX.S32 R3, R10, R11, PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R18, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R3, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xcd0 ?trans5;
IADD3 R3, PT, PT, R6, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B0, 0xcd0 ?trans1;
MOV R18, RZ ?trans1;
MOV R10, R7 ?trans2;
VIMNMX.S32 R3, R2, R3, !PT ?WAIT5_END_GROUP;
IADD3 R12, PT, PT, -R6.reuse, R3.reuse, RZ ?trans2;
IADD3 R11, PT, PT, R6, -R3, RZ ?trans2;
LOP3.LUT R13, R12.reuse, 0xfffffff0, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R28, R12.reuse, 0xf, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R30, R12.reuse, 0x7, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
IADD3 R13, PT, PT, -R13, RZ, RZ ?WAIT7_END_GROUP;
LDCU UR6, c[0x0][0x3a4] &wr=0x1 ?trans1;
ISETP.GT.U32.AND P2, PT, R11, -0x10, PT ?trans1;
IADD3 R17, PT, PT, -R7, R10.reuse, RZ ?trans1;
MOV R15, R10 ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ ?trans1;
BSSY.RECONVERGENT B1, 0x720 ?trans1;
ISETP.NE.AND P0, PT, R28, RZ, PT ?trans1;
MOV R14, R6 ?trans2;
ISETP.GE.AND P1, PT, R10, R0, PT ?trans1;
IMAD R17, R17, UR6, RZ &req={1} ?WAIT4_END_GROUP;
@P2 BRA 0x710 ?trans8;
LDCU UR6, c[0x0][0x39c] &wr=0x1 ?trans1;
MOV R19, R17 ?trans1;
MOV R16, R13 ?trans1;
MOV R14, R6 ?trans1;
IMAD R21, R15, UR6, R6 &req={1} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R2, R21, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
LDG.E R25, desc[UR4][R2.64] &req={0} &wr=0x3 ?trans1;
IMAD.WIDE R4, R19, 0x4, R4 &req={2} ?WAIT3_END_GROUP;
LDG.E R27, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R22, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R34, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R20, desc[UR4][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R24, desc[UR4][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R26, desc[UR4][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R31, desc[UR4][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R32, desc[UR4][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R33, desc[UR4][R4.64+0x14] &wr=0x5 ?trans4;
LDG.E R35, desc[UR4][R4.64+0x3c] &wr=0x5 ?trans1;
IMAD R22, R25, R22, R18 &req={3} ?WAIT3_END_GROUP;
LDG.E R18, desc[UR4][R2.64+0x1c] &wr=0x3 ?trans1;
IMAD R34, R27, R34, R22 &req={2} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R2.64+0x18] &wr=0x2 ?trans4;
LDG.E R27, desc[UR4][R4.64+0x18] &wr=0x2 ?trans1;
IMAD R34, R23, R20, R34 &req={4} ?WAIT3_END_GROUP;
LDG.E R23, desc[UR4][R4.64+0x1c] &wr=0x3 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x20] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R4.64+0x20] &wr=0x4 ?trans1;
IMAD R24, R24, R29, R34 &req={5} ?WAIT3_END_GROUP;
LDG.E R29, desc[UR4][R4.64+0x24] &wr=0x5 ?trans1;
IMAD R26, R26, R31, R24 ?WAIT3_END_GROUP;
LDG.E R24, desc[UR4][R2.64+0x24] &wr=0x5 ?trans4;
LDG.E R31, desc[UR4][R4.64+0x28] &wr=0x5 ?trans1;
IMAD R32, R32, R33, R26 ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64+0x28] &wr=0x5 ?trans4;
LDG.E R33, desc[UR4][R4.64+0x34] &wr=0x5 ?trans4;
LDG.E R34, desc[UR4][R2.64+0x3c] &wr=0x5 ?trans1;
IMAD R32, R22, R27, R32 &req={2} ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R2.64+0x2c] &wr=0x2 ?trans1;
IMAD R32, R18, R23, R32 &req={3} ?WAIT3_END_GROUP;
LDG.E R27, desc[UR4][R4.64+0x2c] &wr=0x2 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x30] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R4.64+0x30] &wr=0x3 ?trans1;
IMAD R36, R20, R25, R32 &req={4} ?WAIT3_END_GROUP;
LDG.E R32, desc[UR4][R2.64+0x34] &wr=0x4 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x38] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R4.64+0x38] &wr=0x4 ?trans1;
IMAD R24, R24, R29, R36 &req={5} ?trans1;
IADD3 R16, PT, PT, R16, 0x10, RZ ?WAIT3_END_GROUP;
IMAD R24, R26, R31, R24 ?trans2;
ISETP.NE.AND P2, PT, R16, RZ, PT ?trans1;
IADD3 R14, PT, PT, R14, 0x10, RZ ?trans2;
IADD3 R21, PT, PT, R21, 0x10, RZ ?trans2;
IADD3 R19, PT, PT, R19, 0x10, RZ ?trans1;
IMAD R22, R22, R27, R24 &req={2} ?WAIT4_END_GROUP;
IMAD R18, R18, R23, R22 &req={3} ?WAIT4_END_GROUP;
IMAD R18, R32, R33, R18 &req={4} ?WAIT4_END_GROUP;
IMAD R18, R20, R25, R18 ?WAIT4_END_GROUP;
IMAD R18, R34, R35, R18 ?trans1;
@P2 BRA 0x370 ?trans6;
BSYNC.RECONVERGENT B1 &req={0} ?trans5;
BSSY.RECONVERGENT B1, 0xcb0 ?trans1;
IADD3 R17, PT, PT, -R6, R17, RZ ?WAIT3_END_GROUP;
@!P0 BRA 0xca0 ?trans5;
IADD3 R2, PT, PT, R28, -0x1, RZ ?trans1;
BSSY.RECONVERGENT B2, 0x9b0 ?trans1;
ISETP.NE.AND P2, PT, R30, RZ, PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, 0x7, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x9a0 ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x1 ?trans1;
IADD3 R21, PT, PT, R17, R14, RZ ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R19, R15, UR6, R14 &req={1} ?trans2;
IMAD.WIDE R2, R21, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R31, desc[UR4][R2.64] &wr=0x3 ?trans1;
IMAD.WIDE R4, R19, 0x4, R4 &req={2} ?WAIT3_END_GROUP;
LDG.E R33, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R29, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E R32, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R35, desc[UR4][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R34, desc[UR4][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R24, desc[UR4][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R22, desc[UR4][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x14] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R4.64+0x14] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R4.64+0x18] &wr=0x5 ?trans4;
LDG.E R27, desc[UR4][R2.64+0x18] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R4.64+0x1c] &wr=0x5 ?trans4;
LDG.E R26, desc[UR4][R2.64+0x1c] &wr=0x5 ?trans1;
IADD3 R14, PT, PT, R14, 0x8, RZ ?trans1;
IMAD R29, R29, R31, R18 &req={3} ?WAIT4_END_GROUP;
IMAD R29, R32, R33, R29 &req={2} ?WAIT4_END_GROUP;
IMAD R29, R34, R35, R29 &req={4} ?WAIT4_END_GROUP;
IMAD R23, R23, R24, R29 &req={5} ?WAIT4_END_GROUP;
IMAD R21, R21, R22, R23 ?WAIT4_END_GROUP;
IMAD R19, R19, R20, R21 ?WAIT4_END_GROUP;
IMAD R16, R16, R27, R19 ?WAIT4_END_GROUP;
IMAD R18, R25, R26, R16 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
@!P2 BRA 0xca0 ?trans5;
IADD3 R2, PT, PT, R30, -0x1, RZ ?trans1;
BSSY.RECONVERGENT B2, 0xb60 ?trans1;
ISETP.NE.AND P2, PT, R12, RZ, PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0xb50 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x1 ?trans1;
IADD3 R21, PT, PT, R17, R14, RZ ?WAIT6_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R19, R15, UR6, R14 &req={1} ?trans2;
IMAD.WIDE R4, R21, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R16, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R2, R19, 0x4, R2 &req={2} ?WAIT3_END_GROUP;
LDG.E R20, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R2.64] &wr=0x3 ?trans4;
LDG.E R21, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R22, desc[UR4][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R23, desc[UR4][R2.64+0x8] &wr=0x4 ?trans4;
LDG.E R25, desc[UR4][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R24, desc[UR4][R4.64+0xc] &wr=0x5 ?trans1;
IADD3 R14, PT, PT, R14, 0x4, RZ ?trans1;
IMAD R16, R19, R16, R18 &req={3} ?WAIT4_END_GROUP;
IMAD R16, R21, R20, R16 &req={2} ?WAIT4_END_GROUP;
IMAD R16, R23, R22, R16 &req={4} ?WAIT4_END_GROUP;
IMAD R18, R25, R24, R16 &req={5} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
@!P2 BRA 0xca0 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x1 ?trans1;
IADD3 R17, PT, PT, R17, R14, RZ ?WAIT6_END_GROUP;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R15, R15, UR6, R14 &req={1} ?trans2;
IMAD.WIDE R4, R17, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R14, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R2, R15, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R15, desc[UR4][R2.64] &wr=0x3 ?trans1;
ISETP.NE.AND P0, PT, R12, 0x1, PT ?trans1;
IMAD R18, R15, R14, R18 &req={3} ?WAIT12_END_GROUP;
@!P0 BRA 0xca0 ?trans5;
ISETP.NE.AND P0, PT, R12, 0x2, PT ?trans1;
LDG.E R15, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R14, desc[UR4][R4.64+0x4] &wr=0x2 ?trans8;
@P0 LDG.E R17, desc[UR4][R2.64+0x8] &wr=0x3 ?trans4;
@P0 LDG.E R16, desc[UR4][R4.64+0x8] &wr=0x3 ?trans1;
IMAD R18, R15, R14, R18 &req={2} ?WAIT4_END_GROUP;
@P0 IMAD R18, R17, R16, R18 &req={3} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
@!P1 BRA 0x270 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x3b0] &wr=0x2 ?trans2;
IMAD R9, R8, UR6, R9 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R18 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xd30;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: convolve(int const*, int const*, int*, int, int, int, int, int, int, int)
_Z8convolvePKiS0_Piiiiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x28
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[3:4]
s_mul_i32 s7, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, s7, v2
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s6, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
s_load_b128 s[8:11], s[0:1], 0x18
v_mul_lo_u32 v6, v0, s4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s10, v6
v_cmp_ge_i32_e32 vcc_lo, s8, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
v_mul_lo_u32 v8, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s11, v8
v_cmp_ge_i32_e32 vcc_lo, s9, v9
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_11
v_mul_lo_u32 v3, s9, v0
s_cmp_gt_i32 s11, 0
s_mov_b32 s8, 0
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v3, s7
s_mov_b32 s7, 0
v_mul_lo_u32 v3, s4, v2
v_mov_b32_e32 v2, 0
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v10, v8
s_mov_b32 s10, 0
s_mov_b32 s4, s8
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
.LBB0_7:
global_load_b32 v13, v[4:5], off
s_ashr_i32 s5, s4, 31
v_add_nc_u32_e32 v10, 1, v10
s_lshl_b64 s[16:17], s[4:5], 2
v_add_co_u32 v4, vcc_lo, v4, 4
s_add_u32 s16, s14, s16
s_addc_u32 s17, s15, s17
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_load_b32 s0, s[16:17], 0x0
s_add_i32 s4, s4, 1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[11:12], null, s0, v13, v[2:3]
v_cmp_ge_i32_e64 s0, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s10, s0, s10
v_mov_b32_e32 v2, v11
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s10
.LBB0_9:
v_add_nc_u32_e32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s9, v3
s_add_i32 s8, s8, s11
v_cmp_ge_i32_e32 vcc_lo, v6, v7
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s7
s_branch .LBB0_12
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s6, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| convolve | 5,694 | 1,959 | stackv2-00000-of-00015 |
// Demangled: Lx1(float const*, float*, int, int, float*)
Function : _Z3Lx1PKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R2, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R3, SR_TID.Y &wr=0x2 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R23, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R23, R23, UR5, R0 &req={1} ?trans1;
IADD3 R0, PT, PT, R4, -0x6, RZ &req={3} ?WAIT2_END_GROUP;
IADD3 R5, PT, PT, R5, -0x6, RZ ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R23, R0, PT ?trans1;
IMAD R0, R2, UR4, R3 &req={2} ?WAIT4_END_GROUP;
ISETP.LT.OR P0, PT, R23, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R0, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, R5, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R2, PT, PT, R0.reuse, 0x1, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R9, PT, PT, R0.reuse, -0x3, RZ ?trans2;
IADD3 R8, PT, PT, R0.reuse, -0x2, RZ ?trans2;
IADD3 R3, PT, PT, R0, -0x1, RZ ?trans1;
IMAD R15, R2, R4.reuse, R23.reuse ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
IMAD R9, R9, R4.reuse, R23.reuse ?trans1;
IADD3 R12, PT, PT, R0, -0x6, RZ ?trans1;
IMAD R13, R8, R4.reuse, R23.reuse ?trans1;
IADD3 R10, PT, PT, R0.reuse, -0x4, RZ ?trans1;
IMAD R3, R3, R4.reuse, R23.reuse ?trans1;
IADD3 R11, PT, PT, R0, -0x5, RZ ?trans1;
IMAD R17, R12, R4, R23 ?WAIT2_END_GROUP;
IMAD R33, R10, R4.reuse, R23.reuse ?trans2;
IMAD R11, R11, R4, R23 ?trans2;
IMAD.WIDE R14, R15, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R28, R9, 0x4, R6.reuse ?trans1;
IADD.64 R8, R4, R4 ?trans2;
LDG.E R31, desc[UR4][R14.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R12, R13, 0x4, R6.reuse ?trans1;
IADD.64 R20, R4, R8 ?trans2;
LDG.E R27, desc[UR4][R28.64] &wr=0x3 ?trans1;
IMAD.WIDE R18, R3, 0x4, R6 ?trans2;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans1;
LDG.E R25, desc[UR4][R12.64] &rd=0x1 &wr=0x4 ?trans1;
IMAD.WIDE R34, R4, 0x4, R14 ?trans1;
LEA R16, P0, R8, R14, 0x2 ?WAIT2_END_GROUP;
LDG.E R24, desc[UR4][R18.64] &rd=0x5 &wr=0x2 ?trans1;
IMAD.WIDE R32, R33, 0x4, R6 ?WAIT3_END_GROUP;
LDG.E R22, desc[UR4][R34.64] &wr=0x4 ?trans1;
IMAD.WIDE R10, R11, 0x4, R6.reuse ?trans1;
LEA R12, P1, R20, R14, 0x2 &req={1} ?trans2;
LDG.E R29, desc[UR4][R2.64+0x4] &req={0} &wr=0x3 ?trans1;
IMAD.WIDE R6, R17, 0x4, R6 ?trans1;
IADD.64 R18, R4, R20 &req={5} ?trans2;
LDG.E R28, desc[UR4][R2.64] &wr=0x5 ?trans1;
LEA.HI.X R17, R8, R15.reuse, R9, 0x2, P0 ?trans2;
LEA.HI.X R13, R20, R15, R21, 0x2, P1 ?trans1;
IADD.64 R20, R4, R18 ?WAIT2_END_GROUP;
LDG.E R16, desc[UR4][R16.64] &wr=0x5 ?trans1;
LEA R8, P0, R18, R14, 0x2 ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R32.64] &wr=0x5 ?trans1;
LEA.HI.X R9, R18, R15.reuse, R19, 0x2, P0 ?trans2;
LEA R18, P0, R20.reuse, R14, 0x2 ?trans1;
LDG.E R5, desc[UR4][R2.64+0x8] &wr=0x5 ?trans3;
LEA.HI.X R19, R20, R15, R21, 0x2, P0 ?trans1;
LDG.E R10, desc[UR4][R10.64] &wr=0x5 ?trans4;
LDG.E R33, desc[UR4][R12.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R9, desc[UR4][R8.64] &wr=0x5 ?trans1;
LDC.64 R12, c[0x0][0x388] &req={0} &wr=0x0 ?trans3;
LDG.E R6, desc[UR4][R6.64] &wr=0x5 ?trans4;
LDG.E R20, desc[UR4][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R18.64] &wr=0x5 ?trans4;
LDG.E R30, desc[UR4][R2.64+0x14] &wr=0x5 ?trans1;
IMAD R23, R0, R4, R23 ?WAIT4_END_GROUP;
IMAD.WIDE R12, R23, 0x4, R12 &req={0} ?WAIT4_END_GROUP;
FADD R31, R31, -R24 &req={2} ?trans1;
FADD R22, R22, -R25 &req={4} ?WAIT4_END_GROUP;
FMUL R29, R29, R22 &req={3} ?WAIT4_END_GROUP;
FFMA R28, R28, R31, R29 &req={5} ?trans1;
FADD R16, R16, -R27 ?WAIT4_END_GROUP;
FFMA R5, R5, R16, R28 ?trans1;
FADD R26, R33, -R26 ?WAIT4_END_GROUP;
FFMA R5, R14, R26, R5 ?trans1;
FADD R9, R9, -R10 ?WAIT4_END_GROUP;
FFMA R5, R20, R9, R5 ?trans1;
FADD R6, R19, -R6 ?WAIT4_END_GROUP;
FFMA R5, R30, R6, R5 ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x5a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Lx1(float const*, float*, int, int, float*)
_Z3Lx1PKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s8, -6
s_add_i32 s3, s9, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB3_2
v_mul_lo_u32 v21, v1, s8
s_lshl_b32 s2, s8, 1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s8, v21
v_subrev_nc_u32_e32 v1, s2, v7
s_lshl_b32 s2, s8, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s8, 3, v[1:2]
v_add_nc_u32_e32 v8, v1, v0
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v3, s2, v2
s_lshl_b32 s2, s8, 3
v_add_nc_u32_e32 v1, v2, v0
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s8, 5, v[3:4]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mad_u64_u32 v[5:6], null, s8, -6, v[4:5]
v_add_nc_u32_e32 v6, v7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_mad_u64_u32 v[10:11], null, s8, 7, v[5:6]
v_add_nc_u32_e32 v11, v3, v0
v_add_nc_u32_e32 v3, v4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_nc_u32_e32 v17, v5, v0
v_ashrrev_i32_e32 v4, 31, v3
v_subrev_nc_u32_e32 v12, s2, v10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_add_nc_u32_e32 v13, v12, v0
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[15:16], null, s8, 9, v[13:14]
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_nc_u32_e32 v5, v10, v0
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_ashrrev_i32_e32 v18, 31, v17
v_ashrrev_i32_e32 v16, 31, v15
s_clause 0x3
global_load_b32 v22, v[6:7], off
global_load_b32 v23, v[8:9], off
global_load_b32 v24, v[1:2], off
global_load_b32 v25, v[11:12], off
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[1:2], 2, v[17:18]
v_mad_u64_u32 v[19:20], null, s8, -10, v[15:16]
v_lshlrev_b64 v[9:10], 2, v[13:14]
v_add_co_u32 v3, vcc_lo, s4, v3
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[7:8], null, s8, 11, v[19:20]
v_add_co_u32 v5, vcc_lo, s4, v5
v_lshlrev_b64 v[11:12], 2, v[15:16]
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[13:14], 2, v[19:20]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_4)
v_mad_u64_u32 v[15:16], null, s8, -12, v[7:8]
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v13
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_ashrrev_i32_e32 v16, 31, v15
s_clause 0x5
global_load_b32 v17, v[3:4], off
global_load_b32 v18, v[1:2], off
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[9:10], off
global_load_b32 v9, v[11:12], off
global_load_b32 v10, v[13:14], off
v_add_nc_u32_e32 v0, v21, v0
v_add_co_u32 v3, vcc_lo, s4, v7
v_lshlrev_b64 v[1:2], 2, v[15:16]
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(8)
v_dual_sub_f32 v4, v22, v23 :: v_dual_sub_f32 v1, v24, v25
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, s9, v1
v_fmac_f32_e32 v7, s8, v4
s_waitcnt vmcnt(6)
v_sub_f32_e32 v1, v17, v18
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v9, v10 :: v_dual_fmac_f32 v7, s10, v1
v_sub_f32_e32 v1, v5, v6
v_fmac_f32_e32 v7, s11, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, s0, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_fmac_f32_e32 v7, s1, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Lx1 | 2,380 | 3,472 | stackv2-00000-of-00015 |
// Demangled: Lx2(float const*, float*, int, int, float*)
Function : _Z3Lx2PKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R21, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R23, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R12, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R23, R23, UR5, R0 &req={1} ?trans1;
IADD3 R0, PT, PT, R12, -0x5, RZ &req={3} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R23, R0, PT ?trans1;
IADD3 R0, PT, PT, R13, -0x5, RZ ?trans1;
IMAD R21, R21, UR4, R2 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R23, 0x5, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R21, 0x5, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R21, R0, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IMAD R0, R21.reuse, R12.reuse, -R12.reuse ?trans1;
SHF.R.S32.HI R13, RZ, 0x1f, R12.reuse ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
IMAD R21, R21, R12.reuse, R23 ?trans2;
IADD3 R3, PT, PT, R0, R12, R12 ?trans2;
IADD3 R17, PT, PT, R23, R0, RZ ?WAIT3_END_GROUP;
IMAD R4, R12.reuse, -0x3, R3 ?trans2;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans3;
LEA R5, R12, R4.reuse, 0x2 ?trans2;
IADD3 R31, PT, PT, R23, R4, RZ ?WAIT3_END_GROUP;
IMAD R5, R12, -0x5, R5 ?WAIT4_END_GROUP;
IMAD R7, R12, 0x6, R5 ?trans1;
IADD3 R19, PT, PT, R23, R5, RZ ?WAIT3_END_GROUP;
IMAD R25, R12, -0x7, R7 ?WAIT5_END_GROUP;
LEA R7, R12, R25.reuse, 0x3 ?trans2;
IADD3 R25, PT, PT, R23, R25, RZ ?trans1;
IMAD.WIDE R8, R21, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD R0, R12.reuse, -0x9, R7 ?trans1;
IADD.64 R6, R12.reuse, R12 ?trans2;
IMAD.WIDE R26, R12.reuse, 0x4, R8 ?trans2;
IADD.64 R10, R12, R6 ?trans2;
IMAD.WIDE R16, R17, 0x4, R2.reuse ?trans1;
LEA R28, P0, R6, R8.reuse, 0x2 ?trans1;
LDG.E R27, desc[UR4][R26.64] &req={0} &wr=0x2 ?trans1;
LEA R4, P1, R10, R8, 0x2 ?trans1;
IMAD.WIDE R30, R31, 0x4, R2 ?trans1;
LEA.HI.X R29, R6, R9, R7, 0x2, P0 ?WAIT2_END_GROUP;
LDC.64 R6, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R23, PT, PT, R23, R0, RZ ?trans2;
LEA.HI.X R5, R10, R9, R11, 0x2, P1 ?trans1;
IADD.64 R10, R12.reuse, R10 ?trans2;
LDG.E R0, desc[UR4][R16.64] &rd=0x1 &wr=0x2 ?trans2;
IADD.64 R12, R12, R10 ?trans2;
LDG.E R22, desc[UR4][R6.64+0x4] &req={0} &wr=0x3 ?trans1;
LEA R14, P0, R10, R8, 0x2 ?trans1;
IMAD.WIDE R18, R19, 0x4, R2 ?WAIT2_END_GROUP;
LDG.E R20, desc[UR4][R30.64] &wr=0x4 ?trans1;
LEA R16, P1, R12, R8, 0x2 &req={1} ?WAIT3_END_GROUP;
LDG.E R29, desc[UR4][R28.64] &wr=0x4 ?trans1;
LEA.HI.X R15, R10, R9.reuse, R11, 0x2, P0 ?trans1;
IMAD.WIDE R10, R25, 0x4, R2 ?trans2;
LDG.E R24, desc[UR4][R6.64] &wr=0x5 ?trans1;
LEA.HI.X R17, R12, R9, R13, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R31, desc[UR4][R8.64] &wr=0x5 ?trans1;
IMAD.WIDE R32, R23, 0x4, R2 ?trans2;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDG.E R18, desc[UR4][R18.64] &wr=0x5 ?trans4;
LDG.E R12, desc[UR4][R6.64+0x8] &wr=0x5 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R14.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R10.64] &wr=0x5 ?trans4;
LDG.E R13, desc[UR4][R6.64+0xc] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x5 ?trans4;
LDG.E R8, desc[UR4][R6.64+0x10] &wr=0x5 ?trans4;
LDG.E R32, desc[UR4][R32.64] &wr=0x5 ?trans4;
LDG.E R26, desc[UR4][R6.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R2, R21, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
FADD R27, R0, R27 &req={2} ?WAIT4_END_GROUP;
FMUL R27, R22, R27 &req={3} ?trans1;
FADD R20, R20, R29 &req={4} ?WAIT3_END_GROUP;
FFMA R27, R24, R31, R27 &req={5} ?WAIT4_END_GROUP;
FFMA R12, R12, R20, R27 ?trans1;
FADD R5, R18, R5 ?trans1;
FADD R11, R11, R14 ?WAIT3_END_GROUP;
FFMA R5, R13, R5, R12 ?WAIT4_END_GROUP;
FFMA R5, R8, R11, R5 ?trans1;
FADD R17, R32, R17 ?WAIT4_END_GROUP;
FFMA R5, R26, R17, R5 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x570;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Lx2(float const*, float*, int, int, float*)
_Z3Lx2PKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s8, -5
s_add_i32 s3, s9, -5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 4, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 4, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v2, v1, s8
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s8, v2
v_add_nc_u32_e32 v11, v2, v0
v_add_nc_u32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshl_add_u32 v3, s8, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s8, -3, v[3:4]
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_lshl_add_u32 v7, s8, 2, v5
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
s_clause 0x2
global_load_b32 v19, v[15:16], off
global_load_b32 v20, v[0:1], off
global_load_b32 v21, v[2:3], off
v_ashrrev_i32_e32 v6, 31, v5
v_mad_u64_u32 v[9:10], null, s8, -5, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_lshlrev_b64 v[0:1], 2, v[7:8]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_mad_u64_u32 v[13:14], null, s8, 6, v[9:10]
v_lshlrev_b64 v[6:7], 2, v[9:10]
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v14, 31, v13
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_mad_u64_u32 v[17:18], null, s8, -7, v[13:14]
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s4, v13
v_lshl_add_u32 v2, s8, 3, v17
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 2, v[17:18]
v_mad_u64_u32 v[8:9], null, s8, -9, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[17:18], null, s8, 10, v[8:9]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_clause 0x5
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[13:14], off
global_load_b32 v10, v[15:16], off
global_load_b32 v13, v[2:3], off
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_u32 v2, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[17:18]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_clause 0x1
s_load_b128 s[0:3], s[10:11], 0x0
s_load_b64 s[4:5], s[10:11], 0x10
s_waitcnt vmcnt(0)
v_dual_add_f32 v1, v20, v21 :: v_dual_add_f32 v0, v2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, s1, v1
v_add_f32_e32 v1, v4, v5
v_fmac_f32_e32 v3, s0, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, s2, v1
v_add_f32_e32 v1, v6, v7
v_fmac_f32_e32 v3, s3, v1
v_add_f32_e32 v1, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, s4, v1
v_fmac_f32_e32 v3, s5, v0
v_add_co_u32 v0, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v12, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Lx2 | 2,281 | 3,148 | stackv2-00000-of-00015 |
// Demangled: Lz1(float const*, float*, int, int, float*)
Function : _Z3Lz1PKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
LDC R7, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x6, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R0, R0, UR6, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR4, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR9, -0x6, URZ ?trans1;
IMAD R7, R7, UR5, R2 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R0, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R7, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R7, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R7, R7, UR8, R0 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x398] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
LDG.E R10, desc[UR4][R4.64+0x4] &req={1} &wr=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R7, 0x4, R8 &req={0} ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x8] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x8] &wr=0x3 ?trans4;
LDG.E R6, desc[UR4][R8.64+0x4] &wr=0x4 ?trans4;
LDG.E R11, desc[UR4][R8.64+-0x4] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R8.64+0xc] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0xc] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R8.64+0x10] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R8.64+-0x10] &wr=0x5 ?trans4;
LDG.E R18, desc[UR4][R8.64+0x14] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R8.64+-0x14] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R20, desc[UR4][R8.64+0x18] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R8.64+-0x18] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R27, desc[UR4][R4.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
FADD R13, R12, -R13 &req={3} ?WAIT4_END_GROUP;
FMUL R13, R10, R13 ?trans1;
FADD R11, R6, -R11 &req={4} ?WAIT4_END_GROUP;
FFMA R0, R0, R11, R13 ?trans1;
FADD R14, R14, -R17 &req={5} ?WAIT4_END_GROUP;
FFMA R0, R15, R14, R0 ?trans1;
FADD R16, R16, -R21 ?trans1;
FADD R18, R18, -R25 ?WAIT3_END_GROUP;
FFMA R0, R19, R16, R0 ?trans1;
FADD R20, R20, -R29 ?WAIT3_END_GROUP;
FFMA R0, R23, R18, R0 ?WAIT4_END_GROUP;
FFMA R27, R27, R20, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 ?trans1;
EXIT ?trans5;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Lz1(float const*, float*, int, int, float*)
_Z3Lz1PKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s6, -6
s_add_i32 s3, s7, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v9, vcc_lo
s_clause 0x3
global_load_b128 v[0:3], v[10:11], off offset:4
global_load_b64 v[12:13], v[10:11], off offset:-8
global_load_b128 v[4:7], v[10:11], off offset:-24
global_load_b64 v[10:11], v[10:11], off offset:20
s_clause 0x1
s_load_b128 s[0:3], s[4:5], 0x0
s_load_b64 s[4:5], s[4:5], 0x10
s_waitcnt vmcnt(2)
v_dual_sub_f32 v1, v1, v12 :: v_dual_sub_f32 v0, v0, v13
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v12, s1, v1 :: v_dual_sub_f32 v1, v2, v7
v_fmac_f32_e32 v12, s0, v0
v_sub_f32_e32 v0, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, s2, v1
s_waitcnt vmcnt(0)
v_dual_sub_f32 v1, v10, v5 :: v_dual_fmac_f32 v12, s3, v0
v_sub_f32_e32 v0, v11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, s4, v1
v_fmac_f32_e32 v12, s5, v0
v_add_co_u32 v0, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v9, vcc_lo
global_store_b32 v[0:1], v12, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Lz1 | 1,545 | 1,355 | stackv2-00000-of-00015 |
// Demangled: Lz2(float const*, float*, int, int, float*)
Function : _Z3Lz2PKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R5, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x5, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R3, R3, UR6, R2 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, UR4, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR9, -0x5, URZ ?trans1;
IMAD R0, R0, UR5, R5 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R3, 0x5, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R0, 0x5, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R9, R0, UR8, R3 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x398] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
LDG.E R8, desc[UR4][R4.64+0x4] &req={1} &wr=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64+-0x4] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E R12, desc[UR4][R6.64+-0x8] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R6.64+0x8] &wr=0x4 ?trans4;
LDG.E R11, desc[UR4][R6.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR4][R6.64+-0xc] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R6.64+0xc] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R6.64+-0x10] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R6.64+0x10] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R18, desc[UR4][R6.64+-0x14] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R6.64+0x14] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R27, desc[UR4][R4.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
FADD R13, R10, R13 &req={3} ?WAIT4_END_GROUP;
FMUL R13, R8, R13 ?trans1;
FADD R12, R12, R17 &req={4} ?WAIT3_END_GROUP;
FFMA R0, R0, R11, R13 &req={5} ?WAIT4_END_GROUP;
FFMA R0, R15, R12, R0 ?trans1;
FADD R14, R14, R21 ?trans1;
FADD R16, R16, R25 ?WAIT3_END_GROUP;
FFMA R0, R19, R14, R0 ?trans1;
FADD R18, R18, R29 ?WAIT3_END_GROUP;
FFMA R0, R23, R16, R0 ?WAIT4_END_GROUP;
FFMA R27, R27, R18, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 ?trans1;
EXIT ?trans5;
BRA 0x360;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Lz2(float const*, float*, int, int, float*)
_Z3Lz2PKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s6, -5
s_add_i32 s3, s7, -5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 4, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 4, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[11:12], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v12, vcc_lo
s_clause 0x2
global_load_b128 v[0:3], v[8:9], off offset:-4
global_load_b128 v[4:7], v[8:9], off offset:-20
global_load_b96 v[8:10], v[8:9], off offset:12
s_clause 0x1
s_load_b128 s[0:3], s[4:5], 0x0
s_load_b64 s[4:5], s[4:5], 0x10
s_waitcnt vmcnt(2)
v_add_f32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, s1, v0
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v7, v3
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v2, s0, v1 :: v_dual_add_f32 v1, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s2, v0
v_add_f32_e32 v0, v5, v9
v_dual_fmac_f32 v2, s3, v1 :: v_dual_add_f32 v1, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s4, v0
v_add_co_u32 v0, vcc_lo, s10, v11
v_fmac_f32_e32 v2, s5, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v12, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| Lz2 | 1,472 | 1,310 | stackv2-00000-of-00015 |
// Demangled: rsgbfd(float const*, float*, float*, int, int, float*)
Function : _Z6rsgbfdPKfPfS1_iiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R25, SR_TID.X &wr=0x1 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x398] &wr=0x3 ?trans1;
S2R R3, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR13, SR_CTAID.X &wr=0x1 ?trans8;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x6, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR12, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R2, R2, UR13, R25 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR4, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR9, -0x6, URZ ?trans1;
IMAD R0, R0, UR12, R3 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R2, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R0, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R0, c[0x0][0x364] &wr=0x0 ?trans1;
MOV R5, UR8 ?trans1;
LDCU.128 UR16, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R10, 0x4 ?trans1;
MOV R17, UR8 ?trans1;
HFMA2 R9, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR8 ?trans2;
UMOV UR4, UR8 ?trans1;
LDC R4, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x3 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR4, URZ ?WAIT6_END_GROUP;
MOV R13, UR6 ?trans1;
MOV R14, UR7 ?trans1;
IMAD R0, R0, UR12, R3 &req={0} ?trans1;
MOV R3, UR8 ?WAIT3_END_GROUP;
IMAD R6, R0, R5, -UR8 ?trans2;
IMAD R25, R4, UR13, R25 &req={2} ?WAIT3_END_GROUP;
IADD3 R2, PT, PT, R6, UR8, R3 ?trans1;
IMAD R0, R0, UR8, R25 ?WAIT4_END_GROUP;
IMAD R8, R5, -0x3, R2 ?WAIT4_END_GROUP;
IMAD R2, R3, 0x4, R8 ?trans1;
IADD3 R7, PT, PT, R25.reuse, R8, RZ ?trans1;
MOV R3, UR6 ?trans1;
IADD3 R8, PT, PT, R25, R6, RZ ?trans1;
IMAD R2, R5, -0x5, R2 ?trans2;
HFMA2 R5, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
IMAD.WIDE R6, R7, R10, UR16 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R0, R5, UR16 ?WAIT4_END_GROUP;
HFMA2 R15, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LDC.64 R10, c[0x0][0x3a0] &wr=0x0 ?trans1;
LDG.E R31, desc[UR10][R6.64+0x4] &req={3} &wr=0x2 ?trans1;
LEA R12, P0, R13, R4, 0x2 ?trans1;
IMAD.WIDE R16, R17, 0x4, R4 ?trans2;
LDG.E R30, desc[UR10][R10.64+0x4] &req={0} &wr=0x3 ?trans1;
LEA.HI.X R13, R3, R5, R14, 0x2, P0 ?trans2;
IADD3 R14, PT, PT, R25, R2, RZ ?trans1;
LDG.E R32, desc[UR10][R16.64+-0x8] &wr=0x2 ?trans1;
IMAD.WIDE R8, R8, R9, UR16 ?trans1;
MOV R3, UR8 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR6, URZ ?trans1;
LDG.E R28, desc[UR10][R4.64+-0x4] &wr=0x4 ?trans1;
IMAD.WIDE R14, R14, R15, UR16 ?trans1;
MOV R19, UR8 ?WAIT2_END_GROUP;
LDG.E R29, desc[UR10][R8.64] &wr=0x4 ?trans1;
IMAD R34, R3, 0x6, R2 ?WAIT3_END_GROUP;
LDG.E R21, desc[UR10][R12.64+-0xc] &wr=0x5 ?trans4;
LDG.E R20, desc[UR10][R14.64+0x8] &wr=0x5 ?trans1;
MOV R3, UR6 ?trans1;
IMAD R34, R19, -0x7, R34 ?trans2;
LDG.E R23, desc[UR10][R10.64] &wr=0x5 ?trans1;
MOV R19, UR6 ?trans1;
MOV R24, UR7 ?trans1;
MOV R27, 0x4 ?trans1;
LEA R2, P0, R3, R4, 0x2 ?trans1;
LDG.E R22, desc[UR10][R10.64+0x8] &wr=0x5 ?trans1;
IADD3 R18, PT, PT, R25, R34, RZ ?WAIT2_END_GROUP;
LEA.HI.X R3, R19, R5, R24, 0x2, P0 ?trans2;
LDG.E R24, desc[UR10][R10.64+0xc] &wr=0x5 ?trans1;
IMAD.WIDE R18, R18, R27, UR16 ?WAIT3_END_GROUP;
LDG.E R26, desc[UR10][R2.64+-0x10] &wr=0x5 ?trans4;
LDG.E R27, desc[UR10][R18.64+0xc] &wr=0x5 ?trans1;
MOV R33, UR8 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR6, URZ ?WAIT4_END_GROUP;
LEA R34, R33, R34, 0x3 ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, UR6, URZ ?trans1;
MOV R35, UR8 ?trans1;
FADD R31, R32, -R31 &req={2} ?WAIT4_END_GROUP;
FMUL R32, R30, R31 &req={3} ?trans1;
MOV R31, UR8 ?trans1;
FADD R30, R28, -R29 &req={4} ?WAIT4_END_GROUP;
IMAD R28, R31, -0x9, R34 ?trans1;
MOV R31, UR6 ?trans1;
FADD R29, R21, -R20 &req={5} ?trans1;
MOV R21, UR6 ?trans1;
FFMA R23, R23, R30, R32 ?trans1;
MOV R32, UR7 ?WAIT3_END_GROUP;
LEA R20, P0, R21, R4, 0x2 ?trans1;
IMAD R30, R33, 0xa, R28 ?WAIT3_END_GROUP;
LEA.HI.X R21, R31, R5, R32, 0x2, P0 ?trans1;
MOV R31, UR4 ?trans1;
IMAD R30, R35, -0xb, R30 ?trans2;
FFMA R29, R22, R29, R23 ?trans1;
HFMA2 R32, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
LEA R22, P0, R31, R4, 0x2 ?trans2;
IADD3 R31, PT, PT, R25.reuse, R28, RZ ?trans2;
IADD3 R25, PT, PT, R25, R30, RZ ?trans1;
MOV R23, UR4 ?trans1;
MOV R33, UR5 ?trans1;
FADD R28, R26, -R27 ?trans1;
MOV R30, 0x4 ?trans1;
IMAD.WIDE R26, R31, R32, UR16 ?WAIT4_END_GROUP;
FFMA R29, R24, R28, R29 ?trans1;
LEA.HI.X R23, R23, R5, R33, 0x2, P0 ?trans1;
IMAD.WIDE R24, R25, R30, UR16 ?trans1;
LDG.E R31, desc[UR10][R20.64+-0x14] &wr=0x2 ?trans4;
LDG.E R32, desc[UR10][R26.64+0x10] &wr=0x2 ?trans4;
LDG.E R30, desc[UR10][R10.64+0x10] &wr=0x3 ?trans4;
LDG.E R33, desc[UR10][R22.64+-0x18] &wr=0x4 ?trans4;
LDG.E R34, desc[UR10][R24.64+0x14] &wr=0x4 ?trans4;
LDG.E R28, desc[UR10][R10.64+0x14] &wr=0x5 ?trans1;
HFMA2 R35, -RZ, RZ, 0, 2.384185791015625e-07 ?WAIT2_END_GROUP;
FADD R31, R31, -R32 &req={2} ?WAIT4_END_GROUP;
FFMA R29, R30, R31, R29 &req={3} ?trans1;
FADD R33, R33, -R34 &req={4} ?WAIT4_END_GROUP;
FFMA R31, R28, R33, R29 &req={5} ?trans1;
IMAD.WIDE R32, R0, R35, UR18 ?WAIT5_END_GROUP;
STG.E desc[UR10][R32.64], R31 &rd=0x0 ?trans4;
LDG.E R16, desc[UR10][R16.64+0x4] &wr=0x2 ?trans4;
LDG.E R7, desc[UR10][R6.64+-0x8] &wr=0x2 ?trans4;
LDG.E R28, desc[UR10][R4.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R9, desc[UR10][R8.64+-0x4] &wr=0x3 ?trans4;
LDG.E R29, desc[UR10][R10.64+0x4] &wr=0x4 ?trans1;
LDC.64 R4, c[0x0][0x390] &req={1} &wr=0x1 ?trans3;
LDG.E R12, desc[UR10][R12.64+0x8] &wr=0x5 ?trans4;
LDG.E R15, desc[UR10][R14.64+-0xc] &wr=0x5 ?trans4;
LDG.E R30, desc[UR10][R10.64] &wr=0x5 ?trans4;
LDG.E R2, desc[UR10][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R19, desc[UR10][R18.64+-0x10] &wr=0x5 ?trans4;
LDG.E R32, desc[UR10][R10.64+0x8] &req={0} &wr=0x5 ?trans4;
LDG.E R20, desc[UR10][R20.64+0x10] &wr=0x5 ?trans4;
LDG.E R27, desc[UR10][R26.64+-0x14] &wr=0x5 ?trans4;
LDG.E R6, desc[UR10][R10.64+0xc] &wr=0x5 ?trans4;
LDG.E R22, desc[UR10][R22.64+0x14] &wr=0x5 ?trans4;
LDG.E R25, desc[UR10][R24.64+-0x18] &wr=0x5 ?trans4;
LDG.E R13, desc[UR10][R10.64+0x10] &wr=0x5 ?trans4;
LDG.E R17, desc[UR10][R10.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R4, R0, 0x4, R4 &req={1} ?WAIT4_END_GROUP;
FADD R16, R16, -R7 &req={2} ?trans1;
FADD R9, R28, -R9 &req={3} ?WAIT3_END_GROUP;
FMUL R29, R29, R16 &req={4} ?trans1;
FADD R12, R12, -R15 &req={5} ?WAIT3_END_GROUP;
FFMA R9, R30, R9, R29 ?trans1;
FADD R2, R2, -R19 ?WAIT3_END_GROUP;
FFMA R9, R32, R12, R9 ?trans1;
FADD R20, R20, -R27 ?WAIT3_END_GROUP;
FFMA R2, R6, R2, R9 ?trans1;
FADD R22, R22, -R25 ?WAIT3_END_GROUP;
FFMA R2, R13, R20, R2 ?WAIT4_END_GROUP;
FFMA R17, R17, R22, R2 ?WAIT5_END_GROUP;
STG.E desc[UR10][R4.64], R17 ?trans1;
EXIT ?trans5;
BRA 0x9e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: rsgbfd(float const*, float*, float*, int, int, float*)
_Z6rsgbfdPKfPfS1_iiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s8, -6
s_add_i32 s3, s9, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB9_2
v_mul_lo_u32 v2, v1, s8
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s8, v2
v_add_nc_u32_e32 v11, v2, v0
v_add_nc_u32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshl_add_u32 v3, s8, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s8, -3, v[3:4]
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_lshl_add_u32 v7, s8, 2, v5
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, s8, -5, v[7:8]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x3
global_load_b32 v28, v[15:16], off offset:-4
global_load_b32 v29, v[0:1], off
global_load_b32 v30, v[2:3], off offset:-8
global_load_b32 v31, v[4:5], off offset:4
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[13:14], null, s8, 6, v[9:10]
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[17:18], null, s8, -7, v[13:14]
v_lshlrev_b64 v[18:19], 2, v[7:8]
v_lshlrev_b64 v[8:9], 2, v[9:10]
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_u32 v22, vcc_lo, s4, v18
v_lshl_add_u32 v6, s8, 3, v17
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v23, vcc_lo, s5, v19, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v13
s_delay_alu instid0(VALU_DEP_4)
v_mad_u64_u32 v[20:21], null, s8, -9, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[24:25], null, s8, 10, v[20:21]
v_lshlrev_b64 v[19:20], 2, v[20:21]
v_ashrrev_i32_e32 v25, 31, v24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[26:27], null, s8, -11, v[24:25]
v_lshlrev_b64 v[24:25], 2, v[24:25]
s_clause 0x5
global_load_b32 v10, v[22:23], off offset:-12
global_load_b32 v21, v[8:9], off offset:8
global_load_b32 v32, v[13:14], off offset:-16
global_load_b32 v33, v[17:18], off offset:12
global_load_b32 v34, v[6:7], off offset:-20
global_load_b32 v35, v[19:20], off offset:16
v_ashrrev_i32_e32 v27, 31, v26
v_add_co_u32 v24, vcc_lo, s4, v24
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[26:27], 2, v[26:27]
v_add_co_u32 v26, vcc_lo, s4, v26
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v27, vcc_lo, s5, v27, vcc_lo
s_clause 0x1
global_load_b32 v36, v[24:25], off offset:-24
global_load_b32 v37, v[26:27], off offset:20
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt vmcnt(10)
v_sub_f32_e32 v28, v28, v29
s_waitcnt vmcnt(8)
v_sub_f32_e32 v30, v30, v31
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v30, s9, v30
v_fmac_f32_e32 v30, s8, v28
v_add_co_u32 v28, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v29, vcc_lo, s7, v12, vcc_lo
s_waitcnt vmcnt(6)
v_sub_f32_e32 v10, v10, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v30, s10, v10
s_waitcnt vmcnt(4)
v_sub_f32_e32 v10, v32, v33
v_fmac_f32_e32 v30, s11, v10
s_waitcnt vmcnt(2)
v_sub_f32_e32 v10, v34, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v30, s4, v10
s_waitcnt vmcnt(0)
v_sub_f32_e32 v10, v36, v37
v_fmac_f32_e32 v30, s5, v10
v_mov_b32_e32 v10, 0
global_store_b32 v[28:29], v30, off
s_clause 0x3
global_load_b32 v21, v[2:3], off offset:4
global_load_b32 v28, v[4:5], off offset:-8
global_load_b32 v15, v[15:16], off
global_load_b32 v16, v[0:1], off offset:-4
global_load_b128 v[0:3], v10, s[0:1]
s_clause 0x7
global_load_b32 v22, v[22:23], off offset:8
global_load_b32 v8, v[8:9], off offset:-12
global_load_b32 v9, v[13:14], off offset:12
global_load_b32 v13, v[17:18], off offset:-16
global_load_b32 v6, v[6:7], off offset:16
global_load_b32 v7, v[19:20], off offset:-20
global_load_b32 v14, v[24:25], off offset:20
global_load_b32 v17, v[26:27], off offset:-24
global_load_b64 v[4:5], v10, s[0:1] offset:16
s_waitcnt vmcnt(12)
v_sub_f32_e32 v10, v21, v28
s_waitcnt vmcnt(9)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_sub_f32 v15, v15, v16 :: v_dual_mul_f32 v10, v1, v10
s_waitcnt vmcnt(7)
v_dual_sub_f32 v1, v22, v8 :: v_dual_fmac_f32 v10, v0, v15
s_waitcnt vmcnt(5)
v_sub_f32_e32 v0, v9, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v2, v1
s_waitcnt vmcnt(3)
v_dual_sub_f32 v1, v6, v7 :: v_dual_fmac_f32 v10, v3, v0
s_waitcnt vmcnt(1)
v_sub_f32_e32 v0, v14, v17
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v4, v1
v_fmac_f32_e32 v10, v5, v0
v_add_co_u32 v0, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v12, vcc_lo
global_store_b32 v[0:1], v10, off
.LBB9_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| rsgbfd | 4,016 | 4,183 | stackv2-00000-of-00015 |
// Demangled: rsgffd(float const*, float*, float*, int, int, float*)
Function : _Z6rsgffdPKfPfS1_iiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x398] &wr=0x3 ?trans1;
S2R R21, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR13, SR_CTAID.X &wr=0x1 ?trans8;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x6, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR12, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R2, R2, UR13, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR4, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR9, -0x6, URZ ?trans1;
IMAD R0, R0, UR12, R21 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R2, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R0, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R0, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R0, c[0x0][0x364] &wr=0x0 ?trans1;
LDCU.128 UR16, c[0x0][0x380] &wr=0x1 ?trans1;
HFMA2 R2, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
MOV R4, 0x4 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR8 ?trans2;
UMOV UR4, UR8 ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x2 ?trans1;
LDC R20, c[0x0][0x360] &wr=0x3 ?trans1;
MOV R19, UR8 ?trans1;
MOV R23, 0x4 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR4, URZ ?WAIT5_END_GROUP;
LDC.64 R8, c[0x0][0x3a0] &wr=0x2 ?trans1;
HFMA2 R16, -RZ, RZ, 0, 2.384185791015625e-07 ?trans1;
MOV R11, UR6 ?trans1;
MOV R5, UR6 ?trans1;
IMAD R21, R0, UR12, R21 &req={0} ?trans1;
MOV R0, UR7 ?trans1;
IMAD R20, R20, UR13, R3 &req={3} ?WAIT3_END_GROUP;
IADD3 R3, PT, PT, R21.reuse, 0x1, RZ ?trans2;
IADD3 R7, PT, PT, R21, -0x2, RZ ?trans1;
LDG.E R25, desc[UR10][R8.64+0x4] &req={2} &wr=0x2 ?trans2;
IMAD R3, R3, UR8, R20.reuse ?trans2;
LDG.E R24, desc[UR10][R8.64+0x8] &wr=0x3 ?trans2;
IMAD.WIDE R2, R3, R2, UR16 &req={1} ?trans2;
LDG.E R26, desc[UR10][R8.64+0xc] &wr=0x4 ?trans1;
LEA R10, P0, R11, R2, 0x2 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR6, URZ ?trans1;
IMAD R12, R7, UR8, R20 ?trans1;
IADD3 R13, PT, PT, R21, -0x3, RZ ?WAIT2_END_GROUP;
LEA.HI.X R11, R5, R3, R0, 0x2, P0 ?trans1;
LDG.E R32, desc[UR10][R2.64] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R21.reuse, -0x1, RZ ?trans1;
IMAD R0, R21, UR8, R20 ?trans2;
IMAD.WIDE R18, R19, 0x4, R2 ?trans1;
MOV R27, UR6 ?trans1;
MOV R22, UR7 ?trans1;
LDG.E R29, desc[UR10][R10.64+-0x8] &wr=0x2 ?trans1;
IMAD R5, R5, UR8, R20 ?trans2;
IMAD.WIDE R6, R0, R15, UR16 ?trans1;
MOV R15, UR6 ?trans1;
LDG.E R31, desc[UR10][R18.64+-0x4] &wr=0x2 ?trans2;
IMAD.WIDE R4, R5, R4, UR16 ?WAIT2_END_GROUP;
LEA R14, P0, R15, R2, 0x2 ?trans1;
LDG.E R33, desc[UR10][R6.64+0x4] &wr=0x5 ?trans1;
IMAD R17, R13, UR8, R20 ?WAIT3_END_GROUP;
LDG.E R30, desc[UR10][R4.64+0x8] &wr=0x2 ?trans1;
IMAD.WIDE R12, R12, R23, UR16 ?trans1;
LEA.HI.X R15, R27, R3, R22, 0x2, P0 ?trans2;
LDG.E R27, desc[UR10][R8.64] &wr=0x3 ?trans1;
IMAD.WIDE R16, R17, R16, UR16 ?WAIT3_END_GROUP;
LDG.E R28, desc[UR10][R12.64+0xc] &wr=0x3 ?trans4;
LDG.E R22, desc[UR10][R16.64+0x10] &wr=0x4 ?trans4;
LDG.E R23, desc[UR10][R14.64+-0xc] &wr=0x4 ?trans1;
UIADD3.64 UR6, UPT, UPT, UR4, UR6, URZ ?WAIT4_END_GROUP;
UIADD3.64 UR4, UPT, UPT, UR4, UR6, URZ ?trans1;
HFMA2 R34, -RZ, RZ, 0, 2.384185791015625e-07 ?trans2;
FADD R32, R32, -R33 &req={5} ?trans1;
FADD R30, R31, -R30 &req={2} ?trans1;
IADD3 R31, PT, PT, R21, -0x4, RZ ?WAIT3_END_GROUP;
FMUL R30, R25, R30 ?trans1;
FADD R29, R29, -R28 &req={3} ?WAIT3_END_GROUP;
FFMA R25, R27, R32, R30 ?trans1;
IADD3 R33, PT, PT, R21, -0x5, RZ ?trans1;
IMAD R21, R31, UR8, R20 ?trans2;
FADD R28, R23, -R22 &req={4} ?trans1;
MOV R23, UR6 ?trans1;
FFMA R29, R24, R29, R25 ?trans1;
MOV R22, 0x4 ?trans1;
MOV R30, UR6 ?trans1;
MOV R31, UR4 ?trans1;
MOV R25, UR7 ?trans1;
LEA R24, P0, R23, R2.reuse, 0x2 ?trans1;
IMAD R27, R33, UR8, R20 ?trans1;
MOV R33, UR4 ?trans1;
MOV R32, UR5 ?trans1;
LEA R20, P1, R31, R2, 0x2 ?trans1;
IMAD.WIDE R22, R21, R22, UR16 ?trans1;
LEA.HI.X R25, R30, R3, R25, 0x2, P0 ?WAIT3_END_GROUP;
FFMA R29, R26, R28, R29 ?trans1;
LEA.HI.X R21, R33, R3, R32, 0x2, P1 ?trans1;
IMAD.WIDE R26, R27, R34, UR16 ?trans1;
LDG.E R32, desc[UR10][R22.64+0x14] &wr=0x2 ?trans4;
LDG.E R31, desc[UR10][R24.64+-0x10] &wr=0x2 ?trans4;
LDG.E R30, desc[UR10][R8.64+0x10] &wr=0x3 ?trans4;
LDG.E R34, desc[UR10][R26.64+0x18] &wr=0x4 ?trans4;
LDG.E R33, desc[UR10][R20.64+-0x14] &wr=0x4 ?trans4;
LDG.E R28, desc[UR10][R8.64+0x14] &wr=0x5 ?trans1;
MOV R35, 0x4 ?trans1;
FADD R31, R31, -R32 &req={2} ?WAIT4_END_GROUP;
FFMA R29, R30, R31, R29 &req={3} ?trans1;
FADD R33, R33, -R34 &req={4} ?WAIT4_END_GROUP;
FFMA R31, R28, R33, R29 &req={5} ?trans1;
IMAD.WIDE R32, R0, R35, UR18 ?WAIT5_END_GROUP;
STG.E desc[UR10][R32.64], R31 &rd=0x0 ?trans4;
LDG.E R18, desc[UR10][R18.64+0x8] &wr=0x2 ?trans4;
LDG.E R5, desc[UR10][R4.64+-0x4] &wr=0x2 ?trans4;
LDG.E R28, desc[UR10][R2.64+0x4] &rd=0x1 &wr=0x3 ?trans4;
LDG.E R7, desc[UR10][R6.64] &wr=0x3 ?trans4;
LDG.E R29, desc[UR10][R8.64+0x4] &wr=0x4 ?trans1;
LDC.64 R2, c[0x0][0x390] &req={1} &wr=0x1 ?trans3;
LDG.E R10, desc[UR10][R10.64+0xc] &wr=0x5 ?trans4;
LDG.E R13, desc[UR10][R12.64+-0x8] &wr=0x5 ?trans4;
LDG.E R30, desc[UR10][R8.64] &wr=0x5 ?trans4;
LDG.E R14, desc[UR10][R14.64+0x10] &wr=0x5 ?trans4;
LDG.E R17, desc[UR10][R16.64+-0xc] &wr=0x5 ?trans4;
LDG.E R32, desc[UR10][R8.64+0x8] &req={0} &wr=0x5 ?trans4;
LDG.E R24, desc[UR10][R24.64+0x14] &wr=0x5 ?trans4;
LDG.E R23, desc[UR10][R22.64+-0x10] &wr=0x5 ?trans4;
LDG.E R4, desc[UR10][R8.64+0xc] &wr=0x5 ?trans4;
LDG.E R20, desc[UR10][R20.64+0x18] &wr=0x5 ?trans4;
LDG.E R27, desc[UR10][R26.64+-0x14] &wr=0x5 ?trans4;
LDG.E R11, desc[UR10][R8.64+0x10] &wr=0x5 ?trans4;
LDG.E R19, desc[UR10][R8.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
FADD R18, R18, -R5 &req={2} ?trans1;
FADD R7, R28, -R7 &req={3} ?WAIT3_END_GROUP;
FMUL R29, R29, R18 &req={4} ?trans1;
FADD R10, R10, -R13 &req={5} ?WAIT3_END_GROUP;
FFMA R7, R30, R7, R29 ?trans1;
FADD R14, R14, -R17 ?WAIT3_END_GROUP;
FFMA R7, R32, R10, R7 ?trans1;
FADD R23, R24, -R23 ?WAIT3_END_GROUP;
FFMA R4, R4, R14, R7 ?trans1;
FADD R20, R20, -R27 ?WAIT3_END_GROUP;
FFMA R4, R11, R23, R4 ?WAIT4_END_GROUP;
FFMA R19, R19, R20, R4 ?WAIT5_END_GROUP;
STG.E desc[UR10][R2.64], R19 ?trans1;
EXIT ?trans5;
BRA 0x920;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: rsgffd(float const*, float*, float*, int, int, float*)
_Z6rsgffdPKfPfS1_iiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s8, -6
s_add_i32 s3, s9, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB8_2
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s8, 1, v2
v_add_nc_u32_e32 v10, s8, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[14:15], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s8, -3, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[10:11]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v16, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v15, vcc_lo
v_lshl_add_u32 v6, s8, 2, v4
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_mad_u64_u32 v[8:9], null, s8, -5, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x3
global_load_b32 v26, v[2:3], off
global_load_b32 v27, v[16:17], off offset:4
global_load_b32 v28, v[0:1], off offset:-4
global_load_b32 v29, v[4:5], off offset:8
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, s8, 6, v[8:9]
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, s8, -7, v[12:13]
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshl_add_u32 v18, s8, 3, v10
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[20:21], null, s8, -9, v[18:19]
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, s4, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
v_mad_u64_u32 v[22:23], null, s8, 10, v[20:21]
v_lshlrev_b64 v[20:21], 2, v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v23, 31, v22
v_add_co_u32 v20, vcc_lo, s4, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v21, vcc_lo, s5, v21, vcc_lo
v_mad_u64_u32 v[24:25], null, s8, -11, v[22:23]
v_lshlrev_b64 v[22:23], 2, v[22:23]
s_clause 0x5
global_load_b32 v30, v[6:7], off offset:-8
global_load_b32 v31, v[8:9], off offset:12
global_load_b32 v32, v[12:13], off offset:-12
global_load_b32 v33, v[10:11], off offset:16
global_load_b32 v34, v[18:19], off offset:-16
global_load_b32 v35, v[20:21], off offset:20
v_ashrrev_i32_e32 v25, 31, v24
v_add_co_u32 v22, vcc_lo, s4, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s5, v23, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[24:25], 2, v[24:25]
v_add_co_u32 v24, vcc_lo, s4, v24
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v25, vcc_lo
s_clause 0x1
global_load_b32 v36, v[22:23], off offset:-20
global_load_b32 v37, v[24:25], off offset:24
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt vmcnt(10)
v_sub_f32_e32 v26, v26, v27
s_waitcnt vmcnt(8)
v_sub_f32_e32 v28, v28, v29
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v28, s9, v28
v_fmac_f32_e32 v28, s8, v26
s_waitcnt vmcnt(6)
v_sub_f32_e32 v26, v30, v31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v28, s10, v26
s_waitcnt vmcnt(4)
v_sub_f32_e32 v26, v32, v33
v_fmac_f32_e32 v28, s11, v26
s_waitcnt vmcnt(2)
v_sub_f32_e32 v26, v34, v35
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v28, s4, v26
v_add_co_u32 v26, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v15, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v29, v36, v37
v_dual_fmac_f32 v28, s5, v29 :: v_dual_mov_b32 v29, 0
global_store_b32 v[26:27], v28, off
s_clause 0x3
global_load_b32 v26, v[0:1], off offset:8
global_load_b32 v27, v[4:5], off offset:-4
global_load_b32 v28, v[2:3], off offset:4
global_load_b32 v16, v[16:17], off
global_load_b128 v[0:3], v29, s[0:1]
s_clause 0x7
global_load_b32 v6, v[6:7], off offset:12
global_load_b32 v7, v[8:9], off offset:-8
global_load_b32 v8, v[12:13], off offset:16
global_load_b32 v9, v[10:11], off offset:-12
global_load_b32 v10, v[18:19], off offset:20
global_load_b32 v11, v[20:21], off offset:-16
global_load_b32 v12, v[22:23], off offset:24
global_load_b32 v13, v[24:25], off offset:-20
global_load_b64 v[4:5], v29, s[0:1] offset:16
s_waitcnt vmcnt(10)
v_dual_sub_f32 v17, v26, v27 :: v_dual_sub_f32 v16, v28, v16
s_waitcnt vmcnt(9)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v17, v1, v17
s_waitcnt vmcnt(7)
v_sub_f32_e32 v1, v6, v7
v_fmac_f32_e32 v17, v0, v16
s_waitcnt vmcnt(5)
v_sub_f32_e32 v0, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, v2, v1
s_waitcnt vmcnt(3)
v_sub_f32_e32 v1, v10, v11
s_waitcnt vmcnt(1)
v_dual_fmac_f32 v17, v3, v0 :: v_dual_sub_f32 v0, v12, v13
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v4, v1
v_fmac_f32_e32 v17, v5, v0
v_add_co_u32 v0, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v15, vcc_lo
global_store_b32 v[0:1], v17, off
.LBB8_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| rsgffd | 3,800 | 4,236 | stackv2-00000-of-00015 |
// Demangled: sbLx(float const*, float*, int, int, float*)
Function : _Z4sbLxPKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R5, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R14, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R9, R9, UR5, R0 &req={1} ?trans1;
IADD3 R0, PT, PT, R14, -0x6, RZ &req={3} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, R0, PT ?trans1;
IADD3 R0, PT, PT, R15, -0x6, RZ ?trans1;
IMAD R5, R5, UR4, R2 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R9, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R5, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R5, R0, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R5.reuse, -0x1, RZ ?trans2;
IADD3 R4, PT, PT, R5.reuse, 0x1, RZ ?trans2;
IADD3 R8, PT, PT, R5.reuse, -0x2, RZ ?trans2;
IADD3 R10, PT, PT, R5.reuse, -0x3, RZ ?trans2;
IADD3 R12, PT, PT, R5.reuse, -0x4, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R15, PT, PT, R5.reuse, -0x5, RZ ?trans1;
IMAD R0, R5, R14, R9 ?WAIT2_END_GROUP;
IMAD R13, R6, R14.reuse, R9.reuse ?trans2;
IMAD R11, R4, R14.reuse, R9.reuse ?trans2;
IMAD R27, R8, R14.reuse, R9.reuse ?trans2;
IMAD R33, R10, R14.reuse, R9.reuse ?trans2;
IMAD R5, R12, R14.reuse, R9.reuse ?trans2;
IMAD R9, R15, R14, R9 ?trans1;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ?trans1;
IMAD.WIDE R10, R11, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IADD.64 R16, R14, R14 ?trans2;
IMAD.WIDE R6, R0, 0x4, R2.reuse ?trans2;
IADD.64 R28, R14, R16 ?trans2;
IMAD.WIDE R12, R13, 0x4, R2 ?trans1;
LEA R18, P0, R16, R10.reuse, 0x2 ?trans1;
LDG.E R20, desc[UR4][R6.64] &req={1} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE R30, R14, 0x4, R10 ?trans1;
LEA R8, P1, R28, R10, 0x2 ?trans1;
LDG.E R21, desc[UR4][R12.64] &rd=0x1 &wr=0x3 ?trans2;
IMAD.WIDE R26, R27, 0x4, R2 ?trans1;
LEA.HI.X R19, R16, R11, R17, 0x2, P0 ?trans1;
LDG.E R24, desc[UR4][R30.64] &wr=0x3 ?trans1;
LDC.64 R6, c[0x0][0x398] &req={0} &wr=0x0 ?trans1;
IMAD.WIDE R32, R33, 0x4, R2 ?trans1;
IADD.64 R16, R14, R28 ?WAIT2_END_GROUP;
LDG.E R22, desc[UR4][R26.64] &wr=0x4 ?trans1;
IMAD.WIDE R4, R5, 0x4, R2 ?WAIT3_END_GROUP;
LDG.E R25, desc[UR4][R6.64] &req={0} &wr=0x5 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 ?trans1;
LEA.HI.X R9, R28, R11, R29, 0x2, P1 ?trans2;
LDG.E R29, desc[UR4][R10.64] &wr=0x2 ?trans1;
LEA R12, P0, R16, R10, 0x2 &req={1} ?trans1;
IADD.64 R14, R14, R16 ?trans2;
LDG.E R26, desc[UR4][R6.64+0x4] &wr=0x4 ?trans1;
LEA.HI.X R13, R16, R11, R17, 0x2, P0 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR4][R18.64] &wr=0x5 ?trans1;
LEA R16, P0, R14, R10, 0x2 ?WAIT3_END_GROUP;
LDG.E R23, desc[UR4][R32.64] &wr=0x5 ?trans1;
LEA.HI.X R17, R14, R11, R15, 0x2, P0 ?WAIT3_END_GROUP;
LDG.E R27, desc[UR4][R6.64+0x8] &wr=0x5 ?trans4;
LDG.E R28, desc[UR4][R8.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R4, desc[UR4][R4.64] &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R6.64+0xc] &wr=0x5 ?trans1;
LDC.64 R8, c[0x0][0x388] &req={0} &wr=0x0 ?trans3;
LDG.E R13, desc[UR4][R12.64] &wr=0x5 ?trans4;
LDG.E R3, desc[UR4][R2.64] &wr=0x5 ?trans4;
LDG.E R11, desc[UR4][R6.64+0x10] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R16.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R6.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R8, R0, 0x4, R8 &req={0} ?WAIT4_END_GROUP;
FADD R21, R24, -R21 &req={3} ?trans1;
FADD R20, R29, -R20 &req={2} ?WAIT3_END_GROUP;
FMUL R26, R26, R21 &req={4} ?WAIT4_END_GROUP;
FFMA R20, R25, R20, R26 &req={5} ?trans1;
FADD R19, R19, -R22 ?WAIT4_END_GROUP;
FFMA R19, R27, R19, R20 ?trans1;
FADD R23, R28, -R23 ?WAIT4_END_GROUP;
FFMA R10, R10, R23, R19 ?trans1;
FADD R4, R13, -R4 ?WAIT4_END_GROUP;
FFMA R4, R11, R4, R10 ?trans1;
FADD R3, R16, R3 ?WAIT4_END_GROUP;
FFMA R3, R15, R3, R4 ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 ?trans1;
EXIT ?trans5;
BRA 0x580;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sbLx(float const*, float*, int, int, float*)
_Z4sbLxPKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s8, -6
s_add_i32 s3, s9, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB4_2
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshl_add_u32 v0, s8, 1, v2
v_add_nc_u32_e32 v10, s8, v2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s8, -3, v[0:1]
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v6, s8, 2, v4
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_mad_u64_u32 v[8:9], null, s8, -5, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_mad_u64_u32 v[12:13], null, s8, 6, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_mad_u64_u32 v[14:15], null, s8, -7, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshl_add_u32 v17, s8, 3, v14
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[19:20], null, s8, -9, v[17:18]
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x3
global_load_b32 v21, v[10:11], off
global_load_b32 v22, v[15:16], off
global_load_b32 v23, v[0:1], off
global_load_b32 v24, v[4:5], off
v_lshlrev_b64 v[4:5], 2, v[8:9]
v_add_co_u32 v0, vcc_lo, s4, v6
v_ashrrev_i32_e32 v20, 31, v19
v_ashrrev_i32_e32 v15, 31, v14
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_4)
v_mad_u64_u32 v[8:9], null, s8, 10, v[19:20]
v_add_co_u32 v4, vcc_lo, s4, v4
v_lshlrev_b64 v[10:11], 2, v[14:15]
v_lshlrev_b64 v[12:13], 2, v[17:18]
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[16:17], null, s8, -11, v[8:9]
v_add_co_u32 v10, vcc_lo, s4, v10
v_lshlrev_b64 v[14:15], 2, v[19:20]
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v12
v_ashrrev_i32_e32 v17, 31, v16
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
s_clause 0x5
global_load_b32 v18, v[0:1], off
global_load_b32 v19, v[4:5], off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
global_load_b32 v11, v[14:15], off
v_lshlrev_b64 v[0:1], 2, v[16:17]
v_add_co_u32 v4, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v0, v[0:1], off
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(8)
v_sub_f32_e32 v1, v23, v24
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v21, v22 :: v_dual_mul_f32 v8, s9, v1
s_waitcnt vmcnt(6)
v_dual_fmac_f32 v8, s8, v5 :: v_dual_sub_f32 v1, v18, v19
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v8, s10, v1 :: v_dual_sub_f32 v1, v6, v7
s_waitcnt vmcnt(2)
v_dual_fmac_f32 v8, s11, v1 :: v_dual_sub_f32 v1, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, s0, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v4, v0
v_fmac_f32_e32 v8, s1, v0
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sbLx | 2,340 | 3,111 | stackv2-00000-of-00015 |
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