sass stringlengths 231 30.8k | rdna stringlengths 69 28.4k | function_name stringlengths 1 85 | sass_tokens int64 90 14.4k ⌀ | rdna_tokens int64 11 14.5k ⌀ | source stringclasses 15 values |
|---|---|---|---|---|---|
// Demangled: sbLz(float const*, float*, int, int, float*)
Function : _Z4sbLzPKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
LDC R7, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x6, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R0, R0, UR6, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR4, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR9, -0x6, URZ ?trans1;
IMAD R7, R7, UR5, R2 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R0, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R7, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R7, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R7, R7, UR8, R0 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x398] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
LDG.E R10, desc[UR4][R4.64+0x4] &req={1} &wr=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R7, 0x4, R8 &req={0} ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x8] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x4] &wr=0x3 ?trans4;
LDG.E R6, desc[UR4][R8.64+0x4] &wr=0x4 ?trans4;
LDG.E R11, desc[UR4][R8.64] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R8.64+0xc] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0x8] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R8.64+0x10] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R8.64+-0xc] &wr=0x5 ?trans4;
LDG.E R18, desc[UR4][R8.64+0x14] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R8.64+-0x10] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R20, desc[UR4][R8.64+0x18] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R8.64+-0x14] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R27, desc[UR4][R4.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
FADD R13, R12, -R13 &req={3} ?WAIT4_END_GROUP;
FMUL R13, R10, R13 ?trans1;
FADD R11, R6, -R11 &req={4} ?WAIT4_END_GROUP;
FFMA R0, R0, R11, R13 ?trans1;
FADD R14, R14, -R17 &req={5} ?WAIT4_END_GROUP;
FFMA R0, R15, R14, R0 ?trans1;
FADD R16, R16, -R21 ?trans1;
FADD R18, R18, -R25 ?WAIT3_END_GROUP;
FFMA R0, R19, R16, R0 ?trans1;
FADD R20, R20, R29 ?WAIT3_END_GROUP;
FFMA R0, R23, R18, R0 ?WAIT4_END_GROUP;
FFMA R27, R27, R20, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 ?trans1;
EXIT ?trans5;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sbLz(float const*, float*, int, int, float*)
_Z4sbLzPKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s6, -6
s_add_i32 s3, s7, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB6_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[12:13], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v13, vcc_lo
s_clause 0x2
global_load_b128 v[0:3], v[8:9], off offset:-4
global_load_b128 v[4:7], v[8:9], off offset:-20
global_load_b128 v[8:11], v[8:9], off offset:12
s_clause 0x1
s_load_b128 s[0:3], s[4:5], 0x0
s_load_b64 s[4:5], s[4:5], 0x10
s_waitcnt vmcnt(2)
v_dual_sub_f32 v0, v3, v0 :: v_dual_sub_f32 v1, v2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, s1, v0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v8, v7
v_dual_fmac_f32 v2, s0, v1 :: v_dual_sub_f32 v1, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s2, v0
v_sub_f32_e32 v0, v10, v5
v_dual_fmac_f32 v2, s3, v1 :: v_dual_add_f32 v1, v11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s4, v0
v_add_co_u32 v0, vcc_lo, s10, v12
v_fmac_f32_e32 v2, s5, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v13, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB6_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sbLz | 1,539 | 1,317 | stackv2-00000-of-00015 |
// Demangled: sfLx(float const*, float*, int, int, float*)
Function : _Z4sfLxPKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R23, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans8;
LDC R25, c[0x0][0x360] &wr=0x1 ?trans8;
LDC.64 R16, c[0x0][0x390] &wr=0x3 ?trans8;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R25, R25, UR5, R0 &req={1} ?trans1;
IADD3 R0, PT, PT, R16, -0x6, RZ &req={3} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R25, R0, PT ?trans1;
IADD3 R0, PT, PT, R17, -0x6, RZ ?trans1;
IMAD R23, R23, UR4, R2 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R25, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R23, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R23, R0, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IMAD R0, R23.reuse, R16.reuse, -R16.reuse ?trans1;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
SHF.R.S32.HI R17, RZ, 0x1f, R16.reuse ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R23, R23, R16.reuse, R25 ?trans1;
IADD3 R3, PT, PT, R0, R16, R16 ?trans2;
IADD3 R11, PT, PT, R25, R0, RZ ?WAIT3_END_GROUP;
IMAD R6, R16, -0x3, R3 ?WAIT5_END_GROUP;
LEA R3, R16, R6.reuse, 0x2 ?trans2;
IADD3 R27, PT, PT, R25, R6, RZ ?WAIT3_END_GROUP;
IMAD R15, R16, -0x5, R3 ?WAIT4_END_GROUP;
IMAD R3, R16, 0x6, R15 ?trans1;
IADD3 R15, PT, PT, R25, R15, RZ ?trans1;
IMAD.WIDE R18, R23, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
IMAD R31, R16, -0x7, R3 ?trans1;
LDG.E R33, desc[UR4][R18.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R26, R27, 0x4, R4 ?WAIT3_END_GROUP;
LEA R3, R16.reuse, R31.reuse, 0x3 ?trans1;
IMAD.WIDE R34, R16.reuse, 0x4, R18 ?trans1;
IADD3 R31, PT, PT, R25, R31, RZ ?trans1;
LDG.E R27, desc[UR4][R26.64] &wr=0x3 ?trans2;
IMAD R29, R16.reuse, -0x9, R3 ?trans1;
IADD.64 R2, R16, R16 ?trans2;
IMAD.WIDE R10, R11, 0x4, R4 ?trans1;
LDG.E R22, desc[UR4][R34.64] &wr=0x3 ?trans1;
IADD.64 R12, R16, R2 ?WAIT2_END_GROUP;
IMAD R7, R16, 0xa, R29 ?trans1;
LEA R20, P0, R2, R18.reuse, 0x2 ?trans2;
LEA R8, P1, R12, R18, 0x2 ?trans1;
IMAD R0, R16, -0xb, R7 ?trans1;
LEA.HI.X R21, R2, R19.reuse, R3, 0x2, P0 ?trans2;
LEA.HI.X R9, R12, R19, R13, 0x2, P1 ?trans1;
IADD.64 R12, R16.reuse, R12 ?trans2;
LDC.64 R2, c[0x0][0x398] &wr=0x0 ?trans2;
IADD.64 R16, R16, R12 ?WAIT3_END_GROUP;
IADD3 R29, PT, PT, R25, R29, RZ ?trans2;
LEA R6, P0, R12.reuse, R18, 0x2 ?trans1;
IMAD.WIDE R14, R15, 0x4, R4 ?trans1;
IADD3 R25, PT, PT, R25, R0, RZ ?trans1;
LDG.E R24, desc[UR4][R2.64+0x4] &req={0} &wr=0x4 ?trans1;
LEA.HI.X R7, R12, R19, R13, 0x2, P0 ?trans1;
IMAD.WIDE R12, R31, 0x4, R4 ?trans2;
LDG.E R0, desc[UR4][R10.64] &rd=0x0 &wr=0x2 ?trans4;
LDG.E R20, desc[UR4][R20.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR4][R14.64] &wr=0x5 ?trans1;
LEA R10, P1, R16, R18, 0x2 &req={0} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR4][R2.64] &wr=0x5 ?trans1;
LEA.HI.X R11, R16, R19, R17, 0x2, P1 ?trans1;
IMAD.WIDE R16, R29, 0x4, R4.reuse ?trans2;
LDG.E R8, desc[UR4][R8.64] &wr=0x5 ?trans4;
LDG.E R18, desc[UR4][R2.64+0x8] &wr=0x5 ?trans1;
IMAD.WIDE R28, R25, 0x4, R4 ?trans2;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDG.E R13, desc[UR4][R12.64] &wr=0x5 ?trans4;
LDG.E R6, desc[UR4][R6.64] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R16.64] &wr=0x5 ?trans4;
LDG.E R30, desc[UR4][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R10, desc[UR4][R10.64] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R2.64+0x10] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R28.64] &wr=0x5 ?trans4;
LDG.E R9, desc[UR4][R2.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R4, R23, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
FADD R27, R22, -R27 &req={3} ?WAIT4_END_GROUP;
FMUL R27, R24, R27 &req={4} ?trans1;
FADD R33, R33, -R0 &req={2} ?trans1;
FADD R15, R20, -R15 &req={5} ?WAIT3_END_GROUP;
FFMA R27, R26, R33, R27 ?WAIT4_END_GROUP;
FFMA R15, R18, R15, R27 ?trans1;
FADD R8, R8, -R13 ?trans1;
FADD R6, R6, -R17 ?WAIT3_END_GROUP;
FFMA R8, R30, R8, R15 ?WAIT4_END_GROUP;
FFMA R6, R19, R6, R8 ?trans1;
FADD R10, R10, R29 ?WAIT4_END_GROUP;
FFMA R9, R9, R10, R6 ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x5d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sfLx(float const*, float*, int, int, float*)
_Z4sfLxPKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s8, -6
s_add_i32 s3, s9, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB5_2
v_mul_lo_u32 v2, v1, s8
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s8, v2
v_add_nc_u32_e32 v11, v2, v0
v_add_nc_u32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshl_add_u32 v3, s8, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s8, -3, v[3:4]
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_lshl_add_u32 v7, s8, 2, v5
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, s8, -5, v[7:8]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x3
global_load_b32 v22, v[15:16], off
global_load_b32 v23, v[0:1], off
global_load_b32 v24, v[2:3], off
global_load_b32 v25, v[4:5], off
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[13:14], null, s8, 6, v[9:10]
v_lshlrev_b64 v[2:3], 2, v[9:10]
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, s8, -7, v[13:14]
v_lshlrev_b64 v[18:19], 2, v[7:8]
v_lshlrev_b64 v[4:5], 2, v[13:14]
v_add_co_u32 v0, vcc_lo, s4, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshl_add_u32 v6, s8, 3, v17
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v19, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[13:14], 2, v[17:18]
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_mad_u64_u32 v[20:21], null, s8, -9, v[6:7]
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, s8, 10, v[20:21]
v_lshlrev_b64 v[15:16], 2, v[20:21]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[17:18], null, s8, -11, v[8:9]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_clause 0x5
global_load_b32 v10, v[0:1], off
global_load_b32 v19, v[2:3], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[13:14], off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[15:16], off
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_u32 v2, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[17:18]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(0)
v_dual_sub_f32 v1, v24, v25 :: v_dual_add_f32 v0, v2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mul_f32 v8, s9, v1 :: v_dual_sub_f32 v1, v10, v19
v_sub_f32_e32 v3, v22, v23
v_fmac_f32_e32 v8, s8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, s10, v1
v_sub_f32_e32 v1, v4, v5
v_dual_fmac_f32 v8, s11, v1 :: v_dual_sub_f32 v1, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, s0, v1
v_fmac_f32_e32 v8, s1, v0
v_add_co_u32 v0, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v12, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sfLx | 2,429 | 3,246 | stackv2-00000-of-00015 |
// Demangled: sfLz(float const*, float*, int, int, float*)
Function : _Z4sfLzPKfPfiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
LDC R7, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R2, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x6, URZ &req={3} ?WAIT7_END_GROUP;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans1;
IMAD R0, R0, UR6, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR4, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR9, -0x6, URZ ?trans1;
IMAD R7, R7, UR5, R2 &req={2} ?WAIT3_END_GROUP;
ISETP.LT.OR P0, PT, R0, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.LT.U32.OR P0, PT, R7, 0x6, P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R7, UR4, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R7, R7, UR8, R0 ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x398] &wr=0x1 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
LDG.E R10, desc[UR4][R4.64+0x4] &req={1} &wr=0x3 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R8, R7, 0x4, R8 &req={0} ?WAIT3_END_GROUP;
LDG.E R15, desc[UR4][R4.64+0x8] &wr=0x5 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x4] &wr=0x3 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x8] &wr=0x3 ?trans4;
LDG.E R6, desc[UR4][R8.64] &wr=0x4 ?trans4;
LDG.E R11, desc[UR4][R8.64+-0x4] &wr=0x4 ?trans4;
LDG.E R14, desc[UR4][R8.64+0x8] &wr=0x5 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0xc] &wr=0x5 ?trans4;
LDG.E R16, desc[UR4][R8.64+0xc] &wr=0x5 ?trans4;
LDG.E R21, desc[UR4][R8.64+-0x10] &wr=0x5 ?trans4;
LDG.E R18, desc[UR4][R8.64+0x10] &wr=0x5 ?trans4;
LDG.E R25, desc[UR4][R8.64+-0x14] &wr=0x5 ?trans4;
LDG.E R19, desc[UR4][R4.64+0xc] &wr=0x5 ?trans4;
LDG.E R20, desc[UR4][R8.64+0x14] &wr=0x5 ?trans4;
LDG.E R29, desc[UR4][R8.64+-0x18] &wr=0x5 ?trans4;
LDG.E R23, desc[UR4][R4.64+0x10] &wr=0x5 ?trans4;
LDG.E R27, desc[UR4][R4.64+0x14] &wr=0x5 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={2} ?WAIT4_END_GROUP;
FADD R13, R12, -R13 &req={3} ?WAIT4_END_GROUP;
FMUL R13, R10, R13 ?trans1;
FADD R11, R6, -R11 &req={4} ?WAIT4_END_GROUP;
FFMA R0, R0, R11, R13 ?trans1;
FADD R14, R14, -R17 &req={5} ?WAIT4_END_GROUP;
FFMA R0, R15, R14, R0 ?trans1;
FADD R16, R16, -R21 ?trans1;
FADD R18, R18, -R25 ?WAIT3_END_GROUP;
FFMA R0, R19, R16, R0 ?trans1;
FADD R20, R20, R29 ?WAIT3_END_GROUP;
FFMA R0, R23, R18, R0 ?WAIT4_END_GROUP;
FFMA R27, R27, R20, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R27 ?trans1;
EXIT ?trans5;
BRA 0x380;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: sfLz(float const*, float*, int, int, float*)
_Z4sfLzPKfPfiiS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_add_i32 s2, s6, -6
s_add_i32 s3, s7, -6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s4, 5, v0
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 5, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB7_2
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[12:13], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v13, vcc_lo
s_clause 0x2
global_load_b128 v[0:3], v[8:9], off offset:-8
global_load_b128 v[4:7], v[8:9], off offset:-24
global_load_b128 v[8:11], v[8:9], off offset:8
s_clause 0x1
s_load_b128 s[0:3], s[4:5], 0x0
s_load_b64 s[4:5], s[4:5], 0x10
s_waitcnt vmcnt(2)
v_dual_sub_f32 v0, v3, v0 :: v_dual_sub_f32 v1, v2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, s1, v0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v8, v7
v_dual_fmac_f32 v2, s0, v1 :: v_dual_sub_f32 v1, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s2, v0
v_sub_f32_e32 v0, v10, v5
v_dual_fmac_f32 v2, s3, v1 :: v_dual_add_f32 v1, v11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s4, v0
v_add_co_u32 v0, vcc_lo, s10, v12
v_fmac_f32_e32 v2, s5, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v13, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB7_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| sfLz | 1,539 | 1,316 | stackv2-00000-of-00015 |
// Demangled: computeCell(int, char const*, char*)
Function : _Z11computeCelliPKcPc
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x380] &wr=0x2 ?trans1;
S2R R5, SR_TID.Y &wr=0x3 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x4 ?trans5;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR6, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R0, c[0x0][0x364] &wr=0x3 ?trans1;
IMAD R2, R2, UR5, R3 &req={1} ?WAIT2_END_GROUP;
IMAD R3, R0, UR6, R5 &req={3} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans3;
IMAD R2, R3, UR4, R2 &req={2} ?WAIT5_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
IADD.64 R4, R2, UR8 &req={4} ?WAIT6_END_GROUP;
LDG.E.U8 R0, desc[UR6][R4.64] &req={1} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, 0x3, PT &req={2} ?WAIT13_END_GROUP;
@!P0 BRA 0x200 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R0, 0x2, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1b0 ?trans5;
ISETP.NE.AND P0, PT, R0, 0x1, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 1.1920928955078125e-07 ?trans1;
IADD.64 R2, R2, UR10 &req={0} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R0 ?trans1;
EXIT ?trans5;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
MOV R0, 0x3 ?trans1;
IADD.64 R2, R2, UR10 &req={0} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R0 ?trans1;
EXIT ?trans5;
ULOP3.LUT UR5, URZ, UR4, URZ, 0x33, !UPT ?trans2;
IADD3 R8, PT, PT, R2.reuse, -UR4, RZ ?trans2;
IADD3 R10, PT, PT, R2.reuse, -0x1, RZ ?trans2;
IADD3 R12, PT, PT, R2.reuse, UR4, RZ ?trans1;
LDG.E.U8 R4, desc[UR6][R4.64+0x1] &wr=0x2 ?trans1;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R2, UR5, RZ ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?WAIT2_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?WAIT3_END_GROUP;
IADD.64 R8, R8, UR8 ?trans2;
IADD.64 R6, R6, UR8 ?WAIT4_END_GROUP;
LDG.E.U8 R14, desc[UR6][R8.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E.U8 R0, desc[UR6][R6.64] &wr=0x4 ?trans1;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT3_END_GROUP;
LDG.E.U8 R15, desc[UR6][R6.64+0x2] &wr=0x5 ?trans2;
IADD.64 R10, R10, UR8 ?trans2;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?WAIT4_END_GROUP;
LDG.E.U8 R16, desc[UR6][R10.64] &wr=0x2 ?trans2;
IADD.64 R8, R10, UR4 &req={1} ?WAIT3_END_GROUP;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?WAIT3_END_GROUP;
LDG.E.U8 R17, desc[UR6][R8.64] &wr=0x2 ?trans2;
IADD.64 R12, R12, UR8 ?trans2;
LDG.E.U8 R6, desc[UR6][R8.64+0x2] &wr=0x2 ?trans5;
LDG.E.U8 R12, desc[UR6][R12.64] &wr=0x2 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
IADD.64 R2, R2, UR10 &req={0} ?WAIT2_END_GROUP;
ISETP.NE.AND P1, PT, R14, 0x1, PT &req={3} ?trans1;
ISETP.NE.AND P0, PT, R0, 0x1, PT &req={4} ?WAIT4_END_GROUP;
SEL R0, RZ, 0x1, P1 ?WAIT8_END_GROUP;
@P1 IADD3 R5, PT, PT, RZ, -0x1, RZ ?trans2;
@!P0 IADD3 R5, PT, PT, R0, RZ, RZ ?trans1;
ISETP.NE.AND P0, PT, R15, 0x1, PT &req={5} ?trans1;
ISETP.NE.AND P1, PT, R16, 0x1, PT &req={2} ?trans2;
IADD3 R0, PT, PT, R5, 0x1, RZ ?WAIT10_END_GROUP;
@P0 IADD3 R0, PT, PT, R5, RZ, RZ ?trans1;
ISETP.NE.AND P0, PT, R4, 0x1, PT ?WAIT3_END_GROUP;
IADD3 R5, PT, PT, R0.reuse, 0x1, RZ ?trans2;
@P1 IADD3 R5, PT, PT, R0, RZ, RZ ?trans1;
ISETP.NE.AND P1, PT, R17, 0x1, PT ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R5, 0x1, RZ ?WAIT4_END_GROUP;
@P0 IADD3 R0, PT, PT, R5, RZ, RZ ?trans1;
ISETP.NE.AND P0, PT, R12, 0x1, PT ?WAIT3_END_GROUP;
IADD3 R4, PT, PT, R0.reuse, 0x1, RZ ?trans2;
@P1 IADD3 R4, PT, PT, R0, RZ, RZ ?trans1;
ISETP.NE.AND P1, PT, R6, 0x1, PT ?WAIT3_END_GROUP;
IADD3 R5, PT, PT, R4, 0x1, RZ ?WAIT4_END_GROUP;
@P0 IADD3 R5, PT, PT, R4, RZ, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R5.reuse, 0x1, RZ ?trans2;
@P1 IADD3 R0, PT, PT, R5, RZ, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ?trans1;
MOV R5, 0x3 ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P0, PT, R0, 0x1, PT ?WAIT5_END_GROUP;
SEL R5, R5, 0x1, P0 ?WAIT5_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x570;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: computeCell(int, char const*, char*)
_Z11computeCelliPKcPc:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b128 s[0:3], s[0:1], 0x8
s_mul_i32 s14, s14, s4
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s6
v_add3_u32 v2, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_u8 v5, v[0:1], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 1, v5
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_8
s_mov_b32 s7, 0
s_mov_b32 s5, exec_lo
v_cmpx_lt_i16_e32 2, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_5
s_mov_b32 s8, exec_lo
v_cmpx_eq_u16_e32 3, v5
s_cbranch_execz .LBB0_4
v_xad_u32 v4, s6, -1, v2
v_add_nc_u32_e32 v6, -1, v2
v_subrev_nc_u32_e32 v10, s6, v2
s_ashr_i32 s9, s6, 31
v_add_nc_u32_e32 v12, s6, v2
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v4, vcc_lo, s0, v4
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s7, exec_lo
v_add_co_u32 v8, vcc_lo, v6, s6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
s_clause 0x6
global_load_u8 v6, v[6:7], off
global_load_u8 v7, v[8:9], off
global_load_u8 v8, v[8:9], off offset:2
global_load_u8 v9, v[10:11], off
global_load_u8 v10, v[4:5], off offset:2
global_load_u8 v4, v[4:5], off
global_load_u8 v5, v[0:1], off offset:1
v_ashrrev_i32_e32 v11, 31, v12
v_add_co_u32 v0, vcc_lo, s0, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v11, vcc_lo
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(4)
v_cmp_eq_u16_e32 vcc_lo, 1, v9
v_cndmask_b32_e64 v1, 0, 1, vcc_lo
s_waitcnt vmcnt(3)
v_cmp_eq_u16_e32 vcc_lo, 1, v10
v_cndmask_b32_e64 v9, 0, 1, vcc_lo
s_waitcnt vmcnt(2)
v_cmp_ne_u16_e32 vcc_lo, 1, v4
v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cmp_eq_u16_e32 vcc_lo, 1, v5
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v7
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v0, vcc_lo, v1, v0, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 2, v0
v_cndmask_b32_e64 v4, 3, 1, vcc_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s7, s7, exec_lo
.LBB0_5:
s_and_not1_saveexec_b32 s0, s5
v_mov_b32_e32 v4, 3
s_or_b32 s7, s7, exec_lo
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s5, s7, exec_lo
.LBB0_8:
s_and_not1_saveexec_b32 s0, s4
v_cmp_eq_u16_e32 vcc_lo, 1, v5
v_mov_b32_e32 v4, 2
s_and_not1_b32 s1, s5, exec_lo
s_and_b32 s4, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s1, s4
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s5
s_cbranch_execz .LBB0_12
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b8 v[0:1], v4, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| computeCell | 2,261 | 2,063 | stackv2-00000-of-00015 |
// Demangled: add_complex(int*, int*, int*)
Function : _Z11add_complexPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R15, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R15, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R0, 0x7ff, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R12, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R8, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R10, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R15, R15, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IMAD.WIDE R2, R0, 0x4, R8 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R0.reuse, 0x4, R10 &req={4} ?trans2;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR6][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R0, 0x4, R12 &req={1,0} ?trans1;
IADD3 R0, PT, PT, R15, R0, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, 0x800, PT ?trans1;
IADD3 R17, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x1 ?trans7;
@!P0 BRA 0xd0 ?trans5;
EXIT ?trans5;
BRA 0x180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_complex(int*, int*, int*)
_Z11add_complexPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x800, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x7ff, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_complex | 684 | 718 | stackv2-00000-of-00015 |
// Demangled: MV(int*, int*, int*, int, int)
Function : _Z2MVPiS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x39c] &wr=0x2 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR8, c[0x0][0x398] &wr=0x0 ?trans1;
HFMA2 R26, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR32, c[0x0][0x358] &wr=0x1 ?trans1;
UISETP.GE.AND UP0, UPT, UR8, 0x1, UPT &req={0} ?WAIT6_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?WAIT13_END_GROUP;
@!P0 BRA 0x1070 &req={1} ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR8, 0x10, UPT ?trans1;
ULOP3.LUT UR34, UR8, 0xf, URZ, 0xc0, !UPT ?trans1;
UMOV UR4, URZ ?trans1;
MOV R26, RZ ?WAIT3_END_GROUP;
PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P1, PT, RZ, UR34, PT ?WAIT12_END_GROUP;
@!P0 BRA 0x940 ?trans5;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?trans1;
LDCU.64 UR4, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R12, R0 ?trans2;
UIADD3.64 UR10, UPT, UPT, UR6, UR6, URZ ?trans1;
ULOP3.LUT UR9, UR8, 0x7ffffff0, URZ, 0xc0, !UPT ?WAIT3_END_GROUP;
UIADD3.64 UR12, UPT, UPT, UR6, UR10, URZ ?trans1;
USHF.L.U64.HI UR11, UR10, 0x2, UR11 ?trans1;
UIADD3 UR9, UPT, UPT, -UR9, URZ, URZ ?trans1;
USHF.L.U32 UR10, UR10, 0x2, URZ ?trans1;
UIADD3.64 UR14, UPT, UPT, UR6, UR12, URZ ?trans1;
USHF.L.U64.HI UR13, UR12, 0x2, UR13 ?trans1;
USHF.L.U32 UR12, UR12, 0x2, URZ ?trans2;
UIADD3.64 UR16, UPT, UPT, UR6, UR14, URZ ?trans1;
USHF.L.U64.HI UR15, UR14, 0x2, UR15 ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0x20, URZ &req={0} ?trans1;
USHF.L.U32 UR14, UR14, 0x2, URZ ?trans1;
UIADD3.64 UR18, UPT, UPT, UR6, UR16, URZ ?trans1;
USHF.L.U64.HI UR17, UR16, 0x2, UR17 ?trans1;
USHF.L.U32 UR16, UR16, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR20, UPT, UPT, UR6, UR18, URZ ?trans1;
USHF.L.U64.HI UR19, UR18, 0x2, UR19 ?trans1;
MOV.64 R2, UR4 ?trans2;
USHF.L.U32 UR18, UR18, 0x2, URZ ?trans1;
UIADD3.64 UR22, UPT, UPT, UR6, UR20, URZ ?trans1;
USHF.L.U64.HI UR21, UR20, 0x2, UR21 ?trans1;
USHF.L.U32 UR20, UR20, 0x2, URZ ?trans1;
UMOV UR4, URZ ?trans1;
UIADD3.64 UR24, UPT, UPT, UR6, UR22, URZ ?trans1;
USHF.L.U64.HI UR23, UR22, 0x2, UR23 ?trans1;
USHF.L.U32 UR22, UR22, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR26, UPT, UPT, UR6, UR24, URZ ?trans1;
USHF.L.U64.HI UR25, UR24, 0x2, UR25 ?trans1;
USHF.L.U32 UR24, UR24, 0x2, URZ ?trans2;
UIADD3.64 UR28, UPT, UPT, UR6, UR26, URZ ?trans1;
USHF.L.U64.HI UR27, UR26, 0x2, UR27 ?trans1;
USHF.L.U32 UR26, UR26, 0x2, URZ ?trans2;
UIADD3.64 UR30, UPT, UPT, UR6, UR28, URZ ?trans1;
USHF.L.U64.HI UR29, UR28, 0x2, UR29 ?trans1;
USHF.L.U32 UR28, UR28, 0x2, URZ ?WAIT2_END_GROUP;
UIADD3.64 UR36, UPT, UPT, UR6, UR30, URZ ?trans1;
USHF.L.U64.HI UR31, UR30, 0x2, UR31 ?trans1;
USHF.L.U32 UR30, UR30, 0x2, URZ ?trans2;
UIADD3.64 UR38, UPT, UPT, UR6, UR36, URZ ?trans1;
USHF.L.U64.HI UR35, UR36, 0x2, UR37 ?WAIT3_END_GROUP;
UIADD3.64 UR40, UPT, UPT, UR6, UR38, URZ ?trans1;
USHF.L.U64.HI UR39, UR38, 0x2, UR39 ?trans1;
USHF.L.U32 UR7, UR36, 0x2, URZ ?trans1;
USHF.L.U32 UR38, UR38, 0x2, URZ ?trans1;
USHF.L.U64.HI UR41, UR40, 0x2, UR41 ?trans1;
USHF.L.U32 UR40, UR40, 0x2, URZ ?WAIT12_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R31, UR6 ?trans1;
LDG.E R28, desc[UR32][R2.64+-0x20] &wr=0x2 ?trans4;
LDG.E R29, desc[UR32][R2.64+-0x1c] &wr=0x3 ?trans4;
LDG.E R20, desc[UR32][R2.64+-0x18] &wr=0x4 ?trans4;
LDG.E R19, desc[UR32][R2.64+-0x14] &wr=0x5 ?trans4;
LDG.E R21, desc[UR32][R2.64+-0xc] &wr=0x2 ?trans1;
UMOV UR36, UR7 ?trans1;
UMOV UR37, UR35 ?WAIT2_END_GROUP;
LDG.E R35, desc[UR32][R2.64+0x10] &wr=0x2 ?trans1;
IMAD.WIDE R4, R12, 0x4, R4 &req={0} ?WAIT3_END_GROUP;
LDG.E R37, desc[UR32][R2.64+0x14] &wr=0x2 ?trans1;
IMAD.WIDE R30, R31, 0x4, R4 ?WAIT3_END_GROUP;
LDG.E R27, desc[UR32][R4.64] &wr=0x2 ?trans4;
LDG.E R36, desc[UR32][R2.64+0x18] &wr=0x3 ?trans4;
LDG.E R30, desc[UR32][R30.64] &wr=0x3 ?trans1;
IADD.64 R10, R4.reuse, UR10 ?trans2;
IADD.64 R22, R4, UR12 ?WAIT2_END_GROUP;
IADD.64 R24, R4.reuse, UR14 ?trans2;
LDG.E R13, desc[UR32][R10.64] &wr=0x4 ?trans1;
IADD.64 R32, R4, UR16 ?WAIT3_END_GROUP;
LDG.E R14, desc[UR32][R22.64] &wr=0x5 ?trans1;
IADD.64 R8, R4, UR18 ?WAIT3_END_GROUP;
LDG.E R15, desc[UR32][R24.64] &rd=0x0 &wr=0x4 ?trans1;
IADD.64 R6, R4, UR20 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR32][R32.64] &wr=0x4 ?trans4;
LDG.E R22, desc[UR32][R2.64+-0x10] &wr=0x4 ?trans1;
IADD.64 R24, R4, UR22 &req={0} ?WAIT3_END_GROUP;
LDG.E R17, desc[UR32][R8.64] &rd=0x0 &wr=0x4 ?trans1;
IADD.64 R10, R4, UR24 ?WAIT3_END_GROUP;
LDG.E R18, desc[UR32][R6.64] &rd=0x1 &wr=0x4 ?trans4;
LDG.E R24, desc[UR32][R24.64] &wr=0x4 ?trans1;
IADD.64 R8, R4, UR26 &req={0} ?WAIT3_END_GROUP;
LDG.E R23, desc[UR32][R10.64] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R32, desc[UR32][R2.64+0x4] &wr=0x5 ?trans4;
LDG.E R25, desc[UR32][R2.64] &wr=0x5 ?trans1;
IADD.64 R6, R4.reuse, UR28 &req={1} ?trans2;
IADD.64 R10, R4, UR30 &req={0} ?WAIT2_END_GROUP;
LDG.E R33, desc[UR32][R2.64+0xc] &wr=0x5 ?trans4;
LDG.E R34, desc[UR32][R2.64+0x1c] &wr=0x5 ?trans4;
LDG.E R10, desc[UR32][R10.64] &wr=0x5 ?trans1;
IMAD R31, R28, R27, R26 &req={2} ?WAIT3_END_GROUP;
LDG.E R26, desc[UR32][R2.64+-0x8] &wr=0x2 ?trans4;
LDG.E R27, desc[UR32][R8.64] &rd=0x0 &wr=0x2 ?trans1;
IMAD R29, R29, R30, R31 &req={3} ?WAIT3_END_GROUP;
LDG.E R31, desc[UR32][R2.64+-0x4] &wr=0x3 ?trans4;
LDG.E R30, desc[UR32][R2.64+0x8] &wr=0x3 ?trans1;
IADD.64 R8, R4, UR36 &req={0} ?WAIT3_END_GROUP;
LDG.E R28, desc[UR32][R6.64] &rd=0x0 &wr=0x3 ?trans1;
UMOV UR36, UR40 ?trans1;
UMOV UR37, UR41 ?trans2;
LDG.E R8, desc[UR32][R8.64] &wr=0x3 ?trans1;
IADD.64 R6, R4.reuse, UR38 &req={0} ?trans2;
IADD.64 R4, R4, UR36 ?WAIT5_END_GROUP;
LDG.E R6, desc[UR32][R6.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E R5, desc[UR32][R4.64] &wr=0x3 ?trans1;
IMAD R13, R20, R13, R29 &req={4} ?WAIT4_END_GROUP;
IMAD R13, R19, R14, R13 &req={5} ?WAIT4_END_GROUP;
IMAD R13, R22, R15, R13 ?WAIT4_END_GROUP;
IMAD R13, R21, R16, R13 ?trans1;
UIADD3 UR9, UPT, UPT, UR9, 0x10, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, RZ, UR9, PT ?trans1;
MOV R7, UR6 &req={0} ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD.64 R2, R2, 0x40 ?WAIT3_END_GROUP;
IMAD R12, R7, 0x10, R12 ?trans2;
IMAD R13, R26, R17, R13 &req={2} ?WAIT4_END_GROUP;
IMAD R13, R31, R18, R13 &req={3} ?WAIT4_END_GROUP;
IMAD R13, R25, R24, R13 ?WAIT4_END_GROUP;
IMAD R13, R32, R23, R13 ?WAIT4_END_GROUP;
IMAD R13, R30, R27, R13 ?WAIT4_END_GROUP;
IMAD R13, R33, R28, R13 ?WAIT4_END_GROUP;
IMAD R10, R35, R10, R13 ?WAIT4_END_GROUP;
IMAD R37, R37, R8, R10 ?WAIT4_END_GROUP;
IMAD R6, R36, R6, R37 ?WAIT4_END_GROUP;
IMAD R26, R34, R5, R6 ?trans1;
@P0 BRA 0x470 ?trans6;
@!P1 BRA 0x1070 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR34, 0x8, UPT ?trans1;
ULOP3.LUT UR5, UR8, 0x7, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR5, PT ?WAIT12_END_GROUP;
@!P1 BRA 0xd10 ?trans5;
LDCU.128 UR12, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R5, UR4 ?trans1;
MOV R14, UR6 ?trans1;
MOV R11, UR6 ?trans1;
USHF.R.S32.HI UR7, URZ, 0x1f, UR6 ?trans2;
IMAD R5, R5, UR6, R0 ?WAIT4_END_GROUP;
MOV R15, UR7 ?WAIT5_END_GROUP;
IADD.64 R2, R14, R14 ?trans2;
MOV.64 R6, UR14 &req={0} ?trans2;
UIMAD.WIDE.U32 UR10, UR4, 0x4, UR12 ?WAIT4_END_GROUP;
IMAD.WIDE R6, R5, 0x4, R6 ?trans1;
IADD.64 R4, R14, R2 ?WAIT3_END_GROUP;
LEA R12, P1, R2, R6, 0x2 ?trans1;
IADD.64 R20, R14, R4 ?trans2;
IMAD.WIDE R10, R11, 0x4, R6 ?trans1;
LEA R16, P2, R4, R6, 0x2 ?trans2;
LEA.HI.X R13, R2, R7.reuse, R3, 0x2, P1 ?trans2;
LEA.HI.X R17, R4, R7, R5, 0x2, P2 ?trans1;
IADD.64 R24, R14, R20 ?trans2;
MOV.64 R4, UR10 ?WAIT3_END_GROUP;
LEA R8, P1, R20.reuse, R6.reuse, 0x2 ?trans1;
LDG.E R18, desc[UR32][R10.64] &rd=0x0 &wr=0x2 ?trans3;
LEA.HI.X R9, R20, R7, R21, 0x2, P1 ?trans1;
LDG.E R23, desc[UR32][R4.64] &wr=0x3 ?trans4;
LDG.E R20, desc[UR32][R6.64] &wr=0x3 ?trans1;
LEA R2, P1, R24, R6, 0x2 ?trans1;
IADD.64 R10, R14, R24 &req={0} ?WAIT2_END_GROUP;
LDG.E R21, desc[UR32][R4.64+0x4] &wr=0x2 ?trans1;
LEA.HI.X R3, R24, R7, R25, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R19, desc[UR32][R12.64] &rd=0x0 &wr=0x4 ?trans4;
LDG.E R22, desc[UR32][R4.64+0x8] &wr=0x4 ?trans1;
IADD.64 R14, R14, R10 ?WAIT3_END_GROUP;
LDG.E R16, desc[UR32][R16.64] &wr=0x5 ?trans1;
LEA R12, P1, R10, R6, 0x2 &req={0} ?WAIT3_END_GROUP;
LDG.E R25, desc[UR32][R4.64+0xc] &wr=0x5 ?trans1;
LEA.HI.X R13, R10, R7, R11, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R8, desc[UR32][R8.64] &wr=0x5 ?trans1;
LEA R6, P1, R14, R6, 0x2 ?WAIT3_END_GROUP;
LDG.E R11, desc[UR32][R4.64+0x10] &wr=0x5 ?trans1;
LEA.HI.X R7, R14, R7, R15, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R2, desc[UR32][R2.64] &wr=0x5 ?trans4;
LDG.E R17, desc[UR32][R4.64+0x14] &wr=0x5 ?trans4;
LDG.E R12, desc[UR32][R12.64] &wr=0x5 ?trans4;
LDG.E R15, desc[UR32][R4.64+0x18] &wr=0x5 ?trans4;
LDG.E R27, desc[UR32][R4.64+0x1c] &wr=0x5 ?trans4;
LDG.E R6, desc[UR32][R6.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IMAD R20, R23, R20, R26 &req={3} ?WAIT4_END_GROUP;
IMAD R18, R21, R18, R20 &req={2} ?WAIT4_END_GROUP;
IMAD R18, R22, R19, R18 &req={4} ?WAIT4_END_GROUP;
IMAD R16, R25, R16, R18 &req={5} ?WAIT4_END_GROUP;
IMAD R8, R11, R8, R16 ?WAIT4_END_GROUP;
IMAD R2, R17, R2, R8 ?WAIT4_END_GROUP;
IMAD R2, R15, R12, R2 ?WAIT4_END_GROUP;
IMAD R26, R27, R6, R2 ?WAIT7_END_GROUP;
@!P0 BRA 0x1070 ?trans5;
UISETP.GE.U32.AND UP0, UPT, UR5, 0x4, UPT ?trans1;
ULOP3.LUT UR7, UR8, 0x3, URZ, 0xc0, !UPT ?WAIT5_END_GROUP;
PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x8 ?trans1;
ISETP.NE.AND P0, PT, RZ, UR7, PT ?WAIT12_END_GROUP;
@!P1 BRA 0xf60 ?trans5;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R7, UR4 ?trans1;
MOV R4, UR6 ?trans1;
MOV R15, UR6 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR6 ?trans2;
IMAD R7, R7, UR6, R0 ?WAIT4_END_GROUP;
MOV R5, UR5 ?trans1;
MOV.64 R2, UR10 &req={0} ?trans2;
UIMAD.WIDE.U32 UR8, UR4, 0x4, UR8 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R7, 0x4, R2 ?trans1;
IADD.64 R6, R4.reuse, R4 ?trans2;
MOV.64 R12, UR8 ?trans2;
IADD.64 R10, R4, R6 ?trans2;
IMAD.WIDE R4, R15, 0x4, R2 ?trans1;
LEA R8, P1, R6.reuse, R2.reuse, 0x2 ?trans1;
LDG.E R14, desc[UR32][R2.64] &wr=0x2 ?trans3;
LEA.HI.X R9, R6, R3, R7, 0x2, P1 ?trans1;
LDG.E R15, desc[UR32][R12.64] &wr=0x2 ?trans1;
LEA R6, P1, R10, R2, 0x2 ?WAIT3_END_GROUP;
LDG.E R4, desc[UR32][R4.64] &wr=0x3 ?trans1;
LEA.HI.X R7, R10, R3, R11, 0x2, P1 ?WAIT3_END_GROUP;
LDG.E R17, desc[UR32][R12.64+0x4] &wr=0x3 ?trans4;
LDG.E R8, desc[UR32][R8.64] &wr=0x4 ?trans4;
LDG.E R11, desc[UR32][R12.64+0x8] &wr=0x4 ?trans4;
LDG.E R10, desc[UR32][R12.64+0xc] &wr=0x5 ?trans4;
LDG.E R6, desc[UR32][R6.64] &wr=0x5 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IMAD R14, R15, R14, R26 &req={2} ?WAIT4_END_GROUP;
IMAD R14, R17, R4, R14 &req={3} ?WAIT4_END_GROUP;
IMAD R11, R11, R8, R14 &req={4} ?WAIT4_END_GROUP;
IMAD R26, R10, R6, R11 &req={5} ?WAIT7_END_GROUP;
@!P0 BRA 0x1070 ?trans5;
LDCU.64 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
LDC.64 R6, c[0x0][0x388] &wr=0x1 ?trans1;
MOV R9, UR4 ?trans1;
IADD3 R8, PT, PT, RZ, -UR7, RZ ?WAIT4_END_GROUP;
IMAD R9, R9, UR6, R0 ?trans1;
UIMAD.WIDE.U32 UR4, UR4, 0x4, UR8 &req={0} ?WAIT6_END_GROUP;
MOV.64 R2, UR4 ?WAIT8_END_GROUP;
IMAD.WIDE R4, R9.reuse, 0x4, R6 &req={1} ?trans1;
LDG.E R11, desc[UR32][R2.64] &rd=0x0 &wr=0x2 ?trans5;
LDG.E R4, desc[UR32][R4.64] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
IADD3 R9, PT, PT, R9, UR6, RZ ?trans1;
IADD.64 R2, R2, 0x4 &req={0} ?WAIT2_END_GROUP;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
IMAD R26, R11, R4, R26 &req={2} ?WAIT12_END_GROUP;
@P0 BRA 0xfe0 ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR32][R2.64], R26 ?trans1;
EXIT ?trans5;
BRA 0x10b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MV(int*, int*, int*, int, int)
_Z2MVPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mov_b32_e32 v2, v1
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s3, v2
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v5, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_cbranch_scc0 .LBB0_3
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MV | 6,944 | 846 | stackv2-00000-of-00015 |
// Demangled: vecadd(int*, int*, int*)
Function : _Z6vecaddPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R0, UR4, R9 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R9, 0xf423f, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecadd(int*, int*, int*)
_Z6vecaddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0xf4240, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecadd | 545 | 553 | stackv2-00000-of-00015 |
// Demangled: deviceKernel(int*, int)
Function : _Z12deviceKernelPii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x2 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
IMAD R2, R3, UR4, R2 &req={1} ?WAIT2_END_GROUP;
IMAD R0, R3, UR5, RZ &req={3} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
I2F.U32.RP R7, R0 &wr=0x0 ?trans1;
MOV R13, R2 ?trans1;
IADD3 R9, PT, PT, RZ, -R0, RZ ?trans1;
HFMA2 R2, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.U32.AND P2, PT, R0.reuse, RZ, PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R4, PT, PT, R0, R13, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x330 ?trans4;
ISETP.GE.AND P0, PT, R4.reuse, UR6, PT ?trans1;
VIMNMX.S32 R5, R4, UR6, !PT ?trans1;
MUFU.RCP R7, R7 &req={0} &wr=0x0 ?trans3;
SEL R6, RZ, 0x1, P0 ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, R5, -R4, -R6 ?trans2;
IADD3 R3, PT, PT, R7, 0xffffffe, RZ &req={0} ?WAIT6_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R3 &wr=0x0 ?trans2;
IMAD R9, R9, R3, RZ &req={0} ?WAIT4_END_GROUP;
IMAD.HI.U32 R2, R3, R9, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R2, R5, RZ ?WAIT5_END_GROUP;
IADD3 R2, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R5, R0, R2, R5 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, R0, PT ?WAIT13_END_GROUP;
@P0 IADD3 R5, PT, PT, -R0, R5, RZ ?trans2;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R5, R0, PT ?WAIT13_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R6, R3, RZ ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R3.reuse, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ?WAIT3_END_GROUP;
LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P0 BRA 0x320 &req={1} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, -R2, RZ, RZ ?trans1;
MOV R7, 0x1 ?WAIT7_END_GROUP;
IMAD.WIDE R2, R13, 0x4, R4 &req={0} ?trans1;
IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
IADD3 R13, PT, PT, R0, R13, RZ ?trans2;
STG.E desc[UR4][R2.64], R7 &rd=0x1 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x2c0 &req={1} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@!P1 EXIT ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R15, 0x1 ?WAIT7_END_GROUP;
IMAD.WIDE R10, R13, 0x4, R8 &req={1,0} ?trans1;
IADD3 R13, PT, PT, R0, R13, R0 ?WAIT4_END_GROUP;
STG.E desc[UR4][R10.64], R15 &rd=0x1 ?trans1;
IMAD.WIDE R2, R0.reuse, 0x4, R10 ?trans1;
IADD3 R13, PT, PT, R0, R13, R0 ?WAIT4_END_GROUP;
STG.E desc[UR4][R2.64], R15 &rd=0x1 ?trans1;
IMAD.WIDE R4, R0, 0x4, R2 ?trans1;
ISETP.GE.AND P0, PT, R13, UR6, PT ?WAIT4_END_GROUP;
STG.E desc[UR4][R4.64], R15 &rd=0x1 ?trans1;
IMAD.WIDE R6, R0, 0x4, R4 ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R15 &rd=0x1 ?trans3;
@!P0 BRA 0x360 ?trans5;
EXIT ?trans5;
BRA 0x430;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: deviceKernel(int*, int)
_Z12deviceKernelPii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s6, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s3, s2, 31
s_mov_b32 s1, 0
s_lshl_b64 s[4:5], s[2:3], 2
.LBB0_2:
v_add_nc_u32_e32 v1, s2, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| deviceKernel | 1,670 | 690 | stackv2-00000-of-00015 |
// Demangled: atomicFunc(float*, float*)
Function : _Z10atomicFuncPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
HFMA2 R8, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R3, R3, UR4, R0 &req={1} ?trans1;
MOV R0, RZ ?WAIT4_END_GROUP;
SHF.L.U32 R8, R8, R3.reuse, RZ ?trans2;
I2FP.F32.U32 R9, R3 ?trans2;
IADD3 R10, PT, PT, R3.reuse, 0x7, R3 ?trans2;
IADD3 R2, PT, PT, R3, -0x1, RZ &req={2} ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x1 ?trans2;
LDG.E R4, desc[UR8][R4.64] &req={1} &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R0, 0x186a0, PT ?trans1;
FSETP.NEU.AND P1, PT, R4, RZ, PT &req={2} ?WAIT13_END_GROUP;
@!P1 BRA 0x7e0 &req={5} ?trans5;
LDC.64 R14, c[0x0][0x380] &wr=0x1 ?trans1;
UMOV.64 UR4, URZ ?WAIT7_END_GROUP;
LDC.64 R16, c[0x0][0x388] &wr=0x2 ?trans2;
USHF.L.U64.HI UR7, UR4, 0x2, UR5 ?trans1;
USHF.L.U32 UR6, UR4, 0x2, URZ ?WAIT6_END_GROUP;
IADD.64 R4, R14, UR6 &req={1} ?WAIT6_END_GROUP;
LDG.E R11, desc[UR8][R4.64] &wr=0x3 ?trans1;
IADD.64 R6, R16, UR6 &req={2} ?trans2;
HFMA2 R13, -RZ, RZ, 2.5625, 0 ?WAIT4_END_GROUP;
STG.E desc[UR8][R6.64], R11 &req={3} &rd=0x1 ?trans4;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR8][R6.64], R13 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={5,1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x4] &wr=0x2 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans2;
POPC R12, UR6 &wr=0x1 ?trans1;
S2R R11, SR_LANEID &wr=0x3 ?trans1;
UFLO.U32 UR6, UR6 ?trans1;
IMAD R19, R12, -0xa, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.EQ.U32.AND P1, PT, R11, UR6, PT &req={3} ?trans1;
STG.E desc[UR8][R6.64+0x4], R13 &req={2} &rd=0x1 ?WAIT12_END_GROUP;
@P1 REDG.E.ADD.STRONG.GPU desc[UR8][R6.64+0x4], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x4] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x8] &wr=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x8], R13 &req={2} &rd=0x1 ?trans4;
ATOMG.E.EXCH.STRONG.GPU PT, RZ, desc[UR8][R6.64+0x8], R9 &rd=0x1 &wr=0x5 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x8] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0xc] &wr=0x2 ?trans1;
REDUX.MAX.S32 UR7, R3 &wr=0x1 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans2;
UFLO.U32 UR6, UR6 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P1, PT, R11, UR6, PT ?trans1;
MOV R19, UR7 &req={1} ?trans1;
STG.E desc[UR8][R6.64+0xc], R13 &req={2} &rd=0x1 ?trans11;
@P1 REDG.E.MAX.S32.STRONG.GPU desc[UR8][R6.64+0xc], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0xc] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x10] &wr=0x2 ?trans1;
REDUX.MIN.S32 UR7, R3 &wr=0x1 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans2;
UFLO.U32 UR6, UR6 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P1, PT, R11, UR6, PT ?trans1;
MOV R19, UR7 &req={1} ?trans1;
STG.E desc[UR8][R6.64+0x10], R13 &req={2} &rd=0x1 ?trans11;
@P1 REDG.E.MIN.S32.STRONG.GPU desc[UR8][R6.64+0x10], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x10] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x14] &wr=0x2 ?trans1;
MOV R19, 0x11 ?WAIT3_END_GROUP;
STG.E desc[UR8][R6.64+0x14], R13 &req={2} &rd=0x1 ?trans4;
REDG.E.INC.STRONG.GPU desc[UR8][R6.64+0x14], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x14] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x18] &wr=0x2 ?trans1;
HFMA2 R19, -RZ, RZ, 0, 8.165836334228515625e-06 ?WAIT3_END_GROUP;
STG.E desc[UR8][R6.64+0x18], R13 &req={2} &rd=0x1 ?trans4;
REDG.E.DEC.STRONG.GPU desc[UR8][R6.64+0x18], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x18] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x1c] &wr=0x2 ?trans4;
STG.E desc[UR8][R6.64+0x1c], R13 &req={2} &rd=0x1 ?trans4;
ATOMG.E.CAS.STRONG.GPU PT, RZ, [R6+0x1c], R2, R3 &rd=0x1 &wr=0x5 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x1c] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x20] &wr=0x2 ?trans1;
REDUX UR7, R10 &wr=0x1 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans2;
UFLO.U32 UR6, UR6 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P1, PT, R11, UR6, PT ?trans1;
MOV R19, UR7 &req={1} ?trans1;
STG.E desc[UR8][R6.64+0x20], R13 &req={2} &rd=0x1 ?trans11;
@P1 REDG.E.AND.STRONG.GPU desc[UR8][R6.64+0x20], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x20] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R13, desc[UR8][R4.64+0x24] &wr=0x2 ?trans1;
REDUX.OR UR7, R8 &wr=0x1 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans2;
UFLO.U32 UR6, UR6 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P1, PT, R11, UR6, PT ?trans1;
MOV R19, UR7 &req={1} ?trans1;
STG.E desc[UR8][R6.64+0x24], R13 &req={2} &rd=0x1 ?trans11;
@P1 REDG.E.OR.STRONG.GPU desc[UR8][R6.64+0x24], R19 &rd=0x1 ?trans4;
LDG.E R12, desc[UR8][R6.64+0x24] &wr=0x2 ?trans2;
FSETP.NEU.AND P1, PT, R12, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x7e0 &req={1} ?trans5;
LDG.E R5, desc[UR8][R4.64+0x28] &wr=0x2 ?trans1;
REDUX.XOR UR7, R3 &wr=0x1 ?trans1;
VOTEU.ANY UR6, UPT, PT ?trans2;
UFLO.U32 UR6, UR6 ?WAIT6_END_GROUP;
ISETP.EQ.U32.AND P1, PT, R11, UR6, PT ?trans1;
MOV R13, UR7 &req={1} ?trans1;
STG.E desc[UR8][R6.64+0x28], R5 &req={2} &rd=0x3 ?trans11;
@P1 REDG.E.XOR.STRONG.GPU desc[UR8][R6.64+0x28], R13 &rd=0x3 ?trans4;
LDG.E R11, desc[UR8][R6.64+0x2c] &wr=0x2 ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, 0xb, URZ ?trans1;
FSETP.NEU.AND P1, PT, R11, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P1 BRA 0x150 &req={3} ?trans5;
@P0 BRA 0xc0 ?trans5;
EXIT ?trans5;
BRA 0x800;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: atomicFunc(float*, float*)
_Z10atomicFuncPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s12, 0
v_mov_b32_e32 v5, 17
v_mov_b32_e32 v9, 0x89
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
v_cvt_f32_u32_e32 v6, v1
v_add_nc_u32_e32 v2, -1, v1
v_lshl_add_u32 v7, v1, 1, 7
v_lshlrev_b32_e64 v8, v1, 1
.LBB0_1:
global_load_b32 v3, v0, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_41
s_mov_b64 s[4:5], 0
s_mov_b64 s[8:9], s[2:3]
.LBB0_3:
s_lshl_b64 s[10:11], s[4:5], 2
s_mov_b32 s14, exec_lo
s_add_u32 s6, s0, s10
s_addc_u32 s7, s1, s11
v_mbcnt_lo_u32_b32 v3, s14, 0
global_load_b32 v4, v0, s[6:7]
s_mov_b32 s13, exec_lo
s_waitcnt vmcnt(0)
global_store_b32 v0, v4, s[8:9]
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_6
s_bcnt1_i32_b32 s14, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_ubyte0_e32 v3, s14
s_mov_b32 s14, 0
v_mul_f32_e32 v10, 0x41200000, v3
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v4, v10
global_atomic_cmpswap_b32 v3, v0, v[3:4], s[8:9] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v3, v4
v_mov_b32_e32 v4, v3
s_or_b32 s14, vcc_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
global_load_b32 v3, v0, s[8:9]
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:4
s_mov_b32 s13, exec_lo
s_add_u32 s8, s2, s10
v_mbcnt_lo_u32_b32 v4, s13, 0
s_addc_u32 s9, s3, s11
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:4
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_9
s_bcnt1_i32_b32 s11, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s11, s11, -10
v_mov_b32_e32 v3, s11
global_atomic_add_u32 v0, v3, s[8:9] offset:4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
global_load_b32 v3, v0, s[8:9] offset:4
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:8
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:8
global_atomic_swap_b32 v0, v6, s[8:9] offset:8
global_load_b32 v3, v0, s[8:9] offset:8
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:12
s_mov_b32 s11, exec_lo
s_brev_b32 s10, 1
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:12
.LBB0_12:
s_ctz_i32_b32 s13, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s14, v1, s13
s_lshl_b32 s13, 1, s13
s_and_not1_b32 s11, s11, s13
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s10, s10, s14
s_cmp_lg_u32 s11, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v3, exec_lo, 0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v3, s10
global_atomic_max_i32 v0, v3, s[8:9] offset:12
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s11
global_load_b32 v3, v0, s[8:9] offset:12
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:16
s_mov_b32 s11, exec_lo
s_brev_b32 s10, -2
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:16
.LBB0_17:
s_ctz_i32_b32 s13, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s14, v1, s13
s_lshl_b32 s13, 1, s13
s_and_not1_b32 s11, s11, s13
s_delay_alu instid0(VALU_DEP_1)
s_min_i32 s10, s10, s14
s_cmp_lg_u32 s11, 0
s_cbranch_scc1 .LBB0_17
v_mbcnt_lo_u32_b32 v3, exec_lo, 0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_20
v_mov_b32_e32 v3, s10
global_atomic_min_i32 v0, v3, s[8:9] offset:16
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s11
global_load_b32 v3, v0, s[8:9] offset:16
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:20
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:20
global_atomic_inc_u32 v0, v5, s[8:9] offset:20
global_load_b32 v3, v0, s[8:9] offset:20
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:24
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:24
global_atomic_dec_u32 v0, v9, s[8:9] offset:24
global_load_b32 v3, v0, s[8:9] offset:24
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:28
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:28
global_atomic_cmpswap_b32 v0, v[1:2], s[8:9] offset:28
global_load_b32 v3, v0, s[8:9] offset:28
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:32
s_mov_b32 s11, exec_lo
s_mov_b32 s10, -1
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:32
.LBB0_25:
s_ctz_i32_b32 s13, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s14, v7, s13
s_lshl_b32 s13, 1, s13
s_and_not1_b32 s11, s11, s13
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s10, s10, s14
s_cmp_lg_u32 s11, 0
s_cbranch_scc1 .LBB0_25
v_mbcnt_lo_u32_b32 v3, exec_lo, 0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_28
v_mov_b32_e32 v3, s10
global_atomic_and_b32 v0, v3, s[8:9] offset:32
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s11
global_load_b32 v3, v0, s[8:9] offset:32
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:36
s_mov_b32 s11, exec_lo
s_mov_b32 s10, 0
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:36
.LBB0_30:
s_ctz_i32_b32 s13, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s14, v8, s13
s_lshl_b32 s13, 1, s13
s_and_not1_b32 s11, s11, s13
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s10, s10, s14
s_cmp_lg_u32 s11, 0
s_cbranch_scc1 .LBB0_30
v_mbcnt_lo_u32_b32 v3, exec_lo, 0
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_33
v_mov_b32_e32 v3, s10
global_atomic_or_b32 v0, v3, s[8:9] offset:36
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s11
global_load_b32 v3, v0, s[8:9] offset:36
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v3
s_cbranch_vccnz .LBB0_39
global_load_b32 v3, v0, s[6:7] offset:40
s_mov_b32 s10, exec_lo
s_mov_b32 s6, 0
s_waitcnt vmcnt(0)
global_store_b32 v0, v3, s[8:9] offset:40
.LBB0_35:
s_ctz_i32_b32 s7, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s11, v1, s7
s_lshl_b32 s7, 1, s7
s_and_not1_b32 s10, s10, s7
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s6, s6, s11
s_cmp_lg_u32 s10, 0
s_cbranch_scc1 .LBB0_35
v_mbcnt_lo_u32_b32 v3, exec_lo, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_38
v_mov_b32_e32 v3, s6
global_atomic_xor_b32 v0, v3, s[8:9] offset:40
.LBB0_38:
s_or_b32 exec_lo, exec_lo, s7
global_load_b32 v3, v0, s[8:9] offset:44
s_add_u32 s4, s4, 11
s_addc_u32 s5, s5, 0
s_add_u32 s8, s8, 44
s_addc_u32 s9, s9, 0
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e64 s6, 0, v3
s_branch .LBB0_40
.LBB0_39:
s_mov_b32 s6, -1
.LBB0_40:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccz .LBB0_3
.LBB0_41:
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, 0x186a0
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| atomicFunc | 3,589 | 4,352 | stackv2-00000-of-00015 |
// Demangled: primeTesting(number*, unsigned int, unsigned int)
Function : _Z12primeTestingP6numberjj
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.GE.U32.AND P0, PT, R0, 0x2, PT &req={1} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
S2UR UR7, SR_CTAID.X &wr=0x0 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans1;
LDCU UR8, c[0x0][0x370] &wr=0x1 ?trans4;
VIMNMX.U32 R0, R0, 0x3, !PT ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x2 ?trans1;
UMOV UR4, 0x2 ?WAIT5_END_GROUP;
LDC R2, c[0x0][0x38c] &wr=0x3 ?trans2;
ISETP.LE.U32.AND P0, PT, R2, UR7, PT &req={3,0} ?WAIT13_END_GROUP;
@P0 BRA 0x320 &req={4} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
MOV R9, UR7 ?trans1;
LDCU UR9, c[0x0][0x38c] &wr=0x3 ?trans1;
UMOV UR5, URZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R4, R9, 0x10, R2 &req={4,0} ?WAIT5_END_GROUP;
LDG.E.64 R6, desc[UR10][R4.64] &req={2} &wr=0x2 ?trans1;
IADD3 R9, PT, PT, R9, UR8, RZ &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R9, UR9, PT &req={3} ?trans1;
ISETP.NE.U32.AND P0, PT, R7, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x2b0 ?trans5;
UI2F.U32.RP UR6, UR4 ?trans1;
HFMA2 R10, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ?WAIT7_END_GROUP;
MUFU.RCP R8, UR6 &wr=0x0 ?trans2;
IADD3 R8, PT, PT, R8, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R11, R8 &wr=0x0 ?trans2;
IADD3 R13, PT, PT, RZ, -R11, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R13, R13, UR4, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R11, R11, R13, R10 ?WAIT6_END_GROUP;
IMAD.HI.U32 R11, R11, R6, RZ ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, -R11, RZ, RZ ?WAIT5_END_GROUP;
IMAD R10, R11, UR4, R6 ?trans1;
MOV R11, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R10, UR4, PT ?WAIT13_END_GROUP;
@P0 IADD3 R10, PT, PT, R10, -UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R10, UR4, PT ?WAIT13_END_GROUP;
@P0 IADD3 R10, PT, PT, R10, -UR4, RZ ?trans2;
@!P2 LOP3.LUT R10, RZ, UR4, RZ, 0x33, !PT ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R10, RZ, PT ?trans2;
BRA 0x2f0 ?WAIT12_END_GROUP;
MOV R10, UR4 ?trans1;
MOV R8, 0x2e0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x360 ?trans5;
ISETP.NE.S64.AND P0, PT, R10, RZ, PT ?WAIT14_END_GROUP;
ISETP.EQ.S64.OR P0, PT, R6, UR4, P0 ?WAIT14_END_GROUP;
@!P0 STG.E.U8 desc[UR10][R4.64+0x8], RZ &rd=0x4 ?trans1;
@!P1 BRA 0x110 ?trans5;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, R0, UR4, PT ?WAIT13_END_GROUP;
@P0 BRA 0xa0 ?trans5;
EXIT &req={2,1} ?trans5;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
I2F.U64.RP R16, R10 &wr=0x0 ?trans2;
MUFU.RCP R16, R16 &req={0} &wr=0x0 ?trans2;
IADD3 R12, PT, PT, R16, 0x1ffffffe, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.U64.TRUNC R12, R12 &wr=0x0 ?trans2;
IMAD.WIDE.U32 R14, R12, R10, RZ &req={0} ?WAIT4_END_GROUP;
IMAD R15, R13, R10, R15 ?trans1;
IADD3 R17, P0, PT, RZ, -R14, RZ ?WAIT4_END_GROUP;
IADD3.X R19, PT, PT, RZ, ~R15, RZ, P0, !PT ?trans1;
IMAD.HI.U32 R14, R12, R17, RZ ?trans1;
MOV R15, R12 ?WAIT3_END_GROUP;
IMAD R21, R13, R19.reuse, RZ ?trans2;
IMAD.WIDE.U32 R14, P0, R12, R19, R14 ?WAIT4_END_GROUP;
IMAD.HI.U32 R19, R13, R19, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R14, P2, R13, R17, R14 ?WAIT5_END_GROUP;
IADD3 R15, P3, PT, R21, R14, RZ ?trans2;
IADD3.X R14, PT, PT, R19, R13, RZ, P0, !PT ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R12, R15, R10, RZ ?trans1;
IADD3.X R17, PT, PT, RZ, RZ, R14, P3, P2 ?trans2;
IADD3 R19, P0, PT, RZ, -R12, RZ ?WAIT3_END_GROUP;
IMAD R12, R17, R10, R13 ?trans2;
HFMA2 R13, -RZ, RZ, 0, 0 ?trans2;
IMAD.HI.U32 R14, R15, R19, RZ ?trans1;
IADD3.X R12, PT, PT, RZ, ~R12, RZ, P0, !PT ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R14, P0, R15, R12, R14 ?WAIT4_END_GROUP;
IMAD R16, R17.reuse, R12, RZ ?trans2;
IMAD.HI.U32 R15, P2, R17, R19, R14 ?WAIT4_END_GROUP;
IMAD.HI.U32 R12, R17, R12, RZ ?trans1;
IADD3 R15, P3, PT, R16, R15, RZ ?WAIT4_END_GROUP;
IADD3.X R17, PT, PT, R12, R17, RZ, P0, !PT ?trans1;
IMAD.HI.U32 R12, R15, R6, RZ ?WAIT3_END_GROUP;
IADD3.X R17, PT, PT, RZ, RZ, R17, P3, P2 ?trans1;
ISETP.NE.S64.AND P2, PT, R10, RZ, PT ?trans2;
IMAD.WIDE.U32 R12, R15, R7, R12 ?WAIT4_END_GROUP;
IMAD.HI.U32 R14, R17, R7, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R13, P0, R17, R6, R12 ?WAIT4_END_GROUP;
IMAD R16, R17, R7, RZ ?trans1;
IADD3.X R12, PT, PT, R14, RZ, RZ, P0, !PT ?WAIT4_END_GROUP;
IADD3 R13, P0, PT, R16, R13, RZ ?WAIT4_END_GROUP;
IADD3.X R15, PT, PT, RZ, R12, RZ, P0, !PT ?trans1;
IMAD.WIDE.U32 R12, R13, R10, RZ ?WAIT4_END_GROUP;
IMAD R13, R15, R10, R13 ?WAIT5_END_GROUP;
IADD.64 R12, R6, -R12 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R12, R10, PT ?WAIT14_END_GROUP;
@P0 IADD.64 R12, -R10, R12 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R12, R10, PT ?WAIT14_END_GROUP;
@P0 IADD.64 R12, -R10, R12 ?WAIT4_END_GROUP;
SEL.64 R10, R12, -0x1, P2 ?trans2;
MOV R12, R8 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R12 0x0 ?trans5;
BRA 0x6c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: primeTesting(number*, unsigned int, unsigned int)
_Z12primeTestingP6numberjj:
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s4, 2
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s2, 2
s_cbranch_scc1 .LBB0_8
s_load_b64 s[6:7], s[0:1], 0x0
s_cmp_lt_u32 s15, s3
s_mov_b32 s11, 0
s_cselect_b32 s5, -1, 0
s_add_u32 s8, s0, 16
v_cndmask_b32_e64 v0, 0, 1, s5
s_addc_u32 s9, s1, 0
s_add_i32 s1, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_max_u32 s2, s1, 3
v_cmp_ne_u32_e64 s0, 1, v0
v_mov_b32_e32 v0, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_7
v_cvt_f32_u32_e32 v1, s4
s_load_b32 s14, s[8:9], 0x0
s_mov_b32 s5, s11
s_mov_b32 s10, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v1, 0, 0x4f800000
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v1, 0xcf800000, v2
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
.LBB0_4:
s_lshl_b64 s[12:13], s[10:11], 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s1, v1
v_readfirstlane_b32 s18, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s16, s6, s12
s_addc_u32 s17, s7, s13
s_sub_u32 s19, 0, s4
s_subb_u32 s20, 0, 0
s_mul_hi_u32 s21, s19, s1
s_mul_i32 s22, s19, s18
s_mul_i32 s23, s20, s1
s_add_i32 s21, s21, s22
s_mul_i32 s22, s19, s1
s_add_i32 s21, s21, s23
s_mul_hi_u32 s24, s1, s22
s_mul_i32 s23, s1, s21
s_mul_hi_u32 s1, s1, s21
s_add_u32 s23, s24, s23
s_mul_i32 s25, s18, s22
s_addc_u32 s1, 0, s1
s_mul_hi_u32 s22, s18, s22
s_mul_hi_u32 s24, s18, s21
s_add_u32 s23, s23, s25
s_addc_u32 s1, s1, s22
s_mul_i32 s21, s18, s21
s_addc_u32 s22, s24, 0
s_add_u32 s1, s1, s21
s_addc_u32 s21, 0, s22
v_add_co_u32 v3, s1, v1, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s1, 0
s_load_b64 s[16:17], s[16:17], 0x0
s_addc_u32 s18, s18, s21
v_readfirstlane_b32 s1, v3
s_mul_i32 s21, s19, s18
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s22, s19, s1
s_mul_i32 s20, s20, s1
s_add_i32 s21, s22, s21
s_mul_i32 s19, s19, s1
s_add_i32 s21, s21, s20
s_mul_hi_u32 s22, s18, s19
s_mul_i32 s23, s18, s19
s_mul_i32 s24, s1, s21
s_mul_hi_u32 s19, s1, s19
s_mul_hi_u32 s1, s1, s21
s_add_u32 s19, s19, s24
s_addc_u32 s1, 0, s1
s_mul_hi_u32 s20, s18, s21
s_add_u32 s19, s19, s23
s_addc_u32 s1, s1, s22
s_mul_i32 s19, s18, s21
s_addc_u32 s20, s20, 0
s_add_u32 s1, s1, s19
s_addc_u32 s19, 0, s20
v_add_co_u32 v3, s1, v3, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s1, 0
s_addc_u32 s18, s18, s19
v_readfirstlane_b32 s1, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s19, s16, s18
s_mul_hi_u32 s21, s16, s18
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s20, s16, s1
s_mul_i32 s22, s17, s1
s_add_u32 s19, s20, s19
s_addc_u32 s20, 0, s21
s_mul_hi_u32 s1, s17, s1
s_mul_hi_u32 s21, s17, s18
s_add_u32 s19, s19, s22
s_addc_u32 s1, s20, s1
s_mul_i32 s18, s17, s18
s_addc_u32 s19, s21, 0
s_add_u32 s1, s1, s18
s_addc_u32 s18, 0, s19
s_mul_hi_u32 s19, s4, s1
s_mul_i32 s1, s4, s1
s_mul_i32 s18, s4, s18
v_sub_co_u32 v3, s1, s16, s1
s_add_i32 s19, s19, s18
s_cmp_lg_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_co_u32 v4, s1, v3, s4
s_subb_u32 s18, s17, s19
s_cmp_lg_u32 s1, 0
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_sub_co_u32 v5, s1, v4, s4
s_subb_u32 s19, s18, 0
s_cmp_lg_u32 s1, 0
v_cndmask_b32_e64 v6, 0, -1, vcc_lo
s_subb_u32 s1, s19, 0
s_cmp_eq_u32 s19, 0
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s18, 0
v_cndmask_b32_e32 v6, -1, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
v_dual_cndmask_b32 v5, v4, v5 :: v_dual_mov_b32 v8, s1
s_cselect_b32 s1, -1, 0
s_cmp_eq_u64 s[16:17], s[4:5]
v_cndmask_b32_e64 v6, -1, v7, s1
s_cselect_b32 s1, -1, 0
v_cndmask_b32_e32 v7, s19, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cndmask_b32_e32 v4, s18, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[3:4]
s_or_b32 s1, s1, vcc_lo
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
global_store_b8 v0, v0, s[12:13] offset:8
.LBB0_6:
s_add_i32 s10, s10, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s10, s3
s_cbranch_scc1 .LBB0_4
.LBB0_7:
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, s2
s_cbranch_scc1 .LBB0_2
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| primeTesting | 2,761 | 2,964 | stackv2-00000-of-00015 |
// Demangled: kernel_1t1c(float (*) [1000], float (*) [1000], float (*) [1000], int)
Function : _Z11kernel_1t1cPA1000_fS0_S0_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R7, c[0x0][0x364] &wr=0x1 ?trans8;
LDC R6, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R7, R7, UR4, R0 &req={1} ?trans1;
ISETP.GE.AND P0, PT, R6, 0x1, PT &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R7, R6, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R6.reuse, 0x10, PT ?trans1;
LOP3.LUT R14, R6, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT3_END_GROUP;
ISETP.NE.AND P0, PT, R14, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x600 ?trans6;
LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
LEA R8, P1, R7.reuse, 0x7d00, 0x2 ?trans2;
LOP3.LUT R10, R6, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x2 ?trans1;
LEA.HI.X R9, R7, RZ, RZ, 0x2, P1 ?trans1;
MOV R0, RZ ?trans1;
IADD3 R10, PT, PT, -R10, RZ, RZ ?WAIT3_END_GROUP;
IADD.64 R2, R8.reuse, UR10 &req={1} ?trans2;
IADD.64 R4, R8.reuse, UR8 ?trans2;
IADD.64 R8, R8, UR6 &req={2} ?WAIT8_END_GROUP;
LDG.E R11, desc[UR4][R2.64+-0x7d00] &req={0} &wr=0x2 ?trans4;
LDG.E R12, desc[UR4][R8.64+-0x7d00] &wr=0x2 ?trans2;
FADD R11, R11, R12 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x7d00], R11 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R2.64+-0x6d60] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x6d60] &wr=0x2 ?trans2;
FADD R13, R12, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x6d60], R13 &rd=0x1 ?trans4;
LDG.E R12, desc[UR4][R2.64+-0x5dc0] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+-0x5dc0] &wr=0x2 ?trans2;
FADD R15, R12, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x5dc0], R15 &rd=0x2 ?trans4;
LDG.E R12, desc[UR4][R2.64+-0x4e20] &wr=0x3 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0x4e20] &wr=0x3 ?trans2;
FADD R17, R12, R17 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x4e20], R17 &rd=0x3 ?trans4;
LDG.E R11, desc[UR4][R2.64+-0x3e80] &req={0} &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R8.64+-0x3e80] &wr=0x4 ?trans2;
FADD R11, R11, R12 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x3e80], R11 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R2.64+-0x2ee0] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x2ee0] &req={1} &wr=0x4 ?trans2;
FADD R13, R12, R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x2ee0], R13 &rd=0x1 ?trans4;
LDG.E R12, desc[UR4][R2.64+-0x1f40] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R8.64+-0x1f40] &req={2} &wr=0x4 ?trans2;
FADD R15, R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0x1f40], R15 &rd=0x2 ?trans4;
LDG.E R12, desc[UR4][R2.64+-0xfa0] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0xfa0] &req={3} &wr=0x4 ?trans2;
FADD R17, R12, R17 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+-0xfa0], R17 &rd=0x3 ?trans4;
LDG.E R11, desc[UR4][R2.64] &req={0} &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R8.64] &wr=0x4 ?trans2;
FADD R11, R11, R12 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R11 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R2.64+0xfa0] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R8.64+0xfa0] &req={1} &wr=0x4 ?trans2;
FADD R13, R12, R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0xfa0], R13 &rd=0x1 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x1f40] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x1f40] &req={2} &wr=0x4 ?trans2;
FADD R15, R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x1f40], R15 &rd=0x2 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x2ee0] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R8.64+0x2ee0] &req={3} &wr=0x4 ?trans2;
FADD R17, R12, R17 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x2ee0], R17 &rd=0x3 ?trans4;
LDG.E R11, desc[UR4][R2.64+0x3e80] &req={0} &wr=0x4 ?trans4;
LDG.E R12, desc[UR4][R8.64+0x3e80] &wr=0x4 ?trans2;
FADD R11, R11, R12 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x3e80], R11 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x4e20] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R8.64+0x4e20] &req={1} &wr=0x4 ?trans2;
FADD R13, R12, R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x4e20], R13 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x5dc0] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x5dc0] &req={2} &wr=0x4 ?trans1;
IADD3 R10, PT, PT, R10, 0x10, RZ ?trans1;
FADD R15, R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x5dc0], R15 ?trans4;
LDG.E R12, desc[UR4][R2.64+0x6d60] &rd=0x0 &wr=0x2 ?trans4;
LDG.E R17, desc[UR4][R8.64+0x6d60] &req={3} &rd=0x1 &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R10, RZ, PT ?trans1;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans1;
IADD.64 R2, R2, 0xfa00 &req={0} ?WAIT2_END_GROUP;
IADD.64 R8, R8, 0xfa00 &req={1} ?trans2;
FADD R17, R12, R17 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x6d60], R17 &rd=0x0 ?trans2;
IADD.64 R4, R4, 0xfa00 &req={0} ?trans2;
@P1 BRA 0x190 ?trans6;
@!P0 EXIT &req={0} ?trans5;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R14, 0x8, PT ?trans1;
IMAD.SHL.U32 R2, R7, 0x4, RZ ?trans1;
SHF.R.U32.HI R3, RZ, 0x1e, R7 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x1 ?trans1;
LOP3.LUT R20, R6, 0x7, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R20, RZ, PT ?trans1;
IADD.64 R10, R2.reuse, UR10 &req={0} ?trans2;
IADD.64 R4, R2.reuse, UR8 ?trans2;
IADD.64 R8, R2, UR6 &req={1} ?trans2;
@!P0 BRA 0x900 ?trans6;
IMAD.WIDE.U32 R16, R0, 0xfa0, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R0.reuse, 0xfa0, R8 ?trans1;
LDG.E R7, desc[UR4][R16.64] &wr=0x2 ?trans4;
LDG.E R18, desc[UR4][R14.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R12, R0, 0xfa0, R4 ?WAIT4_END_GROUP;
FADD R7, R7, R18 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64], R7 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0xfa0] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R14.64+0xfa0] &wr=0x2 ?trans2;
FADD R19, R18, R19 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0xfa0], R19 &rd=0x1 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x1f40] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R14.64+0x1f40] &wr=0x2 ?trans2;
FADD R21, R18, R21 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x1f40], R21 &rd=0x2 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x2ee0] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R14.64+0x2ee0] &wr=0x3 ?trans2;
FADD R23, R18, R23 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x2ee0], R23 &rd=0x3 ?trans4;
LDG.E R7, desc[UR4][R16.64+0x3e80] &req={0} &wr=0x4 ?trans4;
LDG.E R18, desc[UR4][R14.64+0x3e80] &wr=0x4 ?trans2;
FADD R7, R7, R18 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x3e80], R7 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x4e20] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R14.64+0x4e20] &req={1} &wr=0x4 ?trans2;
FADD R19, R18, R19 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x4e20], R19 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x5dc0] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R14.64+0x5dc0] &req={2} &wr=0x4 ?trans2;
FADD R21, R18, R21 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x5dc0], R21 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x6d60] &wr=0x2 ?trans4;
LDG.E R23, desc[UR4][R14.64+0x6d60] &req={3} &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?trans1;
FADD R23, R18, R23 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x6d60], R23 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R20, 0x4, PT ?trans1;
LOP3.LUT R12, R6, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xa90 ?trans6;
IMAD.WIDE.U32 R10, R0, 0xfa0, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R0.reuse, 0xfa0, R8 ?trans1;
LDG.E R6, desc[UR4][R10.64] &wr=0x2 ?trans4;
LDG.E R7, desc[UR4][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R0, 0xfa0, R4 ?WAIT4_END_GROUP;
FADD R7, R6, R7 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R10.64+0xfa0] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R8.64+0xfa0] &wr=0x2 ?trans2;
FADD R13, R6, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0xfa0], R13 &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R10.64+0x1f40] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x1f40] &wr=0x2 ?trans2;
FADD R15, R6, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x1f40], R15 &rd=0x0 ?trans4;
LDG.E R6, desc[UR4][R10.64+0x2ee0] &wr=0x2 ?trans4;
LDG.E R17, desc[UR4][R8.64+0x2ee0] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x4, RZ ?trans1;
FADD R17, R6, R17 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64+0x2ee0], R17 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
IMAD.WIDE.U32 R2, R0, 0xfa0, R2 ?trans1;
IADD3 R12, PT, PT, -R12, RZ, RZ ?WAIT4_END_GROUP;
IADD.64 R4, R2.reuse, UR8 &req={0} ?trans2;
IADD.64 R6, R2.reuse, UR10 ?trans2;
IADD.64 R2, R2, UR6 ?WAIT8_END_GROUP;
LDG.E R0, desc[UR4][R6.64] &rd=0x0 &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R2.64] &rd=0x1 &wr=0x2 ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
IADD.64 R6, R6, 0xfa0 &req={0} ?trans2;
IADD.64 R2, R2, 0xfa0 &req={1} ?trans2;
FADD R9, R0, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R9 &rd=0x0 ?trans2;
IADD.64 R4, R4, 0xfa0 &req={0} ?trans2;
@P0 BRA 0xaf0 ?trans6;
EXIT ?trans5;
BRA 0xba0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel_1t1c(float (*) [1000], float (*) [1000], float (*) [1000], int)
_Z11kernel_1t1cPA1000_fS0_S0_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, 0, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB2_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, 0xfa0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, 0xfa0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, 0xfa0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel_1t1c | 5,417 | 863 | stackv2-00000-of-00015 |
// Demangled: kernel_1t1e(float (*) [1000], float (*) [1000], float (*) [1000], int)
Function : _Z11kernel_1t1ePA1000_fS0_S0_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x2 ?trans1;
S2R R2, SR_TID.Y &wr=0x3 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R11, c[0x0][0x364] &wr=0x3 ?trans1;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT2_END_GROUP;
IMAD R11, R11, UR5, R2 &req={3} ?WAIT5_END_GROUP;
VIMNMX.S32 R0, R9, R11, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0xfa0, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R11, 0x4, R2 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R9, 0xfa0, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R4, R11, 0x4, R4 ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0xfa0, R6 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R11, 0x4, R6 ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x1c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel_1t1e(float (*) [1000], float (*) [1000], float (*) [1000], int)
_Z11kernel_1t1ePA1000_fS0_S0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s4, v[4:5]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v1, v2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_i64_i32 v[3:4], null, 0xfa0, v2, 0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v1, vcc_lo
global_load_b32 v2, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, v3, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v5
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel_1t1e | 777 | 981 | stackv2-00000-of-00015 |
// Demangled: kernel_1t1r(float (*) [1000], float (*) [1000], float (*) [1000], int)
Function : _Z11kernel_1t1rPA1000_fS0_S0_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans8;
LDC R2, c[0x0][0x398] &wr=0x2 ?trans1;
IMAD R3, R3, UR4, R0 &req={1} ?trans1;
ISETP.GE.AND P0, PT, R2, 0x1, PT &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R3, R2, !P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.GE.U32.AND P1, PT, R2.reuse, 0x10, PT ?trans1;
LOP3.LUT R14, R2, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
SHF.R.S32.HI R10, RZ, 0x1f, R3 ?trans2;
ISETP.NE.AND P0, PT, R14, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x630 ?trans6;
LDCU.128 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
MOV.64 R8, 0x20 ?trans2;
IMAD R5, R10, 0xfa0, RZ ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x2 ?trans1;
LOP3.LUT R11, R2, 0x7ffffff0, RZ, 0xc0, !PT ?trans2;
IMAD.WIDE.U32 R8, R3, 0xfa0, R8 ?trans1;
MOV R0, RZ ?trans1;
IADD3 R11, PT, PT, -R11, RZ, RZ ?WAIT3_END_GROUP;
IADD3 R9, PT, PT, R9, R5, RZ ?WAIT5_END_GROUP;
IADD.64 R4, R8.reuse, UR10 &req={1} ?trans2;
IADD.64 R6, R8.reuse, UR8 ?trans2;
IADD.64 R8, R8, UR6 &req={2} ?WAIT8_END_GROUP;
LDG.E R12, desc[UR4][R4.64+-0x20] &req={0} &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x20] &wr=0x2 ?trans2;
FADD R13, R12, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x20], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0x1c] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+-0x1c] &wr=0x2 ?trans2;
FADD R15, R12, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x1c], R15 &rd=0x1 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0x18] &wr=0x2 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0x18] &wr=0x2 ?trans2;
FADD R17, R12, R17 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x18], R17 &rd=0x2 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0x14] &wr=0x3 ?trans4;
LDG.E R19, desc[UR4][R8.64+-0x14] &wr=0x3 ?trans2;
FADD R19, R12, R19 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x14], R19 &rd=0x3 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0x10] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R8.64+-0x10] &req={0} &wr=0x4 ?trans2;
FADD R13, R12, R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x10], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0xc] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R8.64+-0xc] &req={1} &wr=0x4 ?trans2;
FADD R15, R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0xc], R15 &rd=0x1 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0x8] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R8.64+-0x8] &req={2} &wr=0x4 ?trans2;
FADD R17, R12, R17 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x8], R17 &rd=0x2 ?trans4;
LDG.E R12, desc[UR4][R4.64+-0x4] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R8.64+-0x4] &req={3} &wr=0x4 ?trans2;
FADD R19, R12, R19 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x4], R19 &rd=0x3 ?trans4;
LDG.E R12, desc[UR4][R4.64] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R8.64] &req={0} &wr=0x4 ?trans2;
FADD R13, R12, R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x4] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x4] &req={1} &wr=0x4 ?trans2;
FADD R15, R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R15 &rd=0x1 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x8] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R8.64+0x8] &req={2} &wr=0x4 ?trans2;
FADD R17, R12, R17 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x8], R17 &rd=0x2 ?trans4;
LDG.E R12, desc[UR4][R4.64+0xc] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R8.64+0xc] &req={3} &wr=0x4 ?trans2;
FADD R19, R12, R19 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0xc], R19 &rd=0x3 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x10] &wr=0x4 ?trans4;
LDG.E R13, desc[UR4][R8.64+0x10] &req={0} &wr=0x4 ?trans2;
FADD R13, R12, R13 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x10], R13 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x14] &wr=0x4 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x14] &req={1} &wr=0x4 ?trans2;
FADD R15, R12, R15 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x14], R15 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x18] &wr=0x4 ?trans4;
LDG.E R17, desc[UR4][R8.64+0x18] &req={2} &wr=0x4 ?trans1;
IADD3 R11, PT, PT, R11, 0x10, RZ ?trans1;
FADD R17, R12, R17 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x18], R17 ?trans4;
LDG.E R12, desc[UR4][R4.64+0x1c] &rd=0x0 &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R8.64+0x1c] &req={3} &rd=0x1 &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R11, RZ, PT ?trans1;
IADD3 R0, PT, PT, R0, 0x10, RZ ?trans1;
IADD.64 R4, R4, 0x40 &req={0} ?WAIT2_END_GROUP;
IADD.64 R8, R8, 0x40 &req={1} ?trans2;
FADD R19, R12, R19 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x1c], R19 &rd=0x0 ?trans2;
IADD.64 R6, R6, 0x40 &req={0} ?trans2;
@P1 BRA 0x1c0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R14, 0x8, PT ?trans1;
IMAD R7, R10, 0xfa0, RZ ?trans1;
LOP3.LUT R20, R2, 0x7, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R4, R3, 0xfa0, RZ ?WAIT3_END_GROUP;
ISETP.NE.AND P1, PT, R20, RZ, PT ?trans2;
IADD3 R5, PT, PT, R7, R5, RZ ?WAIT5_END_GROUP;
IADD.64 R10, R4.reuse, UR10 &req={0} ?trans2;
IADD.64 R6, R4.reuse, UR8 ?trans2;
IADD.64 R8, R4, UR6 &req={1} ?trans2;
@!P0 BRA 0x940 ?trans6;
IMAD.WIDE.U32 R16, R0, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R14, R0.reuse, 0x4, R8 ?trans1;
LDG.E R3, desc[UR4][R16.64] &wr=0x2 ?trans4;
LDG.E R18, desc[UR4][R14.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R12, R0, 0x4, R6 ?WAIT4_END_GROUP;
FADD R3, R3, R18 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64], R3 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x4] &wr=0x2 ?trans4;
LDG.E R19, desc[UR4][R14.64+0x4] &wr=0x2 ?trans2;
FADD R19, R18, R19 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x4], R19 &rd=0x1 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x8] &wr=0x2 ?trans4;
LDG.E R21, desc[UR4][R14.64+0x8] &wr=0x2 ?trans2;
FADD R21, R18, R21 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x8], R21 &rd=0x2 ?trans4;
LDG.E R18, desc[UR4][R16.64+0xc] &wr=0x3 ?trans4;
LDG.E R23, desc[UR4][R14.64+0xc] &wr=0x3 ?trans2;
FADD R23, R18, R23 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0xc], R23 &rd=0x3 ?trans4;
LDG.E R3, desc[UR4][R16.64+0x10] &req={0} &wr=0x4 ?trans4;
LDG.E R18, desc[UR4][R14.64+0x10] &wr=0x4 ?trans2;
FADD R3, R3, R18 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x10], R3 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x14] &wr=0x4 ?trans4;
LDG.E R19, desc[UR4][R14.64+0x14] &req={1} &wr=0x4 ?trans2;
FADD R19, R18, R19 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x14], R19 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x18] &wr=0x4 ?trans4;
LDG.E R21, desc[UR4][R14.64+0x18] &req={2} &wr=0x4 ?trans2;
FADD R21, R18, R21 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x18], R21 &rd=0x0 ?trans4;
LDG.E R18, desc[UR4][R16.64+0x1c] &wr=0x2 ?trans4;
LDG.E R23, desc[UR4][R14.64+0x1c] &req={3} &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x8, RZ ?trans1;
FADD R23, R18, R23 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+0x1c], R23 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P0, PT, R20, 0x4, PT ?trans1;
LOP3.LUT R12, R2, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R12, RZ, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xad0 ?trans6;
IMAD.WIDE.U32 R10, R0, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R0.reuse, 0x4, R8 ?trans1;
LDG.E R2, desc[UR4][R10.64] &wr=0x2 ?trans4;
LDG.E R3, desc[UR4][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R0, 0x4, R6 ?WAIT4_END_GROUP;
FADD R3, R2, R3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R3 &rd=0x0 ?trans4;
LDG.E R2, desc[UR4][R10.64+0x4] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R8.64+0x4] &wr=0x2 ?trans2;
FADD R13, R2, R13 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R13 &rd=0x0 ?trans4;
LDG.E R2, desc[UR4][R10.64+0x8] &wr=0x2 ?trans4;
LDG.E R15, desc[UR4][R8.64+0x8] &wr=0x2 ?trans2;
FADD R15, R2, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x8], R15 &rd=0x0 ?trans4;
LDG.E R2, desc[UR4][R10.64+0xc] &wr=0x2 ?trans4;
LDG.E R17, desc[UR4][R8.64+0xc] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0x4, RZ ?trans1;
FADD R17, R2, R17 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0xc], R17 &rd=0x0 ?trans2;
@!P1 EXIT ?trans5;
IMAD.WIDE.U32 R4, R0, 0x4, R4 ?trans1;
IADD3 R12, PT, PT, -R12, RZ, RZ ?WAIT4_END_GROUP;
IADD.64 R2, R4.reuse, UR8 &req={0} ?trans2;
IADD.64 R6, R4.reuse, UR10 ?trans2;
IADD.64 R4, R4, UR6 ?WAIT8_END_GROUP;
LDG.E R0, desc[UR4][R6.64] &rd=0x0 &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R4.64] &rd=0x1 &wr=0x2 ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R12, RZ, PT ?trans1;
IADD.64 R6, R6, 0x4 &req={0} ?trans2;
IADD.64 R4, R4, 0x4 &req={1} ?trans2;
FADD R9, R0, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R9 &rd=0x0 ?trans2;
IADD.64 R2, R2, 0x4 &req={0} ?trans2;
@P0 BRA 0xb30 ?trans6;
EXIT ?trans5;
BRA 0xbe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel_1t1r(float (*) [1000], float (*) [1000], float (*) [1000], int)
_Z11kernel_1t1rPA1000_fS0_S0_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB1_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_i64_i32 v[4:5], null, 0xfa0, v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB1_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel_1t1r | 5,338 | 793 | stackv2-00000-of-00015 |
// Demangled: void reduce6<128u>(float*, float*)
Function : _Z7reduce6ILj128EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9.reuse, 0x3f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
@!P0 LDS R2, [R7+0x100] &req={0} ?trans1;
BSSY.RECONVERGENT B0, 0x3a0 ?trans1;
ISETP.GT.U32.AND P2, PT, R0, 0x83, PT ?trans2;
@!P0 LDS R3, [R7] &wr=0x0 ?trans2;
@!P0 FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P1 BRA 0x390 &req={1} ?trans5;
LDS R2, [R7+0x80] &req={0} ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x40] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x20] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans4;
LDS R3, [R7+0x10] ?trans4;
LDS R8, [R7] &wr=0x0 ?trans2;
FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
STS [R7], R8 ?trans4;
LDS R2, [R7+0x8] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x4] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
@P2 BRA 0x190 ?trans6;
EXIT ?trans5;
BRA 0x3d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<128u>(float*, float*)
_Z7reduce6ILj128EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v14, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s4
s_cmpk_lt_u32 s4, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v14, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
v_add_nc_u32_e32 v1, 0x80, v14
v_add_nc_u32_e32 v4, 64, v14
s_mov_b64 s[6:7], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 64, v0
v_lshlrev_b32_e32 v2, 2, v0
v_cmp_ne_u32_e64 s1, -1, v1
v_cmp_gt_u32_e64 s0, 32, v0
v_add_nc_u32_e32 v6, 32, v14
v_cmp_ne_u32_e64 s2, -1, v14
v_add_nc_u32_e32 v8, 16, v14
v_cndmask_b32_e64 v0, 0, v1, s1
v_cndmask_b32_e64 v1, 0, s7, s1
v_cmp_ne_u32_e64 s1, -1, v4
v_add_nc_u32_e32 v10, 8, v14
v_add_nc_u32_e32 v12, 4, v14
v_add3_u32 v15, 0, v2, 0x100
v_cndmask_b32_e64 v3, 0, s7, s2
v_cndmask_b32_e64 v4, 0, v4, s1
v_cndmask_b32_e64 v5, 0, s7, s1
v_cmp_ne_u32_e64 s1, -1, v6
v_cndmask_b32_e64 v2, 0, v14, s2
v_cmp_ne_u32_e64 s2, -1, v8
v_cmp_ne_u32_e64 s3, -1, v12
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v6, 0, v6, s1
v_cndmask_b32_e64 v7, 0, s7, s1
v_cmp_ne_u32_e64 s1, -1, v10
v_cndmask_b32_e64 v8, 0, v8, s2
v_cndmask_b32_e64 v9, 0, s7, s2
v_cndmask_b32_e64 v12, 0, v12, s3
v_cndmask_b32_e64 v13, 0, s7, s3
v_cndmask_b32_e64 v10, 0, v10, s1
v_cndmask_b32_e64 v11, 0, s7, s1
.LBB2_2:
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB2_4
ds_load_b32 v16, v15
ds_load_b32 v17, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
ds_store_b32 v14, v16
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_6
flat_load_b32 v16, v[0:1] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
flat_store_b32 v[2:3], v16 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v16, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
flat_store_b32 v[2:3], v16 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v16, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
flat_store_b32 v[2:3], v16 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v16, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
flat_store_b32 v[2:3], v16 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v16, v[10:11] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
flat_store_b32 v[2:3], v16 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v16, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v17, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
flat_store_b32 v[2:3], v16 dlc
s_waitcnt_vscnt null, 0x0
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s4, 1
s_cmpk_lt_u32 s4, 0x84
s_mov_b32 s4, s1
s_cbranch_scc0 .LBB2_2
.LBB2_7:
s_endpgm
| void_reduce6_128u_ | 1,331 | 2,202 | stackv2-00000-of-00015 |
// Demangled: void reduce6<16u>(float*, float*)
Function : _Z7reduce6ILj16EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
BSSY.RECONVERGENT B0, 0x2c0 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x83, PT ?WAIT3_END_GROUP;
@P0 BRA 0x2b0 &req={0} ?trans10;
LDS R2, [R7+0x20] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x10] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x8] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans4;
LDS R3, [R7+0x4] ?trans4;
LDS R8, [R7] &wr=0x0 ?trans2;
FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
STS [R7], R8 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
@P1 BRA 0x180 ?trans6;
EXIT ?trans5;
BRA 0x2f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<16u>(float*, float*)
_Z7reduce6ILj16EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_cmpk_lt_u32 s3, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v4, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB5_5
v_add_nc_u32_e32 v2, 32, v4
v_add_nc_u32_e32 v5, 16, v4
v_add_nc_u32_e32 v6, 8, v4
v_add_nc_u32_e32 v8, 4, v4
v_cmp_ne_u32_e64 s1, -1, v4
v_cmp_ne_u32_e64 s0, -1, v2
s_mov_b64 s[4:5], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 32, v0
v_cmp_ne_u32_e64 s2, -1, v8
v_cndmask_b32_e64 v1, 0, s5, s1
v_cndmask_b32_e64 v2, 0, v2, s0
v_cndmask_b32_e64 v3, 0, s5, s0
v_cmp_ne_u32_e64 s0, -1, v5
v_cndmask_b32_e64 v0, 0, v4, s1
v_cmp_ne_u32_e64 s1, -1, v6
v_cndmask_b32_e64 v8, 0, v8, s2
v_cndmask_b32_e64 v9, 0, s5, s2
v_cndmask_b32_e64 v4, 0, v5, s0
v_cndmask_b32_e64 v5, 0, s5, s0
v_cndmask_b32_e64 v6, 0, v6, s1
v_cndmask_b32_e64 v7, 0, s5, s1
.LBB5_2:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB5_4
flat_load_b32 v10, v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v10, v10, v11
flat_store_b32 v[0:1], v10 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v10, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v10, v10, v11
flat_store_b32 v[0:1], v10 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v10, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v10, v10, v11
flat_store_b32 v[0:1], v10 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v10, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v11, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v10, v10, v11
flat_store_b32 v[0:1], v10 dlc
s_waitcnt_vscnt null, 0x0
.LBB5_4:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB5_2
.LBB5_5:
s_endpgm
| void_reduce6_16u_ | 1,045 | 1,558 | stackv2-00000-of-00015 |
// Demangled: void reduce6<1u>(float*, float*)
Function : _Z7reduce6ILj1EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R2, R2, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={0} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R2, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans2;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
EXIT ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<1u>(float*, float*)
_Z7reduce6ILj1EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v0, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_endpgm
| void_reduce6_1u_ | 545 | 546 | stackv2-00000-of-00015 |
// Demangled: void reduce6<256u>(float*, float*)
Function : _Z7reduce6ILj256EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R9.reuse, 0x3f, PT ?trans1;
ISETP.GT.U32.AND P2, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
@!P0 LDS R2, [R7+0x200] ?trans1;
BSSY.RECONVERGENT B0, 0x400 ?trans1;
ISETP.GT.U32.AND P3, PT, R0, 0x83, PT ?trans2;
@!P0 LDS R3, [R7] &req={0} &wr=0x0 ?trans2;
@!P0 FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R3, [R7+0x100] ?trans4;
@!P1 LDS R4, [R7] &req={1} &wr=0x0 ?trans2;
@!P1 FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R7], R4 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P2 BRA 0x3f0 ?trans5;
LDS R2, [R7+0x80] ?trans4;
LDS R3, [R7] &wr=0x1 ?trans2;
FADD R2, R2, R3 &req={1} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x40] ?trans4;
LDS R4, [R7] &req={0} &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x20] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans4;
LDS R3, [R7+0x10] ?trans4;
LDS R8, [R7] &wr=0x0 ?trans2;
FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
STS [R7], R8 ?trans4;
LDS R2, [R7+0x8] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x4] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
@P3 BRA 0x1a0 ?trans6;
EXIT ?trans5;
BRA 0x430;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<256u>(float*, float*)
_Z7reduce6ILj256EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v14, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s5
s_cmpk_lt_u32 s5, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v14, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
v_add_nc_u32_e32 v1, 0x80, v14
v_add_nc_u32_e32 v4, 64, v14
s_mov_b64 s[6:7], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
v_cmp_gt_u32_e64 s0, 64, v0
v_cmp_ne_u32_e64 s2, -1, v1
v_cmp_gt_u32_e64 s1, 32, v0
v_add_nc_u32_e32 v6, 32, v14
v_cmp_ne_u32_e64 s3, -1, v14
v_add_nc_u32_e32 v8, 16, v14
v_cndmask_b32_e64 v0, 0, v1, s2
v_cndmask_b32_e64 v1, 0, s7, s2
v_cmp_ne_u32_e64 s2, -1, v4
v_add_nc_u32_e32 v10, 8, v14
v_add_nc_u32_e32 v12, 4, v14
v_cndmask_b32_e64 v3, 0, s7, s3
v_cndmask_b32_e64 v2, 0, v14, s3
v_cndmask_b32_e64 v4, 0, v4, s2
v_cndmask_b32_e64 v5, 0, s7, s2
v_cmp_ne_u32_e64 s2, -1, v6
v_cmp_ne_u32_e64 s3, -1, v8
v_cmp_ne_u32_e64 s4, -1, v12
v_add_nc_u32_e32 v15, 0x200, v14
v_add_nc_u32_e32 v16, 0x100, v14
v_cndmask_b32_e64 v6, 0, v6, s2
v_cndmask_b32_e64 v7, 0, s7, s2
v_cmp_ne_u32_e64 s2, -1, v10
v_cndmask_b32_e64 v8, 0, v8, s3
v_cndmask_b32_e64 v9, 0, s7, s3
v_cndmask_b32_e64 v12, 0, v12, s4
v_cndmask_b32_e64 v13, 0, s7, s4
v_cndmask_b32_e64 v10, 0, v10, s2
v_cndmask_b32_e64 v11, 0, s7, s2
.LBB1_2:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_4
ds_load_b32 v17, v15
ds_load_b32 v18, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
ds_store_b32 v14, v17
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB1_6
ds_load_b32 v17, v16
ds_load_b32 v18, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
ds_store_b32 v14, v17
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB1_8
flat_load_b32 v17, v[0:1] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
flat_store_b32 v[2:3], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v17, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
flat_store_b32 v[2:3], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v17, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
flat_store_b32 v[2:3], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v17, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
flat_store_b32 v[2:3], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v17, v[10:11] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
flat_store_b32 v[2:3], v17 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v17, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
flat_store_b32 v[2:3], v17 dlc
s_waitcnt_vscnt null, 0x0
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b32 s2, s5, 1
s_cmpk_lt_u32 s5, 0x84
s_mov_b32 s5, s2
s_cbranch_scc0 .LBB1_2
.LBB1_9:
s_endpgm
| void_reduce6_256u_ | 1,465 | 2,346 | stackv2-00000-of-00015 |
// Demangled: void reduce6<2u>(float*, float*)
Function : _Z7reduce6ILj2EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
@!P0 LDS R2, [R7+0x4] &req={0} ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x83, PT ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans2;
@!P0 LDS R3, [R7] &wr=0x0 ?trans2;
@!P0 FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 &rd=0x0 ?trans3;
@P1 BRA 0x180 ?trans5;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<2u>(float*, float*)
_Z7reduce6ILj2EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_cmpk_lt_u32 s2, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB8_5
v_add_nc_u32_e32 v3, 4, v2
v_cmp_ne_u32_e64 s0, -1, v2
s_mov_b64 s[4:5], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 32, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s1, -1, v3
v_cndmask_b32_e64 v1, 0, s5, s0
v_cndmask_b32_e64 v0, 0, v2, s0
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v2, 0, v3, s1
v_cndmask_b32_e64 v3, 0, s5, s1
.LBB8_2:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB8_4
flat_load_b32 v4, v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v5, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v4, v4, v5
flat_store_b32 v[0:1], v4 dlc
s_waitcnt_vscnt null, 0x0
.LBB8_4:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s2, 1
s_cmpk_lt_u32 s2, 0x84
s_mov_b32 s2, s0
s_cbranch_scc0 .LBB8_2
.LBB8_5:
s_endpgm
| void_reduce6_2u_ | 816 | 1,009 | stackv2-00000-of-00015 |
// Demangled: void reduce6<32u>(float*, float*)
Function : _Z7reduce6ILj32EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
BSSY.RECONVERGENT B0, 0x300 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x83, PT ?WAIT3_END_GROUP;
@P0 BRA 0x2f0 &req={0} ?trans10;
LDS R2, [R7+0x40] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x20] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x10] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans4;
LDS R3, [R7+0x8] ?trans4;
LDS R8, [R7] &wr=0x0 ?trans2;
FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
STS [R7], R8 ?trans4;
LDS R2, [R7+0x4] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
@P1 BRA 0x180 ?trans6;
EXIT ?trans5;
BRA 0x330;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<32u>(float*, float*)
_Z7reduce6ILj32EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v5, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_cmpk_lt_u32 s3, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB4_5
v_add_nc_u32_e32 v2, 64, v5
v_add_nc_u32_e32 v4, 32, v5
v_cmp_ne_u32_e64 s0, -1, v5
s_mov_b64 s[4:5], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 32, v0
v_cmp_ne_u32_e64 s1, -1, v2
v_add_nc_u32_e32 v6, 16, v5
v_cndmask_b32_e64 v1, 0, s5, s0
v_cndmask_b32_e64 v0, 0, v5, s0
v_cmp_ne_u32_e64 s0, -1, v4
v_add_nc_u32_e32 v8, 8, v5
v_add_nc_u32_e32 v10, 4, v5
v_cndmask_b32_e64 v2, 0, v2, s1
v_cndmask_b32_e64 v3, 0, s5, s1
v_cndmask_b32_e64 v4, 0, v4, s0
v_cmp_ne_u32_e64 s1, -1, v6
v_cndmask_b32_e64 v5, 0, s5, s0
v_cmp_ne_u32_e64 s0, -1, v8
v_cmp_ne_u32_e64 s2, -1, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, 0, v6, s1
v_cndmask_b32_e64 v7, 0, s5, s1
v_cndmask_b32_e64 v8, 0, v8, s0
v_cndmask_b32_e64 v9, 0, s5, s0
v_cndmask_b32_e64 v10, 0, v10, s2
v_cndmask_b32_e64 v11, 0, s5, s2
.LBB4_2:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB4_4
flat_load_b32 v12, v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v12, v12, v13
flat_store_b32 v[0:1], v12 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v12, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v12, v12, v13
flat_store_b32 v[0:1], v12 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v12, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v12, v12, v13
flat_store_b32 v[0:1], v12 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v12, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v12, v12, v13
flat_store_b32 v[0:1], v12 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v12, v[10:11] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v12, v12, v13
flat_store_b32 v[0:1], v12 dlc
s_waitcnt_vscnt null, 0x0
.LBB4_4:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB4_2
.LBB4_5:
s_endpgm
| void_reduce6_32u_ | 1,122 | 1,797 | stackv2-00000-of-00015 |
// Demangled: void reduce6<4u>(float*, float*)
Function : _Z7reduce6ILj4EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
@!P0 LDS R2, [R7+0x8] ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x83, PT ?trans1;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans2;
@!P0 LDS R3, [R7] &req={0} &wr=0x0 ?trans2;
@!P0 FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R7], R2 ?trans4;
@!P0 LDS R3, [R7+0x4] ?trans4;
@!P0 LDS R4, [R7] &wr=0x0 ?trans2;
@!P0 FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R7], R4 &rd=0x0 ?trans1;
@P1 BRA 0x180 ?trans5;
EXIT ?trans5;
BRA 0x240;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<4u>(float*, float*)
_Z7reduce6ILj4EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_cmpk_lt_u32 s3, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v4, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v3, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v4, v1
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB7_5
v_add_nc_u32_e32 v2, 8, v3
v_add_nc_u32_e32 v4, 4, v3
v_cmp_ne_u32_e64 s0, -1, v3
s_mov_b64 s[4:5], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 32, v0
v_cmp_ne_u32_e64 s1, -1, v2
v_cmp_ne_u32_e64 s2, -1, v4
v_cndmask_b32_e64 v1, 0, s5, s0
v_cndmask_b32_e64 v0, 0, v3, s0
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v2, 0, v2, s1
v_cndmask_b32_e64 v3, 0, s5, s1
v_cndmask_b32_e64 v4, 0, v4, s2
v_cndmask_b32_e64 v5, 0, s5, s2
.LBB7_2:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB7_4
flat_load_b32 v6, v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
flat_store_b32 v[0:1], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
flat_store_b32 v[0:1], v6 dlc
s_waitcnt_vscnt null, 0x0
.LBB7_4:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB7_2
.LBB7_5:
s_endpgm
| void_reduce6_4u_ | 891 | 1,166 | stackv2-00000-of-00015 |
// Demangled: void reduce6<512u>(float*, float*)
Function : _Z7reduce6ILj512EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R8, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R3, PT, PT, R8, R8, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R3, UR6, R0 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R8, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R8, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R0, UR4, 0x2 ?trans1;
FADD R6, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R6 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R0, 0xff, PT ?trans1;
MOV R2, R8 ?WAIT12_END_GROUP;
@!P0 LDS R3, [R7+0x400] ?trans1;
ISETP.GT.U32.AND P1, PT, R0.reuse, 0x7f, PT ?trans1;
ISETP.GT.U32.AND P2, PT, R0, 0x3f, PT ?trans1;
BSSY.RECONVERGENT B0, 0x460 ?trans1;
@!P0 LDS R4, [R7] &req={0} &wr=0x0 ?trans2;
@!P0 FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R7], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R3, [R7+0x200] ?trans4;
@!P1 LDS R6, [R7] &req={1} &wr=0x0 ?trans2;
@!P1 FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R7], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x1f, PT ?WAIT5_END_GROUP;
@!P2 LDS R3, [R7+0x100] ?trans4;
@!P2 LDS R8, [R7] &wr=0x0 ?trans2;
@!P2 FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
@!P2 STS [R7], R8 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P2, PT, R2, 0x83, PT ?WAIT5_END_GROUP;
@P1 BRA 0x450 ?trans8;
LDS R3, [R7+0x80] ?trans4;
LDS R4, [R7] &wr=0x1 ?trans2;
FADD R4, R3, R4 &req={1} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x40] ?trans4;
LDS R6, [R7] &wr=0x1 ?trans2;
FADD R6, R3, R6 &req={1} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans4;
LDS R3, [R7+0x20] ?trans4;
LDS R8, [R7] &req={0} &wr=0x0 ?trans2;
FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
STS [R7], R8 ?trans4;
LDS R3, [R7+0x10] ?trans4;
LDS R10, [R7] &wr=0x0 ?trans2;
FADD R10, R3, R10 &req={0} ?WAIT5_END_GROUP;
STS [R7], R10 ?trans4;
LDS R3, [R7+0x8] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x4] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R2, RZ, 0x1, R2 ?trans1;
@P2 BRA 0x180 ?trans6;
EXIT ?trans5;
BRA 0x490;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<512u>(float*, float*)
_Z7reduce6ILj512EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v14, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s6
s_cmpk_lt_u32 s6, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v14, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
v_add_nc_u32_e32 v1, 0x80, v14
v_add_nc_u32_e32 v4, 64, v14
s_mov_b64 s[8:9], src_shared_base
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
v_cmp_gt_u32_e64 s0, 0x80, v0
v_cmp_ne_u32_e64 s3, -1, v1
v_cmp_gt_u32_e64 s1, 64, v0
v_cmp_gt_u32_e64 s2, 32, v0
v_add_nc_u32_e32 v6, 32, v14
v_cmp_ne_u32_e64 s4, -1, v14
v_cndmask_b32_e64 v0, 0, v1, s3
v_cndmask_b32_e64 v1, 0, s9, s3
v_cmp_ne_u32_e64 s3, -1, v4
v_add_nc_u32_e32 v8, 16, v14
v_add_nc_u32_e32 v10, 8, v14
v_add_nc_u32_e32 v12, 4, v14
v_cndmask_b32_e64 v3, 0, s9, s4
v_cndmask_b32_e64 v4, 0, v4, s3
v_cndmask_b32_e64 v5, 0, s9, s3
v_cmp_ne_u32_e64 s3, -1, v6
v_cndmask_b32_e64 v2, 0, v14, s4
v_cmp_ne_u32_e64 s4, -1, v8
v_cmp_ne_u32_e64 s5, -1, v12
v_add_nc_u32_e32 v15, 0x400, v14
v_cndmask_b32_e64 v6, 0, v6, s3
v_cndmask_b32_e64 v7, 0, s9, s3
v_cmp_ne_u32_e64 s3, -1, v10
v_add_nc_u32_e32 v16, 0x200, v14
v_add_nc_u32_e32 v17, 0x100, v14
v_cndmask_b32_e64 v8, 0, v8, s4
v_cndmask_b32_e64 v9, 0, s9, s4
v_cndmask_b32_e64 v10, 0, v10, s3
v_cndmask_b32_e64 v11, 0, s9, s3
v_cndmask_b32_e64 v12, 0, v12, s5
v_cndmask_b32_e64 v13, 0, s9, s5
.LBB0_2:
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
ds_load_b32 v18, v15
ds_load_b32 v19, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
ds_store_b32 v14, v18
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_6
ds_load_b32 v18, v16
ds_load_b32 v19, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
ds_store_b32 v14, v18
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_8
ds_load_b32 v18, v17
ds_load_b32 v19, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
ds_store_b32 v14, v18
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
flat_load_b32 v18, v[0:1] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v19, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
flat_store_b32 v[2:3], v18 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v18, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v19, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
flat_store_b32 v[2:3], v18 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v18, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v19, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
flat_store_b32 v[2:3], v18 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v18, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v19, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
flat_store_b32 v[2:3], v18 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v18, v[10:11] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v19, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
flat_store_b32 v[2:3], v18 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v18, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v19, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v18, v18, v19
flat_store_b32 v[2:3], v18 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_lshr_b32 s3, s6, 1
s_cmpk_lt_u32 s6, 0x84
s_mov_b32 s6, s3
s_cbranch_scc0 .LBB0_2
.LBB0_11:
s_endpgm
| void_reduce6_512u_ | 1,596 | 2,529 | stackv2-00000-of-00015 |
// Demangled: void reduce6<64u>(float*, float*)
Function : _Z7reduce6ILj64EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
BSSY.RECONVERGENT B0, 0x340 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x83, PT ?WAIT3_END_GROUP;
@P0 BRA 0x330 &req={0} ?trans10;
LDS R2, [R7+0x80] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x40] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x20] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 ?trans4;
LDS R3, [R7+0x10] ?trans4;
LDS R8, [R7] &wr=0x0 ?trans2;
FADD R8, R3, R8 &req={0} ?WAIT5_END_GROUP;
STS [R7], R8 ?trans4;
LDS R2, [R7+0x8] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x4] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
@P1 BRA 0x180 ?trans6;
EXIT ?trans5;
BRA 0x370;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<64u>(float*, float*)
_Z7reduce6ILj64EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v7, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_cmpk_lt_u32 s3, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v7, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_5
v_add_nc_u32_e32 v2, 0x80, v7
v_add_nc_u32_e32 v4, 64, v7
v_add_nc_u32_e32 v6, 32, v7
s_mov_b64 s[4:5], src_shared_base
v_cmp_ne_u32_e64 s1, -1, v7
v_cmp_ne_u32_e64 s0, -1, v2
v_cmp_ne_u32_e64 s2, -1, v4
v_add_nc_u32_e32 v8, 16, v7
v_add_nc_u32_e32 v10, 8, v7
v_add_nc_u32_e32 v12, 4, v7
v_cndmask_b32_e64 v2, 0, v2, s0
v_cndmask_b32_e64 v3, 0, s5, s0
v_cmp_ne_u32_e64 s0, -1, v6
v_cmp_gt_u32_e32 vcc_lo, 32, v0
v_cndmask_b32_e64 v1, 0, s5, s1
v_cndmask_b32_e64 v0, 0, v7, s1
v_cndmask_b32_e64 v4, 0, v4, s2
v_cndmask_b32_e64 v5, 0, s5, s2
v_cndmask_b32_e64 v6, 0, v6, s0
v_cmp_ne_u32_e64 s1, -1, v8
v_cndmask_b32_e64 v7, 0, s5, s0
v_cmp_ne_u32_e64 s0, -1, v10
v_cmp_ne_u32_e64 s2, -1, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, 0, v8, s1
v_cndmask_b32_e64 v9, 0, s5, s1
v_cndmask_b32_e64 v10, 0, v10, s0
v_cndmask_b32_e64 v11, 0, s5, s0
v_cndmask_b32_e64 v12, 0, v12, s2
v_cndmask_b32_e64 v13, 0, s5, s2
.LBB3_2:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB3_4
flat_load_b32 v14, v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v14, v14, v15
flat_store_b32 v[0:1], v14 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v14, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v14, v14, v15
flat_store_b32 v[0:1], v14 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v14, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v14, v14, v15
flat_store_b32 v[0:1], v14 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v14, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v14, v14, v15
flat_store_b32 v[0:1], v14 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v14, v[10:11] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v14, v14, v15
flat_store_b32 v[0:1], v14 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v14, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v14, v14, v15
flat_store_b32 v[0:1], v14 dlc
s_waitcnt_vscnt null, 0x0
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB3_2
.LBB3_5:
s_endpgm
| void_reduce6_64u_ | 1,183 | 2,003 | stackv2-00000-of-00015 |
// Demangled: void reduce6<8u>(float*, float*)
Function : _Z7reduce6ILj8EEvPfS0_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans7;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R6, R6, RZ &req={2} ?WAIT5_END_GROUP;
IMAD R3, R0, UR6, R9 &req={1} ?WAIT5_END_GROUP;
IADD3 R7, PT, PT, R3.reuse, R6, RZ ?trans1;
IMAD.WIDE.U32 R2, R3, 0x4, R4 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GE.U32.AND P0, PT, R6, 0x42, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R7, R9, UR4, 0x2 ?trans1;
FADD R0, R2, R5 &req={2} ?WAIT5_END_GROUP;
STS [R7], R0 &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 EXIT &req={0} ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0x1f, PT ?trans1;
MOV R0, R6 &req={1} ?WAIT12_END_GROUP;
BSSY.RECONVERGENT B0, 0x280 ?trans1;
ISETP.GT.U32.AND P1, PT, R0, 0x83, PT ?WAIT3_END_GROUP;
@P0 BRA 0x270 &req={0} ?trans10;
LDS R2, [R7+0x10] ?trans4;
LDS R3, [R7] &wr=0x0 ?trans2;
FADD R2, R2, R3 &req={0} ?WAIT5_END_GROUP;
STS [R7], R2 ?trans4;
LDS R3, [R7+0x8] ?trans4;
LDS R4, [R7] &wr=0x0 ?trans2;
FADD R4, R3, R4 &req={0} ?WAIT5_END_GROUP;
STS [R7], R4 ?trans4;
LDS R3, [R7+0x4] ?trans4;
LDS R6, [R7] &wr=0x0 ?trans2;
FADD R6, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
SHF.R.U32.HI R0, RZ, 0x1, R0 ?trans1;
@P1 BRA 0x180 ?trans6;
EXIT ?trans5;
BRA 0x2b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: void reduce6<8u>(float*, float*)
_Z7reduce6ILj8EEvPfS0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_cmpk_lt_u32 s3, 0x42
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v4, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v3, v1
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB6_5
v_add_nc_u32_e32 v2, 16, v4
v_add_nc_u32_e32 v5, 8, v4
v_add_nc_u32_e32 v6, 4, v4
s_mov_b64 s[4:5], src_shared_base
v_cmp_ne_u32_e64 s1, -1, v4
v_cmp_ne_u32_e64 s0, -1, v2
v_cmp_ne_u32_e64 s2, -1, v5
v_cmp_gt_u32_e32 vcc_lo, 32, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v1, 0, s5, s1
v_cndmask_b32_e64 v2, 0, v2, s0
v_cndmask_b32_e64 v3, 0, s5, s0
v_cmp_ne_u32_e64 s0, -1, v6
v_cndmask_b32_e64 v0, 0, v4, s1
v_cndmask_b32_e64 v4, 0, v5, s2
v_cndmask_b32_e64 v5, 0, s5, s2
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v6, 0, v6, s0
v_cndmask_b32_e64 v7, 0, s5, s0
.LBB6_2:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB6_4
flat_load_b32 v8, v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v8, v8, v9
flat_store_b32 v[0:1], v8 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v8, v8, v9
flat_store_b32 v[0:1], v8 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v8, v[6:7] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v8, v8, v9
flat_store_b32 v[0:1], v8 dlc
s_waitcnt_vscnt null, 0x0
.LBB6_4:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmpk_lt_u32 s3, 0x84
s_mov_b32 s3, s0
s_cbranch_scc0 .LBB6_2
.LBB6_5:
s_endpgm
| void_reduce6_8u_ | 983 | 1,390 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R9, 0x1f, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 32, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 542 | 548 | stackv2-00000-of-00015 |
// Demangled: kernel(uint4*)
Function : _Z6kernelP5uint4
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R4, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
MOV R7, 0x1 ?trans1;
HFMA2 R6, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x10, R2 &req={0} ?trans1;
MOV R5, 0x1 ?WAIT5_END_GROUP;
STG.E.128 desc[UR4][R2.64], R4 &req={1} ?trans1;
EXIT ?trans5;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(HIP_vector_type<unsigned int, 4u>*)
_Z6kernelP15HIP_vector_typeIjLj4EE:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 4, v0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v3, v1
v_mov_b32_e32 v4, v1
s_waitcnt lgkmcnt(0)
global_store_b128 v0, v[1:4], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 345 | 180 | stackv2-00000-of-00015 |
// Demangled: device_add(int*, int*, int*)
Function : _Z10device_addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_CTAID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: device_add(int*, int*, int*)
_Z10device_addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| device_add | 427 | 338 | stackv2-00000-of-00015 |
// Demangled: VecAdd(float*, float*, float*)
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_CTAID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R9, R9, UR6, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R9.reuse, 0x4, R4 &req={3} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={4} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: VecAdd(float*, float*, float*)
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| VecAdd | 496 | 496 | stackv2-00000-of-00015 |
// Demangled: isSubvectorStartingOnIndex(int*, int, int*, int, bool*)
Function : _Z26isSubvectorStartingOnIndexPiiS_iPb
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x398] &wr=0x2 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x220 ?trans1;
MOV R0, 0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x4 ?trans1;
LDCU.64 UR10, c[0x0][0x390] &wr=0x0 ?trans1;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 &req={2} ?WAIT6_END_GROUP;
IADD.64 R4, R2, UR4 &req={1} ?WAIT6_END_GROUP;
ISETP.GT.U64.AND P0, PT, R4, R2, PT ?WAIT14_END_GROUP;
@!P0 BRA 0x210 &req={4,3,0} ?trans5;
LDCU UR5, c[0x0][0x388] &wr=0x0 ?trans1;
MOV.64 R8, R2 ?trans2;
USHF.R.S32.HI UR4, URZ, 0x1f, UR5 &req={0} ?trans2;
MOV R6, UR5 ?WAIT4_END_GROUP;
MOV R7, UR4 ?WAIT7_END_GROUP;
ISETP.GE.U64.AND P0, PT, R8, R6, PT ?WAIT3_END_GROUP;
PRMT R0, RZ, 0x7610, R0 ?WAIT11_END_GROUP;
@P0 BRA 0x210 ?trans5;
SHF.L.U64.HI R11, R8.reuse, 0x2, R9 ?trans1;
IMAD.SHL.U32 R10, R8, 0x4, RZ ?WAIT5_END_GROUP;
IADD.64 R12, R10.reuse, UR8 ?trans2;
IADD.64 R10, R10, UR10 ?WAIT5_END_GROUP;
LDG.E R12, desc[UR6][R12.64] &wr=0x2 ?trans4;
LDG.E R11, desc[UR6][R10.64] &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R12, R11, PT &req={2} ?WAIT13_END_GROUP;
@P0 BRA 0x210 ?trans5;
IADD.64 R8, R8, 0x1 ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P0, PT, R8, R4, PT ?WAIT14_END_GROUP;
@P0 BRA 0x120 ?trans5;
HFMA2 R0, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.64 UR4, c[0x0][0x3a0] &wr=0x0 ?trans2;
IADD.64 R2, R2, UR4 &req={0} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR6][R2.64], R0 ?trans1;
EXIT ?trans5;
BRA 0x260;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: isSubvectorStartingOnIndex(int*, int, int*, int, bool*)
_Z26isSubvectorStartingOnIndexPiiS_iPb:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_add_co_u32 v2, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, null, s3, 0, s2
v_cmp_gt_u32_e64 s2, s4, v0
v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1]
v_cmp_le_u64_e64 s6, v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_add_co_u32 v4, s5, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, null, 0, 0, s5
s_ashr_i32 s5, s4, 31
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s2, s2, v1
v_add_co_ci_u32_e64 v7, null, s3, 0, s2
v_add_co_u32 v8, s2, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, null, s9, 0, s2
s_mov_b32 s8, 0
.LBB0_2:
global_load_b32 v1, v[8:9], off
global_load_b32 v10, v[6:7], off
s_and_not1_b32 s11, s11, exec_lo
s_or_b32 s10, s10, exec_lo
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v1, v10
s_cbranch_execz .LBB0_4
v_cmp_ge_u64_e32 vcc_lo, v[4:5], v[2:3]
v_cmp_le_u64_e64 s2, s[4:5], v[4:5]
v_add_co_u32 v4, s3, v4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s3, 0, v5, s3
s_and_not1_b32 s10, s10, exec_lo
s_or_b32 s3, s2, vcc_lo
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
v_add_co_u32 v8, s2, v8, 4
v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
s_and_not1_b32 s2, s11, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s11, s2, s11
s_or_b32 s10, s10, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s10
s_or_b32 s8, s2, s8
s_and_not1_b32 s2, s9, exec_lo
s_and_b32 s3, s11, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s2, s3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s6, exec_lo
s_and_b32 s3, s9, exec_lo
s_or_b32 s6, s2, s3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_load_b64 s[0:1], s[0:1], 0x20
v_cndmask_b32_e64 v2, 0, 1, s6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| isSubvectorStartingOnIndex | 969 | 1,520 | stackv2-00000-of-00015 |
// Demangled: parallel_scan(float*, float*, int)
Function : _Z13parallel_scanPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
S2UR UR5, SR_CgaCtaId &wr=0x3 ?trans1;
LDCU UR8, c[0x0][0x390] &wr=0x4 ?trans1;
ISETP.NE.AND P0, PT, R9, RZ, PT &req={1} ?WAIT13_END_GROUP;
@P0 LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
@P0 IADD3 R5, PT, PT, R9, -0x1, RZ ?WAIT5_END_GROUP;
@P0 IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT5_END_GROUP;
@P0 LDG.E R0, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
MOV R11, UR8 &req={4} ?trans1;
UMOV UR4, 0x400 ?trans1;
MOV R4, RZ ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={3} ?trans2;
ISETP.GE.AND P0, PT, R11, 0x2, PT ?WAIT4_END_GROUP;
LEA R5, R9, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R5], R0 &req={2} &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x350 &req={0} ?trans5;
BSSY.RECONVERGENT B0, 0x350 ?trans1;
MOV R0, RZ &req={1} ?trans1;
MOV R2, 0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x0 ?trans6;
ISETP.GE.AND P0, PT, R9, R2, PT ?trans1;
BSSY.RECONVERGENT B1, 0x2f0 ?trans1;
IADD3 R4, PT, PT, -R0, 0x1, RZ ?WAIT11_END_GROUP;
@!P0 BRA 0x270 ?trans5;
MOV R11, UR5 &req={0} ?WAIT5_END_GROUP;
IMAD R3, R0, R11.reuse, R9 ?trans2;
IMAD R0, R4, R11, RZ ?WAIT3_END_GROUP;
IADD3 R3, PT, PT, R3, -R2, RZ ?trans1;
IMAD R0, R0, 0x4, R5 ?WAIT3_END_GROUP;
LEA R3, R3, UR4, 0x2 ?trans2;
LDS R6, [R0] ?trans4;
LDS R3, [R3] &wr=0x0 ?trans2;
FADD R7, R3, R6 &req={0} ?WAIT5_END_GROUP;
STS [R0], R7 &rd=0x0 ?trans1;
BRA 0x2e0 ?trans5;
MOV R11, UR5 &req={0} ?WAIT5_END_GROUP;
IMAD R0, R0, R11.reuse, RZ ?trans2;
IMAD R6, R4, R11, RZ ?trans2;
IMAD R0, R0, 0x4, R5.reuse ?trans2;
IMAD R3, R6, 0x4, R5 ?WAIT4_END_GROUP;
LDS R0, [R0] &wr=0x0 ?trans4;
STS [R3], R0 &req={0} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
IADD3 R2, PT, PT, R2, R2, RZ ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
MOV R0, R4 &req={1,0} ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R2, R11, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x180 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
IMAD R4, R4, R11, RZ ?trans1;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans3;
IMAD R4, R4, 0x4, R5 ?WAIT5_END_GROUP;
LDS R5, [R4] &req={1} &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x3c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: parallel_scan(float*, float*, int)
_Z13parallel_scanPfS_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[6:7] offset:-4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s0, s[0:1], 0x10
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s0, 2
s_cbranch_scc1 .LBB0_9
s_mov_b32 s1, 1
.LBB0_4:
s_mov_b32 s3, s2
s_sub_i32 s2, 1, s2
s_mul_i32 s3, s3, s0
s_mul_i32 s6, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_lshl_add_u32 v3, s6, 2, v2
s_mov_b32 s6, exec_lo
v_cmpx_le_i32_e64 s1, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v4, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s1, v4
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
ds_load_b32 v5, v3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v5
ds_store_b32 v3, v4
.LBB0_6:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v4, s3, 2, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s1, s1, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s1, s0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_9:
s_mul_i32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_lshl_add_u32 v0, s0, 2, v2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| parallel_scan | 1,332 | 861 | stackv2-00000-of-00015 |
// Demangled: stencilKernel(unsigned char*, int, unsigned char*)
Function : _Z13stencilKernelPhiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x388] &wr=0x2 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, -0x3, URZ &req={2} ?trans1;
IMAD R2, R2, UR5, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR4, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R2, 0x3, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD.SHL.U32 R2, R2, 0x4, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
IADD3 R4, PT, PT, R2.reuse, -0xc, RZ ?trans2;
IADD3 R12, PT, PT, R2.reuse, -0x7, RZ ?trans2;
IADD3 R14, PT, PT, R2, -0x6, RZ ?WAIT2_END_GROUP;
IADD3 R10, PT, PT, R2.reuse, -0x8, RZ ?trans2;
IADD3 R8, PT, PT, R2.reuse, -0xa, RZ ?trans2;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
LDCU.128 UR8, c[0x3][URZ] &wr=0x2 ?trans1;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?trans2;
SHF.R.S32.HI R15, RZ, 0x1f, R14 ?trans2;
IADD3 R16, PT, PT, R2, -0x5, RZ ?WAIT2_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans1;
IADD.64 R4, R4, UR6 &req={0} ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R2, -0xb, RZ ?trans2;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans1;
IADD.64 R36, R12, UR6 ?trans2;
IADD.64 R14, R14, UR6 ?trans2;
IADD.64 R10, R10, UR6 ?WAIT3_END_GROUP;
IADD3 R12, PT, PT, R2, -0x4, RZ ?trans2;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ?trans1;
LDG.E.U8 R33, desc[UR4][R4.64] &req={1} &rd=0x0 &wr=0x3 ?trans1;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans1;
IADD.64 R8, R8, UR6 ?trans2;
IADD.64 R26, R16, UR6 ?trans2;
LDG.E.U8 R32, desc[UR4][R14.64] &wr=0x2 ?trans1;
SHF.R.S32.HI R13, RZ, 0x1f, R12 ?trans1;
IADD.64 R6, R6, UR6 ?WAIT3_END_GROUP;
IADD3 R4, PT, PT, R2.reuse, -0x9, RZ &req={0} ?trans1;
LDG.E.U8 R34, desc[UR4][R10.64] &rd=0x0 &wr=0x4 ?trans1;
IADD3 R16, PT, PT, R2.reuse, -0x3, RZ ?trans2;
IADD3 R18, PT, PT, R2, -0x2, RZ ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans1;
LDG.E.U8 R9, desc[UR4][R8.64] &wr=0x5 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
IADD.64 R22, R12, UR6 ?trans2;
LDG.E.U8 R35, desc[UR4][R6.64] &rd=0x1 &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R2, -0x1, RZ &req={0} ?WAIT2_END_GROUP;
SHF.R.S32.HI R17, RZ, 0x1f, R16 ?trans1;
IADD.64 R4, R4, UR6 ?trans2;
LDG.E.U8 R36, desc[UR4][R36.64] &wr=0x3 ?trans1;
SHF.R.S32.HI R19, RZ, 0x1f, R18 ?trans2;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?trans1;
IADD.64 R6, R2, UR6 &req={1} ?trans2;
LDG.E.U8 R26, desc[UR4][R26.64] &wr=0x3 ?trans1;
IADD.64 R24, R16, UR6 ?WAIT2_END_GROUP;
IADD.64 R28, R18, UR6 ?trans2;
LDG.E.U8 R8, desc[UR4][R22.64] &wr=0x3 ?trans1;
IADD.64 R30, R10, UR6 ?trans2;
LDCU.64 UR6, c[0x0][0x390] &wr=0x0 ?trans1;
LDG.E.U8 R0, desc[UR4][R4.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E.U8 R13, desc[UR4][R6.64] &wr=0x3 ?trans4;
LDG.E.U8 R10, desc[UR4][R24.64] &wr=0x3 ?trans1;
LDC.64 R4, c[0x3][0x18] &req={1} &wr=0x1 ?trans3;
LDG.E.U8 R11, desc[UR4][R28.64] &rd=0x1 &wr=0x3 ?trans4;
LDG.E.U8 R12, desc[UR4][R30.64] &rd=0x0 &wr=0x3 ?trans4;
LDG.E.U8 R17, desc[UR4][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E.U8 R14, desc[UR4][R6.64+0x1] &wr=0x3 ?trans4;
LDG.E.U8 R15, desc[UR4][R6.64+0x2] &wr=0x3 ?trans4;
LDG.E.U8 R16, desc[UR4][R6.64+0x3] &wr=0x3 ?trans4;
LDG.E.U8 R18, desc[UR4][R6.64+0x8] &wr=0x3 ?trans4;
LDG.E.U8 R19, desc[UR4][R6.64+0x5] &wr=0x3 ?trans4;
LDG.E.U8 R21, desc[UR4][R6.64+0x6] &wr=0x3 ?trans4;
LDG.E.U8 R23, desc[UR4][R6.64+0x7] &wr=0x3 ?trans4;
LDG.E.U8 R25, desc[UR4][R6.64+0xc] &wr=0x3 ?trans4;
LDG.E.U8 R20, desc[UR4][R6.64+0x9] &wr=0x3 ?trans4;
LDG.E.U8 R22, desc[UR4][R6.64+0xa] &wr=0x3 ?trans4;
LDG.E.U8 R24, desc[UR4][R6.64+0xb] &wr=0x3 ?trans4;
LDG.E.U8 R27, desc[UR4][R6.64+0xd] &wr=0x3 ?trans4;
LDG.E.U8 R29, desc[UR4][R6.64+0xe] &wr=0x3 ?trans4;
LDG.E.U8 R31, desc[UR4][R6.64+0xf] &rd=0x0 &wr=0x3 ?trans1;
IABS R28, R5 &req={1} ?WAIT4_END_GROUP;
I2F.RP R30, R28 &req={0} &wr=0x0 ?trans1;
LDC.64 R6, c[0x3][0x10] &wr=0x1 ?trans1;
MUFU.RCP R30, R30 &req={0} &wr=0x0 ?trans1;
IADD.64 R2, R2, UR6 ?trans2;
IMAD R32, R32, UR9, RZ &req={2} ?trans2;
IMAD R34, R34, UR9, RZ &req={4} ?trans2;
IMAD R32, R9, UR8, R32 &req={5} ?trans1;
IADD3 R9, PT, PT, R30, 0xffffffe, RZ &req={0} ?trans1;
IMAD R33, R33, UR8, R34 &req={3} ?WAIT5_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R9 &wr=0x0 ?trans1;
IMAD R36, R36, UR9, RZ ?trans2;
IMAD R37, R26, UR9, RZ ?trans2;
IMAD R35, R35, UR8, R36 ?trans2;
IMAD R8, R8, UR10, R33 ?trans2;
IMAD R37, R0, UR8, R37 ?trans2;
IMAD R8, R13, UR11, R8 ?WAIT2_END_GROUP;
IMAD R35, R10, UR10, R35 ?trans2;
IMAD R32, R11, UR10, R32 ?trans2;
IMAD R37, R12, UR10, R37 ?trans2;
IMAD R8, R17, R6, R8 &req={1} ?trans2;
IMAD R14, R14, UR11, R35 ?trans2;
IMAD R15, R15, UR11, R32 ?WAIT2_END_GROUP;
IMAD R16, R16, UR11, R37 ?trans1;
IADD3 R11, PT, PT, RZ, -R9, RZ &req={0} ?trans1;
IMAD R0, R18, R7, R8 ?trans2;
IMAD R14, R19, R6.reuse, R14 ?trans2;
IMAD R15, R21, R6.reuse, R15 ?trans2;
IMAD R16, R23, R6, R16 ?trans2;
IMAD R0, R25, R4, R0 ?WAIT2_END_GROUP;
HFMA2 R8, -RZ, RZ, 0, 0 ?trans2;
IMAD R6, R20, R7.reuse, R14 ?trans2;
IMAD R10, R22, R7.reuse, R15 ?trans2;
IMAD R16, R24, R7, R16 ?trans2;
IMAD R7, R11, R28, RZ ?trans1;
IABS R11, R0 ?trans1;
IMAD R6, R27, R4, R6 ?WAIT2_END_GROUP;
IMAD.HI.U32 R8, R9, R7, R8 ?trans2;
MOV R7, R11 ?trans1;
IABS R13, R6 ?trans1;
IMAD R10, R29, R4.reuse, R10 ?trans2;
IMAD R16, R31, R4, R16 ?trans2;
IMAD.HI.U32 R4, R8, R7, RZ ?trans1;
IABS R15, R10 ?WAIT3_END_GROUP;
IMAD.HI.U32 R9, R8, R13, RZ ?trans1;
IABS R19, R16 ?trans2;
IADD3 R11, PT, PT, -R4, RZ, RZ ?trans2;
IADD3 R14, PT, PT, -R9, RZ, RZ ?trans1;
IMAD.HI.U32 R12, R8, R15, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, R8, R19, RZ ?WAIT4_END_GROUP;
IMAD R7, R28.reuse, R11, R7 ?trans2;
IMAD R11, R28, R14, R13 ?trans1;
IADD3 R17, PT, PT, -R12, RZ, RZ ?trans2;
IADD3 R14, PT, PT, -R8, RZ, RZ ?trans1;
ISETP.GT.U32.AND P1, PT, R28.reuse, R7, PT ?trans1;
ISETP.GT.U32.AND P3, PT, R28.reuse, R11, PT ?trans1;
IMAD R13, R28.reuse, R17, R15 ?trans2;
IMAD R15, R28, R14, R19 ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P5, PT, R28.reuse, R13, PT ?trans2;
ISETP.GT.U32.AND P6, PT, R28, R15, PT ?WAIT4_END_GROUP;
@!P1 IADD3 R7, PT, PT, R7, -R28.reuse, RZ ?trans2;
@!P3 IADD3 R11, PT, PT, R11, -R28, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P4, PT, R7, R28.reuse, PT ?trans2;
ISETP.GE.U32.AND P2, PT, R11, R28.reuse, PT ?trans1;
@!P5 IADD3 R13, PT, PT, R13, -R28.reuse, RZ ?trans2;
@!P6 IADD3 R15, PT, PT, R15, -R28.reuse, RZ ?trans2;
@!P1 IADD3 R4, PT, PT, R4, 0x1, RZ ?trans2;
LOP3.LUT R0, R0, R5.reuse, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R6, R6, R5, RZ, 0x3c, !PT ?trans1;
ISETP.GE.U32.AND P1, PT, R13, R28, PT ?trans1;
@!P3 IADD3 R9, PT, PT, R9, 0x1, RZ ?WAIT2_END_GROUP;
LOP3.LUT R10, R10, R5.reuse, RZ, 0x3c, !PT ?trans1;
ISETP.GE.U32.AND P3, PT, R15, R28, PT ?trans1;
LOP3.LUT R16, R16, R5, RZ, 0x3c, !PT ?trans2;
@!P6 IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
@P4 IADD3 R4, PT, PT, R4, 0x1, RZ ?trans1;
ISETP.GE.AND P0, PT, R0, RZ, PT ?trans1;
ISETP.GE.AND P6, PT, R6, RZ, PT ?trans1;
ISETP.GE.AND P4, PT, R10, RZ, PT ?trans1;
@P2 IADD3 R9, PT, PT, R9, 0x1, RZ ?trans1;
ISETP.GE.AND P2, PT, R16, RZ, PT ?trans1;
@!P5 IADD3 R12, PT, PT, R12, 0x1, RZ ?WAIT2_END_GROUP;
@P3 IADD3 R8, PT, PT, R8, 0x1, RZ ?trans2;
@P1 IADD3 R12, PT, PT, R12, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R5, RZ, PT ?trans1;
LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ?trans2;
@!P0 IADD3 R4, PT, PT, -R4, RZ, RZ ?trans2;
@!P6 IADD3 R9, PT, PT, -R9, RZ, RZ ?trans2;
@!P4 IADD3 R12, PT, PT, -R12, RZ, RZ ?WAIT2_END_GROUP;
@!P2 IADD3 R8, PT, PT, -R8, RZ, RZ ?trans1;
SEL R7, R5.reuse, R4, !P1 ?trans1;
SEL R9, R5.reuse, R9, !P1 ?trans1;
SEL R11, R5.reuse, R12, !P1 ?trans2;
SEL R5, R5, R8, !P1 ?trans1;
STG.E.U8 desc[UR4][R2.64], R7 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x1], R9 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x2], R11 ?trans4;
STG.E.U8 desc[UR4][R2.64+0x3], R5 ?trans1;
EXIT ?trans5;
BRA 0xb50;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: stencilKernel(unsigned char*, int, unsigned char*)
_Z13stencilKernelPhiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s6, -3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -3
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 2, v4
v_cmp_gt_i32_e64 s2, s3, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s12, 0
v_lshl_add_u32 v5, v4, 2, -12
s_mov_b32 s13, s12
s_mov_b32 s14, s12
s_mov_b32 s15, s12
v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
.LBB0_2:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL6weight@rel32@lo+16
s_addc_u32 s3, s3, _ZL6weight@rel32@hi+24
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v7, 31, v5
s_lshl_b64 s[4:5], s[6:7], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s8, v5
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_load_b32 s5, s[2:3], 0x0
s_mov_b64 s[10:11], 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v7, vcc_lo
s_cmp_eq_u32 s10, 1
s_cselect_b32 vcc_lo, -1, 0
global_load_u8 v11, v[8:9], off
v_cndmask_b32_e32 v8, v0, v1, vcc_lo
s_cmp_eq_u32 s10, 2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s10, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, v8, v2, s2
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s10, 0
s_cselect_b32 s4, -1, 0
v_cndmask_b32_e64 v8, v8, v3, s3
s_add_u32 s10, s10, 1
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s10, 4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[9:10], null, s5, v11, v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v9, s3
v_cndmask_b32_e64 v2, v2, v9, s2
v_cndmask_b32_e32 v1, v1, v9, vcc_lo
v_cndmask_b32_e64 v0, v0, v9, s4
s_cbranch_scc1 .LBB0_3
v_add_nc_u32_e32 v5, 4, v5
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 4
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b64 s[0:1], 0
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
v_cndmask_b32_e32 v6, v0, v1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v6, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v6, v6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshrrev_b32_e32 v7, 28, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, v6, v7
v_add_co_u32 v6, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
v_lshrrev_b32_e32 v8, 4, v8
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 4
global_store_b8 v[6:7], v8, off
s_cbranch_scc1 .LBB0_6
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| stencilKernel | 4,706 | 1,929 | stackv2-00000-of-00015 |
// Demangled: MultiplocarMatrices(int*, int*, int*, int)
Function : _Z19MultiplocarMatricesPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R8, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R28, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x3 ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
S2R R9, SR_TID.Y &wr=0x4 ?trans4;
S2UR UR5, SR_CTAID.Y &wr=0x5 ?trans8;
S2UR UR4, SR_CTAID.X &wr=0x0 ?trans1;
IADD3 R14, PT, PT, R8, R8, RZ &req={1} ?WAIT2_END_GROUP;
IADD3 R3, PT, PT, R8, -0x1, RZ ?WAIT3_END_GROUP;
IMAD R0, R14, UR5, RZ &req={5} ?WAIT5_END_GROUP;
IADD3 R16, PT, PT, R0, R3, RZ ?trans1;
UIADD3 UR4, UPT, UPT, UR4, UR4, URZ &req={0} ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R16, R3, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x340 &req={4,3,2} ?trans5;
S2UR UR7, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR5, 0x400 ?trans1;
IMAD R15, R9, R8, R28 ?trans1;
UIADD3 UR6, UPT, UPT, UR5, 0x10, URZ ?trans1;
MOV R21, RZ ?trans1;
MOV R22, UR4 ?trans1;
MOV R23, R0 ?trans2;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
ULEA UR5, UR7, UR5, 0x18 &req={0} ?trans1;
ULEA UR6, UR7, UR6, 0x18 ?WAIT5_END_GROUP;
LEA R17, R9, UR5, 0x3 ?trans2;
LEA R20, R28, UR6, 0x2 ?WAIT3_END_GROUP;
IMAD R18, R28, 0x4, R17 ?trans2;
IMAD R19, R9, 0x8, R20 ?WAIT7_END_GROUP;
IADD3 R11, PT, PT, R15.reuse, R23, RZ ?trans2;
IADD3 R13, PT, PT, R15, R22, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R10, R11, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R12, R13, 0x4, R4 &req={2} ?trans2;
LDG.E R10, desc[UR8][R10.64] &wr=0x2 ?trans4;
LDG.E R12, desc[UR8][R12.64] &wr=0x3 ?trans1;
IADD3 R23, PT, PT, R23, 0x2, RZ ?trans2;
IADD3 R22, PT, PT, R14, R22, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R23, R16, PT ?trans1;
I2FP.F32.S32 R25, R10 &req={2} ?trans2;
I2FP.F32.S32 R24, R12 &req={3} ?WAIT3_END_GROUP;
STS [R18], R25 ?trans4;
STS [R19], R24 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R26, [R20] ?trans4;
LDS.64 R6, [R17] &wr=0x0 ?trans4;
LDS R27, [R20+0x8] &wr=0x1 ?trans1;
FFMA R6, R6, R26, R21 &req={0} ?WAIT4_END_GROUP;
FFMA R21, R27, R7, R6 &req={1} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0x1e0 ?trans5;
F2I.TRUNC.NTZ R5, R21 &rd=0x0 &wr=0x1 ?trans2;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans1;
IADD3 R4, PT, PT, R28, UR4, RZ ?WAIT5_END_GROUP;
IMAD R9, R9, R8, R4 ?WAIT5_END_GROUP;
IADD3 R9, PT, PT, R0, R9, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0x3b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MultiplocarMatrices(int*, int*, int*, int)
_Z19MultiplocarMatricesPiS_S_i:
s_clause 0x2
s_load_b32 s9, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s3, s9, 1
v_mul_lo_u32 v5, v1, s9
s_add_i32 s8, s9, -1
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s8, s8, s2
s_and_b32 vcc_lo, exec_lo, s8
s_lshl_b32 s8, s14, 1
s_cbranch_vccnz .LBB0_4
v_dual_mov_b32 v9, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_lshlrev_b32_e32 v7, 3, v1
v_lshl_add_u32 v10, s15, 1, v1
v_add3_u32 v1, v0, v5, s8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 16, v2
v_mad_u64_u32 v[3:4], null, s9, v10, v[0:1]
v_mov_b32_e32 v4, 0
v_add_nc_u32_e32 v10, v7, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v11, v8, v7
s_mov_b32 s9, s2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[12:13], 2, v[3:4]
v_add_nc_u32_e32 v3, 2, v3
s_add_i32 s9, s9, 2
v_lshlrev_b64 v[14:15], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s9, v6
global_load_b32 v2, v[12:13], off
global_load_b32 v12, v[14:15], off
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v12, v12
ds_store_b32 v10, v2
ds_store_b32 v11, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b64 v[12:13], v7
ds_load_2addr_b32 v[14:15], v8 offset1:2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v9, v12, v14
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v9, v13, v15
s_cbranch_vccz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v9
.LBB0_4:
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v5, s2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MultiplocarMatrices | 1,441 | 1,401 | stackv2-00000-of-00015 |
// Demangled: saxpy(float*, float*, float)
Function : _Z5saxpyPfS_f
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R7, R7, UR6, R0 &req={0} ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x0 ?trans3;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &req={1} &wr=0x0 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &wr=0x0 ?trans2;
FFMA R7, R0, UR6, R5 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: saxpy(float*, float*, float)
_Z5saxpyPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s0, v4
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| saxpy | 475 | 429 | stackv2-00000-of-00015 |
// Demangled: transpose(float*, float*)
Function : _Z9transposePfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.Y &wr=0x0 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU.128 UR8, c[0x0][0x380] &wr=0x2 ?trans1;
S2R R2, SR_TID.X &wr=0x1 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x0 ?trans8;
LDC R4, c[0x0][0x364] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x370] &wr=0x3 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
IMAD R4, R4, UR5, R5 &req={0} ?WAIT2_END_GROUP;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans2;
IMAD R2, R9.reuse, UR4, R2 &req={1} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
IMAD R9, R9, UR6, RZ &req={3} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R10, R2, R9, R4 ?WAIT3_END_GROUP;
LEA R6, P0, R10, UR8, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R7, R10, UR9, R11, 0x2, P0 ?WAIT6_END_GROUP;
LDG.E R7, desc[UR4][R6.64] &req={0} &wr=0x2 ?trans1;
MOV R3, RZ ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R2, R4, R9, R2 ?WAIT3_END_GROUP;
LEA R4, P0, R2, UR10, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R5, R2, UR11, R3, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transpose(float*, float*)
_Z9transposePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s5, s5, s6
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v7, v3
v_mad_u64_u32 v[4:5], null, v2, s5, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_lshlrev_b64 v[4:5], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v6, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transpose | 655 | 865 | stackv2-00000-of-00015 |
// Demangled: exclusive_scan(int*)
Function : _Z14exclusive_scanPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.GT.U32.AND P0, PT, R9.reuse, 0x3, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R9.reuse, 0x1, PT ?trans1;
ISETP.NE.AND P2, PT, R9, RZ, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R5, R9, UR4, 0x2 ?WAIT4_END_GROUP;
@!P0 LEA R11, R9.reuse, UR4, 0x3 ?trans2;
@!P1 LEA R13, R9, UR4, 0x4 ?trans1;
STS [R5], R0 &req={2} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS.64 R6, [R11] &wr=0x0 ?trans2;
@!P0 IADD3 R4, PT, PT, R7, R6, RZ &req={0} ?trans1;
@!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 STS [R11+0x4], R4 &rd=0x0 ?trans2;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
@!P1 LEA R11, R9, UR4, 0x4 &req={0} ?WAIT5_END_GROUP;
@!P1 LDS R7, [R13+0x4] ?trans4;
@!P1 LDS R6, [R13+0xc] &wr=0x0 ?trans2;
@!P1 IADD3 R6, PT, PT, R6, R7, RZ &req={0} ?trans1;
@!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 STS [R13+0xc], R6 ?trans2;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 LDS R0, [UR4+0x1c] ?trans4;
@!P2 LDS R7, [UR4+0xc] &wr=0x0 ?trans2;
@!P2 IADD3 R0, PT, PT, R0, R7, RZ &req={0} ?trans1;
@!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 STS [UR4+0x1c], R0 ?trans2;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 LDS R4, [UR4+0xc] &wr=0x0 ?trans4;
@!P2 STS [UR4+0x1c], RZ ?trans1;
@!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 STS [UR4+0xc], RZ ?trans4;
@!P2 STS [UR4+0x1c], R4 &req={0} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R7, [R11+0x4] ?trans4;
@!P1 LDS R6, [R11+0xc] &wr=0x0 ?trans1;
@!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
@!P1 IADD3 R0, PT, PT, R6, R7, RZ &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R11+0x4], R6 ?trans1;
@!P0 LEA R7, R9, UR4, 0x3 ?WAIT3_END_GROUP;
@!P1 STS [R11+0xc], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 LDS.64 R8, [R7] &wr=0x0 ?trans2;
@!P0 IADD3 R13, PT, PT, R9, R8, RZ &req={0} ?trans1;
MOV R12, R9 ?trans1;
@!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 STS.64 [R7], R12 ?trans2;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R5, [R5] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x3a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: exclusive_scan(int*)
_Z14exclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_1:
s_lshl_b32 s2, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s2, v4
v_add_nc_u32_e32 v5, -1, v6
v_cmp_gt_u32_e64 s0, 9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_and_b32 s3, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v6, s1, v5
v_lshlrev_b32_e32 v5, 2, v5
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v7, v5
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v6, v6, v7
ds_store_b32 v5, v6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s1, 4
s_mov_b32 s1, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
ds_store_b32 v0, v0 offset:28
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s1, 8
s_mov_b32 s0, 4
.LBB0_7:
s_and_b32 s1, s1, 14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v0, s1, v4, -1
v_mul_u32_u24_e32 v5, s1, v4
s_mov_b32 s1, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, 9, v5
s_and_b32 s2, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_9
v_subrev_nc_u32_e32 v5, s1, v0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v0
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v7, v7, v6
ds_store_b32 v0, v7
ds_store_b32 v5, v6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s1, 1
s_cmp_gt_u32 s1, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| exclusive_scan | 1,368 | 1,272 | stackv2-00000-of-00015 |
// Demangled: inclusive_scan(int*)
Function : _Z14inclusive_scanPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
IADD3 R4, PT, PT, R9.reuse, -0x1, RZ ?trans2;
IADD3 R6, PT, PT, R9, -0x2, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P1, PT, R4, 0x6, PT ?trans2;
ISETP.GT.U32.AND P0, PT, R6, 0x5, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
LEA R5, R9, UR4, 0x2 ?WAIT5_END_GROUP;
STS [R5], R0 &req={2} &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
LOP3.LUT R0, R9, 0x3fc, RZ, 0xc0, !PT &req={0} ?WAIT5_END_GROUP;
@!P1 LDS R4, [R5] ?trans4;
@!P1 LDS R7, [R5+-0x4] &wr=0x0 ?trans2;
@!P1 IADD3 R4, PT, PT, R4, R7, RZ &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R5], R4 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P1, PT, R0, 0x4, PT ?WAIT5_END_GROUP;
@!P0 LDS R6, [R5] ?trans4;
@!P0 LDS R7, [R5+-0x8] &wr=0x0 ?trans2;
@!P0 IADD3 R6, PT, PT, R6, R7, RZ &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R5], R6 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P1 LDS R0, [R5] ?trans4;
@!P1 LDS R7, [R5+-0x10] &wr=0x0 ?trans2;
@!P1 IADD3 R0, PT, PT, R0, R7, RZ &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R5], R0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R7, [R5] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x240;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: inclusive_scan(int*)
_Z14inclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 8, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_1:
v_cmp_le_u32_e64 s0, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_3
v_subrev_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v5
ds_store_b32 v3, v4
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 3
s_mov_b32 s1, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_1
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| inclusive_scan | 889 | 564 | stackv2-00000-of-00015 |
// Demangled: kernel(int*)
Function : _Z6kernelPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_CTAID.Y &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x360] &wr=0x1 ?trans6;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR8, c[0x0][0x364] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans4;
LDC R4, c[0x0][0x370] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R0, R7, UR8, R0 &req={0} ?WAIT2_END_GROUP;
IMAD R7, R7, R4.reuse, UR6 &req={2} ?trans2;
IMAD R0, R0, R4, UR6 ?WAIT4_END_GROUP;
IMAD R5, R0, UR7, R5 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 &req={3} ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(int*)
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_mul_i32 s2, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s2, s2, s14
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s2
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 464 | 533 | stackv2-00000-of-00015 |
// Demangled: exclusive_prefix_sum_gpu(int*, int*, int, int)
Function : _Z24exclusive_prefix_sum_gpuPiS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
IMAD R7, R7, UR4, R0 &req={1} ?trans1;
UIMAD UR4, UR4, UR5, URZ &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans3;
ISETP.GE.AND P0, PT, R7, UR6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R8, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x210 &req={1} ?trans5;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R12, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x394] &wr=0x2 ?trans1;
UIADD3 UR5, UPT, UPT, UR6, -0x1, URZ ?WAIT6_END_GROUP;
LDC.64 R10, c[0x0][0x388] &wr=0x3 ?trans6;
STG.E desc[UR8][R12.64], RZ &req={1} &rd=0x1 ?trans1;
ISETP.GE.AND P0, PT, R7, UR5, PT ?trans1;
BSSY.RECONVERGENT B0, 0x1d0 ?WAIT12_END_GROUP;
@P0 BRA 0x1c0 &req={1} ?trans5;
IMAD.WIDE R2, R7, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
LDG.E R3, desc[UR8][R2.64] &wr=0x4 ?trans1;
IMAD.WIDE R4, R7, 0x4, R10 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR8][R4.64+0x4], R3 &req={4} &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 &req={2} ?trans5;
IADD3 R7, PT, PT, R7, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR7, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x140 ?trans5;
EXIT ?trans5;
UI2F.U32.RP UR5, UR4 ?trans2;
IADD3 R9, PT, PT, RZ, -UR4, RZ ?trans1;
ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ?trans1;
LDCU UR7, c[0x0][0x394] &wr=0x0 ?trans1;
BSSY.RECONVERGENT B0, 0x550 ?trans1;
LDCU.128 UR12, c[0x0][0x380] &wr=0x1 ?trans3;
MUFU.RCP R0, UR5 &wr=0x2 ?trans2;
LDCU UR5, c[0x0][0x390] &wr=0x3 ?trans1;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={2} ?WAIT2_END_GROUP;
IADD3 R0, PT, PT, R7, UR4, RZ ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x2 &wr=0x4 ?trans3;
ISETP.GE.AND P0, PT, R0.reuse, UR6, PT ?trans1;
VIMNMX.S32 R5, R0, UR6, !PT ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x0 ?trans3;
SEL R4, RZ, 0x1, P0 ?trans1;
HFMA2 R2, -RZ, RZ, 0, 0 &req={2} ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R5, -R0, -R4 ?trans1;
IMAD R9, R9, R3, RZ &req={4} ?WAIT4_END_GROUP;
IMAD.HI.U32 R6, R3, R9, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R6, R5, RZ ?WAIT5_END_GROUP;
IADD3 R0, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R5, R0, UR4, R5 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R5, UR4, PT ?WAIT13_END_GROUP;
@P0 IADD3 R5, PT, PT, R5, -UR4, RZ ?trans2;
@P0 IADD3 R3, PT, PT, R3, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R5, UR4, PT ?WAIT13_END_GROUP;
@P1 IADD3 R3, PT, PT, R3, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R3, RZ, UR4, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, R4, R3, RZ ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R3.reuse, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ?WAIT3_END_GROUP;
LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ?WAIT13_END_GROUP;
@!P1 BRA 0x540 &req={3,1,0} ?trans5;
LDC.64 R14, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R0, PT, PT, -R0, RZ, RZ ?trans1;
IMAD.WIDE R2, R8, 0x4, RZ ?WAIT6_END_GROUP;
LDC.64 R12, c[0x0][0x388] &wr=0x1 ?trans2;
ISETP.GE.AND P1, PT, R7.reuse, UR5, PT ?trans1;
IMAD.WIDE R10, R7, 0x4, R14 &req={0} ?WAIT12_END_GROUP;
@P1 IADD.64 R4, -R2, R10 ?trans2;
@P1 LDG.E R6, desc[UR8][R10.64] &wr=0x2 ?trans5;
@P1 LDG.E R5, desc[UR8][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R8, R7, 0x4, R12 &req={1} ?trans1;
@P1 IADD3 R17, PT, PT, R6, R5, RZ &req={2} ?WAIT5_END_GROUP;
@P1 STG.E desc[UR8][R8.64], R17 &rd=0x2 ?trans4;
@!P1 LDG.E R19, desc[UR8][R10.64] &wr=0x3 ?trans1;
IADD3 R0, PT, PT, R0, 0x1, RZ ?trans2;
IADD3 R7, PT, PT, R7, UR4, RZ ?trans1;
@!P1 STG.E desc[UR8][R8.64], R19 &req={3} &rd=0x2 ?trans2;
ISETP.NE.AND P1, PT, R0, RZ, PT ?WAIT13_END_GROUP;
@P1 BRA 0x460 &req={2} ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
@!P0 EXIT ?trans5;
ISETP.GE.AND P0, PT, R7, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R11, PT, PT, R7, -UR6, RZ &req={1} ?trans1;
@P0 MOV.64 R2, UR12 ?WAIT6_END_GROUP;
@P0 IMAD.WIDE R10, R11, 0x4, R2 ?WAIT4_END_GROUP;
@P0 IMAD.WIDE R8, R7, 0x4, R2 ?trans2;
@P0 LDG.E R11, desc[UR8][R10.64] &wr=0x2 ?trans4;
@P0 LDG.E R8, desc[UR8][R8.64] &wr=0x2 ?trans1;
@P0 MOV.64 R4, UR14 ?trans2;
@!P0 MOV.64 R2, UR12 ?WAIT4_END_GROUP;
@P0 IMAD.WIDE R12, R7, 0x4, R4 ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R14, R7.reuse, 0x4, R2 ?trans1;
IADD3 R23, PT, PT, R7, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R23, UR6, PT ?trans1;
@P0 IADD3 R19, PT, PT, R8, R11, RZ &req={2} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR8][R12.64], R19 &rd=0x0 ?trans4;
@!P0 LDG.E R15, desc[UR8][R14.64] &wr=0x2 ?trans1;
@!P0 MOV.64 R4, UR14 ?WAIT3_END_GROUP;
@P1 IADD3 R9, PT, PT, R23, -UR6, RZ ?WAIT3_END_GROUP;
@!P0 IMAD.WIDE R16, R7, 0x4, R4 ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R8, R9, 0x4, R2 ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R6, R23.reuse, 0x4, R2 ?trans1;
@!P0 STG.E desc[UR8][R16.64], R15 &req={2} &rd=0x1 ?trans4;
@P1 LDG.E R9, desc[UR8][R8.64] &wr=0x2 ?trans4;
@P1 LDG.E R6, desc[UR8][R6.64] &wr=0x2 ?trans1;
@P1 IMAD.WIDE R10, R23, 0x4, R4 ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE R12, R23.reuse, 0x4, R2 &req={0} ?trans1;
IADD3 R25, PT, PT, R23, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R25, UR6, PT ?trans1;
@P1 IADD3 R19, PT, PT, R6, R9, RZ &req={2} ?WAIT5_END_GROUP;
@P1 STG.E desc[UR8][R10.64], R19 &rd=0x0 ?trans4;
@!P1 LDG.E R13, desc[UR8][R12.64] &wr=0x2 ?trans3;
@P0 IADD3 R21, PT, PT, R25, -UR6, RZ ?trans1;
@!P1 IMAD.WIDE R14, R23, 0x4, R4 &req={1} ?WAIT4_END_GROUP;
@P0 IMAD.WIDE R8, R21, 0x4, R2 ?WAIT4_END_GROUP;
@P0 IMAD.WIDE R6, R25.reuse, 0x4, R2 ?trans1;
@!P1 STG.E desc[UR8][R14.64], R13 &req={2} &rd=0x1 ?trans4;
@P0 LDG.E R9, desc[UR8][R8.64] &wr=0x2 ?trans4;
@P0 LDG.E R6, desc[UR8][R6.64] &wr=0x2 ?trans1;
@P0 IMAD.WIDE R10, R25, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
@!P0 IMAD.WIDE R16, R25.reuse, 0x4, R2 ?trans1;
IADD3 R23, PT, PT, R25, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P1, PT, R23, UR6, PT ?trans1;
@P0 IADD3 R19, PT, PT, R6, R9, RZ &req={2} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR8][R10.64], R19 &rd=0x0 ?trans4;
@!P0 LDG.E R17, desc[UR8][R16.64] &wr=0x2 ?trans3;
@P1 IADD3 R21, PT, PT, R23, -UR6, RZ ?trans1;
@!P0 IMAD.WIDE R14, R25, 0x4, R4 &req={1} ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R12, R21, 0x4, R2 ?WAIT4_END_GROUP;
@P1 IMAD.WIDE R8, R23.reuse, 0x4, R2 ?trans1;
@!P0 STG.E desc[UR8][R14.64], R17 &req={2} &rd=0x1 ?trans4;
@P1 LDG.E R13, desc[UR8][R12.64] &wr=0x2 ?trans4;
@P1 LDG.E R8, desc[UR8][R8.64] &wr=0x2 ?trans1;
@P1 IMAD.WIDE R10, R23, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE R2, R23, 0x4, R2 ?trans1;
@P1 IADD3 R19, PT, PT, R8, R13, RZ &req={2} ?WAIT5_END_GROUP;
@P1 STG.E desc[UR8][R10.64], R19 &rd=0x1 ?trans4;
@!P1 LDG.E R3, desc[UR8][R2.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R4, R23.reuse, 0x4, R4 ?trans1;
IADD3 R7, PT, PT, R23, UR4, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, UR7, PT ?trans1;
@!P1 STG.E desc[UR8][R4.64], R3 &req={2} &rd=0x1 ?WAIT12_END_GROUP;
@!P0 BRA 0x560 ?trans5;
EXIT ?trans5;
BRA 0x950;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: exclusive_prefix_sum_gpu(int*, int*, int, int)
_Z24exclusive_prefix_sum_gpuPiS_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_13
s_load_b32 s9, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lg_u32 s2, 0
s_mov_b32 s10, s2
s_cselect_b32 s12, -1, 0
s_ashr_i32 s11, s2, 31
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_lshl_b64 s[14:15], s[10:11], 2
v_mov_b32_e32 v0, 0
s_add_i32 s13, s3, -1
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[10:11], s[8:9], 2
s_sub_u32 s9, s4, s14
s_subb_u32 s14, s5, s15
.LBB0_2:
s_and_b32 vcc_lo, exec_lo, s12
s_mov_b32 s0, -1
s_cbranch_vccz .LBB0_8
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v4, v[4:5], off
v_cmpx_le_i32_e64 s2, v1
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_5
v_add_co_u32 v5, vcc_lo, s9, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s14, v3, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v5, v4
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[4:5], v6, off
.LBB0_5:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_7
v_add_co_u32 v5, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v4, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s0, 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_12
s_mov_b32 s0, exec_lo
global_store_b32 v0, v0, s[6:7]
v_cmpx_gt_i32_e64 s13, v1
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off offset:4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_12:
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v2, s0, v2, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
v_cmp_le_i32_e32 vcc_lo, s3, v1
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| exclusive_prefix_sum_gpu | 4,039 | 1,493 | stackv2-00000-of-00015 |
// Demangled: conv_2D(float*, float*, int)
Function : _Z7conv_2DPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
LDC R23, c[0x0][0x360] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R13, SR_TID.Y &wr=0x3 ?trans6;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
S2UR UR5, SR_CTAID.Y &wr=0x3 ?trans8;
LDC R12, c[0x0][0x364] &wr=0x3 ?trans1;
IMAD R23, R23, UR4, R0 &req={1} ?WAIT2_END_GROUP;
IMAD R12, R12, UR5, R13 &req={3} ?WAIT5_END_GROUP;
VIMNMX.U32 R0, R23, R12, !PT ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IADD3 R3, PT, PT, R23, -0x1, RZ ?trans1;
ISETP.GT.AND P4, PT, R12.reuse, UR6, PT ?trans1;
IADD3 R10, PT, PT, R12.reuse, 0x1, RZ ?trans2;
IADD3 R18, PT, PT, R12.reuse, -0x1, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans1;
ISETP.GE.AND P0, PT, R3.reuse, UR6, PT ?trans1;
ISETP.GE.AND P1, PT, R3, UR6, PT ?trans1;
ISETP.EQ.OR P4, PT, R12, RZ, P4 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.AND P6, PT, R23, UR6, PT ?trans1;
ISETP.LT.OR P0, PT, R3.reuse, RZ, P0 ?trans1;
ISETP.GT.AND P1, PT, R3, -0x1, !P1 ?trans1;
IADD3 R19, PT, PT, R23, 0x1, RZ ?WAIT3_END_GROUP;
PLOP3.LUT P2, PT, P0, P4, PT, 0xf8, 0x8f ?trans1;
ISETP.GE.OR P3, PT, R12, UR6, !P1 ?trans1;
ISETP.GE.OR P0, PT, R10, UR6, !P1 ?trans1;
ISETP.GE.AND P1, PT, R23, UR6, PT ?WAIT5_END_GROUP;
ISETP.LT.OR P1, PT, R23, RZ, P1 ?WAIT5_END_GROUP;
@!P2 LDC.64 R4, c[0x0][0x380] &wr=0x1 ?trans1;
@!P2 IMAD R11, R3.reuse, UR6, R18 ?trans1;
PLOP3.LUT P1, PT, P1, P4, PT, 0xf8, 0x8f ?trans1;
@!P0 IMAD R2, R3.reuse, UR6, RZ ?trans1;
@!P0 MOV R13, RZ ?trans1;
@!P3 IMAD R17, R3, UR6, R12 ?trans1;
@!P0 MOV R3, RZ ?trans2;
@!P3 LDC.64 R8, c[0x0][0x380] &wr=0x2 ?trans3;
@!P0 IADD.64 R6, R2, R12 ?WAIT2_END_GROUP;
MOV R13, RZ ?WAIT3_END_GROUP;
@!P0 LDC.64 R14, c[0x0][0x380] &wr=0x3 ?trans1;
@!P2 IMAD.WIDE.U32 R2, R11, 0x4, R4 &req={1} ?WAIT7_END_GROUP;
@!P1 LDC.64 R24, c[0x0][0x380] &wr=0x1 ?trans1;
@!P2 LDG.E R0, desc[UR4][R2.64] &req={0} &rd=0x0 &wr=0x4 ?trans1;
@!P3 IMAD.WIDE.U32 R4, R17, 0x4, R8 &req={2} ?trans1;
ISETP.GT.AND P2, PT, R23, -0x1, !P6 ?WAIT4_END_GROUP;
@!P3 LDG.E R13, desc[UR4][R4.64] &rd=0x2 &wr=0x4 ?trans1;
@!P0 LEA R14, P5, R6, R14, 0x2 &req={3} ?trans1;
ISETP.GE.AND P3, PT, R19, UR6, PT ?WAIT3_END_GROUP;
@!P0 LEA.HI.X R15, R6, R15, R7, 0x2, P5 ?trans1;
ISETP.GE.AND P5, PT, R19.reuse, UR6, PT ?trans1;
ISETP.GE.OR P6, PT, R12, UR6, !P2 ?trans1;
ISETP.GE.OR P2, PT, R10, UR6, !P2 ?trans1;
ISETP.LT.OR P3, PT, R19.reuse, RZ, P3 ?trans2;
ISETP.GT.AND P5, PT, R19, -0x1, !P5 ?WAIT3_END_GROUP;
PLOP3.LUT P3, PT, P3, P4, PT, 0xf8, 0x8f ?trans2;
ISETP.GE.OR P4, PT, R10, UR6, !P5 ?trans1;
ISETP.GE.OR P5, PT, R12, UR6, !P5 ?WAIT3_END_GROUP;
@!P6 LDC.64 R16, c[0x0][0x380] &wr=0x3 ?trans1;
@!P1 IMAD R3, R23, UR6, R18 &req={0} ?WAIT7_END_GROUP;
@!P2 LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans1;
@!P1 IMAD.WIDE.U32 R24, R3, 0x4, R24 &req={1} ?trans1;
@!P2 MOV R26, R12 ?WAIT6_END_GROUP;
@!P4 LDC.64 R4, c[0x0][0x380] &req={2} &wr=0x1 ?trans1;
@!P2 IMAD R10, R23, UR6, RZ ?trans1;
@!P2 MOV R27, RZ ?trans1;
@!P2 MOV R11, RZ ?WAIT5_END_GROUP;
@!P3 LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
CS2R R20, SRZ ?trans1;
@!P2 IADD.64 R10, R26, R10 ?WAIT6_END_GROUP;
@!P5 LDC.64 R2, c[0x0][0x380] &wr=0x5 ?trans1;
@!P3 IMAD R27, R19.reuse, UR6, R18 ?trans1;
@!P0 LDG.E R21, desc[UR4][R14.64+0x4] &rd=0x3 &wr=0x4 ?trans1;
@!P4 IMAD R18, R19.reuse, UR6, RZ ?trans2;
@!P5 IMAD R29, R19, UR6, R12.reuse ?trans1;
@!P4 MOV R19, RZ ?trans1;
IMAD R23, R23, UR6, R12 ?trans2;
HFMA2 R22, -RZ, RZ, 0, 0 ?trans1;
@!P1 LDG.E R20, desc[UR4][R24.64] &wr=0x4 ?trans1;
@!P4 MOV R14, R12 &req={3} ?trans1;
@!P4 MOV R15, RZ ?trans1;
@!P6 IMAD.WIDE.U32 R16, R23, 0x4, R16 ?trans1;
@!P2 LEA R8, P0, R10, R8, 0x2 &req={0} ?WAIT3_END_GROUP;
HFMA2 R12, -RZ, RZ, 0, 0 ?trans1;
@!P4 IADD.64 R14, R14, R18 ?trans2;
@!P6 LDG.E R22, desc[UR4][R16.64] &wr=0x3 ?trans1;
@!P2 LEA.HI.X R9, R10, R9, R11, 0x2, P0 ?trans2;
@!P4 LEA R10, P0, R14.reuse, R4, 0x2 &req={1} ?trans1;
@!P3 IMAD.WIDE.U32 R6, R27, 0x4, R6 &req={2} ?trans1;
MOV R18, RZ ?trans1;
@!P2 LDG.E R12, desc[UR4][R8.64+0x4] &wr=0x2 ?trans1;
@!P4 LEA.HI.X R11, R14, R5, R15, 0x2, P0 ?trans1;
CS2R R4, SRZ ?trans1;
@!P5 IMAD.WIDE.U32 R2, R29, 0x4, R2 &req={5} ?WAIT2_END_GROUP;
@!P3 LDG.E R18, desc[UR4][R6.64] &wr=0x5 ?trans4;
@!P5 LDG.E R4, desc[UR4][R2.64] &rd=0x0 &wr=0x5 ?trans4;
@!P4 LDG.E R5, desc[UR4][R10.64+0x4] &wr=0x5 ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
UMOV.64 UR8, 0x3fbc71c71c71c71c ?trans1;
IMAD.WIDE.U32 R2, R23, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
FADD R0, R13, R0 &req={4} ?WAIT4_END_GROUP;
FADD R21, R0, R21 ?WAIT4_END_GROUP;
FADD R21, R21, R20 ?WAIT4_END_GROUP;
FADD R21, R21, R22 &req={3} ?WAIT4_END_GROUP;
FADD R21, R21, R12 &req={2} ?WAIT4_END_GROUP;
FADD R21, R21, R18 &req={5} ?WAIT4_END_GROUP;
FADD R0, R21, R4 ?WAIT4_END_GROUP;
FADD R0, R0, R5 ?WAIT4_END_GROUP;
F2F.F64.F32 R4, R0 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R4, UR8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2F.F32.F64 R5, R4 &req={0} &wr=0x0 ?trans2;
STG.E desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x7a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: conv_2D(float*, float*, int)
_Z7conv_2DPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v2, v0, v1
v_cmpx_gt_u32_e64 s2, v2
s_cbranch_execz .LBB0_38
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v8, -1, v0
v_add_nc_u32_e32 v2, -1, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v8
v_cmp_gt_i32_e64 s0, s2, v8
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_5
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s2, v2
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s0
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_4
v_mad_u64_u32 v[5:6], null, v8, s2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_9
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_gt_i32_e64 s0, s2, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s0
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[3:4], null, v8, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v4, v[3:4], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, 1, v1
v_mov_b32_e32 v7, 0
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s2, v3
v_mov_b32_e32 v7, 0
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_12
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v8, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_gt_i32_e64 s0, s2, v0
s_and_b32 s1, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_17
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s2, v2
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s0
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_16
v_mad_u64_u32 v[8:9], null, v0, s2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v6, v[8:9], off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_21
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_gt_i32_e64 s0, s2, v1
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s0
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_20
v_mad_u64_u32 v[9:10], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v9, v[9:10], off
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_21:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_25
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s2, v3
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_24
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v0, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v8, v[10:11], off
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v12, 1, v0
v_mov_b32_e32 v10, 0
v_cmp_lt_i32_e32 vcc_lo, -1, v12
v_cmp_gt_i32_e64 s0, s2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_29
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cmp_gt_i32_e64 s0, s2, v2
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s0
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_28
v_mad_u64_u32 v[13:14], null, v12, s2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
global_load_b32 v11, v[13:14], off
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_29:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_33
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_gt_i32_e64 s0, s2, v1
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s0
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_32
v_mad_u64_u32 v[13:14], null, v12, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
global_load_b32 v10, v[13:14], off
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_33:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v13, 0
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_37
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s2, v3
v_mov_b32_e32 v13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_36
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[13:14], null, v12, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v13, v[12:13], off
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_37:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v5, v4
s_mov_b32 s0, 0x1c71c71c
s_mov_b32 s1, 0x3fbc71c7
v_add_f32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v6
v_add_f32_e32 v3, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v8
v_add_f32_e32 v3, v3, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v10
v_add_f32_e32 v3, v3, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[3:4], v3
v_mul_f64 v[3:4], v[3:4], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v5, v[3:4]
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_38:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| conv_2D | 3,159 | 5,345 | stackv2-00000-of-00015 |
// Demangled: reverse(char*, char*, int)
Function : _Z7reversePcS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R2, SR_TID.X &wr=0x0 ?trans1;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x2 ?trans3;
IADD.64 R4, R2, UR8 &req={0} ?WAIT7_END_GROUP;
LDG.E.U8 R5, desc[UR4][R4.64] &req={1} &wr=0x3 ?trans1;
LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R2, UR6, RZ &req={2} ?WAIT4_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR10 ?WAIT6_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R5 &req={3} ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: reverse(char*, char*, int)
_Z7reversePcS_i:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_u8 v2, v0, s[4:5]
v_xad_u32 v0, v0, -1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| reverse | 411 | 251 | stackv2-00000-of-00015 |
// Demangled: VecAdd(float*, float*, float*)
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: VecAdd(float*, float*, float*)
_Z6VecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| VecAdd | 420 | 192 | stackv2-00000-of-00015 |
// Demangled: hello(char*, int*)
Function : _Z5helloPcPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R2, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT6_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R2.reuse, 0x4, R4 &req={0} ?trans1;
IADD.64 R2, R2, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E.U8 R4, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans4;
LDG.E.U8 R7, desc[UR4][R2.64] &wr=0x2 ?trans2;
IADD3 R7, PT, PT, R4, R7, RZ &req={2} ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xd0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: hello(char*, int*)
_Z5helloPcPi:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
global_load_u8 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v2, v1
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| hello | 390 | 156 | stackv2-00000-of-00015 |
// Demangled: CudaCompute(SubBlock*, float*, float*, int, int, int, int, float*)
Function : _Z11CudaComputeP8SubBlockPfS1_iiiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: CudaCompute(SubBlock*, float*, float*, int, int, int, int, float*)
_Z11CudaComputeP8SubBlockPfS1_iiiiS1_:
s_endpgm
| CudaCompute | 106 | 26 | stackv2-00000-of-00015 |
// Demangled: CudaMergeResults(SubBlock*, float*, float*, int, int, int, int, float*)
Function : _Z16CudaMergeResultsP8SubBlockPfS1_iiiiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans8;
LDC.64 R4, c[0x0][0x398] &wr=0x2 ?trans1;
LOP3.LUT P0, RZ, R0, UR4, RZ, 0xfc, !PT &req={1} ?trans1;
VIMNMX.S32 R0, R4, R5, PT &req={2} ?WAIT5_END_GROUP;
ISETP.LT.OR P0, PT, R0, 0x1, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x3a8] &wr=0x0 ?trans1;
LOP3.LUT R24, R5.reuse, 0x7, RZ, 0xc0, !PT ?trans1;
HFMA2 R8, -RZ, RZ, 0, 0 ?trans1;
LOP3.LUT R9, R5, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R0, PT, PT, R24, -0x1, RZ ?trans2;
IADD3 R9, PT, PT, -R9, RZ, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ?trans1;
LOP3.LUT R0, R5, 0x3, RZ, 0xc0, !PT ?trans1;
IADD.64 R2, R2, 0x10 &req={1,0} ?WAIT11_END_GROUP;
LDC.64 R6, c[0x0][0x398] &req={0} &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x380] &req={5,1} &wr=0x1 ?trans1;
ISETP.NE.AND P2, PT, R24, RZ, PT ?trans1;
ISETP.GE.U32.AND P3, PT, R7, 0x8, PT &req={0} ?trans1;
IMAD R10, R8, R7, RZ &req={3} ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R4, R8.reuse, 0x30, R4 &req={1} ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ ?trans1;
MOV R11, RZ ?WAIT4_END_GROUP;
LDG.E.64 R4, desc[UR4][R4.64+0x8] &wr=0x5 ?trans1;
ISETP.NE.AND P0, PT, R8, R6, PT ?WAIT3_END_GROUP;
@!P3 BRA 0x580 &req={2} ?trans10;
IADD.64 R12, R4, 0x10 &req={5} ?trans2;
MOV R11, RZ ?trans1;
MOV R6, R9 ?trans1;
IMAD.WIDE.U32 R14, R10, 0x4, R2 ?WAIT7_END_GROUP;
LDG.E R19, desc[UR4][R12.64+-0x10] &req={2} &wr=0x2 ?trans1;
LDC.64 R16, c[0x0][0x390] &wr=0x2 ?trans3;
LDG.E R20, desc[UR4][R14.64+-0x10] &wr=0x3 ?trans1;
IMAD.WIDE R18, R19, 0x4, R16 &req={2} ?WAIT5_END_GROUP;
LDG.E R21, desc[UR4][R18.64+-0x4] &wr=0x3 ?trans2;
FADD R25, R20, R21 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R18.64+-0x4], R25 &rd=0x0 ?trans4;
LDG.E R21, desc[UR4][R12.64+-0xc] &wr=0x2 ?trans4;
LDG.E R22, desc[UR4][R14.64+-0xc] &wr=0x3 ?trans1;
IMAD.WIDE R20, R21, 0x4, R16 &req={2} ?WAIT5_END_GROUP;
LDG.E R23, desc[UR4][R20.64+-0x4] &wr=0x3 ?trans2;
FADD R27, R22, R23 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R20.64+-0x4], R27 &rd=0x1 ?trans4;
LDG.E R23, desc[UR4][R12.64+-0x8] &wr=0x2 ?trans4;
LDG.E R26, desc[UR4][R14.64+-0x8] &wr=0x3 ?trans1;
IMAD.WIDE R22, R23, 0x4, R16 &req={2} ?WAIT5_END_GROUP;
LDG.E R29, desc[UR4][R22.64+-0x4] &wr=0x3 ?trans2;
FADD R29, R26, R29 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R22.64+-0x4], R29 &rd=0x2 ?trans4;
LDG.E R19, desc[UR4][R12.64+-0x4] &req={0} &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R14.64+-0x4] &wr=0x4 ?trans1;
IMAD.WIDE R18, R19, 0x4, R16 &req={3} ?WAIT5_END_GROUP;
LDG.E R26, desc[UR4][R18.64+-0x4] &wr=0x4 ?trans2;
FADD R25, R25, R26 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R18.64+-0x4], R25 &rd=0x0 ?trans4;
LDG.E R21, desc[UR4][R12.64] &req={1} &wr=0x3 ?trans4;
LDG.E R26, desc[UR4][R14.64] &wr=0x4 ?trans1;
IMAD.WIDE R20, R21, 0x4, R16 &req={3} ?WAIT5_END_GROUP;
LDG.E R27, desc[UR4][R20.64+-0x4] &wr=0x4 ?trans2;
FADD R27, R26, R27 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R20.64+-0x4], R27 &rd=0x1 ?trans4;
LDG.E R23, desc[UR4][R12.64+0x4] &req={2} &wr=0x2 ?trans4;
LDG.E R26, desc[UR4][R14.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R22, R23, 0x4, R16 &req={2} ?WAIT5_END_GROUP;
LDG.E R29, desc[UR4][R22.64+-0x4] &wr=0x3 ?trans2;
FADD R29, R26, R29 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R22.64+-0x4], R29 &rd=0x2 ?trans4;
LDG.E R19, desc[UR4][R12.64+0x8] &req={0} &wr=0x3 ?trans4;
LDG.E R25, desc[UR4][R14.64+0x8] &wr=0x4 ?trans1;
IMAD.WIDE R18, R19, 0x4, R16 &req={3} ?WAIT5_END_GROUP;
LDG.E R26, desc[UR4][R18.64+-0x4] &wr=0x4 ?trans2;
FADD R25, R25, R26 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R18.64+-0x4], R25 &rd=0x2 ?trans4;
LDG.E R21, desc[UR4][R12.64+0xc] &req={1} &wr=0x3 ?trans4;
LDG.E R20, desc[UR4][R14.64+0xc] &rd=0x0 &wr=0x4 ?trans1;
IADD3 R6, PT, PT, R6, 0x8, RZ ?trans1;
IMAD.WIDE R16, R21, 0x4, R16 &req={3} ?WAIT5_END_GROUP;
LDG.E R21, desc[UR4][R16.64+-0x4] &wr=0x4 ?trans1;
ISETP.NE.AND P3, PT, R6, RZ, PT ?trans1;
IADD.64 R12, R12, 0x20 ?trans2;
IADD.64 R14, R14, 0x20 &req={0} ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R11, 0x8, RZ ?trans1;
FADD R21, R20, R21 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R16.64+-0x4], R21 &rd=0x2 ?trans1;
@P3 BRA 0x210 ?trans5;
@!P2 BRA 0xab0 ?trans5;
ISETP.NE.AND P2, PT, R0, RZ, PT ?trans1;
@!P1 BRA 0x810 ?WAIT12_END_GROUP;
IMAD.WIDE.U32 R14, R11, 0x4, R4 &req={5} ?trans1;
LDC.64 R18, c[0x0][0x3a8] &req={2} &wr=0x0 ?trans4;
LDG.E R21, desc[UR4][R14.64] &wr=0x2 ?trans1;
IADD3 R17, PT, PT, R10, R11, RZ ?WAIT3_END_GROUP;
LDC.64 R12, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R28, c[0x0][0x3a8] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R18, R17, 0x4, R18 &req={0} ?WAIT6_END_GROUP;
LDG.E R18, desc[UR4][R18.64] &rd=0x0 &wr=0x3 ?trans1;
IMAD.WIDE R20, R21, 0x4, R12 &req={2} ?WAIT5_END_GROUP;
LDG.E R17, desc[UR4][R20.64+-0x4] &wr=0x3 ?trans1;
MOV R16, R11 ?trans1;
HFMA2 R19, -RZ, RZ, 0, 0 &req={0} ?trans2;
FADD R25, R18, R17 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R20.64+-0x4], R25 &rd=0x0 ?trans4;
LDG.E R27, desc[UR4][R14.64+0x4] &wr=0x2 ?trans1;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans1;
MOV R18, R10 ?WAIT5_END_GROUP;
IADD.64 R22, R16, R18 ?WAIT5_END_GROUP;
LEA R16, P3, R22, R28, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R17, R22, R29, R23, 0x2, P3 ?WAIT5_END_GROUP;
LDG.E R6, desc[UR4][R16.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R18, R27, 0x4, R12 &req={2} ?WAIT5_END_GROUP;
LDG.E R23, desc[UR4][R18.64+-0x4] &wr=0x3 ?trans2;
FADD R23, R6, R23 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R18.64+-0x4], R23 &rd=0x1 ?trans4;
LDG.E R21, desc[UR4][R14.64+0x8] &req={0} &wr=0x2 ?trans4;
LDG.E R6, desc[UR4][R16.64+0x8] &wr=0x3 ?trans1;
IMAD.WIDE R20, R21, 0x4, R12 &req={2} ?WAIT5_END_GROUP;
LDG.E R25, desc[UR4][R20.64+-0x4] &wr=0x3 ?trans2;
FADD R25, R6, R25 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R20.64+-0x4], R25 &rd=0x1 ?trans4;
LDG.E R27, desc[UR4][R14.64+0xc] &wr=0x2 ?trans4;
LDG.E R6, desc[UR4][R16.64+0xc] &wr=0x3 ?trans1;
IMAD.WIDE R12, R27, 0x4, R12 &req={2} ?WAIT5_END_GROUP;
LDG.E R27, desc[UR4][R12.64+-0x4] &wr=0x3 ?trans1;
IADD3 R11, PT, PT, R11, 0x4, RZ ?trans1;
FADD R27, R6, R27 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+-0x4], R27 &rd=0x1 ?trans2;
@!P2 BRA 0xab0 ?trans5;
ISETP.NE.AND P3, PT, R0, 0x1, PT ?trans1;
LOP3.LUT P2, RZ, R7, 0x1, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@!P3 BRA 0x9f0 ?trans5;
IMAD.WIDE.U32 R16, R11, 0x4, R4 &req={5,2} ?trans1;
LDC.64 R12, c[0x0][0x3a8] &req={1} &wr=0x0 ?trans4;
LDG.E R19, desc[UR4][R16.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R10, R11, RZ ?WAIT3_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R20, c[0x0][0x3a8] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R14, R15, 0x4, R12 &req={0} ?WAIT6_END_GROUP;
LDG.E R14, desc[UR4][R14.64] &rd=0x0 &wr=0x3 ?trans1;
IMAD.WIDE R12, R19, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R19, desc[UR4][R12.64+-0x4] &wr=0x3 ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 &req={0} ?trans2;
FADD R23, R14, R19 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R12.64+-0x4], R23 &rd=0x0 ?trans4;
LDG.E R25, desc[UR4][R16.64+0x4] &wr=0x2 ?trans1;
MOV R14, R10 ?trans1;
MOV R12, R11 &req={0} ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R18, R12, R14 ?WAIT5_END_GROUP;
LEA R20, P3, R18, R20, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R21, R18, R21, R19, 0x2, P3 ?WAIT5_END_GROUP;
LDG.E R20, desc[UR4][R20.64+0x4] &wr=0x3 ?trans1;
IMAD.WIDE R6, R25, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R15, desc[UR4][R6.64+-0x4] &wr=0x3 ?trans1;
IADD3 R11, PT, PT, R11, 0x2, RZ ?trans1;
FADD R15, R20, R15 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+-0x4], R15 &rd=0x0 ?trans2;
@!P2 BRA 0xab0 ?trans5;
IMAD.WIDE.U32 R6, R11, 0x4, R4 &req={5,0} ?trans1;
LDC.64 R12, c[0x0][0x390] &req={1} &wr=0x0 ?trans5;
LDG.E R7, desc[UR4][R6.64] &wr=0x0 ?trans1;
IADD3 R11, PT, PT, R10, R11, RZ ?trans2;
LDC.64 R4, c[0x0][0x3a8] &wr=0x1 ?trans3;
IMAD.WIDE.U32 R4, R11, 0x4, R4 &req={1} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x3 ?trans1;
IMAD.WIDE R10, R7, 0x4, R12 &req={0} ?WAIT5_END_GROUP;
LDG.E R13, desc[UR4][R10.64+-0x4] &wr=0x3 ?trans2;
FADD R13, R4, R13 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R10.64+-0x4], R13 &rd=0x3 ?trans2;
@P0 BRA 0x120 ?trans5;
EXIT ?trans5;
BRA 0xad0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: CudaMergeResults(SubBlock*, float*, float*, int, int, int, int, float*)
_Z16CudaMergeResultsP8SubBlockPfS1_iiiiS1_:
s_load_b64 s[2:3], s[0:1], 0x18
v_or_b32_e32 v0, s15, v0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, 0
s_cselect_b32 s4, -1, 0
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s4
s_cbranch_execz .LBB1_6
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x28
s_cmp_gt_i32 s3, 0
v_mov_b32_e32 v0, 0
s_cselect_b32 s12, -1, 0
s_mov_b32 s4, s5
s_mov_b32 s15, s5
s_waitcnt lgkmcnt(0)
s_add_u32 s13, s8, -4
s_addc_u32 s14, s9, -1
.LBB1_2:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB1_5
s_lshl_b64 s[8:9], s[4:5], 2
s_mul_i32 s10, s15, 48
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_mul_hi_u32 s11, s15, 48
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_mov_b32 s16, s3
s_load_b64 s[10:11], s[10:11], 0x8
.LBB1_4:
s_waitcnt lgkmcnt(0)
s_load_b32 s18, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s19, s18, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[18:19], s[18:19], 2
s_add_u32 s18, s13, s18
s_addc_u32 s19, s14, s19
s_clause 0x1
global_load_b32 v1, v0, s[8:9]
global_load_b32 v2, v0, s[18:19]
s_add_i32 s16, s16, -1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s16, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[18:19]
s_cbranch_scc0 .LBB1_4
.LBB1_5:
s_add_i32 s15, s15, 1
s_add_i32 s4, s4, s3
s_cmp_eq_u32 s15, s2
s_cbranch_scc0 .LBB1_2
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| CudaMergeResults | 4,989 | 1,038 | stackv2-00000-of-00015 |
// Demangled: cudaDummy()
Function : _Z9cudaDummyv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: cudaDummy()
_Z9cudaDummyv:
s_endpgm
| cudaDummy | 92 | 12 | stackv2-00000-of-00015 |
// Demangled: add_threads(int*, int*, int*)
Function : _Z11add_threadsPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_threads(int*, int*, int*)
_Z11add_threadsPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_threads | 426 | 193 | stackv2-00000-of-00015 |
// Demangled: MatAddElementThread(int*, int*, int*)
Function : _Z19MatAddElementThreadPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x370] &wr=0x1 ?trans6;
S2UR UR6, SR_CTAID.Y &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x360] &wr=0x2 ?trans1;
S2R R11, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans4;
LDC R0, c[0x0][0x364] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x5 ?trans1;
IMAD R0, R0, UR6, R7 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R0, R0, UR7, R9 &req={1} ?WAIT4_END_GROUP;
IMAD R9, R0, UR8, R11 &req={2} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R9, 0x4, R2 &req={4} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R9.reuse, 0x4, R4 &req={5} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MatAddElementThread(int*, int*, int*)
_Z19MatAddElementThreadPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s14, s4
s_cselect_b32 s6, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s6
global_load_u16 v5, v1, s[2:3]
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshr_b32 s2, s5, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s4, s[14:15]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v3, v5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MatAddElementThread | 638 | 797 | stackv2-00000-of-00015 |
// Demangled: MatMulElementThread(int*, int*, int*, int, int)
Function : _Z19MatMulElementThreadPiS_S_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R8, c[0x0][0x39c] &wr=0x1 ?trans1;
S2R R5, SR_TID.Y &wr=0x2 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x3 ?trans1;
S2R R7, SR_CTAID.X &wr=0x3 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x4 ?trans4;
S2UR UR4, SR_CTAID.Y &wr=0x2 ?trans1;
S2R R11, SR_TID.X &wr=0x4 ?trans7;
LDC R0, c[0x0][0x364] &wr=0x2 ?trans1;
IABS R13, R8 &req={1} ?WAIT4_END_GROUP;
I2F.RP R4, R13 &wr=0x1 ?trans1;
IMAD R0, R0, UR4, R5 &req={2} ?trans1;
MUFU.RCP R4, R4 &req={1} &wr=0x1 ?trans3;
IMAD R0, R0, UR5, R7 &req={3} ?WAIT4_END_GROUP;
IMAD R5, R0, UR6, R11 &req={4} ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
LDC.64 R10, c[0x0][0x390] &wr=0x3 ?trans3;
ISETP.GE.AND P2, PT, R5, RZ, PT ?trans1;
IADD3 R2, PT, PT, R4, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x4 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={1} ?trans2;
IMAD.WIDE R10, R5, 0x4, R10 &req={3} ?trans1;
IADD3 R4, PT, PT, RZ, -R3, RZ &req={4} ?WAIT4_END_GROUP;
STG.E desc[UR6][R10.64], RZ &req={2} &rd=0x1 ?trans1;
MOV R0, R4 ?trans1;
IABS R4, R5 ?WAIT4_END_GROUP;
IMAD R7, R0, R13, RZ ?trans1;
MOV R0, R4 ?WAIT3_END_GROUP;
IMAD.HI.U32 R3, R3, R7, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R3, R3, R0, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
IMAD R2, R13.reuse, R3, R0 ?trans2;
LDC R0, c[0x0][0x398] &wr=0x2 ?trans3;
ISETP.GT.U32.AND P0, PT, R13, R2, PT ?WAIT13_END_GROUP;
@!P0 IADD3 R2, PT, PT, R2, -R13, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13, R2, PT ?trans1;
ISETP.GE.AND P1, PT, R0, 0x1, PT &req={2} ?WAIT12_END_GROUP;
@!P0 IADD3 R2, PT, PT, R2, -R13, RZ ?trans1;
ISETP.NE.AND P0, PT, R8, RZ, PT ?trans1;
@!P1 EXIT &req={1,0} ?WAIT12_END_GROUP;
@!P2 IADD3 R2, PT, PT, -R2, RZ, RZ ?trans1;
ISETP.GE.U32.AND P2, PT, R0.reuse, 0x8, PT ?trans1;
LOP3.LUT R3, R0, 0x7, RZ, 0xc0, !PT ?trans1;
UMOV UR4, URZ ?trans1;
@!P0 LOP3.LUT R2, RZ, R8, RZ, 0x33, !PT ?trans1;
MOV R33, RZ ?trans2;
ISETP.NE.AND P1, PT, R3, RZ, PT ?trans1;
IADD3 R5, PT, PT, R5, -R2, RZ ?WAIT6_END_GROUP;
@!P2 BRA 0x7b0 ?trans6;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans1;
LDC.64 R24, c[0x0][0x380] &wr=0x0 ?trans1;
LOP3.LUT R4, R0, 0x7ffffff8, RZ, 0xc0, !PT ?trans1;
HFMA2 R33, -RZ, RZ, 0, 0 ?trans2;
IADD.64 R6, R8, R8 ?WAIT3_END_GROUP;
IADD3 R4, PT, PT, -R4, RZ, RZ ?trans1;
IADD.64 R14, R8, R6 ?trans2;
IMAD.SHL.U32 R12, R6.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R13, R6, 0x2, R7 ?trans1;
IADD.64 R16, R8, R14 ?WAIT3_END_GROUP;
SHF.L.U64.HI R15, R14, 0x2, R15 ?trans1;
IADD.64 R6, R8, R16 ?trans2;
IMAD.SHL.U32 R14, R14, 0x4, RZ ?trans1;
SHF.L.U64.HI R17, R16, 0x2, R17 ?trans1;
IADD.64 R20, R8, R6 ?trans2;
IMAD.SHL.U32 R18, R6.reuse, 0x4, RZ ?trans1;
SHF.L.U64.HI R19, R6, 0x2, R7 ?trans1;
IADD.64 R22, R8, R20 ?trans2;
IADD.64 R24, R24, 0x10 &req={0} ?WAIT2_END_GROUP;
IMAD.SHL.U32 R16, R16, 0x4, RZ ?trans1;
SHF.L.U64.HI R21, R20.reuse, 0x2, R21 ?trans1;
IMAD.SHL.U32 R20, R20, 0x4, RZ ?trans1;
SHF.L.U64.HI R23, R22.reuse, 0x2, R23 ?trans1;
IMAD.SHL.U32 R22, R22, 0x4, RZ ?trans1;
MOV R7, R5 ?trans1;
MOV R6, R2 ?WAIT7_END_GROUP;
LDC.64 R28, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE R26, R7, 0x4, R24 ?WAIT5_END_GROUP;
LDG.E R30, desc[UR6][R26.64+-0x10] &wr=0x2 ?trans1;
IMAD.WIDE R28, R6, 0x4, R28 &req={0} ?WAIT5_END_GROUP;
LDG.E R31, desc[UR6][R28.64] &wr=0x2 ?trans2;
IMAD R37, R30, R31, R33 &req={2,1} ?trans2;
IMAD.WIDE R32, R8, 0x4, R28 ?WAIT3_END_GROUP;
STG.E desc[UR6][R10.64], R37 &rd=0x0 ?trans4;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans4;
LDG.E R30, desc[UR6][R26.64+-0xc] &wr=0x2 ?trans1;
IADD.64 R34, R28, R12 ?trans2;
IMAD R36, R30, R32, R37 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R36 ?trans4;
LDG.E R34, desc[UR6][R34.64] &wr=0x0 ?trans4;
LDG.E R31, desc[UR6][R26.64+-0x8] &wr=0x0 ?trans2;
IMAD R37, R31, R34, R36 &req={0} ?trans1;
IADD.64 R30, R28, R14 ?WAIT4_END_GROUP;
STG.E desc[UR6][R10.64], R37 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R30.64] &wr=0x0 ?trans4;
LDG.E R32, desc[UR6][R26.64+-0x4] &wr=0x0 ?trans2;
IMAD R37, R32, R30, R37 &req={0} ?trans1;
IADD.64 R32, R28, R16 ?WAIT4_END_GROUP;
STG.E desc[UR6][R10.64], R37 &rd=0x0 ?trans4;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans4;
LDG.E R34, desc[UR6][R26.64] &wr=0x2 ?trans2;
IMAD R36, R34, R32, R37 &req={2} ?trans1;
IADD.64 R34, R28, R18 ?WAIT4_END_GROUP;
STG.E desc[UR6][R10.64], R36 &rd=0x1 ?trans4;
LDG.E R34, desc[UR6][R34.64] &wr=0x2 ?trans4;
LDG.E R31, desc[UR6][R26.64+0x4] &wr=0x2 ?trans2;
IMAD R35, R31, R34, R36 &req={2} ?trans1;
IADD.64 R30, R28, R20 ?WAIT4_END_GROUP;
STG.E desc[UR6][R10.64], R35 &rd=0x1 ?trans4;
LDG.E R30, desc[UR6][R30.64] &wr=0x0 ?trans4;
LDG.E R32, desc[UR6][R26.64+0x8] &wr=0x0 ?trans1;
IADD.64 R28, R28, R22 ?WAIT3_END_GROUP;
IADD3 R4, PT, PT, R4, 0x8, RZ ?trans1;
IMAD R37, R32, R30, R35 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R37 &rd=0x1 ?trans4;
LDG.E R32, desc[UR6][R26.64+0xc] &wr=0x2 ?trans4;
LDG.E R28, desc[UR6][R28.64] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?trans1;
IADD3 R7, PT, PT, R7, 0x8, RZ ?trans1;
IMAD R6, R8, 0x8, R6 ?WAIT2_END_GROUP;
IMAD R33, R32, R28, R37 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R33 &rd=0x1 ?trans3;
@P0 BRA 0x4b0 ?trans5;
@!P1 EXIT ?trans5;
ISETP.GE.U32.AND P1, PT, R3, 0x4, PT ?trans1;
LOP3.LUT R22, R0, 0x3, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R22, RZ, PT ?WAIT7_END_GROUP;
@!P1 BRA 0xa00 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R5, UR4, RZ ?trans1;
IMAD R15, R8, UR4, R2 ?WAIT6_END_GROUP;
LDC.64 R12, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R6, R3, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E R4, desc[UR6][R6.64] &wr=0x3 ?trans1;
IMAD.WIDE R12, R15, 0x4, R12 &req={2} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R12.64] &wr=0x3 ?trans1;
IMAD.WIDE R14, R8, 0x4, R12 ?trans1;
SHF.R.S32.HI R19, RZ, 0x1f, R8 ?trans1;
MOV R18, R8 ?trans2;
IMAD R3, R4, R3, R33 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R3 &rd=0x0 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x2 ?trans4;
LDG.E R4, desc[UR6][R6.64+0x4] &wr=0x2 ?trans1;
IADD.64 R20, R18, R18 ?WAIT5_END_GROUP;
LEA R16, P1, R20, R12, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R17, R20, R13, R21, 0x2, P1 ?trans1;
IMAD R23, R4, R14, R3 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R23 &rd=0x2 ?trans4;
LDG.E R16, desc[UR6][R16.64] &wr=0x0 ?trans4;
LDG.E R4, desc[UR6][R6.64+0x8] &wr=0x0 ?trans1;
IADD.64 R18, R18, R20 ?WAIT5_END_GROUP;
LEA R12, P1, R18, R12, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R13, R18, R13, R19, 0x2, P1 ?trans1;
IMAD R3, R4, R16, R23 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R3 &rd=0x2 ?trans4;
LDG.E R4, desc[UR6][R6.64+0xc] &wr=0x3 ?trans4;
LDG.E R12, desc[UR6][R12.64] &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?trans1;
IMAD R33, R4, R12, R3 &req={3,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R33 &rd=0x2 ?trans6;
@!P0 EXIT ?trans5;
ISETP.NE.AND P0, PT, R22, 0x1, PT ?trans1;
LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ?WAIT7_END_GROUP;
@!P0 BRA 0xb50 ?trans6;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R3, PT, PT, R5, UR4, RZ &req={2} ?trans1;
IMAD R15, R8, UR4, R2 ?WAIT6_END_GROUP;
LDC.64 R12, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R6, R3, 0x4, R6 &req={0} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R6.64] &wr=0x3 ?trans1;
IMAD.WIDE R12, R15, 0x4, R12 &req={2} ?WAIT5_END_GROUP;
LDG.E R3, desc[UR6][R12.64] &wr=0x3 ?trans1;
IMAD.WIDE R14, R8, 0x4, R12 ?WAIT4_END_GROUP;
IMAD R3, R0, R3, R33 &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R3 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R6.64+0x4] &wr=0x2 ?trans4;
LDG.E R14, desc[UR6][R14.64] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x2, URZ ?trans1;
IMAD R33, R0, R14, R3 &req={2,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R33 &rd=0x0 ?trans6;
@P1 EXIT ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IADD3 R3, PT, PT, R5, UR4, RZ &req={2,0} ?trans1;
IMAD R5, R8, UR4, R2 ?WAIT6_END_GROUP;
LDC.64 R12, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE R2, R3, 0x4, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE R4, R5, 0x4, R12 &req={0} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR6][R4.64] &wr=0x2 ?trans2;
IMAD R33, R2, R4, R33 &req={2,1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R33 ?trans1;
EXIT ?trans5;
BRA 0xc10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: MatMulElementThread(int*, int*, int*, int, int)
_Z19MatMulElementThreadPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x2c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s14, s4
s_cselect_b32 s6, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s6
global_load_u16 v7, v1, s[2:3]
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshr_b32 s2, s5, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v2, s4, s[14:15]
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, v7, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_cbranch_scc1 .LBB1_3
s_ashr_i32 s2, s7, 31
v_add_nc_u32_e32 v7, v3, v4
s_add_i32 s3, s7, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s3, s2
v_xor_b32_e32 v7, v7, v4
v_cvt_f32_u32_e32 v5, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s2, v5
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s4
v_sub_nc_u32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v4
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v3, v4
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_cmp_eq_u32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
v_add_nc_u32_e32 v6, 1, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v5, v3, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v7
global_store_b32 v[0:1], v7, off
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| MatMulElementThread | 4,979 | 1,892 | stackv2-00000-of-00015 |
// Demangled: f_kernel(unsigned int, unsigned int, float*, float*)
Function : _Z8f_kerneljjPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R0, UR4, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R4, c[0x0][0x384] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT &req={0} ?trans1;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R5, desc[UR4][R2.64] &req={1} &rd=0x0 &wr=0x5 ?trans7;
@!P0 BRA 0x850 ?trans5;
ISETP.GE.U32.AND P0, PT, R4.reuse, 0x4, PT ?trans1;
LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT12_END_GROUP;
@!P0 BRA 0x7c0 ?trans5;
LOP3.LUT R3, R4, 0xfffffffc, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x6d0 ?trans5;
IADD3 R4, PT, PT, -R3, RZ, RZ ?trans2;
PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x8 ?WAIT3_END_GROUP;
ISETP.GT.AND P1, PT, R4, 0xc, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x4e0 ?trans5;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?WAIT13_END_GROUP;
FMUL R4, R5, R5 &req={5} ?trans1;
IADD3 R3, PT, PT, R3, 0x10, RZ ?WAIT3_END_GROUP;
FFMA R4, R4, R5, -R5 ?trans2;
ISETP.GE.AND P1, PT, R3, -0xc, PT ?trans2;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?trans1;
@!P1 BRA 0x1b0 ?trans6;
IADD3 R4, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
ISETP.GT.AND P1, PT, R4, 0x4, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x6b0 ?trans5;
FMUL R4, R5, R5 &req={5} ?trans1;
PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x80 ?trans2;
IADD3 R3, PT, PT, R3, 0x8, RZ ?trans1;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT7_END_GROUP;
ISETP.NE.OR P0, PT, R3, RZ, P0 ?WAIT13_END_GROUP;
@!P0 BRA 0x7c0 ?trans5;
FMUL R4, R5, R5 &req={5} ?trans1;
IADD3 R3, PT, PT, R3, 0x4, RZ ?WAIT3_END_GROUP;
FFMA R4, R4, R5, -R5 ?trans2;
ISETP.NE.AND P0, PT, R3, RZ, PT ?trans2;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?WAIT4_END_GROUP;
FMUL R4, R5, R5 ?WAIT4_END_GROUP;
FFMA R4, R5, R4, -R5 ?WAIT4_END_GROUP;
FMUL R4, R4, 2.5 ?WAIT4_END_GROUP;
FMUL R5, R4, R4 ?WAIT4_END_GROUP;
FFMA R5, R4, R5, -R4 ?WAIT4_END_GROUP;
FMUL R5, R5, 2.5 ?trans1;
@P0 BRA 0x6d0 ?trans6;
ISETP.NE.AND P0, PT, R2, RZ, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x850 ?trans5;
IADD3 R2, PT, PT, -R2, RZ, RZ ?WAIT7_END_GROUP;
IADD3 R2, PT, PT, R2, 0x1, RZ ?trans1;
FMUL R4, R5, R5 &req={5} ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R2, RZ, PT ?trans1;
FFMA R4, R4, R5, -R5 ?WAIT4_END_GROUP;
FMUL R5, R4, 2.5 ?WAIT8_END_GROUP;
@P0 BRA 0x7f0 ?trans5;
LDCU.64 UR6, c[0x0][0x390] &wr=0x1 ?trans2;
LEA R2, P0, R0, UR6, 0x2 &req={1,0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R0, UR7, RZ, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &req={5} ?trans1;
EXIT ?trans5;
BRA 0x8a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: f_kernel(unsigned int, unsigned int, float*, float*)
_Z8f_kerneljjPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_2:
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v2, v2
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, v2, v3, -v2
v_mul_f32_e32 v2, 0x40200000, v2
s_branch .LBB0_2
.LBB0_4:
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| f_kernel | 2,879 | 633 | stackv2-00000-of-00015 |
// Demangled: saxpy_kernel(unsigned int, float, float*, float*)
Function : _Z12saxpy_kerneljfPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x380] &wr=0x2 ?trans7;
LDC R7, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R7, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x384] &wr=0x2 ?trans6;
LDC.64 R2, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R2.64] &wr=0x2 ?trans2;
FFMA R7, R5, UR6, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: saxpy_kernel(unsigned int, float, float*, float*)
_Z12saxpy_kerneljfPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s3, v0
global_store_b32 v[2:3], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| saxpy_kernel | 553 | 509 | stackv2-00000-of-00015 |
// Demangled: greyscale(unsigned char*, unsigned char*)
Function : _Z9greyscalePhS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x230 ?trans7;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R2, R2, UR4, R3 &req={1} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans3;
IMAD.HI R0, R2, 0x55555556, RZ ?WAIT5_END_GROUP;
LEA.HI R3, R0, R0, RZ, 0x1 ?WAIT5_END_GROUP;
IMAD R3, R3, -0x3, R2 ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R3, 0x1, PT ?WAIT13_END_GROUP;
@!P0 BRA 0x1c0 &req={1,0} ?trans5;
ISETP.NE.AND P0, PT, R3, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x150 ?trans5;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans2;
IADD3 R4, PT, PT, R2.reuse, 0x1, RZ ?trans2;
IADD3 R6, PT, PT, R2, 0x2, RZ ?trans1;
MOV.64 R8, R2 ?WAIT3_END_GROUP;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans2;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans1;
BRA 0x220 ?trans6;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans2;
IADD3 R8, PT, PT, R2.reuse, -0x2, RZ ?trans2;
IADD3 R4, PT, PT, R2, -0x1, RZ ?trans1;
MOV.64 R6, R2 ?WAIT3_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans2;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?trans1;
BRA 0x220 ?trans6;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?trans2;
IADD3 R8, PT, PT, R2.reuse, -0x1, RZ ?trans2;
IADD3 R6, PT, PT, R2, 0x1, RZ ?trans1;
MOV.64 R4, R2 ?WAIT3_END_GROUP;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?trans2;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU.128 UR8, c[0x0][0x380] &wr=0x0 ?trans2;
IADD.64 R8, R8, UR10 &req={0} ?trans2;
IADD.64 R4, R4, UR10 ?trans2;
IADD.64 R6, R6, UR10 ?WAIT3_END_GROUP;
LDG.E.U8 R8, desc[UR4][R8.64] &wr=0x2 ?trans4;
LDG.E.U8 R4, desc[UR4][R4.64] &wr=0x3 ?trans4;
LDG.E.U8 R6, desc[UR4][R6.64] &wr=0x4 ?trans1;
IADD.64 R2, R2, UR8 ?trans2;
I2F.U16 R10, R8 &req={2} &wr=0x0 ?trans1;
I2F.U16 R0, R4 &req={3} &wr=0x1 ?trans1;
I2F.U16 R13, R6 &req={4} &wr=0x2 ?trans1;
FMUL R11, R10, 0.29899999499320983887 &req={0} ?WAIT4_END_GROUP;
FFMA R0, R0, 0.58700001239776611328, R11 &req={1} ?WAIT4_END_GROUP;
FFMA R0, R13, 0.11400000005960464478, R0 &req={2} ?WAIT4_END_GROUP;
F2I.U32.TRUNC.NTZ R11, R0 &wr=0x0 ?trans2;
STG.E.U8 desc[UR4][R2.64], R11 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x340;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: greyscale(unsigned char*, unsigned char*)
_Z9greyscalePhS_:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_hi_i32 v0, 0x55555556, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, v0, 1, v0
v_ashrrev_i32_e32 v0, 31, v1
v_sub_nc_u32_e32 v7, v1, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v0, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, 0
v_cmpx_lt_i32_e32 0, v7
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_4
s_mov_b32 s5, -1
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 1, v7
s_cbranch_execz .LBB0_3
global_load_u16 v4, v[2:3], off offset:-1
s_xor_b32 s5, exec_lo, -1
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte1_e32 v5, v4
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x3f1645a2, v5
v_fmamk_f32 v6, v4, 0x3e991687, v5
v_add_co_u32 v4, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s5, exec_lo
.LBB0_4:
s_and_not1_saveexec_b32 s4, s4
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_and_not1_b32 s3, s3, exec_lo
s_mov_b32 s2, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s5
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s4
s_cbranch_execz .LBB0_8
global_load_u16 v4, v[2:3], off offset:-2
s_and_not1_b32 s2, s2, exec_lo
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte1_e32 v5, v4
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x3f1645a2, v5
v_dual_fmamk_f32 v6, v4, 0x3e991687, v5 :: v_dual_mov_b32 v5, v3
v_mov_b32_e32 v4, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
global_load_u16 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte1_e32 v5, v4
v_cvt_f32_ubyte0_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x3f1645a2, v5
v_fmamk_f32 v6, v4, 0x3e991687, v5
v_add_co_u32 v4, vcc_lo, v2, 2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
global_load_u8 v2, v[4:5], off
v_add_co_u32 v1, vcc_lo, s0, v1
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v3, v2, 0x3de978d5, v6
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v0, vcc_lo
v_cvt_i32_f32_e32 v0, v3
global_store_b8 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| greyscale | 1,338 | 1,621 | stackv2-00000-of-00015 |
// Demangled: wave1Drusanov1(double*, double*, double, int)
Function : _Z14wave1Drusanov1PdS_di
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R3, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans1;
IADD3 R2, PT, PT, R0, 0x1, RZ ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
ISETP.NE.AND P0, PT, R2, UR6, PT ?WAIT5_END_GROUP;
SEL R3, R2, RZ, P0 ?trans1;
IMAD.WIDE R4, R0, 0x8, R6 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R3, 0x8, R6 ?trans2;
LDG.E.64 R4, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR4][R6.64] &wr=0x2 ?trans1;
MUFU.RCP64H R3, -3 &wr=0x0 ?trans1;
MOV.64 R10, 0x4008000000000000 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT6_END_GROUP;
DFMA R8, R2, R10, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R8, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R2, R8, R2 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R8, R10, 1 &req={0} &rd=0x0 &wr=0x1 ?trans2;
LDC.64 R10, c[0x0][0x390] &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R8, R2, R8 &req={1} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R2, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R8, 3, R10 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R10, R8 &req={0} &rd=0x0 &wr=0x1 ?trans2;
LDC R9, c[0x0][0x394] &req={0} &wr=0x0 ?trans1;
FFMA R8, RZ, -2.125, R3 &req={1} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ?trans1;
FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT10_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R6, R4 &req={2} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA P1, 0x440 &req={1,0} ?trans5;
MOV R10, 0x440 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x520 ?trans5;
DADD R4, R6, -R4 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R4, R4, R2 &req={0} &rd=0x0 &wr=0x1 ?trans2;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R2, R0, 0x8, R2 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R4, R8, 0.5, R4 &req={1} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64], R4 &req={0} ?trans1;
EXIT ?trans5;
LDC.64 R18, c[0x0][0x390] &wr=0x0 ?trans1;
MOV.64 R2, 0xbff8000000000000 ?trans2;
MOV R22, 0x1ca00000 ?trans1;
HFMA2 R12, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans2;
MUFU.RCP64H R13, R3 &wr=0x1 ?trans1;
HFMA2 R24, -RZ, RZ, 2, 0 ?WAIT5_END_GROUP;
IADD3 R26, PT, PT, R24, -0x1, RZ ?trans2;
LOP3.LUT R11, R19.reuse, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?trans1;
DFMA R14, R12, -R2, 1 &req={1} &wr=0x0 ?trans1;
FSETP.GEU.AND P1, PT, |R19|, 1.469367938527859385e-39, PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, 0x40000000, PT ?trans1;
MOV R23, R11 ?WAIT4_END_GROUP;
SEL R22, R22, 0x63400000, !P0 ?WAIT5_END_GROUP;
@!P1 LOP3.LUT R16, R22, 0x80000000, R19, 0xf8, !PT ?WAIT4_END_GROUP;
@!P1 LOP3.LUT R17, R16, 0x100000, RZ, 0xfc, !PT ?trans1;
@!P1 MOV R16, RZ ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R14, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R12, R14, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R14, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R12, R14 &req={0} &rd=0x0 ?trans2;
LOP3.LUT R13, R22, 0x800fffff, R19, 0xf8, !PT &req={0} ?trans1;
MOV R12, R18 ?WAIT15_END_GROUP;
NOP ?trans1;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DFMA R12, R12, 2, -R16 &wr=0x0 ?trans2;
@!P1 LOP3.LUT R23, R13, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?WAIT4_END_GROUP;
IADD3 R25, PT, PT, R23, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R25, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R16, R14, R12 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R20, R16, -R2, R12 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R20, R16 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xac0 &req={1,0} ?trans5;
IADD3 R11, PT, PT, R11, -0x40000000, RZ ?trans1;
MOV R18, RZ ?WAIT4_END_GROUP;
VIMNMX.S32 R11, R11, -0x46a00000, !PT ?WAIT5_END_GROUP;
VIMNMX.S32 R11, R11, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, -R22, R11, RZ ?WAIT4_END_GROUP;
IADD3 R19, PT, PT, R11, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R16, R14, R18 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0xbd0 ?trans5;
DFMA R2, R14, -R2, R12 &wr=0x0 ?trans1;
MOV R18, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R2, R3, 0xc0080000, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
LOP3.LUT R13, R2, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R19, R13, R19, RZ, 0xfc, !PT ?WAIT4_END_GROUP;
@!P0 BRA 0xbd0 ?trans5;
IADD3 R3, PT, PT, -R11.reuse, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
IADD3 R11, PT, PT, -R11, -0x43300000, RZ ?WAIT5_END_GROUP;
DFMA R2, R16, -R2, R14 &wr=0x0 ?trans2;
FSETP.NEU.AND P0, PT, |R3|, R11, PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL.RP R14, R14, R18 &wr=0x0 ?trans2;
LOP3.LUT R13, R15, R13, RZ, 0x3c, !PT &req={0} ?trans1;
FSEL R16, R14, R16, !P0 ?WAIT4_END_GROUP;
FSEL R17, R13, R17, !P0 ?trans1;
BRA 0xbd0 ?trans6;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans2;
DSETP.NAN.AND P0, PT, R2, R2, PT &req={0} &wr=0x0 ?trans2;
@P0 BRA 0xbb0 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R23, R24, PT ?trans1;
MOV.64 R16, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0xbd0 ?trans5;
ISETP.NE.AND P0, PT, R23, 0x7ff00000, PT ?trans1;
LOP3.LUT R19, R19, 0xc0080000, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R24, RZ, !P0 ?trans1;
LOP3.LUT R17, R19, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R16, RZ ?trans1;
@P0 MOV R16, RZ ?WAIT3_END_GROUP;
@P0 MOV R17, R2 ?trans1;
BRA 0xbd0 ?trans6;
LOP3.LUT R17, R19, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R18 ?WAIT7_END_GROUP;
MOV R11, 0x0 ?trans1;
MOV R2, R16 ?trans1;
MOV R3, R17 ?trans2;
RET.REL.NODEC R10 0x0 ?trans5;
BRA 0xc10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: wave1Drusanov1(double*, double*, double, int)
_Z14wave1Drusanov1PdS_di:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v0, 1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s8, 0
s_mov_b32 s9, 0xc0080000
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ne_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v3, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[5:6], null, s[8:9], s[8:9], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[7:8], v[7:8], off
v_div_scale_f64 v[13:14], vcc_lo, s[6:7], 0xc0080000, s[6:7]
v_rcp_f64_e32 v[9:10], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[5:6], v[11:12], v[13:14]
v_div_fmas_f64 v[4:5], v[4:5], v[9:10], v[11:12]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[9:10], v[2:3], -v[7:8]
v_add_f64 v[2:3], v[2:3], v[7:8]
v_div_fixup_f64 v[4:5], v[4:5], 0xc0080000, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[9:10]
v_fma_f64 v[2:3], v[2:3], 0.5, v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| wave1Drusanov1 | 4,062 | 1,350 | stackv2-00000-of-00015 |
// Demangled: VecAdd_kernel(float const*, float const*, float*, int)
Function : _Z13VecAdd_kernelPKfS0_Pfi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
EXIT ?trans5;
BRA 0x20;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: VecAdd_kernel(float const*, float const*, float*, int)
_Z13VecAdd_kernelPKfS0_Pfi:
s_endpgm
| VecAdd_kernel | 99 | 19 | stackv2-00000-of-00015 |
// Demangled: countLettersGlobal(unsigned char*, unsigned int*, unsigned int*, unsigned long)
Function : _Z18countLettersGlobalPhPjS0_m
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans7;
LDC.64 R8, c[0x0][0x398] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans7;
LDC.64 R2, c[0x0][0x390] &wr=0x4 ?trans1;
ISETP.NE.S64.AND P0, PT, R8, RZ, PT &req={2} ?WAIT2_END_GROUP;
IMAD R7, R5, 0x1a, RZ &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R6, R7, 0x4, R2 &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], RZ &req={3} &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x4], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x8], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0xc], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x10], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x14], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x18], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x1c], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x20], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x24], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x28], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x2c], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x30], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x34], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x38], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x3c], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x40], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x44], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x48], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x4c], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x50], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x54], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x58], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x5c], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x60], RZ &rd=0x1 ?trans4;
STG.E desc[UR6][R6.64+0x64], RZ &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0xa10 &req={0} ?trans5;
LDCU UR8, c[0x0][0x398] &wr=0x0 ?trans1;
ISETP.GE.U64.AND P1, PT, R8, 0x8, PT ?trans2;
HFMA2 R19, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R8, RZ ?trans2;
ULOP3.LUT UR4, UR8, 0x7, URZ, 0xc0, !UPT &req={0} ?WAIT6_END_GROUP;
MOV R18, UR4 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R18, RZ, PT ?trans2;
@!P1 BRA 0x5f0 ?WAIT12_END_GROUP;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x39c] &wr=0x2 ?trans1;
MOV.64 R8, RZ ?trans2;
ULOP3.LUT UR4, UR8, 0xfffffff8, URZ, 0xc0, !UPT ?trans2;
IMAD.WIDE.U32 R10, R5, UR8, R10 &req={0} ?WAIT4_END_GROUP;
IMAD R11, R5, UR5, R11 &req={2} ?WAIT7_END_GROUP;
LDG.E.U8 R13, desc[UR6][R10.64] &req={0} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R12.64] &wr=0x2 ?trans2;
IADD3 R21, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R21 &rd=0x0 ?trans4;
LDG.E.U8 R15, desc[UR6][R10.64+0x1] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R14, R15, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R14.64] &wr=0x2 ?trans2;
IADD3 R23, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R23 &rd=0x2 ?trans4;
LDG.E.U8 R17, desc[UR6][R10.64+0x2] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R16, R17, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R16.64] &wr=0x3 ?trans2;
IADD3 R25, PT, PT, R0, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R25 &rd=0x3 ?trans4;
LDG.E.U8 R13, desc[UR6][R10.64+0x3] &req={0} &wr=0x4 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R6 &req={4} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R12.64] &wr=0x4 ?trans2;
IADD3 R21, PT, PT, R0, 0x1, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R21 &rd=0x0 ?trans4;
LDG.E.U8 R15, desc[UR6][R10.64+0x4] &req={2} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R14, R15, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R14.64] &wr=0x2 ?trans2;
IADD3 R23, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R23 &rd=0x2 ?trans4;
LDG.E.U8 R17, desc[UR6][R10.64+0x5] &req={3} &wr=0x3 ?trans2;
IMAD.WIDE.U32 R16, R17, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R16.64] &wr=0x3 ?trans2;
IADD3 R25, PT, PT, R0, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R25 &rd=0x3 ?trans4;
LDG.E.U8 R13, desc[UR6][R10.64+0x6] &req={0} &wr=0x4 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R6 &req={4} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R12.64] &wr=0x4 ?trans2;
IADD3 R21, PT, PT, R0, 0x1, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R21 &rd=0x0 ?trans4;
LDG.E.U8 R15, desc[UR6][R10.64+0x7] &req={2} &wr=0x2 ?trans2;
IMAD.WIDE.U32 R14, R15, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R14.64] &wr=0x2 ?trans1;
IADD.64 R8, R8, 0x8 ?trans2;
IADD.64 R10, R10, 0x8 ?trans2;
IADD.64 R16, R8, -UR4 &req={3} ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P1, PT, R16, RZ, PT ?WAIT3_END_GROUP;
IADD3 R23, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R23 &rd=0x0 ?trans6;
@P1 BRA 0x320 ?trans5;
@!P0 BRA 0xa10 ?trans5;
ISETP.GE.U64.AND P0, PT, R18, 0x4, PT ?trans2;
ULOP3.LUT UR4, UR8, 0x3, URZ, 0xc0, !UPT ?trans1;
HFMA2 R21, -RZ, RZ, 0, 0 &req={0} ?WAIT5_END_GROUP;
MOV R20, UR4 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P1, PT, R20, RZ, PT ?trans2;
@!P0 BRA 0x800 ?WAIT12_END_GROUP;
LDCU UR4, c[0x0][0x39c] &wr=0x0 ?trans1;
IMAD.WIDE.U32 R10, R5.reuse, UR8, R8 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x2 ?trans3;
IMAD R11, R5, UR4, R11 &req={0} ?WAIT5_END_GROUP;
IADD.64 R10, R10, UR10 &req={2} ?WAIT6_END_GROUP;
LDG.E.U8 R13, desc[UR6][R10.64] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R12.64] &wr=0x2 ?trans2;
IADD3 R19, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R19 &rd=0x0 ?trans4;
LDG.E.U8 R15, desc[UR6][R10.64+0x1] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R14, R15, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R14.64] &wr=0x2 ?trans2;
IADD3 R23, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R23 &rd=0x2 ?trans4;
LDG.E.U8 R17, desc[UR6][R10.64+0x2] &wr=0x3 ?trans2;
IMAD.WIDE.U32 R16, R17, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R16.64] &wr=0x3 ?trans2;
IADD3 R25, PT, PT, R0, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R25 &rd=0x2 ?trans4;
LDG.E.U8 R13, desc[UR6][R10.64+0x3] &req={0} &wr=0x3 ?trans2;
IMAD.WIDE.U32 R12, R13, 0x4, R6 &req={3} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R12.64] &wr=0x3 ?trans1;
IADD.64 R8, R8, 0x4 ?WAIT3_END_GROUP;
IADD3 R19, PT, PT, R0, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R19 &rd=0x2 ?trans2;
@!P1 BRA 0xa10 ?trans5;
ISETP.NE.S64.AND P0, PT, R20, 0x1, PT ?WAIT14_END_GROUP;
@P0 LDC R0, c[0x0][0x39c] &wr=0x0 ?trans1;
@P0 IMAD.WIDE.U32 R10, R5, UR8, R8 ?WAIT7_END_GROUP;
@P0 LDC.64 R12, c[0x0][0x380] &req={2} &wr=0x2 ?trans1;
@P0 IMAD R11, R5, R0, R11 &req={0} ?WAIT5_END_GROUP;
@P0 IADD.64 R16, R10, R12 &req={2} ?WAIT6_END_GROUP;
@P0 LDG.E.U8 R11, desc[UR6][R16.64] &wr=0x2 ?trans2;
@P0 IMAD.WIDE.U32 R10, R11, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
@P0 LDG.E R0, desc[UR6][R10.64] &wr=0x2 ?trans2;
@P0 IADD3 R19, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR6][R10.64], R19 &rd=0x3 ?trans4;
@P0 LDG.E.U8 R13, desc[UR6][R16.64+0x1] &wr=0x2 ?trans2;
@P0 IMAD.WIDE.U32 R12, R13, 0x4, R6 &req={2} ?WAIT5_END_GROUP;
@P0 LDG.E R0, desc[UR6][R12.64] &wr=0x2 ?trans1;
ULOP3.LUT UR4, UR8, 0x1, URZ, 0xc0, !UPT ?trans1;
MOV R15, RZ ?trans1;
@P0 IADD.64 R8, R8, 0x2 ?WAIT4_END_GROUP;
MOV R14, UR4 ?WAIT5_END_GROUP;
ISETP.NE.U64.AND P1, PT, R14, 0x1, PT ?WAIT3_END_GROUP;
@P0 IADD3 R21, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
@P0 STG.E desc[UR6][R12.64], R21 &rd=0x3 ?trans6;
@P1 BRA 0xa10 ?trans5;
LDCU UR4, c[0x0][0x39c] &wr=0x0 ?trans1;
IMAD.WIDE.U32 R8, R5.reuse, UR8, R8 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x2 ?trans3;
IMAD R9, R5, UR4, R9 &req={0} ?WAIT5_END_GROUP;
IADD.64 R8, R8, UR10 &req={2} ?WAIT7_END_GROUP;
LDG.E.U8 R9, desc[UR6][R8.64] &wr=0x2 ?trans2;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={2,1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R6.64] &wr=0x2 ?trans2;
IADD3 R11, PT, PT, R0, 0x1, RZ &req={3,2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x4 ?trans2;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x19, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R6, c[0x0][0x388] &req={4,1} &wr=0x1 ?trans2;
IMAD.WIDE.U32 R6, R5, 0x4, R6 &req={1} ?WAIT5_END_GROUP;
LDG.E R11, desc[UR6][R6.64] &req={3} &rd=0x1 &wr=0x5 ?trans1;
MOV.64 R8, 0x340 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 ?WAIT7_END_GROUP;
IADD.64 R4, R2, R8 ?WAIT6_END_GROUP;
LDG.E R0, desc[UR6][R4.64+-0x340] &req={3} &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R0, R11, RZ &req={5,3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0x2d8] &wr=0x4 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={4,2,0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0x270] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0x208] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0x1a0] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0x138] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0xd0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+-0x68] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x68] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xd0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x138] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1a0] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x208] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x270] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x2d8] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x340] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x3a8] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x410] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x478] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x4e0] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x548] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x5b0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x618] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x680] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x6e8] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x750] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x7b8] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x820] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x888] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x8f0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x958] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x9c0] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xa28] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xa90] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xaf8] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xb60] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xbc8] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xc30] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xc98] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xd00] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xd68] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xdd0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xe38] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xea0] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xf08] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xf70] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0xfd8] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1040] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R0, R17, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x10a8] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1110] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1178] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x11e0] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1248] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x12b0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1318] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x4 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1380] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R17, R0, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x13e8] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R11, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x0 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1450] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x2 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x14b8] &wr=0x4 ?trans2;
IADD3 R17, PT, PT, R15, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R17 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1520] &wr=0x4 ?trans2;
IADD3 R19, PT, PT, R17, R0, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R19 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1588] &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R19, R0, RZ &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R13 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x15f0] &wr=0x2 ?trans2;
IADD3 R15, PT, PT, R13, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R15 &rd=0x3 ?trans4;
LDG.E R0, desc[UR6][R4.64+0x1658] &wr=0x2 ?trans1;
IADD.64 R8, R8, 0x1a00 ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P0, PT, R8, 0xb940, PT ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R15, R0, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R6.64], R11 &rd=0x3 ?trans6;
@P0 BRA 0xa90 ?trans5;
EXIT ?trans5;
BRA 0x16e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: countLettersGlobal(unsigned char*, unsigned int*, unsigned int*, unsigned long)
_Z18countLettersGlobalPhPjS0_m:
s_load_b256 s[0:7], s[0:1], 0x0
v_mul_u32_u24_e32 v1, 26, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s8, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s5, 0, s8
s_mov_b64 s[8:9], 0
.LBB2_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v3, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_lg_u64 s[8:9], 0x68
global_store_b32 v[5:6], v1, off
s_cbranch_scc1 .LBB2_1
s_cmp_eq_u64 s[6:7], 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_5
v_mad_u64_u32 v[1:2], null, v0, s6, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, s7, v[2:3]
v_mov_b32_e32 v2, v5
.LBB2_4:
global_load_u8 v5, v[1:2], off
s_add_u32 s6, s6, -1
s_addc_u32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u64 s[6:7], 0
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
v_add_co_u32 v5, vcc_lo, v3, v5
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
global_store_b32 v[5:6], v7, off
s_cbranch_scc0 .LBB2_4
.LBB2_5:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_gt_u32_e32 26, v0
s_cbranch_execz .LBB2_8
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v2, v0, s[2:3]
v_add_co_u32 v3, s0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s5, 0, s0
v_add_co_u32 v0, s0, s2, v0
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
s_mov_b64 s[0:1], 0
.LBB2_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_add_u32 s0, s0, 0x68
s_addc_u32 s1, s1, 0
s_cmp_lg_u64 s[0:1], 0xb600
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v5, v2
global_store_b32 v[0:1], v2, off
s_cbranch_scc1 .LBB2_7
.LBB2_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| countLettersGlobal | 10,857 | 1,316 | stackv2-00000-of-00015 |
// Demangled: countLettersShared(unsigned char*, unsigned int*, unsigned long)
Function : _Z18countLettersSharedPhPjm
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_CgaCtaId &wr=0x1 ?trans1;
MOV R0, 0x400 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R5, SR_TID.X &wr=0x3 ?trans3;
LEA R0, R3, R0, 0x18 &req={1} ?trans2;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans3;
IMAD R4, R5, 0x68, R0 &req={3} ?WAIT5_END_GROUP;
STS.64 [R4], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x8], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x10], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x18], RZ &rd=0x3 ?trans1;
ISETP.NE.S64.AND P0, PT, R2, RZ, PT &req={1} ?WAIT3_END_GROUP;
STS.64 [R4+0x20], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x28], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x30], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x38], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x40], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x48], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x50], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x58], RZ &rd=0x3 ?trans4;
STS.64 [R4+0x60], RZ &rd=0x3 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P0 BRA 0xdf0 &req={2,0} ?trans5;
LDCU UR8, c[0x0][0x390] &wr=0x0 ?trans1;
ISETP.GE.U64.AND P1, PT, R2, 0x10, PT ?trans2;
HFMA2 R23, -RZ, RZ, 0, 0 ?trans1;
MOV.64 R2, RZ ?trans2;
ULOP3.LUT UR4, UR8, 0xf, URZ, 0xc0, !UPT &req={0} ?WAIT6_END_GROUP;
MOV R22, UR4 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P0, PT, R22, RZ, PT ?trans2;
@!P1 BRA 0x7b0 ?WAIT12_END_GROUP;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR5, c[0x0][0x394] &wr=0x1 ?trans1;
MOV.64 R2, RZ ?trans2;
ULOP3.LUT UR4, UR8, 0xfffffff0, URZ, 0xc0, !UPT ?trans2;
IMAD.WIDE.U32 R6, R5, UR8, R6 &req={0} ?WAIT4_END_GROUP;
IMAD R7, R5, UR5, R7 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R9, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E.U8 R13, desc[UR6][R6.64+0x1] &wr=0x4 ?trans4;
LDG.E.U8 R15, desc[UR6][R6.64+0x2] &wr=0x5 ?trans4;
LDG.E.U8 R25, desc[UR6][R6.64+0x3] &req={3} &wr=0x3 ?trans4;
LDG.E.U8 R27, desc[UR6][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E.U8 R29, desc[UR6][R6.64+0x5] &wr=0x3 ?trans4;
LDG.E.U8 R11, desc[UR6][R6.64+0x6] &wr=0x3 ?trans1;
IMAD R8, R9, 0x4, R4 &req={2} ?WAIT3_END_GROUP;
LDG.E.U8 R9, desc[UR6][R6.64+0x7] &wr=0x2 ?trans4;
LDS R10, [R8] &wr=0x0 ?trans2;
IADD3 R17, PT, PT, R10, 0x1, RZ &req={0} ?trans1;
IMAD R10, R13, 0x4, R4.reuse &req={4} ?trans2;
LDG.E.U8 R13, desc[UR6][R6.64+0x8] &wr=0x4 ?trans4;
STS [R8], R17 &rd=0x0 ?trans4;
LDS R12, [R10] &wr=0x1 ?trans1;
IMAD R25, R25, 0x4, R4 &req={3} ?WAIT3_END_GROUP;
LDG.E.U8 R17, desc[UR6][R6.64+0xa] &req={0} &wr=0x3 ?trans1;
IADD3 R19, PT, PT, R12, 0x1, RZ &req={1} ?trans1;
IMAD R12, R15, 0x4, R4.reuse &req={5} ?trans2;
LDG.E.U8 R15, desc[UR6][R6.64+0x9] &wr=0x5 ?trans4;
STS [R10], R19 &rd=0x0 ?trans4;
LDS R14, [R12] &wr=0x1 ?trans1;
IMAD R27, R27, 0x4, R4 ?WAIT3_END_GROUP;
LDG.E.U8 R19, desc[UR6][R6.64+0xb] &req={0} &wr=0x3 ?trans1;
IADD3 R21, PT, PT, R14, 0x1, RZ &req={1} ?WAIT5_END_GROUP;
STS [R12], R21 &rd=0x0 ?trans4;
LDS R8, [R25] &wr=0x1 ?trans1;
IMAD R29, R29, 0x4, R4 ?WAIT3_END_GROUP;
LDG.E.U8 R21, desc[UR6][R6.64+0xc] &req={0} &wr=0x3 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ &req={1} ?WAIT5_END_GROUP;
STS [R25], R8 ?trans4;
LDS R10, [R27] &wr=0x0 ?trans2;
IADD3 R10, PT, PT, R10, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R27], R10 ?trans4;
LDS R12, [R29] &wr=0x0 ?trans1;
IMAD R14, R11, 0x4, R4 ?WAIT3_END_GROUP;
LDG.E.U8 R11, desc[UR6][R6.64+0xd] &wr=0x3 ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R29], R12 &rd=0x0 ?trans4;
LDS R8, [R14] &wr=0x1 ?trans4;
LDG.E.U8 R29, desc[UR6][R6.64+0xf] &req={0} &wr=0x3 ?trans1;
IADD3 R25, PT, PT, R8, 0x1, RZ &req={1} ?trans1;
IMAD R8, R9, 0x4, R4 &req={2} ?WAIT2_END_GROUP;
LDG.E.U8 R9, desc[UR6][R6.64+0xe] &wr=0x2 ?trans4;
STS [R14], R25 ?trans4;
LDS R10, [R8] &wr=0x0 ?trans1;
IMAD R13, R13, 0x4, R4 &req={4} ?trans1;
IADD3 R27, PT, PT, R10, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R8], R27 ?trans4;
LDS R10, [R13] &wr=0x0 ?trans1;
IMAD R15, R15, 0x4, R4 &req={5} ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R13], R10 ?trans4;
LDS R12, [R15] &wr=0x0 ?trans1;
IMAD R17, R17, 0x4, R4 &req={3} ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R15], R12 ?trans4;
LDS R14, [R17] &wr=0x0 ?trans1;
IMAD R19, R19, 0x4, R4 ?trans1;
IADD3 R14, PT, PT, R14, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R17], R14 ?trans4;
LDS R8, [R19] &wr=0x0 ?trans1;
IMAD R21, R21, 0x4, R4 ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R19], R8 ?trans4;
LDS R10, [R21] &wr=0x0 ?trans1;
IMAD R11, R11, 0x4, R4 ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R21], R10 ?trans4;
LDS R12, [R11] &wr=0x0 ?trans1;
IMAD R13, R9, 0x4, R4 &req={2} ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R11], R12 ?trans4;
LDS R9, [R13] &wr=0x0 ?trans1;
IMAD R29, R29, 0x4, R4 ?trans1;
IADD3 R14, PT, PT, R9, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R13], R14 ?trans4;
LDS R8, [R29] &wr=0x0 ?trans1;
IADD.64 R2, R2, 0x10 ?trans2;
IADD.64 R6, R6, 0x10 ?WAIT3_END_GROUP;
IADD3 R16, PT, PT, R8, 0x1, RZ &req={0} ?trans1;
IADD.64 R8, R2, -UR4 ?WAIT4_END_GROUP;
STS [R29], R16 &rd=0x0 ?trans2;
ISETP.NE.S64.AND P1, PT, R8, RZ, PT ?WAIT14_END_GROUP;
@P1 BRA 0x260 &req={0} ?trans5;
@!P0 BRA 0xdf0 ?trans5;
ISETP.GE.U64.AND P0, PT, R22, 0x8, PT ?trans2;
ULOP3.LUT UR4, UR8, 0x7, URZ, 0xc0, !UPT ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
MOV R14, UR4 ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P1, PT, R14, RZ, PT ?trans2;
@!P0 BRA 0xb00 ?WAIT12_END_GROUP;
LDCU UR4, c[0x0][0x394] &wr=0x0 ?trans1;
IMAD.WIDE.U32 R6, R5.reuse, UR8, R2 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x1 ?trans3;
IMAD R7, R5, UR4, R7 &req={0} ?WAIT5_END_GROUP;
IADD.64 R6, R6, UR10 &req={1} ?WAIT6_END_GROUP;
LDG.E.U8 R9, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E.U8 R11, desc[UR6][R6.64+0x1] &wr=0x4 ?trans4;
LDG.E.U8 R13, desc[UR6][R6.64+0x2] &wr=0x5 ?trans4;
LDG.E.U8 R17, desc[UR6][R6.64+0x3] &req={3} &wr=0x3 ?trans4;
LDG.E.U8 R19, desc[UR6][R6.64+0x4] &wr=0x3 ?trans4;
LDG.E.U8 R21, desc[UR6][R6.64+0x5] &wr=0x3 ?trans4;
LDG.E.U8 R23, desc[UR6][R6.64+0x6] &wr=0x3 ?trans4;
LDG.E.U8 R25, desc[UR6][R6.64+0x7] &rd=0x0 &wr=0x3 ?trans1;
IMAD R9, R9, 0x4, R4 &req={2} ?WAIT5_END_GROUP;
LDS R8, [R9] &wr=0x1 ?trans1;
IMAD R11, R11, 0x4, R4 &req={4} ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ &req={1} ?WAIT5_END_GROUP;
STS [R9], R8 ?trans4;
LDS R10, [R11] &wr=0x1 ?trans1;
IMAD R13, R13, 0x4, R4 &req={5} ?trans1;
IADD3 R10, PT, PT, R10, 0x1, RZ &req={1} ?WAIT5_END_GROUP;
STS [R11], R10 ?trans4;
LDS R12, [R13] &wr=0x1 ?trans1;
IMAD R17, R17, 0x4, R4 &req={3} ?trans1;
IADD3 R12, PT, PT, R12, 0x1, RZ &req={1} ?WAIT5_END_GROUP;
STS [R13], R12 ?trans4;
LDS R6, [R17] &req={0} &wr=0x0 ?trans1;
IMAD R19, R19, 0x4, R4 ?trans1;
IADD3 R6, PT, PT, R6, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R17], R6 ?trans4;
LDS R7, [R19] &wr=0x0 ?trans1;
IMAD R21, R21, 0x4, R4 ?trans1;
IADD3 R8, PT, PT, R7, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R19], R8 ?trans4;
LDS R7, [R21] &wr=0x0 ?trans1;
IMAD R23, R23, 0x4, R4 ?trans1;
IADD3 R10, PT, PT, R7, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R21], R10 ?trans4;
LDS R7, [R23] &wr=0x0 ?trans1;
IMAD R25, R25, 0x4, R4 ?trans1;
IADD3 R12, PT, PT, R7, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R23], R12 ?trans4;
LDS R6, [R25] &wr=0x0 ?trans1;
IADD.64 R2, R2, 0x8 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R6, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R25], R6 &rd=0x0 ?trans2;
@!P1 BRA 0xdf0 ?trans5;
ISETP.GE.U64.AND P0, PT, R14, 0x4, PT ?trans2;
ULOP3.LUT UR4, UR8, 0x3, URZ, 0xc0, !UPT ?trans1;
UMOV UR5, URZ ?WAIT5_END_GROUP;
ISETP.NE.S64.AND P1, PT, RZ, UR4, PT ?WAIT6_END_GROUP;
@!P0 BRA 0xd00 ?trans8;
LDCU UR9, c[0x0][0x394] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R6, R5.reuse, UR8, R2 &req={0} ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x0 ?trans3;
IMAD R7, R5, UR9, R7 &req={1} ?WAIT5_END_GROUP;
IADD.64 R6, R6, UR10 &req={0} ?WAIT6_END_GROUP;
LDG.E.U8 R9, desc[UR6][R6.64] &wr=0x2 ?trans4;
LDG.E.U8 R13, desc[UR6][R6.64+0x1] &wr=0x4 ?trans4;
LDG.E.U8 R15, desc[UR6][R6.64+0x2] &wr=0x5 ?trans4;
LDG.E.U8 R17, desc[UR6][R6.64+0x3] &req={3} &wr=0x3 ?trans1;
IADD.64 R2, R2, 0x4 ?WAIT2_END_GROUP;
IMAD R11, R9, 0x4, R4.reuse &req={2} ?trans2;
IMAD R12, R13, 0x4, R4 &req={4} ?WAIT3_END_GROUP;
LDS R8, [R11] &wr=0x0 ?trans1;
IMAD R15, R15, 0x4, R4.reuse &req={5} ?trans2;
IMAD R17, R17, 0x4, R4 &req={3} ?trans1;
IADD3 R8, PT, PT, R8, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R11], R8 ?trans4;
LDS R9, [R12] &wr=0x0 ?trans2;
IADD3 R9, PT, PT, R9, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R12], R9 ?trans4;
LDS R10, [R15] &wr=0x0 ?trans2;
IADD3 R10, PT, PT, R10, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R15], R10 ?trans4;
LDS R6, [R17] &wr=0x0 ?trans2;
IADD3 R6, PT, PT, R6, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R17], R6 &rd=0x1 ?trans2;
@!P1 BRA 0xdf0 ?trans5;
LDCU UR9, c[0x0][0x394] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R2, R5.reuse, UR8, R2 ?trans1;
LDCU.64 UR10, c[0x0][0x380] &wr=0x4 ?trans3;
IMAD R3, R5, UR9, R3 &req={2} ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR10 &req={4} ?WAIT8_END_GROUP;
LDG.E.U8 R7, desc[UR6][R2.64] &req={2} &rd=0x2 &wr=0x4 ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, -0x1, URZ ?WAIT6_END_GROUP;
ISETP.NE.S64.AND P0, PT, RZ, UR4, PT ?trans2;
IADD.64 R2, R2, 0x1 &req={2} ?trans2;
IMAD R7, R7, 0x4, R4 &req={4} ?WAIT5_END_GROUP;
LDS R6, [R7] &req={1,0} &wr=0x0 ?trans2;
IADD3 R6, PT, PT, R6, 0x1, RZ &req={0} ?WAIT5_END_GROUP;
STS [R7], R6 &rd=0x2 ?trans1;
@P0 BRA 0xd60 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R5, 0x19, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x388] &wr=0x4 ?trans2;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={4} ?WAIT5_END_GROUP;
LDG.E R15, desc[UR6][R2.64] &rd=0x4 &wr=0x5 ?trans1;
IMAD R0, R5, 0x4, R0 ?trans1;
UMOV.64 UR4, 0x1c0 ?WAIT4_END_GROUP;
IADD3 R0, PT, PT, R0, 0x340, RZ ?WAIT7_END_GROUP;
LDS R14, [R0+-0x340] ?trans1;
UIADD3.64 UR4, UPT, UPT, UR4, -0x70, URZ ?WAIT3_END_GROUP;
LDS R16, [R0+-0x2d8] &wr=0x0 ?trans3;
ISETP.NE.S64.AND P0, PT, RZ, UR4, PT ?trans2;
LDS R17, [R0+-0x270] &req={1} ?trans4;
LDS R20, [R0+-0x208] &wr=0x1 ?trans4;
LDS R23, [R0+-0x1a0] ?trans4;
LDS R22, [R0+-0x138] &wr=0x2 ?trans4;
LDS R25, [R0+-0xd0] &req={0} ?trans4;
LDS R24, [R0+-0x68] &wr=0x0 ?trans4;
LDS R27, [R0] ?trans4;
LDS R26, [R0+0x68] &wr=0x3 ?trans4;
LDS R12, [R0+0xd0] ?trans1;
IADD3 R14, PT, PT, R16, R15, R14 &req={5} ?WAIT3_END_GROUP;
LDS R13, [R0+0x138] &wr=0x4 ?trans4;
LDS R10, [R0+0x1a0] ?trans4;
LDS R11, [R0+0x208] &wr=0x4 ?trans1;
IADD3 R14, PT, PT, R20, R14, R17 &req={1} ?WAIT3_END_GROUP;
LDS R4, [R0+0x270] &req={3} ?trans4;
LDS R5, [R0+0x2d8] &wr=0x1 ?trans1;
IADD3 R14, PT, PT, R22, R14, R23 &req={2} ?WAIT3_END_GROUP;
LDS R6, [R0+0x340] ?trans4;
LDS R7, [R0+0x3a8] &wr=0x2 ?trans1;
IADD3 R14, PT, PT, R24, R14, R25 &req={0} ?WAIT3_END_GROUP;
LDS R8, [R0+0x410] ?trans4;
LDS R9, [R0+0x478] &wr=0x0 ?trans1;
IADD3 R26, PT, PT, R26, R14, R27 ?WAIT3_END_GROUP;
LDS R18, [R0+0x4e0] ?trans4;
LDS R19, [R0+0x548] &wr=0x3 ?trans1;
IADD3 R26, PT, PT, R13, R26, R12 &req={4} ?WAIT3_END_GROUP;
LDS R20, [R0+0x5b0] ?trans4;
LDS R21, [R0+0x618] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R11, R26, R10 ?WAIT3_END_GROUP;
LDS R22, [R0+0x680] ?trans4;
LDS R23, [R0+0x6e8] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R5, R26, R4 &req={1} ?WAIT3_END_GROUP;
LDS R16, [R0+0x750] ?trans4;
LDS R17, [R0+0x7b8] &wr=0x1 ?trans1;
IADD3 R26, PT, PT, R7, R26, R6 &req={2} ?WAIT3_END_GROUP;
LDS R14, [R0+0x820] ?trans4;
LDS R15, [R0+0x888] &wr=0x2 ?trans1;
IADD3 R8, PT, PT, R9, R26, R8 &req={0} ?WAIT3_END_GROUP;
LDS R12, [R0+0x8f0] ?trans4;
LDS R13, [R0+0x958] &wr=0x0 ?trans1;
IADD3 R8, PT, PT, R19, R8, R18 &req={3} ?WAIT3_END_GROUP;
LDS R10, [R0+0x9c0] ?trans4;
LDS R11, [R0+0xa28] &wr=0x3 ?trans1;
IADD3 R20, PT, PT, R21, R8, R20 &req={4} ?WAIT3_END_GROUP;
LDS R4, [R0+0xa90] ?trans4;
LDS R5, [R0+0xaf8] &wr=0x4 ?trans1;
IADD3 R20, PT, PT, R23, R20, R22 ?WAIT3_END_GROUP;
LDS R6, [R0+0xb60] ?trans4;
LDS R7, [R0+0xbc8] &wr=0x4 ?trans1;
IADD3 R16, PT, PT, R17, R20, R16 &req={1} ?WAIT3_END_GROUP;
LDS R24, [R0+0xc30] ?trans4;
LDS R25, [R0+0xc98] &wr=0x1 ?trans1;
IADD3 R14, PT, PT, R15, R16, R14 &req={2} ?WAIT3_END_GROUP;
LDS R26, [R0+0xd00] ?trans4;
LDS R27, [R0+0xd68] &wr=0x2 ?trans1;
IADD3 R12, PT, PT, R13, R14, R12 &req={0} ?WAIT3_END_GROUP;
LDS R8, [R0+0xdd0] ?trans4;
LDS R9, [R0+0xe38] &wr=0x0 ?trans1;
IADD3 R12, PT, PT, R11, R12, R10 &req={3} ?WAIT3_END_GROUP;
LDS R22, [R0+0xea0] ?trans4;
LDS R23, [R0+0xf08] &wr=0x3 ?trans1;
IADD3 R4, PT, PT, R5, R12, R4 &req={4} ?WAIT3_END_GROUP;
LDS R20, [R0+0xf70] ?trans4;
LDS R21, [R0+0xfd8] &wr=0x4 ?trans1;
IADD3 R4, PT, PT, R7, R4, R6 ?WAIT3_END_GROUP;
LDS R18, [R0+0x1040] ?trans4;
LDS R19, [R0+0x10a8] &wr=0x4 ?trans1;
IADD3 R4, PT, PT, R25, R4, R24 &req={1} ?WAIT3_END_GROUP;
LDS R16, [R0+0x1110] ?trans4;
LDS R17, [R0+0x1178] &wr=0x1 ?trans1;
IADD3 R26, PT, PT, R27, R4, R26 &req={2} ?WAIT3_END_GROUP;
LDS R10, [R0+0x11e0] ?trans4;
LDS R11, [R0+0x1248] &wr=0x2 ?trans1;
IADD3 R26, PT, PT, R9, R26, R8 &req={0} ?WAIT3_END_GROUP;
LDS R12, [R0+0x12b0] ?trans4;
LDS R13, [R0+0x1318] &wr=0x0 ?trans1;
IADD3 R26, PT, PT, R23, R26, R22 &req={3} ?WAIT3_END_GROUP;
LDS R14, [R0+0x1380] ?trans4;
LDS R15, [R0+0x13e8] &wr=0x3 ?trans1;
IADD3 R26, PT, PT, R21, R26, R20 &req={4} ?WAIT3_END_GROUP;
LDS R6, [R0+0x1450] ?trans4;
LDS R7, [R0+0x14b8] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R19, R26, R18 ?WAIT3_END_GROUP;
LDS R5, [R0+0x1520] ?trans4;
LDS R4, [R0+0x1588] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R17, R26, R16 &req={1} ?WAIT3_END_GROUP;
LDS R9, [R0+0x15f0] ?trans4;
LDS R8, [R0+0x1658] &wr=0x1 ?trans1;
IADD3 R26, PT, PT, R11, R26, R10 &req={2} ?WAIT3_END_GROUP;
LDS R23, [R0+0x16c0] ?trans4;
LDS R22, [R0+0x1728] &wr=0x2 ?trans1;
IADD3 R26, PT, PT, R13, R26, R12 &req={0} ?WAIT3_END_GROUP;
LDS R21, [R0+0x1790] ?trans4;
LDS R20, [R0+0x17f8] &wr=0x0 ?trans1;
IADD3 R26, PT, PT, R15, R26, R14 &req={3} ?WAIT3_END_GROUP;
LDS R19, [R0+0x1860] ?trans4;
LDS R18, [R0+0x18c8] &wr=0x3 ?trans1;
IADD3 R26, PT, PT, R7, R26, R6 &req={4} ?WAIT3_END_GROUP;
LDS R17, [R0+0x1930] ?trans4;
LDS R16, [R0+0x1998] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R4, R26, R5 ?WAIT3_END_GROUP;
LDS R11, [R0+0x1a00] ?trans4;
LDS R10, [R0+0x1a68] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R8, R26, R9 &req={1} ?WAIT3_END_GROUP;
LDS R12, [R0+0x1ad0] ?trans4;
LDS R13, [R0+0x1b38] &wr=0x1 ?trans1;
IADD3 R26, PT, PT, R22, R26, R23 &req={2} ?WAIT3_END_GROUP;
LDS R14, [R0+0x1ba0] ?trans4;
LDS R15, [R0+0x1c08] &wr=0x2 ?trans1;
IADD3 R26, PT, PT, R20, R26, R21 &req={0} ?WAIT3_END_GROUP;
LDS R6, [R0+0x1c70] ?trans4;
LDS R7, [R0+0x1cd8] &wr=0x0 ?trans1;
IADD3 R26, PT, PT, R18, R26, R19 &req={3} ?WAIT3_END_GROUP;
LDS R4, [R0+0x1d40] ?trans4;
LDS R5, [R0+0x1da8] &wr=0x3 ?trans1;
IADD3 R26, PT, PT, R16, R26, R17 &req={4} ?WAIT3_END_GROUP;
LDS R8, [R0+0x1e10] ?trans4;
LDS R9, [R0+0x1e78] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R10, R26, R11 ?WAIT3_END_GROUP;
LDS R22, [R0+0x1ee0] ?trans4;
LDS R23, [R0+0x1f48] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R13, R26, R12 &req={1} ?WAIT3_END_GROUP;
LDS R20, [R0+0x1fb0] ?trans4;
LDS R21, [R0+0x2018] &wr=0x1 ?trans1;
IADD3 R26, PT, PT, R15, R26, R14 &req={2} ?WAIT3_END_GROUP;
LDS R18, [R0+0x2080] ?trans4;
LDS R19, [R0+0x20e8] &wr=0x2 ?trans1;
IADD3 R26, PT, PT, R7, R26, R6 &req={0} ?WAIT3_END_GROUP;
LDS R16, [R0+0x2150] ?trans4;
LDS R17, [R0+0x21b8] &wr=0x0 ?trans1;
IADD3 R26, PT, PT, R5, R26, R4 &req={3} ?WAIT3_END_GROUP;
LDS R11, [R0+0x2220] ?trans4;
LDS R10, [R0+0x2288] &wr=0x3 ?trans1;
IADD3 R26, PT, PT, R9, R26, R8 &req={4} ?WAIT3_END_GROUP;
LDS R13, [R0+0x22f0] ?trans4;
LDS R12, [R0+0x2358] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R23, R26, R22 ?WAIT3_END_GROUP;
LDS R14, [R0+0x23c0] ?trans4;
LDS R15, [R0+0x2428] &wr=0x4 ?trans1;
IADD3 R26, PT, PT, R21, R26, R20 &req={1} ?WAIT3_END_GROUP;
LDS R7, [R0+0x2490] ?trans4;
LDS R6, [R0+0x24f8] &wr=0x1 ?trans1;
IADD3 R26, PT, PT, R19, R26, R18 &req={2} ?WAIT3_END_GROUP;
LDS R5, [R0+0x2560] ?trans4;
LDS R4, [R0+0x25c8] &wr=0x2 ?trans1;
IADD3 R26, PT, PT, R17, R26, R16 &req={0} ?WAIT3_END_GROUP;
LDS R9, [R0+0x2630] ?trans4;
LDS R8, [R0+0x2698] &wr=0x0 ?trans1;
IADD3 R10, PT, PT, R10, R26, R11 &req={3} ?WAIT3_END_GROUP;
LDS R23, [R0+0x2700] ?trans4;
LDS R22, [R0+0x2768] &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R12, R10, R13 &req={4} ?WAIT3_END_GROUP;
LDS R21, [R0+0x27d0] ?trans4;
LDS R20, [R0+0x2838] &wr=0x4 ?trans1;
IADD3 R14, PT, PT, R15, R10, R14 ?WAIT3_END_GROUP;
LDS R19, [R0+0x28a0] ?trans4;
LDS R18, [R0+0x2908] &wr=0x4 ?trans1;
IADD3 R6, PT, PT, R6, R14, R7 &req={1} ?WAIT3_END_GROUP;
LDS R17, [R0+0x2970] ?trans4;
LDS R16, [R0+0x29d8] &rd=0x1 &wr=0x4 ?trans1;
IADD3 R4, PT, PT, R4, R6, R5 &req={2} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R8, R4, R9 &req={0} ?trans2;
IADD3 R0, PT, PT, R0, 0x2d80, RZ &req={1} ?trans2;
IADD3 R4, PT, PT, R22, R4, R23 &req={3} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R20, R4, R21 &req={4} ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R18, R4, R19 ?WAIT4_END_GROUP;
IADD3 R15, PT, PT, R16, R4, R17 ?trans1;
@P0 BRA 0xe80 ?trans6;
STG.E desc[UR6][R2.64], R15 ?trans1;
EXIT ?trans5;
BRA 0x1960;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: countLettersShared(unsigned char*, unsigned int*, unsigned long)
_Z18countLettersSharedPhPjm:
v_mul_u32_u24_e32 v1, 26, v0
s_mov_b64 s[2:3], 26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v1
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v3
.LBB1_1:
ds_store_b32 v2, v1
v_add_nc_u32_e32 v2, 4, v2
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc1 .LBB1_1
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB1_5
v_mad_u64_u32 v[1:2], null, v0, s4, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s5, v[2:3]
v_mov_b32_e32 v2, v4
.LBB1_4:
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_lshl_add_u32 v4, v4, 2, v3
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, 1, v5
ds_store_b32 v4, v5
s_cbranch_scc0 .LBB1_4
.LBB1_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_gt_u32_e32 26, v0
s_cbranch_execz .LBB1_9
v_lshlrev_b32_e32 v1, 2, v0
v_mad_i32_i24 v3, 0xffffff9c, v0, v3
s_mov_b64 s[0:1], 0x1c0
global_load_b32 v2, v1, s[2:3]
v_add_co_u32 v0, s2, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
.LBB1_7:
ds_load_b32 v4, v3
v_add_nc_u32_e32 v3, 0x68, v3
s_add_u32 s0, s0, -1
s_addc_u32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[0:1], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, v4, v2
s_cbranch_scc1 .LBB1_7
global_store_b32 v[0:1], v2, off
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| countLettersShared | 10,264 | 1,044 | stackv2-00000-of-00015 |
// Demangled: shiftLetters(unsigned char*)
Function : _Z12shiftLettersPh
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R3, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans6;
LDC R2, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.U8 R4, c[0x3][RZ] &wr=0x3 ?trans1;
IMAD R2, R2, UR6, R3 &req={0} ?WAIT2_END_GROUP;
HFMA2 R3, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR8 &req={1} ?WAIT6_END_GROUP;
LDG.E.U8 R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans1;
IADD3 R4, PT, PT, RZ, -R4, RZ &req={3} ?WAIT4_END_GROUP;
PRMT R5, R4, 0x7710, RZ ?WAIT4_END_GROUP;
IADD3 R5, PT, PT, R0, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: shiftLetters(unsigned char*)
_Z12shiftLettersPh:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, shiftAmount@rel32@lo+4
s_addc_u32 s3, s3, shiftAmount@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
global_load_u8 v0, v1, s[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u16 v0, v0, s2
global_store_b8 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| shiftLetters | 465 | 288 | stackv2-00000-of-00015 |
// Demangled: mcarlo(float*, int)
Function : _Z6mcarloPfi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
HFMA2 R6, -RZ, RZ, -310, -36736 ?trans1;
MOV R12, 0xf8a42704 ?WAIT6_END_GROUP;
LDC R4, c[0x0][0x360] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x3 ?trans1;
LOP3.LUT R0, R7, 0xaad26b49, RZ, 0x3c, !PT &req={1} ?trans1;
IMAD R7, R4, UR4, R7 &req={2} ?WAIT2_END_GROUP;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R5, R0, 0x4182bed5, RZ ?trans2;
IMAD.WIDE R2, R7, 0x4, R2 &req={3} ?WAIT3_END_GROUP;
IADD3 R0, PT, PT, R5.reuse, 0x583f19, RZ ?trans2;
LOP3.LUT R8, R5.reuse, 0x159a55e5, RZ, 0x3c, !PT ?trans2;
IADD3 R14, PT, PT, R5.reuse, 0x75bcd15, RZ ?trans2;
IADD3 R5, PT, PT, R5, -0x26039c23, RZ &req={0} ?WAIT7_END_GROUP;
SHF.R.U32.HI R7, RZ, 0x2, R14 ?trans1;
IMAD.SHL.U32 R9, R0, 0x10, RZ ?trans1;
SHF.R.U32.HI R11, RZ, 0x2, R8 ?trans2;
LOP3.LUT R7, R7, R14, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R11, R11, R8, RZ, 0x3c, !PT ?trans2;
IADD3 R10, PT, PT, R7, R7, RZ ?WAIT4_END_GROUP;
LOP3.LUT R10, R0, R9, R10, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R8, R10, R7, RZ, 0x3c, !PT ?trans2;
IADD3 R7, PT, PT, R11, R11, RZ ?WAIT3_END_GROUP;
IMAD.SHL.U32 R10, R8.reuse, 0x10, RZ ?trans1;
IADD3 R9, PT, PT, R8, R5, RZ ?WAIT4_END_GROUP;
LOP3.LUT R7, R11, R7, R10, 0x96, !PT ?trans2;
I2FP.F32.U32 R14, R9 ?trans2;
LOP3.LUT R10, R7, R8, RZ, 0x3c, !PT ?trans1;
MOV R7, 0x2f800000 ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R5, 0x587c5, R10 ?trans2;
FFMA R14, R14, R7, 1.1641532182693481445e-10 ?trans2;
I2FP.F32.U32 R16, R11 ?WAIT5_END_GROUP;
FFMA R16, R16, R7, 1.1641532182693481445e-10 ?WAIT4_END_GROUP;
FMUL R9, R16, R16 ?WAIT4_END_GROUP;
FFMA R9, R14, R14, R9 ?WAIT5_END_GROUP;
FSETP.GTU.AND P1, PT, R9, 1, PT ?WAIT13_END_GROUP;
@!P1 LDG.E R9, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
SHF.R.U32.HI R11, RZ, 0x2, R12 ?trans1;
IMAD.SHL.U32 R13, R10, 0x10, RZ ?trans1;
SHF.R.U32.HI R15, RZ, 0x2, R6 ?trans2;
LOP3.LUT R11, R11, R12, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R15, R15, R6, RZ, 0x3c, !PT ?trans2;
IADD3 R12, PT, PT, R11, R11, RZ ?WAIT4_END_GROUP;
LOP3.LUT R12, R10, R13, R12, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R6, R12, R11, RZ, 0x3c, !PT ?trans2;
IADD3 R11, PT, PT, R15, R15, RZ ?WAIT3_END_GROUP;
IMAD.SHL.U32 R12, R6, 0x10, RZ ?WAIT5_END_GROUP;
LOP3.LUT R11, R15, R11, R12, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R14, R11, R6, RZ, 0x3c, !PT ?trans2;
IADD3 R11, PT, PT, R5.reuse, 0xb0f8a, R6 ?trans2;
IADD3 R12, PT, PT, R5, 0x10974f, R14 ?WAIT4_END_GROUP;
I2FP.F32.U32 R16, R12 ?trans2;
I2FP.F32.U32 R12, R11 ?WAIT3_END_GROUP;
FFMA R16, R16, R7.reuse, 1.1641532182693481445e-10 ?trans2;
FFMA R12, R12, R7, 1.1641532182693481445e-10 ?trans2;
FMUL R11, R16, R16 ?WAIT4_END_GROUP;
FFMA R11, R12, R12, R11 ?WAIT5_END_GROUP;
FSETP.GTU.AND P0, PT, R11, 1, PT ?trans1;
@!P1 FADD R9, R9, 1 &req={2} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R9 &rd=0x0 ?trans7;
@!P0 LDG.E R17, desc[UR4][R2.64] &wr=0x2 ?trans1;
SHF.R.U32.HI R11, RZ, 0x2, R0 ?trans1;
IMAD.SHL.U32 R13, R14, 0x10, RZ ?trans1;
SHF.R.U32.HI R15, RZ, 0x2, R8 ?WAIT2_END_GROUP;
LOP3.LUT R11, R11, R0, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R15, R15, R8, RZ, 0x3c, !PT ?trans2;
IADD3 R0, PT, PT, R11, R11, RZ ?WAIT4_END_GROUP;
LOP3.LUT R0, R14, R13, R0, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R8, R0, R11, RZ, 0x3c, !PT ?trans2;
IADD3 R11, PT, PT, R15, R15, RZ ?WAIT3_END_GROUP;
IMAD.SHL.U32 R0, R8, 0x10, RZ ?WAIT5_END_GROUP;
LOP3.LUT R11, R15, R11, R0, 0x96, !PT ?trans2;
IADD3 R0, PT, PT, R5, 0x161f14, R8 ?trans2;
LOP3.LUT R12, R11, R8, RZ, 0x3c, !PT ?trans2;
I2FP.F32.U32 R0, R0 ?trans2;
IADD3 R9, PT, PT, R5, 0x1ba6d9, R12 &req={0} ?WAIT3_END_GROUP;
FFMA R0, R0, R7, 1.1641532182693481445e-10 ?trans1;
I2FP.F32.U32 R16, R9 ?WAIT5_END_GROUP;
FFMA R16, R16, R7, 1.1641532182693481445e-10 ?WAIT4_END_GROUP;
FMUL R9, R16, R16 ?WAIT4_END_GROUP;
FFMA R9, R0, R0, R9 ?WAIT5_END_GROUP;
FSETP.GTU.AND P1, PT, R9, 1, PT ?trans1;
@!P0 FADD R9, R17, 1 &req={2} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR4][R2.64], R9 &rd=0x0 ?trans7;
@!P1 LDG.E R17, desc[UR4][R2.64] &wr=0x2 ?trans1;
SHF.R.U32.HI R11, RZ, 0x2, R10 ?trans1;
IMAD.SHL.U32 R13, R12, 0x10, RZ ?trans1;
SHF.R.U32.HI R15, RZ, 0x2, R6 ?WAIT2_END_GROUP;
LOP3.LUT R11, R11, R10, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R15, R15, R6, RZ, 0x3c, !PT ?trans2;
IADD3 R0, PT, PT, R11, R11, RZ ?trans2;
IADD3 R10, PT, PT, R15, R15, RZ ?trans2;
LOP3.LUT R0, R12, R13, R0, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R6, R0, R11, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
IADD3 R9, PT, PT, R5, 0x212e9e, R6 &req={0} ?trans1;
IMAD.SHL.U32 R0, R6, 0x10, RZ ?WAIT5_END_GROUP;
LOP3.LUT R15, R15, R10, R0, 0x96, !PT ?WAIT4_END_GROUP;
LOP3.LUT R0, R15, R6, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
IADD3 R10, PT, PT, R5, 0x26b663, R0 ?WAIT4_END_GROUP;
I2FP.F32.U32 R16, R10 ?trans2;
I2FP.F32.U32 R10, R9 ?WAIT3_END_GROUP;
FFMA R16, R16, R7.reuse, 1.1641532182693481445e-10 ?trans2;
FFMA R10, R10, R7, 1.1641532182693481445e-10 ?trans2;
FMUL R7, R16, R16 ?WAIT4_END_GROUP;
FFMA R7, R10, R10, R7 ?WAIT5_END_GROUP;
FSETP.GTU.AND P0, PT, R7, 1, PT ?trans1;
@!P1 FADD R7, R17, 1 &req={2} ?WAIT5_END_GROUP;
@!P1 STG.E desc[UR4][R2.64], R7 &rd=0x0 ?trans7;
@!P0 LDG.E R9, desc[UR4][R2.64] &wr=0x2 ?trans1;
IADD3 R4, PT, PT, R4, 0x4, RZ ?trans2;
IADD3 R5, PT, PT, R5, 0x2c3e28, RZ ?trans1;
@!P0 FADD R9, R9, 1 &req={2} ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR4][R2.64], R9 &rd=0x0 ?trans1;
ISETP.NE.AND P0, PT, R4, 0x989680, PT ?WAIT13_END_GROUP;
@P0 BRA 0x110 &req={0} ?trans5;
EXIT ?trans5;
BRA 0x770;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mcarlo(float*, int)
_Z6mcarloPfi:
s_load_b64 s[2:3], s[0:1], 0x0
v_xor_b32_e32 v1, 0x2c7f967f, v0
v_mov_b32_e32 v3, 0xa96f9d04
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_mov_b32 s4, 0x989680
v_mul_lo_u32 v2, 0x493c4aa1, v1
v_mov_b32_e32 v1, 0x8f14727c
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x75bcd15, v2
v_xor_b32_e32 v7, 0x159a55e5, v2
v_add_nc_u32_e32 v5, 0x583f19, v2
v_add_nc_u32_e32 v2, 0x8ac7d9dd, v2
.LBB0_1:
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v4
v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v5
v_lshrrev_b32_e32 v9, 2, v7
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 2, v6
v_xor_b32_e32 v5, v8, v6
v_lshlrev_b32_e32 v6, 4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v8, 1, v5
v_xor_b32_e32 v8, v8, v6
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor3_b32 v1, v8, v5, v3
v_xor_b32_e32 v5, v9, v7
v_lshlrev_b32_e32 v7, 4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v8, 1, v5
v_xor_b32_e32 v7, v8, v7
v_add_nc_u32_e32 v8, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v5, v7, v5, v1
v_cvt_f32_u32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v7, v2, v5, 0x587c5
v_fmaak_f32 v8, 0x2f800000, v8, 0x2f800000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v7, v7
v_fmaak_f32 v7, 0x2f800000, v7, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v7, v7
v_fmac_f32_e32 v7, v8, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_f32_e32 1.0, v7
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, 1.0, v9
global_store_b32 v[7:8], v9, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
v_dual_mov_b32 v7, v6 :: v_dual_add_nc_u32 v2, 0xb0f8a, v2
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mcarlo | 3,439 | 1,544 | stackv2-00000-of-00015 |
// Demangled: convolve(unsigned char (*) [16], unsigned char*, int, int)
Function : _Z8convolvePA16_hPhii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x390] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
MOV R9, RZ ?trans1;
IADD3 R12, PT, PT, R3, -0x2, RZ &req={1} ?WAIT2_END_GROUP;
IADD3 R10, PT, PT, R3.reuse, -0x1, RZ ?trans2;
IADD3 R4, PT, PT, R3.reuse, 0x1, RZ ?trans2;
IADD3 R6, PT, PT, R3.reuse, 0x2, RZ ?trans1;
ISETP.GT.U32.AND P0, PT, R3, 0xf, PT ?trans1;
ISETP.GT.U32.AND P4, PT, R12, 0xf, PT ?trans1;
ISETP.GT.U32.AND P3, PT, R10, 0xf, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R4, 0xf, PT ?trans1;
ISETP.GT.U32.AND P2, PT, R6, 0xf, PT ?trans1;
IADD3 R8, PT, PT, R2, -0x2, RZ ?WAIT9_END_GROUP;
@P4 BRA 0x2e0 &req={2,0} ?trans5;
LDC.64 R14, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R17, PT, PT, R2, -0x1, RZ ?trans1;
ISETP.GT.U32.AND P6, PT, R8, 0xf, PT ?trans1;
MOV R13, RZ ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P4, PT, R17, 0xf, PT ?trans2;
IADD.64 R12, R12, R14 &req={0} ?WAIT11_END_GROUP;
@!P4 IMAD.WIDE.U32 R16, R17, 0x10, R12 ?WAIT4_END_GROUP;
@!P6 IMAD.WIDE.U32 R14, R8, 0x10, R12 ?trans2;
@!P4 LDG.E.U8 R17, desc[UR4][R16.64] &wr=0x2 ?trans4;
@!P6 LDG.E.U8 R0, desc[UR4][R14.64] &rd=0x0 &wr=0x2 ?trans1;
IADD3 R21, PT, PT, R2.reuse, 0x1, RZ ?trans1;
ISETP.GT.U32.AND P5, PT, R2.reuse, 0xf, PT ?trans1;
@!P6 MOV R9, 0x1 ?trans1;
IADD3 R23, PT, PT, R2, 0x2, RZ ?WAIT2_END_GROUP;
ISETP.GT.U32.AND P6, PT, R21, 0xf, PT ?trans2;
@!P4 LOP3.LUT R9, R9, 0x4, RZ, 0xfc, !PT ?WAIT7_END_GROUP;
@!P5 IMAD.WIDE.U32 R18, R2, 0x10, R12 ?WAIT4_END_GROUP;
@!P6 IMAD.WIDE.U32 R14, R21, 0x10, R12 &req={0} ?trans2;
@!P5 LDG.E.U8 R19, desc[UR4][R18.64] &wr=0x3 ?trans4;
@!P6 LDG.E.U8 R15, desc[UR4][R14.64] &wr=0x4 ?trans1;
@!P4 IMAD R0, R17, 0x4, R0 &req={2} ?trans1;
ISETP.GT.U32.AND P4, PT, R23, 0xf, PT ?WAIT13_END_GROUP;
@!P4 IMAD.WIDE.U32 R12, R23, 0x10, R12 ?WAIT6_END_GROUP;
@!P4 LDG.E.U8 R13, desc[UR4][R12.64] &wr=0x2 ?trans1;
@!P5 IADD3 R9, PT, PT, R9, 0x7, RZ ?trans1;
@!P5 IMAD R0, R19, 0x7, R0 &req={3} ?WAIT3_END_GROUP;
@!P6 IADD3 R9, PT, PT, R9, 0x4, RZ ?trans1;
@!P6 IMAD R0, R15, 0x4, R0 &req={4} ?WAIT3_END_GROUP;
@!P4 IADD3 R9, PT, PT, R9, 0x1, RZ ?trans2;
@!P4 IADD3 R0, PT, PT, R0, R13, RZ &req={2} ?WAIT7_END_GROUP;
@P3 BRA 0x4e0 ?trans5;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P6, PT, R8, 0xf, PT ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?WAIT5_END_GROUP;
IADD.64 R10, R10, R12 &req={0} ?WAIT7_END_GROUP;
@!P6 IMAD.WIDE.U32 R12, R8, 0x10, R10 ?WAIT6_END_GROUP;
@!P6 LDG.E.U8 R13, desc[UR4][R12.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R2.reuse, -0x1, RZ ?trans2;
IADD3 R17, PT, PT, R2.reuse, 0x1, RZ ?trans1;
ISETP.GT.U32.AND P4, PT, R2.reuse, 0xf, PT ?trans1;
IADD3 R19, PT, PT, R2, 0x2, RZ ?trans2;
@!P6 IADD3 R9, PT, PT, R9, 0x4, RZ ?trans1;
ISETP.GT.U32.AND P5, PT, R15, 0xf, PT ?trans1;
ISETP.GT.U32.AND P3, PT, R17, 0xf, PT ?WAIT12_END_GROUP;
@!P5 IMAD.WIDE.U32 R14, R15, 0x10, R10 ?WAIT4_END_GROUP;
@!P3 IMAD.WIDE.U32 R16, R17, 0x10, R10 ?trans2;
@!P5 LDG.E.U8 R15, desc[UR4][R14.64] &wr=0x3 ?trans4;
@!P3 LDG.E.U8 R17, desc[UR4][R16.64] &wr=0x4 ?trans1;
@!P6 IMAD R0, R13, 0x4, R0 &req={2} ?trans1;
ISETP.GT.U32.AND P6, PT, R19, 0xf, PT ?trans1;
@!P4 IMAD.WIDE.U32 R12, R2, 0x10, R10 ?WAIT6_END_GROUP;
@!P4 LDG.E.U8 R13, desc[UR4][R12.64] &wr=0x2 ?trans6;
@!P6 IMAD.WIDE.U32 R10, R19, 0x10, R10 ?WAIT6_END_GROUP;
@!P6 LDG.E.U8 R11, desc[UR4][R10.64] &wr=0x5 ?trans1;
@!P5 IADD3 R9, PT, PT, R9, 0x10, RZ ?trans1;
@!P5 IMAD R0, R15, 0x10, R0 &req={3} ?WAIT3_END_GROUP;
@!P4 IADD3 R9, PT, PT, R9, 0x1a, RZ ?WAIT4_END_GROUP;
@!P3 IADD3 R9, PT, PT, R9, 0x10, RZ ?WAIT4_END_GROUP;
@!P6 IADD3 R9, PT, PT, R9, 0x4, RZ ?trans1;
@!P4 IMAD R0, R13, 0x1a, R0 &req={2} ?WAIT4_END_GROUP;
@!P3 IMAD R0, R17, 0x10, R0 &req={4} ?WAIT4_END_GROUP;
@!P6 IMAD R0, R11, 0x4, R0 &req={5} ?WAIT7_END_GROUP;
@P0 BRA 0x6f0 ?trans5;
LDC.64 R12, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R15, PT, PT, R2, -0x1, RZ ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0xf, PT ?trans1;
MOV R10, R3 ?trans1;
HFMA2 R11, -RZ, RZ, 0, 0 ?trans1;
IADD3 R19, PT, PT, R2.reuse, 0x1, RZ ?trans1;
ISETP.GT.U32.AND P3, PT, R15, 0xf, PT ?trans1;
ISETP.GT.U32.AND P4, PT, R2.reuse, 0xf, PT ?trans1;
IADD3 R3, PT, PT, R2, 0x2, RZ ?trans2;
ISETP.GT.U32.AND P5, PT, R19, 0xf, PT ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P6, PT, R3, 0xf, PT ?trans1;
IADD.64 R10, R10, R12 &req={0} ?WAIT6_END_GROUP;
@!P0 IMAD.WIDE.U32 R12, R8, 0x10, R10 ?WAIT4_END_GROUP;
@!P3 IMAD.WIDE.U32 R14, R15, 0x10, R10.reuse ?trans2;
@!P0 LDG.E.U8 R13, desc[UR4][R12.64] &wr=0x2 ?trans2;
@!P4 IMAD.WIDE.U32 R16, R2, 0x10, R10.reuse ?trans2;
@!P3 LDG.E.U8 R15, desc[UR4][R14.64] &wr=0x3 ?trans2;
@!P5 IMAD.WIDE.U32 R18, R19, 0x10, R10.reuse ?trans2;
@!P4 LDG.E.U8 R17, desc[UR4][R16.64] &wr=0x4 ?trans2;
@!P6 IMAD.WIDE.U32 R10, R3, 0x10, R10 ?WAIT2_END_GROUP;
@!P5 LDG.E.U8 R19, desc[UR4][R18.64] &wr=0x5 ?trans4;
@!P6 LDG.E.U8 R11, desc[UR4][R10.64] &wr=0x5 ?trans1;
@!P0 IADD3 R9, PT, PT, R9, 0x7, RZ ?WAIT4_END_GROUP;
@!P3 IADD3 R9, PT, PT, R9, 0x1a, RZ ?WAIT4_END_GROUP;
@!P4 IADD3 R9, PT, PT, R9, 0x29, RZ ?WAIT4_END_GROUP;
@!P5 IADD3 R9, PT, PT, R9, 0x1a, RZ ?WAIT4_END_GROUP;
@!P6 IADD3 R9, PT, PT, R9, 0x7, RZ ?trans1;
@!P0 IMAD R0, R13, 0x7, R0 &req={2} ?WAIT4_END_GROUP;
@!P3 IMAD R0, R15, 0x1a, R0 &req={3} ?WAIT4_END_GROUP;
@!P4 IMAD R0, R17, 0x29, R0 &req={4} ?WAIT4_END_GROUP;
@!P5 IMAD R0, R19, 0x1a, R0 &req={5} ?WAIT4_END_GROUP;
@!P6 IMAD R0, R11, 0x7, R0 ?WAIT7_END_GROUP;
@P1 BRA 0x8f0 ?trans5;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
IADD3 R13, PT, PT, R2, -0x1, RZ ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0xf, PT ?trans1;
MOV R5, RZ ?trans1;
IADD3 R17, PT, PT, R2.reuse, 0x1, RZ ?trans1;
ISETP.GT.U32.AND P3, PT, R2.reuse, 0xf, PT ?trans1;
ISETP.GT.U32.AND P1, PT, R13, 0xf, PT ?trans1;
IADD3 R3, PT, PT, R2, 0x2, RZ ?trans2;
ISETP.GT.U32.AND P4, PT, R17, 0xf, PT ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P5, PT, R3, 0xf, PT ?trans1;
IADD.64 R4, R4, R10 &req={0} ?WAIT6_END_GROUP;
@!P0 IMAD.WIDE.U32 R10, R8, 0x10, R4 ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE.U32 R12, R13, 0x10, R4.reuse ?trans2;
@!P0 LDG.E.U8 R11, desc[UR4][R10.64] &wr=0x2 ?trans2;
@!P3 IMAD.WIDE.U32 R14, R2, 0x10, R4.reuse ?trans2;
@!P1 LDG.E.U8 R13, desc[UR4][R12.64] &wr=0x3 ?trans2;
@!P4 IMAD.WIDE.U32 R16, R17, 0x10, R4.reuse ?trans2;
@!P3 LDG.E.U8 R15, desc[UR4][R14.64] &wr=0x4 ?trans2;
@!P5 IMAD.WIDE.U32 R4, R3, 0x10, R4 ?WAIT2_END_GROUP;
@!P4 LDG.E.U8 R17, desc[UR4][R16.64] &wr=0x5 ?trans4;
@!P5 LDG.E.U8 R5, desc[UR4][R4.64] &wr=0x5 ?trans1;
@!P0 IADD3 R9, PT, PT, R9, 0x4, RZ ?WAIT4_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, 0x10, RZ ?WAIT4_END_GROUP;
@!P3 IADD3 R9, PT, PT, R9, 0x1a, RZ ?WAIT4_END_GROUP;
@!P4 IADD3 R9, PT, PT, R9, 0x10, RZ ?WAIT4_END_GROUP;
@!P5 IADD3 R9, PT, PT, R9, 0x4, RZ ?trans1;
@!P0 IMAD R0, R11, 0x4, R0 &req={2} ?WAIT4_END_GROUP;
@!P1 IMAD R0, R13, 0x10, R0 &req={3} ?WAIT4_END_GROUP;
@!P3 IMAD R0, R15, 0x1a, R0 &req={4} ?WAIT4_END_GROUP;
@!P4 IMAD R0, R17, 0x10, R0 &req={5} ?WAIT4_END_GROUP;
@!P5 IMAD R0, R5, 0x4, R0 ?WAIT7_END_GROUP;
@P2 BRA 0xaf0 ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R8, 0xf, PT ?trans1;
IADD3 R11, PT, PT, R2.reuse, -0x1, RZ ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
IADD3 R13, PT, PT, R2.reuse, 0x1, RZ ?trans1;
ISETP.GT.U32.AND P2, PT, R2.reuse, 0xf, PT ?trans1;
IADD3 R15, PT, PT, R2, 0x2, RZ ?trans1;
ISETP.GT.U32.AND P1, PT, R11, 0xf, PT ?trans2;
ISETP.GT.U32.AND P3, PT, R13, 0xf, PT ?trans2;
ISETP.GT.U32.AND P4, PT, R15, 0xf, PT ?trans1;
IADD.64 R6, R6, R4 &req={0} ?WAIT6_END_GROUP;
@!P0 IMAD.WIDE.U32 R4, R8, 0x10, R6 ?WAIT4_END_GROUP;
@!P1 IMAD.WIDE.U32 R10, R11, 0x10, R6.reuse ?trans2;
@!P0 LDG.E.U8 R5, desc[UR4][R4.64] &wr=0x2 ?trans2;
@!P2 IMAD.WIDE.U32 R2, R2, 0x10, R6.reuse ?trans2;
@!P1 LDG.E.U8 R11, desc[UR4][R10.64] &wr=0x3 ?trans2;
@!P3 IMAD.WIDE.U32 R12, R13, 0x10, R6.reuse ?trans2;
@!P2 LDG.E.U8 R3, desc[UR4][R2.64] &wr=0x4 ?trans2;
@!P4 IMAD.WIDE.U32 R6, R15, 0x10, R6 ?WAIT2_END_GROUP;
@!P3 LDG.E.U8 R13, desc[UR4][R12.64] &wr=0x5 ?trans4;
@!P4 LDG.E.U8 R7, desc[UR4][R6.64] &wr=0x5 ?trans1;
@!P0 IADD3 R9, PT, PT, R9, 0x1, RZ ?WAIT4_END_GROUP;
@!P1 IADD3 R9, PT, PT, R9, 0x4, RZ ?WAIT4_END_GROUP;
@!P2 IADD3 R9, PT, PT, R9, 0x7, RZ ?WAIT4_END_GROUP;
@!P3 IADD3 R9, PT, PT, R9, 0x4, RZ ?WAIT4_END_GROUP;
@!P4 IADD3 R9, PT, PT, R9, 0x1, RZ ?trans2;
@!P0 IADD3 R0, PT, PT, R0, R5, RZ &req={2} ?WAIT5_END_GROUP;
@!P1 IMAD R0, R11, 0x4, R0 &req={3} ?WAIT4_END_GROUP;
@!P2 IMAD R0, R3, 0x7, R0 &req={4} ?WAIT4_END_GROUP;
@!P3 IMAD R0, R13, 0x4, R0 &req={5} ?WAIT5_END_GROUP;
@!P4 IADD3 R0, PT, PT, R0, R7, RZ ?WAIT7_END_GROUP;
I2F.U32.RP R4, R9 &wr=0x0 ?trans1;
ISETP.NE.U32.AND P2, PT, R9, RZ, PT ?trans1;
MUFU.RCP R4, R4 &req={0} &wr=0x0 ?trans2;
IADD3 R2, PT, PT, R4, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x0 &wr=0x1 ?trans2;
MOV R2, RZ &req={0} ?trans1;
IADD3 R6, PT, PT, RZ, -R3, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R5, R6, R9, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R5, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R3, R0, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R9, R3, R0 ?trans2;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans3;
ISETP.GE.U32.AND P0, PT, R0, R9, PT ?WAIT13_END_GROUP;
@P0 IADD3 R0, PT, PT, R0, -R9, RZ ?trans2;
@P0 IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, R9, PT ?WAIT13_END_GROUP;
@P1 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xc40;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: convolve(unsigned char (*) [16], unsigned char*, int, int)
_Z8convolvePA16_hPhii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_mov_b32 s11, 0
s_mov_b32 s6, s5
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s9, -2
s_add_i32 s12, s8, 2
s_add_i32 s13, s9, 2
s_add_i32 s14, s8, -3
.LBB0_1:
s_cmp_gt_u32 s15, 15
s_mov_b32 s7, -1
s_cbranch_scc0 .LBB0_3
s_add_i32 s4, s6, 5
s_mov_b32 s7, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_9
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, __const._Z8convolvePA16_hPhii.kernel@rel32@lo+4
s_addc_u32 s9, s9, __const._Z8convolvePA16_hPhii.kernel@rel32@hi+12
s_ashr_i32 s7, s6, 31
s_mov_b32 s4, s14
s_lshl_b64 s[16:17], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s16, s8
s_addc_u32 s9, s17, s9
.LBB0_5:
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s4, 15
s_cbranch_scc1 .LBB0_7
s_lshl_b64 s[16:17], s[4:5], 4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s7, s0, s16
s_addc_u32 s17, s1, s17
s_add_u32 s16, s7, s15
s_addc_u32 s17, s17, 0
s_load_b32 s7, s[8:9], 0x0
global_load_u8 v1, v0, s[16:17]
s_waitcnt lgkmcnt(0)
s_add_i32 s11, s7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s16, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s16, s7, s16
s_add_i32 s10, s16, s10
.LBB0_7:
s_add_i32 s6, s6, 1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_ge_i32 s4, s12
s_cbranch_scc0 .LBB0_5
s_mov_b32 s4, s6
.LBB0_9:
s_add_i32 s7, s15, 1
s_cmp_ge_i32 s15, s13
s_cbranch_scc1 .LBB0_11
s_mov_b32 s6, s4
s_mov_b32 s15, s7
s_branch .LBB0_1
.LBB0_11:
s_ashr_i32 s0, s11, 31
s_ashr_i32 s6, s10, 31
s_add_i32 s1, s11, s0
s_add_i32 s7, s10, s6
s_xor_b32 s1, s1, s0
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v0, s1
s_sub_i32 s5, 0, s1
s_xor_b32 s0, s6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v0
v_mov_b32_e32 v0, 0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s1
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s1
s_cmp_ge_u32 s5, s1
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s1
s_cselect_b32 s1, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s1, s0
s_sub_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s0
global_store_b8 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| convolve | 5,684 | 1,689 | stackv2-00000-of-00015 |
// Demangled: Init(int, double*, double)
Function : _Z4InitiPdd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x380] &wr=0x1 ?trans1;
BSSY.RECONVERGENT B0, 0x130 ?trans1;
ISETP.GE.AND P0, PT, R7.reuse, UR4, PT &req={1} ?trans1;
LOP3.LUT R0, R7, 0x1, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
ISETP.EQ.U32.OR P1, PT, R0, 0x1, P0 ?WAIT13_END_GROUP;
@!P1 LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
@!P1 MOV.64 R4, 0xbff0000000000000 ?trans2;
@!P1 IMAD.WIDE.U32 R2, R7, 0x8, R2 &req={2} ?WAIT5_END_GROUP;
@!P1 STG.E.64 desc[UR4][R2.64], R4 &req={1} &rd=0x1 ?trans1;
@!P1 BRA 0x120 &req={0} ?trans5;
ISETP.EQ.OR P0, PT, R0, RZ, P0 ?WAIT13_END_GROUP;
@!P0 LDC.64 R4, c[0x0][0x388] &req={1} &wr=0x0 ?trans1;
@!P0 MOV.64 R2, 0x3ff0000000000000 ?trans2;
@!P0 IMAD.WIDE.U32 R4, R7, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
@!P0 STG.E.64 desc[UR4][R4.64], R2 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
EXIT ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: Init(int, double*, double)
_Z4InitiPdd:
s_load_b32 s2, s[0:1], 0x0
v_and_b32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s2, 0, v1
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0xbff00000
s_and_b32 s3, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s3, -1
s_and_saveexec_b32 s4, s5
s_xor_b32 s5, vcc_lo, -1
v_mov_b32_e32 v1, 0
s_or_b32 s2, s2, s5
v_mov_b32_e32 v2, 0x3ff00000
s_xor_b32 s2, s2, -1
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s2
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_4
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
| Init | 635 | 528 | stackv2-00000-of-00015 |
// Demangled: blur(unsigned char*, unsigned char*, int, int, int, double*, int)
Function : _Z4blurPhS_iiiPdi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.Y &wr=0x1 ?trans7;
LDC R3, c[0x0][0x360] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R0, SR_TID.X &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.Y &wr=0x1 ?trans8;
LDC R2, c[0x0][0x364] &wr=0x1 ?trans1;
MOV R34, UR6 &req={3} ?WAIT7_END_GROUP;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IMAD R2, R2, UR5, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR7, PT ?trans1;
IMAD R3, R3, UR4, R0 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R3, R34, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC R18, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?trans1;
CS2R R4, SRZ ?trans1;
ISETP.GE.AND P0, PT, R18, 0x1, PT &req={0} ?WAIT13_END_GROUP;
@!P0 BRA 0x1410 &req={1} ?trans5;
SHF.R.U32.HI R16, RZ, 0x1, R18 ?trans1;
UMOV UR4, URZ ?trans1;
LOP3.LUT R7, R18.reuse, 0x7, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R18, R18, 0x7ffffff8, RZ, 0xc0, !PT ?trans2;
IADD3 R6, PT, PT, R2, -R16, RZ ?WAIT4_END_GROUP;
IADD3 R4, PT, PT, R6.reuse, 0x6, RZ ?trans2;
IADD3 R5, PT, PT, R6.reuse, 0x5, RZ ?trans2;
IADD3 R8, PT, PT, R6.reuse, 0x4, RZ ?trans2;
IADD3 R0, PT, PT, R6.reuse, 0x7, RZ ?trans2;
IADD3 R10, PT, PT, R6.reuse, 0x3, RZ ?trans2;
IADD3 R12, PT, PT, R6, 0x2, RZ ?WAIT2_END_GROUP;
IADD3 R14, PT, PT, R6, 0x1, RZ ?trans1;
IMAD R11, R4, R34.reuse, R3.reuse ?trans2;
IMAD R13, R5, R34.reuse, R3.reuse ?trans1;
CS2R R4, SRZ ?trans1;
IMAD R15, R8, R34.reuse, R3.reuse ?trans2;
IMAD R9, R0, R34.reuse, R3.reuse ?trans1;
MOV R0, RZ ?trans1;
IMAD R17, R10, R34.reuse, R3.reuse ?trans1;
IADD3 R10, PT, PT, -R16, R11, RZ ?trans1;
IMAD R19, R12, R34.reuse, R3.reuse ?trans1;
IADD3 R11, PT, PT, -R16, R13, RZ ?trans1;
IMAD R21, R14, R34.reuse, R3.reuse ?trans1;
IADD3 R12, PT, PT, -R16, R15, RZ ?trans1;
IMAD R23, R6, R34, R3 ?trans1;
IADD3 R9, PT, PT, -R16, R9, RZ ?WAIT2_END_GROUP;
IADD3 R13, PT, PT, -R16.reuse, R17, RZ ?trans2;
IADD3 R14, PT, PT, -R16.reuse, R19, RZ ?trans2;
IADD3 R15, PT, PT, -R16.reuse, R21, RZ ?trans2;
IADD3 R8, PT, PT, -R16, R23, RZ ?trans2;
IADD3 R16, PT, PT, R3, -R16, RZ ?trans2;
IADD3 R17, PT, PT, -R18, RZ, RZ ?WAIT7_END_GROUP;
LDC R18, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R22, PT, PT, R16, UR4, RZ ?trans1;
UMOV UR5, URZ ?WAIT6_END_GROUP;
LDC R34, c[0x0][0x390] &wr=0x1 ?trans1;
ISETP.GE.U32.AND P1, PT, R18, 0x8, PT &req={0} ?trans1;
ISETP.GE.AND P0, PT, R22, R34, PT &req={1} ?WAIT5_END_GROUP;
ISETP.GT.AND P0, PT, R22, -0x1, !P0 ?WAIT7_END_GROUP;
@!P1 BRA 0xc60 ?trans6;
IADD3 R31, PT, PT, R9, UR4, RZ ?trans2;
IADD3 R25, PT, PT, R10, UR4, RZ ?trans2;
IADD3 R26, PT, PT, R11, UR4, RZ ?trans2;
IADD3 R27, PT, PT, R12, UR4, RZ ?trans2;
IADD3 R28, PT, PT, R13, UR4, RZ ?trans2;
IADD3 R29, PT, PT, R14, UR4, RZ ?WAIT2_END_GROUP;
IADD3 R30, PT, PT, R15, UR4, RZ ?trans2;
IADD3 R24, PT, PT, R8, UR4, RZ ?trans1;
MOV R23, R17 ?trans1;
MOV R32, R6 ?trans1;
IMAD R31, R31, 0x3, RZ ?trans1;
LDCU UR8, c[0x0][0x394] &wr=0x0 ?trans1;
IMAD R25, R25, 0x3, RZ ?trans2;
IMAD R26, R26, 0x3, RZ ?trans1;
UMOV UR5, 0x3 ?trans1;
IMAD R27, R27, 0x3, RZ ?WAIT2_END_GROUP;
IMAD R28, R28, 0x3, RZ ?trans2;
IMAD R29, R29, 0x3, RZ ?trans2;
IMAD R30, R30, 0x3, RZ ?trans2;
IMAD R24, R24, 0x3, RZ ?WAIT7_END_GROUP;
ISETP.LT.OR P1, PT, R32, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P2, PT, R32, UR8, P1 &req={0} ?WAIT13_END_GROUP;
@!P2 LDC.64 R18, c[0x0][0x380] &wr=0x0 ?trans1;
@!P2 SHF.R.S32.HI R21, RZ, 0x1f, R24 ?trans1;
@!P2 MOV R20, R24 ?WAIT5_END_GROUP;
@!P2 IADD.64 R18, R20, R18 &req={0} ?WAIT6_END_GROUP;
@!P2 LDG.E.U8 R35, desc[UR6][R18.64] &wr=0x2 ?trans1;
IADD3 R20, PT, PT, R32, 0x1, RZ ?WAIT3_END_GROUP;
@!P2 LDG.E.U8 R34, desc[UR6][R18.64+0x1] &wr=0x3 ?trans2;
ISETP.LT.OR P1, PT, R20.reuse, RZ, !P0 ?trans2;
@!P2 LDG.E.U8 R33, desc[UR6][R18.64+0x2] &rd=0x0 &wr=0x4 ?trans3;
ISETP.GE.OR P3, PT, R20, UR8, P1 ?WAIT13_END_GROUP;
@!P3 LDC.64 R20, c[0x0][0x380] &wr=0x1 ?trans1;
@!P3 SHF.R.S32.HI R19, RZ, 0x1f, R30 &req={0} ?trans1;
@!P3 MOV R18, R30 ?WAIT5_END_GROUP;
@!P3 IADD.64 R20, R18, R20 &req={1} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R32, 0x2, RZ ?trans2;
@!P2 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P3 LDG.E.U8 R35, desc[UR6][R20.64] &wr=0x2 ?trans1;
ISETP.LT.OR P1, PT, R36, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P1, PT, R36, UR8, P1 ?WAIT13_END_GROUP;
@!P1 LDC.64 R18, c[0x0][0x380] &wr=0x0 ?trans1;
@!P2 IADD3 R4, PT, PT, R4, R34, RZ &req={3} ?trans2;
@!P2 IADD3 R5, PT, PT, R5, R33, RZ &req={4} ?trans1;
@!P3 LDG.E.U8 R34, desc[UR6][R20.64+0x1] &wr=0x3 ?trans4;
@!P3 LDG.E.U8 R33, desc[UR6][R20.64+0x2] &rd=0x1 &wr=0x4 ?trans2;
@!P1 SHF.R.S32.HI R21, RZ, 0x1f, R29 &req={1} ?trans1;
@!P1 MOV R20, R29 ?WAIT5_END_GROUP;
@!P1 IADD.64 R18, R20, R18 &req={0} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R32, 0x3, RZ ?trans2;
@!P3 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P1 LDG.E.U8 R35, desc[UR6][R18.64] &wr=0x2 ?trans1;
ISETP.LT.OR P2, PT, R36, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P2, PT, R36, UR8, P2 ?WAIT13_END_GROUP;
@!P2 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
@!P3 IADD3 R4, PT, PT, R4, R34, RZ &req={3} ?trans2;
@!P1 LDG.E.U8 R34, desc[UR6][R18.64+0x1] &wr=0x3 ?trans1;
@!P3 IADD3 R5, PT, PT, R5, R33, RZ &req={4} ?WAIT3_END_GROUP;
@!P1 LDG.E.U8 R33, desc[UR6][R18.64+0x2] &rd=0x1 &wr=0x4 ?trans2;
@!P2 SHF.R.S32.HI R19, RZ, 0x1f, R28 &req={1} ?trans1;
@!P2 MOV R18, R28 ?WAIT5_END_GROUP;
@!P2 IADD.64 R20, R18, R20 &req={0} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R32, 0x4, RZ ?trans2;
@!P1 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P2 LDG.E.U8 R35, desc[UR6][R20.64] &wr=0x2 ?trans1;
ISETP.LT.OR P3, PT, R36, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P3, PT, R36, UR8, P3 ?WAIT13_END_GROUP;
@!P3 LDC.64 R18, c[0x0][0x380] &wr=0x0 ?trans1;
@!P1 IADD3 R4, PT, PT, R4, R34, RZ &req={3} ?trans2;
@!P2 LDG.E.U8 R34, desc[UR6][R20.64+0x1] &wr=0x3 ?trans1;
@!P1 IADD3 R5, PT, PT, R5, R33, RZ &req={4} ?WAIT3_END_GROUP;
@!P2 LDG.E.U8 R33, desc[UR6][R20.64+0x2] &rd=0x1 &wr=0x4 ?trans2;
@!P3 SHF.R.S32.HI R21, RZ, 0x1f, R27 &req={1} ?trans1;
@!P3 MOV R20, R27 ?WAIT5_END_GROUP;
@!P3 IADD.64 R18, R20, R18 &req={0} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R32, 0x5, RZ ?trans2;
@!P2 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P3 LDG.E.U8 R35, desc[UR6][R18.64] &wr=0x2 ?trans1;
ISETP.LT.OR P1, PT, R36, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P1, PT, R36, UR8, P1 ?WAIT13_END_GROUP;
@!P1 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
@!P2 IADD3 R4, PT, PT, R4, R34, RZ &req={3} ?trans2;
@!P3 LDG.E.U8 R34, desc[UR6][R18.64+0x1] &wr=0x3 ?trans1;
@!P2 IADD3 R5, PT, PT, R5, R33, RZ &req={4} ?WAIT3_END_GROUP;
@!P3 LDG.E.U8 R33, desc[UR6][R18.64+0x2] &rd=0x1 &wr=0x4 ?trans2;
@!P1 SHF.R.S32.HI R19, RZ, 0x1f, R26 &req={1} ?trans1;
@!P1 MOV R18, R26 ?WAIT5_END_GROUP;
@!P1 IADD.64 R20, R18, R20 &req={0} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R32, 0x6, RZ ?trans2;
@!P3 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P1 LDG.E.U8 R35, desc[UR6][R20.64] &wr=0x2 ?trans1;
ISETP.LT.OR P2, PT, R36, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P2, PT, R36, UR8, P2 ?WAIT13_END_GROUP;
@!P2 LDC.64 R18, c[0x0][0x380] &wr=0x0 ?trans1;
@!P3 IADD3 R4, PT, PT, R4, R34, RZ &req={3} ?trans2;
@!P1 LDG.E.U8 R34, desc[UR6][R20.64+0x1] &wr=0x3 ?trans1;
@!P3 IADD3 R5, PT, PT, R5, R33, RZ &req={4} ?WAIT3_END_GROUP;
@!P1 LDG.E.U8 R33, desc[UR6][R20.64+0x2] &rd=0x1 &wr=0x4 ?trans2;
@!P2 SHF.R.S32.HI R21, RZ, 0x1f, R25 &req={1} ?trans1;
@!P2 MOV R20, R25 ?WAIT5_END_GROUP;
@!P2 IADD.64 R18, R20, R18 &req={0} ?WAIT3_END_GROUP;
IADD3 R36, PT, PT, R32, 0x7, RZ ?trans2;
@!P1 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P2 LDG.E.U8 R35, desc[UR6][R18.64] &wr=0x2 ?trans1;
ISETP.LT.OR P3, PT, R36, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P3, PT, R36, UR8, P3 ?trans2;
@!P2 LDG.E.U8 R36, desc[UR6][R18.64+0x2] &wr=0x5 ?trans11;
@!P3 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
@!P1 IADD3 R5, PT, PT, R5, R33, RZ &req={4} ?WAIT2_END_GROUP;
@!P2 LDG.E.U8 R33, desc[UR6][R18.64+0x1] &rd=0x1 &wr=0x4 ?trans2;
@!P3 SHF.R.S32.HI R19, RZ, 0x1f, R31 &req={1} ?trans1;
@!P3 MOV R18, R31 ?WAIT5_END_GROUP;
@!P3 IADD.64 R20, R18, R20 &req={0} ?WAIT6_END_GROUP;
@!P3 LDG.E.U8 R37, desc[UR6][R20.64+0x1] &wr=0x4 ?trans1;
@!P2 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?WAIT3_END_GROUP;
@!P3 LDG.E.U8 R35, desc[UR6][R20.64] &wr=0x2 ?trans4;
@!P3 LDG.E.U8 R20, desc[UR6][R20.64+0x2] &wr=0x2 ?trans1;
@!P1 IADD3 R4, PT, PT, R4, R34, RZ &req={3} ?trans2;
LDC R34, c[0x0][0x390] &wr=0x0 ?trans1;
IADD3 R23, PT, PT, R23, 0x8, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R23, RZ, PT ?trans1;
@!P2 IADD3 R5, PT, PT, R5, R36, RZ &req={5} ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x8, URZ ?trans1;
@!P2 IADD3 R4, PT, PT, R4, R33, RZ &req={4} ?trans2;
IADD3 R32, PT, PT, R32, 0x8, RZ ?trans1;
IMAD R24, R34.reuse, 0x18, R24 &req={0} ?trans2;
IMAD R31, R34.reuse, 0x18, R31 ?trans2;
IMAD R25, R34, 0x18, R25 ?WAIT2_END_GROUP;
IMAD R26, R34.reuse, 0x18, R26 ?trans2;
IMAD R27, R34, 0x18, R27 ?trans1;
@!P3 IADD3 R4, PT, PT, R4, R37, RZ ?trans1;
IMAD R28, R34.reuse, 0x18, R28 ?trans2;
IMAD R29, R34.reuse, 0x18, R29 ?trans2;
IMAD R30, R34, 0x18, R30 ?trans1;
@!P3 IADD3 R0, PT, PT, R0, R35, RZ &req={2} ?trans2;
@!P3 IADD3 R5, PT, PT, R5, R20, RZ ?trans1;
@P1 BRA 0x500 ?trans6;
UIADD3 UR5, UPT, UPT, UR5, -0x3, URZ ?WAIT12_END_GROUP;
ISETP.NE.AND P1, PT, R7, RZ, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x13d0 ?trans5;
LDC R23, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R18, PT, PT, R7, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R18, 0x3, PT ?trans1;
LOP3.LUT P4, R32, R23, 0x3, RZ, 0xc0, !PT &req={0} ?WAIT12_END_GROUP;
@!P1 BRA 0x1070 ?trans5;
LDCU UR8, c[0x0][0x394] &wr=0x0 ?trans1;
IADD3 R19, PT, PT, R6, UR5, RZ ?WAIT4_END_GROUP;
IADD3 R27, PT, PT, R19.reuse, 0x1, RZ ?trans1;
ISETP.LT.OR P1, PT, R19.reuse, RZ, !P0 ?trans1;
IADD3 R29, PT, PT, R19.reuse, 0x2, RZ ?trans2;
IADD3 R33, PT, PT, R19, 0x3, RZ ?trans1;
ISETP.LT.OR P2, PT, R27, RZ, !P0 ?trans2;
ISETP.LT.OR P3, PT, R29, RZ, !P0 ?trans2;
ISETP.LT.OR P5, PT, R33, RZ, !P0 ?trans1;
ISETP.GE.OR P2, PT, R27, UR8, P2 &req={0} ?trans1;
ISETP.GE.OR P1, PT, R19, UR8, P1 ?trans1;
ISETP.GE.OR P3, PT, R29, UR8, P3 ?WAIT2_END_GROUP;
ISETP.GE.OR P5, PT, R33, UR8, P5 ?WAIT9_END_GROUP;
@!P2 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
@!P2 IMAD R28, R27, R34.reuse, R22.reuse ?trans2;
@!P1 IMAD R30, R19, R34.reuse, R22.reuse ?trans2;
@!P2 IMAD R28, R28, 0x3, RZ ?trans2;
@!P3 IMAD R26, R29, R34, R22 ?trans1;
@!P1 LDC.64 R24, c[0x0][0x380] &wr=0x1 ?trans1;
@!P1 IMAD R30, R30, 0x3, RZ ?trans1;
@!P2 SHF.R.S32.HI R29, RZ, 0x1f, R28 ?trans1;
@!P3 IMAD R26, R26, 0x3, RZ ?WAIT3_END_GROUP;
@!P1 SHF.R.S32.HI R31, RZ, 0x1f, R30 ?trans2;
@!P3 LDC.64 R18, c[0x0][0x380] &wr=0x2 ?trans1;
@!P3 SHF.R.S32.HI R27, RZ, 0x1f, R26 ?trans1;
@!P2 IADD.64 R28, R28, R20 &req={0} ?WAIT6_END_GROUP;
@!P5 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
@!P2 LDG.E.U8 R35, desc[UR6][R28.64] &wr=0x3 ?trans1;
@!P1 IADD.64 R24, R30, R24 &req={1} ?trans2;
@!P5 IMAD R30, R33, R34, R22 ?trans1;
@!P2 LDG.E.U8 R36, desc[UR6][R28.64+0x2] &wr=0x4 ?trans4;
@!P1 LDG.E.U8 R31, desc[UR6][R24.64+0x1] &wr=0x5 ?trans1;
@!P3 IADD.64 R18, R26, R18 &req={2} ?WAIT3_END_GROUP;
@!P1 LDG.E.U8 R27, desc[UR6][R24.64] &wr=0x2 ?trans4;
@!P1 LDG.E.U8 R26, desc[UR6][R24.64+0x2] &rd=0x1 &wr=0x3 ?trans4;
@!P2 LDG.E.U8 R33, desc[UR6][R28.64+0x1] &wr=0x4 ?trans4;
@!P3 LDG.E.U8 R37, desc[UR6][R18.64+0x1] &wr=0x4 ?trans1;
@!P5 IMAD R24, R30, 0x3, RZ &req={1} ?WAIT3_END_GROUP;
@!P3 LDG.E.U8 R30, desc[UR6][R18.64] &wr=0x4 ?trans2;
@!P5 SHF.R.S32.HI R25, RZ, 0x1f, R24 ?WAIT5_END_GROUP;
@!P5 IADD.64 R20, R24, R20 &req={0} ?trans2;
@!P3 LDG.E.U8 R18, desc[UR6][R18.64+0x2] &wr=0x4 ?trans4;
@!P5 LDG.E.U8 R25, desc[UR6][R20.64] &wr=0x4 ?trans4;
@!P5 LDG.E.U8 R24, desc[UR6][R20.64+0x1] &wr=0x4 ?trans4;
@!P5 LDG.E.U8 R20, desc[UR6][R20.64+0x2] &wr=0x4 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x4, URZ ?trans1;
@!P1 IADD3 R4, PT, PT, R4, R31, RZ &req={5} ?WAIT2_END_GROUP;
@!P1 IADD3 R0, PT, PT, R0, R27, RZ &req={2} ?trans2;
@!P1 IADD3 R5, PT, PT, R5, R26, RZ &req={3} ?trans2;
@!P2 IADD3 R0, PT, PT, R0, R35, RZ ?trans2;
@!P2 IADD3 R4, PT, PT, R4, R33, RZ &req={4} ?trans2;
@!P2 IADD3 R5, PT, PT, R5, R36, RZ ?trans2;
@!P3 IADD3 R4, PT, PT, R4, R37, RZ ?WAIT2_END_GROUP;
@!P3 IADD3 R0, PT, PT, R0, R30, RZ ?trans2;
@!P3 IADD3 R5, PT, PT, R5, R18, RZ ?trans2;
@!P5 IADD3 R0, PT, PT, R0, R25, RZ ?trans2;
@!P5 IADD3 R4, PT, PT, R4, R24, RZ ?trans2;
@!P5 IADD3 R5, PT, PT, R5, R20, RZ ?WAIT7_END_GROUP;
@!P4 BRA 0x13d0 ?trans5;
ISETP.NE.AND P1, PT, R32, 0x1, PT ?trans1;
LOP3.LUT R23, R23, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.NE.U32.AND P3, PT, R23, 0x1, PT ?WAIT7_END_GROUP;
@!P1 BRA 0x12a0 ?trans6;
LDCU UR8, c[0x0][0x394] &wr=0x0 ?trans1;
IADD3 R25, PT, PT, R6, UR5, RZ ?WAIT5_END_GROUP;
ISETP.LT.OR P1, PT, R25.reuse, RZ, !P0 ?trans1;
IADD3 R23, PT, PT, R25, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.LT.OR P2, PT, R23, RZ, !P0 ?trans1;
ISETP.GE.OR P1, PT, R25, UR8, P1 &req={0} ?WAIT4_END_GROUP;
ISETP.GE.OR P2, PT, R23, UR8, P2 ?WAIT9_END_GROUP;
@!P1 LDC.64 R20, c[0x0][0x380] &wr=0x0 ?trans1;
@!P1 IMAD R26, R25, R34, R22 ?WAIT3_END_GROUP;
@!P2 IMAD R24, R23, R34, R22 ?trans2;
@!P1 IMAD R26, R26, 0x3, RZ ?trans2;
@!P2 IMAD R24, R24, 0x3, RZ ?trans1;
@!P2 LDC.64 R18, c[0x0][0x380] &wr=0x1 ?trans2;
@!P1 SHF.R.S32.HI R27, RZ, 0x1f, R26 ?trans2;
@!P2 SHF.R.S32.HI R25, RZ, 0x1f, R24 ?WAIT3_END_GROUP;
@!P1 IADD.64 R20, R26, R20 &req={0} ?WAIT6_END_GROUP;
@!P1 LDG.E.U8 R23, desc[UR6][R20.64] &wr=0x2 ?trans1;
@!P2 IADD.64 R18, R24, R18 &req={1} ?WAIT3_END_GROUP;
@!P1 LDG.E.U8 R25, desc[UR6][R20.64+0x1] &wr=0x3 ?trans4;
@!P1 LDG.E.U8 R24, desc[UR6][R20.64+0x2] &wr=0x4 ?trans4;
@!P2 LDG.E.U8 R27, desc[UR6][R18.64] &wr=0x5 ?trans4;
@!P2 LDG.E.U8 R29, desc[UR6][R18.64+0x1] &wr=0x5 ?trans4;
@!P2 LDG.E.U8 R26, desc[UR6][R18.64+0x2] &wr=0x5 ?trans1;
UIADD3 UR5, UPT, UPT, UR5, 0x2, URZ ?trans1;
@!P1 IADD3 R0, PT, PT, R0, R23, RZ &req={2} ?WAIT2_END_GROUP;
@!P1 IADD3 R4, PT, PT, R4, R25, RZ &req={3} ?trans2;
@!P1 IADD3 R5, PT, PT, R5, R24, RZ &req={4} ?trans2;
@!P2 IADD3 R0, PT, PT, R0, R27, RZ &req={5} ?trans2;
@!P2 IADD3 R4, PT, PT, R4, R29, RZ ?trans2;
@!P2 IADD3 R5, PT, PT, R5, R26, RZ ?WAIT7_END_GROUP;
@P3 BRA 0x13d0 ?trans5;
LDCU UR8, c[0x0][0x394] &wr=0x0 ?trans1;
IADD3 R19, PT, PT, R6, UR5, RZ ?trans1;
BSSY.RECONVERGENT B0, 0x13d0 ?trans4;
ISETP.LT.OR P0, PT, R19, RZ, !P0 ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R19, UR8, P0 &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x13c0 ?trans5;
LDCU.64 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R18, R19, R34, R22 ?WAIT4_END_GROUP;
IMAD R18, R18, 0x3, RZ ?WAIT5_END_GROUP;
SHF.R.S32.HI R19, RZ, 0x1f, R18 ?WAIT5_END_GROUP;
IADD.64 R18, R18, UR8 &req={0} ?WAIT6_END_GROUP;
LDG.E.U8 R21, desc[UR6][R18.64] &wr=0x2 ?trans4;
LDG.E.U8 R23, desc[UR6][R18.64+0x1] &wr=0x3 ?trans4;
LDG.E.U8 R20, desc[UR6][R18.64+0x2] &wr=0x4 ?trans1;
IADD3 R0, PT, PT, R0, R21, RZ &req={2} ?trans2;
IADD3 R4, PT, PT, R4, R23, RZ &req={3} ?WAIT2_END_GROUP;
IADD3 R5, PT, PT, R5, R20, RZ &req={4} ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDC R18, c[0x0][0x398] &wr=0x0 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x1, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P0, PT, R18, UR4, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0x340 ?trans5;
LDC R7, c[0x0][0x3a8] &wr=0x0 ?trans1;
IABS R12, R0 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans1;
IABS R14, R4 ?trans1;
IMAD R2, R2, R34, R3 ?trans1;
IABS R16, R5 ?WAIT3_END_GROUP;
IMAD R2, R2, 0x3, RZ ?WAIT5_END_GROUP;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR8 &req={1} ?WAIT3_END_GROUP;
IABS R13, R7.reuse &req={0} ?trans2;
LOP3.LUT R0, R0, R7.reuse, RZ, 0x3c, !PT ?trans2;
I2F.RP R6, R13 &wr=0x0 ?trans1;
LOP3.LUT R4, R4, R7.reuse, RZ, 0x3c, !PT ?trans2;
LOP3.LUT R5, R5, R7, RZ, 0x3c, !PT ?trans1;
ISETP.GE.AND P1, PT, R0, RZ, PT ?trans1;
MUFU.RCP R6, R6 &req={0} &wr=0x0 ?trans2;
IADD3 R8, PT, PT, R6, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x0 &wr=0x1 ?trans2;
MOV R8, RZ &req={0} ?trans1;
IADD3 R10, PT, PT, RZ, -R9, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R11, R10, R13, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R9, R9, R11, R8 ?WAIT6_END_GROUP;
IMAD.HI.U32 R6, R9, R12, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R10, R9, R14, RZ ?trans1;
IADD3 R8, PT, PT, -R6, RZ, RZ ?WAIT3_END_GROUP;
IMAD.HI.U32 R11, R9, R16, RZ ?trans1;
IADD3 R9, PT, PT, -R10, RZ, RZ ?WAIT3_END_GROUP;
IMAD R8, R13, R8, R12 ?trans1;
IADD3 R15, PT, PT, -R11, RZ, RZ ?trans1;
IMAD R9, R13, R9, R14 ?WAIT3_END_GROUP;
ISETP.GT.U32.AND P0, PT, R13.reuse, R8, PT ?trans1;
IMAD R12, R13.reuse, R15, R16 ?trans1;
ISETP.GT.U32.AND P2, PT, R13, R9, PT ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P3, PT, R13, R12, PT ?WAIT7_END_GROUP;
@!P0 IADD3 R8, PT, PT, R8, -R13.reuse, RZ ?trans2;
@!P0 IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
@!P2 IADD3 R9, PT, PT, R9, -R13.reuse, RZ ?trans1;
ISETP.GE.AND P0, PT, R4, RZ, PT ?trans1;
@!P2 IADD3 R10, PT, PT, R10, 0x1, RZ ?trans1;
ISETP.GE.U32.AND P4, PT, R8, R13.reuse, PT ?trans1;
@!P3 IADD3 R12, PT, PT, R12, -R13.reuse, RZ ?trans1;
ISETP.GE.U32.AND P5, PT, R9, R13.reuse, PT ?trans1;
@!P3 IADD3 R11, PT, PT, R11, 0x1, RZ ?trans1;
ISETP.GE.AND P3, PT, R5, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R7, RZ, PT ?trans1;
ISETP.GE.U32.AND P6, PT, R12, R13, PT ?trans1;
LOP3.LUT R7, RZ, R7, RZ, 0x33, !PT ?WAIT6_END_GROUP;
@P4 IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
@P5 IADD3 R10, PT, PT, R10, 0x1, RZ ?trans2;
@!P1 IADD3 R6, PT, PT, -R6, RZ, RZ ?trans2;
@P6 IADD3 R11, PT, PT, R11, 0x1, RZ ?trans2;
@!P0 IADD3 R10, PT, PT, -R10, RZ, RZ ?trans1;
SEL R5, R7, R6, !P2 ?trans1;
@!P3 IADD3 R11, PT, PT, -R11, RZ, RZ ?WAIT3_END_GROUP;
SEL R9, R7.reuse, R10, !P2 ?trans1;
STG.E.U8 desc[UR6][R2.64], R5 ?trans1;
SEL R7, R7, R11, !P2 ?WAIT3_END_GROUP;
STG.E.U8 desc[UR6][R2.64+0x1], R9 ?trans4;
STG.E.U8 desc[UR6][R2.64+0x2], R7 ?trans1;
EXIT ?trans5;
BRA 0x17d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: blur(unsigned char*, unsigned char*, int, int, int, double*, int)
_Z4blurPhS_iiiPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[16:19], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_add_nc_u32_e32 v1, s14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s16, v1
v_cmp_gt_i32_e64 s2, s17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_11
s_load_b128 s[8:11], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, 0
s_cmp_lt_i32 s18, 1
s_mov_b32 s5, 0
s_cbranch_scc1 .LBB0_10
s_lshr_b32 s2, s18, 1
s_mul_i32 s6, s16, 3
v_subrev_nc_u32_e32 v5, s2, v0
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s16, v5
v_add3_u32 v2, v6, v2, s14
v_subrev_nc_u32_e32 v6, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s2, v2
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v7, v4, 1, v4
v_mov_b32_e32 v4, 0
.LBB0_3:
v_add_nc_u32_e32 v8, s5, v6
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v8
v_cmp_gt_i32_e64 s2, s16, v8
v_mov_b32_e32 v8, v7
.LBB0_4:
s_and_saveexec_b32 s12, vcc_lo
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v9, s7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, -1, v9
v_cmp_gt_i32_e64 s4, s17, v9
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v10, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s3, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s3, s9, v10, s3
s_clause 0x1
global_load_u16 v11, v[9:10], off
global_load_u8 v9, v[9:10], off offset:2
s_waitcnt vmcnt(1)
v_and_b32_e32 v10, 0xff, v11
v_lshrrev_b32_e32 v11, 8, v11
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, v2, v10
v_add_nc_u32_e32 v3, v3, v11
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s12
v_add_nc_u32_e32 v8, s6, v8
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, s7
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v7, 3, v7
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, s18
s_cbranch_scc0 .LBB0_3
.LBB0_10:
s_load_b32 s0, s[0:1], 0x28
v_ashrrev_i32_e32 v7, 31, v2
v_ashrrev_i32_e32 v8, 31, v3
v_ashrrev_i32_e32 v9, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v7
v_add_nc_u32_e32 v4, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v10, v2, v7
v_xor_b32_e32 v4, v4, v9
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s2
s_xor_b32 s3, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v5, s3
s_sub_i32 s0, 0, s3
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_hi_u32 v6, v10, v2
v_add_nc_u32_e32 v3, v3, v8
v_mul_hi_u32 v12, v4, v2
v_xor_b32_e32 v5, v3, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v13, v6, s3
v_mul_hi_u32 v11, v5, v2
v_mad_u64_u32 v[2:3], null, v0, s16, v[1:2]
v_xor_b32_e32 v3, s2, v8
v_mul_lo_u32 v0, v12, s3
v_sub_nc_u32_e32 v8, v10, v13
v_xor_b32_e32 v1, s2, v7
v_add_nc_u32_e32 v7, 1, v6
v_mul_lo_u32 v14, v11, s3
v_add_nc_u32_e32 v10, 1, v11
v_cmp_le_u32_e32 vcc_lo, s3, v8
v_lshl_add_u32 v2, v2, 1, v2
v_sub_nc_u32_e32 v0, v4, v0
v_cndmask_b32_e32 v4, v6, v7, vcc_lo
v_sub_nc_u32_e32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e64 s1, s3, v0
v_subrev_nc_u32_e32 v6, s3, v5
v_cmp_le_u32_e64 s0, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, v11, v10, s0
v_subrev_nc_u32_e32 v10, s3, v8
v_cndmask_b32_e64 v5, v5, v6, s0
v_add_nc_u32_e32 v13, 1, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, 1, v7
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s3, v5
v_cndmask_b32_e64 v11, v12, v13, s1
v_subrev_nc_u32_e32 v12, s3, v0
v_dual_cndmask_b32 v5, v7, v6 :: v_dual_add_nc_u32 v10, 1, v4
v_cmp_le_u32_e32 vcc_lo, s3, v8
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, v12, s1
v_add_nc_u32_e32 v6, 1, v11
v_xor_b32_e32 v7, s2, v9
v_xor_b32_e32 v5, v5, v3
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v5, v3
v_xor_b32_e32 v4, v4, v1
v_cndmask_b32_e32 v0, v11, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b16 v3, 8, v3
v_sub_nc_u32_e32 v1, v4, v1
v_ashrrev_i32_e32 v4, 31, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v5, v0, v7
v_add_co_u32 v0, vcc_lo, s10, v2
v_and_b32_e32 v6, 0xff, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v4, vcc_lo
v_sub_nc_u32_e32 v2, v5, v7
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v3, v6, v3
s_clause 0x1
global_store_b8 v[0:1], v2, off offset:2
global_store_b16 v[0:1], v3, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| blur | 10,688 | 3,532 | stackv2-00000-of-00015 |
// Demangled: jacobi(double*, double*, double*, int, double)
Function : _Z6jacobiPdS_S_id
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.Y &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X ?trans1;
LDCU UR6, c[0x0][0x370] &wr=0x2 ?trans1;
S2R R7, SR_TID.X &wr=0x3 ?trans1;
LDCU UR7, c[0x0][0x360] &wr=0x3 ?trans5;
S2UR UR5, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R4, c[0x0][0x364] &wr=0x1 ?trans8;
LDC R2, c[0x0][0x398] &wr=0x4 ?trans1;
UIMAD UR4, UR5, UR6, UR4 &req={2} ?WAIT6_END_GROUP;
IMAD R4, R4, UR4, R3 &req={1} ?WAIT4_END_GROUP;
IMAD R4, R4, UR7, R7 &req={3} ?trans2;
IMAD R5, R2, R2, RZ &req={4} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R4, R5, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
IABS R3, R2 ?trans1;
LDC.64 R14, c[0x0][0x380] &wr=0x0 ?trans1;
IABS R9, R4 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans1;
I2F.RP R0, R3 &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
MUFU.RCP R0, R0 &req={2} &wr=0x2 ?trans2;
IADD3 R6, PT, PT, R0, 0xffffffe, RZ &req={2} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R7, R6 &rd=0x2 &wr=0x4 ?trans2;
HFMA2 R6, -RZ, RZ, 0, 0 &req={2} ?trans1;
IADD3 R8, PT, PT, RZ, -R7, RZ &req={4} ?WAIT5_END_GROUP;
IMAD R5, R8, R3, RZ ?trans1;
MOV R8, R9 ?WAIT3_END_GROUP;
IMAD.HI.U32 R7, R7, R5, R6 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?WAIT5_END_GROUP;
IMAD.HI.U32 R7, R7, R8, RZ ?WAIT5_END_GROUP;
IADD3 R0, PT, PT, -R7, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R3, R0, R8 ?trans1;
IADD3 R8, PT, PT, R2, 0x2, RZ ?WAIT4_END_GROUP;
ISETP.GT.U32.AND P0, PT, R3, R0, PT ?trans1;
SHF.R.S32.HI R9, RZ, 0x1f, R8 ?WAIT12_END_GROUP;
@!P0 IADD3 R0, PT, PT, R0, -R3, RZ ?trans2;
@!P0 IADD3 R7, PT, PT, R7, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, R3, PT ?trans1;
LOP3.LUT R0, R4, R2, RZ, 0x3c, !PT ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT3_END_GROUP;
ISETP.GE.AND P0, PT, R0, RZ, PT ?WAIT7_END_GROUP;
@P1 IADD3 R7, PT, PT, R7, 0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R2, RZ, PT ?WAIT5_END_GROUP;
@!P0 IADD3 R7, PT, PT, -R7, RZ, RZ ?WAIT8_END_GROUP;
@!P1 LOP3.LUT R7, RZ, R2.reuse, RZ, 0x33, !PT ?trans1;
IADD.64 R2, R4, R2 ?WAIT3_END_GROUP;
IADD3 R6, PT, PT, R7, R7, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R7, RZ, 0x1f, R6 ?trans2;
IADD3 R5, PT, PT, R6, R4, R8 ?WAIT3_END_GROUP;
IADD.64 R2, R6, R2 ?trans2;
IMAD.WIDE R4, R5, 0x8, R14 &req={0} ?trans2;
IADD.64 R2, R2, 0x1 ?WAIT4_END_GROUP;
IADD.64 R16, R2.reuse, -R8.reuse ?trans2;
IADD.64 R18, R2, R8 ?trans2;
LDG.E.64 R4, desc[UR4][R4.64] &req={3} &wr=0x2 ?trans1;
SHF.L.U64.HI R3, R2.reuse, 0x3, R3 ?trans1;
IMAD.SHL.U32 R2, R2, 0x8, RZ ?trans1;
LEA R10, P0, R16, UR6, 0x3 &req={1} ?trans2;
LEA R12, P1, R18, UR6, 0x3 ?trans2;
IADD.64 R6, R2, R14 ?WAIT3_END_GROUP;
LEA.HI.X R11, R16, UR7, R17, 0x3, P0 ?trans2;
LEA.HI.X R13, R18, UR7, R19, 0x3, P1 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x0 ?trans1;
LDG.E.64 R6, desc[UR4][R6.64+0x18] &wr=0x2 ?trans4;
LDG.E.64 R10, desc[UR4][R10.64+0x10] &wr=0x3 ?trans4;
LDG.E.64 R12, desc[UR4][R12.64+0x10] &wr=0x4 ?trans1;
IADD.64 R14, R2, UR6 &req={0} ?WAIT2_END_GROUP;
LDCU.64 UR6, c[0x0][0x3a0] &wr=0x0 ?trans5;
LDG.E.64 R14, desc[UR4][R14.64+0x10] &wr=0x0 ?trans1;
DADD R8, R4, R6 &req={2} &rd=0x1 &wr=0x3 ?trans2;
LDC.64 R4, c[0x0][0x388] &req={1} &wr=0x1 ?trans2;
IADD.64 R2, R2, R4 &req={1} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R10 &req={3} &wr=0x4 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R12 &req={4} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R14, UR6, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, 0.25 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R2.64+0x10], R8 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x5e0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: jacobi(double*, double*, double*, int, double)
_Z6jacobiPdS_S_id:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v0
s_add_i32 s4, s2, s3
s_load_b64 s[8:9], s[0:1], 0x10
s_xor_b32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v1, s4
v_add_nc_u32_e32 v4, v0, v3
s_sub_i32 s5, 0, s4
v_add3_u32 v0, s2, 2, v0
v_rcp_iflag_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v4, 1, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_lshl_add_u32 v0, v1, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[4:5], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[8:9], v[4:5], off offset:8
v_sub_co_u32 v2, vcc_lo, v2, s2
v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_lshl_b64 s[2:3], s[2:3], 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off offset:-16
v_add_co_u32 v10, vcc_lo, s8, v0
global_load_b64 v[4:5], v[4:5], off offset:16
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[10:11], v[10:11], off offset:8
s_waitcnt vmcnt(3)
v_add_f64 v[6:7], v[6:7], v[8:9]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[6:7], v[2:3]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[10:11], s[0:1], v[2:3]
v_ldexp_f64 v[2:3], v[2:3], -2
global_store_b64 v[0:1], v[2:3], off offset:8
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| jacobi | 2,210 | 2,347 | stackv2-00000-of-00015 |
// Demangled: computeHistogram(int*, unsigned int*, int)
Function : _Z16computeHistogramPiPji
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R5, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R5, R0, UR4, R5 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDG.E R3, desc[UR4][R2.64] &req={1} &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans2;
IMAD.WIDE R4, R3, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR4][R4.64], R7 &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R4.64] &wr=0x2 ?trans2;
ISETP.GE.U32.AND P0, PT, R0, 0x80, PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
MOV R3, 0x7f ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R3 ?trans1;
EXIT ?trans5;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: computeHistogram(int*, unsigned int*, int)
_Z16computeHistogramPiPji:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, 0x7f, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0x7f
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| computeHistogram | 624 | 691 | stackv2-00000-of-00015 |
// Demangled: copy(int*, int const*)
Function : _Z4copyPiPKi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_CTAID.X &wr=0x0 ?trans7;
LDC R4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R13, SR_TID.X &wr=0x0 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x3 ?trans5;
LDC.64 R8, c[0x0][0x388] &wr=0x4 ?trans1;
S2R R10, SR_TID.Y &wr=0x3 ?trans1;
SHF.L.U32 R2, R4, 0x5, RZ &req={1} ?WAIT2_END_GROUP;
LEA R0, R0, R13, 0x5 &req={0} ?trans2;
LEA R3, R3, R10, 0x5 &req={3} ?WAIT5_END_GROUP;
IMAD R11, R3, R2, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R11, 0x4, R8 &req={4} ?trans1;
LEA R15, R4, R11, 0x8 ?WAIT4_END_GROUP;
LEA R17, R4.reuse, R15, 0x8 ?trans1;
LDG.E R0, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans3;
LEA R19, R4, R17, 0x8 ?trans1;
IMAD.WIDE R4, R15, 0x4, R8 ?WAIT4_END_GROUP;
IMAD.WIDE R6, R17, 0x4, R8.reuse ?trans1;
LDG.E R12, desc[UR6][R4.64] &wr=0x3 ?trans3;
IMAD.WIDE R8, R19, 0x4, R8 ?trans1;
LDG.E R14, desc[UR6][R6.64] &wr=0x4 ?trans4;
LDG.E R16, desc[UR6][R8.64] &rd=0x0 &wr=0x5 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
UMOV UR4, 0x400 ?trans1;
LEA R10, R10, R13, 0x5 ?WAIT6_END_GROUP;
LDC.64 R8, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R13, R10, UR4, 0x2 ?trans1;
IMAD.WIDE R2, R11, 0x4, R8 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R15, 0x4, R8 ?WAIT4_END_GROUP;
IMAD.WIDE R6, R17, 0x4, R8 ?WAIT4_END_GROUP;
IMAD.WIDE R8, R19, 0x4, R8 ?trans1;
STS [R13], R0 &req={2} ?trans4;
STS [R13+0x400], R12 &req={3} ?trans4;
STS [R13+0x800], R14 &req={4} ?trans4;
STS [R13+0xc00], R16 &req={5} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R21, [R13] &wr=0x0 ?trans4;
LDS R23, [R13+0x400] &wr=0x1 ?trans4;
LDS R25, [R13+0x800] &wr=0x2 ?trans4;
LDS R27, [R13+0xc00] &wr=0x3 ?trans4;
STG.E desc[UR6][R2.64], R21 &req={0} ?trans4;
STG.E desc[UR6][R4.64], R23 &req={1} ?trans4;
STG.E desc[UR6][R6.64], R25 &req={2} ?trans4;
STG.E desc[UR6][R8.64], R27 &req={3} ?trans1;
EXIT ?trans5;
BRA 0x2f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: copy(int*, int const*)
_Z4copyPiPKi:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, s15, 5, v1
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v1, 7, v3
v_mov_b32_e32 v4, v3
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, s4, v2
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 5, v2
v_add3_u32 v0, v0, v2, s5
s_mov_b32 s5, -8
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v0
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
v_add_nc_u32_e32 v4, 0x400, v4
s_cbranch_scc0 .LBB0_1
s_mov_b32 s2, -8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
ds_load_b32 v4, v3
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v3, 0x400, v3
s_add_i32 s2, s2, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s2, 23
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v4, off
s_cbranch_scc0 .LBB0_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| copy | 1,195 | 1,028 | stackv2-00000-of-00015 |
// Demangled: compute_histo_kernel(int*, unsigned long, unsigned char*, unsigned long, unsigned long)
Function : _Z20compute_histo_kernelPimPhmm
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
S2UR UR4, SR_CTAID.Y ?trans1;
S2R R2, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x370] &wr=0x2 ?trans4;
S2UR UR6, SR_CTAID.X &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x3a0] &wr=0x3 ?trans1;
UIMAD UR4, UR4, UR5, UR6 &req={2} ?WAIT4_END_GROUP;
USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ?trans1;
IMAD R2, R2, UR7, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.LE.U64.AND P0, PT, R4, UR4, PT &req={3} ?WAIT6_END_GROUP;
ISETP.GT.U32.OR P0, PT, R2, 0xff, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x398] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x390] &wr=0x1 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x2 ?trans1;
LDCU.128 UR12, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R0, R4.reuse, UR5, RZ &req={0} ?trans2;
IMAD.WIDE.U32 R2, R4, UR4, R2 ?WAIT4_END_GROUP;
IMAD R5, R5, UR4, R0 ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, R3, R5, RZ ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR6 &req={1} ?WAIT7_END_GROUP;
LDG.E.U8 R2, desc[UR10][R2.64] &req={2} &rd=0x0 &wr=0x2 ?trans1;
UIMAD UR8, UR5, UR14, URZ &req={3} ?trans1;
UIMAD.WIDE.U32 UR6, UR4, UR14, URZ ?WAIT3_END_GROUP;
UIMAD UR8, UR4, UR15, UR8 ?WAIT4_END_GROUP;
UIADD3 UR7, UPT, UPT, UR7, UR8, URZ ?trans1;
MOV R3, RZ &req={0} ?WAIT3_END_GROUP;
USHF.R.U64 UR6, UR6, 0x2, UR7 ?trans1;
USHF.R.U32.HI UR7, URZ, 0x2, UR7 ?WAIT6_END_GROUP;
IADD.64 R4, R2, UR6 &req={2} ?trans2;
HFMA2 R3, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT3_END_GROUP;
LEA R6, P0, R4, UR12, 0x2 ?WAIT4_END_GROUP;
LEA.HI.X R7, R4, UR13, R5, 0x2, P0 ?WAIT5_END_GROUP;
REDG.E.ADD.STRONG.GPU desc[UR10][R6.64], R3 ?trans1;
EXIT ?trans5;
BRA 0x260;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: compute_histo_kernel(int*, unsigned long, unsigned char*, unsigned long, unsigned long)
_Z20compute_histo_kernelPimPhmm:
s_load_b32 s4, s[0:1], 0x34
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u32_u24 v0, v0, s4, v1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[4:5], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s4, s[2:3], s[4:5]
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_3
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v1, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s2, s11
s_mul_hi_u32 s1, s2, s10
s_mul_i32 s11, s3, s10
s_add_i32 s0, s1, s0
s_mul_i32 s1, s2, s10
s_add_i32 s10, s0, s11
s_add_u32 s0, s8, s1
s_addc_u32 s1, s9, s10
s_mul_i32 s3, s3, s6
global_load_u8 v0, v0, s[0:1]
s_mul_i32 s0, s2, s7
s_mul_hi_u32 s1, s2, s6
s_mul_i32 s2, s2, s6
s_add_i32 s0, s1, s0
s_and_b32 s1, s2, -4
s_add_i32 s2, s0, s3
s_add_u32 s0, s4, s1
s_addc_u32 s1, s5, s2
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v0, 2, v0
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| compute_histo_kernel | 1,023 | 829 | stackv2-00000-of-00015 |
// Demangled: lbp_value_kernel(unsigned char const*, unsigned char*, int, int, unsigned long)
Function : _Z16lbp_value_kernelPKhPhiim
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.Y &wr=0x1 ?trans1;
LDCU UR6, c[0x0][0x360] &wr=0x2 ?trans6;
LDC.64 R2, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x364] &wr=0x1 ?trans1;
S2R R6, SR_CTAID.X &wr=0x2 ?trans1;
S2R R9, SR_TID.X &wr=0x2 ?trans1;
IMAD R13, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R13, R3, PT &req={3} ?trans1;
IMAD R15, R6, UR6, R9 &req={2} ?WAIT5_END_GROUP;
ISETP.GE.OR P0, PT, R15, R2, P0 ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.NE.AND P4, PT, R9, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R0.reuse, RZ, PT ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R10, R13, R2, R15 ?trans2;
ISETP.EQ.OR P1, PT, R0.reuse, RZ, !P4 ?trans1;
ISETP.GT.U32.OR P0, PT, R0, 0xe, !P4 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT6_END_GROUP;
@P2 IMAD R16, R13, R2, -R2 ?WAIT4_END_GROUP;
@!P1 IMAD R18, R13, R2, -R2.reuse ?trans1;
@P2 IADD3 R16, PT, PT, R15, R16, RZ ?trans1;
@!P0 IMAD R20, R13, R2, R2 ?trans1;
IADD.64 R4, R10, UR8 &req={0} ?WAIT3_END_GROUP;
@!P1 IADD3 R18, PT, PT, R15, -0x1, R18 ?trans2;
@P2 SHF.R.S32.HI R17, RZ, 0x1f, R16 ?trans1;
LDG.E.U8 R3, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans1;
@!P1 SHF.R.S32.HI R19, RZ, 0x1f, R18 ?WAIT3_END_GROUP;
@P2 IADD.64 R16, R16, UR8 ?trans2;
@!P1 IADD.64 R18, R18, UR8 ?trans2;
@P4 LDG.E.U8 R12, desc[UR4][R4.64+-0x1] &wr=0x2 ?trans1;
@!P0 IADD3 R20, PT, PT, R15, -0x1, R20 ?WAIT3_END_GROUP;
@P2 LDG.E.U8 R16, desc[UR4][R16.64] &rd=0x0 &wr=0x3 ?trans1;
@!P0 SHF.R.S32.HI R21, RZ, 0x1f, R20 ?WAIT3_END_GROUP;
@!P1 LDG.E.U8 R18, desc[UR4][R18.64] &wr=0x4 ?trans2;
@!P0 IADD.64 R20, R20, UR8 ?WAIT7_END_GROUP;
@!P0 LDG.E.U8 R20, desc[UR4][R20.64] &wr=0x5 ?trans1;
PRMT R8, RZ, 0x7610, R8 ?trans2;
PRMT R17, RZ, 0x7610, R17 &req={0} ?trans1;
BSSY.RECONVERGENT B1, 0x460 ?trans4;
BSSY.RELIABLE B0, 0x3f0 ?trans1;
@P4 ISETP.GE.U32.AND P6, PT, R12, R3.reuse, PT &req={2} ?trans1;
@P2 ISETP.GE.U32.AND P3, PT, R16, R3.reuse, PT &req={3} ?trans1;
@!P1 ISETP.GE.U32.AND P5, PT, R18, R3, PT &req={4} ?WAIT4_END_GROUP;
@P2 SEL R8, RZ, 0xff80, !P3 ?trans1;
PRMT R12, RZ, 0x7610, R12 ?trans1;
@!P1 SEL R17, RZ, 0x40, !P5 ?trans1;
@P4 SEL R12, RZ, 0x20, !P6 ?WAIT4_END_GROUP;
LOP3.LUT R17, R17, R8, RZ, 0xfc, !PT ?trans1;
@!P0 ISETP.GE.U32.AND P1, PT, R20, R3, PT &req={5} ?WAIT3_END_GROUP;
LOP3.LUT R12, R17, R12, RZ, 0xfc, !PT ?trans2;
@!P0 SEL R17, RZ, 0x10, !P1 ?trans2;
PRMT R8, R12, 0x7610, R8 ?WAIT4_END_GROUP;
@!P0 LOP3.LUT R17, R17, R8, RZ, 0xfc, !PT ?WAIT4_END_GROUP;
@!P0 PRMT R8, R17, 0x7610, R8 ?trans1;
@!P0 BRA 0x3e0 ?trans6;
ISETP.GT.U32.AND P0, PT, R0, 0xe, PT ?trans1;
PRMT R17, RZ, 0x7610, R17 ?WAIT12_END_GROUP;
@P0 BREAK.RELIABLE B0 ?trans5;
@P0 BRA 0x450 ?trans5;
BSYNC.RELIABLE B0 ?trans5;
IADD3 R10, PT, PT, R10, R2, RZ ?WAIT4_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT5_END_GROUP;
IADD.64 R10, R10, UR8 ?WAIT7_END_GROUP;
LDG.E.U8 R10, desc[UR4][R10.64] &wr=0x2 ?trans2;
ISETP.GE.U32.AND P0, PT, R10, R3, PT &req={2} ?WAIT5_END_GROUP;
SEL R17, RZ, 0x8, !P0 ?WAIT8_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
VIMNMX.U32 R10, R9, R0, !PT ?trans1;
BSSY.RECONVERGENT B1, 0x6d0 ?trans4;
BSSY.RELIABLE B2, 0x5e0 ?trans1;
LOP3.LUT R8, R17, R8, RZ, 0xfc, !PT ?trans1;
ISETP.GT.U32.AND P0, PT, R10, 0xe, PT ?WAIT13_END_GROUP;
@P0 BRA 0x570 ?trans5;
IMAD R10, R13, R2, R2 ?WAIT5_END_GROUP;
IADD3 R10, PT, PT, R15, 0x1, R10 ?WAIT4_END_GROUP;
SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT5_END_GROUP;
IADD.64 R10, R10, UR8 ?WAIT7_END_GROUP;
LDG.E.U8 R10, desc[UR4][R10.64] &wr=0x2 ?trans2;
ISETP.GE.U32.AND P0, PT, R10, R3, PT &req={2} ?WAIT5_END_GROUP;
SEL R12, RZ, 0x4, !P0 ?WAIT5_END_GROUP;
PRMT R17, R12, 0x7610, R17 ?trans1;
BRA 0x5d0 ?trans6;
ISETP.GT.U32.AND P0, PT, R9, 0xe, PT ?trans1;
PRMT R17, RZ, 0x7610, R17 ?trans2;
PRMT R12, RZ, 0x7610, R12 ?trans2;
PRMT R14, RZ, 0x7610, R14 ?WAIT8_END_GROUP;
@P0 BREAK.RELIABLE B2 ?trans5;
@P0 BRA 0x6c0 ?trans5;
BSYNC.RELIABLE B2 ?trans5;
ISETP.GT.U32.AND P0, PT, R9, 0xe, PT ?trans1;
LDG.E.U8 R4, desc[UR4][R4.64+0x1] &wr=0x2 ?trans4;
ISETP.EQ.OR P0, PT, R0, RZ, P0 ?WAIT13_END_GROUP;
@!P0 IMAD R10, R13, R2, -R2 ?WAIT5_END_GROUP;
@!P0 IADD3 R10, PT, PT, R15, 0x1, R10 ?WAIT4_END_GROUP;
@!P0 SHF.R.S32.HI R11, RZ, 0x1f, R10 ?WAIT5_END_GROUP;
@!P0 IADD.64 R10, R10, UR8 ?WAIT7_END_GROUP;
@!P0 LDG.E.U8 R10, desc[UR4][R10.64] &wr=0x3 ?trans1;
PRMT R14, RZ, 0x7610, R14 ?trans1;
ISETP.GE.U32.AND P2, PT, R4, R3, PT &req={2} ?WAIT5_END_GROUP;
SEL R12, RZ, 0x2, !P2 ?trans1;
@!P0 ISETP.GE.U32.AND P1, PT, R10, R3, PT &req={3} ?WAIT5_END_GROUP;
@!P0 SEL R3, RZ, 0x1, !P1 ?WAIT5_END_GROUP;
@!P0 PRMT R14, R3, 0x7610, R14 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B1 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
LDCU.64 UR10, c[0x0][0x398] &wr=0x0 ?trans1;
IMAD R7, R7, R2, RZ ?trans2;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans2;
IMAD R2, R0, UR6, R9 ?trans1;
LDCU.64 UR12, c[0x0][0x388] &wr=0x1 ?trans1;
LOP3.LUT R17, R17, R8, R12, 0xfe, !PT ?WAIT2_END_GROUP;
LEA.HI R7, R7, R6, RZ, 0x1c ?trans2;
LOP3.LUT R17, R17, R14, RZ, 0xfc, !PT ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R2, R7, UR10, R2 &req={0} ?WAIT4_END_GROUP;
IMAD R3, R7, UR11, R3 ?WAIT5_END_GROUP;
IADD.64 R2, R2, UR12 &req={1} ?WAIT6_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R17 ?trans1;
EXIT ?trans5;
BRA 0x7c0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: lbp_value_kernel(unsigned char const*, unsigned char*, int, int, unsigned long)
_Z16lbp_value_kernelPKhPhiim:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s10, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
v_mad_u64_u32 v[2:3], null, s14, s10, v[1:2]
v_cmp_gt_i32_e64 s2, s9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v6, v5, s8
v_mov_b32_e32 v7, 0
v_add_nc_u32_e32 v9, -1, v5
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v6, v2
v_ashrrev_i32_e32 v4, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
global_load_u8 v8, v[3:4], off
s_waitcnt vmcnt(0)
v_dual_mov_b32 v8, 0 :: v_dual_and_b32 v5, 0xff, v8
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_3
v_mad_u64_u32 v[12:13], null, v9, s8, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v12
v_add_co_u32 v12, s2, s4, v12
v_add_co_ci_u32_e64 v13, s2, s5, v8, s2
global_load_u8 v8, v[12:13], off
s_waitcnt vmcnt(0)
v_cmp_lt_u16_e64 s2, v8, v5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0xffffff80, 0, s2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_ne_u32_e64 s2, 0, v1
s_xor_b32 s3, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[12:13], null, v9, s8, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v12
v_add_co_u32 v9, s2, s4, v12
v_add_co_ci_u32_e64 v10, s2, s5, v7, s2
global_load_u8 v7, v[9:10], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e64 s2, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 0, 1, s2
v_lshlrev_b16 v7, 6, v7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_ne_u32_e64 s3, 0, v1
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB0_7
global_load_u8 v10, v[3:4], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e64 s2, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, 1, s2
v_lshlrev_b16 v10, 5, v10
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v13, s8, v11
v_cmp_gt_u32_e64 s2, 15, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v13
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB0_9
v_add_co_u32 v11, s3, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s3, s5, v14, s3
global_load_u8 v9, v[11:12], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e64 s3, v9, v5
v_cndmask_b32_e64 v9, 0, 1, s3
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b16 v9, 4, v9
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s9
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_11
v_add_co_u32 v15, s3, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s3, s5, v14, s3
global_load_u8 v12, v[15:16], off
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e64 s3, v12, v5
v_cndmask_b32_e64 v12, 0, 1, s3
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b16 v12, 3, v12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s9
v_cmp_gt_u32_e64 s3, 15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
v_add_co_u32 v13, s2, s4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s2, s5, v14, s2
global_load_u8 v11, v[13:14], off offset:1
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e64 s2, v11, v5
v_cndmask_b32_e64 v11, 0, 1, s2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b16 v11, 2, v11
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_u32_e64 s2, 14, v1
v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v13, 0
s_mov_b32 s9, exec_lo
v_cmpx_gt_u32_e32 15, v1
s_cbranch_execz .LBB0_15
global_load_u8 v3, v[3:4], off offset:1
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e64 s3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0, 1, s3
v_lshlrev_b16 v13, 1, v3
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s9
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_17
v_subrev_nc_u32_e32 v3, s8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v3, v2
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_u8 v2, v[2:3], off offset:1
s_waitcnt vmcnt(0)
v_cmp_ge_u16_e32 vcc_lo, v2, v5
v_cndmask_b32_e64 v14, 0, 1, vcc_lo
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
v_or_b32_e32 v2, v7, v8
s_load_b64 s[0:1], s[0:1], 0x18
s_mul_i32 s15, s15, s8
v_mad_u32_u24 v0, v0, s10, v1
s_lshr_b32 s2, s15, 4
v_or_b32_e32 v2, v2, v10
s_add_i32 s2, s2, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v2, v9
v_or_b32_e32 v2, v2, v12
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v2, v2, v11
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s1
s_mul_hi_u32 s3, s2, s0
s_mul_i32 s2, s2, s0
s_add_i32 s3, s3, s1
v_or_b32_e32 v2, v2, v13
s_add_u32 s0, s6, s2
s_addc_u32 s1, s7, s3
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v1, v2, v14
global_store_b8 v0, v1, s[0:1]
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| lbp_value_kernel | 3,178 | 3,413 | stackv2-00000-of-00015 |
// Demangled: addKernel(int*, int const*, int const*)
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: addKernel(int*, int const*, int const*)
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| addKernel | 427 | 201 | stackv2-00000-of-00015 |
// Demangled: kernel(float*, float*, int)
Function : _Z6kernelPfS_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x390] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IADD3 R7, PT, PT, R9.reuse, 0x2, RZ ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R4 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R7, 0x4, R4 ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans3;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R0, R2, R5 &req={2} ?WAIT4_END_GROUP;
FMUL R9, R0, 0.5 ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R9 ?trans1;
EXIT ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: kernel(float*, float*, int)
_Z6kernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, 2, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0.5, v0
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[0:1], v2, off offset:4
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| kernel | 586 | 680 | stackv2-00000-of-00015 |
// Demangled: AddOneKernel(int const*, int, int*)
Function : _Z12AddOneKernelPKiiPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x388] &wr=0x2 ?trans7;
LDC R11, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R11, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R6, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x1 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R8, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD R11, R11, UR4, RZ &req={1} ?WAIT7_END_GROUP;
IMAD.WIDE R2, R0, 0x4, R6 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR6][R2.64] &req={2} &wr=0x2 ?trans1;
IMAD.WIDE R4, R0, 0x4, R8 &req={3,1} ?trans1;
IADD3 R0, PT, PT, R11, R0, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT ?trans1;
IADD3 R13, PT, PT, R2, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R13 &rd=0x1 ?trans7;
@!P0 BRA 0xd0 ?trans5;
EXIT ?trans5;
BRA 0x160;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: AddOneKernel(int const*, int, int*)
_Z12AddOneKernelPKiiPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s7
s_mov_b32 s7, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s6, v1
v_add_co_u32 v2, s0, s4, v2
global_load_b32 v0, v[4:5], off
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| AddOneKernel | 612 | 678 | stackv2-00000-of-00015 |
// Demangled: vecadd(float*, float*, float*)
Function : _Z6vecaddPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={2} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecadd(float*, float*, float*)
_Z6vecaddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecadd | 420 | 192 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R9, R9, 0x3, RZ &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={3} ?trans1;
LDG.E R0, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R11, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?trans1;
IADD3 R11, PT, PT, R0, R11, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R11 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x4] &wr=0x2 ?trans4;
LDG.E R9, desc[UR4][R4.64+0x4] &wr=0x2 ?trans2;
IADD3 R9, PT, PT, R0, R9, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x4], R9 ?trans4;
LDG.E R0, desc[UR4][R2.64+0x8] &wr=0x2 ?trans4;
LDG.E R13, desc[UR4][R4.64+0x8] &wr=0x2 ?trans2;
IADD3 R13, PT, PT, R0, R13, RZ &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64+0x8], R13 ?trans1;
EXIT ?trans5;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_u32_u24_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s2, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s5, 0, s2
v_add_co_u32 v2, s2, s6, v4
v_add_co_u32 v4, s0, s0, v4
v_add_co_ci_u32_e64 v3, null, s7, 0, s2
v_add_co_ci_u32_e64 v5, null, s1, 0, s0
s_mov_b64 s[0:1], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v6, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
global_load_b32 v10, v[6:7], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v6, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 12
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, v8, v10
global_store_b32 v[6:7], v8, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 688 | 614 | stackv2-00000-of-00015 |
// Demangled: convolution2D(float*, float*, int, int)
Function : _Z13convolution2DPfS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x364] &wr=0x2 ?trans1;
S2R R2, SR_CTAID.Y &wr=0x2 ?trans1;
LDCU UR6, c[0x0][0x390] &wr=0x3 ?trans1;
S2R R3, SR_TID.Y &wr=0x2 ?trans1;
IMAD R9, R9, UR4, R0 &req={1} ?trans2;
IMAD R2, R2, UR5, R3 &req={2} ?WAIT5_END_GROUP;
VIMNMX.S32 R0, R9, R2, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR6, PT &req={3} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
ISETP.NE.AND P1, PT, R2, RZ, PT ?trans1;
BSSY.RECONVERGENT B1, 0x2b0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans3;
BSSY.RELIABLE B0, 0x240 ?trans1;
ISETP.LT.OR P0, PT, R9, 0x1, !P1 ?WAIT13_END_GROUP;
@P0 BRA 0x1e0 ?trans5;
LDCU UR7, c[0x0][0x394] &wr=0x1 ?trans1;
IADD3 R4, PT, PT, R9, -0x1, RZ ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x2 ?trans3;
IMAD R4, R4, UR7, RZ &req={1} ?WAIT5_END_GROUP;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?WAIT5_END_GROUP;
IADD.64 R4, R4, R2 ?WAIT5_END_GROUP;
LEA R6, P0, R4, UR8, 0x2 &req={2} ?WAIT4_END_GROUP;
LEA.HI.X R7, R4, UR9, R5, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R0, desc[UR4][R6.64+-0x4] &req={0} &rd=0x0 &wr=0x5 ?trans1;
BRA 0x230 ?trans5;
ISETP.GE.AND P0, PT, R9, 0x1, PT ?trans1;
HFMA2 R19, -RZ, RZ, 0, 0 ?trans1;
MOV R0, RZ ?WAIT11_END_GROUP;
@!P0 BREAK.RELIABLE B0 ?trans5;
@!P0 BRA 0x2a0 ?trans5;
BSYNC.RELIABLE B0 &req={0} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR7, c[0x0][0x394] &wr=0x1 ?trans1;
IADD3 R7, PT, PT, R9, -0x1, RZ ?WAIT5_END_GROUP;
IMAD R7, R7, UR7, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E R19, desc[UR4][R4.64] &rd=0x1 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 &req={0} ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
LDCU UR7, c[0x0][0x394] &wr=0x0 ?trans1;
IADD3 R4, PT, PT, R2.reuse, 0x1, RZ &req={1} ?trans1;
ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ?trans1;
IADD3 R7, PT, PT, R9, 0x1, RZ ?trans1;
LDCU.64 UR8, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R16, R2 ?trans1;
HFMA2 R17, -RZ, RZ, 0, 0 ?trans1;
MOV R18, RZ ?trans1;
ISETP.GE.OR P0, PT, R7, UR6, !P0 ?trans1;
HFMA2 R6, -RZ, RZ, 0, 0 ?trans1;
ISETP.GE.AND P2, PT, R4, UR7, PT &req={0} ?trans1;
IMAD R4, R9, UR7, RZ ?WAIT10_END_GROUP;
@!P0 IMAD R12, R7, UR7, RZ ?trans1;
ISETP.LT.OR P3, PT, R9, 0x1, P2 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R4 ?WAIT3_END_GROUP;
@!P0 SHF.R.S32.HI R13, RZ, 0x1f, R12 ?trans2;
IADD.64 R20, R16, R4 ?WAIT3_END_GROUP;
@!P0 IADD.64 R12, R16, R12 ?WAIT4_END_GROUP;
@!P3 IADD3 R8, PT, PT, R9, -0x1, RZ ?trans1;
@!P3 MOV R9, RZ ?WAIT4_END_GROUP;
@!P3 IMAD R8, R8, UR7, RZ ?WAIT5_END_GROUP;
@!P3 IADD.64 R8, R16, R8 ?WAIT5_END_GROUP;
@!P3 LEA R14, P4, R8, UR8, 0x2 &req={1} ?WAIT4_END_GROUP;
@!P3 LEA.HI.X R15, R8, UR9, R9, 0x2, P4 ?trans2;
LEA R10, P4, R20.reuse, UR8, 0x2 ?trans1;
LDC.64 R8, c[0x0][0x388] &wr=0x0 ?trans2;
@!P3 LDG.E R6, desc[UR4][R14.64+0x4] &wr=0x2 ?trans1;
LEA.HI.X R11, R20, UR9, R21, 0x2, P4 ?trans1;
HFMA2 R20, -RZ, RZ, 0, 0 ?trans1;
@!P0 LEA R16, P3, R12, UR8, 0x2 ?WAIT3_END_GROUP;
@P1 LDG.E R18, desc[UR4][R10.64+-0x4] &wr=0x3 ?trans1;
@!P0 LEA.HI.X R17, R12, UR9, R13, 0x2, P3 ?trans1;
MOV R12, RZ ?trans2;
@!P2 LDG.E R20, desc[UR4][R10.64+0x4] &wr=0x4 ?trans4;
@!P0 LDG.E R12, desc[UR4][R16.64+-0x4] &wr=0x4 ?trans1;
FADD R19, R19, R0 &req={5} ?trans1;
ISETP.GE.AND P0, PT, R7, UR6, PT ?trans1;
BSSY.RECONVERGENT B1, 0x600 ?trans1;
HFMA2 R0, -RZ, RZ, 0, 0 ?WAIT2_END_GROUP;
FADD R19, R19, R6 &req={2} ?WAIT4_END_GROUP;
FADD R19, R19, R18 &req={3} ?WAIT4_END_GROUP;
FADD R19, R19, R20 &req={4} ?WAIT4_END_GROUP;
FADD R19, R19, R12 ?trans1;
MOV R12, RZ ?trans1;
@P0 BRA 0x5f0 &req={0} ?trans6;
LDC.64 R10, c[0x0][0x380] &wr=0x0 ?trans1;
IMAD R7, R7, UR7, R2 ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R10 &req={0} ?WAIT5_END_GROUP;
@!P2 LDG.E R12, desc[UR4][R6.64+0x4] &rd=0x0 &wr=0x5 ?trans4;
LDG.E R0, desc[UR4][R6.64] &rd=0x0 &wr=0x5 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
FADD R19, R19, R0 &req={5} ?trans1;
IADD3 R3, PT, PT, R2, R4, RZ ?WAIT3_END_GROUP;
FADD R12, R19, R12 ?trans2;
IMAD.WIDE R8, R3, 0x4, R8 ?WAIT4_END_GROUP;
FMUL R3, R12, 0.125 ?WAIT5_END_GROUP;
STG.E desc[UR4][R8.64], R3 ?trans1;
EXIT ?trans5;
BRA 0x670;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: convolution2D(float*, float*, int, int)
_Z13convolution2DPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_20
s_load_b128 s[4:7], s[0:1], 0x0
v_cmp_lt_i32_e64 s0, 0, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, -1, v0
v_ashrrev_i32_e32 v3, 31, v1
v_mov_b32_e32 v4, 0
s_and_b32 s1, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s8, s1
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v4, v7, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, s1, v1, v4
v_add_co_ci_u32_e64 v5, s1, v3, v5, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s1, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, s5, v5, s1
global_load_b32 v4, v[4:5], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s0
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[5:6], null, v7, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s1, s4, v5
v_add_co_ci_u32_e64 v6, s1, s5, v6, s1
global_load_b32 v2, v[5:6], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v8, 1, v1
v_mov_b32_e32 v6, 0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v6, 0
s_mov_b32 s8, exec_lo
v_cmpx_gt_i32_e64 s3, v8
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v6, v7, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, s0, v6, v1
v_add_co_ci_u32_e64 v7, s0, v7, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v6, v[6:7], off offset:4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_mul_lo_u32 v9, v0, s3
v_ashrrev_i32_e32 v10, 31, v9
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_11
v_add_co_u32 v11, vcc_lo, v1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v12, vcc_lo, v3, v10, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v5, v[11:12], off offset:-4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_i32_e32 vcc_lo, s3, v8
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_13
v_add_co_u32 v8, s0, v1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, v3, v10, s0
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s4, v8
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
global_load_b32 v8, v[8:9], off offset:4
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v13, 1, v0
v_cmp_lt_i32_e64 s1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v13, s3
v_cmp_gt_i32_e64 s0, s2, v13
s_and_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_15
v_add_co_u32 v11, s1, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s1, v10, v3, s1
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s1, s4, v11
v_add_co_ci_u32_e64 v12, s1, s5, v12, s1
global_load_b32 v7, v[11:12], off offset:-4
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_17
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[14:15], null, v13, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[12:13], 2, v[14:15]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s1, s4, v12
v_add_co_ci_u32_e64 v13, s1, s5, v13, s1
global_load_b32 v12, v[12:13], off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
s_and_b32 s1, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_19
v_add_co_u32 v9, vcc_lo, v9, v1
v_add_co_ci_u32_e32 v10, vcc_lo, v10, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v11, v[9:10], off offset:4
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v6
v_add_f32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v2, v8
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_add_f32_e32 v0, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_f32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v0, v11
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x3e000000, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| convolution2D | 2,524 | 3,606 | stackv2-00000-of-00015 |
// Demangled: gpu_matrix_multiply(float*, float*, float*, int)
Function : _Z19gpu_matrix_multiplyPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R2, c[0x0][0x370] &wr=0x1 ?trans1;
S2R R23, SR_CTAID.Y &wr=0x2 ?trans1;
LDCU UR7, c[0x0][0x398] &wr=0x3 ?trans1;
HFMA2 R31, -RZ, RZ, 0, 0 ?trans1;
S2R R0, SR_TID.Y &wr=0x2 ?trans1;
UMOV UR4, 0x400 ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x4 ?trans2;
S2UR UR6, SR_CgaCtaId &wr=0x5 ?trans1;
S2R R10, SR_TID.X &wr=0x0 ?trans1;
UIADD3 UR5, UPT, UPT, UR4, 0x400, URZ ?trans1;
S2R R8, SR_CTAID.X &wr=0x0 ?trans1;
MOV R27, UR7 &req={3} ?trans1;
ISETP.NE.AND P0, PT, R2, 0x1, PT &req={1} ?WAIT4_END_GROUP;
IMAD R20, R27, R27, RZ ?trans1;
ULEA UR4, UR6, UR4, 0x18 &req={5} ?trans1;
ULEA UR5, UR6, UR5, 0x18 ?trans1;
LEA R23, R23, R0, 0x4 &req={2} ?WAIT4_END_GROUP;
LEA R19, R0, UR4, 0x6 ?trans1;
UMOV UR4, URZ ?trans1;
LEA R17, R10.reuse, UR5, 0x2 &req={0} ?trans1;
IMAD R21, R23, R27, R10 ?trans1;
LEA R18, R10, R19, 0x2 ?trans2;
LEA R22, R8, R10, 0x4 ?trans2;
LEA R16, R0, R17, 0x6 ?trans1;
@!P0 BRA 0x910 &req={4} ?trans6;
LDC R4, c[0x0][0x398] &wr=0x0 ?trans1;
IADD3 R6, PT, PT, R0.reuse, 0x10, RZ ?trans1;
IMAD R3, R0, R27.reuse, R10.reuse ?trans1;
LOP3.LUT R5, R2, 0xfffffffe, RZ, 0xc0, !PT ?trans1;
UMOV UR4, 0x10 ?trans1;
MOV R31, RZ ?trans1;
IMAD R7, R6, R27, R10 ?trans1;
LEA R6, R8, R3, 0x4 ?trans1;
LDC.64 R24, c[0x0][0x380] &wr=0x1 ?trans1;
MOV R3, R21 ?trans1;
IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT2_END_GROUP;
LEA R7, R8, R7, 0x4 ?WAIT7_END_GROUP;
ISETP.GE.AND P1, PT, R6, R20.reuse, PT ?trans1;
ISETP.GE.AND P0, PT, R3.reuse, R20, PT ?trans1;
MOV R35, RZ ?trans1;
HFMA2 R37, -RZ, RZ, 0, 0 ?trans2;
IMAD.WIDE R26, R3, 0x4, R24 &req={1} ?WAIT8_END_GROUP;
@!P1 LDC.64 R8, c[0x0][0x388] &wr=0x1 ?trans1;
@!P0 LDG.E R35, desc[UR8][R26.64] &wr=0x2 ?trans1;
@!P1 IMAD.WIDE R28, R6, 0x4, R8 &req={1} ?WAIT5_END_GROUP;
@!P1 LDG.E R37, desc[UR8][R28.64] &wr=0x3 ?trans1;
ISETP.GE.AND P1, PT, R7, R20, PT ?WAIT3_END_GROUP;
STS [R18], R35 &req={2} ?trans4;
STS [R16], R37 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R32, [R17] ?trans4;
LDS.128 R12, [R19] &wr=0x1 ?trans4;
LDS R34, [R17+0x40] &wr=0x2 ?trans4;
LDS R36, [R17+0x80] &wr=0x3 ?trans4;
LDS R30, [R17+0xc0] &wr=0x4 ?trans4;
LDS R33, [R17+0x100] ?trans4;
LDS.128 R8, [R19+0x10] &wr=0x5 ?trans4;
LDS R28, [R17+0x140] &wr=0x0 ?trans4;
LDS R29, [R17+0x180] &wr=0x0 ?trans1;
FFMA R12, R12, R32, R31 &req={1} ?WAIT3_END_GROUP;
LDS R32, [R17+0x1c0] &wr=0x1 ?trans1;
FFMA R13, R34, R13, R12 &req={2} ?WAIT3_END_GROUP;
LDS R31, [R17+0x200] ?trans1;
FFMA R13, R36, R14, R13 &req={3} ?WAIT3_END_GROUP;
LDS R34, [R17+0x2c0] ?trans1;
FFMA R35, R30, R15, R13 &req={4} ?WAIT3_END_GROUP;
LDS.128 R12, [R19+0x20] &wr=0x2 ?trans4;
LDS R30, [R17+0x240] &wr=0x3 ?trans1;
FFMA R33, R8, R33, R35 &req={5} ?WAIT3_END_GROUP;
LDS R35, [R17+0x280] &wr=0x4 ?trans1;
FFMA R28, R28, R9, R33 &req={0} ?trans1;
IADD3 R9, PT, PT, R3, 0x10, RZ ?trans2;
LDS R33, [R17+0x380] ?trans1;
FFMA R29, R29, R10, R28 ?WAIT4_END_GROUP;
FFMA R11, R32, R11, R29 &req={1} ?trans1;
ISETP.GE.AND P0, PT, R9, R20, PT ?trans1;
LDS R32, [R17+0x3c0] ?trans2;
FFMA R11, R12, R31, R11 &req={2} ?trans2;
LDS R31, [R17+0x300] ?trans2;
FFMA R36, R30, R13, R11 &req={3} ?trans2;
@!P1 LDC.64 R12, c[0x0][0x388] &wr=0x0 ?trans1;
LDS R30, [R17+0x340] ?trans4;
LDS.128 R8, [R19+0x30] &wr=0x1 ?trans1;
HFMA2 R37, -RZ, RZ, 0, 0 ?WAIT2_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
@!P1 IMAD.WIDE R28, R7, 0x4, R12 &req={0} ?trans1;
MOV R13, RZ ?WAIT4_END_GROUP;
@!P0 LDG.E R37, desc[UR8][R26.64+0x40] &wr=0x2 ?trans4;
@!P1 LDG.E R13, desc[UR8][R28.64] &wr=0x3 ?trans1;
FFMA R35, R35, R14, R36 &req={4} ?WAIT4_END_GROUP;
FFMA R34, R34, R15, R35 ?WAIT4_END_GROUP;
FFMA R31, R8, R31, R34 &req={1} ?WAIT4_END_GROUP;
FFMA R30, R30, R9, R31 ?WAIT4_END_GROUP;
FFMA R33, R33, R10, R30 ?WAIT4_END_GROUP;
FFMA R33, R32, R11, R33 ?trans1;
IADD3 R5, PT, PT, R5, 0x2, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R5, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x20, URZ ?trans1;
IADD3 R3, PT, PT, R3, 0x20, RZ ?trans1;
STS [R18], R37 &req={2} ?trans4;
STS [R16], R13 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R35, [R17] ?trans4;
LDS.128 R12, [R19] &wr=0x0 ?trans4;
LDS R26, [R17+0x40] &wr=0x1 ?trans4;
LDS R31, [R17+0x80] &wr=0x2 ?trans4;
LDS R34, [R17+0xc0] &wr=0x3 ?trans4;
LDS R29, [R17+0x100] ?trans4;
LDS.128 R8, [R19+0x10] &wr=0x4 ?trans4;
LDS R28, [R17+0x140] &wr=0x5 ?trans4;
LDS R27, [R17+0x180] &wr=0x5 ?trans4;
LDS R30, [R17+0x1c0] &wr=0x5 ?trans4;
LDS R32, [R17+0x340] ?trans1;
FFMA R35, R12, R35, R33 &req={0} ?WAIT4_END_GROUP;
FFMA R26, R26, R13, R35 &req={1} ?WAIT4_END_GROUP;
FFMA R31, R31, R14, R26 &req={2} ?trans2;
LDS R26, [R17+0x240] ?trans2;
FFMA R33, R34, R15, R31 &req={3} ?trans2;
LDS R31, [R17+0x200] ?trans4;
LDS.128 R12, [R19+0x20] &wr=0x0 ?trans1;
FFMA R29, R8, R29, R33 &req={4} ?WAIT3_END_GROUP;
LDS R33, [R17+0x300] ?trans1;
FFMA R28, R28, R9, R29 &req={5} ?WAIT3_END_GROUP;
LDS R29, [R17+0x280] &wr=0x1 ?trans1;
FFMA R27, R27, R10, R28 ?WAIT3_END_GROUP;
LDS R28, [R17+0x2c0] &wr=0x2 ?trans1;
FFMA R35, R30, R11, R27 ?WAIT3_END_GROUP;
LDS.128 R8, [R19+0x30] &wr=0x3 ?trans4;
LDS R27, [R17+0x380] &wr=0x4 ?trans4;
LDS R30, [R17+0x3c0] &wr=0x5 ?trans1;
FFMA R31, R12, R31, R35 &req={0} ?WAIT4_END_GROUP;
FFMA R26, R26, R13, R31 ?WAIT4_END_GROUP;
FFMA R29, R29, R14, R26 &req={1} ?WAIT4_END_GROUP;
FFMA R15, R28, R15, R29 &req={2} ?WAIT4_END_GROUP;
FFMA R15, R8, R33, R15 &req={3} ?WAIT4_END_GROUP;
FFMA R32, R32, R9, R15 ?WAIT4_END_GROUP;
FFMA R31, R27, R10, R32 &req={4} ?trans1;
MOV R27, R4 ?WAIT3_END_GROUP;
FFMA R31, R30, R11, R31 &req={5} ?trans2;
LEA R6, R27.reuse, R6, 0x5 ?trans2;
LEA R7, R27, R7, 0x5 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 BRA 0x260 ?trans5;
UIADD3 UR4, UPT, UPT, UR4, -0x10, URZ ?WAIT12_END_GROUP;
LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ?trans1;
VIMNMX.S32 R4, R23, R22, !PT ?WAIT4_END_GROUP;
ISETP.NE.U32.AND P1, PT, R2, 0x1, PT ?trans1;
ISETP.GE.AND P0, PT, R4, R27, PT ?WAIT12_END_GROUP;
@P1 BRA 0xcb0 ?trans5;
IADD3 R0, PT, PT, R0, UR4, RZ ?trans2;
IADD3 R21, PT, PT, R21, UR4, RZ ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?trans1;
MOV R25, RZ ?trans1;
IMAD R3, R0, R27, R22 ?trans2;
ISETP.GE.AND P1, PT, R21, R20, PT ?WAIT3_END_GROUP;
ISETP.GE.AND P2, PT, R3, R20, PT ?WAIT10_END_GROUP;
@!P1 LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
@!P2 LDC.64 R12, c[0x0][0x388] &wr=0x1 ?trans1;
@!P1 IMAD.WIDE R8, R21, 0x4, R8 &req={0} ?WAIT5_END_GROUP;
@!P1 LDG.E R15, desc[UR8][R8.64] &wr=0x2 ?trans1;
@!P2 IMAD.WIDE R12, R3, 0x4, R12 &req={1} ?WAIT5_END_GROUP;
@!P2 LDG.E R25, desc[UR8][R12.64] &wr=0x3 ?trans4;
STS [R18], R15 &req={2} ?trans4;
STS [R16], R25 &req={3} ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R24, [R17] ?trans4;
LDS.128 R4, [R19] &wr=0x0 ?trans4;
LDS R29, [R17+0x40] &wr=0x1 ?trans4;
LDS R26, [R17+0x80] &wr=0x2 ?trans4;
LDS R20, [R17+0xc0] &wr=0x3 ?trans4;
LDS R3, [R17+0x100] ?trans4;
LDS.128 R8, [R19+0x10] &wr=0x4 ?trans4;
LDS R0, [R17+0x140] &wr=0x5 ?trans4;
LDS R21, [R17+0x180] &wr=0x5 ?trans4;
LDS R2, [R17+0x1c0] &wr=0x5 ?trans4;
LDS R25, [R17+0x200] ?trans4;
LDS.128 R12, [R19+0x20] &wr=0x5 ?trans1;
FFMA R4, R4, R24, R31 &req={0} ?WAIT3_END_GROUP;
LDS R16, [R17+0x240] &wr=0x0 ?trans1;
FFMA R5, R29, R5, R4 &req={1} ?WAIT3_END_GROUP;
LDS R33, [R17+0x280] &wr=0x1 ?trans1;
FFMA R35, R26, R6, R5 &req={2} ?WAIT3_END_GROUP;
LDS R4, [R17+0x2c0] &wr=0x2 ?trans1;
FFMA R7, R20, R7, R35 &req={3} ?WAIT3_END_GROUP;
LDS R5, [R17+0x300] ?trans4;
LDS.128 R28, [R19+0x30] &wr=0x3 ?trans1;
FFMA R3, R8, R3, R7 &req={4} ?WAIT3_END_GROUP;
LDS R6, [R17+0x340] &wr=0x4 ?trans1;
FFMA R0, R0, R9, R3 &req={5} ?WAIT3_END_GROUP;
LDS R8, [R17+0x380] &wr=0x5 ?trans4;
LDS R3, [R17+0x3c0] &wr=0x5 ?trans1;
FFMA R21, R21, R10, R0 ?WAIT4_END_GROUP;
FFMA R11, R2, R11, R21 ?WAIT4_END_GROUP;
FFMA R11, R12, R25, R11 ?WAIT4_END_GROUP;
FFMA R16, R16, R13, R11 &req={0} ?WAIT4_END_GROUP;
FFMA R33, R33, R14, R16 &req={1} ?WAIT4_END_GROUP;
FFMA R15, R4, R15, R33 &req={2} ?WAIT4_END_GROUP;
FFMA R5, R28, R5, R15 &req={3} ?WAIT4_END_GROUP;
FFMA R5, R6, R29, R5 &req={4} ?WAIT4_END_GROUP;
FFMA R8, R8, R30, R5 &req={5} ?WAIT4_END_GROUP;
FFMA R31, R3, R31, R8 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@P0 EXIT ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
IMAD R23, R23, R27, R22 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R23, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR8][R2.64], R31 ?trans1;
EXIT ?trans5;
BRA 0xd10;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpu_matrix_multiply(float*, float*, float*, int)
_Z19gpu_matrix_multiplyPfS_S_i:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_bfe_u32 v6, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_9
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b32_e32 v7, 6, v6
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_mul_i32 s9, s2, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 0x400, v5
v_add_nc_u32_e32 v9, v7, v5
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB0_2:
s_lshl_b32 s10, s8, 4
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v2, s10, v1
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v11, v[2:3], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v12, s10, v6
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
v_mad_u64_u32 v[2:3], null, v12, s2, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s9, v2
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v2, v8
s_mov_b32 s10, 0
s_waitcnt vmcnt(0)
ds_store_b32 v10, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_7:
v_add_nc_u32_e32 v3, s10, v7
s_add_i32 s10, s10, 4
ds_load_b32 v11, v2
ds_load_b32 v3, v3
v_add_nc_u32_e32 v2, 64, v2
s_cmp_eq_u32 s10, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v3, v11
s_cbranch_scc0 .LBB0_7
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_10
.LBB0_9:
v_mov_b32_e32 v5, 0
.LBB0_10:
v_max_i32_e32 v1, v4, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpu_matrix_multiply | 5,113 | 1,692 | stackv2-00000-of-00015 |
// Demangled: conv8(int*, int*)
Function : _Z5conv8PiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans2;
LDG.E R3, desc[UR4][R2.64] &req={0} &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: conv8(int*, int*)
_Z5conv8PiS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| conv8 | 260 | 146 | stackv2-00000-of-00015 |
// Demangled: vecMatrixTransposed(int*, int*)
Function : _Z19vecMatrixTransposedPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
S2R R4, SR_TID.Y &wr=0x2 ?trans6;
S2UR UR5, SR_CTAID.X &wr=0x0 ?trans8;
S2UR UR8, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R7, c[0x0][0x364] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x370] &wr=0x3 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R0, R0, UR5, R5 &req={0} ?trans1;
USHF.L.U32 UR4, UR4, 0x3, URZ &req={3} ?trans1;
IMAD R7, R7, UR8, R4 &req={2} ?WAIT5_END_GROUP;
IMAD R5, R7, UR4, R0 ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={4} ?trans2;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans4;
LDG.E R3, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD R7, R0, UR4, R7 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x150;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecMatrixTransposed(int*, int*)
_Z19vecMatrixTransposedPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_lshl_b32 s4, s4, 3
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s3, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecMatrixTransposed | 569 | 700 | stackv2-00000-of-00015 |
// Demangled: updateHeat(double*, double*, int, int)
Function : _Z10updateHeatPdS_ii
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R3, SR_TID.X &wr=0x1 ?trans7;
S2UR UR5, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR7, c[0x0][0x390] &wr=0x2 ?trans1;
S2R R5, SR_TID.Y &wr=0x3 ?trans6;
LDC R2, c[0x0][0x360] &wr=0x1 ?trans8;
S2UR UR6, SR_CTAID.Y &wr=0x3 ?trans1;
UIADD3 UR4, UPT, UPT, UR7, -0x1, URZ &req={2} ?WAIT7_END_GROUP;
LDC R0, c[0x0][0x364] &wr=0x3 ?trans1;
IMAD R2, R2, UR5, R3 &req={1} ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R2, UR4, PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R2, RZ, P0 ?trans1;
IMAD R3, R0, UR6, R5 &req={3} ?WAIT4_END_GROUP;
IMAD R0, R2, UR7, R3 ?trans1;
ISETP.NE.AND P1, PT, R3.reuse, UR4, PT ?trans1;
ISETP.NE.AND P0, PT, R3, RZ, P0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?WAIT12_END_GROUP;
@P0 BRA P1, 0x190 &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD.WIDE R2, R0, 0x8, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E.64 R2, desc[UR4][R2.64] &req={1} &wr=0x3 ?trans1;
IMAD.WIDE R4, R0, 0x8, R4 &req={2} ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R4.64], R2 &req={3} ?trans1;
EXIT ?trans5;
VIMNMX.S32 R2, R2, R3, !PT ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R2, UR7, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={1} ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU UR6, c[0x0][0x394] &wr=0x1 ?trans1;
IMAD.WIDE R4, R0, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
LDG.E.64 R6, desc[UR4][R4.64] &rd=0x0 &wr=0x5 ?trans1;
MUFU.RCP64H R3, 0.0099999979138374328613 &wr=0x2 ?trans1;
MOV.64 R12, 0x3f847ae147ae147c ?trans2;
HFMA2 R2, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans1;
UMOV.64 UR8, 0x3f28e757928e0c9e ?trans1;
I2F.F64 R8, UR6 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R2, -R12, 1 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R10, R10, R10 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R10, R2, R10, R2 &req={2} &wr=0x2 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, -R12, 1 &req={2} ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R8, R8, UR8 &req={1} &wr=0x1 ?trans2;
FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT &req={1} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R10, R2, R10 &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R10, R8, R2 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R12, R10, -R12, R8 &req={1} &wr=0x1 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R2, R12, R10 &req={1} &wr=0x1 ?trans2;
FFMA R10, RZ, 1.0349999666213989258, R3 &req={1} ?WAIT5_END_GROUP;
FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ?WAIT13_END_GROUP;
@P0 BRA P1, 0x580 &req={0} ?trans5;
MOV R10, 0x580 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0x790 &req={5} ?trans5;
LDC R15, c[0x0][0x390] &wr=0x0 ?trans1;
LDG.E.64 R10, desc[UR4][R4.64+0x8] &wr=0x2 ?trans7;
LDC.64 R12, c[0x0][0x380] &wr=0x1 ?trans1;
IADD3 R9, PT, PT, R0, -R15, RZ &req={0} ?trans1;
IMAD.WIDE R14, R15, 0x8, R4 ?WAIT6_END_GROUP;
LDG.E.64 R14, desc[UR4][R14.64] &wr=0x3 ?trans1;
IMAD.WIDE R12, R9, 0x8, R12 &req={1} ?WAIT3_END_GROUP;
LDG.E.64 R8, desc[UR4][R4.64+-0x8] &wr=0x2 ?trans4;
LDG.E.64 R12, desc[UR4][R12.64] &wr=0x4 ?trans1;
DADD R8, R8, R10 &req={2} &rd=0x0 &wr=0x4 ?trans2;
LDC.64 R10, c[0x0][0x388] &req={0} &wr=0x0 ?trans2;
IMAD.WIDE R10, R0, 0x8, R10 &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R12 &req={4} &wr=0x3 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DADD R8, R8, R14 &req={3} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R6, -4, R8 &req={5,0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R8, R8, R2, R6 &req={0} &wr=0x0 ?trans2;
STG.E.64 desc[UR4][R10.64], R8 &req={0} ?trans1;
EXIT ?trans5;
MOV.64 R2, 0x3ff47ae147ae147c ?trans2;
HFMA2 R12, -RZ, RZ, 0, 5.9604644775390625e-08 ?trans2;
HFMA2 R21, -RZ, RZ, 0.0045166015625, 0 ?trans1;
MUFU.RCP64H R13, R3 &wr=0x0 ?trans1;
HFMA2 R23, -RZ, RZ, 1.875, 0 ?WAIT5_END_GROUP;
IADD3 R24, PT, PT, R23, -0x1, RZ ?trans1;
DFMA R14, R12, -R2, 1 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R14, R14, R14 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R12, R14, R12 &req={0} &rd=0x0 ?trans2;
MOV R13, R9 &req={0} ?trans1;
MOV R12, R8 ?WAIT4_END_GROUP;
LOP3.LUT R11, R13.reuse, 0x7ff00000, RZ, 0xc0, !PT ?trans1;
FSETP.GEU.AND P1, PT, |R13|, 1.469367938527859385e-39, PT ?trans1;
MOV R8, R12 ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R11, 0x3f800000, PT ?trans1;
MOV R20, R11 ?WAIT4_END_GROUP;
SEL R21, R21, 0x63400000, !P0 ?WAIT5_END_GROUP;
@!P1 LOP3.LUT R14, R21.reuse, 0x80000000, R13.reuse, 0xf8, !PT ?trans2;
LOP3.LUT R9, R21, 0x800fffff, R13, 0xf8, !PT ?trans2;
@!P1 LOP3.LUT R15, R14, 0x100000, RZ, 0xfc, !PT ?trans1;
@!P1 MOV R14, RZ ?WAIT15_END_GROUP;
NOP ?WAIT7_END_GROUP;
NOP ?WAIT15_END_GROUP;
@!P1 DFMA R8, R8, 2, -R14 &wr=0x0 ?trans2;
@!P1 LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT &req={0} ?WAIT4_END_GROUP;
IADD3 R22, PT, PT, R20, -0x1, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ?WAIT5_END_GROUP;
ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ?WAIT15_END_GROUP;
NOP ?WAIT3_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, -R2, 1 &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R18, R16, R18, R16 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DMUL R14, R18, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R16, R14, -R2, R8 &req={0} &wr=0x0 ?WAIT15_END_GROUP;
NOP ?WAIT4_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R14, R18, R16, R14 &req={0} &rd=0x0 &wr=0x1 ?trans2;
@P0 BRA 0xd40 &req={1,0} ?trans5;
IADD3 R11, PT, PT, R11, -0x3f800000, RZ ?WAIT5_END_GROUP;
VIMNMX.S32 R11, R11, -0x46a00000, !PT ?WAIT5_END_GROUP;
VIMNMX.S32 R12, R11, 0x46a00000, PT ?WAIT5_END_GROUP;
IADD3 R21, PT, PT, -R21, R12, RZ ?trans1;
MOV R12, RZ ?WAIT3_END_GROUP;
IADD3 R13, PT, PT, R21, 0x7fe00000, RZ ?WAIT6_END_GROUP;
DMUL R16, R14, R12 &wr=0x0 ?trans2;
FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT &req={0} ?WAIT13_END_GROUP;
@P0 BRA 0xe40 ?trans5;
DFMA R2, R14, -R2, R8 &wr=0x0 ?trans1;
MOV R12, RZ ?trans1;
FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT &req={0} ?trans1;
LOP3.LUT R2, R3, 0x3f847ae1, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
LOP3.LUT R9, R2, 0x80000000, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
LOP3.LUT R13, R9, R13, RZ, 0xfc, !PT ?WAIT4_END_GROUP;
@!P0 BRA 0xe40 ?trans5;
IADD3 R3, PT, PT, -R21.reuse, RZ, RZ ?trans1;
MOV R2, RZ ?trans1;
IADD3 R21, PT, PT, -R21, -0x43300000, RZ ?trans1;
DMUL.RP R12, R14, R12 &wr=0x0 ?trans2;
LOP3.LUT R9, R13, R9, RZ, 0x3c, !PT &req={0} ?WAIT15_END_GROUP;
NOP ?trans2;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
DFMA R2, R16, -R2, R14 &wr=0x0 ?trans2;
FSETP.NEU.AND P0, PT, |R3|, R21, PT &req={0} ?WAIT5_END_GROUP;
FSEL R16, R12, R16, !P0 ?trans1;
FSEL R17, R9, R17, !P0 ?trans1;
BRA 0xe40 ?trans6;
DSETP.NAN.AND P0, PT, R12, R12, PT &wr=0x0 ?trans2;
@P0 BRA 0xe20 &req={0} ?trans5;
ISETP.NE.AND P0, PT, R20, R23, PT ?trans1;
MOV.64 R16, 0xfff8000000000000 ?WAIT12_END_GROUP;
@!P0 BRA 0xe40 ?trans5;
ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ?trans1;
LOP3.LUT R12, R13, 0x3f847ae1, RZ, 0x3c, !PT ?WAIT4_END_GROUP;
ISETP.EQ.OR P0, PT, R23, RZ, !P0 ?trans1;
LOP3.LUT R17, R12, 0x80000000, RZ, 0xc0, !PT ?WAIT12_END_GROUP;
@P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ?trans1;
@!P0 MOV R16, RZ ?trans1;
@P0 MOV R16, RZ ?WAIT3_END_GROUP;
@P0 MOV R17, R2 ?trans1;
BRA 0xe40 ?trans6;
LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ?trans1;
MOV R16, R12 ?WAIT7_END_GROUP;
MOV R11, 0x0 ?trans1;
MOV R2, R16 ?trans1;
MOV R3, R17 ?trans2;
RET.REL.NODEC R10 0x0 ?trans5;
BRA 0xe80;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: updateHeat(double*, double*, int, int)
_Z10updateHeatPdS_ii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s8, 0xffff
s_lshr_b32 s0, s8, 16
v_mad_u64_u32 v[4:5], null, s14, s1, v[1:2]
v_mad_u64_u32 v[5:6], null, s15, s0, v[0:1]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s8, 0, v4
v_mad_u64_u32 v[0:1], null, v4, s2, v[5:6]
v_cmpx_ne_u32_e32 0, v4
s_cbranch_execz .LBB0_6
s_add_i32 s1, s2, -1
v_cmp_ne_u32_e64 s0, 0, v5
v_cmp_ne_u32_e32 vcc_lo, s1, v4
v_cmp_ne_u32_e64 s1, s1, v5
s_mov_b32 s11, -1
s_mov_b32 s10, 0
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_5
v_max_i32_e32 v1, v4, v5
s_mov_b32 s1, 0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v1, 31, v0
v_cvt_f64_i32_e32 v[10:11], s3
v_subrev_nc_u32_e32 v12, s2, v0
s_mov_b32 s12, 0x928e0c9e
s_mov_b32 s13, 0x3f28e757
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v13, 31, v12
s_lshl_b64 s[2:3], s[2:3], 3
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_lshlrev_b64 v[12:13], 3, v[12:13]
s_clause 0x1
global_load_b64 v[8:9], v[6:7], off offset:8
global_load_b128 v[2:5], v[6:7], off offset:-8
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b64 v[12:13], v[12:13], off
s_mov_b32 s2, 0x47ae147c
s_mov_b32 s3, 0x3f847ae1
global_load_b64 v[6:7], v[6:7], off
v_mul_f64 v[10:11], v[10:11], s[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[14:15], null, s[2:3], s[2:3], v[10:11]
v_rcp_f64_e32 v[16:17], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
v_div_scale_f64 v[18:19], vcc_lo, v[10:11], s[2:3], v[10:11]
v_mul_f64 v[20:21], v[18:19], v[16:17]
s_waitcnt vmcnt(2)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], -v[14:15], v[20:21], v[18:19]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[8:9], v[8:9], v[16:17], v[20:21]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[6:7], v[8:9], s[2:3], v[10:11]
v_fma_f64 v[2:3], v[4:5], -4.0, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s10, s1, exec_lo
s_xor_b32 s11, exec_lo, -1
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s1, s8, exec_lo
s_and_b32 s2, s11, exec_lo
s_and_b32 s0, s10, exec_lo
s_or_b32 s8, s1, s2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_and_saveexec_b32 s1, s8
s_cbranch_execz .LBB0_8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 s0, s0, exec_lo
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_10
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| updateHeat | 4,877 | 2,558 | stackv2-00000-of-00015 |
// Demangled: add_matrix(float*, float*, float*, int)
Function : _Z10add_matrixPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x398] &wr=0x1 ?trans2;
ISETP.GE.AND P0, PT, R4, 0x1, PT &req={1} ?WAIT13_END_GROUP;
@!P0 EXIT &req={0} ?trans5;
IADD3 R2, PT, PT, R4.reuse, -0x1, RZ ?trans2;
LOP3.LUT R6, R4.reuse, 0x7ffffff0, RZ, 0xc0, !PT ?trans1;
HFMA2 R5, -RZ, RZ, 0, 0 ?trans1;
LOP3.LUT R0, R4, 0xf, RZ, 0xc0, !PT ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x0 ?trans1;
ISETP.GE.U32.AND P0, PT, R2, 0xf, PT ?trans1;
LOP3.LUT R2, R4.reuse, 0x7, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R3, R4.reuse, 0x3, RZ, 0xc0, !PT ?trans2;
SHF.L.U32 R4, R4, 0x4, RZ ?WAIT2_END_GROUP;
IADD3 R6, PT, PT, -R6, RZ, RZ ?WAIT7_END_GROUP;
UMOV UR4, URZ ?trans1;
ISETP.NE.AND P2, PT, R0, RZ, PT ?trans1;
@!P0 BRA 0xab0 &req={4,3,2,1,0} ?WAIT12_END_GROUP;
LDC R16, c[0x0][0x398] &wr=0x1 ?trans1;
MOV R34, R6 ?trans1;
IMAD.WIDE.U32 R22, R5.reuse, 0x4, RZ ?trans1;
UMOV UR4, URZ ?trans1;
IADD3 R18, PT, PT, R5.reuse, R16.reuse, RZ &req={1} ?trans2;
IADD3 R7, PT, PT, R5, R16, R16 ?trans1;
IMAD R9, R16.reuse, 0x3, R5.reuse ?trans1;
LEA R11, R16.reuse, R5.reuse, 0x2 ?trans1;
IMAD R13, R16.reuse, 0x5, R5.reuse ?trans1;
LEA R19, R16.reuse, R5, 0x3 ?trans1;
IMAD R15, R16, 0x6, R5 ?WAIT2_END_GROUP;
IMAD R17, R16.reuse, 0x7, R5.reuse ?trans2;
IMAD R35, R16.reuse, 0x9, R5.reuse ?trans2;
IMAD R37, R16.reuse, 0xa, R5.reuse ?trans2;
IMAD R8, R16.reuse, 0xb, R5.reuse ?trans2;
IMAD R10, R16.reuse, 0xc, R5.reuse ?trans2;
IMAD R12, R16, 0xd, R5 ?WAIT2_END_GROUP;
IMAD R14, R16.reuse, 0xe, R5.reuse ?trans2;
IMAD R16, R16, 0xf, R5 ?WAIT7_END_GROUP;
LDC.64 R24, c[0x0][0x388] &req={1} &wr=0x1 ?trans8;
LDC.64 R26, c[0x0][0x380] &wr=0x2 ?trans1;
IADD.64 R28, R22, R24 &req={1} ?WAIT7_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &req={0} &wr=0x3 ?trans1;
IADD.64 R20, R22, R26 &req={2} ?WAIT6_END_GROUP;
LDG.E R30, desc[UR6][R20.64] &rd=0x0 &wr=0x3 ?trans2;
LDC.64 R20, c[0x0][0x390] &req={0} &wr=0x0 ?trans2;
IADD.64 R32, R22, R20 &req={0} ?trans2;
FADD R36, R30, R29 &req={3} ?trans1;
IMAD.WIDE.U32 R30, R18, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R18, 0x4, R26 &req={0} ?WAIT5_END_GROUP;
LDG.E R28, desc[UR6][R32.64] &wr=0x2 ?trans2;
FADD R36, R28, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R18, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R28, R7.reuse, 0x4, R26 ?trans1;
STG.E desc[UR6][R30.64], R36 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R28.64] &req={0} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R7, 0x4, R24 &req={0} ?WAIT6_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R7, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R30, R29 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R9, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R9, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R11, 0x4, R26 ?WAIT4_END_GROUP;
FADD R36, R32, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R9, 0x4, R20 ?WAIT5_END_GROUP;
STG.E desc[UR6][R30.64], R36 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R28.64] &req={0} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R11, 0x4, R24 &req={0} ?WAIT6_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R11, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R30, R29 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R13, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R13, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R15, 0x4, R26 ?WAIT4_END_GROUP;
FADD R36, R32, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R13, 0x4, R20 ?WAIT5_END_GROUP;
STG.E desc[UR6][R30.64], R36 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R28.64] &req={0} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R15, 0x4, R24 &req={0} ?WAIT6_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R15, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R30, R29 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R17, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R17, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R19, 0x4, R26 ?WAIT4_END_GROUP;
FADD R36, R32, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R17, 0x4, R20 ?WAIT5_END_GROUP;
STG.E desc[UR6][R30.64], R36 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R28.64] &req={0} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R19, 0x4, R24 &req={0} ?WAIT6_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R19, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R30, R29 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R35, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R35, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R37, 0x4, R26 ?WAIT4_END_GROUP;
FADD R36, R32, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R35, 0x4, R20 ?WAIT5_END_GROUP;
STG.E desc[UR6][R30.64], R36 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R28.64] &req={0} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R37, 0x4, R24 &req={0} ?WAIT6_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R37, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R30, R29 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R8, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R8, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R10, 0x4, R26 ?WAIT4_END_GROUP;
FADD R36, R32, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R8, 0x4, R20 ?WAIT5_END_GROUP;
STG.E desc[UR6][R30.64], R36 &rd=0x0 ?trans4;
LDG.E R30, desc[UR6][R28.64] &req={0} &rd=0x0 &wr=0x2 ?trans2;
IMAD.WIDE.U32 R28, R10, 0x4, R24 &req={0} ?WAIT6_END_GROUP;
LDG.E R29, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R10, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R30, R29 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R12, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R12, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R32, desc[UR6][R32.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R12, 0x4, R20 ?WAIT4_END_GROUP;
FADD R36, R32, R31 &req={2} ?trans1;
IMAD.WIDE.U32 R30, R14, 0x4, R24 ?WAIT4_END_GROUP;
STG.E desc[UR6][R28.64], R36 &rd=0x0 ?trans4;
LDG.E R31, desc[UR6][R30.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R28, R14, 0x4, R26 &req={0} ?WAIT6_END_GROUP;
LDG.E R28, desc[UR6][R28.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R32, R14, 0x4, R20 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R16, 0x4, R26 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R16, 0x4, R24 ?WAIT4_END_GROUP;
FADD R36, R28, R31 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R32.64], R36 &rd=0x1 ?trans4;
LDG.E R26, desc[UR6][R26.64] &wr=0x2 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x2 ?trans1;
IADD3 R34, PT, PT, R34, 0x10, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R34, RZ, PT ?trans1;
IMAD.WIDE.U32 R20, R16, 0x4, R20 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x10, URZ ?trans1;
IADD3 R18, PT, PT, R4.reuse, R18, RZ ?trans2;
IADD3 R7, PT, PT, R4.reuse, R7, RZ ?trans2;
IADD3 R9, PT, PT, R4.reuse, R9, RZ ?trans2;
IADD3 R11, PT, PT, R4.reuse, R11, RZ ?trans2;
IADD3 R13, PT, PT, R4, R13, RZ ?WAIT2_END_GROUP;
IADD3 R15, PT, PT, R4.reuse, R15, RZ ?trans2;
IADD3 R17, PT, PT, R4.reuse, R17, RZ ?trans2;
IADD3 R19, PT, PT, R4.reuse, R19, RZ ?trans2;
IADD3 R35, PT, PT, R4.reuse, R35, RZ ?trans2;
IADD3 R37, PT, PT, R4.reuse, R37, RZ ?trans2;
IADD3 R8, PT, PT, R4, R8, RZ ?WAIT2_END_GROUP;
IADD3 R10, PT, PT, R4.reuse, R10, RZ ?trans2;
IADD3 R12, PT, PT, R4.reuse, R12, RZ ?trans2;
IADD3 R14, PT, PT, R4.reuse, R14, RZ ?trans2;
IADD3 R16, PT, PT, R4.reuse, R16, RZ ?trans1;
IMAD.WIDE.U32 R22, R4, 0x4, R22 ?WAIT4_END_GROUP;
FADD R29, R26, R25 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R20.64], R29 &rd=0x1 ?trans1;
@P1 BRA 0x240 ?trans5;
@!P2 BRA 0x1400 ?trans5;
IADD3 R7, PT, PT, R0, -0x1, RZ ?trans1;
ISETP.NE.AND P2, PT, R2, RZ, PT ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R7, 0x7, PT ?WAIT13_END_GROUP;
@!P1 BRA 0xf50 ?trans5;
LDC R14, c[0x0][0x398] &wr=0x2 ?trans8;
LDC.64 R10, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R21, R14, UR4, R5 &req={2,1} ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R16, R21, 0x4, R10 &req={3} ?WAIT6_END_GROUP;
LDG.E R16, desc[UR6][R16.64] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R18, R21, 0x4, R8 &req={4} ?WAIT6_END_GROUP;
LDG.E R19, desc[UR6][R18.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R21.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R20, R21, 0x4, R12 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R15, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R15, 0x4, R8 ?WAIT4_END_GROUP;
FADD R7, R16, R19 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R20.64], R7 &rd=0x0 ?trans4;
LDG.E R22, desc[UR6][R22.64] &wr=0x2 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x2 ?trans1;
IADD3 R29, PT, PT, R15.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R16, R15, 0x4, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R29, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R29, 0x4, R8 ?WAIT4_END_GROUP;
FADD R15, R22, R25 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R15 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R18.64] &wr=0x2 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x2 ?trans1;
IADD3 R31, PT, PT, R29.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R20, R29, 0x4, R12 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R31, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R31, 0x4, R8 ?WAIT4_END_GROUP;
FADD R7, R18, R27 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R20.64], R7 &rd=0x0 ?trans4;
LDG.E R22, desc[UR6][R22.64] &wr=0x2 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x2 ?trans1;
IADD3 R29, PT, PT, R31.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R16, R31, 0x4, R12 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R29, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R29, 0x4, R8 ?WAIT4_END_GROUP;
FADD R15, R22, R25 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R15 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R18.64] &wr=0x2 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x2 ?trans1;
IADD3 R31, PT, PT, R29.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R20, R29, 0x4, R12 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R31, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R31, 0x4, R8 ?WAIT4_END_GROUP;
FADD R7, R18, R27 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R20.64], R7 &rd=0x0 ?trans4;
LDG.E R22, desc[UR6][R22.64] &wr=0x2 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R31.reuse, R14, RZ &req={1} ?trans1;
IMAD.WIDE.U32 R16, R31, 0x4, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R15, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R15, 0x4, R8 ?WAIT4_END_GROUP;
FADD R29, R22, R25 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R29 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R18.64] &wr=0x2 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x2 ?trans1;
IADD3 R21, PT, PT, R15.reuse, R14, RZ &req={0} ?trans1;
IMAD.WIDE.U32 R14, R15, 0x4, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R10, R21, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R21, 0x4, R8 ?WAIT4_END_GROUP;
FADD R7, R18, R27 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R7 &rd=0x2 ?trans4;
LDG.E R10, desc[UR6][R10.64] &wr=0x1 ?trans4;
LDG.E R9, desc[UR6][R8.64] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R12, R21, 0x4, R12 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x8, URZ ?WAIT3_END_GROUP;
FADD R17, R10, R9 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R17 &rd=0x2 ?trans4;
@!P2 BRA 0x1400 ?trans5;
IADD3 R7, PT, PT, R2, -0x1, RZ &req={2} ?trans1;
ISETP.NE.AND P2, PT, R3, RZ, PT ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ?WAIT13_END_GROUP;
@!P1 BRA 0x11f0 ?trans5;
LDC R14, c[0x0][0x398] &wr=0x2 ?trans8;
LDC.64 R10, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R21, R14, UR4, R5 &req={2,1} ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R16, R21, 0x4, R10 &req={3} ?WAIT6_END_GROUP;
LDG.E R16, desc[UR6][R16.64] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R18, R21, 0x4, R8 &req={4} ?WAIT6_END_GROUP;
LDG.E R19, desc[UR6][R18.64] &wr=0x2 ?trans1;
IADD3 R15, PT, PT, R21.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R20, R21, 0x4, R12 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R15, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R24, R15, 0x4, R8 ?WAIT4_END_GROUP;
FADD R7, R16, R19 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R20.64], R7 &rd=0x0 ?trans4;
LDG.E R22, desc[UR6][R22.64] &wr=0x2 ?trans4;
LDG.E R25, desc[UR6][R24.64] &wr=0x2 ?trans1;
IADD3 R31, PT, PT, R15.reuse, R14, RZ ?trans1;
IMAD.WIDE.U32 R16, R15, 0x4, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R18, R31, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R26, R31, 0x4, R8 ?WAIT4_END_GROUP;
FADD R29, R22, R25 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R16.64], R29 &rd=0x1 ?trans4;
LDG.E R18, desc[UR6][R18.64] &wr=0x2 ?trans4;
LDG.E R27, desc[UR6][R26.64] &wr=0x2 ?trans1;
IADD3 R21, PT, PT, R31.reuse, R14, RZ &req={0} ?trans1;
IMAD.WIDE.U32 R14, R31, 0x4, R12 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R10, R21, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R21, 0x4, R8 ?WAIT4_END_GROUP;
FADD R7, R18, R27 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R14.64], R7 &rd=0x2 ?trans4;
LDG.E R10, desc[UR6][R10.64] &wr=0x1 ?trans4;
LDG.E R9, desc[UR6][R8.64] &wr=0x1 ?trans1;
IMAD.WIDE.U32 R12, R21, 0x4, R12 ?trans1;
UIADD3 UR4, UPT, UPT, UR4, 0x4, URZ ?WAIT3_END_GROUP;
FADD R17, R10, R9 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R17 &rd=0x2 ?trans4;
@!P2 BRA 0x1400 ?trans5;
LDC R20, c[0x0][0x398] &req={1} &wr=0x1 ?trans8;
LDC.64 R10, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R8, c[0x0][0x388] &wr=0x4 ?trans1;
IMAD R21, R20, UR4, R5 &req={1} ?WAIT7_END_GROUP;
LDC.64 R12, c[0x0][0x390] &req={2} &wr=0x1 ?trans1;
IMAD.WIDE.U32 R14, R21, 0x4, R10 &req={3} ?WAIT6_END_GROUP;
LDG.E R14, desc[UR6][R14.64] &req={0} &wr=0x2 ?trans1;
IMAD.WIDE.U32 R16, R21, 0x4, R8 &req={4} ?WAIT6_END_GROUP;
LDG.E R17, desc[UR6][R16.64] &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R3, 0x1, PT ?trans1;
IMAD.WIDE.U32 R18, R21, 0x4, R12 &req={1} ?WAIT4_END_GROUP;
FADD R7, R14, R17 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R7 &rd=0x3 ?trans3;
@!P1 BRA 0x1400 ?trans5;
IADD3 R21, PT, PT, R21, R20, RZ ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R14, R21, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, R21, 0x4, R8 ?trans2;
LDG.E R14, desc[UR6][R14.64] &wr=0x2 ?trans4;
LDG.E R17, desc[UR6][R16.64] &wr=0x2 ?trans1;
ISETP.NE.AND P1, PT, R3, 0x2, PT ?trans1;
IMAD.WIDE.U32 R18, R21, 0x4, R12 &req={3} ?WAIT4_END_GROUP;
FADD R7, R14, R17 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R18.64], R7 &rd=0x4 ?trans3;
@!P1 BRA 0x1400 ?trans5;
IADD3 R7, PT, PT, R21, R20, RZ &req={4} ?WAIT5_END_GROUP;
IMAD.WIDE.U32 R10, R7, 0x4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R8, R7.reuse, 0x4, R8 ?trans2;
LDG.E R10, desc[UR6][R10.64] &wr=0x2 ?trans4;
LDG.E R9, desc[UR6][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R12, R7, 0x4, R12 ?WAIT4_END_GROUP;
FADD R7, R10, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R12.64], R7 &rd=0x0 ?trans2;
LDCU UR4, c[0x0][0x398] &wr=0x5 ?trans1;
IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
ISETP.NE.AND P1, PT, R5, UR4, PT &req={5} ?WAIT13_END_GROUP;
@P1 BRA 0xe0 ?trans5;
EXIT &req={0} ?trans5;
BRA 0x1450;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_matrix(float*, float*, float*, int)
_Z10add_matrixPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_mov_b32 s9, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, s9
s_mov_b32 s10, s3
.LBB0_3:
s_lshl_b64 s[12:13], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s14, s4, s12
s_addc_u32 s15, s5, s13
s_add_u32 s16, s6, s12
s_addc_u32 s17, s7, s13
s_clause 0x1
global_load_b32 v1, v0, s[14:15]
global_load_b32 v2, v0, s[16:17]
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
s_add_i32 s10, s10, 1
s_add_i32 s2, s2, s8
s_cmp_eq_u32 s8, s10
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[12:13]
s_cbranch_scc0 .LBB0_3
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s8
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_matrix | 9,071 | 568 | stackv2-00000-of-00015 |
// Demangled: add_matrix_tid(float*, float*, float*, int)
Function : _Z14add_matrix_tidPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU UR8, c[0x0][0x398] &wr=0x1 ?trans1;
S2R R9, SR_TID.Y &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans5;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
S2UR UR7, SR_CTAID.Y &wr=0x2 ?trans8;
LDC R6, c[0x0][0x364] &wr=0x2 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x4 ?trans1;
IMAD R0, R0, UR6, R7 &req={0} ?WAIT7_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD R7, R6, UR7, R9 &req={2} ?WAIT4_END_GROUP;
IMAD R9, R7, UR8, R0 &req={1} ?WAIT3_END_GROUP;
LDC.64 R6, c[0x0][0x390] &wr=0x1 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={4} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={3} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={1} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x170;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add_matrix_tid(float*, float*, float*, int)
_Z14add_matrix_tidPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add_matrix_tid | 630 | 654 | stackv2-00000-of-00015 |
// Demangled: reduce_kernel(int const*, int*, unsigned int)
Function : _Z13reduce_kernelPKiPij
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR8, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R6, SR_TID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x390] &wr=0x2 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x3 ?trans1;
IMAD R5, R7, UR8, R6 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R5, UR4, PT &req={2} ?WAIT13_END_GROUP;
@!P1 LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans2;
@!P1 IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={1} ?WAIT6_END_GROUP;
@!P1 LDG.E R3, desc[UR6][R2.64] &req={3} &wr=0x2 ?trans1;
S2UR UR5, SR_CgaCtaId &wr=0x1 ?trans1;
MOV R4, UR8 ?trans1;
UMOV UR4, 0x400 ?trans1;
ISETP.NE.AND P0, PT, R6, RZ, PT ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P2, PT, R4, 0x2, PT ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={1} ?WAIT6_END_GROUP;
LEA R0, R6, UR4, 0x2 ?WAIT5_END_GROUP;
@!P1 STS [R0], R3 &req={2} &rd=0x1 ?trans4;
@P1 STS [R0], RZ &rd=0x1 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
@!P2 BRA 0x210 &req={0} ?trans5;
SHF.R.U32.HI R5, RZ, 0x1, R4 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R6, R5, PT ?WAIT13_END_GROUP;
@!P1 IMAD R2, R5, 0x4, R0 ?trans1;
@!P1 LDS R3, [R0] &req={1} ?trans5;
@!P1 LDS R2, [R2] &wr=0x0 ?trans2;
@!P1 IADD3 R3, PT, PT, R2, R3, RZ &req={0} ?WAIT5_END_GROUP;
@!P1 STS [R0], R3 &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P1, PT, R4, 0x3, PT ?trans1;
MOV R4, R5 ?WAIT12_END_GROUP;
@P1 BRA 0x160 &req={0} ?trans5;
@P0 EXIT ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={1} &wr=0x1 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?trans1;
IMAD.WIDE.U32 R2, R7, 0x4, R2 &req={1} ?WAIT8_END_GROUP;
LDS R5, [UR4] &wr=0x0 ?trans4;
STG.E desc[UR6][R2.64], R5 &req={0} ?trans1;
EXIT ?trans5;
BRA 0x2a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: reduce_kernel(int const*, int*, unsigned int)
_Z13reduce_kernelPKiPij:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s5, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
.LBB0_3:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_lshr_b32 s0, s5, 1
s_mov_b32 s1, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_6
v_lshl_add_u32 v2, s0, 2, v1
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s0
s_branch .LBB0_3
.LBB0_7:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[4:5], 2
s_add_u32 s0, s2, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s3, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| reduce_kernel | 1,054 | 917 | stackv2-00000-of-00015 |
// Demangled: HL_kernel(unsigned char*, unsigned int, unsigned int, unsigned char*)
Function : _Z9HL_kernelPhjjS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
LDCU.64 UR8, c[0x0][0x388] &wr=0x1 ?trans1;
S2R R5, SR_TID.X &wr=0x2 ?trans6;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
HFMA2 R2, -RZ, RZ, 0, 0 ?trans1;
UMOV UR7, URZ ?trans1;
BSSY.RECONVERGENT B0, 0x3d0 ?trans1;
UI2F.U32.RP UR4, UR8 &req={1} ?WAIT2_END_GROUP;
ISETP.NE.U32.AND P2, PT, RZ, UR8, PT ?trans1;
UIADD3 UR6, UPT, UPT, UR9, 0x2, URZ ?WAIT6_END_GROUP;
MUFU.RCP R0, UR4 &wr=0x1 ?trans2;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R0, 0xffffffe, RZ &req={1} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R3, R0 &wr=0x1 ?trans1;
IMAD R6, R6, UR4, R5 &req={2} ?trans1;
UMOV UR4, URZ ?trans1;
IADD3 R7, PT, PT, RZ, -R3, RZ &req={1} ?WAIT5_END_GROUP;
IMAD R7, R7, UR8, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R3, R3, R7, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R7, R3, R6, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R7, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R3, UR8, R6 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R0, UR8, PT ?WAIT13_END_GROUP;
@P0 IADD3 R0, PT, PT, R0, -UR8, RZ ?trans2;
@P0 IADD3 R7, PT, PT, R7, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, UR8, PT ?WAIT13_END_GROUP;
@P1 IADD3 R7, PT, PT, R7, 0x1, RZ ?trans2;
@!P2 LOP3.LUT R7, RZ, UR8, RZ, 0x33, !PT ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R7.reuse, 0x1, RZ ?trans2;
IADD3 R7, PT, PT, -R7, RZ, RZ ?trans2;
SHF.R.S32.HI R3, RZ, 0x1f, R2 ?WAIT3_END_GROUP;
IMAD R6, R7, UR8, R6 ?trans2;
IADD.64 R4, R2, UR6 ?WAIT4_END_GROUP;
IADD.64 R12, R4, -0x1 ?WAIT6_END_GROUP;
ISETP.NE.U32.AND P0, PT, R13, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x370 &req={0} ?trans5;
UI2F.U32.RP UR5, UR6 ?trans2;
IADD3 R9, PT, PT, RZ, -UR6, RZ ?trans1;
MOV R4, RZ ?trans1;
ISETP.NE.U32.AND P1, PT, RZ, UR6, PT ?WAIT5_END_GROUP;
MUFU.RCP R0, UR5 &wr=0x0 ?trans2;
IADD3 R0, PT, PT, R0, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R0 &wr=0x0 ?trans2;
IMAD R9, R9, R5, RZ &req={0} ?WAIT4_END_GROUP;
IMAD.HI.U32 R5, R5, R9, R4 ?trans1;
MOV R9, RZ ?WAIT5_END_GROUP;
IMAD.HI.U32 R5, R5, R12, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R8, R5, UR6, R12 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R8, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R8, PT, PT, R8, -UR6, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R8, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R8, PT, PT, R8, -UR6, RZ ?trans2;
@!P1 LOP3.LUT R8, RZ, UR6, RZ, 0x33, !PT ?trans1;
BRA 0x3c0 ?trans6;
MOV R10, UR6 ?trans1;
MOV R0, 0x3a0 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xc50 ?trans5;
MOV R8, R10 ?trans1;
MOV R9, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
MOV R12, R2 ?trans1;
MOV R13, R3 ?trans1;
BSSY.RECONVERGENT B0, 0x5c0 ?trans4;
IADD.64 R12, R12, 0x1 ?WAIT6_END_GROUP;
ISETP.NE.U32.AND P0, PT, R13, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x560 ?trans5;
UI2F.U32.RP UR5, UR6 ?trans2;
IADD3 R11, PT, PT, RZ, -UR6, RZ ?trans1;
HFMA2 R4, -RZ, RZ, 0, 0 ?trans1;
ISETP.NE.U32.AND P1, PT, RZ, UR6, PT ?WAIT5_END_GROUP;
MUFU.RCP R0, UR5 &wr=0x0 ?trans2;
IADD3 R10, PT, PT, R0, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R5, R10 &wr=0x0 ?trans2;
IMAD R11, R11, R5, RZ &req={0} ?WAIT4_END_GROUP;
IMAD.HI.U32 R11, R5, R11, R4 ?WAIT6_END_GROUP;
IMAD.HI.U32 R0, R11, R12, RZ ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, -R0, RZ, RZ ?WAIT5_END_GROUP;
IMAD R4, R5, UR6, R12 ?trans1;
MOV R5, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR6, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R4, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R4, PT, PT, R4, -UR6, RZ ?trans2;
@!P1 LOP3.LUT R4, RZ, UR6, RZ, 0x33, !PT ?trans1;
BRA 0x5b0 ?trans6;
MOV R10, UR6 ?trans1;
MOV R0, 0x590 ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xc50 ?trans5;
MOV R4, R10 ?trans1;
MOV R5, R11 ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR6, c[0x0][0x388] &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
BSSY.RECONVERGENT B0, 0x7d0 ?trans1;
UMOV UR7, URZ ?trans1;
LDCU.64 UR8, c[0x0][0x358] &wr=0x1 ?trans2;
IADD.64 R10, R6, UR6 &req={0} ?WAIT4_END_GROUP;
IADD.64 R12, R10, -0x1 ?WAIT6_END_GROUP;
ISETP.NE.U32.AND P0, PT, R13, RZ, PT ?WAIT13_END_GROUP;
@P0 BRA 0x780 &req={1} ?trans5;
UI2F.U32.RP UR5, UR6 ?trans1;
MOV R10, RZ ?trans1;
ISETP.NE.U32.AND P1, PT, RZ, UR6, PT ?WAIT7_END_GROUP;
MUFU.RCP R0, UR5 &wr=0x0 ?trans2;
IADD3 R13, PT, PT, R0, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R11, R13 &wr=0x0 ?trans2;
IADD3 R15, PT, PT, RZ, -R11, RZ &req={0} ?WAIT5_END_GROUP;
IMAD R15, R15, UR6, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R15, R11, R15, R10 ?WAIT6_END_GROUP;
IMAD.HI.U32 R0, R15, R12, RZ ?WAIT5_END_GROUP;
IADD3 R11, PT, PT, -R0, RZ, RZ ?WAIT5_END_GROUP;
IMAD R10, R11, UR6, R12 ?trans1;
MOV R11, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P0, PT, R10, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R10, PT, PT, R10, -UR6, RZ ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P0, PT, R10, UR6, PT ?WAIT13_END_GROUP;
@P0 IADD3 R10, PT, PT, R10, -UR6, RZ ?trans2;
@!P1 LOP3.LUT R10, RZ, UR6, RZ, 0x33, !PT ?trans1;
BRA 0x7c0 ?trans6;
LDCU UR5, c[0x0][0x388] &wr=0x0 ?trans1;
MOV R0, 0x7c0 ?trans1;
MOV R10, UR5 &req={0} ?WAIT7_END_GROUP;
CALL.REL.NOINC 0xc50 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDCU UR4, c[0x0][0x388] &wr=0x0 ?trans1;
HFMA2 R7, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x1 ?trans4;
IADD.64 R18, R6, 0x1 ?trans2;
UMOV UR5, URZ ?WAIT4_END_GROUP;
ISETP.NE.S64.AND P0, PT, R18, UR4, PT &req={0} ?trans2;
IMAD.WIDE.U32 R20, R8, UR4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R22, R2, UR4, R10 ?trans1;
SEL.64 R18, R18, RZ, P0 ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R14, R4, UR4, R10 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R12, R8, UR4, R6 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R10, R4, UR4, R6 ?WAIT4_END_GROUP;
IMAD R16, R3, UR4, RZ ?trans2;
IMAD.WIDE.U32 R6, R2, UR4, R6 ?WAIT3_END_GROUP;
IADD3 R23, PT, PT, R23, R16, RZ ?trans1;
IMAD R3, R5, UR4, RZ ?trans1;
IADD3 R7, PT, PT, R16, R7, RZ ?trans1;
IMAD R0, R9, UR4, RZ ?trans2;
IMAD.WIDE.U32 R8, R8, UR4, R18.reuse ?trans1;
IADD3 R15, PT, PT, R15, R3, RZ ?trans2;
IADD3 R11, PT, PT, R3, R11, RZ ?trans2;
IADD3 R21, PT, PT, R21, R0, RZ ?trans1;
IMAD.WIDE.U32 R4, R4, UR4, R18 ?trans1;
IADD.64 R24, R6, UR6 &req={1} ?WAIT3_END_GROUP;
IADD3 R13, PT, PT, R0, R13, RZ ?trans1;
IMAD.WIDE.U32 R18, R2, UR4, R18 ?trans1;
IADD.64 R14, R14, UR6 ?trans2;
IADD.64 R20, R20, UR6 ?trans2;
IADD.64 R22, R22, UR6 ?WAIT3_END_GROUP;
IADD3 R27, PT, PT, R0, R9, RZ ?trans1;
MOV R26, R8 ?trans1;
IADD3 R19, PT, PT, R16, R19, RZ ?trans1;
IADD.64 R12, R12, UR6 ?trans2;
IADD.64 R10, R10, UR6 ?trans2;
LDG.E.U8 R24, desc[UR8][R24.64] &wr=0x2 ?trans1;
IADD3 R5, PT, PT, R3, R5, RZ ?trans1;
IADD.64 R16, R26, UR6 ?trans2;
LDG.E.U8 R2, desc[UR8][R20.64] &wr=0x3 ?trans1;
IADD.64 R18, R18, UR6 ?WAIT3_END_GROUP;
LDG.E.U8 R9, desc[UR8][R22.64] &wr=0x3 ?trans4;
LDG.E.U8 R14, desc[UR8][R14.64] &wr=0x3 ?trans1;
IADD.64 R4, R4, UR6 ?WAIT3_END_GROUP;
LDG.E.U8 R13, desc[UR8][R12.64] &wr=0x4 ?trans4;
LDG.E.U8 R10, desc[UR8][R10.64] &wr=0x4 ?trans4;
LDG.E.U8 R17, desc[UR8][R16.64] &wr=0x5 ?trans4;
LDG.E.U8 R18, desc[UR8][R18.64] &wr=0x5 ?trans4;
LDG.E.U8 R5, desc[UR8][R4.64] &wr=0x5 ?trans1;
BSSY.RECONVERGENT B0, 0xc30 ?trans1;
ISETP.NE.AND P0, PT, R24, 0x1, PT &req={2} ?trans1;
IADD3 R2, PT, PT, R14, R9, R2 &req={3} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R10, R2, R13 &req={4} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R18, R2, R17 &req={5} ?WAIT4_END_GROUP;
IADD3 R2, PT, PT, R2, R5, RZ ?trans1;
@P0 BRA 0xbb0 ?trans6;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
LOP3.LUT R0, R2, 0xfffffffe, RZ, 0xc0, !PT ?trans1;
MOV R3, 0x1 ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R0, 0x2, PT ?trans1;
IADD.64 R6, R6, UR4 &req={0} ?WAIT12_END_GROUP;
@!P0 STG.E.U8 desc[UR8][R6.64], R3 &rd=0x0 ?trans4;
@P0 STG.E.U8 desc[UR8][R6.64], RZ &rd=0x0 ?trans1;
BRA 0xc20 ?trans5;
LDCU.64 UR4, c[0x0][0x390] &wr=0x0 ?trans1;
ISETP.NE.AND P0, PT, R2, 0x3, PT ?trans1;
MOV R3, 0x1 ?WAIT4_END_GROUP;
ISETP.NE.AND P0, PT, R2, 0x6, P0 ?trans1;
IADD.64 R6, R6, UR4 &req={0} ?WAIT12_END_GROUP;
@!P0 STG.E.U8 desc[UR8][R6.64], R3 &rd=0x1 ?trans4;
@P0 STG.E.U8 desc[UR8][R6.64], RZ &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
EXIT ?trans5;
MOV R11, UR4 ?WAIT4_END_GROUP;
I2F.U64.RP R18, R10 &wr=0x0 ?trans2;
MUFU.RCP R18, R18 &req={0} &wr=0x0 ?trans2;
IADD3 R14, PT, PT, R18, 0x1ffffffe, RZ &req={0} ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
NOP ?WAIT15_END_GROUP;
F2I.U64.TRUNC R14, R14 &wr=0x0 ?trans2;
IMAD.WIDE.U32 R16, R14, R10, RZ &req={0} ?WAIT4_END_GROUP;
IMAD R17, R14, UR4, R17 ?trans1;
IADD3 R19, P0, PT, RZ, -R16, RZ ?WAIT3_END_GROUP;
IMAD R17, R15, R10, R17 ?trans2;
IMAD.HI.U32 R16, R14, R19, RZ ?WAIT3_END_GROUP;
IADD3.X R21, PT, PT, RZ, ~R17, RZ, P0, !PT ?trans1;
MOV R17, R14 ?WAIT4_END_GROUP;
IMAD R23, R15, R21.reuse, RZ ?trans2;
IMAD.WIDE.U32 R16, P0, R14, R21, R16 ?WAIT4_END_GROUP;
IMAD.HI.U32 R21, R15, R21, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R16, P1, R15, R19, R16 ?WAIT5_END_GROUP;
IADD3 R17, P2, PT, R23, R16, RZ ?trans2;
IADD3.X R16, PT, PT, R21, R15, RZ, P0, !PT ?WAIT3_END_GROUP;
IMAD.WIDE.U32 R14, R17, R10, RZ ?trans1;
IADD3.X R19, PT, PT, RZ, RZ, R16, P2, P1 ?WAIT3_END_GROUP;
IMAD R15, R17, UR4, R15 ?trans1;
IADD3 R21, P0, PT, RZ, -R14, RZ ?WAIT3_END_GROUP;
IMAD R15, R19, R10, R15 ?trans2;
IMAD.HI.U32 R16, R17, R21, RZ ?WAIT3_END_GROUP;
IADD3.X R14, PT, PT, RZ, ~R15, RZ, P0, !PT ?trans1;
HFMA2 R15, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R16, P0, R17, R14, R16 ?WAIT4_END_GROUP;
IMAD R18, R19.reuse, R14, RZ ?trans2;
IMAD.HI.U32 R17, P1, R19, R21, R16 ?WAIT4_END_GROUP;
IMAD.HI.U32 R14, R19, R14, RZ ?trans1;
IADD3 R17, P2, PT, R18, R17, RZ ?WAIT4_END_GROUP;
IADD3.X R19, PT, PT, R14, R19, RZ, P0, !PT ?trans1;
IMAD.HI.U32 R14, R17, R12, RZ ?WAIT3_END_GROUP;
IADD3.X R19, PT, PT, RZ, RZ, R19, P2, P1 ?trans1;
IMAD.WIDE.U32 R14, R17, R13, R14 ?WAIT4_END_GROUP;
IMAD R17, R19.reuse, R13, RZ ?trans2;
IMAD.HI.U32 R14, P0, R19, R12, R14 ?WAIT4_END_GROUP;
IMAD.HI.U32 R16, R19, R13, RZ ?trans1;
IADD3 R17, P1, PT, R17, R14, RZ ?WAIT4_END_GROUP;
IADD3.X R16, PT, PT, R16, RZ, RZ, P0, !PT ?trans1;
IMAD.WIDE.U32 R14, R17, R10, RZ ?WAIT3_END_GROUP;
IADD3.X R19, PT, PT, RZ, R16, RZ, P1, !PT ?trans1;
IMAD R15, R17, UR4, R15 ?trans1;
ISETP.NE.S64.AND P1, PT, R10, RZ, PT ?WAIT3_END_GROUP;
IMAD R15, R19, R10, R15 ?WAIT5_END_GROUP;
IADD.64 R12, R12, -R14 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R12, R10, PT ?WAIT14_END_GROUP;
@P0 IADD.64 R12, -R10, R12 ?WAIT6_END_GROUP;
ISETP.GE.U64.AND P0, PT, R12, R10, PT ?WAIT14_END_GROUP;
@P0 IADD.64 R12, -R10, R12 ?WAIT4_END_GROUP;
SEL.64 R10, R12, -0x1, P1 ?trans2;
MOV R12, R0 ?trans1;
HFMA2 R13, -RZ, RZ, 0, 0 ?WAIT4_END_GROUP;
RET.REL.NODEC R12 0x0 ?trans5;
BRA 0xfe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: HL_kernel(unsigned char*, unsigned int, unsigned int, unsigned char*)
_Z9HL_kernelPhjjS_:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s7, 2
v_cvt_f32_u32_e32 v3, s6
v_cvt_f32_u32_e32 v1, s1
s_and_b32 s0, s8, 0xffff
s_sub_i32 s9, 0, s6
s_mov_b32 s8, s6
v_rcp_iflag_f32_e32 v4, v3
v_fmamk_f32 v2, 0, 0x4f800000, v1
v_fmac_f32_e64 v3, 0, 0x4f800000
v_rcp_iflag_f32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x5f7ffffc, v2
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_rcp_f32_e32 v0, v3
v_dual_mul_f32 v3, 0x4f7ffffe, v4 :: v_dual_mul_f32 v4, 0x4f7ffffe, v5
s_add_u32 s0, s1, -1
s_addc_u32 s10, 0, -1
s_sub_u32 s11, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v3, v3
s_subb_u32 s12, 0, 0
v_cvt_u32_f32_e32 v4, v4
s_sub_i32 s7, -2, s7
v_mul_lo_u32 v5, s9, v3
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_lo_u32 v8, s7, v4
s_add_u32 s7, s6, -1
s_addc_u32 s13, 0, -1
s_sub_u32 s14, 0, s6
s_subb_u32 s15, 0, 0
v_mul_hi_u32 v5, v3, v5
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v8, v4, v8
v_dual_mul_f32 v2, 0x2f800000, v6 :: v_dual_add_nc_u32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, 0x2f800000, v0
v_mul_hi_u32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v2, v2
v_trunc_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, 0xcf800000, v2
v_cvt_u32_f32_e32 v2, v2
v_fmac_f32_e32 v0, 0xcf800000, v7
v_cvt_u32_f32_e32 v12, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_u32_f32_e32 v6, v6
v_mul_lo_u32 v9, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, s11, v6
v_mul_lo_u32 v11, s12, v6
v_add_nc_u32_e32 v7, v10, v9
v_mul_lo_u32 v9, s11, v6
v_mul_lo_u32 v10, s14, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, v7, v11
v_mul_hi_u32 v5, v6, v9
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v11, v6, v7
v_mul_hi_u32 v14, v6, v7
v_mul_hi_u32 v15, v2, v9
v_mul_lo_u32 v9, v2, v9
v_mul_hi_u32 v16, v2, v7
v_mul_lo_u32 v7, v2, v7
v_add_co_u32 v5, vcc_lo, v5, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v14, vcc_lo
v_add_nc_u32_e32 v14, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, v5, v9
v_add_co_ci_u32_e32 v5, vcc_lo, v11, v15, vcc_lo
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v16, vcc_lo
v_mul_lo_u32 v11, v3, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, v5, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, v6, v5
v_sub_nc_u32_e32 v6, v1, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, v2, v7, vcc_lo
v_mul_hi_u32 v7, s11, v5
v_mul_lo_u32 v17, s12, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v16, s6, v6
v_cmp_le_u32_e32 vcc_lo, s6, v6
v_mul_lo_u32 v11, s11, v2
v_cndmask_b32_e32 v3, v3, v14, vcc_lo
v_cvt_u32_f32_e32 v0, v0
v_dual_cndmask_b32 v6, v6, v16 :: v_dual_add_nc_u32 v7, v7, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v11, 1, v3
v_mul_lo_u32 v9, s15, v0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s6, v6
v_add_nc_u32_e32 v8, v4, v8
v_mul_hi_u32 v4, s14, v0
v_add_nc_u32_e32 v7, v7, v17
v_mul_lo_u32 v13, s14, v0
v_cndmask_b32_e32 v11, v3, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v6, v5, v7
v_mul_hi_u32 v17, v5, v7
v_add_nc_u32_e32 v4, v4, v10
v_mul_hi_u32 v20, v2, v7
v_mul_lo_u32 v7, v2, v7
v_add_nc_u32_e32 v18, 1, v11
v_mul_hi_u32 v10, v0, v13
v_add_nc_u32_e32 v4, v4, v9
v_mul_lo_u32 v9, s11, v5
v_mul_hi_u32 v15, v12, v13
v_mul_lo_u32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v16, v0, v4
v_mul_hi_u32 v14, v0, v4
v_mul_hi_u32 v22, v12, v4
v_mul_lo_u32 v23, v12, v4
v_mul_hi_u32 v3, v5, v9
v_mul_hi_u32 v19, v2, v9
v_mul_lo_u32 v9, v2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v6
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v17, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, v6, v19, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v20, vcc_lo
v_ashrrev_i32_e32 v9, 31, v18
v_add_co_u32 v3, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v17, vcc_lo, s0, v18
v_add_co_u32 v7, s0, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v19, s0, v2, v6, s0
v_add_co_ci_u32_e32 v20, vcc_lo, s10, v9, vcc_lo
v_mul_hi_u32 v21, v17, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, v17, v19, 0
v_mad_u64_u32 v[4:5], null, v20, v7, 0
v_mad_u64_u32 v[6:7], null, v20, v19, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v21, v2
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, v16
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v3, v5, vcc_lo
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, v10, v13
v_add_co_ci_u32_e32 v2, vcc_lo, v14, v15, vcc_lo
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v22, vcc_lo
v_mul_lo_u32 v4, v11, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, v23
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_nc_u32_e32 v10, 2, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v12, vcc_lo, v12, v3, vcc_lo
v_mad_u64_u32 v[2:3], null, v18, s6, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v7, v10, v8
v_mul_hi_u32 v8, s14, v11
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v13, s14, v12
v_sub_nc_u32_e32 v15, v1, v4
v_mul_lo_u32 v1, s15, v11
v_mul_lo_u32 v19, s14, v11
v_mov_b32_e32 v0, v3
v_mul_lo_u32 v14, v7, s1
v_add_nc_u32_e32 v3, v8, v13
v_add_co_u32 v13, s0, s7, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v18, null, s13, 0, s0
v_add_nc_u32_e32 v1, v3, v1
v_add_co_u32 v3, s0, v15, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, null, 0, 0, s0
v_mad_u64_u32 v[7:8], null, v9, s6, v[0:1]
v_mul_hi_u32 v0, v11, v19
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u64_e64 s0, s[8:9], v[3:4]
v_mul_lo_u32 v8, v11, v1
v_mul_hi_u32 v9, v11, v1
v_mul_hi_u32 v22, v12, v1
v_mul_lo_u32 v1, v12, v1
v_sub_nc_u32_e32 v10, v10, v14
v_cndmask_b32_e64 v21, 0, v4, s0
v_mul_hi_u32 v4, v12, v19
v_mul_lo_u32 v19, v12, v19
v_add_co_u32 v0, vcc_lo, v0, v8
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
v_cndmask_b32_e64 v14, 0, v3, s0
v_cmp_le_u32_e64 s0, s1, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v0, v19
v_add_co_ci_u32_e32 v0, vcc_lo, v8, v4, vcc_lo
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v22, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v11, v0
v_add_co_ci_u32_e32 v11, vcc_lo, v12, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, v6
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v16, v13, v8
v_mad_u64_u32 v[0:1], null, v13, v11, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[3:4], null, s1, v5, 0
v_mad_u64_u32 v[5:6], null, v18, v8, 0
v_mad_u64_u32 v[8:9], null, v18, v11, 0
v_add_co_u32 v0, vcc_lo, v16, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_subrev_nc_u32_e32 v11, s1, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
v_mov_b32_e32 v0, v4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, v1, v8
v_mad_u64_u32 v[4:5], null, s1, v12, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
v_sub_co_u32 v6, vcc_lo, v17, v3
v_mad_u64_u32 v[0:1], null, s6, v8, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_ci_u32_e32 v8, vcc_lo, v20, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s1, v6
v_mov_b32_e32 v16, v7
v_cndmask_b32_e64 v7, v10, v11, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s0, 0, v8
v_mad_u64_u32 v[3:4], null, s6, v5, v[1:2]
v_cndmask_b32_e64 v9, 0, -1, vcc_lo
v_sub_co_u32 v10, vcc_lo, v6, s1
v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v8, vcc_lo
v_cndmask_b32_e64 v8, -1, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v10
v_subrev_nc_u32_e32 v5, s1, v10
v_cndmask_b32_e64 v4, 0, -1, vcc_lo
v_sub_co_u32 v0, vcc_lo, v13, v0
v_sub_co_ci_u32_e32 v3, vcc_lo, v18, v3, vcc_lo
v_sub_co_u32 v11, vcc_lo, v0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v11
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v1, -1, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, 0, v1
v_cndmask_b32_e64 v4, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_cndmask_b32_e64 v1, v10, v5, s0
v_cndmask_b32_e32 v12, -1, v12, vcc_lo
v_sub_co_u32 v13, vcc_lo, v11, s6
v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v9, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e32 v4, -1, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e64 s0, 0, v4
v_cndmask_b32_e32 v5, v9, v17, vcc_lo
v_cndmask_b32_e32 v4, v11, v13, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v8
v_subrev_nc_u32_e32 v9, s1, v7
v_cndmask_b32_e64 v3, v3, v5, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v0, v4, s0
v_cndmask_b32_e32 v6, v6, v1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s1, v7
v_add_co_u32 v17, s0, s4, v15
v_add_co_ci_u32_e64 v18, null, s5, 0, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[0:1], null, v6, s6, 0
v_cndmask_b32_e32 v5, v7, v9, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v3, vcc_lo
v_mad_u64_u32 v[3:4], null, v5, s6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, v9, v0
v_add_co_ci_u32_e32 v6, vcc_lo, v10, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, v9, v2
v_add_co_ci_u32_e32 v8, vcc_lo, v10, v16, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, v3
v_add_co_ci_u32_e32 v10, vcc_lo, v10, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, v17, v0
v_add_co_ci_u32_e32 v12, vcc_lo, v18, v1, vcc_lo
v_add_co_u32 v19, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v21, vcc_lo
v_add_co_u32 v13, vcc_lo, v17, v3
v_add_co_ci_u32_e32 v14, vcc_lo, v18, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v19, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v20, v1, vcc_lo
s_clause 0x5
global_load_u8 v21, v[5:6], off
global_load_u8 v7, v[7:8], off
global_load_u8 v8, v[9:10], off
global_load_u8 v9, v[11:12], off
global_load_u8 v10, v[13:14], off
global_load_u8 v11, v[0:1], off
v_add_co_u32 v0, vcc_lo, v19, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v20, v16, vcc_lo
v_add_co_u32 v3, vcc_lo, v19, v3
v_add_co_ci_u32_e32 v4, vcc_lo, v20, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v17, v2
v_add_co_ci_u32_e32 v6, vcc_lo, v18, v16, vcc_lo
s_clause 0x2
global_load_u8 v12, v[0:1], off
global_load_u8 v3, v[3:4], off
global_load_u8 v4, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(7)
v_add_nc_u32_e32 v0, v7, v21
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v8, v9
s_waitcnt vmcnt(3)
v_add3_u32 v5, v0, v10, v11
v_add_co_u32 v0, vcc_lo, v2, v15
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v16, vcc_lo
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v2, v5, v12, v3
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 1, v4
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_10
s_mov_b32 s5, 0
s_mov_b32 s4, 0
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 5, v2
s_xor_b32 s0, exec_lo, s0
v_cmp_ne_u32_e32 vcc_lo, 6, v2
s_mov_b32 s4, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s6, s0
v_cmp_eq_u32_e32 vcc_lo, 3, v2
v_cmp_ne_u32_e64 s0, 3, v2
s_and_not1_b32 s4, s4, exec_lo
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s4, s4, s7
s_or_b32 s5, s5, s0
s_or_b32 exec_lo, exec_lo, s6
s_and_saveexec_b32 s0, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_7
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v4, 0
s_and_not1_b32 s4, s4, exec_lo
global_store_b8 v[2:3], v4, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s4
s_cbranch_execz .LBB0_9
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_10:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_16
v_add_co_u32 v0, s0, s2, v0
v_and_b32_e32 v2, 0x7fe, v2
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ne_u32_e32 2, v2
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_13:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
| HL_kernel | 5,994 | 8,495 | stackv2-00000-of-00015 |
// Demangled: gpuVecadd(int*, int*, int*, int)
Function : _Z9gpuVecaddPiS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x398] &wr=0x2 ?trans7;
LDC R9, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R9, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x140;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: gpuVecadd(int*, int*, int*, int)
_Z9gpuVecaddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| gpuVecadd | 573 | 577 | stackv2-00000-of-00015 |
// Demangled: init_a(int*)
Function : _Z6init_aPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R5, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R5, R5, UR6, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5.reuse, 0x4, R2 &req={2} ?trans1;
IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: init_a(int*)
_Z6init_aPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| init_a | 321 | 338 | stackv2-00000-of-00015 |
// Demangled: scan_a(int*)
Function : _Z6scan_aPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R0, SR_TID.X &wr=0x0 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x0 ?trans8;
LDC R5, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
IMAD R5, R5, UR4, R0 &req={0} ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x0 ?trans4;
IADD3 R0, PT, PT, R5.reuse, 0x1, RZ ?trans1;
IMAD.WIDE R2, R5, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.HI R4, R0, 0x55555556, RZ ?WAIT5_END_GROUP;
LEA.HI R7, R4, R4, RZ, 0x1 ?WAIT5_END_GROUP;
IMAD R7, R7, -0x3, R0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R7 &req={0} ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: scan_a(int*)
_Z6scan_aPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v0, 0x55555556, v3
v_lshrrev_b32_e32 v2, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
v_lshl_add_u32 v4, v0, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_sub_nc_u32_e32 v2, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| scan_a | 390 | 524 | stackv2-00000-of-00015 |
// Demangled: call_min(double*, double const*)
Function : _Z8call_minPdPKd
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x8, R4 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R7, 0x8, R2 &req={2} ?trans2;
LDG.E.64 R4, desc[UR4][R4.64] &req={1} &wr=0x2 ?trans4;
LDG.E.64 R6, desc[UR4][R2.64] &wr=0x2 ?trans2;
DSETP.GEU.AND P0, PT, R4, R6, PT &req={2} &wr=0x0 ?trans2;
FSEL R6, R4, R6, !P0 &req={0} ?trans1;
FSEL R7, R5, R7, !P0 ?WAIT5_END_GROUP;
STG.E.64 desc[UR4][R2.64], R6 ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: call_min(double*, double const*)
_Z8call_minPdPKd:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[2:3]
global_load_b64 v[2:3], v4, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| call_min | 422 | 220 | stackv2-00000-of-00015 |
// Demangled: init_vec(int, float*)
Function : _Z8init_veciPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R5, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x2 ?trans1;
IMAD R5, R0, UR6, R5 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?trans1;
I2FP.F32.S32 R5, R5 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0xb0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: init_vec(int, float*)
_Z8init_veciPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| init_vec | 315 | 340 | stackv2-00000-of-00015 |
// Demangled: multi_vec(int, int, int, int, float*, float*, float*)
Function : _Z9multi_veciiiiPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans8;
LDC.64 R2, c[0x0][0x388] &wr=0x0 ?trans1;
S2R R7, SR_TID.X &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans8;
S2UR UR6, SR_CTAID.X &wr=0x4 ?trans1;
I2F.U32.RP R6, R2 &req={0} &wr=0x0 ?trans1;
I2F.U32.RP R0, R5 &req={3} &wr=0x3 ?trans1;
ISETP.NE.U32.AND P3, PT, R5, RZ, PT ?trans1;
MUFU.RCP R6, R6 &req={0} &wr=0x0 ?trans1;
MUFU.RCP R0, R0 &req={3} &wr=0x3 ?trans1;
IADD3 R10, PT, PT, R6, 0xffffffe, RZ &req={0} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R11, R10 &rd=0x0 &wr=0x5 ?trans1;
IADD3 R8, PT, PT, R0, 0xffffffe, RZ &req={3} ?WAIT4_END_GROUP;
F2I.FTZ.U32.TRUNC.NTZ R9, R8 &rd=0x3 &wr=0x1 ?trans1;
HFMA2 R10, -RZ, RZ, 0, 0 &req={0} ?trans1;
IADD3 R13, PT, PT, RZ, -R11, RZ &req={5} ?trans1;
MOV R8, RZ &req={3} ?WAIT4_END_GROUP;
IMAD R13, R13, R2, RZ ?trans1;
IADD3 R6, PT, PT, RZ, -R9, RZ &req={1} ?WAIT3_END_GROUP;
IMAD.HI.U32 R0, R11, R13, R10 ?WAIT4_END_GROUP;
IMAD R11, R6, R5, RZ ?trans2;
IMAD.HI.U32 R6, R0, R7, RZ ?WAIT4_END_GROUP;
IMAD.HI.U32 R8, R9, R11, R8 ?trans1;
IADD3 R9, PT, PT, -R6, RZ, RZ ?trans1;
LDC.64 R10, c[0x0][0x3a0] &wr=0x0 ?trans4;
IMAD.HI.U32 R8, R8, R7, RZ ?WAIT4_END_GROUP;
IMAD R9, R2, R9, R7 ?trans1;
IADD3 R8, PT, PT, -R8, RZ, RZ ?WAIT4_END_GROUP;
ISETP.GE.U32.AND P2, PT, R9, R2, PT ?trans1;
IMAD R0, R5, R8, R7 ?WAIT5_END_GROUP;
ISETP.GE.U32.AND P1, PT, R0, R5, PT ?WAIT7_END_GROUP;
@P2 IADD3 R9, PT, PT, R9, -R2, RZ ?trans2;
@P2 IADD3 R6, PT, PT, R6, 0x1, RZ ?WAIT3_END_GROUP;
ISETP.GE.U32.AND P0, PT, R9, R2, PT ?trans1;
@P1 IADD3 R0, PT, PT, R0, -R5.reuse, RZ ?trans1;
ISETP.NE.U32.AND P1, PT, R2, RZ, PT ?trans1;
LDC.64 R8, c[0x0][0x398] &wr=0x1 ?trans3;
ISETP.GE.U32.AND P2, PT, R0, R5, PT ?WAIT7_END_GROUP;
@P0 IADD3 R6, PT, PT, R6, 0x1, RZ ?trans2;
@!P1 LOP3.LUT R6, RZ, R2, RZ, 0x33, !PT ?WAIT4_END_GROUP;
@P2 IADD3 R0, PT, PT, R0, -R5.reuse, RZ ?trans2;
IADD3 R12, PT, PT, -R6, RZ, RZ ?trans2;
@!P3 LOP3.LUT R0, RZ, R5, RZ, 0x33, !PT ?WAIT3_END_GROUP;
IMAD R2, R2, R12, R7 ?trans2;
IMAD R5, R4, UR6, R0 &req={4} ?trans2;
IMAD R13, R2, R3, R6 ?trans2;
IMAD.WIDE R2, R5, 0x4, R8 &req={1} ?trans1;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans3;
IMAD.WIDE R4, R13, 0x4, R10 &req={0} ?WAIT2_END_GROUP;
LDG.E.CONSTANT R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans3;
LDC.64 R8, c[0x0][0x390] &wr=0x0 ?trans1;
LDG.E.CONSTANT R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD R7, R0, UR6, R7 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE R6, R7, 0x4, R8 &req={0} ?WAIT4_END_GROUP;
FMUL R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x3a0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: multi_vec(int, int, int, int, float*, float*, float*)
_Z9multi_veciiiiPfS_S_:
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s6
v_cvt_f32_u32_e32 v2, s5
s_sub_i32 s2, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, s2, v1
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, s2, v2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s0, s[0:1], 0x34
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v4
v_mul_hi_u32 v2, v0, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_sub_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v3, v1, s6
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s5, v2
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_add_nc_u32 v5, 1, v1
v_cmp_le_u32_e32 vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v3, s5, v2
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v4, v1, s6
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v0, v4
v_mad_u64_u32 v[3:4], null, s15, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v7, s7, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[5:6]
v_add_co_u32 v1, vcc_lo, s10, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v5, v[1:2], off
global_load_b32 v3, v[3:4], off
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v5, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| multi_vec | 1,567 | 1,918 | stackv2-00000-of-00015 |
// Demangled: reduction_row(int, float*, float*)
Function : _Z13reduction_rowiPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R4, c[0x0][0x380] &wr=0x1 ?trans1;
S2R R7, SR_TID.X &wr=0x2 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x2 ?trans8;
LDC R6, c[0x0][0x360] &wr=0x2 ?trans1;
IABS R9, R4 &req={1} ?WAIT4_END_GROUP;
I2F.RP R0, R9 &wr=0x1 ?trans1;
IMAD R7, R6, UR4, R7 &req={2} ?trans1;
MUFU.RCP R0, R0 &req={1} &wr=0x1 ?trans4;
ISETP.GE.AND P2, PT, R7, RZ, PT ?trans1;
IADD3 R2, PT, PT, R0, 0xffffffe, RZ &req={1} ?trans2;
IABS R0, R7 ?trans2;
F2I.FTZ.U32.TRUNC.NTZ R3, R2 &rd=0x1 &wr=0x2 ?trans2;
HFMA2 R2, -RZ, RZ, 0, 0 &req={1} ?trans1;
IADD3 R5, PT, PT, RZ, -R3, RZ &req={2} ?WAIT5_END_GROUP;
MOV R6, R5 ?WAIT5_END_GROUP;
IMAD R5, R6, R9, RZ ?trans1;
LOP3.LUT R6, RZ, R4, RZ, 0x33, !PT ?WAIT3_END_GROUP;
IMAD.HI.U32 R3, R3, R5, R2 ?WAIT6_END_GROUP;
IMAD.HI.U32 R5, R3, R0, RZ ?WAIT5_END_GROUP;
IADD3 R3, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
IMAD R0, R9, R3, R0 ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P1, PT, R9, R0, PT ?WAIT13_END_GROUP;
@!P1 IADD3 R0, PT, PT, R0, -R9, RZ ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, R0, PT ?trans1;
IADD3 R3, PT, PT, R0, -R9, RZ ?WAIT5_END_GROUP;
SEL R3, R3, R0, !P0 ?trans1;
ISETP.NE.AND P0, PT, R4, RZ, PT ?WAIT4_END_GROUP;
@!P2 IADD3 R3, PT, PT, -R3, RZ, RZ ?WAIT5_END_GROUP;
SEL R3, R6, R3, !P0 ?WAIT5_END_GROUP;
ISETP.NE.AND P2, PT, R3, 0x1f, PT ?WAIT13_END_GROUP;
@P2 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x390] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E.CONSTANT R8, desc[UR4][R2.64+-0x7c] &req={1} &wr=0x2 ?trans4;
LDG.E.CONSTANT R33, desc[UR4][R2.64+-0x78] &wr=0x2 ?trans4;
LDG.E.CONSTANT R35, desc[UR4][R2.64+-0x74] &wr=0x3 ?trans4;
LDG.E.CONSTANT R37, desc[UR4][R2.64+-0x70] &wr=0x4 ?trans4;
LDG.E.CONSTANT R32, desc[UR4][R2.64+-0x6c] &wr=0x5 ?trans4;
LDG.E.CONSTANT R31, desc[UR4][R2.64+-0x68] &wr=0x5 ?trans4;
LDG.E.CONSTANT R11, desc[UR4][R2.64+-0x64] &wr=0x5 ?trans4;
LDG.E.CONSTANT R12, desc[UR4][R2.64+-0x60] &wr=0x5 ?trans4;
LDG.E.CONSTANT R13, desc[UR4][R2.64+-0x5c] &wr=0x5 ?trans4;
LDG.E.CONSTANT R14, desc[UR4][R2.64+-0x58] &wr=0x5 ?trans4;
LDG.E.CONSTANT R15, desc[UR4][R2.64+-0x54] &wr=0x5 ?trans4;
LDG.E.CONSTANT R16, desc[UR4][R2.64+-0x50] &wr=0x5 ?trans4;
LDG.E.CONSTANT R17, desc[UR4][R2.64+-0x4c] &wr=0x5 ?trans4;
LDG.E.CONSTANT R18, desc[UR4][R2.64+-0x48] &wr=0x5 ?trans4;
LDG.E.CONSTANT R19, desc[UR4][R2.64+-0x44] &wr=0x5 ?trans4;
LDG.E.CONSTANT R20, desc[UR4][R2.64+-0x40] &wr=0x5 ?trans4;
LDG.E.CONSTANT R21, desc[UR4][R2.64+-0x3c] &wr=0x5 ?trans4;
LDG.E.CONSTANT R22, desc[UR4][R2.64+-0x38] &wr=0x5 ?trans4;
LDG.E.CONSTANT R23, desc[UR4][R2.64+-0x34] &wr=0x5 ?trans4;
LDG.E.CONSTANT R24, desc[UR4][R2.64+-0x30] &wr=0x5 ?trans4;
LDG.E.CONSTANT R25, desc[UR4][R2.64+-0x2c] &wr=0x5 ?trans4;
LDG.E.CONSTANT R26, desc[UR4][R2.64+-0x28] &wr=0x5 ?trans4;
LDG.E.CONSTANT R27, desc[UR4][R2.64+-0x24] &wr=0x5 ?trans4;
LDG.E.CONSTANT R28, desc[UR4][R2.64+-0x20] &wr=0x5 ?trans4;
LDG.E.CONSTANT R29, desc[UR4][R2.64+-0x1c] &wr=0x5 ?trans4;
LDG.E.CONSTANT R30, desc[UR4][R2.64+-0x18] &wr=0x5 ?trans4;
LDG.E.CONSTANT R10, desc[UR4][R2.64+-0x14] &wr=0x5 ?trans1;
FADD R8, R8, R33 &req={2} ?WAIT3_END_GROUP;
LDG.E.CONSTANT R33, desc[UR4][R2.64+-0x4] &wr=0x2 ?trans1;
FADD R8, R8, R35 &req={3} ?WAIT4_END_GROUP;
FADD R37, R8, R37 &req={4} ?trans2;
LDG.E.CONSTANT R8, desc[UR4][R2.64+-0x10] &wr=0x3 ?trans2;
FADD R34, R37, R32 &req={5} ?trans2;
LDG.E.CONSTANT R32, desc[UR4][R2.64+-0xc] &wr=0x4 ?trans2;
FADD R36, R34, R31 ?trans2;
LDG.E.CONSTANT R34, desc[UR4][R2.64+-0x8] &wr=0x5 ?trans4;
LDG.E.CONSTANT R31, desc[UR4][R2.64] &rd=0x0 &wr=0x2 ?trans1;
FADD R11, R36, R11 ?WAIT4_END_GROUP;
FADD R12, R11, R12 ?WAIT4_END_GROUP;
FADD R13, R12, R13 ?trans1;
ISETP.GE.U32.AND P2, PT, R0, R9, PT ?trans1;
LOP3.LUT R4, R7, R4, RZ, 0x3c, !PT ?trans1;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans1;
FADD R14, R13, R14 ?WAIT4_END_GROUP;
FADD R15, R14, R15 ?WAIT4_END_GROUP;
FADD R16, R15, R16 ?WAIT4_END_GROUP;
FADD R17, R16, R17 ?WAIT4_END_GROUP;
FADD R18, R17, R18 ?WAIT4_END_GROUP;
FADD R19, R18, R19 ?WAIT4_END_GROUP;
FADD R20, R19, R20 ?WAIT4_END_GROUP;
FADD R21, R20, R21 ?WAIT4_END_GROUP;
FADD R22, R21, R22 ?WAIT4_END_GROUP;
FADD R23, R22, R23 ?WAIT4_END_GROUP;
FADD R24, R23, R24 ?WAIT4_END_GROUP;
FADD R25, R24, R25 ?WAIT4_END_GROUP;
FADD R26, R25, R26 ?WAIT4_END_GROUP;
FADD R27, R26, R27 ?WAIT4_END_GROUP;
FADD R28, R27, R28 ?WAIT4_END_GROUP;
FADD R29, R28, R29 ?trans1;
@!P1 IADD3 R5, PT, PT, R5, 0x1, RZ ?trans1;
ISETP.GE.AND P1, PT, R4, RZ, PT ?trans2;
FADD R29, R29, R30 ?WAIT4_END_GROUP;
FADD R29, R29, R10 ?trans1;
@P2 IADD3 R5, PT, PT, R5, 0x1, RZ ?WAIT6_END_GROUP;
@!P1 IADD3 R5, PT, PT, -R5, RZ, RZ ?WAIT5_END_GROUP;
SEL R5, R6, R5, !P0 ?WAIT5_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={0} ?WAIT4_END_GROUP;
FADD R29, R29, R8 &req={3} ?WAIT4_END_GROUP;
FADD R29, R29, R32 &req={4} ?WAIT4_END_GROUP;
FADD R34, R29, R34 &req={5} ?WAIT4_END_GROUP;
FADD R34, R34, R33 &req={2} ?WAIT4_END_GROUP;
FADD R31, R34, R31 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R31 ?trans1;
EXIT ?trans5;
BRA 0x6d0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: reduction_row(int, float*, float*)
_Z13reduction_rowiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s5
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_xor_b32_e32 v5, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v5
v_mul_lo_u32 v3, v0, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v3
v_cmpx_eq_u32_e32 31, v3
s_cbranch_execz .LBB3_2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v29, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v30, vcc_lo, s3, v2, vcc_lo
s_clause 0x7
global_load_b128 v[1:4], v[29:30], off offset:-124
global_load_b128 v[5:8], v[29:30], off offset:-108
global_load_b128 v[9:12], v[29:30], off offset:-92
global_load_b128 v[13:16], v[29:30], off offset:-76
global_load_b128 v[17:20], v[29:30], off offset:-60
global_load_b128 v[21:24], v[29:30], off offset:-44
global_load_b128 v[25:28], v[29:30], off offset:-28
global_load_b128 v[29:32], v[29:30], off offset:-12
s_waitcnt vmcnt(7)
v_add_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v3
v_add_f32_e32 v1, v1, v4
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v5
v_add_f32_e32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v7
v_add_f32_e32 v1, v1, v8
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v9
v_add_f32_e32 v1, v1, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v11
v_add_f32_e32 v1, v1, v12
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v13
v_add_f32_e32 v1, v1, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v15
v_add_f32_e32 v1, v1, v16
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v17
v_add_f32_e32 v1, v1, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v19
v_add_f32_e32 v1, v1, v20
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v21
v_add_f32_e32 v1, v1, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v23
v_add_f32_e32 v1, v1, v24
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v25
v_add_f32_e32 v1, v1, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v27
v_add_f32_e32 v1, v1, v28
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v1, v29
v_ashrrev_i32_e32 v1, 31, v0
v_add_f32_e32 v2, v2, v30
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_f32_e32 v2, v2, v31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_f32_e32 v2, v2, v32
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| reduction_row | 2,936 | 2,734 | stackv2-00000-of-00015 |
// Demangled: scalareMatrice(float*, float, float*)
Function : _Z14scalareMatricePffS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD R7, R0, UR6, R7 &req={0} ?trans1;
LDCU UR6, c[0x0][0x388] &wr=0x0 ?trans3;
IMAD.WIDE R2, R7, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R2, desc[UR4][R2.64] &req={1} &wr=0x0 ?trans1;
IMAD.WIDE R4, R7, 0x4, R4 &req={3} ?WAIT4_END_GROUP;
FMUL R7, R2, UR6 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R7 ?trans1;
EXIT ?trans5;
BRA 0xf0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: scalareMatrice(float*, float, float*)
_Z14scalareMatricePffS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| scalareMatrice | 427 | 471 | stackv2-00000-of-00015 |
// Demangled: transpose(int, int, float*, float*)
Function : _Z9transposeiiPfS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R7, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R8, c[0x0][0x380] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans1;
IMAD R5, R9, UR6, R7 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT3_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans3;
LDG.E.CONSTANT R3, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD R7, R7, R8, UR6 ?WAIT4_END_GROUP;
IMAD.WIDE R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0xe0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: transpose(int, int, float*, float*)
_Z9transposeiiPfS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, v0, s4, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| transpose | 406 | 517 | stackv2-00000-of-00015 |
// Demangled: vecdif(int, float*, float*, float*)
Function : _Z6vecdifiPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD R9, R0, UR6, R9 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R9, R2, -R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecdif(int, float*, float*, float*)
_Z6vecdifiPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecdif | 503 | 497 | stackv2-00000-of-00015 |
// Demangled: vecsum(int, float*, float*, float*)
Function : _Z6vecsumiPfS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
S2UR UR6, SR_CTAID.X &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC R0, c[0x0][0x360] &wr=0x0 ?trans8;
LDC.64 R2, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R4, c[0x0][0x398] &wr=0x3 ?trans1;
IMAD R9, R0, UR6, R9 &req={0} ?WAIT7_END_GROUP;
LDC.64 R6, c[0x0][0x388] &wr=0x0 ?trans1;
IMAD.WIDE R2, R9, 0x4, R2 &req={2} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
IMAD.WIDE R4, R9, 0x4, R4 &req={3} ?WAIT6_END_GROUP;
LDG.E.CONSTANT R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE R6, R9, 0x4, R6 &req={0} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x110;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: vecsum(int, float*, float*, float*)
_Z6vecsumiPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| vecsum | 502 | 497 | stackv2-00000-of-00015 |
// Demangled: mat_add(float*, float*, float*, int)
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R9, R9, 0xa, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={3} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?WAIT4_END_GROUP;
FADD R9, R2, R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mat_add(float*, float*, float*, int)
_Z7mat_addPfS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, 10, v1
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mat_add | 480 | 287 | stackv2-00000-of-00015 |
// Demangled: mat_mult(float*, float*, float*, int)
Function : _Z8mat_multPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x388] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R0, SR_TID.Y &wr=0x1 ?trans6;
LDC.64 R4, c[0x0][0x380] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R9, R9, 0xa, RZ &req={0} ?WAIT2_END_GROUP;
IMAD.WIDE.U32 R2, R0, 0x4, R2 &req={1} ?WAIT3_END_GROUP;
IADD3 R11, PT, PT, R9.reuse, R0, RZ ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={3} ?trans1;
LDG.E R8, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans3;
IMAD.WIDE.U32 R6, R11, 0x4, R6 &req={4} ?trans1;
LDG.E R9, desc[UR4][R4.64] &wr=0x2 ?trans4;
LDG.E R0, desc[UR4][R6.64] &wr=0x2 ?trans2;
FFMA R9, R9, R8, R0 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x4] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x28] &wr=0x2 ?trans2;
FFMA R11, R0, R8, R9 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R11 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x8] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x50] &wr=0x2 ?trans2;
FFMA R13, R0, R8, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R13 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64+0xc] &wr=0x0 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x78] &wr=0x0 ?trans2;
FFMA R9, R0, R8, R13 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x10] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R2.64+0xa0] &wr=0x1 ?trans2;
FFMA R11, R0, R8, R9 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R11 &rd=0x1 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x14] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R2.64+0xc8] &wr=0x2 ?trans2;
FFMA R13, R0, R8, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R13 &rd=0x2 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x18] &wr=0x0 ?trans4;
LDG.E R8, desc[UR4][R2.64+0xf0] &wr=0x0 ?trans2;
FFMA R9, R0, R8, R13 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 &rd=0x0 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x1c] &wr=0x1 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x118] &wr=0x1 ?trans2;
FFMA R11, R0, R8, R9 &req={1} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R11 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x20] &wr=0x2 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x140] &wr=0x2 ?trans2;
FFMA R13, R0, R8, R11 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R13 ?trans4;
LDG.E R0, desc[UR4][R4.64+0x24] &wr=0x0 ?trans4;
LDG.E R8, desc[UR4][R2.64+0x168] &wr=0x0 ?trans2;
FFMA R9, R0, R8, R13 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x360;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mat_mult(float*, float*, float*, int)
_Z8mat_multPfS_S_i:
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v2, 10, v1
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_lshl_u32 v1, v2, v0, 2
v_lshlrev_b32_e32 v5, 2, v2
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v1, s[4:5]
v_add_co_u32 v0, s4, s4, v1
v_add_co_u32 v2, s2, s2, v3
v_add_co_u32 v5, s0, s0, v5
v_add_co_ci_u32_e64 v1, null, s5, 0, s4
v_add_co_ci_u32_e64 v3, null, s3, 0, s2
v_add_co_ci_u32_e64 v6, null, s1, 0, s0
s_mov_b64 s[0:1], 0
.LBB2_1:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
global_load_b32 v9, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 40
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cmp_eq_u32 s0, 40
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v7, v9
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB2_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mat_mult | 1,548 | 677 | stackv2-00000-of-00015 |
// Demangled: mat_sub(float*, float*, float*, int)
Function : _Z7mat_subPfS_S_i
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R9, SR_TID.X &wr=0x0 ?trans7;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x2 ?trans1;
S2R R0, SR_TID.Y &wr=0x0 ?trans6;
LDC.64 R4, c[0x0][0x388] &wr=0x3 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x4 ?trans1;
IMAD R9, R9, 0xa, R0 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R4, R9.reuse, 0x4, R4 &req={3} ?trans2;
LDG.E R2, desc[UR4][R2.64] &req={2} &wr=0x2 ?trans4;
LDG.E R5, desc[UR4][R4.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={4} ?WAIT4_END_GROUP;
FADD R9, R2, -R5 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x100;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: mat_sub(float*, float*, float*, int)
_Z7mat_subPfS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, 10, v1
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| mat_sub | 481 | 287 | stackv2-00000-of-00015 |
// Demangled: hello(char*)
Function : _Z5helloPc
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] ?trans1;
S2R R2, SR_TID.X &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x380] &wr=0x0 ?trans1;
HFMA2 R3, -RZ, RZ, 0, 0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans4;
IADD.64 R2, R2, UR6 &req={0} ?WAIT6_END_GROUP;
LDG.E.U8 R0, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans2;
IADD3 R5, PT, PT, R0, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
STG.E.U8 desc[UR4][R2.64], R5 ?trans1;
EXIT ?trans5;
BRA 0xa0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: hello(char*)
_Z5helloPc:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| hello | 306 | 117 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*, int*)
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R9, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans2;
IMAD R9, R9, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GT.U32.AND P0, PT, R9, 0x270f, PT ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x0][0x380] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans7;
LDC.64 R4, c[0x0][0x388] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x390] &wr=0x3 ?trans1;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x4 ?trans1;
IMAD.WIDE.U32 R4, R9, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDG.E R5, desc[UR4][R4.64] &wr=0x4 ?trans1;
IMAD.WIDE.U32 R6, R9, 0x4, R6 &req={3} ?trans1;
IADD3 R9, PT, PT, R2, R5, RZ &req={4} ?WAIT5_END_GROUP;
STG.E desc[UR4][R6.64], R9 ?trans1;
EXIT ?trans5;
BRA 0x130;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*, int*)
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x2710, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 557 | 545 | stackv2-00000-of-00015 |
// Demangled: SpMV_COO_kernel_v1(SparseMatrixCOO, float const*, float*)
Function : _Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3a0] &wr=0x2 ?trans7;
LDC R13, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R13, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR4, c[0x0][0x370] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R13, R13, UR4, RZ &req={0} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x3a8] &wr=0x0 ?trans1;
LDG.E R3, desc[UR6][R2.64] &req={1} &wr=0x0 ?trans1;
IMAD.WIDE R4, R0, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDC.64 R10, c[0x0][0x3b0] &wr=0x1 ?trans1;
LDG.E R5, desc[UR6][R4.64] &wr=0x1 ?trans1;
IMAD.WIDE R6, R0, 0x4, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
IMAD.WIDE R8, R3, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
LDG.E R9, desc[UR6][R8.64] &wr=0x2 ?trans1;
IMAD.WIDE R10, R5, 0x4, R10 &req={1} ?WAIT5_END_GROUP;
LDG.E R15, desc[UR6][R10.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R13, R0, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT ?trans1;
FFMA R15, R6, R9, R15 &req={2} ?WAIT5_END_GROUP;
STG.E desc[UR6][R10.64], R15 &rd=0x0 ?trans7;
@!P0 BRA 0xb0 ?trans5;
EXIT ?trans5;
BRA 0x200;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: SpMV_COO_kernel_v1(SparseMatrixCOO, float const*, float*)
_Z18SpMV_COO_kernel_v115SparseMatrixCOOPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v0, v[2:3], off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[6:7], off
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v0, v2
global_store_b32 v[6:7], v3, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| SpMV_COO_kernel_v1 | 922 | 1,114 | stackv2-00000-of-00015 |
// Demangled: SpMV_COO_kernel_v2(SparseMatrixCOO, float const*, float*)
Function : _Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans7;
S2UR UR4, SR_CTAID.X &wr=0x1 ?trans1;
LDCU UR5, c[0x0][0x3a0] &wr=0x2 ?trans7;
LDC R13, c[0x0][0x360] &wr=0x1 ?trans2;
IMAD R0, R13, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDCU UR4, c[0x0][0x370] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R13, R13, UR4, RZ &req={0} ?WAIT7_END_GROUP;
LDC.64 R2, c[0x0][0x388] &req={0} &wr=0x0 ?trans8;
LDC.64 R4, c[0x0][0x390] &wr=0x2 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x3 ?trans1;
IMAD.WIDE R2, R0, 0x4, R2 &req={0} ?WAIT7_END_GROUP;
LDC.64 R8, c[0x0][0x3a8] &wr=0x0 ?trans1;
LDG.E R3, desc[UR6][R2.64] &req={1} &wr=0x0 ?trans1;
IMAD.WIDE R4, R0, 0x4, R4 &req={2} ?WAIT6_END_GROUP;
LDC.64 R10, c[0x0][0x3b0] &wr=0x1 ?trans1;
LDG.E R5, desc[UR6][R4.64] &wr=0x1 ?trans1;
IMAD.WIDE R6, R0, 0x4, R6 &req={3} ?WAIT6_END_GROUP;
LDG.E R6, desc[UR6][R6.64] &wr=0x2 ?trans1;
IMAD.WIDE R8, R3, 0x4, R8 &req={0} ?WAIT6_END_GROUP;
LDG.E R9, desc[UR6][R8.64] &wr=0x2 ?trans1;
IADD3 R0, PT, PT, R13, R0, RZ ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR5, PT ?trans1;
IMAD.WIDE R2, R5, 0x4, R10 &req={1} ?WAIT4_END_GROUP;
FMUL R11, R6, R9 &req={2} ?WAIT5_END_GROUP;
REDG.E.ADD.F32.FTZ.RN.STRONG.GPU desc[UR6][R2.64], R11 &rd=0x0 ?trans3;
@!P0 BRA 0xb0 ?trans5;
EXIT ?trans5;
BRA 0x1f0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: SpMV_COO_kernel_v2(SparseMatrixCOO, float const*, float*)
_Z18SpMV_COO_kernel_v215SparseMatrixCOOPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_5
s_load_b32 s2, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
.LBB1_2:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s10, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v2
global_load_b32 v4, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[8:9], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, v0, v4
.LBB1_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v5, v0
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_2
.LBB1_5:
s_endpgm
| SpMV_COO_kernel_v2 | 886 | 1,312 | stackv2-00000-of-00015 |
// Demangled: add(int*, int*)
Function : _Z3addPiS_
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans8;
LDC R0, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R8, SR_TID.X &wr=0x2 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x3 ?trans1;
ISETP.GE.U32.AND P0, PT, R0, 0x2, PT &req={1} ?WAIT13_END_GROUP;
@!P0 BRA 0x1a0 &req={3,2,0} ?trans5;
S2R R9, SR_CTAID.X &wr=0x0 ?trans1;
LDC.64 R2, c[0x0][0x380] &wr=0x1 ?trans8;
LDC.64 R6, c[0x0][0x380] &wr=0x2 ?trans1;
IMAD R9, R9, 0x8, R8 &req={0} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R9, 0x4, R2 &req={1} ?WAIT7_END_GROUP;
SHF.R.U32.HI R10, RZ, 0x1, R0 ?trans1;
BSSY.RECONVERGENT B0, 0x160 ?trans4;
ISETP.GE.U32.AND P0, PT, R8, R10, PT ?WAIT13_END_GROUP;
@P0 BRA 0x150 &req={0} ?trans5;
IADD3 R5, PT, PT, R9, R10, RZ ?trans1;
LDG.E R11, desc[UR4][R2.64] &wr=0x3 ?trans4;
IMAD.WIDE.U32 R4, R5, 0x4, R6 &req={2} ?WAIT6_END_GROUP;
LDG.E R4, desc[UR4][R4.64] &wr=0x3 ?trans2;
IADD3 R11, PT, PT, R4, R11, RZ &req={3} ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R11 &rd=0x0 ?trans2;
BSYNC.RECONVERGENT B0 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.GT.U32.AND P0, PT, R0, 0x3, PT ?trans1;
MOV R0, R10 ?WAIT12_END_GROUP;
@P0 BRA 0xb0 ?trans5;
ISETP.NE.AND P0, PT, R8, RZ, PT ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R7, SR_CTAID.X &req={2} &wr=0x1 ?trans1;
LDC.64 R2, c[0x0][0x380] &req={0} &wr=0x0 ?trans1;
IMAD.SHL.U32 R5, R7, 0x8, RZ &req={1} ?WAIT4_END_GROUP;
IMAD.WIDE.U32 R2, R5, 0x4, R2 &req={0} ?WAIT3_END_GROUP;
LDC.64 R4, c[0x0][0x388] &wr=0x0 ?trans3;
LDG.E R3, desc[UR4][R2.64] &wr=0x2 ?trans1;
IMAD.WIDE.U32 R4, R7, 0x4, R4 &req={0} ?WAIT5_END_GROUP;
STG.E desc[UR4][R4.64], R3 &req={2} ?trans1;
EXIT ?trans5;
BRA 0x250;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: add(int*, int*)
_Z3addPiS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s5, 2
s_cbranch_scc1 .LBB0_5
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v3, s4, 3, v0
s_lshr_b32 s5, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_2:
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v1, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v1, v[6:7], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v6, v1
global_store_b32 v[4:5], v1, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s6, s5, 1
s_cmp_gt_u32 s5, 1
s_mov_b32 s5, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_mov_b32 s5, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_lshl_b64 s[6:7], s[4:5], 2
v_mov_b32_e32 v0, 0
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_lshl_b32 s4, s4, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| add | 980 | 977 | stackv2-00000-of-00015 |
// Demangled: bfs_do_i()
Function : _Z8bfs_do_iv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R0, SR_CTAID.Z &wr=0x1 ?trans1;
LDCU UR4, c[0x3][URZ] &wr=0x2 ?trans1;
S2R R11, SR_TID.Z &wr=0x1 ?trans2;
IMAD R0, R0, 0x8, R11 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R0, UR4, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2R R4, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR8, c[0x3][0x4] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x0 ?trans2;
IMAD R6, R3, 0x8, R4 &req={0} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R6, UR8, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R10, SR_TID.X &wr=0x0 ?trans1;
LDCU UR4, c[0x3][0x8] &wr=0x1 ?trans1;
S2R R5, SR_CTAID.X &wr=0x0 ?trans2;
IMAD R5, R5, 0x8, R10 &req={0} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R5, UR4, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDCU UR5, c[0x3][0xc] &wr=0x0 ?trans1;
LDC.64 R8, c[0x3][0x30] &wr=0x1 ?trans1;
LDCU.64 UR10, c[0x0][0x358] &wr=0x2 ?trans1;
IMAD R3, R0, UR5, R5 &req={0} ?WAIT4_END_GROUP;
IMAD R7, R6, UR4, R3 ?trans2;
LDC.64 R2, c[0x3][0x28] &wr=0x0 ?trans2;
IMAD.WIDE R8, R7, 0x4, R8 &req={1} ?WAIT5_END_GROUP;
LDG.E R0, desc[UR10][R8.64] &req={2} &rd=0x1 &wr=0x2 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT5_END_GROUP;
LDG.E R7, desc[UR10][R2.64] &wr=0x3 ?trans1;
LOP3.LUT P0, RZ, R10.reuse, R11, R4.reuse, 0xfe, !PT ?trans1;
UIADD3 UR4, UPT, UPT, UR4, -0x1, URZ ?trans1;
S2UR UR7, SR_CgaCtaId &wr=0x0 ?trans1;
ISETP.NE.AND P2, PT, R10.reuse, RZ, PT ?trans1;
P2R R13, PR, RZ, 0x1 ?trans1;
UMOV UR5, 0x400 ?trans1;
BSSY.RECONVERGENT B0, 0xa80 ?trans1;
ISETP.NE.AND P1, PT, R5, UR4, PT ?trans1;
IMAD R5, R11.reuse, 0x8, R4 ?trans1;
ISETP.NE.AND P5, PT, R11, RZ, P2 ?trans1;
UIADD3 UR6, UPT, UPT, UR5, 0x4, URZ ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x1, URZ ?trans1;
IMAD.U32 R8, R5, 0x8, R10 &req={1} ?trans1;
@!P0 S2R R15, SR_CgaCtaId &wr=0x1 ?trans1;
@!P0 MOV R12, 0x400 ?trans1;
ISETP.NE.AND P1, PT, R10, 0x7, P1 ?WAIT5_END_GROUP;
ISETP.NE.AND P4, PT, R11, RZ, P1 ?trans1;
ULEA UR6, UR7, UR6, 0x18 &req={0} ?trans1;
ULEA UR5, UR7, UR5, 0x18 ?trans1;
@!P0 LEA R5, R15, R12, 0x18 &req={1} ?trans1;
ISETP.NE.AND P0, PT, R11, RZ, PT ?trans1;
SHF.R.U32.HI R10, RZ, 0x9, R0.reuse &req={2} ?trans2;
SHF.R.U32.HI R9, RZ, 0x5, R0 ?trans2;
LOP3.LUT R10, R10, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R9, R9, 0x1, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
SHF.R.U32.HI R11, RZ, 0x4, R0.reuse ?trans1;
ISETP.EQ.U32.AND P0, PT, R10, 0x1, P0 ?trans1;
SHF.R.U32.HI R10, RZ, 0x6, R0.reuse ?trans1;
ISETP.EQ.U32.AND P3, PT, R9, 0x1, P1 ?trans1;
LOP3.LUT R11, R11, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R10, R10, 0x1, RZ, 0xc0, !PT ?trans2;
P2R R16, PR, RZ, 0x8 ?trans2;
SHF.R.U32.HI R9, RZ, 0x2, R0.reuse ?trans1;
ISETP.EQ.U32.AND P3, PT, R10, 0x1, P2 ?trans1;
ISETP.EQ.U32.AND P1, PT, R11, 0x1, P1 ?trans1;
SHF.R.U32.HI R10, RZ, 0x8, R0 ?WAIT2_END_GROUP;
SHF.R.U32.HI R11, RZ, 0x7, R0.reuse ?trans2;
P2R R18, PR, RZ, 0x8 ?trans1;
ISETP.NE.AND P3, PT, R6, UR4, PT ?trans1;
LEA R6, R8, UR6, 0x2 ?trans1;
LDCU UR6, c[0x3][URZ] &wr=0x0 ?trans1;
LOP3.LUT R9, R9, 0x1, RZ, 0xc0, !PT ?trans2;
ISETP.NE.AND P3, PT, R4, 0x7, P3 ?trans1;
SHF.R.U32.HI R8, RZ, 0x1, R0 ?trans1;
STS [R6], R7 &req={3} &rd=0x1 ?trans1;
LOP3.LUT R10, R10, 0x1, RZ, 0xc0, !PT ?WAIT2_END_GROUP;
LOP3.LUT R11, R11, 0x1, RZ, 0xc0, !PT ?trans2;
LOP3.LUT R8, R8, 0x1, RZ, 0xc0, !PT ?trans1;
ISETP.EQ.U32.AND P6, PT, R9, 0x1, P3 ?trans1;
SHF.R.U32.HI R12, RZ, 0x3, R0 ?trans1;
ISETP.EQ.U32.AND P3, PT, R10, 0x1, P4 ?trans1;
ISETP.EQ.U32.AND P4, PT, R11, 0x1, P5 ?trans1;
ISETP.NE.U32.AND P5, PT, R8, 0x1, PT ?trans1;
LOP3.LUT R12, R12, 0x1, RZ, 0xc0, !PT ?trans2;
P2R R22, PR, RZ, 0x40 ?WAIT2_END_GROUP;
LOP3.LUT P6, RZ, R0, 0x3ff, RZ, 0xc0, !PT ?trans1;
ISETP.NE.AND P5, PT, R4, RZ, !P5 ?trans1;
ISETP.EQ.U32.AND P2, PT, R12, 0x1, P2 ?trans1;
MOV R4, UR5 ?trans1;
P2R R7, PR, RZ, 0x40 &req={1,0} ?WAIT11_END_GROUP;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
P2R R7, PR, RZ, 0x1 ?trans1;
ISETP.NE.AND P0, PT, R13, RZ, PT ?trans1;
LOP3.LUT P6, RZ, R0, 0x3ff, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
BSSY.RECONVERGENT B1, 0xa30 ?trans9;
@!P0 MOV R4, R5 &req={0} ?WAIT5_END_GROUP;
@!P0 STS [R4], RZ &rd=0x0 ?trans1;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans1;
ISETP.NE.AND P0, PT, R7, RZ, PT ?WAIT5_END_GROUP;
@!P6 BRA 0xa20 ?trans8;
S2R R9, SR_TID.Z &wr=0x1 ?trans1;
ISETP.NE.AND P6, PT, R22, RZ, PT ?trans1;
UIADD3 UR4, UPT, UPT, UR6, -0x1, URZ ?trans1;
P2R R11, PR, RZ, 0x20 ?trans1;
S2R R10, SR_CTAID.Z &wr=0x1 ?trans1;
BSSY.RECONVERGENT B2, 0x890 ?trans1;
LDS R7, [R6] ?trans4;
@P1 LDS R14, [R6+0x4] ?trans4;
@P6 LDS R8, [R6+0x20] &wr=0x2 ?trans4;
@P2 LDS R17, [R6+-0x4] &rd=0x3 &wr=0x4 ?trans4;
@P3 LDS R19, [R6+-0xfc] &rd=0x3 &wr=0x0 ?trans4;
@P4 LDS R20, [R6+-0x104] &rd=0x3 &wr=0x0 ?trans4;
@P0 LDS R21, [R6+-0x100] &rd=0x3 &wr=0x0 ?trans1;
IMAD R10, R10, 0x8, R9 &req={1} ?WAIT3_END_GROUP;
@P5 LDS R12, [R6+-0x20] &rd=0x3 &wr=0x1 ?trans1;
ISETP.NE.AND P5, PT, R22, RZ, PT ?trans1;
ISETP.NE.AND P6, PT, R10, UR4, PT ?WAIT5_END_GROUP;
ISETP.EQ.OR P6, PT, R9, 0x7, !P6 ?WAIT7_END_GROUP;
@P5 IADD3 R15, PT, PT, R8, 0x1, RZ &req={2} ?trans1;
ISETP.NE.AND P5, PT, R11, RZ, PT ?trans1;
MOV R8, R7 ?WAIT4_END_GROUP;
@P6 BRA 0x880 &req={4,3} ?trans8;
LOP3.LUT P6, RZ, R0, 0x1, RZ, 0xc0, !PT ?trans2;
P2R R23, PR, RZ, 0x1 ?trans1;
ISETP.NE.AND P0, PT, R16, RZ, PT ?trans1;
MOV R8, R7 ?WAIT9_END_GROUP;
@P6 LDS R9, [R6+0x100] &wr=0x2 ?trans2;
@P6 IADD3 R10, PT, PT, R9, 0x1, RZ &req={2} ?trans2;
@P0 LDS R9, [R6+0x104] &wr=0x2 ?trans3;
@P6 VIMNMX.S32 R8, R7, R10, PT ?trans1;
ISETP.NE.AND P6, PT, R18, RZ, PT ?WAIT13_END_GROUP;
@P6 LDS R10, [R6+0xfc] &wr=0x3 ?trans1;
@P0 IADD3 R9, PT, PT, R9, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
@P0 VIMNMX.S32 R8, R8, R9, PT ?trans1;
ISETP.NE.AND P0, PT, R23, RZ, PT ?trans1;
@P6 IADD3 R11, PT, PT, R10, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
@P6 VIMNMX.S32 R8, R8, R11, PT ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
ISETP.NE.AND P6, PT, R22, RZ, PT ?trans1;
@P5 IADD3 R9, PT, PT, R12, 0x1, RZ &req={1} ?trans2;
@P2 IADD3 R17, PT, PT, R17, 0x1, RZ ?trans2;
@P3 IADD3 R19, PT, PT, R19, 0x1, RZ &req={0} ?trans2;
@P0 IADD3 R21, PT, PT, R21, 0x1, RZ ?WAIT6_END_GROUP;
@P6 VIMNMX.S32 R8, R8, R15, PT ?WAIT5_END_GROUP;
@P5 VIMNMX.S32 R8, R8, R9, PT ?trans1;
@P1 IADD3 R9, PT, PT, R14, 0x1, RZ ?WAIT5_END_GROUP;
@P1 VIMNMX.S32 R8, R8, R9, PT ?trans1;
@P4 IADD3 R9, PT, PT, R20, 0x1, RZ ?WAIT4_END_GROUP;
@P2 VIMNMX.S32 R8, R8, R17, PT ?WAIT5_END_GROUP;
@P3 VIMNMX.S32 R8, R8, R19, PT ?WAIT5_END_GROUP;
@P4 VIMNMX.S32 R8, R8, R9, PT ?WAIT5_END_GROUP;
@P0 VIMNMX.S32 R8, R8, R21, PT ?WAIT5_END_GROUP;
ISETP.NE.AND P6, PT, R8, R7, PT ?WAIT13_END_GROUP;
@!P6 BRA 0xa20 ?trans5;
S2UR UR5, SR_CgaCtaId &wr=0x0 ?trans1;
UMOV UR4, 0x400 ?trans1;
STS [R6], R8 ?trans1;
ULEA UR4, UR5, UR4, 0x18 &req={0} ?WAIT6_END_GROUP;
MOV R4, UR4 ?WAIT5_END_GROUP;
LDS R7, [R4] &wr=0x0 ?trans2;
ISETP.NE.AND P6, PT, R7, RZ, PT &req={0} ?WAIT13_END_GROUP;
@!P6 MOV R7, 0x1 ?WAIT5_END_GROUP;
@!P6 STS [R4], R7 &rd=0x1 ?trans2;
BSYNC.RECONVERGENT B1 ?trans5;
BAR.SYNC.DEFER_BLOCKING 0x0 ?trans6;
LDS R7, [R4] &req={1} &wr=0x1 ?trans2;
ISETP.NE.AND P6, PT, R7, RZ, PT &req={1} ?WAIT13_END_GROUP;
@P6 BRA 0x590 ?trans5;
BSYNC.RECONVERGENT B0 ?trans5;
LDS R5, [R6] &wr=0x1 ?trans4;
STG.E desc[UR10][R2.64], R5 &req={1} ?trans1;
EXIT ?trans5;
BRA 0xab0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bfs_do_i()
_Z8bfs_do_iv:
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, size_s@rel32@lo+4
s_addc_u32 s1, s1, size_s@rel32@hi+12
v_bfe_u32 v2, v0, 20, 10
s_load_b32 s0, s[0:1], 0x0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, s15, 3, v2
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s0, v4
s_cbranch_execz .LBB3_32
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size_h@rel32@lo+4
s_addc_u32 s3, s3, size_h@rel32@hi+12
v_bfe_u32 v3, v0, 10, 10
s_load_b32 s7, s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v5, s14, 3, v3
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s7, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_32
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size_w@rel32@lo+4
s_addc_u32 s3, s3, size_w@rel32@hi+12
v_and_b32_e32 v7, 0x3ff, v0
s_load_b32 s8, s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v6, s13, 3, v7
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_32
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size_hw@rel32@lo+4
s_addc_u32 s3, s3, size_hw@rel32@hi+12
v_mul_lo_u32 v0, s8, v5
s_load_b32 s1, s[2:3], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, TAG@rel32@lo+4
s_addc_u32 s3, s3, TAG@rel32@hi+12
v_cmp_ne_u32_e64 s6, 7, v3
s_load_b64 s[2:3], s[2:3], 0x0
v_lshlrev_b32_e32 v10, 2, v7
v_cmp_eq_u32_e64 s5, 0, v7
v_cmp_ne_u32_e64 s4, 0, v7
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s1, v4
v_cmp_eq_u32_e64 s1, 7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v6, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v8, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, HGT@rel32@lo+4
s_addc_u32 s3, s3, HGT@rel32@hi+12
s_add_i32 s0, s0, -1
s_load_b64 s[2:3], s[2:3], 0x0
global_load_b32 v13, v[8:9], off
s_add_i32 s10, s8, -1
s_add_i32 s9, s7, -1
v_cmp_eq_u32_e64 s7, 7, v7
v_cmp_eq_u32_e64 s8, s0, v4
v_cmp_eq_u32_e64 s10, s10, v6
v_cmp_ne_u32_e64 s9, s9, v5
v_lshlrev_b32_e32 v8, 8, v2
v_lshlrev_b32_e32 v9, 5, v3
s_or_b32 s16, s1, s8
s_or_b32 s1, s7, s10
s_and_b32 s17, s6, s9
s_or_b32 s6, s16, s1
v_or3_b32 v7, v2, v3, v7
s_xor_b32 s20, s6, -1
s_xor_b32 s18, s16, -1
s_xor_b32 s19, s1, -1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cmp_eq_u32_e64 s2, 0, v2
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_mov_b32_e32 v2, 0
global_load_b32 v14, v[0:1], off
v_cmp_ne_u32_e64 s3, 0, v3
v_mov_b32_e32 v3, 1
v_add3_u32 v4, v8, v9, v10
v_add3_u32 v5, v9, v10, v8
v_add3_u32 v6, v8, v10, v9
s_or_b32 s1, s2, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, -4, v4
v_add_nc_u32_e32 v7, 0x100, v5
v_add_nc_u32_e32 v8, 0xfc, v5
v_subrev_nc_u32_e32 v9, 32, v6
v_add_nc_u32_e32 v11, 0xffffff00, v5
v_add_nc_u32_e32 v12, 0xfffffefc, v5
s_xor_b32 s21, s1, -1
s_waitcnt vmcnt(1)
v_and_b32_e32 v16, 1, v13
v_and_b32_e32 v18, 64, v13
v_and_b32_e32 v24, 0x80, v13
v_and_b32_e32 v19, 4, v13
v_and_b32_e32 v21, 16, v13
v_and_b32_e32 v15, 0x3ff, v13
v_and_b32_e32 v17, 32, v13
v_and_b32_e32 v20, 2, v13
v_and_b32_e32 v22, 8, v13
v_and_b32_e32 v23, 0x100, v13
v_and_b32_e32 v13, 0x200, v13
v_cmp_eq_u32_e64 s6, 1, v16
v_cmp_eq_u32_e64 s8, 0, v18
v_cmp_eq_u32_e64 s14, 0, v24
v_cmp_ne_u32_e64 s9, 0, v19
v_cmp_ne_u32_e64 s11, 0, v21
v_cmp_ne_u32_e64 s7, 0, v17
v_cmp_ne_u32_e64 s10, 0, v20
v_cmp_ne_u32_e64 s12, 0, v22
v_cmp_ne_u32_e64 s13, 0, v23
v_cmp_ne_u32_e64 s15, 0, v13
s_and_b32 s6, s18, s6
s_or_b32 s18, s5, s8
s_or_b32 s5, s5, s14
v_cmp_ne_u32_e64 s1, 0, v15
s_and_b32 s8, s17, s9
s_and_b32 s9, s19, s11
s_or_b32 s11, s16, s18
s_or_b32 s5, s2, s5
s_and_b32 s7, s20, s7
s_and_b32 s3, s3, s10
s_and_b32 s4, s4, s12
s_and_b32 s10, s21, s13
s_xor_b32 s2, s11, -1
s_xor_b32 s5, s5, -1
s_and_b32 s11, vcc_lo, s15
s_waitcnt vmcnt(0)
ds_store_b32 v4, v14
.LBB3_4:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s0
s_cbranch_execz .LBB3_6
ds_store_b32 v2, v2 offset:2048
.LBB3_6:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s1
s_cbranch_execz .LBB3_30
ds_load_b32 v14, v4
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v13, v14
s_and_saveexec_b32 s13, s6
s_cbranch_execz .LBB3_9
ds_load_b32 v13, v5 offset:256
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v13, 1, v13
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v14, v13
.LBB3_9:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s7
s_cbranch_execz .LBB3_11
ds_load_b32 v15, v7 offset:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_11:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB3_13
ds_load_b32 v15, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_13:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s8
s_cbranch_execz .LBB3_15
ds_load_b32 v15, v6 offset:32
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_15:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB3_17
ds_load_b32 v15, v9
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_17:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s9
s_cbranch_execz .LBB3_19
ds_load_b32 v15, v4 offset:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_19:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s4
s_cbranch_execz .LBB3_21
ds_load_b32 v15, v10
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_21:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s10
s_cbranch_execz .LBB3_23
ds_load_b32 v15, v11 offset:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_23:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s5
s_cbranch_execz .LBB3_25
ds_load_b32 v15, v12
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_25:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s11
s_cbranch_execz .LBB3_27
ds_load_b32 v15, v11
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v15, 1, v15
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v13, v13, v15
.LBB3_27:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, v13, v14
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_30
ds_load_b32 v14, v2 offset:2048
ds_store_b32 v4, v13
s_waitcnt lgkmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 0, v14
s_cbranch_vccnz .LBB3_30
ds_store_b32 v2, v3 offset:2048
.LBB3_30:
s_or_b32 exec_lo, exec_lo, s12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v13, v2 offset:2048
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v13
s_cbranch_vccnz .LBB3_4
ds_load_b32 v2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB3_32:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bfs_do_i | 4,276 | 4,391 | stackv2-00000-of-00015 |
// Demangled: bfs_do_o(int*)
Function : _Z8bfs_do_oPi
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R11, SR_CTAID.Z &wr=0x1 ?trans1;
LDCU UR5, c[0x3][URZ] &wr=0x2 ?trans1;
S2R R4, SR_TID.Z &wr=0x1 ?trans2;
IMAD R11, R11, 0x8, R4 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R11, UR5, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
S2R R8, SR_TID.Y &wr=0x0 ?trans1;
LDCU UR8, c[0x3][0x4] &wr=0x1 ?trans1;
S2R R3, SR_CTAID.Y &wr=0x0 ?trans2;
IMAD R10, R3, 0x8, R8 &req={0} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R10, UR8, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
S2R R7, SR_TID.X &wr=0x0 ?trans1;
LDC R15, c[0x3][0x8] &wr=0x1 ?trans1;
S2R R6, SR_CTAID.X &wr=0x0 ?trans2;
IMAD R6, R6, 0x8, R7 &req={0} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R6, R15, PT &req={1} ?WAIT13_END_GROUP;
@P0 EXIT ?trans5;
LDC R13, c[0x3][0xc] &wr=0x0 ?trans1;
LDCU.64 UR6, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD R9, R10, R15, RZ ?WAIT6_END_GROUP;
LDC.64 R2, c[0x3][0x30] &wr=0x2 ?trans1;
IMAD R12, R11, R13, R6 &req={0} ?WAIT5_END_GROUP;
IADD3 R5, PT, PT, R9, R12, RZ ?WAIT5_END_GROUP;
IMAD.WIDE R2, R5, 0x4, R2 &req={2} ?WAIT5_END_GROUP;
LDG.E R14, desc[UR6][R2.64] &req={1} &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR5, -0x1, URZ ?WAIT6_END_GROUP;
ISETP.NE.AND P4, PT, R11, UR4, PT ?trans1;
LOP3.LUT P0, RZ, R14, 0x3ff, RZ, 0xc0, !PT &req={2} ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDCU.64 UR4, c[0x3][0x28] &wr=0x0 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R5 ?trans2;
LEA R2, P0, R5, UR4, 0x2 &req={0} ?WAIT4_END_GROUP;
LEA.HI.X R3, R5, UR5, R0, 0x2, P0 ?WAIT5_END_GROUP;
LDG.E R0, desc[UR6][R2.64] &rd=0x0 &wr=0x5 ?trans1;
ISETP.EQ.AND P4, PT, R4, 0x7, P4 ?trans1;
IADD3 R5, PT, PT, R15, -0x1, RZ ?trans1;
ISETP.NE.AND P1, PT, R11, RZ, PT ?trans1;
ISETP.NE.AND P2, PT, R6.reuse, RZ, PT ?trans1;
BSSY.RECONVERGENT B0, 0x4b0 ?trans4;
BSSY.RELIABLE B1, 0x470 ?trans1;
ISETP.NE.AND P5, PT, R6, R5, PT ?trans1;
ISETP.EQ.AND P1, PT, R4, RZ, P1 ?trans1;
SHF.R.S32.HI R5, RZ, 0x1f, R13 ?WAIT2_END_GROUP;
LEA R4, P0, R13, R2, 0x2 ?trans1;
ISETP.EQ.AND P2, PT, R7.reuse, RZ, P2 ?trans1;
ISETP.EQ.AND P5, PT, R7, 0x7, P5 ?trans2;
LEA.HI.X R5, R13, R3, R5, 0x2, P0 ?trans2;
SHF.R.S32.HI R17, RZ, 0x1f, R15 ?trans1;
@P4 BRA 0x3a0 &req={0} ?trans8;
SHF.R.U32.HI R7, RZ, 0x5, R14 ?WAIT4_END_GROUP;
LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.EQ.U32.AND P0, PT, R7, 0x1, PT ?trans1;
MOV R7, R0 &req={5} ?WAIT12_END_GROUP;
@P5 BRA P0, 0x460 ?trans5;
BREAK.RELIABLE B1 ?trans5;
BRA 0x4a0 ?trans5;
LOP3.LUT R7, R14.reuse, 0x1, RZ, 0xc0, !PT ?trans1;
BSSY.RECONVERGENT B2, 0x440 ?trans1;
LOP3.LUT P3, RZ, R14, 0x20, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.NE.U32.AND P0, PT, R7, 0x1, PT ?trans1;
MOV R7, R0 &req={5} ?WAIT12_END_GROUP;
@P0 BRA 0x430 ?trans5;
LDG.E R7, desc[UR6][R4.64] &wr=0x2 ?trans2;
IADD3 R7, PT, PT, R7, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.S32 R7, R0, R7, PT ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B2 ?trans5;
@!P3 BREAK.RELIABLE B1 ?trans5;
@!P3 BRA 0x4a0 ?trans5;
BSYNC.RELIABLE B1 ?trans5;
LDG.E R16, desc[UR6][R4.64+0x4] &wr=0x2 ?trans2;
IADD3 R16, PT, PT, R16, 0x1, RZ &req={2} ?WAIT5_END_GROUP;
VIMNMX.S32 R7, R16, R7, PT ?WAIT7_END_GROUP;
BSYNC.RECONVERGENT B0 ?trans5;
WARPSYNC.ALL ?trans5;
NOP ?trans1;
LOP3.LUT P0, RZ, R14, 0x40, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P4, PT, P0, P2, P4, 0x1f, 0x0 ?WAIT13_END_GROUP;
@!P4 LDG.E R4, desc[UR6][R4.64+-0x4] &wr=0x2 ?trans1;
UIADD3 UR4, UPT, UPT, UR8, -0x1, URZ ?trans1;
LOP3.LUT P0, RZ, R14.reuse, 0x4, RZ, 0xc0, !PT ?trans2;
LOP3.LUT P3, RZ, R14, 0x10, RZ, 0xc0, !PT ?WAIT3_END_GROUP;
ISETP.EQ.OR P0, PT, R10, UR4, !P0 ?trans1;
PLOP3.LUT P3, PT, P5, P3, PT, 0x2f, 0xf2 ?WAIT4_END_GROUP;
ISETP.NE.OR P0, PT, R8, 0x7, P0 ?WAIT13_END_GROUP;
@!P0 LEA R16, P6, R15, R2, 0x2 ?WAIT4_END_GROUP;
@!P0 LEA.HI.X R17, R15, R3, R17, 0x2, P6 ?trans2;
LOP3.LUT P6, RZ, R14.reuse, 0x100, RZ, 0xc0, !PT ?trans1;
IMAD R11, R11, R13, -R13 ?trans2;
@!P0 LDG.E R16, desc[UR6][R16.64] &wr=0x3 ?trans1;
PLOP3.LUT P6, PT, P6, P1, P5, 0x1f, 0x0 ?trans2;
LOP3.LUT P5, RZ, R14, 0x80, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P5, PT, P5, P1, P2, 0x1f, 0x0 ?trans2;
IADD3 R11, PT, PT, R9, R6, R11 ?trans2;
@!P3 LDG.E R6, desc[UR6][R2.64+0x4] &wr=0x4 ?trans2;
IADD3 R11, PT, PT, R11, 0x1, RZ ?trans2;
@!P4 IADD3 R18, PT, PT, R4, 0x1, RZ &req={2} ?trans2;
LDC.64 R4, c[0x3][0x28] &wr=0x0 ?trans3;
@!P4 VIMNMX.S32 R7, R7, R18, PT ?trans1;
LOP3.LUT P4, RZ, R14, 0x8, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P4, PT, P2, P4, PT, 0x2f, 0xf2 ?trans2;
LOP3.LUT P2, RZ, R14, 0x200, RZ, 0xc0, !PT ?WAIT4_END_GROUP;
PLOP3.LUT P1, PT, P1, P2, PT, 0x2f, 0xf2 ?trans2;
LOP3.LUT P2, RZ, R14, 0x2, RZ, 0xc0, !PT ?WAIT5_END_GROUP;
ISETP.EQ.OR P2, PT, R10, RZ, !P2 ?WAIT5_END_GROUP;
ISETP.NE.OR P2, PT, R8, RZ, P2 ?trans2;
@!P4 LDG.E R8, desc[UR6][R2.64+-0x4] &wr=0x2 ?trans11;
@!P2 IADD3 R15, PT, PT, R12, R9, -R15 ?WAIT5_END_GROUP;
@!P2 IMAD.WIDE R14, R15, 0x4, R4 &req={0} ?WAIT6_END_GROUP;
@!P2 LDG.E R14, desc[UR6][R14.64] &wr=0x5 ?trans1;
IMAD.WIDE R4, R11, 0x4, R4 ?WAIT5_END_GROUP;
@!P6 LDG.E R9, desc[UR6][R4.64] &wr=0x5 ?trans4;
@!P5 LDG.E R10, desc[UR6][R4.64+-0x8] &wr=0x5 ?trans4;
@!P1 LDG.E R11, desc[UR6][R4.64+-0x4] &wr=0x5 ?trans1;
@!P0 IADD3 R16, PT, PT, R16, 0x1, RZ &req={3} ?WAIT5_END_GROUP;
@!P0 VIMNMX.S32 R7, R7, R16, PT ?trans1;
@!P3 IADD3 R6, PT, PT, R6, 0x1, RZ &req={4} ?trans2;
@!P4 IADD3 R8, PT, PT, R8, 0x1, RZ &req={2} ?trans2;
@!P2 IADD3 R14, PT, PT, R14, 0x1, RZ &req={5} ?WAIT5_END_GROUP;
@!P2 VIMNMX.S32 R7, R7, R14, PT ?WAIT5_END_GROUP;
@!P3 VIMNMX.S32 R7, R7, R6, PT ?trans1;
@!P6 IADD3 R6, PT, PT, R9, 0x1, RZ ?WAIT4_END_GROUP;
@!P4 VIMNMX.S32 R7, R7, R8, PT ?trans1;
@!P5 IADD3 R10, PT, PT, R10, 0x1, RZ ?WAIT4_END_GROUP;
@!P6 VIMNMX.S32 R7, R7, R6, PT ?trans1;
@!P1 IADD3 R4, PT, PT, R11, 0x1, RZ ?WAIT4_END_GROUP;
@!P5 VIMNMX.S32 R7, R7, R10, PT ?WAIT5_END_GROUP;
@!P1 VIMNMX.S32 R7, R7, R4, PT ?WAIT5_END_GROUP;
ISETP.NE.AND P0, PT, R7, R0, PT ?WAIT13_END_GROUP;
@!P0 EXIT ?trans5;
LDC.64 R4, c[0x0][0x380] &wr=0x0 ?trans1;
STG.E desc[UR6][R2.64], R7 &rd=0x1 ?trans4;
LDG.E R0, desc[UR6][R4.64] &req={0} &wr=0x2 ?trans2;
ISETP.NE.AND P0, PT, R0, RZ, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={1} ?trans5;
HFMA2 R3, -RZ, RZ, 0, 5.9604644775390625e-08 ?WAIT5_END_GROUP;
STG.E desc[UR6][R4.64], R3 ?trans1;
EXIT ?trans5;
BRA 0x8b0;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bfs_do_o(int*)
_Z8bfs_do_oPi:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, size_s@rel32@lo+4
s_addc_u32 s3, s3, size_s@rel32@hi+12
v_bfe_u32 v9, v0, 20, 10
s_load_b32 s2, s[2:3], 0x0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v8, s15, 3, v9
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v8
s_cbranch_execz .LBB4_27
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, size_h@rel32@lo+4
s_addc_u32 s5, s5, size_h@rel32@hi+12
v_bfe_u32 v13, v0, 10, 10
s_load_b32 s10, s[4:5], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v12, s14, 3, v13
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s10, v12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_27
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, size_w@rel32@lo+4
s_addc_u32 s5, s5, size_w@rel32@hi+12
v_and_b32_e32 v14, 0x3ff, v0
s_load_b32 s7, s[4:5], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, s13, 3, v14
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s7, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_27
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, size_hw@rel32@lo+4
s_addc_u32 s5, s5, size_hw@rel32@hi+12
v_mul_lo_u32 v4, s7, v12
s_load_b32 s6, s[4:5], 0x0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, TAG@rel32@lo+4
s_addc_u32 s5, s5, TAG@rel32@hi+12
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v10, s6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v10, v3
v_add_nc_u32_e32 v0, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[5:6], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v5, 0x3ff, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_27
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, HGT@rel32@lo+4
s_addc_u32 s5, s5, HGT@rel32@hi+12
v_and_b32_e32 v7, 1, v6
s_load_b64 s[4:5], s[4:5], 0x0
s_add_i32 s2, s2, -1
v_add_nc_u32_e32 v15, s6, v10
v_cmp_ne_u32_e64 s2, s2, v8
v_cmp_eq_u32_e64 s3, 1, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v9
global_load_b32 v5, v[0:1], off
s_and_b32 s11, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s11, s3
s_waitcnt vmcnt(0)
v_mov_b32_e32 v7, v5
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_6
v_add3_u32 v16, v4, v3, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 2, v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b32 v7, v[16:17], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v7, v5, v7
.LBB4_6:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s7, -1
v_and_b32_e32 v11, 32, v6
v_cmp_eq_u32_e32 vcc_lo, 7, v14
v_cmp_ne_u32_e64 s2, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s3, 0, v11
v_add_nc_u32_e32 v11, v3, v4
s_and_b32 s8, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s11, s8
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_8
v_add3_u32 v16, v11, v15, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v17, 31, v16
v_lshlrev_b64 v[16:17], 2, v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s4, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
global_load_b32 v16, v[16:17], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v16, 1, v16
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v7, v7, v16
.LBB4_8:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_eq_u32_e32 vcc_lo, 0, v14
v_and_b32_e32 v14, 64, v6
v_cmp_ne_u32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, 0, v14
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s9, s11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_10
v_add3_u32 v14, v11, v15, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v14, 1, v14
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v7, v7, v14
.LBB4_10:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v14, 4, v6
s_add_i32 s10, s10, -1
v_cmp_eq_u32_e32 vcc_lo, 7, v13
v_cmp_ne_u32_e64 s2, s10, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, 0, v14
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_12
v_add3_u32 v14, v4, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b32 v14, v[14:15], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v14, 1, v14
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v7, v7, v14
.LBB4_12:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v14, 2, v6
v_cmp_eq_u32_e32 vcc_lo, 0, v13
v_cmp_ne_u32_e64 s2, 0, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, 0, v14
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_14
v_add_nc_u32_e32 v14, -1, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, s7, v14, v[2:3]
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v2, v[12:13], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
v_min_i32_e32 v7, v7, v2
.LBB4_14:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 16, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 s3, s8, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_16
v_add3_u32 v12, v11, v10, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v2, v[12:13], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v7, v7, v2
.LBB4_16:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 s3, s9, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_18
v_add3_u32 v12, v11, v10, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v2, v[12:13], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v7, v7, v2
.LBB4_18:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 0x100, v6
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_cmp_ne_u32_e64 s2, 0, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s3, 0, v2
v_add_nc_u32_e32 v2, -1, v8
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s2, s8
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s7, s7, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s7
s_cbranch_execz .LBB4_20
v_mul_lo_u32 v8, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v8, v11, v8, 1
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 1, v8
v_min_i32_e32 v7, v7, v8
.LBB4_20:
s_or_b32 exec_lo, exec_lo, s3
v_and_b32_e32 v8, 0x80, v6
s_or_b32 s3, s2, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_and_b32 s7, s3, vcc_lo
s_and_saveexec_b32 s3, s7
s_cbranch_execz .LBB4_22
v_mul_lo_u32 v8, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v8, v11, v8, -1
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 1, v8
v_min_i32_e32 v7, v7, v8
.LBB4_22:
s_or_b32 exec_lo, exec_lo, s3
v_and_b32_e32 v6, 0x200, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
s_and_b32 s3, s2, vcc_lo
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB4_24
v_mul_lo_u32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v3, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
v_min_i32_e32 v7, v7, v2
.LBB4_24:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, v7, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_27
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v7, off
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_cbranch_vccnz .LBB4_27
v_mov_b32_e32 v0, 1
global_store_b32 v2, v0, s[0:1]
.LBB4_27:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bfs_do_o | 3,740 | 6,365 | stackv2-00000-of-00015 |
// Demangled: bfs_init()
Function : _Z8bfs_initv
.headerflags @"EF_CUDA_SM120 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM120)"
LDC R1, c[0x0][0x37c] &wr=0x0 ?trans1;
S2R R7, SR_CTAID.X &wr=0x1 ?trans7;
LDC R6, c[0x3][0x10] &wr=0x2 ?trans1;
LDCU UR4, c[0x0][0x360] &wr=0x1 ?trans1;
S2R R0, SR_TID.X &wr=0x1 ?trans2;
IMAD R7, R7, UR4, R0 &req={1} ?WAIT5_END_GROUP;
ISETP.GE.AND P0, PT, R7, R6, PT &req={2} ?WAIT13_END_GROUP;
@P0 EXIT &req={0} ?trans5;
LDC.64 R2, c[0x3][0x20] &wr=0x0 ?trans1;
LDCU.64 UR4, c[0x0][0x358] &wr=0x1 ?trans1;
IMAD.WIDE R2, R7, 0x4, R2 &req={0} ?WAIT6_END_GROUP;
LDG.E R2, desc[UR4][R2.64] &req={1} &wr=0x2 ?trans1;
SHF.R.S32.HI R0, RZ, 0x1f, R7 ?trans1;
ISETP.GT.AND P0, PT, R2, -0x1, PT &req={2} ?WAIT13_END_GROUP;
@!P0 LDC.64 R4, c[0x3][0x28] &wr=0x0 ?trans2;
@!P0 LEA R4, P1, R7, R4, 0x2 &req={0} ?WAIT4_END_GROUP;
@!P0 LEA.HI.X R5, R7, R5, R0, 0x2, P1 ?WAIT5_END_GROUP;
@!P0 STG.E desc[UR4][R4.64], RZ &rd=0x0 ?trans1;
@!P0 EXIT ?trans5;
LDCU.64 UR6, c[0x3][0x28] &wr=0x1 ?trans2;
LEA R2, P0, R7, UR6, 0x2 &req={1} ?WAIT4_END_GROUP;
LEA.HI.X R3, R7, UR7, R0, 0x2, P0 ?WAIT5_END_GROUP;
STG.E desc[UR4][R2.64], R6 ?trans1;
EXIT ?trans5;
BRA 0x180;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
..........
| // Demangled: bfs_init()
_Z8bfs_initv:
s_load_b32 s2, s[0:1], 0xc
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, size_shw@rel32@lo+4
s_addc_u32 s1, s1, size_shw@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s0, v1
s_cbranch_execz .LBB2_2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, OVF@rel32@lo+4
s_addc_u32 s3, s3, OVF@rel32@hi+12
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[2:3], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, HGT@rel32@lo+4
s_addc_u32 s3, s3, HGT@rel32@hi+12
s_load_b64 s[2:3], s[2:3], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cndmask_b32_e64 v2, 0, s0, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
| bfs_init | 692 | 710 | stackv2-00000-of-00015 |
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