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Two parallel short decoders - These translate the most commonly used x86
instructions into zero, one, or two RISC86 operations each. They are also
designed to decode up to two x86 instructions per clock.
Long decoder - This handles commonly used x86 instructions that can be
represented in four or fewer RISC86 operations.
Vectoring decoder - This handles all other translations in concert with
RISC86 operation sequences fetched from an on-chip ROM."
Contemporary Intel processors now process complex instructions through the
Microcode Sequencer (MS). This unit retrieves micro-operations from the
Microcode Sequencer ROM (MSROM) and coordinates their dispatch to execution
units. Intel's Optimization Reference Manual (Section 22.5.7.2,
'Understanding the Sources of the Micro-op Queue') confirms that string
instructions are processed in this manner.
This means we could actually tweak how the CMPS instruction works. However,
accessing and altering x86 microcode has historically been a substantial
technical challenge due to Intel's proprietary security mechanisms.
Pioneering work by Ermolov, Sklyarov, and Goryachy has achieved critical
breakthroughs in this domain through their research on Intel's Goldmont
microarchitecture. Their research uncovered a critical vulnerability in TXE
firmware that permits arbitrary code execution and achieves privileged "red
unlock" status[23][24], effectively bypassing conventional microcode
security protections.
Furthermore, their discovery of previously undocumented UDBGRD/UDBGWR
instructions[30][26] provides direct access to the internal CRBUS (Control
Register Bus), enabling unprecedented low-level processor control.
Complementing these findings, the uCodeDisasm project[25] has made
substantial progress in decoding microcode semantics and identifying
numerous undocumented microarchitectural features and control registers.
All these efforts together have opened new avenues for deeper analysis of
processor internals.
--[ 3.4.2 CMPS Microcode Analysis
Identifying the microcode entry point for the CMPS instruction is
relatively straightforward due to its characteristic usage of architectural
registers. The instruction employs RCX as its loop counter while utilizing
RSI and RDI as string pointers. So, simply look for microcode associated
with RCX, RDI, and RSI and fits the three rules[25] for microcode entries.
1. The address for any x86 entry point is in the range U0000-U1000
2. The address for x86 instruction entry must be a multiple of 8
3. There must not be references in other places of ucode to the x86 entry
address
The CMPS microcode entry is located at U08b0. Fortunately/Unfortunately, no
backdoor functionality exists, much to my disappointment, since I was
hoping for a major scandal. The microcode itself is quite basic, as shown
below.
U08b0: 108100034021 tmp4:= OR_DSZN(rcx)
U08b1: 01505e100234 UJMPCC_DIRECT_NOTTAKEN_CONDZ(tmp4, U045e)
U08b2: 021e3b000200 SIGEVENT(0x0000003b)
U08b4: 014310a00200 AETTRACE(0x08, IMM_MACRO_ALIAS_INSTRUCTION)
U08b5: 213e0003a000 tmp10:= MOVEMERGEFLGS_DSZ32(0x00000000)
01bcc872 SEQW GOTO U3cc8
U3cc8: 1c0000231027 tmp1:= LDZX_DSZN_ASZ32_SC1(rdi, mode=0x08)
U3cc9: 1c0000630026 tmp0:= LDZX_DSZN_ASZ32_SC1(rsi, mode=0x18)
U3cca: 108501034d08 tmp4:= SUB_DSZN(0x00000001, tmp4)
U3ccc: 11890b8279c8 rdi:= ADDSUB_DSZ16_CONDD(IMM_MACRO_ALIAS_DATASIZE, rdi)
U3ccd: 11890b826988 rsi:= ADDSUB_DSZ16_CONDD(IMM_MACRO_ALIAS_DATASIZE, rsi)
U3cce: 10050003ac31 MSLOOP-> tmp10:= SUB_DSZN(tmp1, tmp0)
U3cd0: 015f6410023a UJMPCC_DIRECT_TAKEN_CONDZ(tmp10, U0464)
U3cd1: 015064100234 UJMPCC_DIRECT_NOTTAKEN_CONDZ(tmp4, U0464)
053cc840 SEQW GOTO U3cc8
U045c: 1088000269a6 rsi:= ZEROEXT_DSZ16N(rsi, rsi)
U045d: 1088000279e7 rdi:= ZEROEXT_DSZ16N(rdi, rdi)
U045e: 108800021861 rcx:= ZEROEXT_DSZ16N(rcx, rcx)
018000f2 SEQW UEND0
U0464: 237d3f000e88 GENARITHFLAGS(0x0000003f, tmp10)
U0465: 108800021874 rcx:= ZEROEXT_DSZ16N(tmp4, rcx)
U0466: 0fff00000000 SYNCWAIT-> SFENCE(0x00000000)
0b0000f2 SEQW UEND0
The microcode binary was disassembled into assembly language using the
uCodeDisasm. Before analyzing the code, it is necessary to first establish
some fundamental concepts.
The microcode comprises fixed-length RISC instructions. In Intel's Goldmont
microarchitecture, these are 48-bit instructions grouped into sets of three
called Microcode Triads. Each triad is accompanied by a Sequence Word
(30-bit) that manages synchronization and memory fence attributes for the
micro-instructions within the triad and controls program flow by selecting
between sequential execution of the next triad, jumps to specified
microcode addresses, or termination of the current routine.