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----[ 4.2 Other Thoughts
In a computer system, trust is rooted in the firmware. Upon startup, the
CPU runs immutable code stored in ROM or OTPROM (One-Time Programmable
ROM), which authenticates the next firmware stage through digital signature
verification. This process typically relies on asymmetric cryptography,
such as RSA. The subsequent firmware is signed with a private key, while
the ROM contains the corresponding public key to validate its integrity.
Together, this immutable ROM code and embedded public key form the root of
trust for the system.
In practice, the OTPROM has limited capacity. Consequently, instead of
storing the entire public key, only its hash is kept in OTPROM, while the
full public key resides in external storage (e.g., EEPROM or FLASH). Thus,
the ROM code's first step is to fetch the public key and verify its hash
against the one stored in ROM. This comparison establishes the root of
trust.
After successfully authenticating the root public key, the system proceeds
to validate the next stage firmware's digital signature. To understand how
digital signatures work, let's take RSA (specifically, the
RSASSA-PKCS1-V1_5 scheme) as an example. Suppose we have the firmware bin,
that needs to be verified, along with its digital signature, bin_sig. The
verification process uses the signer's public key to confirm that the
signature is valid and the data has not been altered.
1. Hash the input data: Compute the SHA-256 digest of the original data
("bin"):
hash = sha256(bin);
2. Encode the hash: Format the hash according to the EMSA-PKCS1-v1_5
padding scheme (which does not use salt):
hash_encode = EMSA-PKCS1-v1_5(hash);
3. Decrypt the signature: Use the RSA public key to decrypt "bin_sig",
get the encoded hash:
hash_encode_from_sig = rsa_decrypt(bin_sig, public_key);
4. Compare the hashes: Verify the signature by checking if the decrypted
encoded hash matches the locally computed encoded hash:
cmp(hash_encode_from_sig, hash_encode);
The final hash comparison decides whether verification passes or fails.
So far, the system has performed two hash string comparisons. But what if
the CPU recognizes even a single one of these hashes? This could break the
trust chain, allowing the execution of malicious code.
In practice, storing just a few hash strings in the CPU is not particularly
useful because a single hash only represents one digital signature. Now,
consider if the hash function had an algorithmic backdoor: one that
produces detectable patterns when processing specially crafted inputs (such
as those beginning with a particular header sequence). The CPU could detect
this pattern during string comparison and let the malicious hash to pass
authentication.
I'm not certain whether this is feasible, but it's certainly an interesting
idea to explore.
--[ 5. Conclusion
This paper introduces a CPU backdoor that enables an attacker to log into
any account on the system using a master password.
To test the idea, three prototypes are built: one on the QEMU TCG emulator,
another on the OpenSPARC T1 processor (FPGA-based), and a third via
microcode modification on an Intel Pentium N4200 CPU.
The idea we aim to convey is this: while embedding backdoors deeper into
hardware improves stealth, hardware alone imposes usability constraints.
However, if the software intentionally cooperates the hardware, we gain
more opportunities to deploy effective CPU backdoors. In our approach, the
upper-layer operating system's password authentication module exhibits
detectable behavioral patterns, which the CPU monitors to infer
authentication events.
--[ 6. Acknowledgements
Special thank you to my wife uay and our kids Ray and Summer! You never
stop believing in me. Even after three long years, you still have faith
that I'll finish this paper. I love you all so much!
Thanks to ChatGPT and DeepSeek for helping me write this paper!
--[ 7. References
[1] https://wiki.qemu.org/Documentation/TCG/frontend-ops
[2] SPARC Assembly Language Reference Manual
ERROR: type should be string, got " https://docs.oracle.com/cd/E36784_01/pdf/E36858.pdf"
[3] CPU bugs, CPU backdoors and consequences on security
[4] Live Migration with AMD-V Extended Migration Technology