id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
zephyrproject-rtos/zephyr:arch/arm64/core/switch.S:6 | /* If not nested: switch to IRQ stack and save current sp on it. */
cbnz w3, 1f
ldr x3, [x2, #___cpu_t_irq_stack_OFFSET]
mov x4, sp
mov sp, x3
str x4, [sp, #-16]!
#if defined(CONFIG_ARM64_SAFE_EXCEPTION_STACK)
/* update the stack limit with IRQ stack limit */
sub x3, x3, #CONFIG_ISR_STACK_SIZE
str x3, [x2, #_cp... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/switch.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/switch.S | 201 | 232 |
zephyrproject-rtos/zephyr:arch/arm64/core/userspace.S:1 | /*
* Copyright (c) 2020 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/syscall.h>
#include <zephyr/arch/arm64/mm.h>
#include "macro_priv.inc"
_... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/userspace.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm64/core/userspace.S:2 | add x0, x0, #1
b strlen_loop
z_arm64_user_string_nlen_fixup:
mov x4, #-1
mov x0, #0
strlen_done:
str w4, [x2]
ret
/*
* int arch_buffer_validate(const void *addr, size_t size, int write)
*/
GTEXT(arch_buffer_validate)
SECTION_FUNC(TEXT, arch_buffer_validate)
add x1, x1, x0
mrs x3, DAIF
msr DAIFSET, #DAIFS... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/userspace.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm64/core/userspace.S:3 | mov x0, #0
ret
abv_fail:
msr DAIF, x3
mov x0, #-1
ret
/*
* System call entry point.
*/
GTEXT(z_arm64_do_syscall)
SECTION_FUNC(TEXT, z_arm64_do_syscall)
/*
* CFI: entered from z_arm64_sync_exc with SP at struct arch_esf.
* Needed so GDB can unwind from syscall implementations.
*/
.cfi_sections .debug_fr... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/userspace.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm64/core/userspace.S:4 | blo valid_syscall_id
/* Save the bad ID for handler_bad_syscall() */
mov x0, x8
ldr x8, =K_SYSCALL_BAD
valid_syscall_id:
ldr x9, =_k_syscall_table
ldr x9, [x9, x8, lsl #3]
/* Jump into the syscall */
msr daifclr, #(DAIFSET_IRQ_BIT)
blr x9
msr daifset, #(DAIFSET_IRQ_BIT)
/* Save the return value into the E... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/userspace.S | 121 | 141 |
zephyrproject-rtos/zephyr:arch/arm64/core/userspace.S:2 | add x0, x0, #1
b strlen_loop
z_arm64_user_string_nlen_fixup:
mov x4, #-1
mov x0, #0
strlen_done:
str w4, [x2]
ret
/*
* int arch_buffer_validate(const void *addr, size_t size, int write)
*/
GTEXT(arch_buffer_validate)
SECTION_FUNC(TEXT, arch_buffer_validate)
add x1, x1, x0
mrs x3, DAIF
msr DAIFSET, #DAIFS... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/userspace.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/userspace.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm64/core/userspace.S:3 | mov x0, #0
ret
abv_fail:
msr DAIF, x3
mov x0, #-1
ret
/*
* System call entry point.
*/
GTEXT(z_arm64_do_syscall)
SECTION_FUNC(TEXT, z_arm64_do_syscall)
/* Recover the syscall parameters from the ESF */
ldp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
ldp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
ldp x4, x5, [sp, ___esf_t... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/userspace.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/userspace.S | 81 | 128 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:1 | /*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Populated vector table
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/offsets.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/arm64/tpidrro_el0.h>
#include <of... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:2 | .cfi_def_cfa_offset 0
sub sp, sp, ___esf_t_SIZEOF
.cfi_adjust_cfa_offset ___esf_t_SIZEOF
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
.if \el == el1
/*
* EL1t mode cannot access sp_el1, so set x0 to sp_el1 without corrupt
* other registers
*/
add sp, sp, x0 // sp' = sp + x0
sub x0, sp, x0 // x0' = sp' - x... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:3 | #endif
mrs \xreg0, spsr_el1
mrs \xreg1, elr_el1
stp \xreg0, \xreg1, [sp, ___esf_t_spsr_elr_OFFSET]
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
.if \el == el0
mrs x0, sp_el0
str x0, [sp, ___esf_t_sp_el0_OFFSET]
/* Retrieving safe exception stack */
get_cpu x0
ldr x1, [x0, #_cpu_offset_to_safe_exception_stack]
... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:5 | .cfi_sections .debug_frame
/* The whole table must be 2K aligned */
.align 11
/* Current EL with SP0 / Synchronous */
.align 7
z_arm64_enter_exc x0, x1, el1
b z_arm64_sync_exc
.cfi_endproc
/* Current EL with SP0 / IRQ */
.align 7
z_arm64_enter_exc x0, x1, el1
#ifdef CONFIG_GEN_SW_ISR_TABLE
b _isr_wrapper... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:6 | #ifdef CONFIG_GEN_SW_ISR_TABLE
b _isr_wrapper
#else
b z_irq_spurious
#endif
.cfi_endproc
/* Current EL with SPx / FIQ */
.align 7
b .
/* Current EL with SPx / SError */
.align 7
z_arm64_enter_exc x0, x1, el1
b z_arm64_serror
.cfi_endproc
/* Lower EL using AArch64 / Synchronous */
.align 7
z_arm64_ente... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:7 | b z_arm64_serror
.cfi_endproc
/* Lower EL using AArch32 / Synchronous */
.align 7
b .
/* Lower EL using AArch32 / IRQ */
.align 7
b .
/* Lower EL using AArch32 / FIQ */
.align 7
b .
/* Lower EL using AArch32 / SError */
.align 7
b .
GTEXT(z_arm64_serror)
SECTION_FUNC(TEXT, z_arm64_serror)
/*
* CFI:... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:8 | #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
GTEXT(z_arm64_quick_stack_check)
SECTION_FUNC(TEXT, z_arm64_quick_stack_check)
/*
* x0 is SP_EL1
* Retrieve the current stack limit
*/
get_cpu x16
ldr x17, [x16, #_cpu_offset_to_current_stack_limit]
/*
* If priv sp <= the stack limit, then keep the safe exception sta... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:9 | /*
* switch sp to safe exception stack, which means we handle the fatal
* error with safe exception stack.
*/
sub sp, x18, ___esf_t_SIZEOF
ret
#endif
/*
* Restore volatile registers, LR, SPSR_EL1 and ELR_EL1
*
* This is the common exit point for z_arm64_sync_exc() and _isr_wrapper().
*/
GTEXT(z_arm64_exit... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:10 | tst x0, #SPSR_MODE_MASK /* EL0 == 0 */
mrs x0, tpidrro_el0
mov x1, #TPIDRROEL0_EXC_UNIT
orr x2, x0, #TPIDRROEL0_IN_EL0
csel x0, x2, x0, eq
sub x0, x0, x1
msr tpidrro_el0, x0
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
bne 1f
ldr x0, [sp, ___esf_t_sp_el0_OFFSET]
msr sp_el0, x0
1:
#endif
ldp x0, x1, [sp, ___esf_... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/vector_table.S | 361 | 402 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:1 | /*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Populated vector table
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/offsets.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/arm64/tpidrro_el0.h>
#include <of... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:2 | #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
.if \el == el1
/*
* EL1t mode cannot access sp_el1, so set x0 to sp_el1 without corrupt
* other registers
*/
add sp, sp, x0 // sp' = sp + x0
sub x0, sp, x0 // x0' = sp' - x0 = sp
msr SPSel, #0
stp x16, x17, [sp, -(___esf_t_SIZEOF - ___esf_t_x16_x17_OFFSET)]
stp ... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:3 | stp \xreg0, \xreg1, [sp, ___esf_t_spsr_elr_OFFSET]
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
.if \el == el0
mrs x0, sp_el0
str x0, [sp, ___esf_t_sp_el0_OFFSET]
/* Retrieving safe exception stack */
get_cpu x0
ldr x1, [x0, #_cpu_offset_to_safe_exception_stack]
msr sp_el0, x1
.endif
#endif
/* Clear usermode fl... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:4 | *
* +------------------+------------------+-------------------------+
* | Address | Exception type | Description |
* +------------------+------------------+-------------------------+
* | VBAR_ELn + 0x000 | Synchronous | Current EL with SP0 |
* | + 0x080 | IRQ / vIRQ |... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:5 | #ifdef CONFIG_GEN_SW_ISR_TABLE
b _isr_wrapper
#else
b z_irq_spurious
#endif
/* Current EL with SP0 / FIQ */
.align 7
b .
/* Current EL with SP0 / SError */
.align 7
z_arm64_enter_exc x0, x1, el1
b z_arm64_serror
/* Current EL with SPx / Synchronous */
.align 7
z_arm64_enter_exc x0, x1, el1
b z_arm64_s... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:6 | z_arm64_enter_exc x0, x1, el0
b z_arm64_sync_exc
/* Lower EL using AArch64 / IRQ */
.align 7
z_arm64_enter_exc x0, x1, el0
#ifdef CONFIG_GEN_SW_ISR_TABLE
b _isr_wrapper
#else
b z_irq_spurious
#endif
/* Lower EL using AArch64 / FIQ */
.align 7
b .
/* Lower EL using AArch64 / SError */
.align 7
z_arm64_en... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:7 | mov x1, sp
mov x0, #0 /* K_ERR_CPU_EXCEPTION */
bl z_arm64_fatal_error
/* Return here only in case of recoverable error */
b z_arm64_exit_exc
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
GTEXT(z_arm64_quick_stack_check)
SECTION_FUNC(TEXT, z_arm64_quick_stack_check)
/*
* x0 is SP_EL1
* Retrieve the current stack ... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:8 | * exception stack
* x16 is still the current _cpu
*/
mrs x18, sp_el0
mov x17, sp
str x17, [x16, #_cpu_offset_to_corrupted_sp]
/*
* switch sp to safe exception stack, which means we handle the fatal
* error with safe exception stack.
*/
sub sp, x18, ___esf_t_SIZEOF
ret
#endif
/*
* Restore volatile regi... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm64/core/vector_table.S:9 | sub x0, x0, x1
msr tpidrro_el0, x0
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
bne 1f
ldr x0, [sp, ___esf_t_sp_el0_OFFSET]
msr sp_el0, x0
1:
#endif
ldp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
ldp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
ldp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
ldp x6, x7, [sp, ___esf_t_x6_x7_OFFSET]
ldp ... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm64/core/vector_table.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/vector_table.S | 321 | 356 |
zephyrproject-rtos/zephyr:arch/arm64/core/xen/hypercall.S:1 | /* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2021-2023 EPAM Systems
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/xen/public/arch-arm.h>
#include <zephyr/xen/public/xen.h>
#define HYPERCALL(hypercall) \
GTEXT(HYPERVISOR_##hypercall); \
SECTION_FUNC(TEXT, H... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/xen/hypercall.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm64/core/xen/hypercall.S | 1 | 32 |
zephyrproject-rtos/zephyr:arch/arm64/core/xen/hypercall.S:1 | /* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2021-2023 EPAM Systems
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/xen/public/arch-arm.h>
#include <zephyr/xen/public/xen.h>
#define HYPERCALL(hypercall) \
GTEXT(HYPERVISOR_##hypercall); \
SECTION_FUNC(TEXT, H... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/xen/hypercall.S | Apache-2.0 | eaaa5400dc29ce9c72cdfb8e6b16b1155e9294f7 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/eaaa5400dc29ce9c72cdfb8e6b16b1155e9294f7/arch/arm64/core/xen/hypercall.S | 1 | 31 |
zephyrproject-rtos/zephyr:arch/arm64/core/xen/hypercall.S:1 | /* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2021-2023 EPAM Systems
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/xen/public/arch-arm.h>
#include <zephyr/xen/public/xen.h>
#define HYPERCALL(hypercall) \
GTEXT(HYPERVISOR_##hypercall); \
SECTION_FUNC(TEXT, H... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/xen/hypercall.S | Apache-2.0 | 571f5b92a02c475cf55825b6c55ccb7e901d5d17 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/571f5b92a02c475cf55825b6c55ccb7e901d5d17/arch/arm64/core/xen/hypercall.S | 1 | 30 |
zephyrproject-rtos/zephyr:arch/arm64/core/xen/hypercall.S:1 | /* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2021-2023 EPAM Systems
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/xen/public/arch-arm.h>
#include <zephyr/xen/public/xen.h>
#define HYPERCALL(hypercall) \
GTEXT(HYPERVISOR_##hypercall); \
SECTION_FUNC(TEXT, H... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm64/core/xen/hypercall.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm64/core/xen/hypercall.S | 1 | 29 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:1 | /*
* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
*
* based on arch/riscv/core/isr.S and arch/nios2/core/exception.S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/kernel_structs.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include <mips/re... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:2 | op gp, ESF_O(gp)(sp) ;\
op AT, ESF_O(at)(sp) ;\
op t0, ESF_O(t0)(sp) ;\
op t1, ESF_O(t1)(sp) ;\
op t2, ESF_O(t2)(sp) ;\
op t3, ESF_O(t3)(sp) ;\
op t4, ESF_O(t4)(sp) ;\
op t5, ESF_O(t5)(sp) ;\
op t6, ESF_O(t6)(sp) ;\
op t7, ESF_O(t7)(sp) ;\
op t8, ESF_O(t8)(sp) ;\
op t9, ESF_O(t9)(sp) ;\
op a0, E... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:3 | SECTION_FUNC(exception.other, _mips_interrupt)
.set noat
/*
* Save caller-saved registers on current thread stack.
*/
STORE_CALLER_SAVED()
/* save CP0 registers */
mfhi t0
mflo t1
OP_STOREREG t0, ESF_O(hi)(sp)
OP_STOREREG t1, ESF_O(lo)(sp)
mfc0 t0, CP0_EPC
OP_STOREREG t0, ESF_O(epc)(sp)
mfc0 t1, CP0_BAD... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:4 | bnez k1, unhandled
/* cause IP_MASK != 0 ? */
bnez a0, is_interrupt
unhandled:
move a0, sp
jal z_mips_fault
eret
is_kernel_syscall:
/*
* A syscall is the result of an syscall instruction, in which case the
* EPC will contain the address of the syscall instruction.
* Increment saved EPC by 4 to prevent tr... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:5 | */
j reschedule
is_interrupt:
/*
* Save current thread stack pointer and switch
* stack pointer to interrupt stack.
*/
/* Save thread stack pointer to temp register k0 */
move k0, sp
/* Switch to interrupt stack */
la k1, _kernel
OP_LOADREG sp, _kernel_offset_to_irq_stack(k1)
/*
* Save thread stack ... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:6 | /*
* Check if next thread to schedule is current thread.
* If yes do not perform a reschedule
*/
OP_LOADREG t3, _kernel_offset_to_ready_q_cache(k1)
beq t3, t2, no_reschedule
#else
j no_reschedule
#endif /* CONFIG_PREEMPT_ENABLED */
reschedule:
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
jal z_thread_mark_switc... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:7 | skip_callee_saved_reg:
/*
* Save stack pointer of current thread and set the default return value
* of z_swap to _errno_neg_eagain for the thread.
*/
OP_STOREREG sp, _thread_offset_to_sp(t1)
la t2, _errno_neg_eagain
lw t3, 0(t2)
sw t3, _thread_offset_to_swap_return_value(t1)
/* Get next thread to schedule... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/isr.S | 241 | 289 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:2 | op gp, ESF_O(gp)(sp) ;\
op AT, ESF_O(at)(sp) ;\
op t0, ESF_O(t0)(sp) ;\
op t1, ESF_O(t1)(sp) ;\
op t2, ESF_O(t2)(sp) ;\
op t3, ESF_O(t3)(sp) ;\
op t4, ESF_O(t4)(sp) ;\
op t5, ESF_O(t5)(sp) ;\
op t6, ESF_O(t6)(sp) ;\
op t7, ESF_O(t7)(sp) ;\
op t8, ESF_O(t8)(sp) ;\
op t9, ESF_O(t9)(sp) ;\
op a0, E... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/mips/core/isr.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:6 | /*
* Check if next thread to schedule is current thread.
* If yes do not perform a reschedule
*/
OP_LOADREG t3, _kernel_offset_to_ready_q_cache(k1)
beq t3, t2, no_reschedule
#else
j no_reschedule
#endif /* CONFIG_PREEMPT_ENABLED */
reschedule:
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
jal z_thread_mark_switc... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/mips/core/isr.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/mips/core/isr.S:7 | skip_callee_saved_reg:
/*
* Save stack pointer of current thread and set the default return value
* of z_swap to _k_neg_eagain for the thread.
*/
OP_STOREREG sp, _thread_offset_to_sp(t1)
la t2, _k_neg_eagain
lw t3, 0(t2)
sw t3, _thread_offset_to_swap_return_value(t1)
/* Get next thread to schedule. */
OP... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/isr.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/mips/core/isr.S | 241 | 289 |
zephyrproject-rtos/zephyr:arch/mips/core/reset.S:1 | /*
* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <mips/regdef.h>
#include <mips/mipsregs.h>
GTEXT(__initialize)
GTEXT(__stack)
GTEXT(z_prep_c)
/*
* Remainder of asm-land initializ... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/reset.S | 1 | 57 |
zephyrproject-rtos/zephyr:arch/mips/core/swap.S:1 | /*
* Copyright (c) 2020, 2021 Antony Pavlov <antonynpavlov@gmail.com>
*
* based on arch/riscv/core/swap.S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include <mips/regdef.h>
/*
* unsigned int arch_swap(unsigned int key)
*
*... | mips | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/mips/core/swap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/mips/core/swap.S | 1 | 48 |
zephyrproject-rtos/zephyr:arch/openrisc/core/asm_macros.inc:1 | /*
* Copyright (c) 2025 NVIDIA Corporation
*
* Convenience macros for assembly code
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Convenience macros for assembly code. */
/*
* Helper macro which stores the value of a register to a the address contained
* in a pointer register plus an immediate offset.
*/
.... | arm | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/asm_macros.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/asm_macros.inc | 1 | 29 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:1 | /*
* Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <offsets_short.h>
#include <openrisc/openriscregs.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/openrisc/syscall.h>
#include <zephyr/kernel_structs.h>
#include <zephyr/linker/sections.h>
... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:2 | */
.altmacro
.macro zero_regs first=0, last=31
l.movhi r\first, 0
.if \last-\first
zero_regs %first+1, \last
.endif
.endm
/*
* Calls a given function, and sets the return address to return to another
* location.
*/
.macro chain_call proc1, proc2
l.movhi r9, hi(\proc2)
#ifdef __OR1K_NODELAY__
l.ori r9, r9, lo... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:3 | l.ori r9, r9, lo(\proc2)
#endif
.endm
/*
* Helper macro which loads or stores all caller-saved registers to the stack.
*/
.macro do_caller_saved op
\op r3, ESF_O(r3), r1
\op r4, ESF_O(r4), r1
\op r5, ESF_O(r5), r1
\op r6, ESF_O(r6), r1
\op r7, ESF_O(r7), r1
\op r8, ESF_O(r8), r1
\op r11, ESF_O(r11), r1
\op... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:4 | /*
* Loads all caller-saved registers from the stack.
*/
.macro load_caller_saved
do_caller_saved op_load_reg
.endm
/*
* Stores the values of the ESR and EPCR registers into the est_t structure
* pointed at by the r1 stack pointer.
*
* Modifies: r15
*/
.macro store_esr_epcr
/* Save ESR */
l.mfspr r15, r0,... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:5 | l.lwz r15, ESF_O(epcr)(r1)
l.mtspr r0, r15, SPR_EPCR_BASE
.endm
/*
* Stores the values of the MAC registers into the est_t structure pointed at
* by the r1 stack pointer.
*
* Modifies: r15
*/
.macro store_mac
l.mfspr r15, r0, SPR_MACLO
l.sw ESF_O(mac_lo)(r1), r15
l.mfspr r15, r0, SPR_MACHI
l.sw ESF_O(mac_h... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:6 | .global _\label
.org ((\num) * 0x100)
_\label\():
.endm
/*
* Saves r9 on the current stack.
*/
.macro push_r9
l.addi r1, r1, -4
l.sw 0(r1), r9
.endm
/*
* Restores r9 from the current stack.
*/
.macro pop_r9
l.lwz r9, 0(r1)
l.addi r1, r1, 4
.endm
/*
* Increments or decrements the _cpu->nested counter.... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:7 | /*
* Gets the current CPU structure.
* Loads the IRQ stack pointer, and updates the nested IRQ counter.
*
* Modifies: dst
*/
.macro get_current_cpu dst
l.movhi \dst, hi(_kernel + ___kernel_t_cpus_OFFSET)
l.ori \dst, \dst, lo(_kernel + ___kernel_t_cpus_OFFSET)
.endm
/*
* Loads the IRQ stack pointer, and updat... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:8 | l.addi r1, r1, -4
l.sw 0(r1), r17
1:
.endm
/*
* Common head code required by all exception handler.
*/
.macro exception_handler_head
/* Allocate esf_t on the stack */
l.addi r1, r1, lo(-__struct_arch_esf_SIZEOF)
/* Store caller-saved, exception and MAC registers */
store_caller_saved
store_esr_epcr
store_... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:9 | .macro error_handler_tail num
/* Call z_openrisc_fault with the esf and reason arguments */
l.ori r3, r1, 0
#ifdef __OR1K_NODELAY__
l.ori r4, r0, \num
l.jal z_openrisc_fault
#else
l.jal z_openrisc_fault
l.ori r4, r0, \num
#endif
/* Halt */
l.j .
#ifndef __OR1K_NODELAY__
l.nop
#endif
.endm
/*
* Implement... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:10 | l.jal soc_reset_hook
#ifndef __OR1K_NODELAY__
l.nop
#endif
#endif
#ifdef CONFIG_INIT_STACKS
/* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
l.movhi r14, hi(z_interrupt_stacks)
l.ori r14, r14, lo(z_interrupt_stacks)
l.addi r16, r14, __z_interrupt_all_stacks_SIZEOF
l.movhi r18, 0xAAAA
l.ori r18, r1... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:11 | /*
* Handles exception errors
*/
.macro exception_error num, label
exception_label \num, \label
exception_handler_head
error_handler_tail \num
.endm
/*
* Handles Tick Timer Exception.
*
* Saves register state, then implements tick-timer handling functionality
* then hands off to _isr_tail to implemented shar... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:12 | /* Call to z_openrisc_handle_irqs and return to _isr_tail. */
chain_call z_openrisc_handle_irqs, _isr_tail
.endm
/*
* Handles syscalls
*/
.macro exception_syscall
exception_label 0xC, syscall
exception_handler_head
#ifdef CONFIG_IRQ_OFFLOAD
/* Determine what to do. Operation code is in r11 */
l.sfeqi r11, OR_... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:13 | #endif
.endm
SECTION_FUNC(exceptions, _exceptions)
SECTION_SUBSEC_FUNC(exceptions, _reset_and__start, __reset)
SECTION_SUBSEC_FUNC(exceptions, _reset_and__start, __start)
l.j _reset
/* Reset */
exception_reset
/* Bus Error */
exception_error 0x2, bus_error
/* Data Page Fault */
exception_error 0x3, data_page_faul... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:14 | exception_error 0xB, range_exception
/* System Call */
exception_syscall
/* Floating Point Exception */
exception_error 0xD, floating_point_exception
/* Trap */
exception_error 0xE, trap_exception
/*
* Common interrupt handler tail routine.
*
* This routing implements common interrupt handler tail behaviour, sh... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:15 | retain_irq_stack:
#if defined(CONFIG_MULTITHREADING)
/* Save temporary registers */
l.addi r1, r1, -8
l.sw 0(r1), r9
l.sw 4(r1), r14
check_reschedule:
/*
* Load the address of the current k_thread from the current cpu_t for use by
* z_openrisc_switch
*/
get_current_cpu r14
l.lwz r14, ___cpu_t_current_OFFS... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/openrisc/core/exception.S:16 | l.jal z_openrisc_switch
#else
l.jal z_openrisc_switch
l.ori r4, r14, 0
#endif
no_reschedule:
#endif
/* Restore temporary registers */
#if defined(CONFIG_MULTITHREADING)
l.lwz r9, 0(r1)
l.lwz r14, 4(r1)
l.addi r1, r1, 8
#elif defined(CONFIG_STACK_SENTINEL)
l.lwz r9, 0(r1)
l.addi r1, r1, 4
#endif
z_openrisc_... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/exception.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/exception.S | 601 | 631 |
zephyrproject-rtos/zephyr:arch/openrisc/core/switch.S:1 | /*
* Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include "asm_macros.inc"
#define THREAD_O(FIELD) _thread_offset_to_##FIELD
.macro do_callee_saved op, reg
... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/switch.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/openrisc/core/switch.S:2 | SECTION_FUNC(TEXT, z_openrisc_switch)
/* Save the old thread's callee-saved registers */
store_callee_saved r4
/* Save the old thread's stack pointer */
l.sw _thread_offset_to_r1(r4), r1
/* Set thread->switch_handle = thread to mark completion */
l.sw ___thread_t_switch_handle_OFFSET(r4), r4
/* Get the new t... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/openrisc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/openrisc/core/switch.S | 41 | 74 |
zephyrproject-rtos/zephyr:arch/riscv/core/asm_macros.inc:1 | /*
* Assembly macros and helpers
*
* Copyright (c) 2022 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifdef CONFIG_64BIT
/* register-wide load/store based on ld/sd (XLEN = 64) */
.macro lr, rd, mem
ld \rd, \mem
.endm
.macro sr, rs, mem
sd \rs, \mem
.endm
#else
/* register-wide load/store b... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/asm_macros.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/asm_macros.inc | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/asm_macros.inc:2 | .endm
#else
.macro flr, rd, mem
flw \rd, \mem
.endm
.macro fsr, rs, mem
fsw \rs, \mem
.endm
#endif
/*
* Perform rd += rs * mult using only shifts and adds.
* Useful when the mul instruction isn't available.
* mult must be a constant. rs will be clobbered.
*/
.macro shiftmul_add rd, rs, mult
beqz ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/asm_macros.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/asm_macros.inc | 41 | 87 |
zephyrproject-rtos/zephyr:arch/riscv/core/fpu.S:1 | /*
* Copyright (c) 2023 BayLibre SAS
* Written by: Nicolas Pitre
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/offsets.h>
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
#define LOAD fld
#define STORE fsd
#else
#define LOAD flw
#define ST... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/fpu.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/fpu.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/fpu.S:2 | op ft0, __z_riscv_fp_context_t_ft0_OFFSET (ptr); \
op ft1, __z_riscv_fp_context_t_ft1_OFFSET (ptr); \
op ft2, __z_riscv_fp_context_t_ft2_OFFSET (ptr); \
op ft3, __z_riscv_fp_context_t_ft3_OFFSET (ptr); \
op ft4, __z_riscv_fp_context_t_ft4_OFFSET (ptr); \
op ft5, __z_riscv_fp_context_t_ft5_OFFSET (ptr); \
op... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/fpu.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/fpu.S | 41 | 68 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:2 | * kernel context uses ebreak (cause=3, breakpoint) which IS delegated to
* S-mode. The is_kernel_syscall handler below recognises this via t0==0
* (RV_ECALL_RUNTIME_EXCEPT) and reads the reason from saved a0.
*/
#define EXC_SYSCALL RISCV_EXC_BREAKPOINT
#else
#define RV_SCRATCH mscratch
#define RV_CAUSE mcaus... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:3 | * Note: s0 is callee-saved and the exception entry code already saved it
* in struct arch_esf so it could be used as the current CPU pointer.
* Also stores address of csf to the esf. Clobbers t0.
*/
#define STORE_CALLEE_SAVED(esf) \
lr t0, __struct_arch_esf_s0_OFFSET(esf);\
RV_E( sr t0, ___callee_saved_t_s0_OFFSE... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:4 | GTEXT(z_get_next_switch_handle)
GTEXT(z_riscv_switch)
GTEXT(z_riscv_thread_start)
#ifdef CONFIG_TRACING
GTEXT(sys_trace_isr_enter)
GTEXT(sys_trace_isr_exit)
#endif
#ifdef CONFIG_USERSPACE
GDATA(_k_syscall_table)
#endif
#ifdef CONFIG_RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
GTEXT(__soc_handle_all_irqs)
#endif
#ifdef CONFIG... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:5 | * - __soc_handle_irq: handle SoC-specific details for a pending IRQ
* (e.g. clear a pending bit in a SoC-specific register)
*
* If CONFIG_RISCV_SOC_CONTEXT_SAVE=y, calls to SoC-level context save/restore
* routines are also made here. For details, see the Kconfig help text.
*/
/*
* Handler called upon ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:6 | lr tp, _thread_offset_to_tls(t0)
/* Make sure global pointer is sane */
#ifdef CONFIG_RISCV_GP
.option push
.option norelax
la gp, __global_pointer$
.option pop
#elif defined(CONFIG_RISCV_CURRENT_VIA_GP)
lr gp, ___cpu_t_current_OFFSET(s0)
#endif /* CONFIG_RISCV_GP / CONFIG_RISCV_CURRENT_VIA_GP */
/* Clear our ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:7 | sr t0, __struct_arch_esf_mcause_OFFSET(sp)
#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
/* Save RV_EPC register */
csrr t0, RV_EPC
sr t0, __struct_arch_esf_mepc_OFFSET(sp)
/* Save RV_STATUS register */
csrr t2, RV_STATUS
sr t2, __struct_arch_esf_mstatus_OFFSET(sp)
#if defined(CONFIG_FPU_SHARING)
/* determ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:8 | * 1001011 = NMSUB
* 1001111 = NMADD
* 1010011 = OP-FP
*/
xori t1, t0, 0b1010011 /* OP-FP */
beqz t1, is_fp
ori t1, t0, 0b0100000
xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
beqz t1, is_fp
ori t1, t0, 0b0001100
xori t1, t1, 0b1001111 /* MADD / MSUB / NMSUB / NMADD */
beqz t1, is_fp
/*
* The FRCSR,... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:9 | * 011...........10 = C.FLWSPP RV32 (RV64/128 = C.LDSP)
* 101...........00 = C.FSD RV32/64 (RV128 = C.SQ)
* 101...........10 = C.FSDSP RV32/64 (RV128 = C.SQSP)
* 111...........00 = C.FSW RV32 (RV64/128 = C.SD)
* 111...........10 = C.FSWSP RV32 (RV64/128 = C.SDSP)
*
* so must be .01........ | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:10 | /*
* Check if exception is the result of an interrupt or not.
* Following the RISC-V architecture spec, the MSB
* of the RV_CAUSE register is used to indicate whether an exception
* is the result of an interrupt or an exception/fault.
*/
csrr t0, RV_CAUSE
bltz t0, is_interrupt
/*
* If the exception is t... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:11 | 1:
#endif /* CONFIG_CUSTOM_STACK_GUARD */
/*
* If RV_CAUSE == RISCV_EXC_ECALLU, handle system call
* for user mode thread.
*/
li t1, RISCV_EXC_ECALLU
beq t0, t1, is_user_syscall
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
/*
* Determine if we come from user space. If so, reconfigure the PMP for
* kernel mode ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:12 | /* Restore SP if z_riscv_fault returns before jumping to no_reschedule */
addi sp, sp, __callee_saved_t_SIZEOF
j no_reschedule
#else
la ra, no_reschedule
tail z_riscv_fault
#endif /* CONFIG_EXCEPTION_DEBUG */
is_kernel_syscall:
/*
* A syscall is the result of an ecall instruction, in which case the
* RV_EPC ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | beq t0, t1, do_irq_offload
#endif
#ifdef CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL
li t1, RV_ECALL_SCHEDULE
bne t0, t1, skip_schedule
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
#ifdef CONFIG_FPU_SHARING
/*
* When an ECALL is used for a context-switch, the current thread has
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | #endif /* CONFIG_EXCEPTION_DEBUG */
call z_riscv_fatal_error
j check_reschedule
#if defined(CONFIG_IRQ_OFFLOAD)
do_irq_offload:
/*
* Retrieve provided routine and argument from the stack.
* Routine pointer is in saved a0, argument in saved a1
* so we load them with a1/a0 (reversed).
*/
lr a1, __struct_arch... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:15 | */
lr t0, 0(sp)
lr a1, __struct_arch_esf_a0_OFFSET(t0)
lr a0, __struct_arch_esf_a1_OFFSET(t0)
#endif /* CONFIG_CUSTOM_STACK_GUARD */
1:
/* Execute provided routine (argument is in a0 already). */
jalr ra, a1, 0
/* Leave through the regular IRQ exit path */
j irq_done
#endif /* CONFIG_IRQ_OFFLOAD */
#ifdef CON... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:16 | lr a2, __struct_arch_esf_a2_OFFSET(sp)
lr a3, __struct_arch_esf_a3_OFFSET(sp)
lr a4, __struct_arch_esf_a4_OFFSET(sp)
lr a5, __struct_arch_esf_a5_OFFSET(sp)
lr t0, __struct_arch_esf_t0_OFFSET(sp)
#if defined(CONFIG_RISCV_ISA_RV32E)
/* Stack alignment for RV32E is 4 bytes */
addi sp, sp, -4
mv t1, sp
sw t1, 0(sp)... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:17 | /* Disable IRQs again before leaving */
csrc RV_STATUS, STATUS_IE
j might_have_rescheduled
#endif /* CONFIG_USERSPACE */
is_interrupt:
#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
#ifdef CONFIG_USERSPACE
/*
* If we came from userspace then we need to reconfigure the
* PMP for kernel mode configuration.
*/
lr t0, _... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:18 | /* Disable the custom stack guard */
call z_riscv_custom_stack_guard_disable
#endif /* CONFIG_CUSTOM_STACK_GUARD */
/* Switch to interrupt stack */
mv t0, sp
lr sp, ___cpu_t_irq_stack_OFFSET(s0)
/*
* Save thread stack pointer on interrupt stack
* In RISC-V, stack pointer needs to be 16-byte aligned
*/
add... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:19 | jal ra, __soc_handle_irq
#if defined CONFIG_GEN_SW_ISR_TABLE
/*
* Call corresponding registered function in _sw_isr_table.
* (table is 2-word wide, we should shift index accordingly)
*/
la t0, _sw_isr_table
slli a0, a0, (RV_REGSHIFT + 1)
add t0, t0, a0
/* Load argument in a0 register */
lr a0, 0(t0)
/* ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:20 | /* Disable the custom stack guard for interrupt stack */
call z_riscv_custom_stack_guard_disable
#endif /* CONFIG_CUSTOM_STACK_GUARD */
/* nested count is back to 0: Return to thread stack */
lr sp, 0(sp)
#ifdef CONFIG_CUSTOM_STACK_GUARD
/* Enable the custom stack guard for thread stack */
lr a0, ___cpu_t_curren... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 761 | 820 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:21 | * Perform context switch:
* a0 = new thread
* a1 = old thread
*/
call z_riscv_switch
z_riscv_thread_start:
might_have_rescheduled:
/* reload s0 with &_current_cpu as it might have changed or be unset */
get_current_cpu s0
#endif /* CONFIG_MULTITHREADING */
no_reschedule:
#ifdef CONFIG_RISCV_SOC_CONTEXT_SA... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 801 | 860 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:22 | /* Restore RV_CAUSE register for previous interrupt level. */
lr t1, __struct_arch_esf_mcause_OFFSET(sp)
csrw RV_CAUSE, t1
#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
csrw RV_EPC, t0
csrw RV_STATUS, t2
#ifdef CONFIG_USERSPACE
/*
* Check if we are returning to user mode. If so then we must
* set is_user_... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 841 | 900 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:23 | 1:
/*
* We are returning to kernel mode. Store the stack pointer to
* be re-loaded further down.
*/
addi t0, sp, __struct_arch_esf_SIZEOF
sr t0, __struct_arch_esf_sp_OFFSET(sp)
2:
#endif
/* Restore s0 (it is no longer ours) */
lr s0, __struct_arch_esf_s0_OFFSET(sp)
#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/isr.S | 881 | 910 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:1 | /*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Copyright (c) 2018 Foundries.io Ltd
* Copyright (c) 2020 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:2 | RV_I( op a7, __struct_arch_esf_a7_OFFSET(sp) );\
RV_E( op ra, __struct_arch_esf_ra_OFFSET(sp) )
#ifdef CONFIG_EXCEPTION_DEBUG
/*
* Convenience macro for storing callee saved register [s0 - s11] states.
* Note: s0 is callee-saved and the exception entry code already saved it
* in struct arch_esf so it could be used... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:3 | #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
GTEXT(z_riscv_fatal_error)
GTEXT(z_get_next_switch_handle)
GTEXT(z_riscv_switch)
GTEXT(z_riscv_thread_start)
#ifdef CONFIG_TRACING
GTEXT(sys_trace_isr_enter)
GTEXT(sys_trace_isr_exit)... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:4 | *
* Since RISC-V does not completely prescribe IRQ handling behavior,
* implementations vary (some implementations also deviate from
* what standard behavior is defined). Hence, the arch level code expects
* the following functions to be provided at the SOC level:
*
* - __soc_handle_irq: handle SoC-specific d... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:5 | * can't overflow the privileged stack. The esf will be allocated
* later but it is safe to store our saved user sp here. */
sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp)
/* Make sure tls pointer is sane */
lr t0, ___cpu_t_current_OFFSET(s0)
lr tp, _thread_offset_to_tls(t0)
/* Make sure g... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:6 | sr s0, __struct_arch_esf_s0_OFFSET(sp)
get_current_cpu s0
#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
/* Save mcause register */
csrr t0, mcause
sr t0, __struct_arch_esf_mcause_OFFSET(sp)
#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
/* Save MEPC register */
csrr t0, mepc
sr t0, __struct_arch_esf_mepc_OFFSET... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:7 | /*
* Major FP opcodes:
* 0000111 = LOAD-FP
* 0100111 = STORE-FP
* 1000011 = MADD
* 1000111 = MSUB
* 1001011 = NMSUB
* 1001111 = NMADD
* 1010011 = OP-FP
*/
xori t1, t0, 0b1010011 /* OP-FP */
beqz t1, is_fp
ori t1, t0, 0b0100000
xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
beqz t1, is_fp
ori ... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:8 | andi t1, t2, 1
bnez t1, no_fp
/*
* 001...........00 = C.FLD RV32/64 (RV128 = C.LQ)
* 001...........10 = C.FLDSP RV32/64 (RV128 = C.LQSP)
* 011...........00 = C.FLW RV32 (RV64/128 = C.LD)
* 011...........10 = C.FLWSPP RV32 (RV64/128 = C.LDSP)
* 101...........00 = C.FSD RV32/64 (RV128 = C... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:9 | #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Handle context saving at SOC level. */
addi a0, sp, __struct_arch_esf_soc_context_OFFSET
jal ra, __soc_save_context
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
/*
* Check if exception is the result of an interrupt or not.
* (SOC dependent). Following the RISC-V architectu... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:10 | and t1, t1, t2
bnez t1, 1f
lr a0, ___cpu_t_current_OFFSET(s0)
call z_riscv_custom_stack_guard_enable
1:
#endif /* CONFIG_CUSTOM_STACK_GUARD */
/*
* If mcause == RISCV_EXC_ECALLU, handle system call
* for user mode thread.
*/
li t1, RISCV_EXC_ECALLU
beq t0, t1, is_user_syscall
#ifdef CONFIG_PMP_KERNEL_MODE... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:11 | addi sp, sp, -__callee_saved_t_SIZEOF
STORE_CALLEE_SAVED(a0)
call z_riscv_fault
/* Restore SP if z_riscv_fault returns before jumping to no_reschedule */
addi sp, sp, __callee_saved_t_SIZEOF
j no_reschedule
#else
la ra, no_reschedule
tail z_riscv_fault
#endif /* CONFIG_EXCEPTION_DEBUG */
is_kernel_syscall:
... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:12 | beqz t0, do_fault
#if defined(CONFIG_IRQ_OFFLOAD)
li t1, RV_ECALL_IRQ_OFFLOAD
beq t0, t1, do_irq_offload
#endif
#ifdef CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL
li t1, RV_ECALL_SCHEDULE
bne t0, t1, skip_schedule
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
#ifdef CONFIG_FPU_SHAR... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:13 | #ifdef CONFIG_EXCEPTION_DEBUG
addi sp, sp, -__callee_saved_t_SIZEOF
STORE_CALLEE_SAVED(a1)
#endif /* CONFIG_EXCEPTION_DEBUG */
call z_riscv_fatal_error
j check_reschedule
#if defined(CONFIG_IRQ_OFFLOAD)
do_irq_offload:
/*
* Retrieve provided routine and argument from the stack.
* Routine pointer is in saved a... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/riscv/core/isr.S:14 | call z_riscv_custom_stack_guard_enable
/*
* Reload the routine and argument from the stack, since the custom
* stack guard hook clobbers a0 and a1.
*/
lr t0, 0(sp)
lr a1, __struct_arch_esf_a0_OFFSET(t0)
lr a0, __struct_arch_esf_a1_OFFSET(t0)
#endif /* CONFIG_CUSTOM_STACK_GUARD */
1:
/* Execute provided rout... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/isr.S | Apache-2.0 | 26af854046c533bc50069ebff9eb56176d4b9edc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/26af854046c533bc50069ebff9eb56176d4b9edc/arch/riscv/core/isr.S | 521 | 580 |
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