id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:2 | /* Generate a rotated (modulo NREGS/4 bits!) WINDOWSTART in A2
* by duplicating the bits twice and shifting down by WINDOWBASE
* bits. Now the LSB is the register quad at WINDOWBASE.
*/
rsr a2, WINDOWSTART
slli a3, a2, (XCHAL_NUM_AREGS / 4)
or a2, a2, a3
rsr a3, WINDOWBASE
ssr a3
srl a2, a2
mov a3, a1 /*... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:3 | _high_gpr_spill_done:
/* Push the original stack pointer so we know at restore
* time how many registers were spilled, then return, leaving the
* modified SP in A1.
*/
addi a1, a1, -4
s32i a3, a1, 0
ret
/*
* xtensa_restore_high_regs
*
* Does the inverse of xtensa_save_high_regs, taking a stack pointer
*... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:4 | beq a1, a2, _high_restore_done
addi a2, a2, -16
l32i a12, a2, 0
l32i a13, a2, 4
l32i a14, a2, 8
l32i a15, a2, 12
_high_restore_done:
mov a1, a3 /* Original stack */
ret
/*
* _restore_context
*
* Arrive here via a jump. Enters into the restored context and does
* not return. A1 should have a context point... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:5 | * instead of the one in the thread stack.
* Both scenarios will have nested value of 0.
*/
rsr.ZSR_CPU a2
l32i a0, a2, ___cpu_t_nested_OFFSET
bnez a0, _restore_ps_from_stack
l32i a0, a2, ___cpu_t_current_OFFSET
l32i a0, a0, _thread_offset_to_return_ps
wsr a0, ZSR_EPS
j _restore_ps_after
_restore_ps_from_s... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:6 | rfi ZSR_RFI_LEVEL
/*
* void xtensa_arch_except(int reason_p);
*
* Implements hardware exception for Xtensa ARCH_EXCEPT to save
* interrupted stack frame and reason_p for use in exception handler
* and coredump
*/
.global xtensa_arch_except
.global xtensa_arch_except_epc
.align 4
xtensa_arch_except:
entry a1, 16... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:7 | .align 4
xtensa_switch:
#ifdef CONFIG_USERSPACE
entry a1, 32
s32i a4, a1, 0
s32i a5, a1, 4
s32i a6, a1, 8
s32i a7, a1, 12
rsr a6, ZSR_CPU
l32i a6, a6, ___cpu_t_current_OFFSET
#ifdef CONFIG_XTENSA_MMU
#ifdef CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP
call4 xtensa_swap_update_page_tables
#else
SWAP_PAGE_... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:8 | s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
ODD_REG_SAVE a0, a1
#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
FPU_REG_SAVE
#endif
/* Stash our PS register contents and a "restore" PC. */
rsr a0... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:9 | #if defined(CONFIG_KERNEL_COHERENCE) && !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
/* Flush the stack. The top of stack was stored for us by
* arch_cohere_stacks(). It can be NULL for a dummy thread.
*/
rsync
rsr a0, ZSR_FLUSH
beqz a0, noflush
mov a3, a1
flushloop:
dhwb a3, 0
addi a3, a3, XCHAL_DCACHE_LINESI... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:11 | #endif
#endif
#if MAX_INTR_LEVEL >= 5
#if !(defined(CONFIG_GDBSTUB) && (XCHAL_DEBUGLEVEL == 5))
DEF_EXCINT 5, _handle_excint, xtensa_int5_c
#endif
#endif
#if MAX_INTR_LEVEL >= 6
#if !(defined(CONFIG_GDBSTUB) && (XCHAL_DEBUGLEVEL == 6))
DEF_EXCINT 6, _handle_excint, xtensa_int6_c
#endif
#endif
#if MAX_INTR_LEVEL >= 7... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:12 | wsr a0, ZSR_A0SAVE
rsync
rsr.exccause a0
#ifdef CONFIG_XTENSA_MMU
beqi a0, EXCCAUSE_ITLB_MISS, _handle_tlb_miss_user
#endif /* CONFIG_XTENSA_MMU */
#ifdef CONFIG_USERSPACE
beqi a0, EXCCAUSE_SYSCALL, _syscall
#endif /* CONFIG_USERSPACE */
#ifdef CONFIG_XTENSA_MMU
addi a0, a0, -EXCCAUSE_DTLB_MISS
beqz a0, _handle_t... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:13 | #ifdef CONFIG_USERSPACE
_syscall:
rsr a0, ZSR_A0SAVE
j xtensa_do_syscall
#endif /* CONFIG_USERSPACE */
.popsection
/* In theory you can have levels up to 15, but known hardware only uses 7. */
#if XCHAL_NMILEVEL > 7
#error More interrupts than expected.
#endif
/* We don't actually use "kernel mode" currently. Popu... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:14 | #endif
.popsection
#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
.pushsection .DoubleExceptionVector.text, "ax"
.global _DoubleExceptionVector
_DoubleExceptionVector:
#ifdef CONFIG_XTENSA_MMU
wsr a0, ZSR_DBLEXC
rsync
rsr.exccause a0
addi a0, a0, -EXCCAUSE_DTLB_MISS
beqz a0, _handle_tlb_miss_dblexc
/* Need to stash the D... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:15 | * simulator so that traces will not have infinite iterations of
* jumps.
*/
movi a3, 1
movi a2, SYS_exit
simcall
#endif
1:
j 1b
#ifdef CONFIG_XTENSA_MMU
_handle_tlb_miss_dblexc:
/* Handle all data TLB misses here.
* These data TLB misses are mostly caused by preloading
* page table entries in the level 1 ex... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_asm2_util.S | 561 | 592 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:9 | #if defined(CONFIG_KERNEL_COHERENCE) && !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
/* Flush the stack. The top of stack was stored for us by
* arch_cohere_stacks(). It can be NULL for a dummy thread.
*/
rsync
rsr a0, ZSR_FLUSH
beqz a0, noflush
mov a3, a1
flushloop:
dhwb a3, 0
addi a3, a3, XCHAL_DCACHE_LINESI... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/core/xtensa_asm2_util.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_asm2_util.S:15 | * simulator so that traces will not have infinite iterations of
* jumps.
*/
movi a3, 1
movi a2, SYS_exit
simcall
#endif
1:
j 1b
#ifdef CONFIG_XTENSA_MMU
_handle_tlb_miss_dblexc:
/* Handle all data TLB misses here.
* These data TLB misses are mostly caused by preloading
* page table entries in the level 1 ex... | x86_64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_asm2_util.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/xtensa/core/xtensa_asm2_util.S | 561 | 588 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_hifi.S:1 | /*
* Copyright (c) 2024 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <xtensa/config/tie.h>
#include <xtensa/config/tie-asm.h>
#if defined(CONFIG_XTENSA_EAGER_HIFI_SHARING)
/*
* Load the HiFi registers from the hifi buffer in the BSA. Round the address
* of t... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_hifi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_hifi.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/xtensa/core/xtensa_hifi.S:2 | * A1 - address of BSA (do not modify)
* A2 - available for use
* A3 - available for use
*/
.global _xtensa_hifi_save
.align 4
_xtensa_hifi_save:
addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
movi a3, ~(XCHAL_CP1_SA_ALIGN - 1)
and a2, a2, a3
xchal_cp1_store a... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/xtensa/core/xtensa_hifi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/core/xtensa_hifi.S | 41 | 83 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:2 | *
* - More easily maintained if changes are needed to window over/underflow
* exception handling.
*
* - Requires no scratch registers to do its work, so can be used safely in any
* context.
*
* - If the WOE bit is not enabled (for example, in code written for
* the CALL0 ABI), this becomes a silent noop a... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:3 | and a12, a12, a12
rotw 3
and a12, a12, a12
rotw 3
and a12, a12, a12
rotw 4
#elif XCHAL_NUM_AREGS == 32
and a12, a12, a12
rotw 3
and a12, a12, a12
rotw 3
and a4, a4, a4
rotw 2
#else
#error Unrecognized XCHAL_NUM_AREGS
#endif
.endm
#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:4 | ssi f7, a1, ___xtensa_irq_bsa_t_fpu7_OFFSET
ssi f8, a1, ___xtensa_irq_bsa_t_fpu8_OFFSET
ssi f9, a1, ___xtensa_irq_bsa_t_fpu9_OFFSET
ssi f10, a1, ___xtensa_irq_bsa_t_fpu10_OFFSET
ssi f11, a1, ___xtensa_irq_bsa_t_fpu11_OFFSET
ssi f12, a1, ___xtensa_irq_bsa_t_fpu12_OFFSET
ssi f13, a1, ___xtensa_irq_bsa_t_fpu13_OFFSE... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:5 | * On exit, the scratch register specified by parameter SCRATCH_REG
* will have been modified, and the shift/loop instructions can be
* used freely (though note loops don't work in exceptions for other
* reasons!).
*
* Does not populate or modify the PS/PC save locations.
*/
.macro ODD_REG_SAVE SCRATCH_REG, BSA_PT... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:6 | *
* Does not restore the PS/PC save locations.
*/
.macro ODD_REG_RESTORE SCRATCH_REG, BSA_PTR
l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_sar_OFFSET
wsr.sar \SCRATCH_REG
#if XCHAL_HAVE_LOOPS
l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lbeg_OFFSET
wsr.lbeg \SCRATCH_REG
l32i \SCRATCH_REG, \BSA_PTR, ___xt... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:7 | */
.macro SWAP_PAGE_TABLE THREAD_PTR_REG, SC1_REG, SC2_REG
l32i \THREAD_PTR_REG, \THREAD_PTR_REG, _thread_offset_to_mem_domain
j _swap_page_table_\@
.align 16
_swap_page_table_\@:
l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptevaddr
l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:9 | * Enter this macro with a valid "context saved" pointer (i.e. SP
* should point to a stored pointer which points to one BSA below the
* interrupted/old stack) in A1, a handler function in A2, and a "new"
* stack pointer (i.e. a pointer to the word ABOVE the allocated stack
* area) in A3. Exceptions should be enabl... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:10 | /* We want an ENTRY to set a bit in windowstart and do the
* rotation, but we want our own SP. After that, we are
* running in a valid frame, so re-enable interrupts.
*/
entry a1, 16
mov a1, a2
rsr.ZSR_EPS a2
wsr.ps a2
#ifdef CONFIG_USERSPACE
/* Save "context handle" in A3 as we need it to determine
* if... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:11 | #else
SWAP_PAGE_TABLE a6, a3, a7
#endif
#endif
#ifdef CONFIG_XTENSA_MPU
call4 xtensa_mpu_map_write
#endif
_xstack_skip_table_swap_\@:
#endif /* CONFIG_USERSPACE */
retw
_xstack_returned_\@:
.endm
/* Entry setup for all exceptions and interrupts. Arrive here with
* the stack pointer decremented across a base sav... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:12 | * So when nested value is zero, we store the PS
* value into thread struct.
*/
rsr.ZSR_CPU a0
l32i a2, a0, ___cpu_t_nested_OFFSET
bnez a2, _excint_skip_ps_save_to_thread
l32i a2, a0, ___cpu_t_current_OFFSET
s32i a3, a2, _thread_offset_to_return_ps
_excint_skip_ps_save_to_thread:
/* DEF_EXCINT saved PS into ... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:13 | #endif /* XCHAL_HAVE_THREADPTR && CONFIG_USERSPACE */
/* Setting up the cross stack call below has states where the
* resulting frames are invalid/non-reentrant, so we can't
* allow nested interrupts. But we do need EXCM unmasked, as
* we use CALL/ENTRY instructions in the process and need to
* handle except... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:14 | * good to put this code into the L1 handler only, but there's
* not enough room in the vector without some work there to
* squash it some. Next choice would be to make this a macro
* argument and expand two versions of this handler. An
* optimization FIXME, I guess.
*/
movi a3, PS_INTLEVEL_MASK
and a3, a0... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:15 | addi a0, a0, 1
s32i a0, a3, \NEST_OFF
l32i a3, a3, \INTSTACK_OFF
_do_call_\@:
CROSS_STACK_CALL
/* Mask interrupts (which have been unmasked during the handler
* execution) while we muck with the windows and decrement the nested
* count. The restore will unmask them correctly.
*/
rsil a0, XCHAL_NUM_INTLEVE... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:16 | #if defined(CONFIG_KERNEL_COHERENCE) && \
defined(CONFIG_USERSPACE) && \
!defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
/* With userspace enabled, we need to swap page table via function calls
* above after returning from syscall handler above in CROSS_STACK_CALL.
* This means that the stack is being actively used, a... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:17 | /* Defines an exception/interrupt vector for a specified level. Saves
* off the interrupted A0-A3 registers and the per-level PS/PC
* registers to the stack before jumping to a handler (defined with
* EXCINT_HANDLER) to do the rest of the work.
*
* Arguments are a numeric interrupt level and symbol names for the
... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:18 | * to handle these misses. This results in DEPC, EXCCAUSE
* and EXCVADDR being overwritten, and then execution returned
* back to this site of TLB misses. When it gets to the C handler,
* it will not see the original cause. So stash the EXCCAUSE
* and EXCVADDR here so C handler can see the original cause.
*
... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:19 | j _TripleFault
_not_triple_fault:
.endif
#endif
addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
#ifdef CONFIG_XTENSA_MMU
.if \LVL == 1
/* Save EXCVADDR register needed for handling the exception
* as this register can be overwritten during nested
* exceptions. It has to be saved first, because
* executing the stor... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:20 | * calling convention. No special register holds the
* interrupted PS, instead we just assume that the CPU has
* turned on the EXCM bit and set INTLEVEL.
*/
.if \LVL == 1
rsr.ps a0
#ifdef CONFIG_XTENSA_MMU
/* TLB misses also come through level 1 interrupts.
* We do not want to unconditionally unmask interrupt... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 761 | 820 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:21 | * at a fixed address in their own section, and don't (in our
* current linker setup) have anywhere "definitely before
* vectors" to place immediates. Some platforms and apps will
* link by dumb luck, others won't. We add an extra jump just
* to clear space we know to be legal.
*
* The right way to fix thi... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/xtensa/include/xtensa_asm2.inc.S | 801 | 843 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:4 | ssi f7, a1, ___xtensa_irq_bsa_t_fpu7_OFFSET
ssi f8, a1, ___xtensa_irq_bsa_t_fpu8_OFFSET
ssi f9, a1, ___xtensa_irq_bsa_t_fpu9_OFFSET
ssi f10, a1, ___xtensa_irq_bsa_t_fpu10_OFFSET
ssi f11, a1, ___xtensa_irq_bsa_t_fpu11_OFFSET
ssi f12, a1, ___xtensa_irq_bsa_t_fpu12_OFFSET
ssi f13, a1, ___xtensa_irq_bsa_t_fpu13_OFFSE... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:5 | * On exit, the scratch register specified by parameter SCRATCH_REG
* will have been modified, and the shift/loop instructions can be
* used freely (though note loops don't work in exceptions for other
* reasons!).
*
* Does not populate or modify the PS/PC save locations.
*/
.macro ODD_REG_SAVE SCRATCH_REG, BSA_PT... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:6 | * Does not restore the PS/PC save locations.
*/
.macro ODD_REG_RESTORE SCRATCH_REG, BSA_PTR
l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_sar_OFFSET
wsr.sar \SCRATCH_REG
#if XCHAL_HAVE_LOOPS
l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lbeg_OFFSET
wsr.lbeg \SCRATCH_REG
l32i \SCRATCH_REG, \BSA_PTR, ___xtens... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:7 | .macro SWAP_PAGE_TABLE THREAD_PTR_REG, SC1_REG, SC2_REG
l32i \THREAD_PTR_REG, \THREAD_PTR_REG, _thread_offset_to_mem_domain
j _swap_page_table_\@
.align 16
_swap_page_table_\@:
l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptevaddr
l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_re... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:9 | * should point to a stored pointer which points to one BSA below the
* interrupted/old stack) in A1, a handler function in A2, and a "new"
* stack pointer (i.e. a pointer to the word ABOVE the allocated stack
* area) in A3. Exceptions should be enabled via PS.EXCM, but
* PS.INTLEVEL must (!) be set such that no ne... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:10 | * rotation, but we want our own SP. After that, we are
* running in a valid frame, so re-enable interrupts.
*/
entry a1, 16
mov a1, a2
rsr.ZSR_EPS a2
wsr.ps a2
#ifdef CONFIG_USERSPACE
/* Save "context handle" in A3 as we need it to determine
* if we need to swap page table later.
*/
mov a3, a6
#endif
... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:11 | SWAP_PAGE_TABLE a6, a3, a7
#endif
#endif
#ifdef CONFIG_XTENSA_MPU
call4 xtensa_mpu_map_write
#endif
_xstack_skip_table_swap_\@:
#endif /* CONFIG_USERSPACE */
retw
_xstack_returned_\@:
.endm
/* Entry setup for all exceptions and interrupts. Arrive here with
* the stack pointer decremented across a base save area,... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:12 | * value into thread struct.
*/
rsr.ZSR_CPU a0
l32i a2, a0, ___cpu_t_nested_OFFSET
bnez a2, _excint_skip_ps_save_to_thread
l32i a2, a0, ___cpu_t_current_OFFSET
s32i a3, a2, _thread_offset_to_return_ps
_excint_skip_ps_save_to_thread:
/* DEF_EXCINT saved PS into A3 so we need to restore
* A3 here before procee... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:13 | /* Setting up the cross stack call below has states where the
* resulting frames are invalid/non-reentrant, so we can't
* allow nested interrupts. But we do need EXCM unmasked, as
* we use CALL/ENTRY instructions in the process and need to
* handle exceptions to spill caller/interruptee frames. Use
* PS.INT... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:14 | * not enough room in the vector without some work there to
* squash it some. Next choice would be to make this a macro
* argument and expand two versions of this handler. An
* optimization FIXME, I guess.
*/
movi a3, PS_INTLEVEL_MASK
and a3, a0, a3
bnez a3, _not_l1
/* interrupt masking is zero, so no nee... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 521 | 580 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:15 | s32i a0, a3, \NEST_OFF
l32i a3, a3, \INTSTACK_OFF
_do_call_\@:
CROSS_STACK_CALL
/* Mask interrupts (which have been unmasked during the handler
* execution) while we muck with the windows and decrement the nested
* count. The restore will unmask them correctly.
*/
rsil a0, XCHAL_NUM_INTLEVELS
/* Decremen... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:16 | #if defined(CONFIG_KERNEL_COHERENCE) && \
defined(CONFIG_USERSPACE) && \
!defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
/* With userspace enabled, we need to swap page table via function calls
* above after returning from syscall handler above in CROSS_STACK_CALL.
* This means that the stack is being actively used, a... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:17 | * off the interrupted A0-A3 registers and the per-level PS/PC
* registers to the stack before jumping to a handler (defined with
* EXCINT_HANDLER) to do the rest of the work.
*
* Arguments are a numeric interrupt level and symbol names for the
* entry code (defined via EXCINT_HANDLER) and a C handler for this
* p... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:18 | * and EXCVADDR being overwritten, and then execution returned
* back to this site of TLB misses. When it gets to the C handler,
* it will not see the original cause. So stash the EXCCAUSE
* and EXCVADDR here so C handler can see the original cause.
*
* For double exception, DEPC in saved in earlier vector
*... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:19 | _not_triple_fault:
.endif
#endif
addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
#ifdef CONFIG_XTENSA_MMU
.if \LVL == 1
/* Save EXCVADDR register needed for handling the exception
* as this register can be overwritten during nested
* exceptions. It has to be saved first, because
* executing the store instruction ma... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:20 | * interrupted PS, instead we just assume that the CPU has
* turned on the EXCM bit and set INTLEVEL.
*/
.if \LVL == 1
rsr.ps a0
#ifdef CONFIG_XTENSA_MMU
/* TLB misses also come through level 1 interrupts.
* We do not want to unconditionally unmask interrupts.
* Execution continues after a TLB miss is handled,... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 761 | 820 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:21 | * current linker setup) have anywhere "definitely before
* vectors" to place immediates. Some platforms and apps will
* link by dumb luck, others won't. We add an extra jump just
* to clear space we know to be legal.
*
* The right way to fix this would be to use a "literal_prefix"
* to put the literals in... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | c1a2b3be459d4f34d31ae54774fd57e96438d237 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/c1a2b3be459d4f34d31ae54774fd57e96438d237/arch/xtensa/include/xtensa_asm2.inc.S | 801 | 842 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:17 | * off the interrupted A0-A3 registers and the per-level PS/PC
* registers to the stack before jumping to a handler (defined with
* EXCINT_HANDLER) to do the rest of the work.
*
* Arguments are a numeric interrupt level and symbol names for the
* entry code (defined via EXCINT_HANDLER) and a C handler for this
* p... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | fd8188a408240090498bac31597148f41cdc160e | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/fd8188a408240090498bac31597148f41cdc160e/arch/xtensa/include/xtensa_asm2.inc.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:18 | * being overwritten, and then execution returned back to
* this site of TLB misses. When it gets to the C handler,
* it will not see the original cause. So stash
* the EXCCAUSE here so C handler can see the original cause.
*
* For double exception, DEPC in saved in earlier vector
* code.
*/
wsr a0, ZSR_A... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | fd8188a408240090498bac31597148f41cdc160e | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/fd8188a408240090498bac31597148f41cdc160e/arch/xtensa/include/xtensa_asm2.inc.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:19 | .endif
#endif
addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
/* Save register needed for handling the exception as
* this register can be overwritten during nested
* exceptions.
*/
rs... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | fd8188a408240090498bac31597148f41cdc160e | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/fd8188a408240090498bac31597148f41cdc160e/arch/xtensa/include/xtensa_asm2.inc.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:20 | #ifdef CONFIG_USERSPACE
/* Stash the PS into A3 so EXCINT_HANDLER can read this
* and save it into thread struct if needed.
*/
mov a3, a0
#endif
rsr.epc\LVL a0
s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
/* What's happening with this jump is that the L32R
* instruction to load a full 32 bit immediate must u... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | fd8188a408240090498bac31597148f41cdc160e | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/fd8188a408240090498bac31597148f41cdc160e/arch/xtensa/include/xtensa_asm2.inc.S | 761 | 819 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:21 | #if defined(CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY)
.if \LVL == 1
.pushsection .iram0.text, "ax"
.elseif \LVL == XCHAL_DEBUGLEVEL
.pushsection .DebugExceptionVector.text, "ax"
.elseif \LVL == XCHAL_NMILEVEL
.pushsection .NMIExceptionVector.text, "ax"
.else
.pushsection .Level\LVL\()InterruptVector.text, "ax"
.endif
.gl... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | fd8188a408240090498bac31597148f41cdc160e | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/fd8188a408240090498bac31597148f41cdc160e/arch/xtensa/include/xtensa_asm2.inc.S | 801 | 819 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:18 | * being overwritten, and then execution returned back to
* this site of TLB misses. When it gets to the C handler,
* it will not see the original cause. So stash
* the EXCCAUSE here so C handler can see the original cause.
*
* For double exception, DEPC in saved in earlier vector
* code.
*/
wsr a0, ZSR_A... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/xtensa/include/xtensa_asm2.inc.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:19 | .endif
#endif
addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
/* Save registers needed for handling the exception as
* these registers can be overwritten during nested
* exceptions.
*/
... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/xtensa/include/xtensa_asm2.inc.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:20 | rsr.eps\LVL a0
s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
.endif
#ifdef CONFIG_USERSPACE
/* Stash the PS into A3 so EXCINT_HANDLER can read this
* and save it into thread struct if needed.
*/
mov a3, a0
#endif
rsr.epc\LVL a0
s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
/* What's happening with this jump is t... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/xtensa/include/xtensa_asm2.inc.S | 761 | 820 |
zephyrproject-rtos/zephyr:arch/xtensa/include/xtensa_asm2.inc.S:21 | jx a0
.popsection
#if defined(CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY)
.if \LVL == 1
.pushsection .iram0.text, "ax"
.elseif \LVL == XCHAL_DEBUGLEVEL
.pushsection .DebugExceptionVector.text, "ax"
.elseif \LVL == XCHAL_NMILEVEL
.pushsection .NMIExceptionVector.text, "ax"
.else
.pushsection .Level\LVL\()InterruptVector.te... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/xtensa/include/xtensa_asm2.inc.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/xtensa/include/xtensa_asm2.inc.S | 801 | 822 |
zephyrproject-rtos/zephyr:boards/nxp/common/board-footer.rst.inc:1 | Support Resources for Zephyr
============================
- `NXP Board Support Status`_
- `NXP Zephyr Downstream Software Development Kit`_
- `MCUXpresso for VS Code documentation`_, and `Zephyr lab guides`_
- `NXP Zephyr Knowledge Hub`_
- `NXP’s Zephyr landing page`_ (including training resources)
- `NXP Support Comm... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | boards/nxp/common/board-footer.rst.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/boards/nxp/common/board-footer.rst.inc | 1 | 32 |
zephyrproject-rtos/zephyr:boards/nxp/common/board-footer.rst.inc:1 | Support Resources for Zephyr
============================
- `NXP Board Support Status`_
- `NXP Zephyr Downstream Software Development Kit`_
- `MCUXpresso for VS Code`_, `wiki`_ documentation and `Zephyr lab guides`_
- `NXP Zephyr Knowledge Hub`_
- `NXP’s Zephyr landing page`_ (including training resources)
- `NXP Supp... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | boards/nxp/common/board-footer.rst.inc | Apache-2.0 | 348ae31ccce003257fc5340cbaba0bf25f9df96c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/348ae31ccce003257fc5340cbaba0bf25f9df96c/boards/nxp/common/board-footer.rst.inc | 1 | 32 |
zephyrproject-rtos/zephyr:boards/nxp/common/board-footer.rst.inc:1 | Support Resources for Zephyr
============================
- `NXP Zephyr Downstream Software Development Kit`_
- `MCUXpresso for VS Code`_, `wiki`_ documentation and `Zephyr lab guides`_
- `NXP Zephyr Knowledge Hub`_
- `NXP’s Zephyr landing page`_ (including training resources)
- `NXP Support Community forum for Zephyr... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | boards/nxp/common/board-footer.rst.inc | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/boards/nxp/common/board-footer.rst.inc | 1 | 28 |
zephyrproject-rtos/zephyr:boards/nxp/common/opensda-debug.rst.inc:1 | A debug probe is used for both flashing and debugging the board. This board has
an :ref:`opensda-onboard-debug-probe`. The default firmware present on this
probe is the :ref:`opensda-daplink-onboard-debug-probe`.
Based on the host tool installed, please use the following instructions
to setup your debug probe:
* :ref... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | boards/nxp/common/opensda-debug.rst.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/boards/nxp/common/opensda-debug.rst.inc | 1 | 35 |
zephyrproject-rtos/zephyr:boards/nxp/common/rt1xxx-lpclink2-debug.rst.inc:1 | A debug probe is used for both flashing and debugging the board. This board has
an :ref:`lpc-link2-onboard-debug-probe`. The default firmware present on this
probe is the :ref:`lpclink2-daplink-onboard-debug-probe`.
Based on the host tool installed, please use the following instructions
to setup your debug probe:
* :... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | boards/nxp/common/rt1xxx-lpclink2-debug.rst.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/boards/nxp/common/rt1xxx-lpclink2-debug.rst.inc | 1 | 41 |
zephyrproject-rtos/zephyr:boards/nxp/common/segger-ecc-systemview.rst.inc:1 | Using Segger SystemView and RTT
-------------------------------
Note that when using SEGGER SystemView or RTT with this SOC, the RTT control
block address must be set manually within SystemView or the RTT Viewer. The
address provided to the tool should be the location of the ``_SEGGER_RTT``
symbol, which can be found ... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | boards/nxp/common/segger-ecc-systemview.rst.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/boards/nxp/common/segger-ecc-systemview.rst.inc | 1 | 13 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_clic.S:1 | /*
* Copyright (c) 2024 Baumer Electric AG
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Assembler-hooks specific to RISC-V Core Local Interrupt Controller
*/
#include <zephyr/arch/cpu.h>
#include "intc_clic.h"
#ifdef CONFIG_64BIT
/* register-wide load/store based on ld/sd (XLEN = 64) */
.macro lr... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_clic.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_clic.S | 1 | 60 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_clic.S:2 | * In vectored mode, interrupts are cleared automatically.
* In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
* __soc_handle_all_irqs).
* Thus this function can directly return.
*/
SECTION_FUNC(exception.other, __soc_handle_irq)
ret
GTEXT(__soc_handle_all_irqs)
#ifdef CONFIG_T... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_clic.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_clic.S | 41 | 100 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_clic.S:3 | add t0, t0, a0
/* Load argument in a0 register */
lr a0, 0(t0)
/* Load ISR function address in register t1 */
lr t1, RV_REGSIZE(t0)
/* Call ISR function */
jalr ra, t1, 0
#ifdef CONFIG_TRACING_ISR
call sys_trace_isr_exit
#endif
/* Read and clear mnxti to get highest current interrupt and enable interrupts.... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_clic.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_clic.S | 81 | 103 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_hazard3.S:1 | /*
* Copyright (C) 2025 Andrew Featherstone
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include "hardware/platform_defs.h"
#include "hardware/regs/rvcsr.h"
/* imports */
#ifdef CONFIG_TRACING
GTEXT(sys_trace_isr_enter)
GTEXT(sys_trace_isr_exit)
#endif
/* exports */
GTEXT(__soc_handle_... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_hazard3.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_hazard3.S | 1 | 60 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_hazard3.S:2 | slli a0, a0, (1)
add t0, t0, a0
/* Load argument in a0 register */
lw a0, 0(t0)
/* Load ISR function address in register t1 */
lw t1, 4(t0)
/* Call ISR function */
jalr ra, t1, 0
#ifdef CONFIG_TRACING_ISR
call sys_trace_isr_exit
#endif
/* Get the next highest interrupt, and process that, or continue to do... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_hazard3.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_hazard3.S | 41 | 64 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_loapic_spurious.S:1 | /*
* Copyright (c) 2015 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief LOAPIC spurious interrupt handler
*/
#include <zephyr/kernel_structs.h>
#include <zephyr/arch/x86/ia32/asm.h>
GTEXT(z_loapic_spurious_handler)
SECTION_FUNC(PINNED_TEXT, z_loapic_spurious_handler)
iret | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_loapic_spurious.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_loapic_spurious.S | 1 | 18 |
zephyrproject-rtos/zephyr:drivers/interrupt_controller/intc_nrfx_clic.S:1 | /*
* Copyright (C) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
/* Exports */
GTEXT(__soc_handle_irq)
/*
* No need to clear anything, pending bit is cleared by HW.
*/
SECTION_FUNC(exception.other, __soc_handle_irq)
ret | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | drivers/interrupt_controller/intc_nrfx_clic.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/drivers/interrupt_controller/intc_nrfx_clic.S | 1 | 15 |
zephyrproject-rtos/zephyr:include/zephyr/arch/arm64/macro.inc:1 | /*
* Copyright 2020 Broadcom.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_MACRO_INC_
#define ZEPHYR_INCLUDE_ARCH_ARM64_MACRO_INC_
#ifdef _ASMLANGUAGE
.macro switch_el, xreg, el3_label, el2_label, el1_label
mrs \xreg, CurrentEL
cmp \xreg, 0xc
beq \el3_label
cmp \xreg, 0x8
beq... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | include/zephyr/arch/arm64/macro.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/include/zephyr/arch/arm64/macro.inc | 1 | 47 |
zephyrproject-rtos/zephyr:samples/boards/nxp/adsp/rtxxx/common/src/dspimgs.S:1 | /*
* Copyright 2025 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: Apache-2.0
*/
.section .text
.global dsp_img_reset_start
.type dsp_img_reset_start, %object
.align 2
dsp_img_reset_start:
.incbin HIFI4_BIN_RESET
.global dsp_img_reset_end
.type dsp_img_reset_end, %object
dsp_img_reset_end:
.global ... | unknown | gas-like | handwritten | zephyrproject-rtos/zephyr | samples/boards/nxp/adsp/rtxxx/common/src/dspimgs.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/samples/boards/nxp/adsp/rtxxx/common/src/dspimgs.S | 1 | 59 |
zephyrproject-rtos/zephyr:soc/adi/max32/soc_irq_rv32.S:1 | /*
* Copyright (c) 2018 Foundries.io Ltd
* Copyright (c) 2026 Analog Devices, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel_structs.h>
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/riscv/irq.h>
#include <soc_ri5cy.h>
... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/adi/max32/soc_irq_rv32.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/adi/max32/soc_irq_rv32.S | 1 | 60 |
zephyrproject-rtos/zephyr:soc/adi/max32/soc_irq_rv32.S:2 | * If the toolchain generates instructions that use them, they must be saved
* prior to handling an interrupt/exception. This case is handled using
* Zephyr's generic RISC-V mechanism for soc-specific context.
*
* For details, see the Kconfig help for CONFIG_RISCV_SOC_CONTEXT_SAVE.
*/
SECTION_FUNC(exception.other, ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/adi/max32/soc_irq_rv32.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/adi/max32/soc_irq_rv32.S | 41 | 78 |
zephyrproject-rtos/zephyr:soc/adi/max32/vector_rv32.S:1 | /*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/arch/riscv/irq.h>
/* exports */
GTEXT(__start)
GTEXT(__ivt)
GTEXT(__rv32_isr_wrapper)
/* imports */
GTEXT(... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/adi/max32/vector_rv32.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/adi/max32/vector_rv32.S | 1 | 60 |
zephyrproject-rtos/zephyr:soc/adi/max32/vector_rv32.S:2 | j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr_wrapper
j __rv32_isr... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/adi/max32/vector_rv32.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/adi/max32/vector_rv32.S | 41 | 98 |
zephyrproject-rtos/zephyr:soc/adi/max32/vector_rv32.S:3 | .option pop
#endif
.option norvc;
#if defined(CONFIG_SOC_RESET_HOOK)
call soc_reset_hook
#endif
la t0, __ivt /* Load address of interrupt vector table */
addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
csrw mtvec, t0
/* Enable IRQs */
csrwi mstatus, 8
/* Jump to __reset */
tail __reset | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/adi/max32/vector_rv32.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/adi/max32/vector_rv32.S | 81 | 98 |
zephyrproject-rtos/zephyr:soc/andestech/ae350/soc_irq.S:1 | /*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <csr_irq.inc>
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Exports */
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
SECTION_FUNC(exception.other... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/andestech/ae350/soc_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/andestech/ae350/soc_irq.S | 1 | 30 |
zephyrproject-rtos/zephyr:soc/cdns/swerv/s420/startup.S:1 | /*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Copyright (c) 2026 Intel Corporation
*
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__initialize)
GTEXT(_isr_wrappe... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/cdns/swerv/s420/startup.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/cdns/swerv/s420/startup.S | 1 | 50 |
zephyrproject-rtos/zephyr:soc/common/riscv-privileged/soc_irq.S:1 | /*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* common interrupt management code for riscv SOCs supporting the riscv
* privileged architecture specification
*/
#include <zephyr/kernel_structs.h>
#include <zephyr/offsets.h>
#include <zephyr/toolc... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/common/riscv-privileged/soc_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/common/riscv-privileged/soc_irq.S | 1 | 51 |
zephyrproject-rtos/zephyr:soc/common/riscv-privileged/vector.S:1 | /*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__initialize)
#if defined(CONFIG_USE_ISR_WRAPPER)
GTEXT(_isr_wrapper)
#end... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/common/riscv-privileged/vector.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/common/riscv-privileged/vector.S | 1 | 60 |
zephyrproject-rtos/zephyr:soc/common/riscv-privileged/vector.S:2 | * mtvec.base must be aligned to 64 bytes (this is done using
* CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
*/
#if defined(CONFIG_USE_ISR_WRAPPER)
la t0, _isr_wrapper
#else
add t0, zero, zero
#endif
addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
csrw mtvec, t0
/*
* CLIC vectored mode has a similar... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/common/riscv-privileged/vector.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/common/riscv-privileged/vector.S | 41 | 100 |
zephyrproject-rtos/zephyr:soc/common/riscv-privileged/vector.S:3 | la t0, _irq_vector_table /* Load address of interrupt vector table */
addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
#ifdef CONFIG_RISCV_S_MODE
csrw stvec, t0
#else
csrw mtvec, t0
#endif
#endif /* CONFIG_RISCV_HAS_CLIC */
#else /* !CONFIG_RISCV_VECTORED_MODE */
#if defined(CONFIG_RISCV_HAS_CLIC) && !... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/common/riscv-privileged/vector.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/common/riscv-privileged/vector.S | 81 | 119 |
zephyrproject-rtos/zephyr:soc/common/riscv-privileged/vector.S:2 | * mtvec.base must be aligned to 64 bytes (this is done using
* CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
*/
#if defined(CONFIG_USE_ISR_WRAPPER)
la t0, _isr_wrapper
#else
add t0, zero, zero
#endif
addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
csrw mtvec, t0
/*
* CLIC vectored mode has a similar... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/common/riscv-privileged/vector.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/soc/common/riscv-privileged/vector.S | 41 | 100 |
zephyrproject-rtos/zephyr:soc/common/riscv-privileged/vector.S:3 | la t0, _irq_vector_table /* Load address of interrupt vector table */
addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
csrw mtvec, t0
#endif /* CONFIG_RISCV_HAS_CLIC */
#else /* !CONFIG_RISCV_VECTORED_MODE */
#if defined(CONFIG_RISCV_HAS_CLIC) && !defined(CONFIG_LEGACY_CLIC)
la t0, _isr_wrapper
addi ... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/common/riscv-privileged/vector.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/soc/common/riscv-privileged/vector.S | 81 | 111 |
zephyrproject-rtos/zephyr:soc/egis/et171/soc_irq.S:1 | /*
* Copyright (c) 2025 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <csr_irq.inc>
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Exports */
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
SECTION_FUNC(exception.other... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/egis/et171/soc_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/egis/et171/soc_irq.S | 1 | 30 |
zephyrproject-rtos/zephyr:soc/egis/et171/start.S:1 | /*
* Copyright (c) 2021 Andes Technology Corporation
* Copyright (c) 2025 Egis Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
/* exports */
GTEXT(entry)
SECTION_FUNC(init, entry)
/* Disable linker relaxation before GP register initialization. */
.option push
.option ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/egis/et171/start.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/egis/et171/start.S | 1 | 37 |
zephyrproject-rtos/zephyr:soc/egis/et171/start.S:1 | /*
* Copyright (c) 2021 Andes Technology Corporation
* Copyright (c) 2025 Egis Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
/* exports */
GTEXT(entry)
SECTION_FUNC(init, entry)
/* Disable linker relaxation before GP register initialization. */
.option push
.option ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/egis/et171/start.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/soc/egis/et171/start.S | 1 | 33 |
zephyrproject-rtos/zephyr:soc/espressif/esp32/Kconfig.mac:1 | # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32
choice ESP32_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally administe... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32/Kconfig.mac | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32/Kconfig.mac | 1 | 45 |
zephyrproject-rtos/zephyr:soc/espressif/esp32c2/Kconfig.mac:1 | # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C2
choice ESP32C2_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32C2_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally adm... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32c2/Kconfig.mac | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32c2/Kconfig.mac | 1 | 48 |
zephyrproject-rtos/zephyr:soc/espressif/esp32c3/Kconfig.mac:1 | # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C3
choice ESP32C3_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally adm... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32c3/Kconfig.mac | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32c3/Kconfig.mac | 1 | 48 |
zephyrproject-rtos/zephyr:soc/espressif/esp32c3/soc_irq.S:1 | /* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
/* Exports */
GTEXT(__soc_handle_irq)
SECTION_FUNC(exception.other, __soc_handle_irq)
/* int status clearing is done at ISR */
ret | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32c3/soc_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32c3/soc_irq.S | 1 | 15 |
zephyrproject-rtos/zephyr:soc/espressif/esp32c3/vectors.S:1 | /* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/interrupt_reg.h"
#include "riscv/rvruntime-frames.h"
#include "soc/soc_caps.h"
#include <zephyr/toolchain.h>
/* Imports */
GTEXT(_isr_wrapper)
/* This is the vector table. MTV... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32c3/vectors.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32c3/vectors.S | 1 | 35 |
zephyrproject-rtos/zephyr:soc/espressif/esp32c5/Kconfig.mac:1 | # Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_ESP32C5
choice ESP32C5_UNIVERSAL_MAC_ADDRESSES
bool "Number of universally administered (by IEEE) MAC address"
default ESP32C5_UNIVERSAL_MAC_ADDRESSES_FOUR
help
Configure the number of universally adm... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32c5/Kconfig.mac | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32c5/Kconfig.mac | 1 | 49 |
zephyrproject-rtos/zephyr:soc/espressif/esp32c5/soc_irq.S:1 | /* Copyright 2026 Espressif Systems (Shanghai) PTE LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <zephyr/arch/riscv/irq.h>
/* Exports */
GTEXT(__soc_handle_irq)
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
SECTION_FUNC(exception.other, ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | soc/espressif/esp32c5/soc_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/soc/espressif/esp32c5/soc_irq.S | 1 | 55 |
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