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value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:4 | riscv_tls_init_early
#endif
#ifdef CONFIG_RISCV_SMRNMI_ENABLE_NMI_DELIVERY
csrs CSR_MNSTATUS, MNSTATUS_NMIE
#endif
#ifdef CONFIG_WDOG_INIT
call _WdogInit
#endif
#ifdef CONFIG_RISCV_S_MODE
/* Set M-mode trap vector to our SBI handler */
la t0, __m_mode_sbi_handler
csrw mtvec, t0
/* Delegate all exceptions to S... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 729110c12fec2cf1843e39f19f88a86c7c676513 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/729110c12fec2cf1843e39f19f88a86c7c676513/arch/riscv/core/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:5 | /* Allow S-mode to read cycle, time and instret counters */
li t0, (MCOUNTEREN_CY | MCOUNTEREN_TM | MCOUNTEREN_IR)
csrw mcounteren, t0
/* Enable M-mode timer interrupt so MTIP fires and is forwarded to S-mode as STIP */
li t0, MIP_MTIP
csrs mie, t0
/* Set MPP=S-mode in mstatus then mret into S-mode */
li t0, M... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 729110c12fec2cf1843e39f19f88a86c7c676513 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/729110c12fec2cf1843e39f19f88a86c7c676513/arch/riscv/core/reset.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:6 | la t0, riscv_cpu_sp
lr sp, 0(t0)
#ifdef CONFIG_THREAD_LOCAL_STORAGE
/* Initialize tp early so TLS-based stack canaries work on secondary CPUs */
mv s2, a0 /* save hartid across TLS init calls */
riscv_tls_init_early
mv a0, s2 /* restore hartid */
#endif
la t0, riscv_cpu_boot_flag
li t1, 1
sr t1, 0(t0)
j ar... | riscv | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 729110c12fec2cf1843e39f19f88a86c7c676513 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/729110c12fec2cf1843e39f19f88a86c7c676513/arch/riscv/core/reset.S | 201 | 221 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:1 | /*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/offsets.h>
#include <zephyr/arch/riscv/csr.... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8/arch/riscv/core/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:2 | * This will be dependent on linker.ld configuration.
*/
call __initialize
#endif /* CONFIG_INCLUDE_RESET_VECTOR */
/* use ABI name of registers for the sake of simplicity */
/*
* Remainder of asm-land initialization code before we can jump into
* the C domain
*/
SECTION_FUNC(TEXT, __initialize)
csrr a0, mharti... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8/arch/riscv/core/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:3 | /* Populate z_interrupt_stacks with 0xaaaaaaaa */
li t2, 0xaaaaaaaa
aa_loop:
sw t2, 0x00(t0)
addi t0, t0, 4
blt t0, t1, aa_loop
#endif /* CONFIG_INIT_STACKS */
/*
* Initially, setup stack pointer to
* z_interrupt_stacks + __z_interrupt_stack_SIZEOF
*/
la sp, z_interrupt_stacks
li t0, __z_interrupt_stack_S... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8/arch/riscv/core/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:4 | /* PMP entry 0: NAPOT, RWX, covers all memory so S-mode can
* access everything
*/
li t0, -1
csrw pmpaddr0, t0
li t0, (PMP_NAPOT | PMP_R | PMP_W | PMP_X)
csrw pmpcfg0, t0
/* Initialize mscratch to M-mode stack top */
la t0, m_mode_stack_top
csrw mscratch, t0
/* Allow S-mode to read cycle, time and instret c... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8/arch/riscv/core/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:5 | #if CONFIG_MP_MAX_NUM_CPUS > 1
la t0, riscv_cpu_wake_flag
li t1, -1
sr t1, 0(t0)
la t0, riscv_cpu_boot_flag
sr zero, 0(t0)
wait_secondary_wake_flag:
la t0, riscv_cpu_wake_flag
lr t0, 0(t0)
bne a0, t0, wait_secondary_wake_flag
/* Set up stack */
la t0, riscv_cpu_sp
lr sp, 0(t0)
la t0, riscv_cpu_boot_flag
... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/1cf1de81a1b6673e81f75cc6b0c5b55ac0bc80f8/arch/riscv/core/reset.S | 161 | 187 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:1 | /*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
* Contributors: 2018 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/offsets.h>
#include <zephyr/arch/riscv/csr.... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:2 | SECTION_FUNC(TEXT, __initialize)
csrr a0, mhartid
li t0, CONFIG_RV_BOOT_HART
beq a0, t0, boot_first_core
j boot_secondary_core
boot_first_core:
#ifdef CONFIG_FPU
/*
* Enable floating-point.
*/
li t0, MSTATUS_FS_INIT
csrs mstatus, t0
/*
* Floating-point rounding mode set to IEEE-754 default, and clear
... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/reset.S:3 | */
la sp, z_interrupt_stacks
li t0, __z_interrupt_stack_SIZEOF
add sp, sp, t0
#ifdef CONFIG_RISCV_SMRNMI_ENABLE_NMI_DELIVERY
csrs CSR_MNSTATUS, MNSTATUS_NMIE
#endif
#ifdef CONFIG_WDOG_INIT
call _WdogInit
#endif
/*
* Jump into C domain. z_prep_c zeroes BSS, copies rw data into RAM,
* and then enters kernel ... | riscv | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/reset.S | 81 | 127 |
zephyrproject-rtos/zephyr:arch/riscv/core/sbi.S:1 | /*
* Copyright (c) 2026 Alexios Lyrakis <alexios.lyrakis@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*
* Minimal M-mode SBI runtime.
* Handles machine timer interrupts (MTIP) and SBI ecalls from S-mode.
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/riscv/csr.h>
#includ... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/sbi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/sbi.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/sbi.S:2 | GTEXT(__m_mode_sbi_handler)
SECTION_FUNC(TEXT, __m_mode_sbi_handler)
/*
* mscratch holds the M-mode stack pointer (initialised in reset.S).
* Atomically swap sp and mscratch: now sp = M-mode stack,
* mscratch = S-mode sp (saved for later restore).
*/
csrrw sp, mscratch, sp
/* Save all regi... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/sbi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/sbi.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/sbi.S:3 | /* Dispatch on SBI extension ID in a7 */
li t0, SBI_EXT_TIME
beq a7, t0, m_mode_ext_time
li t0, SBI_EXT_SRST
beq a7, t0, m_mode_ext_srst
/* Unknown extension — a1 is undefined on error per SBI spec */
li a0, SBI_ERR_NOT_SUPPORTED
sd a0, 32(sp)
j m_mode_return
m_mode_ext_time:
/* D... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/sbi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/sbi.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/riscv/core/sbi.S:4 | m_mode_ext_srst:
/* Only function 0 (SBI_FUNC_SYSTEM_RESET) is defined */
li t0, SBI_FUNC_SYSTEM_RESET
bne a6, t0, m_mode_srst_unsupported
#ifdef CONFIG_QEMU_TARGET
/*
* Write FINISHER_EXIT to the QEMU virt "sifive_test" device.
* QEMU exits immediately; the loop below is unreachable in pract... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/sbi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/sbi.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/riscv/core/sbi.S:5 | sd t1, 0(t0)
/* Forward to S-mode by raising STIP */
li t0, MIP_STIP
csrs mip, t0
j m_mode_return
m_mode_unhandled:
/*
* Unexpected trap in M-mode. We have no recovery path — spin
* forever. This will show as a hang in QEMU and signals a fatal
* M-mode error during debugging.
*/
m_mode_unhan... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/sbi.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/sbi.S | 161 | 195 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:1 | /*
* Copyright (c) 2022 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include "asm_macros.inc"
#ifdef CONFIG_CUSTOM_STACK_GU... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/switch.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:2 | /* void z_riscv_switch(k_thread_t *switch_to, k_thread_t *switch_from) */
SECTION_FUNC(TEXT, z_riscv_switch)
/* Save the old thread's callee-saved registers */
DO_CALLEE_SAVED(sr, a1)
/* Save the old thread's stack pointer */
sr sp, _thread_offset_to_sp(a1)
/* Set thread->switch_handle = thread to mark completi... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/switch.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:3 | #if defined(CONFIG_THREAD_LOCAL_STORAGE)
/* Get the new thread's tls pointer */
lr tp, _thread_offset_to_tls(a0)
#endif
#if defined(CONFIG_FPU_SHARING)
/* Preserve a0 across following call. s0 is not yet restored. */
mv s0, a0
call z_riscv_fpu_thread_context_switch
mv a0, s0
#endif
#ifdef CONFIG_PMP_KERNEL_MOD... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/switch.S | 81 | 125 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:1 | /*
* Copyright (c) 2022 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include "asm_macros.inc"
/* Convenience macros for loa... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 3944b0cfc7f9f7a9d31479f2a2bd5a89e6ca82a5 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/3944b0cfc7f9f7a9d31479f2a2bd5a89e6ca82a5/arch/riscv/core/switch.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:2 | DO_CALLEE_SAVED(sr, a1)
/* Save the old thread's stack pointer */
sr sp, _thread_offset_to_sp(a1)
/* Set thread->switch_handle = thread to mark completion */
sr a1, ___thread_t_switch_handle_OFFSET(a1)
/* Get the new thread's stack pointer */
lr sp, _thread_offset_to_sp(a0)
#if defined(CONFIG_THREAD_LOCAL_STO... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 3944b0cfc7f9f7a9d31479f2a2bd5a89e6ca82a5 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/3944b0cfc7f9f7a9d31479f2a2bd5a89e6ca82a5/arch/riscv/core/switch.S | 41 | 95 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:3 | mv a0, s0
not_user_task:
#endif
#if CONFIG_INSTRUMENT_THREAD_SWITCHING
mv s0, a0
call z_thread_mark_switched_in
mv a0, s0
#endif
/* Restore the new thread's callee-saved registers */
DO_CALLEE_SAVED(lr, a0)
/* Return to arch_switch() or _irq_wrapper() */
ret | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 3944b0cfc7f9f7a9d31479f2a2bd5a89e6ca82a5 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/3944b0cfc7f9f7a9d31479f2a2bd5a89e6ca82a5/arch/riscv/core/switch.S | 81 | 95 |
zephyrproject-rtos/zephyr:arch/riscv/core/switch.S:2 | DO_CALLEE_SAVED(sr, a1)
/* Save the old thread's stack pointer */
sr sp, _thread_offset_to_sp(a1)
/* Set thread->switch_handle = thread to mark completion */
sr a1, ___thread_t_switch_handle_OFFSET(a1)
/* Get the new thread's stack pointer */
lr sp, _thread_offset_to_sp(a0)
#if defined(CONFIG_THREAD_LOCAL_STO... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/switch.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/riscv/core/switch.S | 41 | 95 |
zephyrproject-rtos/zephyr:arch/riscv/core/userspace.S:1 | /*
* Userspace and service handler hooks
*
* Copyright (c) 2020 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/syscall.h>
#include <zephyr/kernel_structs.h>
#includ... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/core/userspace.S | 1 | 51 |
zephyrproject-rtos/zephyr:arch/riscv/custom/andes/csr_irq.inc:1 | /*
* Copyright (c) 2025 Andes Technology Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <andes_csr.h>
#ifdef CONFIG_64BIT
/* register-wide load/store based on ld/sd (XLEN = 64) */
.macro lr, rd, mem
ld \rd, \mem
.endm
.macro sr, rs, me... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/custom/andes/csr_irq.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/custom/andes/csr_irq.inc | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/custom/andes/csr_irq.inc:2 | #endif
#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP
csrr \reg, NDS_UCODE
sr \reg, __soc_esf_t_ucode_OFFSET(\__soc_esf_reg)
#endif
.endm
.macro __custom_csr_restore_context __soc_esf_reg reg
#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_PFT
lr \reg, __soc_esf_t_mxstatus_OFFSET(\__soc_esf_reg)
csrw NDS_MXSTATUS, \reg
#en... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/custom/andes/csr_irq.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/custom/andes/csr_irq.inc | 41 | 63 |
zephyrproject-rtos/zephyr:arch/riscv/custom/andes/reset.S:1 | /*
* Copyright (c) 2025 Andes Technology Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <andes_csr.h>
#include <zephyr/toolchain.h>
#include <zephyr/devicetree.h>
/* exports */
GTEXT(__reset)
/* imports */
GTEXT(__initialize)
SECTION_FUNC(reset, __reset)
#ifdef CONFIG_RISCV_CUSTOM_CSR_ANDES_EXECI... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/custom/andes/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/custom/andes/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/riscv/custom/andes/reset.S:2 | /* Enable D-cache CM (Coherence Manager). */
li t0, (1 << 19)
csrs NDS_MCACHE_CTL, t0
/* Check if CPU support CM or not. */
csrr t0, NDS_MCACHE_CTL
li t1, (1 << 19)
and t0, t0, t1
beqz t0, cache_enable_finish
/* If CPU support CM, check if CM is enabled. */
li t1, (1 << 20)
check_cm_enabled:
csrr t0, NDS_MC... | riscv | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/riscv/custom/andes/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/custom/andes/reset.S | 41 | 67 |
zephyrproject-rtos/zephyr:arch/riscv/custom/openisa/ri5cy/csr_irq.inc:1 | /*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <ri5cy_csr.h>
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
.macro __custom_csr_save_context __soc_esf_reg reg
csrr \reg, RI5CY_LPSTART0
sw \reg, __soc_esf_t_lpstart0_... | riscv | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/riscv/custom/openisa/ri5cy/csr_irq.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/riscv/custom/openisa/ri5cy/csr_irq.inc | 1 | 47 |
zephyrproject-rtos/zephyr:arch/rx/core/isr_exit.S:1 | /*
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
.list
.section .text
GTEXT(_z_rx_irq_exit)
_z_rx_irq_exit:
mov #__kernel, r1 ; Load the base address of _kernel into r1
mov r1, r3 ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/isr_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/isr_exit.S | 1 | 39 |
zephyrproject-rtos/zephyr:arch/rx/core/reset.S:1 | /*
* Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
.list
.section .text
GTEXT(__start)
__start :
/* during initialization (before the main thread is started), z_initialization... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/rx/core/reset.S:2 | 1: mov.b [r2+], r5
mov.b r5, [r1+]
sub #1, r3
bne 1b
2:
#endif
/* bss initialisation: zero out bss */
mov #0,r2 /* load R2 reg with zero */
mov #_ebss, r3 /* store the end address of bss in R3 */
mov #_bss, r1 /* store the start address of bss in R1 */
... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/rx/core/reset.S:3 | mov #_rx_run_inilist,r7
jsr r7
.global _rx_run_init_array
.type _rx_run_init_array,@function
_rx_run_init_array:
mov #__init_array_start,r1
mov #__init_array_end,r2
mov #4, r3
mov #_rx_run_inilist,r7
jsr r7
.global _rx_run_fini_array
.type _rx_r... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/rx/core/reset.S:4 | .balign 4
.global __rx_init
__rx_init:
.section .fini,"ax"
.balign 4
.global __rx_fini
__rx_fini:
mov #_rx_run_fini_array,r7
jsr r7
.section .sdata
.balign 4
.global __gp
.weak __gp
__gp:
.section .data
.global ___dso_handle
.weak ___dso_... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/reset.S | 121 | 171 |
zephyrproject-rtos/zephyr:arch/rx/core/reset.S:5 | #endif
/* call to exit*/
_exit:
bra _loop_here
_loop_here:
bra _loop_here
.text
.end | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/reset.S | 161 | 171 |
zephyrproject-rtos/zephyr:arch/rx/core/switch.S:1 | /*
* Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
* Copyright (c) 2024 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
GTEXT(_z_rx_arch_switch)
GTEXT(_switch_isr_wrapper)
/* void z... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/switch.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/rx/core/switch.S:2 | * will not change by invoking the interrupt so the parameters switch_to and switched_from
* will be available in _z_rx_context_switch_isr, which has been entered into the vector
* table as ISR for interrupt 1
*/
int #1
/* at this point, r0 points to the entry point, so RTS will enter it */
rts
/* void switch... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/switch.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/rx/core/switch.S:3 | popm r1-r15
rte
/* void z_rx_context_switch_isr(void *switch_to, void **switched_from)
*
* @brief switch between threads in the interrupt context
*
* @param switch_to (r1) pointer to switch handle of the new thread
* @param switched_from (r2) pointer to pointer to switch handle of the old thread
*
* si... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/switch.S | 81 | 137 |
zephyrproject-rtos/zephyr:arch/rx/core/switch.S:4 | mov r1,[r5] /* store stack pointer of old thread in *switched_from */
mov r2,r1 /* set r1 (smovf dest) to the beginning of the interrupt stack */
mov r4,r2 /* set r2 (smovf source) to the sp of the new thread*/
mov #76,r3 /* set r3 to number of bytes to move */
smovf /* block copy from new thread stack to inte... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/rx/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/rx/core/switch.S | 121 | 137 |
zephyrproject-rtos/zephyr:arch/sparc/core/fault_trap.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include <zephyr/arch/sparc/sparc.h>
GTEXT(__sparc_trap_except_reason)
GTEXT(__sparc_trap_fault)
/*
* Fault trap handler
*
* - ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/fault_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/fault_trap.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/fault_trap.S:2 | srl %g2, %l0, %g3
cmp %g3, 1
bne .Lwodone
nop
/* Do the window overflow. */
sll %g2, (CONFIG_SPARC_NWIN-1), %g3
srl %g2, 1, %g2
or %g2, %g3, %g2
/* Enter window to save. */
save
/* Install new wim calculated above. */
mov %g2, %wim
nop
nop
nop
/* Put registers on the dedicated save area of the ABI sta... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/fault_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/fault_trap.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/sparc/core/fault_trap.S:3 | mov %l7, %o0
/* Fill in the content of the exception stack frame */
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
std %i0, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x00]
std %i2, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x08]
std %i4, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x10]
std %i6, [%sp + 96 + __struct_ar... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/fault_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/fault_trap.S | 81 | 133 |
zephyrproject-rtos/zephyr:arch/sparc/core/fault_trap.S:4 | /*
* Entry for trap we don't handle explicitly
*
* Just drop into __sparc_trap_except_reason with reason set to
* K_ERR_CPU_EXCEPTION. Note that "reason" is transported in %l7 of the
* trapped-into window and global %g1 is preserved.
*/
SECTION_FUNC(TEXT, __sparc_trap_fault)
b .Ldoit
/* K_ERR_CPU_EXCEPTION */
... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/fault_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/fault_trap.S | 121 | 133 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include <zephyr/arch/sparc/sparc.h>
#include "stack_offsets.h"
GTEXT(__sparc_trap_interrupt)
GTEXT(__sparc_trap_irq_offload)
/*
... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:2 | /* %g2, %g3 are used at manual window overflow so save temporarily */
mov %g2, %l4
mov %g3, %l5
/* We may have trapped into the invalid window. If so, make it valid. */
rd %wim, %g2
srl %g2, %l0, %g3
cmp %g3, 1
bne .Lwodone
nop
/* Do the window overflow. */
sll %g2, (CONFIG_SPARC_NWIN-1), %g3
srl %g2, 1, ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:3 | * Save the state of the interrupted task including global registers on
* the task stack.
*
* IMPORTANT: Globals are saved here as well on the task stack, since a
* context switch might happen before the context of this interrupted
* task is restored.
*/
/* Allocate stack for isr context. */
sub %fp, ISF_... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:4 | #if defined(CONFIG_FPU)
/*
* We now check if the interrupted context was using the FPU. The
* result is stored in register l5 which will either get the value 0
* (FPU not used) or PSR_EF (FPU used).
*
* If the FPU was used by the interrupted context, then we do two
* things:
* 1. Store FSR to memory. Thi... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:5 | #ifdef CONFIG_TRACING_ISR
call sys_trace_isr_exit
nop
#endif
/*
* %fp: %sp of interrupted task - ISF_SIZE.
* %sp: irq stack - 96. An ABI frame
*/
#ifdef CONFIG_PREEMPT_ENABLED
/* allocate stack for calling C function and for its output value */
sub %fp, (96+8), %sp
/*
* %fp: %sp of interrupted task - I... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:6 | * - Allocate space for the FP registers above the save area used for
* the z_sparc_context_switch() call.
*/
wr %l6, %l5, %psr
nop
nop
nop
sub %sp, 34 * 4, %sp
std %f0, [%sp + 64 + 0x00]
std %f2, [%sp + 64 + 0x08]
std %f4, [%sp + 64 + 0x10]
std %f6, [%sp + 64 + 0x18]
std %f8, [%sp + 64 + 0x20]
st... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:7 | ldd [%sp + 64 + 0x58], %f22
ldd [%sp + 64 + 0x60], %f24
ldd [%sp + 64 + 0x68], %f26
ldd [%sp + 64 + 0x70], %f28
ldd [%sp + 64 + 0x78], %f30
ld [%sp + 64 + 0x80], %fsr
ba .Lno_reschedule
add %sp, 34 * 4, %sp
.Lno_fp_context:
#endif /* CONFIG_FPU_SHARING */
call z_sparc_context_switch
nop
.Lno_reschedule... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:8 | nop
nop
/* Calculate %l6 := (cwp+1) % NWIN */
rd %wim, %l3
set (CONFIG_SPARC_NWIN), %l7
add %l0, 1, %l6
and %l6, PSR_CWP, %l6
cmp %l6, %l7
bge,a .Lwrapok
mov 0, %l6
.Lwrapok:
/* Determine if we must prepare the return window. */
/* %l5 := %wim >> (cwp+1) */
srl %l3, %l6, %l5
/* %l5 is 1 if (cwp+1) is an... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 281 | 335 |
zephyrproject-rtos/zephyr:arch/sparc/core/interrupt_trap.S:9 | .Lwudone:
/*
* Restore %psr since we may have trashed condition codes. PSR.ET is
* still 0.
*/
wr %l0, %psr
nop
nop
nop
/* restore g1 */
ld [%g1 + ISF_G1_OFFSET], %g1
jmp %l1
rett %l2 | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/interrupt_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/interrupt_trap.S | 321 | 335 |
zephyrproject-rtos/zephyr:arch/sparc/core/reset_trap.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/sparc/sparc.h>
/* The trap table reset entry jumps to here. */
GTEXT(__sparc_trap_reset)
SECTION_FUNC(TEXT, __sparc_trap_reset)
#ifdef ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/reset_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/reset_trap.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/reset_trap.S:2 | * stack frame by setting the frame pointer to zero. No other frame's
* %fp has a zero value.
*/
sub %l3, 96, %sp
clr %fp
clr %i7
#ifdef CONFIG_INIT_STACKS
/* In-place memset() to avoid register window related traps. */
set 0xaaaaaaaa, %l0
mov %l0, %l1
1:
std %l0, [%g2]
add %g2, 8, %g2
cmp %g2, %l3
bne 1b... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/reset_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/reset_trap.S | 41 | 72 |
zephyrproject-rtos/zephyr:arch/sparc/core/sw_trap_set_pil.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/sparc/sparc.h>
GTEXT(__sparc_trap_sw_set_pil)
/*
* Set processor interrupt level
*
* Handler for SPARC trap 0x89: trap_instruction, ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/sw_trap_set_pil.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/sw_trap_set_pil.S | 1 | 43 |
zephyrproject-rtos/zephyr:arch/sparc/core/switch.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <offsets_short.h>
#include <zephyr/arch/sparc/sparc.h>
GTEXT(z_sparc_arch_switch)
GTEXT(z_sparc_context_switch)
GTEXT(z_thread_entry_wrapper)
/*
* ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/switch.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/switch.S:2 | std %i4, [%o1 + _thread_offset_to_i4]
std %i6, [%o1 + _thread_offset_to_i6]
std %o6, [%o1 + _thread_offset_to_o6]
rd %psr, %o4
st %o4, [%o1 + _thread_offset_to_psr]
and %o4, PSR_CWP, %g3 /* %g3 = CWP */
andn %o4, PSR_ET, %g1 /* %g1 = psr with traps disabled */
wr %g1, %psr /* disabl... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/switch.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/sparc/core/switch.S:3 | ba .Lsave_frame_loop
nop
.Ldone_flushing:
/*
* "wrpsr" is a delayed write instruction so wait three instructions
* after the write before using non-global registers or instructions
* affecting the CWP.
*/
wr %g1, %psr /* restore cwp */
nop
nop
nop
add %g3, 1, %g2 /* calculate ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/switch.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/sparc/core/switch.S:4 | ldd [%o0 + _thread_offset_to_l0_and_l1], %l0
ldd [%o0 + _thread_offset_to_l2], %l2
ldd [%o0 + _thread_offset_to_l4], %l4
ldd [%o0 + _thread_offset_to_l6], %l6
/* restore input registers */
ldd [%o0 + _thread_offset_to_i0], %i0
ldd [%o0 + _thread_offset_to_i2], %i2
ldd [%o0 + _thread_offset_to_i4], %i4
ldd [%o0... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/switch.S | 121 | 158 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_mvt.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This file contains a full SPARC V8 trap table. The processor redirects
* exection to the trap table on trap events. Each trap table entrys is four
* instructions.
*/
#include <zephyr/toolchain.h>
#include <zephyr/li... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_mvt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_mvt.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_mvt.S:2 | * Generate the "trap in trap" condition which causes the processor to halt and
* enter error mode. Typically used to stop a simulator (QEMU, TSIM) or leave
* control to a hardware debug monitor (LEON DSU via GRMON).
*/
#define TRAP_IN_TRAP \
ta 0x00; \
nop; \
nop; \
nop;
#define SOFT_TRAP BAD_TRAP
#define WOF_... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_mvt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_mvt.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_mvt.S:3 | BAD_TRAP; ! 07 mem_address_not_aligned
BAD_TRAP; ! 08 fp_exception
BAD_TRAP; ! 09 data_access_exception
BAD_TRAP; ! 0A tag_overflow
BAD_TRAP; ! 0B watchpoint_detected
BAD_TRAP; ! 0C r... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_mvt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_mvt.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_mvt.S:4 | BAD_TRAP; ! 2D reserved
BAD_TRAP; ! 2E reserved
BAD_TRAP; ! 2F reserved
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 reserved
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 reserved
BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_T... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_mvt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_mvt.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_mvt.S:5 | SOFT_TRAP; ! 6 Fix alignment
SOFT_TRAP; ! 7 Integer overflow
SOFT_TRAP ! 8 System calls
TRAP(__sparc_trap_sw_set_pil); ! 9 Reserved for the os
SOFT_TRAP; ! ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_mvt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_mvt.S | 161 | 199 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_svt.S:1 | /*
* Copyright (c) 2023 Frontgrade Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This file contains the trap entry for SPARC operating with
* single-vector trap model, defined in SPARC V8E. The processor
* redirects execution to a single entry on any trap event. From
* there, two levels of look-up... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_svt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_svt.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_svt.S:2 | and %l6, 0xf00, %l7
srl %l7, 6, %l7
set __sparc_trap_table_svt_level0, %l4
ld [%l4 + %l7], %l4
and %l6, 0x0f0, %l7
srl %l7, 2, %l7
ld [%l4 + %l7], %l4
srl %l6, 4, %l3
jmp %l4
and %l3, 0xf, %l3 /* Interrupt level */
__sparc_trap_svt_in_trap:
ta 0x00
nop
SECTION_VAR(RODATA, __sparc_trap_table_svt_tables)
... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_svt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_svt.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_svt.S:3 | .word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_window_overflow
.word __sparc_trap_window_underflow
__sparc_trap_table_svt_allbad:
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_svt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_svt.S | 81 | 138 |
zephyrproject-rtos/zephyr:arch/sparc/core/trap_table_svt.S:4 | __sparc_trap_table_svt_80:
.word __sparc_trap_svt_in_trap
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_flush_windows
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_fault
.word __sparc_trap_sw_set_pil
.word __sparc... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/trap_table_svt.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/trap_table_svt.S | 121 | 138 |
zephyrproject-rtos/zephyr:arch/sparc/core/window_trap.S:1 | /*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This file contains standard handlers for the SPARC V8 window overflow and
* underflow traps. It also implements the handler for SPARC-ABI
* "Flush windows" which is used for example by longjmp() and C++ exceptions.
*... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/window_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/window_trap.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/sparc/core/window_trap.S:2 | nop
std %i6, [%sp + 0x38]
/* Go back to trap window. */
restore
/* Re-execute save. */
jmp %l1
rett %l2
SECTION_FUNC(TEXT, __sparc_trap_window_underflow)
rd %wim, %l3
/* l4 := WIM << 1 */
sll %l3, 1, %l4
/* l5 := WIM >> (NWIN-1) */
srl %l3, (CONFIG_SPARC_NWIN-1), %l5
/* WIM := (WIM << 1) ^ (WIM >> (NWIN-1... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/window_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/window_trap.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/sparc/core/window_trap.S:3 | * Handler for SPARC trap 0x83: trap_instruction, defined as "Flush windows" by
* SPARC-ABI:
* "By executing a type 3 trap, a process asks the system to flush all its
* register windows to the stack."
*
* On entry:
* %l0: psr
* %l1: pc
* %l2: npc
*/
SECTION_FUNC(TEXT, __sparc_trap_flush_windows)
/* Save gl... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/window_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/window_trap.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/sparc/core/window_trap.S:4 | std %i4, [%sp + 0x30]
std %i6, [%sp + 0x38]
/*
* Check if next window is invalid by comparing
* (1 << ((cwp + 1) % NWIN)) with WIM
*/
.LcheckNextWindow:
set CONFIG_SPARC_NWIN, %g5
cmp %g1, %g5
bge,a .Lnowrap
sub %g1, %g5, %g1
.Lnowrap:
sll %g4, %g1, %g5
cmp %g5, %g2
be .LflushWindowDone
inc %g1
/* ... | sparc | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/sparc/core/window_trap.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/sparc/core/window_trap.S | 121 | 167 |
zephyrproject-rtos/zephyr:arch/x86/core/common.S:1 | /*
* Copyright (c) 2019 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/x86/multiboot.h>
#include <zephyr/devicetree.h>
/*
* This is included by ia32/crt0.S and intel64/locore.S
* at their 32-bit entry points to cover common ground.
*/
#ifdef CONFIG_MULTIBOOT_INFO
/*
... | x86_64 | gas-att | handwritten | zephyrproject-rtos/zephyr | arch/x86/core/common.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/common.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/x86/core/common.S:2 | movl __multiboot_info_t_cmdline_OFFSET(%ebx), %esi
copy_cmdline:
cmpl %esi, %edx
je end_cmdline
cmpb $0, (%esi)
je end_cmdline
movsb
jmp copy_cmdline
end_cmdline:
movb $0, (%edi)
#endif
#endif
#ifdef CONFIG_PIC_DISABLE
/*
* "Disable" legacy i8259 interrupt controllers. Note that we
* can't actually disab... | x86_64 | gas-att | handwritten | zephyrproject-rtos/zephyr | arch/x86/core/common.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/common.S | 41 | 83 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:1 | /*
* Copyright (c) 2010-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Crt0 module for the IA-32 boards
*
* This module contains the initial code executed by the Zephyr Kernel ELF image
* after having been loaded into RAM.
*
* Note that most addresses (functions... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:2 | #endif
#if defined(CONFIG_X86_SSE)
GDATA(_sse_mxcsr_default_value)
#endif
#if defined(CONFIG_THREAD_LOCAL_STORAGE)
GTEXT(z_x86_early_tls_update_gdt)
#endif
GDATA(x86_cpu_boot_arg)
.macro install_page_tables
#ifdef CONFIG_X86_MMU
/* Enable paging. If virtual memory is enabled, the instruction pointer
* is cur... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:3 | * this above in PAE code.
*/
movl %cr4, %eax
orl $CR4_PSE, %eax
movl %eax, %cr4
#endif /* CONFIG_X86_PAE */
/* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */
movl %cr0, %eax
orl $(CR0_PG | CR0_WP), %eax
movl %eax, %cr0
#ifdef K_MEM_IS_VM_KERNEL
/* Jump to a virtual address, which works b... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:4 | cli
/*
* Although the bootloader sets up an Interrupt Descriptor Table (IDT)
* and a Global Descriptor Table (GDT), the specification encourages
* booted operating systems to setup their own IDT and GDT.
*/
#if CONFIG_SET_GDT
/* load 32-bit operand size GDT */
lgdt K_MEM_PHYS_ADDR(_gdt_rom)
/* If we set o... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:5 | * and that _no_ handler for x87 FPU exceptions (#MF) is provided.
*/
movl %cr0, %eax /* move CR0 to EAX */
orl $0x22, %eax /* CR0[NE+MP]=1 */
andl $~0xc, %eax /* CR0[TS+EM]=0 */
movl %eax, %cr0 /* move EAX to CR0 */
fninit /* set x87 FPU to its default state */
#if defined(CONFIG_X86_SSE)
/*
* Per... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:6 | */
#ifdef CONFIG_INIT_STACKS
movl $0xAAAAAAAA, %eax
leal K_MEM_PHYS_ADDR(z_interrupt_stacks), %edi
#ifdef CONFIG_X86_STACK_PROTECTION
addl $4096, %edi
#endif
stack_size_dwords = (CONFIG_ISR_STACK_SIZE / 4)
movl $stack_size_dwords, %ecx
rep stosl
#endif
movl $K_MEM_PHYS_ADDR(z_interrupt_stacks), %esp
#ifdef CON... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:7 | #endif
#if defined(CONFIG_X86_ENABLE_TSS)
mov $MAIN_TSS, %ax
ltr %ax
#endif
#ifdef K_MEM_IS_VM_KERNEL
/* Need to reset the stack to virtual address after
* page table is loaded.
*/
movl $z_interrupt_stacks, %esp
#ifdef CONFIG_X86_STACK_PROTECTION
addl $(CONFIG_ISR_STACK_SIZE + 4096), %esp
#else
addl $CONFI... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:8 | #ifdef CONFIG_X86_CET
call z_x86_cet_enable
#ifdef CONFIG_X86_CET_IBT
call z_x86_ibt_enable
#endif
#ifdef CONFIG_HW_SHADOW_STACK
call z_x86_set_irq_shadow_stack
#endif
#endif
/* load 32-bit operand size IDT */
lidt z_x86_idt
movl $x86_cpu_boot_arg, %ebp
/* Boot type to multiboot, ebx content will help to mitig... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:9 | * setup by the BIOS (or GRUB?).
*/
/* IDT table start address */
.long _idt_base_address
#ifdef CONFIG_SET_GDT
/*
* The following 3 GDT entries implement the so-called "basic
* flat model", i.e. a single code segment descriptor and a single
* data segment descriptor, giving the kernel access to a continuo... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/crt0.S:10 | /* Limit on GDT */
.word K_MEM_PHYS_ADDR(_gdt_rom_end) - K_MEM_PHYS_ADDR(_gdt_rom) - 1
/* table address: _gdt_rom */
.long K_MEM_PHYS_ADDR(_gdt_rom)
.word 0x0000
/* Entry 1 (selector=0x0008): Code descriptor: DPL0 */
.word 0xffff /* limit: xffff */
.word 0x0000 /* base : xxxx0000 */
.byte 0x00 /* b... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/crt0.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/crt0.S | 361 | 386 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/excstub.S:3 | * ESP -> ECX (excepting task)
* Exception Error code (or junk)
* EIP (excepting task)
* CS (excepting task)
* EFLAGS (excepting task)
* ...
*
* ECX now contains the address of the handler function */
/*
* Push the remaining volatile registers on the existing stack.
*/
pushl %eax
pushl %... | x86_64 | gas-att | handwritten | zephyrproject-rtos/zephyr | arch/x86/core/ia32/excstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/excstub.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/excstub.S:4 | 2:
#endif
#ifdef CONFIG_GDBSTUB
pushl %ds
pushl %es
pushl %fs
pushl %gs
pushl %ss
#endif
/* ESP is pointing to the ESF at this point */
#if defined(CONFIG_LAZY_FPU_SHARING)
movl _kernel + _kernel_offset_to_current, %edx
/* inc exception nest count */
incl _thread_offset_to_excNestCount(%edx)
/*
* Set X... | x86_64 | gas-att | handwritten | zephyrproject-rtos/zephyr | arch/x86/core/ia32/excstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/excstub.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/excstub.S:5 | /* ESP is still pointing to the ESF at this point */
testl $0x200, __struct_arch_esf_eflags_OFFSET(%esp)
je allDone
sti
allDone:
pushl %esp /* push struct_arch_esf * parameter */
call *%ecx /* call exception handler */
addl $0x4, %esp
#if defined(CONFIG_LAZY_FPU_SHARING)
movl _kernel + _kernel_offset_to_... | x86_64 | gas-att | handwritten | zephyrproject-rtos/zephyr | arch/x86/core/ia32/excstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/excstub.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/excstub.S:6 | nestedException:
#endif /* CONFIG_LAZY_FPU_SHARING */
#ifdef CONFIG_GDBSTUB
popl %ss
popl %gs
popl %fs
popl %es
popl %ds
#endif
/*
* Pop the non-volatile registers from the stack.
* Note that debug tools may have altered the saved register values while
* the task was stopped, and we want to pick up the alt... | x86_64 | gas-att | handwritten | zephyrproject-rtos/zephyr | arch/x86/core/ia32/excstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/excstub.S | 201 | 239 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:3 | * 4 isr_param
* 0 isr <-- stack pointer
*/
/*
* The gen_idt tool creates an interrupt-gate descriptor for
* all connections. The processor will automatically clear the IF
* bit in the EFLAGS register upon execution of the handler, hence
* this need not issue an 'cli' as the first instruction.
*
... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:4 | * Also it helps in stack unwinding
* Rest of the callee-saved regs get saved by invocation of C
* functions (isr handler, arch_swap(), etc)
*/
pushl %ebp
pushl %edi
pushl %ebx
/* load %ecx with &_kernel */
movl $_kernel, %ecx
/* switch to the interrupt stack for the non-nested case */
incl _kernel_offs... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:5 | * Note that first scratch register will contain SSP after this
* macro runs.
*/
save_ssp_restore_token %ebx, %edi
movl %ebx, _thread_offset_to_shstk_addr(%ebp)
#ifdef CONFIG_X86_CET_SOC_PREPARE_SHADOW_STACK_SWITCH
pushl %eax
pushl %edx
pushl %ecx
soc_prepare_irq_shadow_stack_switch
popl %ecx
popl %edx
pop... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:6 | #endif
#ifdef CONFIG_PM
cmpl $0, _kernel_offset_to_idle(%ecx)
jne handle_idle
/* fast path is !idle, in the pipeline */
#endif /* CONFIG_PM */
/* fall through to nested case */
alreadyOnIntStack:
push %eax /* interrupt handler argument */
#if defined(CONFIG_TRACING_ISR)
/* Save these as we are using to keep ... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:7 | #if defined(CONFIG_X86_RUNTIME_IRQ_STATS)
/*
* The runtime_irq_stats() function should be implemented
* by platform with this config.
*/
pushl %eax
call runtime_irq_stats
popl %eax
#endif
xorl %eax, %eax
#if defined(CONFIG_X2APIC)
xorl %edx, %edx
movl $(X86_X2APIC_BASE_MSR + (LOAPIC_EOI >> 4)), %ecx
wr... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:8 | * debug tools that a preemptive context switch has occurred.
*/
#if defined(CONFIG_LAZY_FPU_SHARING)
orb $X86_THREAD_FLAG_INT, _thread_offset_to_flags(%edx)
#endif
/*
* A context reschedule is required: keep the volatile registers of
* the interrupted thread on the context's stack. Utilize
* the existing a... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:9 | call z_check_stack_sentinel
#endif
pushfl /* push KERNEL_LOCK_KEY argument */
call arch_swap
addl $4, %esp /* pop KERNEL_LOCK_KEY argument */
/*
* The interrupted thread has now been scheduled,
* as the result of a _later_ invocation of arch_swap().
*
* Now need to restore the interrupted thread's envir... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:10 | /*
* A thread reschedule is not required; switch back to the
* interrupted thread's stack and restore volatile registers
*/
#ifdef CONFIG_HW_SHADOW_STACK
movl _kernel_offset_to_current(%ecx), %ebp
cmpl $0, _thread_offset_to_shstk_addr(%ebp)
jz __sh_stk_out_no_reschedule
/* No need to save SSP on _kernel as ... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:11 | */
nestedInterrupt:
popl %ebx
popl %edi
popl %ebp
popl %ecx /* pop volatile registers in reverse order */
popl %edx
popl %eax
/* Pop of EFLAGS will re-enable interrupts and restore direction flag */
KPTI_IRET
#ifdef CONFIG_PM
handle_idle:
pushl %eax
pushl %edx
/* Zero out _kernel.idle */
movl $0, _kerne... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:12 | * former stub is connected to exception vectors where the processor pushes an
* error code onto the stack (or kernel stack) in addition to the EFLAGS/CS/EIP
* records.
*
* A spurious interrupt is considered a fatal condition; there is no provision
* to return to the interrupted execution context and thus the volat... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:13 | pushl %esi
pushl %ebx
pushl %ebp
leal 44(%esp), %ecx /* Calculate ESP before exception occurred */
pushl %ecx /* Save calculated ESP */
pushl %esp /* push cur stack pointer: pEsf arg */
/* re-enable interrupts */
sti
/* call the fatal error handler */
call z_x86_spurious_irq
/* handler doe... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/x86/core/ia32/intstub.S:14 | * Create nice labels for all the stubs so we can see where we
* are in a debugger
*/
.altmacro
.macro __INT_STUB_NUM id
z_dynamic_irq_stub_\id:
.endm
.macro INT_STUB_NUM id
__INT_STUB_NUM %id
.endm
z_dynamic_stubs_begin:
stub_num = 0
.rept ((CONFIG_X86_DYNAMIC_IRQ_STUBS + Z_DYN_STUB_PER_BLOCK - 1) / Z_DYN_STUB_PER_B... | x86_64 | gas-att | macro-heavy | zephyrproject-rtos/zephyr | arch/x86/core/ia32/intstub.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/x86/core/ia32/intstub.S | 521 | 567 |
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