code
stringlengths 1
2.01M
| repo_name
stringlengths 3
62
| path
stringlengths 1
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| language
stringclasses 231
values | license
stringclasses 13
values | size
int64 1
2.01M
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|---|---|---|---|---|---|
/*
* INET An implementation of the TCP/IP protocol suite for the LINUX
* operating system. INET is implemented using the BSD Socket
* interface as the means of communication with the user level.
*
* Definitions for the Interfaces handler.
*
* Version: @(#)dev.h 1.0.10 08/12/93
*
* Authors: Ross Biro
* Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
* Corey Minyard <wf-rch!minyard@relay.EU.net>
* Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
* Alan Cox, <Alan.Cox@linux.org>
* Bjorn Ekwall. <bj0rn@blox.se>
* Pekka Riikonen <priikone@poseidon.pspt.fi>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Moved to /usr/include/linux for NET3
*/
#ifndef _LINUX_NETDEVICE_H
#define _LINUX_NETDEVICE_H
/*
* Network device statistics. Akin to the 2.0 ether stats but
* with byte counters.
*/
struct net_device_stats {
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
#endif /* _LINUX_NETDEVICE_H */
|
1001-study-uboot
|
include/linux/netdevice.h
|
C
|
gpl3
| 2,318
|
#ifndef __LINUX_COMPILER_H
#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead."
#endif
/* GCC 4.1.[01] miscompiles __weak */
#ifdef __KERNEL__
# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1
# error Your version of gcc miscompiles the __weak directive
# endif
#endif
#define __used __attribute__((__used__))
#define __must_check __attribute__((warn_unused_result))
#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
#define __always_inline inline __attribute__((always_inline))
/*
* A trick to suppress uninitialized variable warning without generating any
* code
*/
#define uninitialized_var(x) x = x
#if __GNUC_MINOR__ >= 3
/* Mark functions as cold. gcc will assume any path leading to a call
to them will be unlikely. This means a lot of manual unlikely()s
are unnecessary now for any paths leading to the usual suspects
like BUG(), printk(), panic() etc. [but let's keep them for now for
older compilers]
Early snapshots of gcc 4.3 don't support this and we can't detect this
in the preprocessor, but we can live with this because they're unreleased.
Maketime probing would be overkill here.
gcc also has a __attribute__((__hot__)) to move hot functions into
a special section, but I don't see any sense in this right now in
the kernel context */
#define __cold __attribute__((__cold__))
#if __GNUC_MINOR__ >= 5
/*
* Mark a position in code as unreachable. This can be used to
* suppress control flow warnings after asm blocks that transfer
* control elsewhere.
*
* Early snapshots of gcc 4.5 don't support this and we can't detect
* this in the preprocessor, but we can live with this because they're
* unreleased. Really, we need to have autoconf for the kernel.
*/
#define unreachable() __builtin_unreachable()
#endif
#endif
#if __GNUC_MINOR__ > 0
#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
#endif
#if __GNUC_MINOR__ >= 4
#define __compiletime_warning(message) __attribute__((warning(message)))
#define __compiletime_error(message) __attribute__((error(message)))
#endif
|
1001-study-uboot
|
include/linux/compiler-gcc4.h
|
C
|
gpl3
| 2,125
|
/*
* linux/include/linux/mtd/onenand.h
*
* Copyright (C) 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MTD_ONENAND_H
#define __LINUX_MTD_ONENAND_H
#include <linux/mtd/onenand_regs.h>
/* Note: The header order is impoertant */
#include <onenand_uboot.h>
#include <linux/mtd/compat.h>
#include <linux/mtd/bbm.h>
#define MAX_DIES 2
#define MAX_BUFFERRAM 2
#define MAX_ONENAND_PAGESIZE (4096 + 128)
/* Scan and identify a OneNAND device */
extern int onenand_scan (struct mtd_info *mtd, int max_chips);
/* Free resources held by the OneNAND device */
extern void onenand_release (struct mtd_info *mtd);
/**
* struct onenand_bufferram - OneNAND BufferRAM Data
* @param blockpage block & page address in BufferRAM
*/
struct onenand_bufferram {
int blockpage;
};
/**
* struct onenand_chip - OneNAND Private Flash Chip Data
* @param base [BOARDSPECIFIC] address to access OneNAND
* @dies: [INTERN][FLEXONENAND] number of dies on chip
* @boundary: [INTERN][FLEXONENAND] Boundary of the dies
* @diesize: [INTERN][FLEXONENAND] Size of the dies
* @param chipsize [INTERN] the size of one chip for multichip arrays
* @param device_id [INTERN] device ID
* @param verstion_id [INTERN] version ID
* @technology [INTERN] describes the internal NAND array technology such as SLC or MLC.
* @density_mask: [INTERN] chip density, used for DDP devices
* @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
* @param erase_shift [INTERN] number of address bits in a block
* @param page_shift [INTERN] number of address bits in a page
* @param ppb_shift [INTERN] number of address bits in a pages per block
* @param page_mask [INTERN] a page per block mask
* @param writesize [INTERN] a real page size
* @param bufferam_index [INTERN] BufferRAM index
* @param bufferam [INTERN] BufferRAM info
* @param readw [REPLACEABLE] hardware specific function for read short
* @param writew [REPLACEABLE] hardware specific function for write short
* @param command [REPLACEABLE] hardware specific function for writing commands to the chip
* @param wait [REPLACEABLE] hardware specific function for wait on ready
* @param read_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
* @param write_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
* @param chip_lock [INTERN] spinlock used to protect access to this structure and the chip
* @param wq [INTERN] wait queue to sleep on if a OneNAND operation is in progress
* @param state [INTERN] the current state of the OneNAND device
* @param autooob [REPLACEABLE] the default (auto)placement scheme
* @param priv [OPTIONAL] pointer to private chip date
*/
struct onenand_chip {
void __iomem *base;
unsigned int dies;
unsigned int boundary[MAX_DIES];
unsigned int diesize[MAX_DIES];
unsigned int chipsize;
unsigned int device_id;
unsigned int version_id;
unsigned int technology;
unsigned int density_mask;
unsigned int options;
unsigned int erase_shift;
unsigned int page_shift;
unsigned int ppb_shift; /* Pages per block shift */
unsigned int page_mask;
unsigned int writesize;
unsigned int bufferram_index;
struct onenand_bufferram bufferram[MAX_BUFFERRAM];
int (*command) (struct mtd_info *mtd, int cmd, loff_t address,
size_t len);
int (*wait) (struct mtd_info *mtd, int state);
int (*bbt_wait) (struct mtd_info *mtd, int state);
void (*unlock_all)(struct mtd_info *mtd);
int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
unsigned char *buffer, int offset, size_t count);
int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
const unsigned char *buffer, int offset,
size_t count);
unsigned short (*read_word) (void __iomem *addr);
void (*write_word) (unsigned short value, void __iomem *addr);
void (*mmcontrol) (struct mtd_info *mtd, int sync_read);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
int (*scan_bbt)(struct mtd_info *mtd);
unsigned char *main_buf;
unsigned char *spare_buf;
#ifdef DONT_USE_UBOOT
spinlock_t chip_lock;
wait_queue_head_t wq;
#endif
int state;
unsigned char *page_buf;
unsigned char *oob_buf;
struct nand_oobinfo *autooob;
int subpagesize;
struct nand_ecclayout *ecclayout;
void *bbm;
void *priv;
};
/*
* Helper macros
*/
#define ONENAND_CURRENT_BUFFERRAM(this) (this->bufferram_index)
#define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1)
#define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1)
#define ONENAND_SET_PREV_BUFFERRAM(this) (this->bufferram_index ^= 1)
#define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0)
#define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1)
#define FLEXONENAND(this) (this->device_id & DEVICE_IS_FLEXONENAND)
#define ONENAND_IS_MLC(this) (this->technology & ONENAND_TECHNOLOGY_IS_MLC)
#define ONENAND_IS_DDP(this) \
(this->device_id & ONENAND_DEVICE_IS_DDP)
#define ONENAND_IS_2PLANE(this) (0)
/*
* Options bits
*/
#define ONENAND_HAS_CONT_LOCK (0x0001)
#define ONENAND_HAS_UNLOCK_ALL (0x0002)
#define ONENAND_HAS_2PLANE (0x0004)
#define ONENAND_RUNTIME_BADBLOCK_CHECK (0x0200)
#define ONENAND_PAGEBUF_ALLOC (0x1000)
#define ONENAND_OOBBUF_ALLOC (0x2000)
/*
* OneNAND Flash Manufacturer ID Codes
*/
#define ONENAND_MFR_NUMONYX 0x20
#define ONENAND_MFR_SAMSUNG 0xec
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
* @param name: Manufacturer name
* @param id: manufacturer ID code of device.
*/
struct onenand_manufacturers {
int id;
char *name;
};
int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops);
unsigned int onenand_block(struct onenand_chip *this, loff_t addr);
int flexonenand_region(struct mtd_info *mtd, loff_t addr);
#endif /* __LINUX_MTD_ONENAND_H */
|
1001-study-uboot
|
include/linux/mtd/onenand.h
|
C
|
gpl3
| 6,125
|
/*
* (C) 1999-2003 David Woodhouse <dwmw2@infradead.org>
*/
#ifndef __MTD_NFTL_H__
#define __MTD_NFTL_H__
#include <linux/mtd/mtd.h>
#include <linux/mtd/blktrans.h>
#include <linux/mtd/nftl-user.h>
/* these info are used in ReplUnitTable */
#define BLOCK_NIL 0xffff /* last block of a chain */
#define BLOCK_FREE 0xfffe /* free block */
#define BLOCK_NOTEXPLORED 0xfffd /* non explored block, only used during mounting */
#define BLOCK_RESERVED 0xfffc /* bios block or bad block */
struct NFTLrecord {
struct mtd_blktrans_dev mbd;
__u16 MediaUnit, SpareMediaUnit;
__u32 EraseSize;
struct NFTLMediaHeader MediaHdr;
int usecount;
unsigned char heads;
unsigned char sectors;
unsigned short cylinders;
__u16 numvunits;
__u16 lastEUN; /* should be suppressed */
__u16 numfreeEUNs;
__u16 LastFreeEUN; /* To speed up finding a free EUN */
int head,sect,cyl;
__u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */
__u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */
unsigned int nb_blocks; /* number of physical blocks */
unsigned int nb_boot_blocks; /* number of blocks used by the bios */
struct erase_info instr;
struct nand_ecclayout oobinfo;
};
int NFTL_mount(struct NFTLrecord *s);
int NFTL_formatblock(struct NFTLrecord *s, int block);
int nftl_read_oob(struct mtd_info *mtd, loff_t offs, size_t len,
size_t *retlen, uint8_t *buf);
int nftl_write_oob(struct mtd_info *mtd, loff_t offs, size_t len,
size_t *retlen, uint8_t *buf);
#ifndef NFTL_MAJOR
#define NFTL_MAJOR 93
#endif
#define MAX_NFTLS 16
#define MAX_SECTORS_PER_UNIT 64
#define NFTL_PARTN_BITS 4
#endif /* __MTD_NFTL_H__ */
|
1001-study-uboot
|
include/linux/mtd/nftl.h
|
C
|
gpl3
| 1,664
|
#ifndef _LINUX_COMPAT_H_
#define _LINUX_COMPAT_H_
#define __user
#define __iomem
#define ndelay(x) udelay(1)
#define printk printf
#define KERN_EMERG
#define KERN_ALERT
#define KERN_CRIT
#define KERN_ERR
#define KERN_WARNING
#define KERN_NOTICE
#define KERN_INFO
#define KERN_DEBUG
#define kmalloc(size, flags) malloc(size)
#define kzalloc(size, flags) calloc(size, 1)
#define vmalloc(size) malloc(size)
#define kfree(ptr) free(ptr)
#define vfree(ptr) free(ptr)
#define DECLARE_WAITQUEUE(...) do { } while (0)
#define add_wait_queue(...) do { } while (0)
#define remove_wait_queue(...) do { } while (0)
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
/*
* ..and if you can't take the strict
* types, you can specify one yourself.
*
* Or not use min/max at all, of course.
*/
#define min_t(type,x,y) \
({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
#define max_t(type,x,y) \
({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
#ifndef BUG
#define BUG() do { \
printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
} while (0)
#define BUG_ON(condition) do { if (condition) BUG(); } while(0)
#endif /* BUG */
#define PAGE_SIZE 4096
#endif
|
1001-study-uboot
|
include/linux/mtd/compat.h
|
C
|
gpl3
| 1,196
|
/*
* $Id: jffs2-user.h,v 1.1 2004/05/05 11:57:54 dwmw2 Exp $
*
* JFFS2 definitions for use in user space only
*/
#ifndef __JFFS2_USER_H__
#define __JFFS2_USER_H__
/* This file is blessed for inclusion by userspace */
#include <linux/jffs2.h>
#include <endian.h>
#include <byteswap.h>
#undef cpu_to_je16
#undef cpu_to_je32
#undef cpu_to_jemode
#undef je16_to_cpu
#undef je32_to_cpu
#undef jemode_to_cpu
extern int target_endian;
#define t16(x) ({ uint16_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_16(__b); })
#define t32(x) ({ uint32_t __b = (x); (target_endian==__BYTE_ORDER)?__b:bswap_32(__b); })
#define cpu_to_je16(x) ((jint16_t){t16(x)})
#define cpu_to_je32(x) ((jint32_t){t32(x)})
#define cpu_to_jemode(x) ((jmode_t){t32(x)})
#define je16_to_cpu(x) (t16((x).v16))
#define je32_to_cpu(x) (t32((x).v32))
#define jemode_to_cpu(x) (t32((x).m))
#endif /* __JFFS2_USER_H__ */
|
1001-study-uboot
|
include/linux/mtd/jffs2-user.h
|
C
|
gpl3
| 897
|
/*
* $Id: mtd-abi.h,v 1.13 2005/11/07 11:14:56 gleixner Exp $
*
* Portions of MTD ABI definition which are shared by kernel and user space
*/
#ifndef __MTD_ABI_H__
#define __MTD_ABI_H__
#if 1
#include <linux/mtd/compat.h>
#endif
struct erase_info_user {
uint32_t start;
uint32_t length;
};
struct mtd_oob_buf {
uint32_t start;
uint32_t length;
unsigned char __user *ptr;
};
#define MTD_ABSENT 0
#define MTD_RAM 1
#define MTD_ROM 2
#define MTD_NORFLASH 3
#define MTD_NANDFLASH 4
#define MTD_DATAFLASH 6
#define MTD_UBIVOLUME 7
#define MTD_WRITEABLE 0x400 /* Device is writeable */
#define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */
#define MTD_NO_ERASE 0x1000 /* No erase necessary */
#define MTD_STUPID_LOCK 0x2000 /* Always locked after reset */
/* Some common devices / combinations of capabilities */
#define MTD_CAP_ROM 0
#define MTD_CAP_RAM (MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE)
#define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE)
#define MTD_CAP_NANDFLASH (MTD_WRITEABLE)
/* ECC byte placement */
#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */
#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */
#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */
#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */
#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */
/* OTP mode selection */
#define MTD_OTP_OFF 0
#define MTD_OTP_FACTORY 1
#define MTD_OTP_USER 2
struct mtd_info_user {
uint8_t type;
uint32_t flags;
uint32_t size; /* Total size of the MTD */
uint32_t erasesize;
uint32_t writesize;
uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */
/* The below two fields are obsolete and broken, do not use them
* (TODO: remove at some point) */
uint32_t ecctype;
uint32_t eccsize;
};
struct region_info_user {
uint32_t offset; /* At which this region starts,
* from the beginning of the MTD */
uint32_t erasesize; /* For this region */
uint32_t numblocks; /* Number of blocks in this region */
uint32_t regionindex;
};
struct otp_info {
uint32_t start;
uint32_t length;
uint32_t locked;
};
#define MEMGETINFO _IOR('M', 1, struct mtd_info_user)
#define MEMERASE _IOW('M', 2, struct erase_info_user)
#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf)
#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf)
#define MEMLOCK _IOW('M', 5, struct erase_info_user)
#define MEMUNLOCK _IOW('M', 6, struct erase_info_user)
#define MEMGETREGIONCOUNT _IOR('M', 7, int)
#define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user)
#define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo)
#define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo)
#define MEMGETBADBLOCK _IOW('M', 11, loff_t)
#define MEMSETBADBLOCK _IOW('M', 12, loff_t)
#define OTPSELECT _IOR('M', 13, int)
#define OTPGETREGIONCOUNT _IOW('M', 14, int)
#define OTPGETREGIONINFO _IOW('M', 15, struct otp_info)
#define OTPLOCK _IOR('M', 16, struct otp_info)
#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout)
#define ECCGETSTATS _IOR('M', 18, struct mtd_ecc_stats)
#define MTDFILEMODE _IO('M', 19)
/*
* Obsolete legacy interface. Keep it in order not to break userspace
* interfaces
*/
struct nand_oobinfo {
uint32_t useecc;
uint32_t eccbytes;
uint32_t oobfree[8][2];
uint32_t eccpos[48];
};
struct nand_oobfree {
uint32_t offset;
uint32_t length;
};
#define MTD_MAX_OOBFREE_ENTRIES 8
/*
* ECC layout control structure. Exported to userspace for
* diagnosis and to allow creation of raw images
*/
struct nand_ecclayout {
uint32_t eccbytes;
uint32_t eccpos[128];
uint32_t oobavail;
struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
};
/**
* struct mtd_ecc_stats - error correction stats
*
* @corrected: number of corrected bits
* @failed: number of uncorrectable errors
* @badblocks: number of bad blocks in this partition
* @bbtblocks: number of blocks reserved for bad block tables
*/
struct mtd_ecc_stats {
uint32_t corrected;
uint32_t failed;
uint32_t badblocks;
uint32_t bbtblocks;
};
/*
* Read/write file modes for access to MTD
*/
enum mtd_file_modes {
MTD_MODE_NORMAL = MTD_OTP_OFF,
MTD_MODE_OTP_FACTORY = MTD_OTP_FACTORY,
MTD_MODE_OTP_USER = MTD_OTP_USER,
MTD_MODE_RAW,
};
#endif /* __MTD_ABI_H__ */
|
1001-study-uboot
|
include/linux/mtd/mtd-abi.h
|
C
|
gpl3
| 4,431
|
/*
* linux/include/linux/mtd/ndfc.h
*
* Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Info:
* Contains defines, datastructures for ndfc nand controller
*
*/
#ifndef __LINUX_MTD_NDFC_H
#define __LINUX_MTD_NDFC_H
/* NDFC Register definitions */
#define NDFC_CMD 0x00
#define NDFC_ALE 0x04
#define NDFC_DATA 0x08
#define NDFC_ECC 0x10
#define NDFC_BCFG0 0x30
#define NDFC_BCFG1 0x34
#define NDFC_BCFG2 0x38
#define NDFC_BCFG3 0x3c
#define NDFC_CCR 0x40
#define NDFC_STAT 0x44
#define NDFC_HWCTL 0x48
#define NDFC_REVID 0x50
#define NDFC_STAT_IS_READY 0x01000000
#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
#define NDFC_MAX_BANKS 4
struct ndfc_controller_settings {
uint32_t ccr_settings;
uint64_t ndfc_erpn;
};
struct ndfc_chip_settings {
uint32_t bank_settings;
};
#endif
|
1001-study-uboot
|
include/linux/mtd/ndfc.h
|
C
|
gpl3
| 2,257
|
/*
* (C) 2003 David Woodhouse <dwmw2@infradead.org>
*
* Interface to Linux block layer for MTD 'translation layers'.
*
*/
#ifndef __MTD_TRANS_H__
#define __MTD_TRANS_H__
/* XXX U-BOOT XXX */
#if 0
#include <linux/mutex.h>
#else
#include <linux/list.h>
#endif
struct hd_geometry;
struct mtd_info;
struct mtd_blktrans_ops;
struct file;
struct inode;
struct mtd_blktrans_dev {
struct mtd_blktrans_ops *tr;
struct list_head list;
struct mtd_info *mtd;
/* XXX U-BOOT XXX */
#if 0
struct mutex lock;
#endif
int devnum;
unsigned long size;
int readonly;
void *blkcore_priv; /* gendisk in 2.5, devfs_handle in 2.4 */
};
struct blkcore_priv; /* Differs for 2.4 and 2.5 kernels; private */
struct mtd_blktrans_ops {
char *name;
int major;
int part_bits;
int blksize;
int blkshift;
/* Access functions */
int (*readsect)(struct mtd_blktrans_dev *dev,
unsigned long block, char *buffer);
int (*writesect)(struct mtd_blktrans_dev *dev,
unsigned long block, char *buffer);
/* Block layer ioctls */
int (*getgeo)(struct mtd_blktrans_dev *dev, struct hd_geometry *geo);
int (*flush)(struct mtd_blktrans_dev *dev);
/* Called with mtd_table_mutex held; no race with add/remove */
int (*open)(struct mtd_blktrans_dev *dev);
int (*release)(struct mtd_blktrans_dev *dev);
/* Called on {de,}registration and on subsequent addition/removal
of devices, with mtd_table_mutex held. */
void (*add_mtd)(struct mtd_blktrans_ops *tr, struct mtd_info *mtd);
void (*remove_dev)(struct mtd_blktrans_dev *dev);
struct list_head devs;
struct list_head list;
struct module *owner;
struct mtd_blkcore_priv *blkcore_priv;
};
extern int register_mtd_blktrans(struct mtd_blktrans_ops *tr);
extern int deregister_mtd_blktrans(struct mtd_blktrans_ops *tr);
extern int add_mtd_blktrans_dev(struct mtd_blktrans_dev *dev);
extern int del_mtd_blktrans_dev(struct mtd_blktrans_dev *dev);
#endif /* __MTD_TRANS_H__ */
|
1001-study-uboot
|
include/linux/mtd/blktrans.h
|
C
|
gpl3
| 1,936
|
/*
* MTD device concatenation layer definitions
*
* (C) 2002 Robert Kaiser <rkaiser@sysgo.de>
*
* This code is GPL
*/
#ifndef MTD_CONCAT_H
#define MTD_CONCAT_H
struct mtd_info *mtd_concat_create(
struct mtd_info *subdev[], /* subdevices to concatenate */
int num_devs, /* number of subdevices */
const char *name); /* name for the new device */
void mtd_concat_destroy(struct mtd_info *mtd);
#endif
|
1001-study-uboot
|
include/linux/mtd/concat.h
|
C
|
gpl3
| 452
|
/*
* linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
* Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Info:
* Contains standard defines and IDs for NAND flash devices
*
* Changelog:
* See git changelog.
*/
#ifndef __LINUX_MTD_NAND_H
#define __LINUX_MTD_NAND_H
/* XXX U-BOOT XXX */
#if 0
#include <linux/wait.h>
#include <linux/spinlock.h>
#include <linux/mtd/mtd.h>
#endif
#include "config.h"
#include "linux/mtd/compat.h"
#include "linux/mtd/mtd.h"
#include "linux/mtd/bbm.h"
struct mtd_info;
struct nand_flash_dev;
/* Scan and identify a NAND device */
extern int nand_scan (struct mtd_info *mtd, int max_chips);
/* Separate phases of nand_scan(), allowing board driver to intervene
* and override command or ECC setup according to flash type */
extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
const struct nand_flash_dev *table);
extern int nand_scan_tail(struct mtd_info *mtd);
/* Free resources held by the NAND device */
extern void nand_release (struct mtd_info *mtd);
/* Internal helper for board drivers which need to override command function */
extern void nand_wait_ready(struct mtd_info *mtd);
/* This constant declares the max. oobsize / page, which
* is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly.
*/
#define NAND_MAX_OOBSIZE 218
#define NAND_MAX_PAGESIZE 4096
/*
* Constants for hardware specific CLE/ALE/NCE function
*
* These are bits which can be or'ed to set/clear multiple
* bits in one go.
*/
/* Select the chip by setting nCE to low */
#define NAND_NCE 0x01
/* Select the command latch by setting CLE to high */
#define NAND_CLE 0x02
/* Select the address latch by setting ALE to high */
#define NAND_ALE 0x04
#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
#define NAND_CTRL_CHANGE 0x80
/*
* Standard NAND flash commands
*/
#define NAND_CMD_READ0 0
#define NAND_CMD_READ1 1
#define NAND_CMD_RNDOUT 5
#define NAND_CMD_PAGEPROG 0x10
#define NAND_CMD_READOOB 0x50
#define NAND_CMD_ERASE1 0x60
#define NAND_CMD_STATUS 0x70
#define NAND_CMD_STATUS_MULTI 0x71
#define NAND_CMD_SEQIN 0x80
#define NAND_CMD_RNDIN 0x85
#define NAND_CMD_READID 0x90
#define NAND_CMD_PARAM 0xec
#define NAND_CMD_ERASE2 0xd0
#define NAND_CMD_RESET 0xff
/* Extended commands for large page devices */
#define NAND_CMD_READSTART 0x30
#define NAND_CMD_RNDOUTSTART 0xE0
#define NAND_CMD_CACHEDPROG 0x15
/* Extended commands for AG-AND device */
/*
* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
* there is no way to distinguish that from NAND_CMD_READ0
* until the remaining sequence of commands has been completed
* so add a high order bit and mask it off in the command.
*/
#define NAND_CMD_DEPLETE1 0x100
#define NAND_CMD_DEPLETE2 0x38
#define NAND_CMD_STATUS_MULTI 0x71
#define NAND_CMD_STATUS_ERROR 0x72
/* multi-bank error status (banks 0-3) */
#define NAND_CMD_STATUS_ERROR0 0x73
#define NAND_CMD_STATUS_ERROR1 0x74
#define NAND_CMD_STATUS_ERROR2 0x75
#define NAND_CMD_STATUS_ERROR3 0x76
#define NAND_CMD_STATUS_RESET 0x7f
#define NAND_CMD_STATUS_CLEAR 0xff
#define NAND_CMD_NONE -1
/* Status bits */
#define NAND_STATUS_FAIL 0x01
#define NAND_STATUS_FAIL_N1 0x02
#define NAND_STATUS_TRUE_READY 0x20
#define NAND_STATUS_READY 0x40
#define NAND_STATUS_WP 0x80
/*
* Constants for ECC_MODES
*/
typedef enum {
NAND_ECC_NONE,
NAND_ECC_SOFT,
NAND_ECC_HW,
NAND_ECC_HW_SYNDROME,
NAND_ECC_HW_OOB_FIRST,
} nand_ecc_modes_t;
/*
* Constants for Hardware ECC
*/
/* Reset Hardware ECC for read */
#define NAND_ECC_READ 0
/* Reset Hardware ECC for write */
#define NAND_ECC_WRITE 1
/* Enable Hardware ECC before syndrom is read back from flash */
#define NAND_ECC_READSYN 2
/* Bit mask for flags passed to do_nand_read_ecc */
#define NAND_GET_DEVICE 0x80
/* Option constants for bizarre disfunctionality and real
* features
*/
/* Chip can not auto increment pages */
#define NAND_NO_AUTOINCR 0x00000001
/* Buswitdh is 16 bit */
#define NAND_BUSWIDTH_16 0x00000002
/* Device supports partial programming without padding */
#define NAND_NO_PADDING 0x00000004
/* Chip has cache program function */
#define NAND_CACHEPRG 0x00000008
/* Chip has copy back function */
#define NAND_COPYBACK 0x00000010
/* AND Chip which has 4 banks and a confusing page / block
* assignment. See Renesas datasheet for further information */
#define NAND_IS_AND 0x00000020
/* Chip has a array of 4 pages which can be read without
* additional ready /busy waits */
#define NAND_4PAGE_ARRAY 0x00000040
/* Chip requires that BBT is periodically rewritten to prevent
* bits from adjacent blocks from 'leaking' in altering data.
* This happens with the Renesas AG-AND chips, possibly others. */
#define BBT_AUTO_REFRESH 0x00000080
/* Chip does not require ready check on read. True
* for all large page devices, as they do not support
* autoincrement.*/
#define NAND_NO_READRDY 0x00000100
/* Chip does not allow subpage writes */
#define NAND_NO_SUBPAGE_WRITE 0x00000200
/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS \
(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
/* Macros to identify the above */
#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
/* Large page NAND with SOFT_ECC should support subpage reads */
#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
&& (chip->page_shift > 9))
/* Mask to zero out the chip options, which come from the id table */
#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
/* Non chip related options */
/* Use a flash based bad block table. This option is passed to the
* default bad block table function. */
#define NAND_USE_FLASH_BBT 0x00010000
/* This option skips the bbt scan during initialization. */
#define NAND_SKIP_BBTSCAN 0x00020000
/* This option is defined if the board driver allocates its own buffers
(e.g. because it needs them DMA-coherent */
#define NAND_OWN_BUFFERS 0x00040000
/* Options set by nand scan */
/* bbt has already been read */
#define NAND_BBT_SCANNED 0x40000000
/* Nand scan has allocated controller struct */
#define NAND_CONTROLLER_ALLOC 0x80000000
/* Cell info constants */
#define NAND_CI_CHIPNR_MSK 0x03
#define NAND_CI_CELLTYPE_MSK 0x0C
/* Keep gcc happy */
struct nand_chip;
struct nand_onfi_params {
/* rev info and features block */
/* 'O' 'N' 'F' 'I' */
u8 sig[4];
__le16 revision;
__le16 features;
__le16 opt_cmd;
u8 reserved[22];
/* manufacturer information block */
char manufacturer[12];
char model[20];
u8 jedec_id;
__le16 date_code;
u8 reserved2[13];
/* memory organization block */
__le32 byte_per_page;
__le16 spare_bytes_per_page;
__le32 data_bytes_per_ppage;
__le16 spare_bytes_per_ppage;
__le32 pages_per_block;
__le32 blocks_per_lun;
u8 lun_count;
u8 addr_cycles;
u8 bits_per_cell;
__le16 bb_per_lun;
__le16 block_endurance;
u8 guaranteed_good_blocks;
__le16 guaranteed_block_endurance;
u8 programs_per_page;
u8 ppage_attr;
u8 ecc_bits;
u8 interleaved_bits;
u8 interleaved_ops;
u8 reserved3[13];
/* electrical parameter block */
u8 io_pin_capacitance_max;
__le16 async_timing_mode;
__le16 program_cache_timing_mode;
__le16 t_prog;
__le16 t_bers;
__le16 t_r;
__le16 t_ccs;
__le16 src_sync_timing_mode;
__le16 src_ssync_features;
__le16 clk_pin_capacitance_typ;
__le16 io_pin_capacitance_typ;
__le16 input_pin_capacitance_typ;
u8 input_pin_capacitance_max;
u8 driver_strenght_support;
__le16 t_int_r;
__le16 t_ald;
u8 reserved4[7];
/* vendor */
u8 reserved5[90];
__le16 crc;
} __attribute__((packed));
#define ONFI_CRC_BASE 0x4F4E
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
* @lock: protection lock
* @active: the mtd device which holds the controller currently
* @wq: wait queue to sleep on if a NAND operation is in progress
* used instead of the per chip wait queue when a hw controller is available
*/
struct nand_hw_control {
/* XXX U-BOOT XXX */
#if 0
spinlock_t lock;
wait_queue_head_t wq;
#endif
struct nand_chip *active;
};
/**
* struct nand_ecc_ctrl - Control structure for ecc
* @mode: ecc mode
* @steps: number of ecc steps per page
* @size: data bytes per ecc step
* @bytes: ecc bytes per step
* @total: total number of ecc bytes per page
* @prepad: padding information for syndrome based ecc generators
* @postpad: padding information for syndrome based ecc generators
* @layout: ECC layout control struct pointer
* @hwctl: function to control hardware ecc generator. Must only
* be provided if an hardware ECC is available
* @calculate: function for ecc calculation or readback from ecc hardware
* @correct: function for ecc correction, matching to ecc generator (sw/hw)
* @read_page_raw: function to read a raw page without ECC
* @write_page_raw: function to write a raw page without ECC
* @read_page: function to read a page according to the ecc generator requirements
* @write_page: function to write a page according to the ecc generator requirements
* @read_oob: function to read chip OOB data
* @write_oob: function to write chip OOB data
*/
struct nand_ecc_ctrl {
nand_ecc_modes_t mode;
int steps;
int size;
int bytes;
int total;
int prepad;
int postpad;
struct nand_ecclayout *layout;
void (*hwctl)(struct mtd_info *mtd, int mode);
int (*calculate)(struct mtd_info *mtd,
const uint8_t *dat,
uint8_t *ecc_code);
int (*correct)(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc,
uint8_t *calc_ecc);
int (*read_page_raw)(struct mtd_info *mtd,
struct nand_chip *chip,
uint8_t *buf, int page);
void (*write_page_raw)(struct mtd_info *mtd,
struct nand_chip *chip,
const uint8_t *buf);
int (*read_page)(struct mtd_info *mtd,
struct nand_chip *chip,
uint8_t *buf, int page);
int (*read_subpage)(struct mtd_info *mtd,
struct nand_chip *chip,
uint32_t offs, uint32_t len,
uint8_t *buf);
void (*write_page)(struct mtd_info *mtd,
struct nand_chip *chip,
const uint8_t *buf);
int (*read_oob)(struct mtd_info *mtd,
struct nand_chip *chip,
int page,
int sndcmd);
int (*write_oob)(struct mtd_info *mtd,
struct nand_chip *chip,
int page);
};
/**
* struct nand_buffers - buffer structure for read/write
* @ecccalc: buffer for calculated ecc
* @ecccode: buffer for ecc read from flash
* @databuf: buffer for data - dynamically sized
*
* Do not change the order of buffers. databuf and oobrbuf must be in
* consecutive order.
*/
struct nand_buffers {
uint8_t ecccalc[NAND_MAX_OOBSIZE];
uint8_t ecccode[NAND_MAX_OOBSIZE];
uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
};
/**
* struct nand_chip - NAND Private Flash Chip Data
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
* @read_byte: [REPLACEABLE] read one byte from the chip
* @read_word: [REPLACEABLE] read one word from the chip
* @write_buf: [REPLACEABLE] write data from the buffer to the chip
* @read_buf: [REPLACEABLE] read data from the chip into the buffer
* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
* @select_chip: [REPLACEABLE] select chip nr
* @block_bad: [REPLACEABLE] check, if the block is bad
* @block_markbad: [REPLACEABLE] mark the block bad
* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
* ALE/CLE/nCE. Also used to write command and address
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
* If set to NULL no access to ready/busy is available and the ready/busy information
* is read from the chip status register
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
* @ecc: [BOARDSPECIFIC] ecc control ctructure
* @buffers: buffer structure for read/write
* @hwcontrol: platform-specific hardware control structure
* @ops: oob operation operands
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
* @state: [INTERN] the current state of the NAND device
* @oob_poi: poison value buffer
* @page_shift: [INTERN] number of address bits in a page (column address bits)
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
* @chip_shift: [INTERN] number of address bits in one chip
* @datbuf: [INTERN] internal buffer for one page + oob
* @oobbuf: [INTERN] oob buffer for one eraseblock
* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
* @data_poi: [INTERN] pointer to a data buffer
* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
* special functionality. See the defines for further explanation
* @badblockpos: [INTERN] position of the bad block marker in the oob area
* @cellinfo: [INTERN] MLC/multichip data from chip ident
* @numchips: [INTERN] number of physical chips
* @chipsize: [INTERN] the size of one chip for multichip arrays
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
* @subpagesize: [INTERN] holds the subpagesize
* @ecclayout: [REPLACEABLE] the default ecc placement scheme
* @bbt: [INTERN] bad block table pointer
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
* @controller: [REPLACEABLE] a pointer to a hardware controller structure
* which is shared among multiple independend devices
* @priv: [OPTIONAL] pointer to private chip date
* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
* (determine if errors are correctable)
* @write_page: [REPLACEABLE] High-level page write function
*/
struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
uint8_t (*read_byte)(struct mtd_info *mtd);
u16 (*read_word)(struct mtd_info *mtd);
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
void (*select_chip)(struct mtd_info *mtd, int chip);
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
unsigned int ctrl);
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
void (*erase_cmd)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
const uint8_t *buf, int page, int cached, int raw);
int chip_delay;
unsigned int options;
int page_shift;
int phys_erase_shift;
int bbt_erase_shift;
int chip_shift;
int numchips;
uint64_t chipsize;
int pagemask;
int pagebuf;
int subpagesize;
uint8_t cellinfo;
int badblockpos;
int onfi_version;
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
struct nand_onfi_params onfi_params;
#endif
int state;
uint8_t *oob_poi;
struct nand_hw_control *controller;
struct nand_ecclayout *ecclayout;
struct nand_ecc_ctrl ecc;
struct nand_buffers *buffers;
struct nand_hw_control hwcontrol;
struct mtd_oob_ops ops;
uint8_t *bbt;
struct nand_bbt_descr *bbt_td;
struct nand_bbt_descr *bbt_md;
struct nand_bbt_descr *badblock_pattern;
void *priv;
};
/*
* NAND Flash Manufacturer ID Codes
*/
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xec
#define NAND_MFR_FUJITSU 0x04
#define NAND_MFR_NATIONAL 0x8f
#define NAND_MFR_RENESAS 0x07
#define NAND_MFR_STMICRO 0x20
#define NAND_MFR_HYNIX 0xad
#define NAND_MFR_MICRON 0x2c
#define NAND_MFR_AMD 0x01
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
* @name: Identify the device type
* @id: device ID code
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* If the pagesize is 0, then the real pagesize
* and the eraseize are determined from the
* extended id bytes in the chip
* @erasesize: Size of an erase block in the flash device.
* @chipsize: Total chipsize in Mega Bytes
* @options: Bitfield to store chip relevant options
*/
struct nand_flash_dev {
char *name;
int id;
unsigned long pagesize;
unsigned long chipsize;
unsigned long erasesize;
unsigned long options;
};
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
* @name: Manufacturer name
* @id: manufacturer ID code of device.
*/
struct nand_manufacturers {
int id;
char * name;
};
extern const struct nand_flash_dev nand_flash_ids[];
extern const struct nand_manufacturers nand_manuf_ids[];
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
extern int nand_default_bbt(struct mtd_info *mtd);
extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
int allowbbt);
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t * retlen, uint8_t * buf);
/*
* Constants for oob configuration
*/
#define NAND_SMALL_BADBLOCK_POS 5
#define NAND_LARGE_BADBLOCK_POS 0
/**
* struct platform_nand_chip - chip level device structure
* @nr_chips: max. number of chips to scan for
* @chip_offset: chip number offset
* @nr_partitions: number of partitions pointed to by partitions (or zero)
* @partitions: mtd partition list
* @chip_delay: R/B delay value in us
* @options: Option flags, e.g. 16bit buswidth
* @ecclayout: ecc layout info structure
* @part_probe_types: NULL-terminated array of probe types
* @priv: hardware controller specific settings
*/
struct platform_nand_chip {
int nr_chips;
int chip_offset;
int nr_partitions;
struct mtd_partition *partitions;
struct nand_ecclayout *ecclayout;
int chip_delay;
unsigned int options;
const char **part_probe_types;
void *priv;
};
/**
* struct platform_nand_ctrl - controller level device structure
* @hwcontrol: platform specific hardware control structure
* @dev_ready: platform specific function to read ready/busy pin
* @select_chip: platform specific chip select function
* @cmd_ctrl: platform specific function for controlling
* ALE/CLE/nCE. Also used to write command and address
* @priv: private data to transport driver specific settings
*
* All fields are optional and depend on the hardware driver requirements
*/
struct platform_nand_ctrl {
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
int (*dev_ready)(struct mtd_info *mtd);
void (*select_chip)(struct mtd_info *mtd, int chip);
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
unsigned int ctrl);
void *priv;
};
/**
* struct platform_nand_data - container structure for platform-specific data
* @chip: chip level chip structure
* @ctrl: controller level device structure
*/
struct platform_nand_data {
struct platform_nand_chip chip;
struct platform_nand_ctrl ctrl;
};
/* Some helpers to access the data structures */
static inline
struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
return chip->priv;
}
/* Standard NAND functions from nand_base.c */
void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
uint8_t nand_read_byte(struct mtd_info *mtd);
#endif /* __LINUX_MTD_NAND_H */
|
1001-study-uboot
|
include/linux/mtd/nand.h
|
C
|
gpl3
| 21,192
|
/*
* drivers/mtd/nand_ecc.h
*
* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This file is the header for the ECC algorithm.
*/
#ifndef __MTD_NAND_ECC_H__
#define __MTD_NAND_ECC_H__
struct mtd_info;
/*
* Calculate 3 byte ECC code for 256 byte block
*/
int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
/*
* Detect and correct a 1 bit error for 256 byte block
*/
int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
#endif /* __MTD_NAND_ECC_H__ */
|
1001-study-uboot
|
include/linux/mtd/nand_ecc.h
|
C
|
gpl3
| 748
|
/*
* Copyright (c) International Business Machines Corp., 2006
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
* the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Author: Artem Bityutskiy (Битюцкий Артём)
*/
#ifndef __LINUX_UBI_H__
#define __LINUX_UBI_H__
/* #include <asm/ioctl.h> */
#include <linux/types.h>
#include <mtd/ubi-user.h>
/*
* enum ubi_open_mode - UBI volume open mode constants.
*
* UBI_READONLY: read-only mode
* UBI_READWRITE: read-write mode
* UBI_EXCLUSIVE: exclusive mode
*/
enum {
UBI_READONLY = 1,
UBI_READWRITE,
UBI_EXCLUSIVE
};
/**
* struct ubi_volume_info - UBI volume description data structure.
* @vol_id: volume ID
* @ubi_num: UBI device number this volume belongs to
* @size: how many physical eraseblocks are reserved for this volume
* @used_bytes: how many bytes of data this volume contains
* @used_ebs: how many physical eraseblocks of this volume actually contain any
* data
* @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
* @corrupted: non-zero if the volume is corrupted (static volumes only)
* @upd_marker: non-zero if the volume has update marker set
* @alignment: volume alignment
* @usable_leb_size: how many bytes are available in logical eraseblocks of
* this volume
* @name_len: volume name length
* @name: volume name
* @cdev: UBI volume character device major and minor numbers
*
* The @corrupted flag is only relevant to static volumes and is always zero
* for dynamic ones. This is because UBI does not care about dynamic volume
* data protection and only cares about protecting static volume data.
*
* The @upd_marker flag is set if the volume update operation was interrupted.
* Before touching the volume data during the update operation, UBI first sets
* the update marker flag for this volume. If the volume update operation was
* further interrupted, the update marker indicates this. If the update marker
* is set, the contents of the volume is certainly damaged and a new volume
* update operation has to be started.
*
* To put it differently, @corrupted and @upd_marker fields have different
* semantics:
* o the @corrupted flag means that this static volume is corrupted for some
* reasons, but not because an interrupted volume update
* o the @upd_marker field means that the volume is damaged because of an
* interrupted update operation.
*
* I.e., the @corrupted flag is never set if the @upd_marker flag is set.
*
* The @used_bytes and @used_ebs fields are only really needed for static
* volumes and contain the number of bytes stored in this static volume and how
* many eraseblock this data occupies. In case of dynamic volumes, the
* @used_bytes field is equivalent to @size*@usable_leb_size, and the @used_ebs
* field is equivalent to @size.
*
* In general, logical eraseblock size is a property of the UBI device, not
* of the UBI volume. Indeed, the logical eraseblock size depends on the
* physical eraseblock size and on how much bytes UBI headers consume. But
* because of the volume alignment (@alignment), the usable size of logical
* eraseblocks if a volume may be less. The following equation is true:
* @usable_leb_size = LEB size - (LEB size mod @alignment),
* where LEB size is the logical eraseblock size defined by the UBI device.
*
* The alignment is multiple to the minimal flash input/output unit size or %1
* if all the available space is used.
*
* To put this differently, alignment may be considered is a way to change
* volume logical eraseblock sizes.
*/
struct ubi_volume_info {
int ubi_num;
int vol_id;
int size;
long long used_bytes;
int used_ebs;
int vol_type;
int corrupted;
int upd_marker;
int alignment;
int usable_leb_size;
int name_len;
const char *name;
dev_t cdev;
};
/**
* struct ubi_device_info - UBI device description data structure.
* @ubi_num: ubi device number
* @leb_size: logical eraseblock size on this UBI device
* @min_io_size: minimal I/O unit size
* @ro_mode: if this device is in read-only mode
* @cdev: UBI character device major and minor numbers
*
* Note, @leb_size is the logical eraseblock size offered by the UBI device.
* Volumes of this UBI device may have smaller logical eraseblock size if their
* alignment is not equivalent to %1.
*/
struct ubi_device_info {
int ubi_num;
int leb_size;
int min_io_size;
int ro_mode;
dev_t cdev;
};
/* UBI descriptor given to users when they open UBI volumes */
struct ubi_volume_desc;
int ubi_get_device_info(int ubi_num, struct ubi_device_info *di);
void ubi_get_volume_info(struct ubi_volume_desc *desc,
struct ubi_volume_info *vi);
struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode);
struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name,
int mode);
void ubi_close_volume(struct ubi_volume_desc *desc);
int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset,
int len, int check);
int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf,
int offset, int len, int dtype);
int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf,
int len, int dtype);
int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum);
int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum);
int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype);
int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum);
/*
* This function is the same as the 'ubi_leb_read()' function, but it does not
* provide the checking capability.
*/
static inline int ubi_read(struct ubi_volume_desc *desc, int lnum, char *buf,
int offset, int len)
{
return ubi_leb_read(desc, lnum, buf, offset, len, 0);
}
/*
* This function is the same as the 'ubi_leb_write()' functions, but it does
* not have the data type argument.
*/
static inline int ubi_write(struct ubi_volume_desc *desc, int lnum,
const void *buf, int offset, int len)
{
return ubi_leb_write(desc, lnum, buf, offset, len, UBI_UNKNOWN);
}
/*
* This function is the same as the 'ubi_leb_change()' functions, but it does
* not have the data type argument.
*/
static inline int ubi_change(struct ubi_volume_desc *desc, int lnum,
const void *buf, int len)
{
return ubi_leb_change(desc, lnum, buf, len, UBI_UNKNOWN);
}
#endif /* !__LINUX_UBI_H__ */
|
1001-study-uboot
|
include/linux/mtd/ubi.h
|
C
|
gpl3
| 6,971
|
/*
* FSL UPM NAND driver
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __LINUX_MTD_NAND_FSL_UPM
#define __LINUX_MTD_NAND_FSL_UPM
#include <linux/mtd/nand.h>
#define FSL_UPM_WAIT_RUN_PATTERN 0x1
#define FSL_UPM_WAIT_WRITE_BYTE 0x2
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
struct fsl_upm {
void __iomem *mdr;
void __iomem *mxmr;
void __iomem *mar;
void __iomem *io_addr;
};
struct fsl_upm_nand {
struct fsl_upm upm;
int width;
int upm_cmd_offset;
int upm_addr_offset;
int upm_mar_chip_offset;
int wait_flags;
int (*dev_ready)(int chip_nr);
int chip_delay;
int chip_offset;
int chip_nr;
/* no need to fill */
int last_ctrl;
};
extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
#endif
|
1001-study-uboot
|
include/linux/mtd/fsl_upm.h
|
C
|
gpl3
| 1,074
|
/*
* Copyright (C) 2005-2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SAMSUNG_ONENAND_H__
#define __SAMSUNG_ONENAND_H__
/*
* OneNAND Controller
*/
#ifndef __ASSEMBLY__
struct samsung_onenand {
unsigned int mem_cfg; /* 0x0000 */
unsigned char res1[0xc];
unsigned int burst_len; /* 0x0010 */
unsigned char res2[0xc];
unsigned int mem_reset; /* 0x0020 */
unsigned char res3[0xc];
unsigned int int_err_stat; /* 0x0030 */
unsigned char res4[0xc];
unsigned int int_err_mask; /* 0x0040 */
unsigned char res5[0xc];
unsigned int int_err_ack; /* 0x0050 */
unsigned char res6[0xc];
unsigned int ecc_err_stat; /* 0x0060 */
unsigned char res7[0xc];
unsigned int manufact_id; /* 0x0070 */
unsigned char res8[0xc];
unsigned int device_id; /* 0x0080 */
unsigned char res9[0xc];
unsigned int data_buf_size; /* 0x0090 */
unsigned char res10[0xc];
unsigned int boot_buf_size; /* 0x00A0 */
unsigned char res11[0xc];
unsigned int buf_amount; /* 0x00B0 */
unsigned char res12[0xc];
unsigned int tech; /* 0x00C0 */
unsigned char res13[0xc];
unsigned int fba; /* 0x00D0 */
unsigned char res14[0xc];
unsigned int fpa; /* 0x00E0 */
unsigned char res15[0xc];
unsigned int fsa; /* 0x00F0 */
unsigned char res16[0x3c];
unsigned int sync_mode; /* 0x0130 */
unsigned char res17[0xc];
unsigned int trans_spare; /* 0x0140 */
unsigned char res18[0x3c];
unsigned int err_page_addr; /* 0x0180 */
unsigned char res19[0x1c];
unsigned int int_pin_en; /* 0x01A0 */
unsigned char res20[0x1c];
unsigned int acc_clock; /* 0x01C0 */
unsigned char res21[0x1c];
unsigned int err_blk_addr; /* 0x01E0 */
unsigned char res22[0xc];
unsigned int flash_ver_id; /* 0x01F0 */
unsigned char res23[0x6c];
unsigned int watchdog_cnt_low; /* 0x0260 */
unsigned char res24[0xc];
unsigned int watchdog_cnt_hi; /* 0x0270 */
unsigned char res25[0xc];
unsigned int sync_write; /* 0x0280 */
unsigned char res26[0x1c];
unsigned int cold_reset; /* 0x02A0 */
unsigned char res27[0xc];
unsigned int ddp_device; /* 0x02B0 */
unsigned char res28[0xc];
unsigned int multi_plane; /* 0x02C0 */
unsigned char res29[0x1c];
unsigned int trans_mode; /* 0x02E0 */
unsigned char res30[0x1c];
unsigned int ecc_err_stat2; /* 0x0300 */
unsigned char res31[0xc];
unsigned int ecc_err_stat3; /* 0x0310 */
unsigned char res32[0xc];
unsigned int ecc_err_stat4; /* 0x0320 */
unsigned char res33[0x1c];
unsigned int dev_page_size; /* 0x0340 */
unsigned char res34[0x4c];
unsigned int int_mon_status; /* 0x0390 */
};
#endif
#define ONENAND_MEM_RESET_HOT 0x3
#define ONENAND_MEM_RESET_COLD 0x2
#define ONENAND_MEM_RESET_WARM 0x1
#define INT_ERR_ALL 0x3fff
#define CACHE_OP_ERR (1 << 13)
#define RST_CMP (1 << 12)
#define RDY_ACT (1 << 11)
#define INT_ACT (1 << 10)
#define UNSUP_CMD (1 << 9)
#define LOCKED_BLK (1 << 8)
#define BLK_RW_CMP (1 << 7)
#define ERS_CMP (1 << 6)
#define PGM_CMP (1 << 5)
#define LOAD_CMP (1 << 4)
#define ERS_FAIL (1 << 3)
#define PGM_FAIL (1 << 2)
#define INT_TO (1 << 1)
#define LD_FAIL_ECC_ERR (1 << 0)
#define TSRF (1 << 0)
/* common initialize function */
extern void s3c_onenand_init(struct mtd_info *);
#endif
|
1001-study-uboot
|
include/linux/mtd/samsung_onenand.h
|
C
|
gpl3
| 4,101
|
/*
* $Id: inftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $
*
* Parts of INFTL headers shared with userspace
*
*/
#ifndef __MTD_INFTL_USER_H__
#define __MTD_INFTL_USER_H__
#define OSAK_VERSION 0x5120
#define PERCENTUSED 98
#define SECTORSIZE 512
/* Block Control Information */
struct inftl_bci {
uint8_t ECCsig[6];
uint8_t Status;
uint8_t Status1;
} __attribute__((packed));
struct inftl_unithead1 {
uint16_t virtualUnitNo;
uint16_t prevUnitNo;
uint8_t ANAC;
uint8_t NACs;
uint8_t parityPerField;
uint8_t discarded;
} __attribute__((packed));
struct inftl_unithead2 {
uint8_t parityPerField;
uint8_t ANAC;
uint16_t prevUnitNo;
uint16_t virtualUnitNo;
uint8_t NACs;
uint8_t discarded;
} __attribute__((packed));
struct inftl_unittail {
uint8_t Reserved[4];
uint16_t EraseMark;
uint16_t EraseMark1;
} __attribute__((packed));
union inftl_uci {
struct inftl_unithead1 a;
struct inftl_unithead2 b;
struct inftl_unittail c;
};
struct inftl_oob {
struct inftl_bci b;
union inftl_uci u;
};
/* INFTL Media Header */
struct INFTLPartition {
__u32 virtualUnits;
__u32 firstUnit;
__u32 lastUnit;
__u32 flags;
__u32 spareUnits;
__u32 Reserved0;
__u32 Reserved1;
} __attribute__((packed));
struct INFTLMediaHeader {
char bootRecordID[8];
__u32 NoOfBootImageBlocks;
__u32 NoOfBinaryPartitions;
__u32 NoOfBDTLPartitions;
__u32 BlockMultiplierBits;
__u32 FormatFlags;
__u32 OsakVersion;
__u32 PercentUsed;
struct INFTLPartition Partitions[4];
} __attribute__((packed));
/* Partition flag types */
#define INFTL_BINARY 0x20000000
#define INFTL_BDTL 0x40000000
#define INFTL_LAST 0x80000000
#endif /* __MTD_INFTL_USER_H__ */
|
1001-study-uboot
|
include/linux/mtd/inftl-user.h
|
C
|
gpl3
| 1,672
|
/*
* $Id: nftl-user.h,v 1.2 2005/11/07 11:14:56 gleixner Exp $
*
* Parts of NFTL headers shared with userspace
*
*/
#ifndef __MTD_NFTL_USER_H__
#define __MTD_NFTL_USER_H__
/* Block Control Information */
struct nftl_bci {
unsigned char ECCSig[6];
uint8_t Status;
uint8_t Status1;
}__attribute__((packed));
/* Unit Control Information */
struct nftl_uci0 {
uint16_t VirtUnitNum;
uint16_t ReplUnitNum;
uint16_t SpareVirtUnitNum;
uint16_t SpareReplUnitNum;
} __attribute__((packed));
struct nftl_uci1 {
uint32_t WearInfo;
uint16_t EraseMark;
uint16_t EraseMark1;
} __attribute__((packed));
struct nftl_uci2 {
uint16_t FoldMark;
uint16_t FoldMark1;
uint32_t unused;
} __attribute__((packed));
union nftl_uci {
struct nftl_uci0 a;
struct nftl_uci1 b;
struct nftl_uci2 c;
};
struct nftl_oob {
struct nftl_bci b;
union nftl_uci u;
};
/* NFTL Media Header */
struct NFTLMediaHeader {
char DataOrgID[6];
uint16_t NumEraseUnits;
uint16_t FirstPhysicalEUN;
uint32_t FormattedSize;
unsigned char UnitSizeFactor;
} __attribute__((packed));
#define MAX_ERASE_ZONES (8192 - 512)
#define ERASE_MARK 0x3c69
#define SECTOR_FREE 0xff
#define SECTOR_USED 0x55
#define SECTOR_IGNORE 0x11
#define SECTOR_DELETED 0x00
#define FOLD_MARK_IN_PROGRESS 0x5555
#define ZONE_GOOD 0xff
#define ZONE_BAD_ORIGINAL 0
#define ZONE_BAD_MARKED 7
#endif /* __MTD_NFTL_USER_H__ */
|
1001-study-uboot
|
include/linux/mtd/nftl-user.h
|
C
|
gpl3
| 1,387
|
/*
* Linux driver for Disk-On-Chip devices
*
* Copyright (C) 1999 Machine Vision Holdings, Inc.
* Copyright (C) 2001-2003 David Woodhouse <dwmw2@infradead.org>
* Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com>
* Copyright (C) 2002-2003 SnapGear Inc
*
* Released under GPL
*/
#ifndef __MTD_DOC2000_H__
#define __MTD_DOC2000_H__
#include <linux/mtd/mtd.h>
#if 0
#include <linux/mutex.h>
#endif
#define DoC_Sig1 0
#define DoC_Sig2 1
#define DoC_ChipID 0x1000
#define DoC_DOCStatus 0x1001
#define DoC_DOCControl 0x1002
#define DoC_FloorSelect 0x1003
#define DoC_CDSNControl 0x1004
#define DoC_CDSNDeviceSelect 0x1005
#define DoC_ECCConf 0x1006
#define DoC_2k_ECCStatus 0x1007
#define DoC_CDSNSlowIO 0x100d
#define DoC_ECCSyndrome0 0x1010
#define DoC_ECCSyndrome1 0x1011
#define DoC_ECCSyndrome2 0x1012
#define DoC_ECCSyndrome3 0x1013
#define DoC_ECCSyndrome4 0x1014
#define DoC_ECCSyndrome5 0x1015
#define DoC_AliasResolution 0x101b
#define DoC_ConfigInput 0x101c
#define DoC_ReadPipeInit 0x101d
#define DoC_WritePipeTerm 0x101e
#define DoC_LastDataRead 0x101f
#define DoC_NOP 0x1020
#define DoC_Mil_CDSN_IO 0x0800
#define DoC_2k_CDSN_IO 0x1800
#define DoC_Mplus_NOP 0x1002
#define DoC_Mplus_AliasResolution 0x1004
#define DoC_Mplus_DOCControl 0x1006
#define DoC_Mplus_AccessStatus 0x1008
#define DoC_Mplus_DeviceSelect 0x1008
#define DoC_Mplus_Configuration 0x100a
#define DoC_Mplus_OutputControl 0x100c
#define DoC_Mplus_FlashControl 0x1020
#define DoC_Mplus_FlashSelect 0x1022
#define DoC_Mplus_FlashCmd 0x1024
#define DoC_Mplus_FlashAddress 0x1026
#define DoC_Mplus_FlashData0 0x1028
#define DoC_Mplus_FlashData1 0x1029
#define DoC_Mplus_ReadPipeInit 0x102a
#define DoC_Mplus_LastDataRead 0x102c
#define DoC_Mplus_LastDataRead1 0x102d
#define DoC_Mplus_WritePipeTerm 0x102e
#define DoC_Mplus_ECCSyndrome0 0x1040
#define DoC_Mplus_ECCSyndrome1 0x1041
#define DoC_Mplus_ECCSyndrome2 0x1042
#define DoC_Mplus_ECCSyndrome3 0x1043
#define DoC_Mplus_ECCSyndrome4 0x1044
#define DoC_Mplus_ECCSyndrome5 0x1045
#define DoC_Mplus_ECCConf 0x1046
#define DoC_Mplus_Toggle 0x1046
#define DoC_Mplus_DownloadStatus 0x1074
#define DoC_Mplus_CtrlConfirm 0x1076
#define DoC_Mplus_Power 0x1fff
/* How to access the device?
* On ARM, it'll be mmap'd directly with 32-bit wide accesses.
* On PPC, it's mmap'd and 16-bit wide.
* Others use readb/writeb
*/
#if defined(__arm__)
#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
#define DOC_IOREMAP_LEN 0x8000
#elif defined(__ppc__)
#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
#define DOC_IOREMAP_LEN 0x4000
#else
#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg))
#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg))
#define DOC_IOREMAP_LEN 0x2000
#endif
#if defined(__i386__) || defined(__x86_64__)
#define USE_MEMCPY
#endif
/* These are provided to directly use the DoC_xxx defines */
#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg)
#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg)
#define DOC_MODE_RESET 0
#define DOC_MODE_NORMAL 1
#define DOC_MODE_RESERVED1 2
#define DOC_MODE_RESERVED2 3
#define DOC_MODE_CLR_ERR 0x80
#define DOC_MODE_RST_LAT 0x10
#define DOC_MODE_BDECT 0x08
#define DOC_MODE_MDWREN 0x04
#define DOC_ChipID_Doc2k 0x20
#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */
#define DOC_ChipID_DocMil 0x30
#define DOC_ChipID_DocMilPlus32 0x40
#define DOC_ChipID_DocMilPlus16 0x41
#define CDSN_CTRL_FR_B 0x80
#define CDSN_CTRL_FR_B0 0x40
#define CDSN_CTRL_FR_B1 0x80
#define CDSN_CTRL_ECC_IO 0x20
#define CDSN_CTRL_FLASH_IO 0x10
#define CDSN_CTRL_WP 0x08
#define CDSN_CTRL_ALE 0x04
#define CDSN_CTRL_CLE 0x02
#define CDSN_CTRL_CE 0x01
#define DOC_ECC_RESET 0
#define DOC_ECC_ERROR 0x80
#define DOC_ECC_RW 0x20
#define DOC_ECC__EN 0x08
#define DOC_TOGGLE_BIT 0x04
#define DOC_ECC_RESV 0x02
#define DOC_ECC_IGNORE 0x01
#define DOC_FLASH_CE 0x80
#define DOC_FLASH_WP 0x40
#define DOC_FLASH_BANK 0x02
/* We have to also set the reserved bit 1 for enable */
#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
#define DOC_ECC_DIS (DOC_ECC_RESV)
struct Nand {
char floor, chip;
unsigned long curadr;
unsigned char curmode;
/* Also some erase/write/pipeline info when we get that far */
};
#define MAX_FLOORS 4
#define MAX_CHIPS 4
#define MAX_FLOORS_MIL 1
#define MAX_CHIPS_MIL 1
#define MAX_FLOORS_MPLUS 2
#define MAX_CHIPS_MPLUS 1
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
struct DiskOnChip {
unsigned long physadr;
void __iomem *virtadr;
unsigned long totlen;
unsigned char ChipID; /* Type of DiskOnChip */
int ioreg;
unsigned long mfr; /* Flash IDs - only one type of flash per device */
unsigned long id;
int chipshift;
char page256;
char pageadrlen;
char interleave; /* Internal interleaving - Millennium Plus style */
unsigned long erasesize;
int curfloor;
int curchip;
int numchips;
struct Nand *chips;
struct mtd_info *nextdoc;
/* XXX U-BOOT XXX */
#if 0
struct mutex lock;
#endif
};
int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
/* XXX U-BOOT XXX */
#if 1
/*
* NAND Flash Manufacturer ID Codes
*/
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xec
#endif
#endif /* __MTD_DOC2000_H__ */
|
1001-study-uboot
|
include/linux/mtd/doc2000.h
|
C
|
gpl3
| 5,647
|
/*
* MTD partitioning layer definitions
*
* (C) 2000 Nicolas Pitre <nico@cam.org>
*
* This code is GPL
*
* $Id: partitions.h,v 1.17 2005/11/07 11:14:55 gleixner Exp $
*/
#ifndef MTD_PARTITIONS_H
#define MTD_PARTITIONS_H
#include <linux/types.h>
/*
* Partition definition structure:
*
* An array of struct partition is passed along with a MTD object to
* add_mtd_partitions() to create them.
*
* For each partition, these fields are available:
* name: string that will be used to label the partition's MTD device.
* size: the partition size; if defined as MTDPART_SIZ_FULL, the partition
* will extend to the end of the master MTD device.
* offset: absolute starting position within the master MTD device; if
* defined as MTDPART_OFS_APPEND, the partition will start where the
* previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block.
* mask_flags: contains flags that have to be masked (removed) from the
* master MTD flag set for the corresponding MTD partition.
* For example, to force a read-only partition, simply adding
* MTD_WRITEABLE to the mask_flags will do the trick.
*
* Note: writeable partitions require their size and offset be
* erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK).
*/
struct mtd_partition {
char *name; /* identifier string */
uint64_t size; /* partition size */
uint64_t offset; /* offset within the master MTD space */
u_int32_t mask_flags; /* master MTD flags to mask out for this partition */
struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/
struct mtd_info **mtdp; /* pointer to store the MTD object */
};
#define MTDPART_OFS_NXTBLK (-2)
#define MTDPART_OFS_APPEND (-1)
#define MTDPART_SIZ_FULL (0)
int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
int del_mtd_partitions(struct mtd_info *);
#if 0
/*
* Functions dealing with the various ways of partitioning the space
*/
struct mtd_part_parser {
struct list_head list;
struct module *owner;
const char *name;
int (*parse_fn)(struct mtd_info *, struct mtd_partition **, unsigned long);
};
extern int register_mtd_parser(struct mtd_part_parser *parser);
extern int deregister_mtd_parser(struct mtd_part_parser *parser);
extern int parse_mtd_partitions(struct mtd_info *master, const char **types,
struct mtd_partition **pparts, unsigned long origin);
#define put_partition_parser(p) do { module_put((p)->owner); } while(0)
struct device;
struct device_node;
int __devinit of_mtd_parse_partitions(struct device *dev,
struct mtd_info *mtd,
struct device_node *node,
struct mtd_partition **pparts);
#endif
#endif
|
1001-study-uboot
|
include/linux/mtd/partitions.h
|
C
|
gpl3
| 2,675
|
/*
* Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
*
* Released under GPL
*/
#ifndef __MTD_MTD_H__
#define __MTD_MTD_H__
#include <linux/types.h>
#include <div64.h>
#include <linux/mtd/mtd-abi.h>
#define MTD_CHAR_MAJOR 90
#define MTD_BLOCK_MAJOR 31
#define MAX_MTD_DEVICES 32
#define MTD_ERASE_PENDING 0x01
#define MTD_ERASING 0x02
#define MTD_ERASE_SUSPEND 0x04
#define MTD_ERASE_DONE 0x08
#define MTD_ERASE_FAILED 0x10
#define MTD_FAIL_ADDR_UNKNOWN -1LL
/*
* Enumeration for NAND/OneNAND flash chip state
*/
enum {
FL_READY,
FL_READING,
FL_WRITING,
FL_ERASING,
FL_SYNCING,
FL_CACHEDPRG,
FL_RESETING,
FL_UNLOCKING,
FL_LOCKING,
FL_PM_SUSPENDED,
};
/* If the erase fails, fail_addr might indicate exactly which block failed. If
fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not
specific to any particular block. */
struct erase_info {
struct mtd_info *mtd;
uint64_t addr;
uint64_t len;
uint64_t fail_addr;
u_long time;
u_long retries;
u_int dev;
u_int cell;
void (*callback) (struct erase_info *self);
u_long priv;
u_char state;
struct erase_info *next;
int scrub;
};
struct mtd_erase_region_info {
uint64_t offset; /* At which this region starts, from the beginning of the MTD */
u_int32_t erasesize; /* For this region */
u_int32_t numblocks; /* Number of blocks of erasesize in this region */
unsigned long *lockmap; /* If keeping bitmap of locks */
};
/*
* oob operation modes
*
* MTD_OOB_PLACE: oob data are placed at the given offset
* MTD_OOB_AUTO: oob data are automatically placed at the free areas
* which are defined by the ecclayout
* MTD_OOB_RAW: mode to read raw data+oob in one chunk. The oob data
* is inserted into the data. Thats a raw image of the
* flash contents.
*/
typedef enum {
MTD_OOB_PLACE,
MTD_OOB_AUTO,
MTD_OOB_RAW,
} mtd_oob_mode_t;
/**
* struct mtd_oob_ops - oob operation operands
* @mode: operation mode
*
* @len: number of data bytes to write/read
*
* @retlen: number of data bytes written/read
*
* @ooblen: number of oob bytes to write/read
* @oobretlen: number of oob bytes written/read
* @ooboffs: offset of oob data in the oob area (only relevant when
* mode = MTD_OOB_PLACE)
* @datbuf: data buffer - if NULL only oob data are read/written
* @oobbuf: oob data buffer
*
* Note, it is allowed to read more then one OOB area at one go, but not write.
* The interface assumes that the OOB write requests program only one page's
* OOB area.
*/
struct mtd_oob_ops {
mtd_oob_mode_t mode;
size_t len;
size_t retlen;
size_t ooblen;
size_t oobretlen;
uint32_t ooboffs;
uint8_t *datbuf;
uint8_t *oobbuf;
};
struct mtd_info {
u_char type;
u_int32_t flags;
uint64_t size; /* Total size of the MTD */
/* "Major" erase size for the device. Naïve users may take this
* to be the only erase size available, or may use the more detailed
* information below if they desire
*/
u_int32_t erasesize;
/* Minimal writable flash unit size. In case of NOR flash it is 1 (even
* though individual bits can be cleared), in case of NAND flash it is
* one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
* it is of ECC block size, etc. It is illegal to have writesize = 0.
* Any driver registering a struct mtd_info must ensure a writesize of
* 1 or larger.
*/
u_int32_t writesize;
u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */
u_int32_t oobavail; /* Available OOB bytes per block */
/* Kernel-only stuff starts here. */
const char *name;
int index;
/* ecc layout structure pointer - read only ! */
struct nand_ecclayout *ecclayout;
/* Data for variable erase regions. If numeraseregions is zero,
* it means that the whole device has erasesize as given above.
*/
int numeraseregions;
struct mtd_erase_region_info *eraseregions;
/*
* Erase is an asynchronous operation. Device drivers are supposed
* to call instr->callback() whenever the operation completes, even
* if it completes with a failure.
* Callers are supposed to pass a callback function and wait for it
* to be called before writing to the block.
*/
int (*erase) (struct mtd_info *mtd, struct erase_info *instr);
/* This stuff for eXecute-In-Place */
/* phys is optional and may be set to NULL */
int (*point) (struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, void **virt, phys_addr_t *phys);
/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
void (*unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
/* In blackbox flight recorder like scenarios we want to make successful
writes in interrupt context. panic_write() is only intended to be
called when its known the kernel is about to panic and we need the
write to succeed. Since the kernel is not going to be running for much
longer, this function can break locks and delay to ensure the write
succeeds (but not sleep). */
int (*panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
int (*read_oob) (struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops);
int (*write_oob) (struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops);
/*
* Methods to access the protection register area, present in some
* flash devices. The user data is one time programmable but the
* factory data is read only.
*/
int (*get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
int (*get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf, size_t len);
int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len);
/* XXX U-BOOT XXX */
#if 0
/* kvec-based read/write methods.
NB: The 'count' parameter is the number of _vectors_, each of
which contains an (ofs, len) tuple.
*/
int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen);
#endif
/* Sync */
void (*sync) (struct mtd_info *mtd);
/* Chip-supported device locking */
int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
/* Bad block management functions */
int (*block_isbad) (struct mtd_info *mtd, loff_t ofs);
int (*block_markbad) (struct mtd_info *mtd, loff_t ofs);
/* XXX U-BOOT XXX */
#if 0
struct notifier_block reboot_notifier; /* default mode before reboot */
#endif
/* ECC status information */
struct mtd_ecc_stats ecc_stats;
/* Subpage shift (NAND) */
int subpage_sft;
void *priv;
struct module *owner;
int usecount;
/* If the driver is something smart, like UBI, it may need to maintain
* its own reference counting. The below functions are only for driver.
* The driver may register its callbacks. These callbacks are not
* supposed to be called by MTD users */
int (*get_device) (struct mtd_info *mtd);
void (*put_device) (struct mtd_info *mtd);
};
static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
{
do_div(sz, mtd->erasesize);
return sz;
}
static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
{
return do_div(sz, mtd->erasesize);
}
/* Kernel-side ioctl definitions */
extern int add_mtd_device(struct mtd_info *mtd);
extern int del_mtd_device (struct mtd_info *mtd);
extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num);
extern struct mtd_info *get_mtd_device_nm(const char *name);
extern void put_mtd_device(struct mtd_info *mtd);
extern void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
const uint64_t length, uint64_t *len_incl_bad,
int *truncated);
/* XXX U-BOOT XXX */
#if 0
struct mtd_notifier {
void (*add)(struct mtd_info *mtd);
void (*remove)(struct mtd_info *mtd);
struct list_head list;
};
extern void register_mtd_user (struct mtd_notifier *new);
extern int unregister_mtd_user (struct mtd_notifier *old);
int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
unsigned long count, loff_t to, size_t *retlen);
int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs,
unsigned long count, loff_t from, size_t *retlen);
#endif
#ifdef CONFIG_MTD_PARTITIONS
void mtd_erase_callback(struct erase_info *instr);
#else
static inline void mtd_erase_callback(struct erase_info *instr)
{
if (instr->callback)
instr->callback(instr);
}
#endif
/*
* Debugging macro and defines
*/
#define MTD_DEBUG_LEVEL0 (0) /* Quiet */
#define MTD_DEBUG_LEVEL1 (1) /* Audible */
#define MTD_DEBUG_LEVEL2 (2) /* Loud */
#define MTD_DEBUG_LEVEL3 (3) /* Noisy */
#ifdef CONFIG_MTD_DEBUG
#define MTDDEBUG(n, args...) \
do { \
if (n <= CONFIG_MTD_DEBUG_VERBOSE) \
printk(KERN_INFO args); \
} while(0)
#else /* CONFIG_MTD_DEBUG */
#define MTDDEBUG(n, args...) \
do { \
if (0) \
printk(KERN_INFO args); \
} while(0)
#endif /* CONFIG_MTD_DEBUG */
#endif /* __MTD_MTD_H__ */
|
1001-study-uboot
|
include/linux/mtd/mtd.h
|
C
|
gpl3
| 9,463
|
/*
* linux/include/linux/mtd/onenand_regs.h
*
* OneNAND Register header file
*
* Copyright (C) 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ONENAND_REG_H
#define __ONENAND_REG_H
/* Memory Address Map Translation (Word order) */
#define ONENAND_MEMORY_MAP(x) ((x) << 1)
/*
* External BufferRAM area
*/
#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
/*
* OneNAND Registers
*/
#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
/*
* Device ID Register F001h (R)
*/
#define DEVICE_IS_FLEXONENAND (1 << 9)
#define FLEXONENAND_PI_MASK (0x3ff)
#define FLEXONENAND_PI_UNLOCK_SHIFT (14)
#define ONENAND_DEVICE_DENSITY_MASK (0xf)
#define ONENAND_DEVICE_DENSITY_SHIFT (4)
#define ONENAND_DEVICE_IS_DDP (1 << 3)
#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
#define ONENAND_DEVICE_VCC_MASK (0x3)
#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
#define ONENAND_DEVICE_DENSITY_1Gb (0x003)
#define ONENAND_DEVICE_DENSITY_2Gb (0x004)
#define ONENAND_DEVICE_DENSITY_4Gb (0x005)
/*
* Version ID Register F002h (R)
*/
#define ONENAND_VERSION_PROCESS_SHIFT (8)
/*
* Technology Register F006h (R)
*/
#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0)
/*
* Start Address 1 F100h (R/W)
*/
#define ONENAND_DDP_SHIFT (15)
#define ONENAND_DDP_CHIP0 (0)
#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT)
/*
* Start Address 8 F107h (R/W)
*/
#define ONENAND_FPA_MASK (0x7f)
#define ONENAND_FPA_SHIFT (2)
#define ONENAND_FSA_MASK (0x03)
/*
* Start Buffer Register F200h (R/W)
*/
#define ONENAND_BSA_MASK (0x03)
#define ONENAND_BSA_SHIFT (8)
#define ONENAND_BSA_BOOTRAM (0 << 2)
#define ONENAND_BSA_DATARAM0 (2 << 2)
#define ONENAND_BSA_DATARAM1 (3 << 2)
#define ONENAND_BSC_MASK (0x07)
/*
* Command Register F220h (R/W)
*/
#define ONENAND_CMD_READ (0x00)
#define ONENAND_CMD_READOOB (0x13)
#define ONENAND_CMD_PROG (0x80)
#define ONENAND_CMD_PROGOOB (0x1A)
#define ONENAND_CMD_2X_PROG (0x7D)
#define ONENAND_CMD_2X_CACHE_PROG (0x7F)
#define ONENAND_CMD_UNLOCK (0x23)
#define ONENAND_CMD_LOCK (0x2A)
#define ONENAND_CMD_LOCK_TIGHT (0x2C)
#define ONENAND_CMD_UNLOCK_ALL (0x27)
#define ONENAND_CMD_ERASE (0x94)
#define ONENAND_CMD_MULTIBLOCK_ERASE (0x95)
#define ONENAND_CMD_ERASE_VERIFY (0x71)
#define ONENAND_CMD_RESET (0xF0)
#define ONENAND_CMD_READID (0x90)
#define FLEXONENAND_CMD_RESET (0xF3)
#define FLEXONENAND_CMD_PI_UPDATE (0x05)
#define FLEXONENAND_CMD_PI_ACCESS (0x66)
#define FLEXONENAND_CMD_RECOVER_LSB (0x05)
/* NOTE: Those are not *REAL* commands */
#define ONENAND_CMD_BUFFERRAM (0x1978)
#define FLEXONENAND_CMD_READ_PI (0x1985)
/*
* System Configuration 1 Register F221h (R, R/W)
*/
#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
#define ONENAND_SYS_CFG1_BL_SHIFT (9)
#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
#define ONENAND_SYS_CFG1_RDY (1 << 7)
#define ONENAND_SYS_CFG1_INT (1 << 6)
#define ONENAND_SYS_CFG1_IOBE (1 << 5)
#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
/*
* Controller Status Register F240h (R)
*/
#define ONENAND_CTRL_ONGO (1 << 15)
#define ONENAND_CTRL_LOCK (1 << 14)
#define ONENAND_CTRL_LOAD (1 << 13)
#define ONENAND_CTRL_PROGRAM (1 << 12)
#define ONENAND_CTRL_ERASE (1 << 11)
#define ONENAND_CTRL_ERROR (1 << 10)
#define ONENAND_CTRL_RSTB (1 << 7)
/*
* Interrupt Status Register F241h (R)
*/
#define ONENAND_INT_MASTER (1 << 15)
#define ONENAND_INT_READ (1 << 7)
#define ONENAND_INT_WRITE (1 << 6)
#define ONENAND_INT_ERASE (1 << 5)
#define ONENAND_INT_RESET (1 << 4)
#define ONENAND_INT_CLEAR (0 << 0)
/*
* NAND Flash Write Protection Status Register F24Eh (R)
*/
#define ONENAND_WP_US (1 << 2)
#define ONENAND_WP_LS (1 << 1)
#define ONENAND_WP_LTS (1 << 0)
/*
* ECC Status Reigser FF00h (R)
*/
#define ONENAND_ECC_1BIT (1 << 0)
#define ONENAND_ECC_1BIT_ALL (0x5555)
#define ONENAND_ECC_2BIT (1 << 1)
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
#endif /* __ONENAND_REG_H */
|
1001-study-uboot
|
include/linux/mtd/onenand_regs.h
|
C
|
gpl3
| 6,812
|
/*
* linux/include/linux/mtd/bbm.h
*
* NAND family Bad Block Management (BBM) header file
* - Bad Block Table (BBT) implementation
*
* Copyright (c) 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Copyright (c) 2000-2005
* Thomas Gleixner <tglx@linuxtronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MTD_BBM_H
#define __LINUX_MTD_BBM_H
/* The maximum number of NAND chips in an array */
#ifndef CONFIG_SYS_NAND_MAX_CHIPS
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#endif
/**
* struct nand_bbt_descr - bad block table descriptor
* @param options options for this descriptor
* @param pages the page(s) where we find the bbt, used with
* option BBT_ABSPAGE when bbt is searched,
* then we store the found bbts pages here.
* Its an array and supports up to 8 chips now
* @param offs offset of the pattern in the oob area of the page
* @param veroffs offset of the bbt version counter in the oob are of the page
* @param version version read from the bbt page during scan
* @param len length of the pattern, if 0 no pattern check is performed
* @param maxblocks maximum number of blocks to search for a bbt. This number of
* blocks is reserved at the end of the device
* where the tables are written.
* @param reserved_block_code if non-0, this pattern denotes a reserved
* (rather than bad) block in the stored bbt
* @param pattern pattern to identify bad block table or factory marked
* good / bad blocks, can be NULL, if len = 0
*
* Descriptor for the bad block table marker and the descriptor for the
* pattern which identifies good and bad blocks. The assumption is made
* that the pattern and the version count are always located in the oob area
* of the first block.
*/
struct nand_bbt_descr {
int options;
int pages[CONFIG_SYS_NAND_MAX_CHIPS];
int offs;
int veroffs;
uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
int len;
int maxblocks;
int reserved_block_code;
uint8_t *pattern;
};
/* Options for the bad block table descriptors */
/* The number of bits used per block in the bbt on the device */
#define NAND_BBT_NRBITS_MSK 0x0000000F
#define NAND_BBT_1BIT 0x00000001
#define NAND_BBT_2BIT 0x00000002
#define NAND_BBT_4BIT 0x00000004
#define NAND_BBT_8BIT 0x00000008
/* The bad block table is in the last good block of the device */
#define NAND_BBT_LASTBLOCK 0x00000010
/* The bbt is at the given page, else we must scan for the bbt */
#define NAND_BBT_ABSPAGE 0x00000020
/* The bbt is at the given page, else we must scan for the bbt */
#define NAND_BBT_SEARCH 0x00000040
/* bbt is stored per chip on multichip devices */
#define NAND_BBT_PERCHIP 0x00000080
/* bbt has a version counter at offset veroffs */
#define NAND_BBT_VERSION 0x00000100
/* Create a bbt if none axists */
#define NAND_BBT_CREATE 0x00000200
/* Search good / bad pattern through all pages of a block */
#define NAND_BBT_SCANALLPAGES 0x00000400
/* Scan block empty during good / bad block scan */
#define NAND_BBT_SCANEMPTY 0x00000800
/* Write bbt if neccecary */
#define NAND_BBT_WRITE 0x00001000
/* Read and write back block contents when writing bbt */
#define NAND_BBT_SAVECONTENT 0x00002000
/* Search good / bad pattern on the first and the second page */
#define NAND_BBT_SCAN2NDPAGE 0x00004000
/* The maximum number of blocks to scan for a bbt */
#define NAND_BBT_SCAN_MAXBLOCKS 4
/*
* Constants for oob configuration
*/
#define ONENAND_BADBLOCK_POS 0
/*
* Bad block scanning errors
*/
#define ONENAND_BBT_READ_ERROR 1
#define ONENAND_BBT_READ_ECC_ERROR 2
#define ONENAND_BBT_READ_FATAL_ERROR 4
/**
* struct bbt_info - [GENERIC] Bad Block Table data structure
* @param bbt_erase_shift [INTERN] number of address bits in a bbt entry
* @param badblockpos [INTERN] position of the bad block marker in the oob area
* @param bbt [INTERN] bad block table pointer
* @param badblock_pattern [REPLACEABLE] bad block scan pattern used for initial bad block scan
* @param priv [OPTIONAL] pointer to private bbm date
*/
struct bbm_info {
int bbt_erase_shift;
int badblockpos;
int options;
uint8_t *bbt;
int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
/* TODO Add more NAND specific fileds */
struct nand_bbt_descr *badblock_pattern;
void *priv;
};
/* OneNAND BBT interface */
extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int onenand_default_bbt (struct mtd_info *mtd);
#endif /* __LINUX_MTD_BBM_H */
|
1001-study-uboot
|
include/linux/mtd/bbm.h
|
C
|
gpl3
| 4,658
|
/*
* Copied from Linux:
* commit 37487a56523d402e25650da16c337acf4cecd13d
* Author: Christoph Lameter <clameter@sgi.com>
*/
#ifndef __LINUX_KBUILD_H
#define __LINUX_KBUILD_H
#define DEFINE(sym, val) \
asm volatile("\n->" #sym " %0 " #val : : "i" (val))
#define BLANK() asm volatile("\n->" : : )
#define OFFSET(sym, str, mem) \
DEFINE(sym, offsetof(struct str, mem))
#define COMMENT(x) \
asm volatile("\n->#" x)
#endif
|
1001-study-uboot
|
include/linux/kbuild.h
|
C
|
gpl3
| 430
|
#ifndef _LINUX_CONFIG_H
#define _LINUX_CONFIG_H
/* #include <linux/autoconf.h> */
#endif
|
1001-study-uboot
|
include/linux/config.h
|
C
|
gpl3
| 91
|
/*
* linux/mdio.h: definitions for MDIO (clause 45) transceivers
* Copyright 2006-2009 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation, incorporated herein by reference.
*/
#ifndef __LINUX_MDIO_H__
#define __LINUX_MDIO_H__
#include <linux/mii.h>
/* MDIO Manageable Devices (MMDs). */
#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/
* Physical Medium Dependent */
#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
#define MDIO_MMD_TC 6 /* Transmission Convergence */
#define MDIO_MMD_AN 7 /* Auto-Negotiation */
#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
/* Generic MDIO registers. */
#define MDIO_CTRL1 MII_BMCR
#define MDIO_STAT1 MII_BMSR
#define MDIO_DEVID1 MII_PHYSID1
#define MDIO_DEVID2 MII_PHYSID2
#define MDIO_SPEED 4 /* Speed ability */
#define MDIO_DEVS1 5 /* Devices in package */
#define MDIO_DEVS2 6
#define MDIO_CTRL2 7 /* 10G control 2 */
#define MDIO_STAT2 8 /* 10G status 2 */
#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
#define MDIO_PKGID1 14 /* Package identifier */
#define MDIO_PKGID2 15
#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
/* Media-dependent registers. */
#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
* Lanes B-D are numbered 134-136. */
#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
/* Control register 1. */
/* Enable extended speed selection */
#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
/* All speed selection bits */
#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
#define MDIO_CTRL1_LPOWER BMCR_PDOWN
#define MDIO_CTRL1_RESET BMCR_RESET
#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
/* 10 Gb/s */
#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
/* 10PASS-TS/2BASE-TL */
#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
/* Status register 1. */
#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
#define MDIO_STAT1_FAULT 0x0080 /* Fault */
#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */
/* Speed register. */
#define MDIO_SPEED_10G 0x0001 /* 10G capable */
#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
#define MDIO_DEVS_LINK (MDIO_DEVS_PMAPMD | \
MDIO_DEVS_WIS | \
MDIO_DEVS_PCS | \
MDIO_DEVS_PHYXS | \
MDIO_DEVS_DTEXS | \
MDIO_DEVS_AN)
/* Control register 2. */
#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
/* Status register 2. */
#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
/* Transmit disable register. */
#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
/* Receive signal detect register. */
#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
/* Extended abilities register. */
#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
/* PHY XGXS lane state register. */
#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
/* PMA 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */
/* PMA 10GBASE-T TX power register. */
#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
/* PMA 10GBASE-T SNR registers. */
/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
#define MDIO_PMA_10GBT_SNR_MAX 127
/* PMA 10GBASE-R FEC ability register. */
#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
/* PCS 10GBASE-R/-T status register 1. */
#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */
/* PCS 10GBASE-R/-T status register 2. */
#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
/* AN 10GBASE-T control register. */
#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
/* AN 10GBASE-T status register. */
#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */
#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */
#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */
#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */
#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
/* AN EEE Advertisement register. */
#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
/* LASI RX_ALARM control/status registers. */
#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */
/* LASI TX_ALARM control/status registers. */
#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */
#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */
#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */
/* LASI control/status registers. */
#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */
#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */
#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */
/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
#define MDIO_PHY_ID_C45 0x8000
#define MDIO_PHY_ID_PRTAD 0x03e0
#define MDIO_PHY_ID_DEVAD 0x001f
#define MDIO_PHY_ID_C45_MASK \
(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
#define MDIO_PRTAD_NONE (-1)
#define MDIO_DEVAD_NONE (-1)
#define MDIO_EMULATE_C22 4
#endif /* __LINUX_MDIO_H__ */
|
1001-study-uboot
|
include/linux/mdio.h
|
C
|
gpl3
| 13,289
|
/*
* Copyright 2004, 2007 Freescale Semiconductor.
* Copyright(c) 2003 Motorola Inc.
*/
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
/* define for common ppc_asm.tmpl */
#define EXC_OFF_SYS_RESET 0x100 /* System reset */
#define _START_OFFSET 0
#if defined(CONFIG_E500)
#include <e500.h>
#endif
/*
* SCCR - System Clock Control Register, 9-8
*/
#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
#define SCCR_DFBRG_SHIFT 0
#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
/*
* Define default values for some CCSR macros to make header files cleaner*
*
* To completely disable CCSR relocation in a board header file, define
* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
* to a value that is the same as CONFIG_SYS_CCSRBAR.
*/
#ifdef CONFIG_SYS_CCSRBAR_PHYS
#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
#endif
#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#ifndef CONFIG_SYS_IMMR
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
#endif
#endif /* __MPC85xx_H__ */
|
1001-study-uboot
|
include/mpc85xx.h
|
C
|
gpl3
| 2,002
|
/*
* (C) Copyright 2008 Semihalf
*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef __IMAGE_H__
#define __IMAGE_H__
#include "compiler.h"
#ifdef USE_HOSTCC
/* new uImage format support enabled on host */
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#else
#include <lmb.h>
#include <asm/u-boot.h>
#include <command.h>
#endif /* USE_HOSTCC */
#if defined(CONFIG_FIT)
#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#define CONFIG_MD5 /* FIT images need MD5 support */
#define CONFIG_SHA1 /* and SHA1 */
#endif
/*
* Operating System Codes
*/
#define IH_OS_INVALID 0 /* Invalid OS */
#define IH_OS_OPENBSD 1 /* OpenBSD */
#define IH_OS_NETBSD 2 /* NetBSD */
#define IH_OS_FREEBSD 3 /* FreeBSD */
#define IH_OS_4_4BSD 4 /* 4.4BSD */
#define IH_OS_LINUX 5 /* Linux */
#define IH_OS_SVR4 6 /* SVR4 */
#define IH_OS_ESIX 7 /* Esix */
#define IH_OS_SOLARIS 8 /* Solaris */
#define IH_OS_IRIX 9 /* Irix */
#define IH_OS_SCO 10 /* SCO */
#define IH_OS_DELL 11 /* Dell */
#define IH_OS_NCR 12 /* NCR */
#define IH_OS_LYNXOS 13 /* LynxOS */
#define IH_OS_VXWORKS 14 /* VxWorks */
#define IH_OS_PSOS 15 /* pSOS */
#define IH_OS_QNX 16 /* QNX */
#define IH_OS_U_BOOT 17 /* Firmware */
#define IH_OS_RTEMS 18 /* RTEMS */
#define IH_OS_ARTOS 19 /* ARTOS */
#define IH_OS_UNITY 20 /* Unity OS */
#define IH_OS_INTEGRITY 21 /* INTEGRITY */
#define IH_OS_OSE 22 /* OSE */
/*
* CPU Architecture Codes (supported by Linux)
*/
#define IH_ARCH_INVALID 0 /* Invalid CPU */
#define IH_ARCH_ALPHA 1 /* Alpha */
#define IH_ARCH_ARM 2 /* ARM */
#define IH_ARCH_I386 3 /* Intel x86 */
#define IH_ARCH_IA64 4 /* IA64 */
#define IH_ARCH_MIPS 5 /* MIPS */
#define IH_ARCH_MIPS64 6 /* MIPS 64 Bit */
#define IH_ARCH_PPC 7 /* PowerPC */
#define IH_ARCH_S390 8 /* IBM S390 */
#define IH_ARCH_SH 9 /* SuperH */
#define IH_ARCH_SPARC 10 /* Sparc */
#define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */
#define IH_ARCH_M68K 12 /* M68K */
#define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */
#define IH_ARCH_NIOS2 15 /* Nios-II */
#define IH_ARCH_BLACKFIN 16 /* Blackfin */
#define IH_ARCH_AVR32 17 /* AVR32 */
#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */
#define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */
#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */
/*
* Image Types
*
* "Standalone Programs" are directly runnable in the environment
* provided by U-Boot; it is expected that (if they behave
* well) you can continue to work in U-Boot after return from
* the Standalone Program.
* "OS Kernel Images" are usually images of some Embedded OS which
* will take over control completely. Usually these programs
* will install their own set of exception handlers, device
* drivers, set up the MMU, etc. - this means, that you cannot
* expect to re-enter U-Boot except by resetting the CPU.
* "RAMDisk Images" are more or less just data blocks, and their
* parameters (address, size) are passed to an OS kernel that is
* being started.
* "Multi-File Images" contain several images, typically an OS
* (Linux) kernel image and one or more data images like
* RAMDisks. This construct is useful for instance when you want
* to boot over the network using BOOTP etc., where the boot
* server provides just a single image file, but you want to get
* for instance an OS kernel and a RAMDisk image.
*
* "Multi-File Images" start with a list of image sizes, each
* image size (in bytes) specified by an "uint32_t" in network
* byte order. This list is terminated by an "(uint32_t)0".
* Immediately after the terminating 0 follow the images, one by
* one, all aligned on "uint32_t" boundaries (size rounded up to
* a multiple of 4 bytes - except for the last file).
*
* "Firmware Images" are binary images containing firmware (like
* U-Boot or FPGA images) which usually will be programmed to
* flash memory.
*
* "Script files" are command sequences that will be executed by
* U-Boot's command interpreter; this feature is especially
* useful when you configure U-Boot to use a real shell (hush)
* as command interpreter (=> Shell Scripts).
*/
#define IH_TYPE_INVALID 0 /* Invalid Image */
#define IH_TYPE_STANDALONE 1 /* Standalone Program */
#define IH_TYPE_KERNEL 2 /* OS Kernel Image */
#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */
#define IH_TYPE_MULTI 4 /* Multi-File Image */
#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
#define IH_TYPE_SCRIPT 6 /* Script file */
#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */
#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */
#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */
#define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */
#define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */
#define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */
#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */
#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
/*
* Compression Types
*/
#define IH_COMP_NONE 0 /* No Compression Used */
#define IH_COMP_GZIP 1 /* gzip Compression Used */
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
#define IH_COMP_LZMA 3 /* lzma Compression Used */
#define IH_COMP_LZO 4 /* lzo Compression Used */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
/*
* Legacy format image header,
* all data in network byte order (aka natural aka bigendian).
*/
typedef struct image_header {
uint32_t ih_magic; /* Image Header Magic Number */
uint32_t ih_hcrc; /* Image Header CRC Checksum */
uint32_t ih_time; /* Image Creation Timestamp */
uint32_t ih_size; /* Image Data Size */
uint32_t ih_load; /* Data Load Address */
uint32_t ih_ep; /* Entry Point Address */
uint32_t ih_dcrc; /* Image Data CRC Checksum */
uint8_t ih_os; /* Operating System */
uint8_t ih_arch; /* CPU architecture */
uint8_t ih_type; /* Image Type */
uint8_t ih_comp; /* Compression Type */
uint8_t ih_name[IH_NMLEN]; /* Image Name */
} image_header_t;
typedef struct image_info {
ulong start, end; /* start/end of blob */
ulong image_start, image_len; /* start of image within blob, len of image */
ulong load; /* load addr for the image */
uint8_t comp, type, os; /* compression, type of image, os type */
} image_info_t;
/*
* Legacy and FIT format headers used by do_bootm() and do_bootm_<os>()
* routines.
*/
typedef struct bootm_headers {
/*
* Legacy os image header, if it is a multi component image
* then boot_get_ramdisk() and get_fdt() will attempt to get
* data from second and third component accordingly.
*/
image_header_t *legacy_hdr_os; /* image header pointer */
image_header_t legacy_hdr_os_copy; /* header copy */
ulong legacy_hdr_valid;
#if defined(CONFIG_FIT)
const char *fit_uname_cfg; /* configuration node unit name */
void *fit_hdr_os; /* os FIT image header */
const char *fit_uname_os; /* os subimage node unit name */
int fit_noffset_os; /* os subimage node offset */
void *fit_hdr_rd; /* init ramdisk FIT image header */
const char *fit_uname_rd; /* init ramdisk subimage node unit name */
int fit_noffset_rd; /* init ramdisk subimage node offset */
void *fit_hdr_fdt; /* FDT blob FIT image header */
const char *fit_uname_fdt; /* FDT blob subimage node unit name */
int fit_noffset_fdt;/* FDT blob subimage node offset */
#endif
#ifndef USE_HOSTCC
image_info_t os; /* os image info */
ulong ep; /* entry point of OS */
ulong rd_start, rd_end;/* ramdisk start/end */
#ifdef CONFIG_OF_LIBFDT
char *ft_addr; /* flat dev tree address */
#endif
ulong ft_len; /* length of flat device tree */
ulong initrd_start;
ulong initrd_end;
ulong cmdline_start;
ulong cmdline_end;
bd_t *kbd;
#endif
int verify; /* getenv("verify")[0] != 'n' */
#define BOOTM_STATE_START (0x00000001)
#define BOOTM_STATE_LOADOS (0x00000002)
#define BOOTM_STATE_RAMDISK (0x00000004)
#define BOOTM_STATE_FDT (0x00000008)
#define BOOTM_STATE_OS_CMDLINE (0x00000010)
#define BOOTM_STATE_OS_BD_T (0x00000020)
#define BOOTM_STATE_OS_PREP (0x00000040)
#define BOOTM_STATE_OS_GO (0x00000080)
int state;
#ifdef CONFIG_LMB
struct lmb lmb; /* for memory mgmt */
#endif
} bootm_headers_t;
/*
* Some systems (for example LWMON) have very short watchdog periods;
* we must make sure to split long operations like memmove() or
* checksum calculations into reasonable chunks.
*/
#ifndef CHUNKSZ
#define CHUNKSZ (64 * 1024)
#endif
#ifndef CHUNKSZ_CRC32
#define CHUNKSZ_CRC32 (64 * 1024)
#endif
#ifndef CHUNKSZ_MD5
#define CHUNKSZ_MD5 (64 * 1024)
#endif
#ifndef CHUNKSZ_SHA1
#define CHUNKSZ_SHA1 (64 * 1024)
#endif
#define uimage_to_cpu(x) be32_to_cpu(x)
#define cpu_to_uimage(x) cpu_to_be32(x)
/*
* Translation table for entries of a specific type; used by
* get_table_entry_id() and get_table_entry_name().
*/
typedef struct table_entry {
int id;
char *sname; /* short (input) name to find table entry */
char *lname; /* long (output) name to print for messages */
} table_entry_t;
/*
* get_table_entry_id() scans the translation table trying to find an
* entry that matches the given short name. If a matching entry is
* found, it's id is returned to the caller.
*/
int get_table_entry_id(const table_entry_t *table,
const char *table_name, const char *name);
/*
* get_table_entry_name() scans the translation table trying to find
* an entry that matches the given id. If a matching entry is found,
* its long name is returned to the caller.
*/
char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
const char *genimg_get_os_name(uint8_t os);
const char *genimg_get_arch_name(uint8_t arch);
const char *genimg_get_type_name(uint8_t type);
const char *genimg_get_comp_name(uint8_t comp);
int genimg_get_os_id(const char *name);
int genimg_get_arch_id(const char *name);
int genimg_get_type_id(const char *name);
int genimg_get_comp_id(const char *name);
void genimg_print_size(uint32_t size);
#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
int genimg_get_format(void *img_addr);
int genimg_has_config(bootm_headers_t *images);
ulong genimg_get_image(ulong img_addr);
int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, ulong *rd_start, ulong *rd_end);
#ifdef CONFIG_OF_LIBFDT
int boot_get_fdt(int flag, int argc, char * const argv[],
bootm_headers_t *images, char **of_flat_tree, ulong *of_size);
void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
#endif
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
ulong *initrd_start, ulong *initrd_end);
#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */
#ifdef CONFIG_SYS_BOOT_GET_KBD
int boot_get_kbd(struct lmb *lmb, bd_t **kbd);
#endif /* CONFIG_SYS_BOOT_GET_KBD */
#endif /* !USE_HOSTCC */
/*******************************************************************/
/* Legacy format specific code (prefixed with image_) */
/*******************************************************************/
static inline uint32_t image_get_header_size(void)
{
return (sizeof(image_header_t));
}
#define image_get_hdr_l(f) \
static inline uint32_t image_get_##f(const image_header_t *hdr) \
{ \
return uimage_to_cpu(hdr->ih_##f); \
}
image_get_hdr_l(magic) /* image_get_magic */
image_get_hdr_l(hcrc) /* image_get_hcrc */
image_get_hdr_l(time) /* image_get_time */
image_get_hdr_l(size) /* image_get_size */
image_get_hdr_l(load) /* image_get_load */
image_get_hdr_l(ep) /* image_get_ep */
image_get_hdr_l(dcrc) /* image_get_dcrc */
#define image_get_hdr_b(f) \
static inline uint8_t image_get_##f(const image_header_t *hdr) \
{ \
return hdr->ih_##f; \
}
image_get_hdr_b(os) /* image_get_os */
image_get_hdr_b(arch) /* image_get_arch */
image_get_hdr_b(type) /* image_get_type */
image_get_hdr_b(comp) /* image_get_comp */
static inline char *image_get_name(const image_header_t *hdr)
{
return (char *)hdr->ih_name;
}
static inline uint32_t image_get_data_size(const image_header_t *hdr)
{
return image_get_size(hdr);
}
/**
* image_get_data - get image payload start address
* @hdr: image header
*
* image_get_data() returns address of the image payload. For single
* component images it is image data start. For multi component
* images it points to the null terminated table of sub-images sizes.
*
* returns:
* image payload data start address
*/
static inline ulong image_get_data(const image_header_t *hdr)
{
return ((ulong)hdr + image_get_header_size());
}
static inline uint32_t image_get_image_size(const image_header_t *hdr)
{
return (image_get_size(hdr) + image_get_header_size());
}
static inline ulong image_get_image_end(const image_header_t *hdr)
{
return ((ulong)hdr + image_get_image_size(hdr));
}
#define image_set_hdr_l(f) \
static inline void image_set_##f(image_header_t *hdr, uint32_t val) \
{ \
hdr->ih_##f = cpu_to_uimage(val); \
}
image_set_hdr_l(magic) /* image_set_magic */
image_set_hdr_l(hcrc) /* image_set_hcrc */
image_set_hdr_l(time) /* image_set_time */
image_set_hdr_l(size) /* image_set_size */
image_set_hdr_l(load) /* image_set_load */
image_set_hdr_l(ep) /* image_set_ep */
image_set_hdr_l(dcrc) /* image_set_dcrc */
#define image_set_hdr_b(f) \
static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
{ \
hdr->ih_##f = val; \
}
image_set_hdr_b(os) /* image_set_os */
image_set_hdr_b(arch) /* image_set_arch */
image_set_hdr_b(type) /* image_set_type */
image_set_hdr_b(comp) /* image_set_comp */
static inline void image_set_name(image_header_t *hdr, const char *name)
{
strncpy(image_get_name(hdr), name, IH_NMLEN);
}
int image_check_hcrc(const image_header_t *hdr);
int image_check_dcrc(const image_header_t *hdr);
#ifndef USE_HOSTCC
int getenv_yesno(char *var);
ulong getenv_bootm_low(void);
phys_size_t getenv_bootm_size(void);
phys_size_t getenv_bootm_mapsize(void);
void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
#endif
static inline int image_check_magic(const image_header_t *hdr)
{
return (image_get_magic(hdr) == IH_MAGIC);
}
static inline int image_check_type(const image_header_t *hdr, uint8_t type)
{
return (image_get_type(hdr) == type);
}
static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
{
return (image_get_arch(hdr) == arch);
}
static inline int image_check_os(const image_header_t *hdr, uint8_t os)
{
return (image_get_os(hdr) == os);
}
ulong image_multi_count(const image_header_t *hdr);
void image_multi_getimg(const image_header_t *hdr, ulong idx,
ulong *data, ulong *len);
void image_print_contents(const void *hdr);
#ifndef USE_HOSTCC
static inline int image_check_target_arch(const image_header_t *hdr)
{
#ifndef IH_ARCH_DEFAULT
# error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h"
#endif
return image_check_arch(hdr, IH_ARCH_DEFAULT);
}
#endif /* USE_HOSTCC */
/*******************************************************************/
/* New uImage format specific code (prefixed with fit_) */
/*******************************************************************/
#if defined(CONFIG_FIT)
#define FIT_IMAGES_PATH "/images"
#define FIT_CONFS_PATH "/configurations"
/* hash node */
#define FIT_HASH_NODENAME "hash"
#define FIT_ALGO_PROP "algo"
#define FIT_VALUE_PROP "value"
/* image node */
#define FIT_DATA_PROP "data"
#define FIT_TIMESTAMP_PROP "timestamp"
#define FIT_DESC_PROP "description"
#define FIT_ARCH_PROP "arch"
#define FIT_TYPE_PROP "type"
#define FIT_OS_PROP "os"
#define FIT_COMP_PROP "compression"
#define FIT_ENTRY_PROP "entry"
#define FIT_LOAD_PROP "load"
/* configuration node */
#define FIT_KERNEL_PROP "kernel"
#define FIT_RAMDISK_PROP "ramdisk"
#define FIT_FDT_PROP "fdt"
#define FIT_DEFAULT_PROP "default"
#define FIT_MAX_HASH_LEN 20 /* max(crc32_len(4), sha1_len(20)) */
/* cmdline argument format parsing */
inline int fit_parse_conf(const char *spec, ulong addr_curr,
ulong *addr, const char **conf_name);
inline int fit_parse_subimage(const char *spec, ulong addr_curr,
ulong *addr, const char **image_name);
void fit_print_contents(const void *fit);
void fit_image_print(const void *fit, int noffset, const char *p);
void fit_image_print_hash(const void *fit, int noffset, const char *p);
/**
* fit_get_end - get FIT image size
* @fit: pointer to the FIT format image header
*
* returns:
* size of the FIT image (blob) in memory
*/
static inline ulong fit_get_size(const void *fit)
{
return fdt_totalsize(fit);
}
/**
* fit_get_end - get FIT image end
* @fit: pointer to the FIT format image header
*
* returns:
* end address of the FIT image (blob) in memory
*/
static inline ulong fit_get_end(const void *fit)
{
return (ulong)fit + fdt_totalsize(fit);
}
/**
* fit_get_name - get FIT node name
* @fit: pointer to the FIT format image header
*
* returns:
* NULL, on error
* pointer to node name, on success
*/
static inline const char *fit_get_name(const void *fit_hdr,
int noffset, int *len)
{
return fdt_get_name(fit_hdr, noffset, len);
}
int fit_get_desc(const void *fit, int noffset, char **desc);
int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp);
int fit_image_get_node(const void *fit, const char *image_uname);
int fit_image_get_os(const void *fit, int noffset, uint8_t *os);
int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch);
int fit_image_get_type(const void *fit, int noffset, uint8_t *type);
int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp);
int fit_image_get_load(const void *fit, int noffset, ulong *load);
int fit_image_get_entry(const void *fit, int noffset, ulong *entry);
int fit_image_get_data(const void *fit, int noffset,
const void **data, size_t *size);
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
int *value_len);
int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
int fit_set_hashes(void *fit);
int fit_image_set_hashes(void *fit, int image_noffset);
int fit_image_hash_set_value(void *fit, int noffset, uint8_t *value,
int value_len);
int fit_image_check_hashes(const void *fit, int noffset);
int fit_all_image_check_hashes(const void *fit);
int fit_image_check_os(const void *fit, int noffset, uint8_t os);
int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
int fit_image_check_type(const void *fit, int noffset, uint8_t type);
int fit_image_check_comp(const void *fit, int noffset, uint8_t comp);
int fit_check_format(const void *fit);
int fit_conf_get_node(const void *fit, const char *conf_uname);
int fit_conf_get_kernel_node(const void *fit, int noffset);
int fit_conf_get_ramdisk_node(const void *fit, int noffset);
int fit_conf_get_fdt_node(const void *fit, int noffset);
void fit_conf_print(const void *fit, int noffset, const char *p);
#ifndef USE_HOSTCC
static inline int fit_image_check_target_arch(const void *fdt, int node)
{
return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
}
#endif /* USE_HOSTCC */
#ifdef CONFIG_FIT_VERBOSE
#define fit_unsupported(msg) printf("! %s:%d " \
"FIT images not supported for '%s'\n", \
__FILE__, __LINE__, (msg))
#define fit_unsupported_reset(msg) printf("! %s:%d " \
"FIT images not supported for '%s' " \
"- must reset board to recover!\n", \
__FILE__, __LINE__, (msg))
#else
#define fit_unsupported(msg)
#define fit_unsupported_reset(msg)
#endif /* CONFIG_FIT_VERBOSE */
#endif /* CONFIG_FIT */
#endif /* __IMAGE_H__ */
|
1001-study-uboot
|
include/image.h
|
C
|
gpl3
| 21,346
|
#ifndef _SPD_SDRAM_H_
#define _SPD_SDRAM_H_
long int spd_sdram(void);
#endif
|
1001-study-uboot
|
include/spd_sdram.h
|
C
|
gpl3
| 79
|
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Generic RTC interface.
*/
#ifndef _RTC_H_
#define _RTC_H_
/* bcd<->bin functions are needed by almost all the RTC drivers, let's include
* it there instead of in evey single driver */
#include <bcd.h>
/*
* The struct used to pass data from the generic interface code to
* the hardware dependend low-level code ande vice versa. Identical
* to struct rtc_time used by the Linux kernel.
*
* Note that there are small but significant differences to the
* common "struct time":
*
* struct time: struct rtc_time:
* tm_mon 0 ... 11 1 ... 12
* tm_year years since 1900 years since 0
*/
struct rtc_time {
int tm_sec;
int tm_min;
int tm_hour;
int tm_mday;
int tm_mon;
int tm_year;
int tm_wday;
int tm_yday;
int tm_isdst;
};
int rtc_get (struct rtc_time *);
int rtc_set (struct rtc_time *);
void rtc_reset (void);
void GregorianDay (struct rtc_time *);
void to_tm (int, struct rtc_time *);
unsigned long mktime (unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int);
#endif /* _RTC_H_ */
|
1001-study-uboot
|
include/rtc.h
|
C
|
gpl3
| 1,935
|
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* SDRAM Controller
*/
#ifndef __FTSDMC020_H
#define __FTSDMC020_H
#define FTSDMC020_OFFSET_TP0 0x00
#define FTSDMC020_OFFSET_TP1 0x04
#define FTSDMC020_OFFSET_CR 0x08
#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
#define FTSDMC020_OFFSET_BANK1_BSR 0x10
#define FTSDMC020_OFFSET_BANK2_BSR 0x14
#define FTSDMC020_OFFSET_BANK3_BSR 0x18
#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
#define FTSDMC020_OFFSET_BANK5_BSR 0x20
#define FTSDMC020_OFFSET_BANK6_BSR 0x24
#define FTSDMC020_OFFSET_BANK7_BSR 0x28
#define FTSDMC020_OFFSET_ACR 0x34
/*
* Timing Parametet 0 Register
*/
#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
/*
* Timing Parametet 1 Register
*/
#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
/*
* Configuration Register
*/
#define FTSDMC020_CR_SREF (1 << 0)
#define FTSDMC020_CR_PWDN (1 << 1)
#define FTSDMC020_CR_ISMR (1 << 2)
#define FTSDMC020_CR_IREF (1 << 3)
#define FTSDMC020_CR_IPREC (1 << 4)
#define FTSDMC020_CR_REFTYPE (1 << 5)
/*
* SDRAM External Bank Base/Size Register
*/
#define FTSDMC020_BANK_ENABLE (1 << 28)
#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
#define FTSDMC020_BANK_DDW_X4 (0 << 12)
#define FTSDMC020_BANK_DDW_X8 (1 << 12)
#define FTSDMC020_BANK_DDW_X16 (2 << 12)
#define FTSDMC020_BANK_DDW_X32 (3 << 12)
#define FTSDMC020_BANK_DSZ_16M (0 << 8)
#define FTSDMC020_BANK_DSZ_64M (1 << 8)
#define FTSDMC020_BANK_DSZ_128M (2 << 8)
#define FTSDMC020_BANK_DSZ_256M (3 << 8)
#define FTSDMC020_BANK_MBW_8 (0 << 4)
#define FTSDMC020_BANK_MBW_16 (1 << 4)
#define FTSDMC020_BANK_MBW_32 (2 << 4)
#define FTSDMC020_BANK_SIZE_1M 0x0
#define FTSDMC020_BANK_SIZE_2M 0x1
#define FTSDMC020_BANK_SIZE_4M 0x2
#define FTSDMC020_BANK_SIZE_8M 0x3
#define FTSDMC020_BANK_SIZE_16M 0x4
#define FTSDMC020_BANK_SIZE_32M 0x5
#define FTSDMC020_BANK_SIZE_64M 0x6
#define FTSDMC020_BANK_SIZE_128M 0x7
#define FTSDMC020_BANK_SIZE_256M 0x8
/*
* Arbiter Control Register
*/
#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
#define FTSDMC020_ACR_TOE (1 << 8)
#endif /* __FTSDMC020_H */
|
1001-study-uboot
|
include/faraday/ftsdmc020.h
|
C
|
gpl3
| 3,166
|
/*
* Faraday FTSDC010 Secure Digital Memory Card Host Controller
*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __FTSDC010_H
#define __FTSDC010_H
#ifndef __ASSEMBLY__
/* sd controller register */
struct ftsdc010_mmc {
unsigned int cmd; /* 0x00 - command reg */
unsigned int argu; /* 0x04 - argument reg */
unsigned int rsp0; /* 0x08 - response reg0 */
unsigned int rsp1; /* 0x0c - response reg1 */
unsigned int rsp2; /* 0x10 - response reg2 */
unsigned int rsp3; /* 0x14 - response reg3 */
unsigned int rsp_cmd; /* 0x18 - responded cmd reg */
unsigned int dcr; /* 0x1c - data control reg */
unsigned int dtr; /* 0x20 - data timer reg */
unsigned int dlr; /* 0x24 - data length reg */
unsigned int status; /* 0x28 - status reg */
unsigned int clr; /* 0x2c - clear reg */
unsigned int int_mask; /* 0x30 - intrrupt mask reg */
unsigned int pcr; /* 0x34 - power control reg */
unsigned int ccr; /* 0x38 - clock contorl reg */
unsigned int bwr; /* 0x3c - bus width reg */
unsigned int dwr; /* 0x40 - data window reg */
#ifndef CONFIG_FTSDC010_SDIO
unsigned int feature; /* 0x44 - feature reg */
unsigned int rev; /* 0x48 - revision reg */
#else
unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */
unsigned int gpo; /* 0x48 - gerenal purpose output */
unsigned int reserved[8]; /* 0x50 - 0x68 reserved */
unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */
unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */
unsigned int sdio_status; /* 0x74 - SDIO status regi */
unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */
unsigned int feature; /* 0x9c - feature reg */
unsigned int rev; /* 0xa0 - revision reg */
#endif /* CONFIG_FTSDC010_SDIO */
};
struct mmc_host {
struct ftsdc010_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int fifo_len; /* bytes */
unsigned int last_opcode; /* Last OP Code */
unsigned int card_type; /* Card type */
};
/* functions */
int ftsdc010_mmc_init(int dev_index);
#endif /* __ASSEMBLY__ */
/* global defines */
#define FTSDC010_CMD_RETRY 0x100000
#define FTSDC010_PIO_RETRY 100 /* pio retry times */
#define FTSDC010_DELAY_UNIT 100 /* 100 us */
/* define from Linux kernel - include/linux/mmc/card.h */
#define MMC_TYPE_SDIO 2 /* SDIO card */
/* define for mmc layer */
#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
/* this part is strange */
#define FTSDC010_SDIO_CTRL1_REG 0x0000006C
#define FTSDC010_SDIO_CTRL2_REG 0x0000006C
#define FTSDC010_SDIO_STATUS_REG 0x00000070
/* 0x00 - command register */
#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0)
#define FTSDC010_CMD_NEED_RSP (1 << 6)
#define FTSDC010_CMD_LONG_RSP (1 << 7)
#define FTSDC010_CMD_APP_CMD (1 << 8)
#define FTSDC010_CMD_CMD_EN (1 << 9)
#define FTSDC010_CMD_SDC_RST (1 << 10)
#define FTSDC010_CMD_MMC_INT_STOP (1 << 11)
/* 0x18 - responded command register */
#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f)
#define FTSDC010_RSP_CMD_APP (1 << 6)
/* 0x1c - data control register */
#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0)
#define FTSDC010_DCR_DATA_WRITE (1 << 4)
#define FTSDC010_DCR_DMA_EN (1 << 5)
#define FTSDC010_DCR_DATA_EN (1 << 6)
#ifdef CONFIG_FTSDC010_SDIO
#define FTSDC010_DCR_FIFOTH (1 << 7)
#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8)
#define FTSDC010_DCR_FIFO_RST (1 << 10)
#endif /* CONFIG_FTSDC010_SDIO */
#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */
#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */
#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */
#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */
/* CPRM related define */
#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008
#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010
/* 0x28 - status register */
#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0)
#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1)
#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2)
#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3)
#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4)
#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5)
#define FTSDC010_STATUS_CMD_SEND (1 << 6)
#define FTSDC010_STATUS_DATA_END (1 << 7)
#define FTSDC010_STATUS_FIFO_URUN (1 << 8)
#define FTSDC010_STATUS_FIFO_ORUN (1 << 9)
#define FTSDC010_STATUS_CARD_CHANGE (1 << 10)
#define FTSDC010_STATUS_CARD_DETECT (1 << 11)
#define FTSDC010_STATUS_WRITE_PROT (1 << 12)
#ifdef CONFIG_FTSDC010_SDIO
#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */
#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */
#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */
#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */
#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
#endif /* CONFIG_FTSDC010_SDIO */
/* 0x2c - clear register */
#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0)
#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1)
#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2)
#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3)
#define FTSDC010_CLR_RSP_CRC_OK (1 << 4)
#define FTSDC010_CLR_DATA_CRC_OK (1 << 5)
#define FTSDC010_CLR_CMD_SEND (1 << 6)
#define FTSDC010_CLR_DATA_END (1 << 7)
#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */
#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */
#define FTSDC010_CLR_CARD_CHANGE (1 << 10)
#ifdef CONFIG_FTSDC010_SDIO
#define FTSDC010_CLR_SDIO_IRPT (1 << 16)
#endif /* CONFIG_FTSDC010_SDIO */
/* 0x30 - interrupt mask register */
#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0)
#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1)
#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2)
#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3)
#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4)
#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5)
#define FTSDC010_INT_MASK_CMD_SEND (1 << 6)
#define FTSDC010_INT_MASK_DATA_END (1 << 7)
#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8)
#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9)
#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10)
#ifdef CONFIG_FTSDC010_SDIO
#define FTSDC010_INT_MASK_CP_READY (1 << 13)
#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14)
#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15)
#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16)
#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
#endif /* CONFIG_FTSDC010_SDIO */
/* ? */
#define FTSDC010_CARD_INSERT 0x0
#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT
/* 0x34 - power control register */
#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0)
#define FTSDC010_PCR_POWER_ON (1 << 4)
/* 0x38 - clock control register */
#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0)
#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */
#define FTSDC010_CCR_CLK_DIS (1 << 8)
/* card type */
#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE
#define FTSDC010_CARD_TYPE_MMC 0x0
/* 0x3c - bus width register */
#define FTSDC010_BWR_SINGLE_BUS (1 << 0)
#define FTSDC010_BWR_WIDE_8_BUS (1 << 1)
#define FTSDC010_BWR_WIDE_4_BUS (1 << 2)
#define FTSDC010_BWR_WIDE_BUS_SUPPORT(x) (((x) >> 3) & 0x3)
#define FTSDC010_BWR_CARD_DETECT (1 << 5)
#define FTSDC010_BWR_1_BUS_SUPPORT 0x0
#define FTSDC010_BWR_4_BUS_SUPPORT 0x1
#define FTSDC010_BWR_8_BUS_SUPPORT 0x2
/* 0x44 or 0x9c - feature register */
#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff)
#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8)
#define FTSDC010_FIFO_DEPTH_4 0x04
#define FTSDC010_FIFO_DEPTH_8 0x08
#define FTSDC010_FIFO_DEPTH_16 0x10
/* 0x48 or 0xa0 - revision register */
#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0)
#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8)
#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16)
#ifdef CONFIG_FTSDC010_SDIO
/* 0x44 - general purpose output */
#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0)
/* 0x6c - sdio control register 1 */
#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0)
#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12)
#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13)
#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14)
#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15)
/* 0x70 - sdio control register 2 */
#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0)
#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1)
/* 0x74 - sdio status register */
#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff)
#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef)
#endif /* CONFIG_FTSDC010_SDIO */
#endif /* __FTSDC010_H */
|
1001-study-uboot
|
include/faraday/ftsdc010.h
|
C
|
gpl3
| 9,326
|
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Static Memory Controller
*/
#ifndef __FTSMC020_H
#define __FTSMC020_H
#ifndef __ASSEMBLY__
struct ftsmc020_bank {
unsigned int cr;
unsigned int tpr;
};
struct ftsmc020 {
struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */
unsigned int pad[8]; /* 0x20 - 0x3c */
unsigned int ssr; /* 0x40 */
};
void ftsmc020_init(void);
#endif /* __ASSEMBLY__ */
/*
* Memory Bank Configuration Register
*/
#define FTSMC020_BANK_ENABLE (1 << 28)
#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
#define FTSMC020_BANK_WPROT (1 << 11)
#define FTSMC020_BANK_TYPE1 (1 << 10)
#define FTSMC020_BANK_TYPE2 (1 << 9)
#define FTSMC020_BANK_TYPE3 (1 << 8)
#define FTSMC020_BANK_SIZE_32K (0xb << 4)
#define FTSMC020_BANK_SIZE_64K (0xc << 4)
#define FTSMC020_BANK_SIZE_128K (0xd << 4)
#define FTSMC020_BANK_SIZE_256K (0xe << 4)
#define FTSMC020_BANK_SIZE_512K (0xf << 4)
#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
#define FTSMC020_BANK_SIZE_64M (0x6 << 4)
#define FTSMC020_BANK_MBW_8 (0x0 << 0)
#define FTSMC020_BANK_MBW_16 (0x1 << 0)
#define FTSMC020_BANK_MBW_32 (0x2 << 0)
/*
* Memory Bank Timing Parameter Register
*/
#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
#define FTSMC020_TPR_RBE (1 << 20)
#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
#endif /* __FTSMC020_H */
|
1001-study-uboot
|
include/faraday/ftsmc020.h
|
C
|
gpl3
| 2,611
|
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Timer
*/
#ifndef __FTTMR010_H
#define __FTTMR010_H
struct fttmr010 {
unsigned int timer1_counter; /* 0x00 */
unsigned int timer1_load; /* 0x04 */
unsigned int timer1_match1; /* 0x08 */
unsigned int timer1_match2; /* 0x0c */
unsigned int timer2_counter; /* 0x10 */
unsigned int timer2_load; /* 0x14 */
unsigned int timer2_match1; /* 0x18 */
unsigned int timer2_match2; /* 0x1c */
unsigned int timer3_counter; /* 0x20 */
unsigned int timer3_load; /* 0x24 */
unsigned int timer3_match1; /* 0x28 */
unsigned int timer3_match2; /* 0x2c */
unsigned int cr; /* 0x30 */
unsigned int interrupt_state; /* 0x34 */
unsigned int interrupt_mask; /* 0x38 */
};
/*
* Timer Control Register
*/
#define FTTMR010_TM3_UPDOWN (1 << 11)
#define FTTMR010_TM2_UPDOWN (1 << 10)
#define FTTMR010_TM1_UPDOWN (1 << 9)
#define FTTMR010_TM3_OFENABLE (1 << 8)
#define FTTMR010_TM3_CLOCK (1 << 7)
#define FTTMR010_TM3_ENABLE (1 << 6)
#define FTTMR010_TM2_OFENABLE (1 << 5)
#define FTTMR010_TM2_CLOCK (1 << 4)
#define FTTMR010_TM2_ENABLE (1 << 3)
#define FTTMR010_TM1_OFENABLE (1 << 2)
#define FTTMR010_TM1_CLOCK (1 << 1)
#define FTTMR010_TM1_ENABLE (1 << 0)
/*
* Timer Interrupt State & Mask Registers
*/
#define FTTMR010_TM3_OVERFLOW (1 << 8)
#define FTTMR010_TM3_MATCH2 (1 << 7)
#define FTTMR010_TM3_MATCH1 (1 << 6)
#define FTTMR010_TM2_OVERFLOW (1 << 5)
#define FTTMR010_TM2_MATCH2 (1 << 4)
#define FTTMR010_TM2_MATCH1 (1 << 3)
#define FTTMR010_TM1_OVERFLOW (1 << 2)
#define FTTMR010_TM1_MATCH2 (1 << 1)
#define FTTMR010_TM1_MATCH1 (1 << 0)
#endif /* __FTTMR010_H */
|
1001-study-uboot
|
include/faraday/fttmr010.h
|
C
|
gpl3
| 2,375
|
/*
* Watchdog driver for the FTWDT010 Watch Dog Driver
*
* (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
* Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
* Based on SoftDog driver by Alan Cox <alan@redhat.com>
*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* 27/11/2004 Initial release, Faraday.
* 12/01/2011 Port to u-boot, Macpaul Lin.
*/
#ifndef __FTWDT010_H
#define __FTWDT010_H
struct ftwdt010_wdt {
unsigned int wdcounter; /* Counter Reg - 0x00 */
unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */
unsigned int wdrestart; /* Counter Restart Reg - 0x08 */
unsigned int wdcr; /* Control Reg - 0x0c */
unsigned int wdstatus; /* Status Reg - 0x10 */
unsigned int wdclear; /* Timer Clear - 0x14 */
unsigned int wdintrlen; /* Interrupt Length - 0x18 */
};
/*
* WDLOAD - Counter Auto Reload Register
* The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default.
* Which means in a 66MHz system, the period of Watch Dog timer reset is
* one second.
*/
#define FTWDT010_WDLOAD(x) ((x) & 0xffffffff)
/*
* WDRESTART - Watch Dog Timer Counter Restart Register
* If writing 0x5AB9 to WDRESTART register, Watch Dog timer will
* automatically reload WDLOAD to WDCOUNTER and restart counting.
*/
#define FTWDT010_WDRESTART_MAGIC 0x5AB9
/* WDCR - Watch Dog Timer Control Register */
#define FTWDT010_WDCR_ENABLE (1 << 0)
#define FTWDT010_WDCR_RST (1 << 1)
#define FTWDT010_WDCR_INTR (1 << 2)
/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */
#define FTWDT010_WDCR_EXT (1 << 3)
/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK.
* The clock source PCLK cannot be gated when system sleeps, even if
* WDCLOCK bit is turned on.
*
* Faraday's Watch Dog timer can be driven by an external clock. The
* programmer just needs to write one to WdCR[WdClock] bit.
*
* Note: There is a limitation between EXTCLK and PCLK:
* EXTCLK cycle time / PCLK cycle time > 2.
* If the system does not need an external clock,
* just keep WdCR[WdClock] bit in its default value.
*/
#define FTWDT010_WDCR_CLOCK (1 << 4)
/*
* WDSTATUS - Watch Dog Timer Status Register
* This bit is set when the counter reaches Zero
*/
#define FTWDT010_WDSTATUS(x) ((x) & 0x1)
/*
* WDCLEAR - Watch Dog Timer Clear Register
* Writing one to this register will clear WDSTATUS.
*/
#define FTWDT010_WDCLEAR (1 << 0)
/*
* WDINTRLEN - Watch Dog Timer Interrupt Length
* This register controls the duration length of wd_rst, wd_intr and wd_ext.
* The default value is 0xFF.
*/
#define FTWDT010_WDINTRLEN(x) ((x) & 0xff)
/*
* Variable timeout should be set in ms.
* (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
* WDLOAD = timeout * TIMEOUT_FACTOR.
*/
#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
void ftwdt010_wdt_reset(void);
void ftwdt010_wdt_disable(void);
#endif /* __FTWDT010_H */
|
1001-study-uboot
|
include/faraday/ftwdt010_wdt.h
|
C
|
gpl3
| 3,700
|
/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
#ifndef __FTAHBC020S_H
#define __FTAHBC202S_H
/* Registers Offsets */
/*
* AHB Slave BSR, offset: n * 4, n=0~31
*/
#ifndef __ASSEMBLY__
struct ftahbc02s {
unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */
unsigned int pcr; /* 0x80 - Priority Ctrl Reg */
unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */
unsigned int cr; /* 0x88 - Ctrl Reg */
};
#endif /* __ASSEMBLY__ */
/*
* FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
*/
#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20)
#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16)
/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */
/*
* FTAHBC020S_PCR - Priority Control Register
*/
#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */
/*
* FTAHBC020S_CR - Interrupt Control Register
*/
#define FTAHBC020S_CR_INTSTS (1 << 24)
#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20)
#define FTAHBC020S_CR_INTSMASK (1 << 16)
#define FTAHBC020S_CR_REMAP (1 << 0)
#endif /* __FTAHBC020S_H */
|
1001-study-uboot
|
include/faraday/ftahbc020s.h
|
C
|
gpl3
| 1,973
|
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* (C) Copyright 2011 Andes Technology Corp
* Macpaul Lin <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* FTSDMC021 - SDRAM Controller
*/
#ifndef __FTSDMC021_H
#define __FTSDMC021_H
#ifndef __ASSEMBLY__
struct ftsdmc021 {
unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */
unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */
unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */
unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */
unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */
unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */
unsigned int frr; /* 0x34 - Flush Request Register */
unsigned int ebisr; /* 0x38 - EBI Support Register */
unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */
unsigned int crr; /* 0x100 - Controller Revision Reg */
unsigned int cfr; /* 0x104 - Controller Feature Reg */
};
#endif /* __ASSEMBLY__ */
/*
* Timing Parameter 1 Register
*/
#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */
#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */
#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */
#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */
#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */
#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20)
/*
* Timing Parameter 2 Register
*/
#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */
/* b(16:19) - Initial Refresh Times */
#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16)
/* b(20:23) - Initial Pre-Charge Times */
#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20)
/*
* SDRAM Configuration Register 1
*/
#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */
#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */
#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */
#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */
/* b(16) MA2T: Double Memory Address Cycle Enable */
#define FTSDMC021_CR1_MA2T(x) (1 << 16)
/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1)
/*
* Configuration Register 2
*/
#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */
#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */
#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */
#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */
#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */
#define FTSDMC021_CR2_REFTYPE (1 << 5)
/*
* SDRAM External Bank Base/Size Register
*/
#define FTSDMC021_BANK_ENABLE (1 << 12)
/* 12-bit base address of external bank.
* Default value is 0x800.
* The 12-bit equals to the haddr[31:20] of AHB address bus. */
#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff)
/*
* Read Arbitration Grant Window Register
*/
#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0)
#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4)
#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8)
#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12)
#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16)
#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20)
#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24)
#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28)
/*
* Flush Request Register
*/
#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0)
#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */
/*
* External Bus Interface Support Register (EBISR)
*/
#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */
#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */
#define FTSDMC021_EBISR_POPREC (1 << 13)
#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */
/*
* Controller Revision Register (CRR, Read Only)
*/
#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff)
#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff)
#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff)
/*
* Controller Feature Register (CFR, Read Only)
*/
#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf)
#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf)
#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1)
#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1)
#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1)
#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1)
#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1)
#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1)
#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1)
#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1)
#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1)
#endif /* __FTSDMC021_H */
|
1001-study-uboot
|
include/faraday/ftsdmc021.h
|
C
|
gpl3
| 5,798
|
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Power Management Unit
*/
#ifndef __FTPMU010_H
#define __FTPMU010_H
#ifndef __ASSEMBLY__
struct ftpmu010 {
unsigned int IDNMBR0; /* 0x00 */
unsigned int reserved0; /* 0x04 */
unsigned int OSCC; /* 0x08 */
unsigned int PMODE; /* 0x0C */
unsigned int PMCR; /* 0x10 */
unsigned int PED; /* 0x14 */
unsigned int PEDSR; /* 0x18 */
unsigned int reserved1; /* 0x1C */
unsigned int PMSR; /* 0x20 */
unsigned int PGSR; /* 0x24 */
unsigned int MFPSR; /* 0x28 */
unsigned int MISC; /* 0x2C */
unsigned int PDLLCR0; /* 0x30 */
unsigned int PDLLCR1; /* 0x34 */
unsigned int AHBMCLKOFF; /* 0x38 */
unsigned int APBMCLKOFF; /* 0x3C */
unsigned int DCSRCR0; /* 0x40 */
unsigned int DCSRCR1; /* 0x44 */
unsigned int DCSRCR2; /* 0x48 */
unsigned int SDRAMHTC; /* 0x4C */
unsigned int PSPR0; /* 0x50 */
unsigned int PSPR1; /* 0x54 */
unsigned int PSPR2; /* 0x58 */
unsigned int PSPR3; /* 0x5C */
unsigned int PSPR4; /* 0x60 */
unsigned int PSPR5; /* 0x64 */
unsigned int PSPR6; /* 0x68 */
unsigned int PSPR7; /* 0x6C */
unsigned int PSPR8; /* 0x70 */
unsigned int PSPR9; /* 0x74 */
unsigned int PSPR10; /* 0x78 */
unsigned int PSPR11; /* 0x7C */
unsigned int PSPR12; /* 0x80 */
unsigned int PSPR13; /* 0x84 */
unsigned int PSPR14; /* 0x88 */
unsigned int PSPR15; /* 0x8C */
unsigned int AHBDMA_RACCS; /* 0x90 */
unsigned int reserved2; /* 0x94 */
unsigned int reserved3; /* 0x98 */
unsigned int JSS; /* 0x9C */
unsigned int CFC_RACC; /* 0xA0 */
unsigned int SSP1_RACC; /* 0xA4 */
unsigned int UART1TX_RACC; /* 0xA8 */
unsigned int UART1RX_RACC; /* 0xAC */
unsigned int UART2TX_RACC; /* 0xB0 */
unsigned int UART2RX_RACC; /* 0xB4 */
unsigned int SDC_RACC; /* 0xB8 */
unsigned int I2SAC97_RACC; /* 0xBC */
unsigned int IRDATX_RACC; /* 0xC0 */
unsigned int reserved4; /* 0xC4 */
unsigned int USBD_RACC; /* 0xC8 */
unsigned int IRDARX_RACC; /* 0xCC */
unsigned int IRDA_RACC; /* 0xD0 */
unsigned int ED0_RACC; /* 0xD4 */
unsigned int ED1_RACC; /* 0xD8 */
};
#endif /* __ASSEMBLY__ */
/*
* ID Number 0 Register
*/
#define FTPMU010_ID_A320A 0x03200000
#define FTPMU010_ID_A320C 0x03200010
#define FTPMU010_ID_A320D 0x03200030
/*
* OSC Control Register
*/
#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
/*
* Power Mode Register
*/
#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
#define FTPMU010_PMODE_FCS (1 << 2)
#define FTPMU010_PMODE_TURBO (1 << 1)
#define FTPMU010_PMODE_SLEEP (1 << 0)
/*
* Power Manager Status Register
*/
#define FTPMU010_PMSR_SMR (1 << 10)
#define FTPMU010_PMSR_RDH (1 << 2)
#define FTPMU010_PMSR_PH (1 << 1)
#define FTPMU010_PMSR_CKEHLOW (1 << 0)
/*
* Multi-Function Port Setting Register
*/
#define FTPMU010_MFPSR_DEBUGSEL (1 << 17)
#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16)
#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15)
#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11)
#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10)
#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9)
#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8)
#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6)
#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5)
#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4)
#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1)
#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0)
/*
* PLL/DLL Control Register 0
* Note:
* 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
* Datasheet indicated it starts at bit #21 which was wrong.
* 2. FTPMU010_PDLLCR0_DLLFRAG:
* Datasheet indicated it has 2 bit which was wrong.
*/
#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12)
#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3)
#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
/*
* SDRAM Signal Hold Time Control Register
*/
#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28)
#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24)
#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20)
#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18)
#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17)
#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16)
#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15)
#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14)
#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13)
#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12)
#ifndef __ASSEMBLY__
void ftpmu010_32768osc_enable(void);
void ftpmu010_dlldis_disable(void);
void ftpmu010_mfpsr_diselect_dev(unsigned int dev);
void ftpmu010_mfpsr_select_dev(unsigned int dev);
void ftpmu010_sdram_clk_disable(unsigned int cr0);
void ftpmu010_sdramhtc_set(unsigned int val);
#endif
#ifdef __ASSEMBLY__
#define FTPMU010_IDNMBR0 0x00
#define FTPMU010_reserved0 0x04
#define FTPMU010_OSCC 0x08
#define FTPMU010_PMODE 0x0C
#define FTPMU010_PMCR 0x10
#define FTPMU010_PED 0x14
#define FTPMU010_PEDSR 0x18
#define FTPMU010_reserved1 0x1C
#define FTPMU010_PMSR 0x20
#define FTPMU010_PGSR 0x24
#define FTPMU010_MFPSR 0x28
#define FTPMU010_MISC 0x2C
#define FTPMU010_PDLLCR0 0x30
#define FTPMU010_PDLLCR1 0x34
#define FTPMU010_AHBMCLKOFF 0x38
#define FTPMU010_APBMCLKOFF 0x3C
#define FTPMU010_DCSRCR0 0x40
#define FTPMU010_DCSRCR1 0x44
#define FTPMU010_DCSRCR2 0x48
#define FTPMU010_SDRAMHTC 0x4C
#define FTPMU010_PSPR0 0x50
#define FTPMU010_PSPR1 0x54
#define FTPMU010_PSPR2 0x58
#define FTPMU010_PSPR3 0x5C
#define FTPMU010_PSPR4 0x60
#define FTPMU010_PSPR5 0x64
#define FTPMU010_PSPR6 0x68
#define FTPMU010_PSPR7 0x6C
#define FTPMU010_PSPR8 0x70
#define FTPMU010_PSPR9 0x74
#define FTPMU010_PSPR10 0x78
#define FTPMU010_PSPR11 0x7C
#define FTPMU010_PSPR12 0x80
#define FTPMU010_PSPR13 0x84
#define FTPMU010_PSPR14 0x88
#define FTPMU010_PSPR15 0x8C
#define FTPMU010_AHBDMA_RACCS 0x90
#define FTPMU010_reserved2 0x94
#define FTPMU010_reserved3 0x98
#define FTPMU010_JSS 0x9C
#define FTPMU010_CFC_RACC 0xA0
#define FTPMU010_SSP1_RACC 0xA4
#define FTPMU010_UART1TX_RACC 0xA8
#define FTPMU010_UART1RX_RACC 0xAC
#define FTPMU010_UART2TX_RACC 0xB0
#define FTPMU010_UART2RX_RACC 0xB4
#define FTPMU010_SDC_RACC 0xB8
#define FTPMU010_I2SAC97_RACC 0xBC
#define FTPMU010_IRDATX_RACC 0xC0
#define FTPMU010_reserved4 0xC4
#define FTPMU010_USBD_RACC 0xC8
#define FTPMU010_IRDARX_RACC 0xCC
#define FTPMU010_IRDA_RACC 0xD0
#define FTPMU010_ED0_RACC 0xD4
#define FTPMU010_ED1_RACC 0xD8
#endif /* __ASSEMBLY__ */
#endif /* __FTPMU010_H */
|
1001-study-uboot
|
include/faraday/ftpmu010.h
|
C
|
gpl3
| 8,057
|
/*
* (C) Copyright 2010
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __GDSYS_FPGA_H
#define __GDSYS_FPGA_H
int init_func_fpga(void);
enum {
FPGA_STATE_DONE_FAILED = 1 << 0,
FPGA_STATE_REFLECTION_FAILED = 1 << 1,
FPGA_STATE_PLATFORM = 1 << 2,
};
int get_fpga_state(unsigned dev);
void print_fpga_state(unsigned dev);
typedef struct ihs_gpio {
u16 read;
u16 clear;
u16 set;
} ihs_gpio_t;
typedef struct ihs_i2c {
u16 write_mailbox;
u16 write_mailbox_ext;
u16 read_mailbox;
u16 read_mailbox_ext;
} ihs_i2c_t;
typedef struct ihs_osd {
u16 version;
u16 features;
u16 control;
u16 xy_size;
u16 xy_scale;
u16 x_pos;
u16 y_pos;
} ihs_osd_t;
#ifdef CONFIG_IO
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_features; /* 0x0004 */
u16 fpga_version; /* 0x0006 */
u16 reserved_0[5]; /* 0x0008 */
u16 quad_serdes_reset; /* 0x0012 */
u16 reserved_1[8181]; /* 0x0014 */
u16 reflection_high; /* 0x3ffe */
} ihs_fpga_t;
#endif
#ifdef CONFIG_IO64
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_features; /* 0x0004 */
u16 fpga_version; /* 0x0006 */
u16 reserved_0[5]; /* 0x0008 */
u16 quad_serdes_reset; /* 0x0012 */
u16 reserved_1[502]; /* 0x0014 */
u16 ch0_status_int; /* 0x0400 */
u16 ch0_config_int; /* 0x0402 */
u16 reserved_2[7677]; /* 0x0404 */
u16 reflection_high; /* 0x3ffe */
} ihs_fpga_t;
#endif
#ifdef CONFIG_IOCON
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[6]; /* 0x0008 */
ihs_gpio_t gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
u16 reserved_1[19]; /* 0x001c */
u16 videocontrol; /* 0x0042 */
u16 reserved_2[93]; /* 0x0044 */
u16 reflection_high; /* 0x00fe */
ihs_osd_t osd; /* 0x0100 */
u16 reserved_3[88]; /* 0x010e */
u16 videomem; /* 0x0800 */
} ihs_fpga_t;
#endif
#ifdef CONFIG_DLVISION_10G
typedef struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[10]; /* 0x0008 */
u16 extended_interrupt; /* 0x001c */
u16 reserved_1[9]; /* 0x001e */
ihs_i2c_t i2c; /* 0x0030 */
u16 reserved_2[16]; /* 0x0038 */
u16 mpc3w_control; /* 0x0058 */
u16 reserved_3[34]; /* 0x005a */
u16 videocontrol; /* 0x009e */
u16 reserved_4[176]; /* 0x00a0 */
ihs_osd_t osd; /* 0x0200 */
u16 reserved_5[761]; /* 0x020e */
u16 videomem; /* 0x0800 */
} ihs_fpga_t;
#endif
#endif
|
1001-study-uboot
|
include/gdsys_fpga.h
|
C
|
gpl3
| 3,381
|
#ifndef __CRAMFS_H
#define __CRAMFS_H
#define CRAMFS_MAGIC 0x28cd3d45 /* some random number */
#define CRAMFS_SIGNATURE "Compressed ROMFS"
/*
* Width of various bitfields in struct cramfs_inode.
* Primarily used to generate warnings in mkcramfs.
*/
#define CRAMFS_MODE_WIDTH 16
#define CRAMFS_UID_WIDTH 16
#define CRAMFS_SIZE_WIDTH 24
#define CRAMFS_GID_WIDTH 8
#define CRAMFS_NAMELEN_WIDTH 6
#define CRAMFS_OFFSET_WIDTH 26
/*
* Since inode.namelen is a unsigned 6-bit number, the maximum cramfs
* path length is 63 << 2 = 252.
*/
#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2)
/*
* Reasonably terse representation of the inode data.
*/
struct cramfs_inode {
u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH;
/* SIZE for device files is i_rdev */
u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH;
/* NAMELEN is the length of the file name, divided by 4 and
rounded up. (cramfs doesn't support hard links.) */
/* OFFSET: For symlinks and non-empty regular files, this
contains the offset (divided by 4) of the file data in
compressed form (starting with an array of block pointers;
see README). For non-empty directories it is the offset
(divided by 4) of the inode of the first file in that
directory. For anything else, offset is zero. */
u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH;
};
struct cramfs_info {
u32 crc;
u32 edition;
u32 blocks;
u32 files;
};
/*
* Superblock information at the beginning of the FS.
*/
struct cramfs_super {
u32 magic; /* 0x28cd3d45 - random number */
u32 size; /* length in bytes */
u32 flags; /* feature flags */
u32 future; /* reserved for future use */
u8 signature[16]; /* "Compressed ROMFS" */
struct cramfs_info fsid; /* unique filesystem info */
u8 name[16]; /* user-defined name */
struct cramfs_inode root; /* root inode data */
};
/*
* Feature flags
*
* 0x00000000 - 0x000000ff: features that work for all past kernels
* 0x00000100 - 0xffffffff: features that don't work for past kernels
*/
#define CRAMFS_FLAG_FSID_VERSION_2 0x00000001 /* fsid version #2 */
#define CRAMFS_FLAG_SORTED_DIRS 0x00000002 /* sorted dirs */
#define CRAMFS_FLAG_HOLES 0x00000100 /* support for holes */
#define CRAMFS_FLAG_WRONG_SIGNATURE 0x00000200 /* reserved */
#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400 /* shifted root fs */
/*
* Valid values in super.flags. Currently we refuse to mount
* if (flags & ~CRAMFS_SUPPORTED_FLAGS). Maybe that should be
* changed to test super.future instead.
*/
#define CRAMFS_SUPPORTED_FLAGS ( 0x000000ff \
| CRAMFS_FLAG_HOLES \
| CRAMFS_FLAG_WRONG_SIGNATURE \
| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
#define CRAMFS_16(x) (x)
#define CRAMFS_24(x) (x)
#define CRAMFS_32(x) (x)
#define CRAMFS_GET_NAMELEN(x) ((x)->namelen)
#define CRAMFS_GET_OFFSET(x) ((x)->offset)
#define CRAMFS_SET_OFFSET(x,y) ((x)->offset = (y))
#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y))
/* Uncompression interfaces to the underlying zlib */
int cramfs_uncompress_block(void *dst, void *src, int srclen);
int cramfs_uncompress_init(void);
int cramfs_uncompress_exit(void);
#endif /* __CRAMFS_H */
|
1001-study-uboot
|
include/cramfs/cramfs_fs.h
|
C
|
gpl3
| 3,177
|
#ifndef _CRAMFS_FS_SB
#define _CRAMFS_FS_SB
/*
* cramfs super-block data in memory
*/
struct cramfs_sb_info {
unsigned long magic;
unsigned long size;
unsigned long blocks;
unsigned long files;
unsigned long flags;
#ifdef CONFIG_CRAMFS_LINEAR
unsigned long linear_phys_addr;
char * linear_virt_addr;
#endif
};
#endif
|
1001-study-uboot
|
include/cramfs/cramfs_fs_sb.h
|
C
|
gpl3
| 349
|
/*
* (C) Copyright 2006 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* DA9030 register definitions */
#define CID 0x00
#define EVENT_A 0x01
#define EVENT_B 0x02
#define EVENT_C 0x03
#define STATUS 0x04
#define IRQ_MASK_A 0x05
#define IRQ_MASK_B 0x06
#define IRQ_MASK_C 0x07
#define SYS_CONTROL_A 0x08
#define SYS_CONTROL_B 0x09
#define FAULT_LOG 0x0A
#define LDO_10_11 0x10
#define LDO_15 0x11
#define LDO_14_16 0x12
#define LDO_18_19 0x13
#define LDO_17_SIMCP0 0x14
#define BUCK2_DVC1 0x15
#define BUCK2_DVC2 0x16
#define REG_CONTROL_1_17 0x17
#define REG_CONTROL_2_18 0x18
#define USBPUMP 0x19
#define SLEEP_CONTROL 0x1A
#define STARTUP_CONTROL 0x1B
#define LED1_CONTROL 0x20
#define LED2_CONTROL 0x21
#define LED3_CONTROL 0x22
#define LED4_CONTROL 0x23
#define LEDPC_CONTROL 0x24
#define WLED_CONTROL 0x25
#define MISC_CONTROLA 0x26
#define MISC_CONTROLB 0x27
#define CHARGE_CONTROL 0x28
#define CCTR_CONTROL 0x29
#define TCTR_CONTROL 0x2A
#define CHARGE_PULSE 0x2B
/* ... some missing ...*/
#define LDO1 0x90
#define LDO2_3 0x91
#define LDO4_5 0x92
#define LDO6_SIMCP 0x93
#define LDO7_8 0x94
#define LDO9_12 0x95
#define BUCK 0x96
#define REG_CONTROL_1_97 0x97
#define REG_CONTROL_2_98 0x98
#define REG_SLEEP_CONTROL1 0x99
#define REG_SLEEP_CONTROL2 0x9A
#define REG_SLEEP_CONTROL3 0x9B
#define ADC_MAN_CONTROL 0xA0
#define ADC_AUTO_CONTROL 0xA1
#define VBATMON 0xA2
#define VBATMONTXMON 0xA3
#define TBATHIGHP 0xA4
#define TBATHIGHN 0xA5
#define TBATLOW 0xA6
#define MAN_RES 0xB0
#define VBAT_RES 0xB1
#define VBATMIN_RES 0xB2
#define VBATMINTXON_RES 0xB3
#define ICHMAX_RES 0xB4
#define ICHMIN_RES 0xB5
#define ICHAVERAGE_RES 0xB6
#define VCHMAX_RES 0xB7
#define VCHMIN_RES 0xB8
#define TBAT_RES 0xB9
#define ADC_IN4_RES 0xBA
#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */
#define STATUS_PWREN1 (1<<1) /* PWREN1 value */
#define STATUS_EXTON (1<<2) /* EXTON value */
#define STATUS_CHDET (1<<3) /* Charger detection status */
#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */
#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */
#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */
#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */
#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1
#define SYS_CONTROL_A_SHUT_DOWN (1<<1)
#define SYS_CONTROL_A_HWRES_ENABLE (1<<2)
#define SYS_CONTROL_A_WDOG_ACTION (1<<3)
#define SYS_CONTROL_A_WATCHDOG (1<<7)
#define MISC_CONTROLB_USB_INT_RISING (1<<2)
#define MISC_CONTROLB_SESSION_VALID_EN (1<<3)
#define USB_PUMP_USBVE (1<<0)
#define USB_PUMP_USBVEP (1<<1)
#define USB_PUMP_SRP_DETECT (1<<2)
#define USB_PUMP_SESSION_VALID (1<<3)
#define USB_PUMP_VBUS_VALID_4_0 (1<<4)
#define USB_PUMP_VBUS_VALID_4_4 (1<<5)
#define USB_PUMP_EN_USBVE (1<<6)
#define USB_PUMP_EN_USBVEP (1<<7)
|
1001-study-uboot
|
include/da9030.h
|
C
|
gpl3
| 3,668
|
#ifndef _ERRNO_H
#include <asm-generic/errno.h>
extern int errno;
#define __set_errno(val) do { errno = val; } while (0)
#endif /* _ERRNO_H */
|
1001-study-uboot
|
include/errno.h
|
C
|
gpl3
| 147
|
/*
* Enable all PHYs
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#ifndef _CONFIG_PHYLIB_ALL_H
#define _CONFIG_PHYLIB_ALL_H
#ifdef CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_MARVELL
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_BROADCOM
#define CONFIG_PHY_DAVICOM
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_LXT
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_PHYLIB_10G
#define CONFIG_PHY_TERANETICS
#endif /* CONFIG_PHYLIB_10G */
#endif /* CONFIG_PHYLIB */
#endif /*_CONFIG_PHYLIB_ALL_H */
|
1001-study-uboot
|
include/config_phylib_all_drivers.h
|
C
|
gpl3
| 721
|
/*
*==========================================================================
*
* crc.h
*
* Interface for the CRC algorithms.
*
*==========================================================================
*####ECOSGPLCOPYRIGHTBEGIN####
* -------------------------------------------
* This file is part of eCos, the Embedded Configurable Operating System.
* Copyright (C) 2002 Andrew Lunn
*
* eCos is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 or (at your option) any later version.
*
* eCos is distributed in the hope that it will be useful, but WITHOUT ANY
* WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with eCos; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*
* As a special exception, if other files instantiate templates or use macros
* or inline functions from this file, or you compile this file and link it
* with other works to produce a work based on this file, this file does not
* by itself cause the resulting work to be covered by the GNU General Public
* License. However the source code for this file must still be made available
* in accordance with section (3) of the GNU General Public License.
*
* This exception does not invalidate any other reasons why a work based on
* this file might be covered by the GNU General Public License.
*
* Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
* at http: *sources.redhat.com/ecos/ecos-license/
* -------------------------------------------
*####ECOSGPLCOPYRIGHTEND####
*==========================================================================
*#####DESCRIPTIONBEGIN####
*
* Author(s): Andrew Lunn
* Contributors: Andrew Lunn
* Date: 2002-08-06
* Purpose:
* Description:
*
* This code is part of eCos (tm).
*
*####DESCRIPTIONEND####
*
*==========================================================================
*/
#ifndef _SERVICES_CRC_CRC_H_
#define _SERVICES_CRC_CRC_H_
#include <linux/types.h>
#ifndef __externC
# ifdef __cplusplus
# define __externC extern "C"
# else
# define __externC extern
# endif
#endif
/* Compute a CRC, using the POSIX 1003 definition */
extern uint32_t
cyg_posix_crc32(unsigned char *s, int len);
/* Gary S. Brown's 32 bit CRC */
extern uint32_t
cyg_crc32(unsigned char *s, int len);
/* Gary S. Brown's 32 bit CRC, but accumulate the result from a */
/* previous CRC calculation */
extern uint32_t
cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
/* Ethernet FCS Algorithm */
extern uint32_t
cyg_ether_crc32(unsigned char *s, int len);
/* Ethernet FCS algorithm, but accumulate the result from a previous */
/* CRC calculation. */
extern uint32_t
cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
/* 16 bit CRC with polynomial x^16+x^12+x^5+1 */
extern uint16_t cyg_crc16(unsigned char *s, int len);
#endif /* _SERVICES_CRC_CRC_H_ */
|
1001-study-uboot
|
include/crc.h
|
C
|
gpl3
| 3,264
|
/*
* include/asm-ppc/mpc5xxx.h
*
* Prototypes, etc. for the Motorola MPC5xxx
* embedded cpu chips
*
* 2003 (c) MontaVista, Software, Inc.
* Author: Dale Farnsworth <dfarnsworth@mvista.com>
*
* 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASMPPC_MPC5XXX_H
#define __ASMPPC_MPC5XXX_H
#include <asm/types.h>
/* Processor name */
#define CPU_ID_STR "MPC5200"
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/* useful macros for manipulating CSx_START/STOP */
#define START_REG(start) ((start) >> 16)
#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
/* Internal memory map */
#define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004)
#define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008)
#define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c)
#define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010)
#define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014)
#define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018)
#define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c)
#define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020)
#define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024)
#define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028)
#define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c)
#define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030)
#define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c)
#define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
#define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
#define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
#define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
#define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
#define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
#define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
#define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
#define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
#define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
#define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300)
#define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500)
#define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600)
#define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00)
#define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00)
#define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00)
#define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00)
#define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000)
#define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
#define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
#define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
#define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
#define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
#define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
#define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
#define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
#define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
#define MPC5XXX_SRAM_SIZE (16*1024)
/* SDRAM Controller */
#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
/* Clock Distribution Module */
#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
#define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008)
#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
#define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014)
#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
/* Local Plus Bus interface */
#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
/* XLB Arbiter registers */
#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
/* GPIO registers */
#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
/* Standard GPIO registers (simple, output only and simple interrupt */
#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
/* WakeUp GPIO registers */
#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
/* GPIO pins, for Rev.B chip */
#define GPIO_WKUP_7 0x80000000UL
#define GPIO_PSC6_0 0x10000000UL
#define GPIO_PSC3_9 0x04000000UL
#define GPIO_PSC1_4 0x01000000UL
#define GPIO_PSC2_4 0x02000000UL
#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
#define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL
#define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL
#define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL
#define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL
#define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL
#define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL
#define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL
#define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL
#define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL
#define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL
#define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL
#define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL
#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
#define MPC5XXX_GPIO_SINT_ETH_16 0x80
#define MPC5XXX_GPIO_SINT_ETH_15 0x40
#define MPC5XXX_GPIO_SINT_ETH_14 0x20
#define MPC5XXX_GPIO_SINT_ETH_13 0x10
#define MPC5XXX_GPIO_SINT_USB1_9 0x08
#define MPC5XXX_GPIO_SINT_PSC3_8 0x04
#define MPC5XXX_GPIO_SINT_PSC3_5 0x02
#define MPC5XXX_GPIO_SINT_PSC3_4 0x01
#define MPC5XXX_GPIO_WKUP_7 0x80
#define MPC5XXX_GPIO_WKUP_6 0x40
#define MPC5XXX_GPIO_WKUP_PSC6_1 0x20
#define MPC5XXX_GPIO_WKUP_PSC6_0 0x10
#define MPC5XXX_GPIO_WKUP_ETH17 0x08
#define MPC5XXX_GPIO_WKUP_PSC3_9 0x04
#define MPC5XXX_GPIO_WKUP_PSC2_4 0x02
#define MPC5XXX_GPIO_WKUP_PSC1_4 0x01
/* PCI registers */
#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
/* Interrupt Controller registers */
#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
#define NR_IRQS 64
/* IRQ mapping - these are our logical IRQ numbers */
#define MPC5XXX_CRIT_IRQ_NUM 4
#define MPC5XXX_MAIN_IRQ_NUM 17
#define MPC5XXX_SDMA_IRQ_NUM 17
#define MPC5XXX_PERP_IRQ_NUM 23
#define MPC5XXX_CRIT_IRQ_BASE 1
#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
/* General Purpose Timers registers */
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
/* ATA registers */
#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
/* I2Cn control register bits */
#define I2C_EN 0x80
#define I2C_IEN 0x40
#define I2C_STA 0x20
#define I2C_TX 0x10
#define I2C_TXAK 0x08
#define I2C_RSTA 0x04
#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
/* I2Cn status register bits */
#define I2C_CF 0x80
#define I2C_AAS 0x40
#define I2C_BB 0x20
#define I2C_AL 0x10
#define I2C_SRW 0x04
#define I2C_IF 0x02
#define I2C_RXAK 0x01
/* SPI control register 1 bits */
#define SPI_CR_LSBFE 0x01
#define SPI_CR_SSOE 0x02
#define SPI_CR_CPHA 0x04
#define SPI_CR_CPOL 0x08
#define SPI_CR_MSTR 0x10
#define SPI_CR_SWOM 0x20
#define SPI_CR_SPE 0x40
#define SPI_CR_SPIE 0x80
/* SPI status register bits */
#define SPI_SR_MODF 0x10
#define SPI_SR_WCOL 0x40
#define SPI_SR_SPIF 0x80
/* SPI port data register bits */
#define SPI_PDR_SS 0x08
/* Programmable Serial Controller (PSC) status register bits */
#define PSC_SR_CDE 0x0080
#define PSC_SR_RXRDY 0x0100
#define PSC_SR_RXFULL 0x0200
#define PSC_SR_TXRDY 0x0400
#define PSC_SR_TXEMP 0x0800
#define PSC_SR_OE 0x1000
#define PSC_SR_PE 0x2000
#define PSC_SR_FE 0x4000
#define PSC_SR_RB 0x8000
/* PSC Command values */
#define PSC_RX_ENABLE 0x0001
#define PSC_RX_DISABLE 0x0002
#define PSC_TX_ENABLE 0x0004
#define PSC_TX_DISABLE 0x0008
#define PSC_SEL_MODE_REG_1 0x0010
#define PSC_RST_RX 0x0020
#define PSC_RST_TX 0x0030
#define PSC_RST_ERR_STAT 0x0040
#define PSC_RST_BRK_CHG_INT 0x0050
#define PSC_START_BRK 0x0060
#define PSC_STOP_BRK 0x0070
/* PSC Rx FIFO status bits */
#define PSC_RX_FIFO_ERR 0x0040
#define PSC_RX_FIFO_UF 0x0020
#define PSC_RX_FIFO_OF 0x0010
#define PSC_RX_FIFO_FR 0x0008
#define PSC_RX_FIFO_FULL 0x0004
#define PSC_RX_FIFO_ALARM 0x0002
#define PSC_RX_FIFO_EMPTY 0x0001
/* PSC interrupt mask bits */
#define PSC_IMR_TXRDY 0x0100
#define PSC_IMR_RXRDY 0x0200
#define PSC_IMR_DB 0x0400
#define PSC_IMR_IPC 0x8000
/* PSC input port change bits */
#define PSC_IPCR_CTS 0x01
#define PSC_IPCR_DCD 0x02
/* PSC mode fields */
#define PSC_MODE_5_BITS 0x00
#define PSC_MODE_6_BITS 0x01
#define PSC_MODE_7_BITS 0x02
#define PSC_MODE_8_BITS 0x03
#define PSC_MODE_PAREVEN 0x00
#define PSC_MODE_PARODD 0x04
#define PSC_MODE_PARFORCE 0x08
#define PSC_MODE_PARNONE 0x10
#define PSC_MODE_ERR 0x20
#define PSC_MODE_FFULL 0x40
#define PSC_MODE_RXRTS 0x80
#define PSC_MODE_ONE_STOP_5_BITS 0x00
#define PSC_MODE_ONE_STOP 0x07
#define PSC_MODE_TWO_STOP 0x0f
/* ATA config fields */
#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
reset */
#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
in PIO */
#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
IORDY protocol */
#ifndef __ASSEMBLY__
/* Memory map registers */
struct mpc5xxx_mmap_ctl {
volatile u32 mbar;
volatile u32 cs0_start; /* 0x0004 */
volatile u32 cs0_stop;
volatile u32 cs1_start; /* 0x000c */
volatile u32 cs1_stop;
volatile u32 cs2_start; /* 0x0014 */
volatile u32 cs2_stop;
volatile u32 cs3_start; /* 0x001c */
volatile u32 cs3_stop;
volatile u32 cs4_start; /* 0x0024 */
volatile u32 cs4_stop;
volatile u32 cs5_start; /* 0x002c */
volatile u32 cs5_stop;
volatile u32 sdram0; /* 0x0034 */
volatile u32 sdram1; /* 0x0038 */
volatile u32 dummy1[4]; /* 0x003c */
volatile u32 boot_start; /* 0x004c */
volatile u32 boot_stop;
volatile u32 ipbi_ws_ctrl; /* 0x0054 */
volatile u32 cs6_start; /* 0x0058 */
volatile u32 cs6_stop;
volatile u32 cs7_start; /* 0x0060 */
volatile u32 cs7_stop;
};
/* Clock distribution module */
struct mpc5xxx_cdm {
volatile u32 jtagid; /* 0x0000 */
volatile u32 porcfg;
volatile u32 brdcrmb; /* 0x0008 */
volatile u32 cfg;
volatile u32 fourtyeight_fdc;/* 0x0010 */
volatile u32 clock_enable;
volatile u32 system_osc; /* 0x0018 */
volatile u32 ccscr;
volatile u32 sreset; /* 0x0020 */
volatile u32 pll_status;
volatile u32 psc1_mccr; /* 0x0028 */
volatile u32 psc2_mccr;
volatile u32 psc3_mccr; /* 0x0030 */
volatile u32 psc6_mccr;
};
/* SDRAM controller */
struct mpc5xxx_sdram {
volatile u32 mode;
volatile u32 ctrl;
volatile u32 config1;
volatile u32 config2;
volatile u32 dummy[32];
volatile u32 sdelay;
};
struct mpc5xxx_lpb {
volatile u32 cs0_cfg;
volatile u32 cs1_cfg;
volatile u32 cs2_cfg;
volatile u32 cs3_cfg;
volatile u32 cs4_cfg;
volatile u32 cs5_cfg;
volatile u32 cs_ctrl;
volatile u32 cs_status;
volatile u32 cs6_cfg;
volatile u32 cs7_cfg;
volatile u32 cs_burst;
volatile u32 cs_deadcycle;
};
struct mpc5xxx_psc {
volatile u8 mode; /* PSC + 0x00 */
volatile u8 reserved0[3];
union { /* PSC + 0x04 */
volatile u16 status;
volatile u16 clock_select;
} sr_csr;
#define psc_status sr_csr.status
#define psc_clock_select sr_csr.clock_select
volatile u16 reserved1;
volatile u8 command; /* PSC + 0x08 */
volatile u8 reserved2[3];
union { /* PSC + 0x0c */
volatile u8 buffer_8;
volatile u16 buffer_16;
volatile u32 buffer_32;
} buffer;
#define psc_buffer_8 buffer.buffer_8
#define psc_buffer_16 buffer.buffer_16
#define psc_buffer_32 buffer.buffer_32
union { /* PSC + 0x10 */
volatile u8 ipcr;
volatile u8 acr;
} ipcr_acr;
#define psc_ipcr ipcr_acr.ipcr
#define psc_acr ipcr_acr.acr
volatile u8 reserved3[3];
union { /* PSC + 0x14 */
volatile u16 isr;
volatile u16 imr;
} isr_imr;
#define psc_isr isr_imr.isr
#define psc_imr isr_imr.imr
volatile u16 reserved4;
volatile u8 ctur; /* PSC + 0x18 */
volatile u8 reserved5[3];
volatile u8 ctlr; /* PSC + 0x1c */
volatile u8 reserved6[3];
volatile u16 ccr; /* PSC + 0x20 */
volatile u8 reserved7[14];
volatile u8 ivr; /* PSC + 0x30 */
volatile u8 reserved8[3];
volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved9[3];
volatile u8 op1; /* PSC + 0x38 */
volatile u8 reserved10[3];
volatile u8 op0; /* PSC + 0x3c */
volatile u8 reserved11[3];
volatile u32 sicr; /* PSC + 0x40 */
volatile u8 ircr1; /* PSC + 0x44 */
volatile u8 reserved12[3];
volatile u8 ircr2; /* PSC + 0x44 */
volatile u8 reserved13[3];
volatile u8 irsdr; /* PSC + 0x4c */
volatile u8 reserved14[3];
volatile u8 irmdr; /* PSC + 0x50 */
volatile u8 reserved15[3];
volatile u8 irfdr; /* PSC + 0x54 */
volatile u8 reserved16[3];
volatile u16 rfnum; /* PSC + 0x58 */
volatile u16 reserved17;
volatile u16 tfnum; /* PSC + 0x5c */
volatile u16 reserved18;
volatile u32 rfdata; /* PSC + 0x60 */
volatile u16 rfstat; /* PSC + 0x64 */
volatile u16 reserved20;
volatile u8 rfcntl; /* PSC + 0x68 */
volatile u8 reserved21[5];
volatile u16 rfalarm; /* PSC + 0x6e */
volatile u16 reserved22;
volatile u16 rfrptr; /* PSC + 0x72 */
volatile u16 reserved23;
volatile u16 rfwptr; /* PSC + 0x76 */
volatile u16 reserved24;
volatile u16 rflrfptr; /* PSC + 0x7a */
volatile u16 reserved25;
volatile u16 rflwfptr; /* PSC + 0x7e */
volatile u32 tfdata; /* PSC + 0x80 */
volatile u16 tfstat; /* PSC + 0x84 */
volatile u16 reserved26;
volatile u8 tfcntl; /* PSC + 0x88 */
volatile u8 reserved27[5];
volatile u16 tfalarm; /* PSC + 0x8e */
volatile u16 reserved28;
volatile u16 tfrptr; /* PSC + 0x92 */
volatile u16 reserved29;
volatile u16 tfwptr; /* PSC + 0x96 */
volatile u16 reserved30;
volatile u16 tflrfptr; /* PSC + 0x9a */
volatile u16 reserved31;
volatile u16 tflwfptr; /* PSC + 0x9e */
};
struct mpc5xxx_intr {
volatile u32 per_mask; /* INTR + 0x00 */
volatile u32 per_pri1; /* INTR + 0x04 */
volatile u32 per_pri2; /* INTR + 0x08 */
volatile u32 per_pri3; /* INTR + 0x0c */
volatile u32 ctrl; /* INTR + 0x10 */
volatile u32 main_mask; /* INTR + 0x14 */
volatile u32 main_pri1; /* INTR + 0x18 */
volatile u32 main_pri2; /* INTR + 0x1c */
volatile u32 reserved1; /* INTR + 0x20 */
volatile u32 enc_status; /* INTR + 0x24 */
volatile u32 crit_status; /* INTR + 0x28 */
volatile u32 main_status; /* INTR + 0x2c */
volatile u32 per_status; /* INTR + 0x30 */
volatile u32 reserved2; /* INTR + 0x34 */
volatile u32 per_error; /* INTR + 0x38 */
};
struct mpc5xxx_gpio {
volatile u32 port_config; /* GPIO + 0x00 */
volatile u32 simple_gpioe; /* GPIO + 0x04 */
volatile u32 simple_ode; /* GPIO + 0x08 */
volatile u32 simple_ddr; /* GPIO + 0x0c */
volatile u32 simple_dvo; /* GPIO + 0x10 */
volatile u32 simple_ival; /* GPIO + 0x14 */
volatile u8 outo_gpioe; /* GPIO + 0x18 */
volatile u8 reserved1[3]; /* GPIO + 0x19 */
volatile u8 outo_dvo; /* GPIO + 0x1c */
volatile u8 reserved2[3]; /* GPIO + 0x1d */
volatile u8 sint_gpioe; /* GPIO + 0x20 */
volatile u8 reserved3[3]; /* GPIO + 0x21 */
volatile u8 sint_ode; /* GPIO + 0x24 */
volatile u8 reserved4[3]; /* GPIO + 0x25 */
volatile u8 sint_ddr; /* GPIO + 0x28 */
volatile u8 reserved5[3]; /* GPIO + 0x29 */
volatile u8 sint_dvo; /* GPIO + 0x2c */
volatile u8 reserved6[3]; /* GPIO + 0x2d */
volatile u8 sint_inten; /* GPIO + 0x30 */
volatile u8 reserved7[3]; /* GPIO + 0x31 */
volatile u16 sint_itype; /* GPIO + 0x34 */
volatile u16 reserved8; /* GPIO + 0x36 */
volatile u8 gpio_control; /* GPIO + 0x38 */
volatile u8 reserved9[3]; /* GPIO + 0x39 */
volatile u8 sint_istat; /* GPIO + 0x3c */
volatile u8 sint_ival; /* GPIO + 0x3d */
volatile u8 bus_errs; /* GPIO + 0x3e */
volatile u8 reserved10; /* GPIO + 0x3f */
};
struct mpc5xxx_wu_gpio {
volatile u8 enable; /* WU_GPIO + 0x00 */
volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */
volatile u8 ode; /* WU_GPIO + 0x04 */
volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */
volatile u8 ddr; /* WU_GPIO + 0x08 */
volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */
volatile u8 dvo; /* WU_GPIO + 0x0c */
volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */
volatile u8 inten; /* WU_GPIO + 0x10 */
volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */
volatile u8 iinten; /* WU_GPIO + 0x14 */
volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */
volatile u16 itype; /* WU_GPIO + 0x18 */
volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */
volatile u8 master_enable; /* WU_GPIO + 0x1c */
volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */
volatile u8 ival; /* WU_GPIO + 0x20 */
volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */
volatile u8 status; /* WU_GPIO + 0x24 */
volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */
};
struct mpc5xxx_sdma {
volatile u32 taskBar; /* SDMA + 0x00 */
volatile u32 currentPointer; /* SDMA + 0x04 */
volatile u32 endPointer; /* SDMA + 0x08 */
volatile u32 variablePointer; /* SDMA + 0x0c */
volatile u8 IntVect1; /* SDMA + 0x10 */
volatile u8 IntVect2; /* SDMA + 0x11 */
volatile u16 PtdCntrl; /* SDMA + 0x12 */
volatile u32 IntPend; /* SDMA + 0x14 */
volatile u32 IntMask; /* SDMA + 0x18 */
volatile u16 tcr_0; /* SDMA + 0x1c */
volatile u16 tcr_1; /* SDMA + 0x1e */
volatile u16 tcr_2; /* SDMA + 0x20 */
volatile u16 tcr_3; /* SDMA + 0x22 */
volatile u16 tcr_4; /* SDMA + 0x24 */
volatile u16 tcr_5; /* SDMA + 0x26 */
volatile u16 tcr_6; /* SDMA + 0x28 */
volatile u16 tcr_7; /* SDMA + 0x2a */
volatile u16 tcr_8; /* SDMA + 0x2c */
volatile u16 tcr_9; /* SDMA + 0x2e */
volatile u16 tcr_a; /* SDMA + 0x30 */
volatile u16 tcr_b; /* SDMA + 0x32 */
volatile u16 tcr_c; /* SDMA + 0x34 */
volatile u16 tcr_d; /* SDMA + 0x36 */
volatile u16 tcr_e; /* SDMA + 0x38 */
volatile u16 tcr_f; /* SDMA + 0x3a */
volatile u8 IPR0; /* SDMA + 0x3c */
volatile u8 IPR1; /* SDMA + 0x3d */
volatile u8 IPR2; /* SDMA + 0x3e */
volatile u8 IPR3; /* SDMA + 0x3f */
volatile u8 IPR4; /* SDMA + 0x40 */
volatile u8 IPR5; /* SDMA + 0x41 */
volatile u8 IPR6; /* SDMA + 0x42 */
volatile u8 IPR7; /* SDMA + 0x43 */
volatile u8 IPR8; /* SDMA + 0x44 */
volatile u8 IPR9; /* SDMA + 0x45 */
volatile u8 IPR10; /* SDMA + 0x46 */
volatile u8 IPR11; /* SDMA + 0x47 */
volatile u8 IPR12; /* SDMA + 0x48 */
volatile u8 IPR13; /* SDMA + 0x49 */
volatile u8 IPR14; /* SDMA + 0x4a */
volatile u8 IPR15; /* SDMA + 0x4b */
volatile u8 IPR16; /* SDMA + 0x4c */
volatile u8 IPR17; /* SDMA + 0x4d */
volatile u8 IPR18; /* SDMA + 0x4e */
volatile u8 IPR19; /* SDMA + 0x4f */
volatile u8 IPR20; /* SDMA + 0x50 */
volatile u8 IPR21; /* SDMA + 0x51 */
volatile u8 IPR22; /* SDMA + 0x52 */
volatile u8 IPR23; /* SDMA + 0x53 */
volatile u8 IPR24; /* SDMA + 0x54 */
volatile u8 IPR25; /* SDMA + 0x55 */
volatile u8 IPR26; /* SDMA + 0x56 */
volatile u8 IPR27; /* SDMA + 0x57 */
volatile u8 IPR28; /* SDMA + 0x58 */
volatile u8 IPR29; /* SDMA + 0x59 */
volatile u8 IPR30; /* SDMA + 0x5a */
volatile u8 IPR31; /* SDMA + 0x5b */
volatile u32 res1; /* SDMA + 0x5c */
volatile u32 res2; /* SDMA + 0x60 */
volatile u32 res3; /* SDMA + 0x64 */
volatile u32 MDEDebug; /* SDMA + 0x68 */
volatile u32 ADSDebug; /* SDMA + 0x6c */
volatile u32 Value1; /* SDMA + 0x70 */
volatile u32 Value2; /* SDMA + 0x74 */
volatile u32 Control; /* SDMA + 0x78 */
volatile u32 Status; /* SDMA + 0x7c */
volatile u32 EU00; /* SDMA + 0x80 */
volatile u32 EU01; /* SDMA + 0x84 */
volatile u32 EU02; /* SDMA + 0x88 */
volatile u32 EU03; /* SDMA + 0x8c */
volatile u32 EU04; /* SDMA + 0x90 */
volatile u32 EU05; /* SDMA + 0x94 */
volatile u32 EU06; /* SDMA + 0x98 */
volatile u32 EU07; /* SDMA + 0x9c */
volatile u32 EU10; /* SDMA + 0xa0 */
volatile u32 EU11; /* SDMA + 0xa4 */
volatile u32 EU12; /* SDMA + 0xa8 */
volatile u32 EU13; /* SDMA + 0xac */
volatile u32 EU14; /* SDMA + 0xb0 */
volatile u32 EU15; /* SDMA + 0xb4 */
volatile u32 EU16; /* SDMA + 0xb8 */
volatile u32 EU17; /* SDMA + 0xbc */
volatile u32 EU20; /* SDMA + 0xc0 */
volatile u32 EU21; /* SDMA + 0xc4 */
volatile u32 EU22; /* SDMA + 0xc8 */
volatile u32 EU23; /* SDMA + 0xcc */
volatile u32 EU24; /* SDMA + 0xd0 */
volatile u32 EU25; /* SDMA + 0xd4 */
volatile u32 EU26; /* SDMA + 0xd8 */
volatile u32 EU27; /* SDMA + 0xdc */
volatile u32 EU30; /* SDMA + 0xe0 */
volatile u32 EU31; /* SDMA + 0xe4 */
volatile u32 EU32; /* SDMA + 0xe8 */
volatile u32 EU33; /* SDMA + 0xec */
volatile u32 EU34; /* SDMA + 0xf0 */
volatile u32 EU35; /* SDMA + 0xf4 */
volatile u32 EU36; /* SDMA + 0xf8 */
volatile u32 EU37; /* SDMA + 0xfc */
};
struct mpc5xxx_i2c {
volatile u32 madr; /* I2Cn + 0x00 */
volatile u32 mfdr; /* I2Cn + 0x04 */
volatile u32 mcr; /* I2Cn + 0x08 */
volatile u32 msr; /* I2Cn + 0x0C */
volatile u32 mdr; /* I2Cn + 0x10 */
};
struct mpc5xxx_spi {
volatile u8 cr1; /* SPI + 0x0F00 */
volatile u8 cr2; /* SPI + 0x0F01 */
volatile u8 reserved1[2];
volatile u8 brr; /* SPI + 0x0F04 */
volatile u8 sr; /* SPI + 0x0F05 */
volatile u8 reserved2[3];
volatile u8 dr; /* SPI + 0x0F09 */
volatile u8 reserved3[3];
volatile u8 pdr; /* SPI + 0x0F0D */
volatile u8 reserved4[2];
volatile u8 ddr; /* SPI + 0x0F10 */
};
struct mpc5xxx_gpt {
volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
};
struct mpc5xxx_gpt_0_7 {
struct mpc5xxx_gpt gpt0;
struct mpc5xxx_gpt gpt1;
struct mpc5xxx_gpt gpt2;
struct mpc5xxx_gpt gpt3;
struct mpc5xxx_gpt gpt4;
struct mpc5xxx_gpt gpt5;
struct mpc5xxx_gpt gpt6;
struct mpc5xxx_gpt gpt7;
};
struct mscan_buffer {
volatile u8 idr[0x8]; /* 0x00 */
volatile u8 dsr[0x10]; /* 0x08 */
volatile u8 dlr; /* 0x18 */
volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
volatile u16 rsrv1; /* 0x1A */
volatile u8 tsrh; /* 0x1C */
volatile u8 tsrl; /* 0x1D */
volatile u16 rsrv2; /* 0x1E */
};
struct mpc5xxx_mscan {
volatile u8 canctl0; /* MSCAN + 0x00 */
volatile u8 canctl1; /* MSCAN + 0x01 */
volatile u16 rsrv1; /* MSCAN + 0x02 */
volatile u8 canbtr0; /* MSCAN + 0x04 */
volatile u8 canbtr1; /* MSCAN + 0x05 */
volatile u16 rsrv2; /* MSCAN + 0x06 */
volatile u8 canrflg; /* MSCAN + 0x08 */
volatile u8 canrier; /* MSCAN + 0x09 */
volatile u16 rsrv3; /* MSCAN + 0x0A */
volatile u8 cantflg; /* MSCAN + 0x0C */
volatile u8 cantier; /* MSCAN + 0x0D */
volatile u16 rsrv4; /* MSCAN + 0x0E */
volatile u8 cantarq; /* MSCAN + 0x10 */
volatile u8 cantaak; /* MSCAN + 0x11 */
volatile u16 rsrv5; /* MSCAN + 0x12 */
volatile u8 cantbsel; /* MSCAN + 0x14 */
volatile u8 canidac; /* MSCAN + 0x15 */
volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
volatile u8 canrxerr; /* MSCAN + 0x1C */
volatile u8 cantxerr; /* MSCAN + 0x1D */
volatile u16 rsrv7; /* MSCAN + 0x1E */
volatile u8 canidar0; /* MSCAN + 0x20 */
volatile u8 canidar1; /* MSCAN + 0x21 */
volatile u16 rsrv8; /* MSCAN + 0x22 */
volatile u8 canidar2; /* MSCAN + 0x24 */
volatile u8 canidar3; /* MSCAN + 0x25 */
volatile u16 rsrv9; /* MSCAN + 0x26 */
volatile u8 canidmr0; /* MSCAN + 0x28 */
volatile u8 canidmr1; /* MSCAN + 0x29 */
volatile u16 rsrv10; /* MSCAN + 0x2A */
volatile u8 canidmr2; /* MSCAN + 0x2C */
volatile u8 canidmr3; /* MSCAN + 0x2D */
volatile u16 rsrv11; /* MSCAN + 0x2E */
volatile u8 canidar4; /* MSCAN + 0x30 */
volatile u8 canidar5; /* MSCAN + 0x31 */
volatile u16 rsrv12; /* MSCAN + 0x32 */
volatile u8 canidar6; /* MSCAN + 0x34 */
volatile u8 canidar7; /* MSCAN + 0x35 */
volatile u16 rsrv13; /* MSCAN + 0x36 */
volatile u8 canidmr4; /* MSCAN + 0x38 */
volatile u8 canidmr5; /* MSCAN + 0x39 */
volatile u16 rsrv14; /* MSCAN + 0x3A */
volatile u8 canidmr6; /* MSCAN + 0x3C */
volatile u8 canidmr7; /* MSCAN + 0x3D */
volatile u16 rsrv15; /* MSCAN + 0x3E */
struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
};
struct mpc5xxx_xlb {
volatile u8 reserved[0x40]; /* XLB + 0x00 */
volatile u32 config; /* XLB + 0x40 */
volatile u32 version; /* XLB + 0x44 */
volatile u32 status; /* XLB + 0x48 */
volatile u32 int_enable; /* XLB + 0x4c */
volatile u32 addr_capture; /* XLB + 0x50 */
volatile u32 bus_sig_capture; /* XLB + 0x54 */
volatile u32 addr_timeout; /* XLB + 0x58 */
volatile u32 data_timeout; /* XLB + 0x5c */
volatile u32 bus_act_timeout; /* XLB + 0x60 */
volatile u32 master_pri_enable; /* XLB + 0x64 */
volatile u32 master_priority; /* XLB + 0x68 */
volatile u32 base_address; /* XLB + 0x6c */
volatile u32 snoop_window; /* XLB + 0x70 */
};
/* function prototypes */
void loadtask(int basetask, int tasks);
#endif /* __ASSEMBLY__ */
#endif /* __ASMPPC_MPC5XXX_H */
|
1001-study-uboot
|
include/mpc5xxx.h
|
C
|
gpl3
| 33,337
|
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
* @Author: Markus Pietrek
* @References: [1] NS9750 Hardware Reference, December 2003
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
***********************************************************************/
#ifndef FS_NS9750_SER_H
#define FS_NS9750_SER_H
#define NS9750_SER_MODULE_BASE (0x90200000)
#define get_ser_reg_addr(c) \
((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
#define get_ser_reg_addr_channel(reg,chan) \
get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
/* the register addresses */
#define NS9750_SER_CTRL_A (0x00)
#define NS9750_SER_CTRL_B (0x04)
#define NS9750_SER_STAT_A (0x08)
#define NS9750_SER_BITRATE (0x0C)
#define NS9750_SER_FIFO (0x10)
#define NS9750_SER_RX_BUF_TIMER (0x14)
#define NS9750_SER_RX_CHAR_TIMER (0x18)
#define NS9750_SER_RX_MATCH (0x1C)
#define NS9750_SER_RX_MATCH_MASK (0x20)
#define NS9750_SER_FLOW_CTRL (0x34)
#define NS9750_SER_FLOW_CTRL_FORCE (0x38)
/* register bit fields */
/* control A register */
#define NS9750_SER_CTRL_A_CE (0x80000000)
#define NS9750_SER_CTRL_A_BRK (0x40000000)
#define NS9750_SER_CTRL_A_STICKP (0x20000000)
#define NS9750_SER_CTRL_A_EPS (0x10000000)
#define NS9750_SER_CTRL_A_PE (0x08000000)
#define NS9750_SER_CTRL_A_STOP (0x04000000)
#define NS9750_SER_CTRL_A_WLS_MA (0x03000000)
#define NS9750_SER_CTRL_A_WLS_5 (0x00000000)
#define NS9750_SER_CTRL_A_WLS_6 (0x01000000)
#define NS9750_SER_CTRL_A_WLS_7 (0x02000000)
#define NS9750_SER_CTRL_A_WLS_8 (0x03000000)
#define NS9750_SER_CTRL_A_CTSTX (0x00800000)
#define NS9750_SER_CTRL_A_RTSRX (0x00400000)
#define NS9750_SER_CTRL_A_RL (0x00200000)
#define NS9750_SER_CTRL_A_LL (0x00100000)
#define NS9750_SER_CTRL_A_RES (0x000CF000)
#define NS9750_SER_CTRL_A_DTR (0x00020000)
#define NS9750_SER_CTRL_A_RTS (0x00010000)
#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00)
#define NS9750_SER_CTRL_A_ERXDMA (0x00000100)
#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0)
#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E)
#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
/* control B register */
#define NS9750_SER_CTRL_B_RDM1 (0x80000000)
#define NS9750_SER_CTRL_B_RDM2 (0x40000000)
#define NS9750_SER_CTRL_B_RDM3 (0x20000000)
#define NS9750_SER_CTRL_B_RDM4 (0x10000000)
#define NS9750_SER_CTRL_B_RBGT (0x08000000)
#define NS9750_SER_CTRL_B_RCGT (0x04000000)
#define NS9750_SER_CTRL_B_MODE_MA (0x00300000)
#define NS9750_SER_CTRL_B_MODE_UART (0x00000000)
#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000)
#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000)
#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000)
#define NS9750_SER_CTRL_B_BITORDR (0x00080000)
#define NS9750_SER_CTRL_B_RES (0x0007703F)
#define NS9750_SER_CTRL_B_RTSTX (0x00008000)
#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0)
/* status A register */
#define NS9750_SER_STAT_A_MATCH1 (0x80000000)
#define NS9750_SER_STAT_A_MATCH2 (0x40000000)
#define NS9750_SER_STAT_A_MATCH3 (0x20000000)
#define NS9750_SER_STAT_A_MATCH4 (0x10000000)
#define NS9750_SER_STAT_A_BGAP (0x08000000)
#define NS9750_SER_STAT_A_CGAP (0x04000000)
#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000)
#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000)
#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000)
#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000)
#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000)
#define NS9750_SER_STAT_A_DCD (0x00080000)
#define NS9750_SER_STAT_A_RI (0x00040000)
#define NS9750_SER_STAT_A_DSR (0x00020000)
#define NS9750_SER_STAT_A_CTS (0x00010000)
#define NS9750_SER_STAT_A_RBRK (0x00008000)
#define NS9750_SER_STAT_A_RFE (0x00004000)
#define NS9750_SER_STAT_A_RPE (0x00002000)
#define NS9750_SER_STAT_A_ROVER (0x00001000)
#define NS9750_SER_STAT_A_RRDY (0x00000800)
#define NS9750_SER_STAT_A_RHALF (0x00000400)
#define NS9750_SER_STAT_A_RBC (0x00000200)
#define NS9750_SER_STAT_A_RFULL (0x00000100)
#define NS9750_SER_STAT_A_DCDI (0x00000080)
#define NS9750_SER_STAT_A_RII (0x00000040)
#define NS9750_SER_STAT_A_DSRI (0x00000020)
#define NS9750_SER_STAT_A_CTSI (0x00000010)
#define NS9750_SER_STAT_A_TRDY (0x00000008)
#define NS9750_SER_STAT_A_THALF (0x00000004)
#define NS9750_SER_STAT_A_TBC (0x00000002)
#define NS9750_SER_STAT_A_TEMPTY (0x00000001)
#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
NS9750_SER_STAT_A_ROVER | \
NS9750_SER_STAT_A_RPE )
#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
NS9750_SER_STAT_A_RBRK | \
NS9750_SER_STAT_A_RRDY | \
NS9750_SER_STAT_A_RHALF | \
NS9750_SER_STAT_A_RBC | \
NS9750_SER_STAT_A_DCDI | \
NS9750_SER_STAT_A_RII | \
NS9750_SER_STAT_A_DSRI | \
NS9750_SER_STAT_A_CTSI )
#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
NS9750_SER_STAT_A_THALF | \
NS9750_SER_STAT_A_TBC | \
NS9750_SER_STAT_A_TEMPTY )
/* bit rate register */
#define NS9750_SER_BITRATE_EBIT (0x80000000)
#define NS9750_SER_BITRATE_TMODE (0x40000000)
#define NS9750_SER_BITRATE_RXSRC (0x20000000)
#define NS9750_SER_BITRATE_TXSRC (0x10000000)
#define NS9750_SER_BITRATE_RXEXT (0x08000000)
#define NS9750_SER_BITRATE_TXEXT (0x04000000)
#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000)
#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000)
#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000)
#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000)
#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000)
#define NS9750_SER_BITRATE_TXCINV (0x00800000)
#define NS9750_SER_BITRATE_RXCINV (0x00400000)
#define NS9750_SER_BITRATE_TCDR_MA (0x00180000)
#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
#define NS9750_SER_BITRATE_TCDR_16 (0x00100000)
#define NS9750_SER_BITRATE_TCDR_32 (0x00180000)
#define NS9750_SER_BITRATE_RCDR_MA (0x00070000)
#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
#define NS9750_SER_BITRATE_RCDR_16 (0x00040000)
#define NS9750_SER_BITRATE_RCDR_32 (0x00060000)
#define NS9750_SER_BITRATE_TICS (0x00010000)
#define NS9750_SER_BITRATE_RICS (0x00008000)
#define NS9750_SER_BITRATE_N_MA (0x00007FFF)
/* receive buffer gap timer */
#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */
#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */
#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
/* receive character gap timer */
#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000)
#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF)
/* receive match */
#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000)
#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000)
#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00)
#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF)
/* receive match mask */
#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
#endif /* FS_NS9750_SER_H */
|
1001-study-uboot
|
include/ns9750_ser.h
|
C
|
gpl3
| 7,939
|
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* winbond access routines and defines*/
/* from the winbond data sheet -
The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
*/
/*ISA bridge configuration space*/
#define W83C553F_VID 0x10AD
#define W83C553F_DID 0x0565
#define WINBOND_PCICONTR 0x40 /*pci control reg*/
#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
#define WINBOND_ATSCR 0x4e /*AT System Control register*/
#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
#define IPADCR_MBE512 0x1
#define IPADCR_MBE640 0x2
#define IPADCR_IPATOM4 0x10
#define IPADCR_IPATOM5 0x20
#define IPADCR_IPATOM6 0x40
#define IPADCR_IPATOM7 0x80
#define CSCR_UBIOSCSE 0x10
#define CSCR_BIOSWP 0x20
#define IDECSR_P0EN 0x01
#define IDECSR_P0F16 0x02
#define IDECSR_P1EN 0x10
#define IDECSR_P1F16 0x20
#define IDECSR_LEGIRQ 0x800
/*
* Interrupt controller
*/
#define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20
#define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21
#define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21
#define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21
#define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21
#define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20
#define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20
#define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0
#define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0
#define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1
#define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1
#define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1
#define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1
#define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0
#define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0
#define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1
#define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43
/*
* DMA controller
*/
#define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
#define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
/* command/status register bit definitions */
#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
/* mode register bit definitions */
#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
/* request register bit definitions */
#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
/* write single mask bit register bit definitions */
#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
/* read/write all mask bits register bit definitions */
#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
/* typedefs */
#define W83C553F_DMA1_CS 0x8
#define W83C553F_DMA1_WR 0x9
#define W83C553F_DMA1_WSMB 0xA
#define W83C553F_DMA1_WM 0xB
#define W83C553F_DMA1_CBP 0xC
#define W83C553F_DMA1_MC 0xD
#define W83C553F_DMA1_CM 0xE
#define W83C553F_DMA1_RWAMB 0xF
#define W83C553F_DMA2_CS 0x10
#define W83C553F_DMA2_WR 0x12
#define W83C553F_DMA2_WSMB 0x14
#define W83C553F_DMA2_WM 0x16
#define W83C553F_DMA2_CBP 0x18
#define W83C553F_DMA2_MC 0x1A
#define W83C553F_DMA2_CM 0x1C
#define W83C553F_DMA2_RWAMB 0x1E
void initialise_w83c553f(void);
|
1001-study-uboot
|
include/w83c553f.h
|
C
|
gpl3
| 7,355
|
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Michael Zaidman, Kodak, michael.zaidman@kodak.com
* post_word_{load|store} cleanup.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _POST_H
#define _POST_H
#ifndef __ASSEMBLY__
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS
#ifdef CONFIG_SYS_POST_WORD_ADDR
#define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR
#else
#ifdef CONFIG_MPC5xxx
#define _POST_WORD_ADDR (MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE)
#elif defined(CONFIG_MPC512X)
#define _POST_WORD_ADDR \
(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#elif defined(CONFIG_8xx)
#define _POST_WORD_ADDR \
(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR)
#elif defined(CONFIG_MPC8260)
#include <asm/cpm_8260.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#elif defined(CONFIG_MPC8360)
#include <asm/immap_qe.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#elif defined (CONFIG_MPC85xx)
#include <asm/immap_85xx.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_MPC86xx)
#include <asm/immap_86xx.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_4xx)
#define _POST_WORD_ADDR \
(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#endif
#ifndef _POST_WORD_ADDR
#error "_POST_WORD_ADDR currently not implemented for this platform!"
#endif
#endif /* CONFIG_SYS_POST_WORD_ADDR */
static inline ulong post_word_load (void)
{
return in_le32((volatile void *)(_POST_WORD_ADDR));
}
static inline void post_word_store (ulong value)
{
out_le32((volatile void *)(_POST_WORD_ADDR), value);
}
#else
extern ulong post_word_load(void);
extern void post_word_store(ulong value);
#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */
#endif /* defined (CONFIG_POST) || defined(CONFIG_LOGBUFFER) */
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_POST
#define POST_POWERON 0x01 /* test runs on power-on booting */
#define POST_NORMAL 0x02 /* test runs on normal booting */
#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
#define POST_COLDBOOT 0x80 /* first boot after power-on */
#define POST_ROM 0x0100 /* test runs in ROM */
#define POST_RAM 0x0200 /* test runs in RAM */
#define POST_MANUAL 0x0400 /* test runs on diag command */
#define POST_REBOOT 0x0800 /* test may cause rebooting */
#define POST_PREREL 0x1000 /* test runs before relocation */
#define POST_CRITICAL 0x2000 /* Use failbootcmd if test failed */
#define POST_STOP 0x4000 /* Interrupt POST sequence on fail */
#define POST_MEM (POST_RAM | POST_ROM)
#define POST_ALWAYS (POST_NORMAL | \
POST_SLOWTEST | \
POST_MANUAL | \
POST_POWERON )
#define POST_FAIL_SAVE 0x80
#define POST_BEFORE 1
#define POST_AFTER 0
#define POST_PASSED 1
#define POST_FAILED 0
#ifndef __ASSEMBLY__
struct post_test {
char *name;
char *cmd;
char *desc;
int flags;
int (*test) (int flags);
int (*init_f) (void);
void (*reloc) (void);
unsigned long testid;
};
int post_init_f (void);
void post_bootmode_init (void);
int post_bootmode_get (unsigned int * last_test);
void post_bootmode_clear (void);
void post_output_backlog ( void );
int post_run (char *name, int flags);
int post_info (char *name);
int post_log (char *format, ...);
#ifdef CONFIG_NEEDS_MANUAL_RELOC
void post_reloc (void);
#endif
unsigned long post_time_ms (unsigned long base);
extern struct post_test post_list[];
extern unsigned int post_list_size;
extern int post_hotkeys_pressed(void);
extern int memory_post_test(int flags);
/*
* If GCC is configured to use a version of GAS that supports
* the .gnu_attribute directive, it will use that directive to
* record certain properties of the output code.
* This feature is new to GCC 4.3.0.
* .gnu_attribute is new to GAS 2.18.
*/
#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3)
/* Tag_GNU_Power_ABI_FP/soft-float */
#define GNU_FPOST_ATTR asm(".gnu_attribute 4, 2");
#else
#define GNU_FPOST_ATTR
#endif /* __GNUC__ */
#endif /* __ASSEMBLY__ */
#define CONFIG_SYS_POST_RTC 0x00000001
#define CONFIG_SYS_POST_WATCHDOG 0x00000002
#define CONFIG_SYS_POST_MEMORY 0x00000004
#define CONFIG_SYS_POST_CPU 0x00000008
#define CONFIG_SYS_POST_I2C 0x00000010
#define CONFIG_SYS_POST_CACHE 0x00000020
#define CONFIG_SYS_POST_UART 0x00000040
#define CONFIG_SYS_POST_ETHER 0x00000080
#define CONFIG_SYS_POST_SPI 0x00000100
#define CONFIG_SYS_POST_USB 0x00000200
#define CONFIG_SYS_POST_SPR 0x00000400
#define CONFIG_SYS_POST_SYSMON 0x00000800
#define CONFIG_SYS_POST_DSP 0x00001000
#define CONFIG_SYS_POST_OCM 0x00002000
#define CONFIG_SYS_POST_FPU 0x00004000
#define CONFIG_SYS_POST_ECC 0x00008000
#define CONFIG_SYS_POST_BSPEC1 0x00010000
#define CONFIG_SYS_POST_BSPEC2 0x00020000
#define CONFIG_SYS_POST_BSPEC3 0x00040000
#define CONFIG_SYS_POST_BSPEC4 0x00080000
#define CONFIG_SYS_POST_BSPEC5 0x00100000
#define CONFIG_SYS_POST_CODEC 0x00200000
#define CONFIG_SYS_POST_COPROC 0x00400000
#define CONFIG_SYS_POST_FLASH 0x00800000
#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000
#endif /* CONFIG_POST */
#endif /* _POST_H */
|
1001-study-uboot
|
include/post.h
|
C
|
gpl3
| 6,179
|
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _PART_H
#define _PART_H
#include <ide.h>
typedef struct block_dev_desc {
int if_type; /* type of the interface */
int dev; /* device number */
unsigned char part_type; /* partition type */
unsigned char target; /* target SCSI ID */
unsigned char lun; /* target LUN */
unsigned char type; /* device type */
unsigned char removable; /* removable device */
#ifdef CONFIG_LBA48
unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */
#endif
lbaint_t lba; /* number of blocks */
unsigned long blksz; /* block size */
char vendor [40+1]; /* IDE model, SCSI Vendor */
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
unsigned long (*block_read)(int dev,
unsigned long start,
lbaint_t blkcnt,
void *buffer);
unsigned long (*block_write)(int dev,
unsigned long start,
lbaint_t blkcnt,
const void *buffer);
unsigned long (*block_erase)(int dev,
unsigned long start,
lbaint_t blkcnt);
void *priv; /* driver private struct pointer */
}block_dev_desc_t;
/* Interface types: */
#define IF_TYPE_UNKNOWN 0
#define IF_TYPE_IDE 1
#define IF_TYPE_SCSI 2
#define IF_TYPE_ATAPI 3
#define IF_TYPE_USB 4
#define IF_TYPE_DOC 5
#define IF_TYPE_MMC 6
#define IF_TYPE_SD 7
#define IF_TYPE_SATA 8
/* Part types */
#define PART_TYPE_UNKNOWN 0x00
#define PART_TYPE_MAC 0x01
#define PART_TYPE_DOS 0x02
#define PART_TYPE_ISO 0x03
#define PART_TYPE_AMIGA 0x04
#define PART_TYPE_EFI 0x05
/*
* Type string for U-Boot bootable partitions
*/
#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */
#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */
/* device types */
#define DEV_TYPE_UNKNOWN 0xff /* not connected */
#define DEV_TYPE_HARDDISK 0x00 /* harddisk */
#define DEV_TYPE_TAPE 0x01 /* Tape */
#define DEV_TYPE_CDROM 0x05 /* CD-ROM */
#define DEV_TYPE_OPDISK 0x07 /* optical disk */
typedef struct disk_partition {
ulong start; /* # of first block in partition */
ulong size; /* number of blocks in partition */
ulong blksz; /* block size in bytes */
uchar name[32]; /* partition name */
uchar type[32]; /* string type description */
} disk_partition_t;
/* Misc _get_dev functions */
#ifdef CONFIG_PARTITIONS
block_dev_desc_t* get_dev(char* ifname, int dev);
block_dev_desc_t* ide_get_dev(int dev);
block_dev_desc_t* sata_get_dev(int dev);
block_dev_desc_t* scsi_get_dev(int dev);
block_dev_desc_t* usb_stor_get_dev(int dev);
block_dev_desc_t* mmc_get_dev(int dev);
block_dev_desc_t* systemace_get_dev(int dev);
block_dev_desc_t* mg_disk_get_dev(int dev);
/* disk/part.c */
int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part (block_dev_desc_t *dev_desc);
void init_part (block_dev_desc_t *dev_desc);
void dev_print(block_dev_desc_t *dev_desc);
#else
static inline block_dev_desc_t* get_dev(char* ifname, int dev) { return NULL; }
static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
static inline int get_partition_info (block_dev_desc_t * dev_desc, int part,
disk_partition_t *info) { return -1; }
static inline void print_part (block_dev_desc_t *dev_desc) {}
static inline void init_part (block_dev_desc_t *dev_desc) {}
static inline void dev_print(block_dev_desc_t *dev_desc) {}
#endif
#ifdef CONFIG_MAC_PARTITION
/* disk/part_mac.c */
int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part_mac (block_dev_desc_t *dev_desc);
int test_part_mac (block_dev_desc_t *dev_desc);
#endif
#ifdef CONFIG_DOS_PARTITION
/* disk/part_dos.c */
int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part_dos (block_dev_desc_t *dev_desc);
int test_part_dos (block_dev_desc_t *dev_desc);
#endif
#ifdef CONFIG_ISO_PARTITION
/* disk/part_iso.c */
int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part_iso (block_dev_desc_t *dev_desc);
int test_part_iso (block_dev_desc_t *dev_desc);
#endif
#ifdef CONFIG_AMIGA_PARTITION
/* disk/part_amiga.c */
int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part_amiga (block_dev_desc_t *dev_desc);
int test_part_amiga (block_dev_desc_t *dev_desc);
#endif
#ifdef CONFIG_EFI_PARTITION
/* disk/part_efi.c */
int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
void print_part_efi (block_dev_desc_t *dev_desc);
int test_part_efi (block_dev_desc_t *dev_desc);
#endif
#endif /* _PART_H */
|
1001-study-uboot
|
include/part.h
|
C
|
gpl3
| 5,993
|
/*
* NOTE: DAVICOM ethernet Physical layer
*
* Version: @(#)DM9161.h 1.0.0 01/10/2001
*
* Authors: ATMEL Rousset
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
#define DM9161_BMCR 0 /* Basic Mode Control Register */
#define DM9161_BMSR 1 /* Basic Mode Status Register */
#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */
#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */
#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */
#define DM9161_DSCR 16 /* Specified Configuration Register */
#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */
#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */
#define DM9161_MDINTR 21 /* Specified Interrupt Register */
#define DM9161_RECR 22 /* Specified Receive Error Counter Register */
#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */
#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */
/* --Bit definitions: DM9161_BMCR */
#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define DM9161_AUTONEG (1 << 12)
#define DM9161_POWER_DOWN (1 << 11)
#define DM9161_ISOLATE (1 << 10)
#define DM9161_RESTART_AUTONEG (1 << 9)
#define DM9161_DUPLEX_MODE (1 << 8)
#define DM9161_COLLISION_TEST (1 << 7)
/*--Bit definitions: DM9161_BMSR */
#define DM9161_100BASE_TX (1 << 15)
#define DM9161_100BASE_TX_FD (1 << 14)
#define DM9161_100BASE_TX_HD (1 << 13)
#define DM9161_10BASE_T_FD (1 << 12)
#define DM9161_10BASE_T_HD (1 << 11)
#define DM9161_MF_PREAMB_SUPPR (1 << 6)
#define DM9161_AUTONEG_COMP (1 << 5)
#define DM9161_REMOTE_FAULT (1 << 4)
#define DM9161_AUTONEG_ABILITY (1 << 3)
#define DM9161_LINK_STATUS (1 << 2)
#define DM9161_JABBER_DETECT (1 << 1)
#define DM9161_EXTEND_CAPAB (1 << 0)
/*--definitions: DM9161_PHYID1 */
#define DM9161_PHYID1_OUI 0x606E
#define DM9161_LSB_MASK 0x3F
/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
#define DM9161_NP (1 << 15)
#define DM9161_ACK (1 << 14)
#define DM9161_RF (1 << 13)
#define DM9161_FCS (1 << 10)
#define DM9161_T4 (1 << 9)
#define DM9161_TX_FDX (1 << 8)
#define DM9161_TX_HDX (1 << 7)
#define DM9161_10_FDX (1 << 6)
#define DM9161_10_HDX (1 << 5)
#define DM9161_AN_IEEE_802_3 0x0001
/*--Bit definitions: DM9161_ANER */
#define DM9161_PDF (1 << 4)
#define DM9161_LP_NP_ABLE (1 << 3)
#define DM9161_NP_ABLE (1 << 2)
#define DM9161_PAGE_RX (1 << 1)
#define DM9161_LP_AN_ABLE (1 << 0)
/*--Bit definitions: DM9161_DSCR */
#define DM9161_BP4B5B (1 << 15)
#define DM9161_BP_SCR (1 << 14)
#define DM9161_BP_ALIGN (1 << 13)
#define DM9161_BP_ADPOK (1 << 12)
#define DM9161_REPEATER (1 << 11)
#define DM9161_TX (1 << 10)
#define DM9161_RMII_ENABLE (1 << 8)
#define DM9161_F_LINK_100 (1 << 7)
#define DM9161_SPLED_CTL (1 << 6)
#define DM9161_COLLED_CTL (1 << 5)
#define DM9161_RPDCTR_EN (1 << 4)
#define DM9161_SM_RST (1 << 3)
#define DM9161_MFP SC (1 << 2)
#define DM9161_SLEEP (1 << 1)
#define DM9161_RLOUT (1 << 0)
/*--Bit definitions: DM9161_DSCSR */
#define DM9161_100FDX (1 << 15)
#define DM9161_100HDX (1 << 14)
#define DM9161_10FDX (1 << 13)
#define DM9161_10HDX (1 << 12)
/*--Bit definitions: DM9161_10BTCSR */
#define DM9161_LP_EN (1 << 14)
#define DM9161_HBE (1 << 13)
#define DM9161_SQUELCH (1 << 12)
#define DM9161_JABEN (1 << 11)
#define DM9161_10BT_SER (1 << 10)
#define DM9161_POLR (1 << 0)
/*--Bit definitions: DM9161_MDINTR */
#define DM9161_INTR_PEND (1 << 15)
#define DM9161_FDX_MASK (1 << 11)
#define DM9161_SPD_MASK (1 << 10)
#define DM9161_LINK_MASK (1 << 9)
#define DM9161_INTR_MASK (1 << 8)
#define DM9161_FDX_CHANGE (1 << 4)
#define DM9161_SPD_CHANGE (1 << 3)
#define DM9161_LINK_CHANGE (1 << 2)
#define DM9161_INTR_STATUS (1 << 0)
/****************** function prototypes **********************/
unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
|
1001-study-uboot
|
include/dm9161.h
|
C
|
gpl3
| 5,092
|
/*
* (C) Copyright 2008
* Benjamin Warren, biggerbadderben@gmail.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* netdev.h - definitions an prototypes for network devices
*/
#ifndef _NETDEV_H_
#define _NETDEV_H_
/*
* Board and CPU-specific initialization functions
* board_eth_init() has highest priority. cpu_eth_init() only
* gets called if board_eth_init() isn't instantiated or fails.
* Return values:
* 0: success
* -1: failure
*/
int board_eth_init(bd_t *bis);
int cpu_eth_init(bd_t *bis);
/* Driver initialization prototypes */
int altera_tse_initialize(u8 dev_num, int mac_base,
int sgdma_rx_base, int sgdma_tx_base,
u32 sgdma_desc_base, u32 sgdma_desc_size);
int at91emac_register(bd_t *bis, unsigned long iobase);
int au1x00_enet_initialize(bd_t*);
int ax88180_initialize(bd_t *bis);
int bfin_EMAC_initialize(bd_t *bis);
int cs8900_initialize(u8 dev_num, int base_addr);
int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
int dm9000_initialize(bd_t *bis);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
int enc28j60_initialize(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode);
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
int eth_3com_initialize (bd_t * bis);
int ethoc_initialize(u8 dev_num, int base_addr);
int fec_initialize (bd_t *bis);
int fecmxc_initialize(bd_t *bis);
int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
int ftgmac100_initialize(bd_t *bits);
int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
int ks8695_eth_initialize(void);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
int mcffec_initialize(bd_t *bis);
int mpc512x_fec_initialize(bd_t *bis);
int mpc5xxx_fec_initialize(bd_t *bis);
int mpc8220_fec_initialize(bd_t *bis);
int mpc82xx_scc_enet_initialize(bd_t *bis);
int mvgbe_initialize(bd_t *bis);
int natsemi_initialize(bd_t *bis);
int ne2k_register(void);
int npe_initialize(bd_t *bis);
int ns8382x_initialize(bd_t *bis);
int pcnet_initialize(bd_t *bis);
int plb2800_eth_initialize(bd_t *bis);
int ppc_4xx_eth_initialize (bd_t *bis);
int rtl8139_initialize(bd_t *bis);
int rtl8169_initialize(bd_t *bis);
int scc_initialize(bd_t *bis);
int sh_eth_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
int armada100_fec_register(unsigned long base_addr);
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr);
int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp);
/* Boards with PCI network controllers can call this from their board_eth_init()
* function to initialize whatever's on board.
* Return value is total # of devices found */
static inline int pci_eth_init(bd_t *bis)
{
int num = 0;
#ifdef CONFIG_PCI
#ifdef CONFIG_EEPRO100
num += eepro100_initialize(bis);
#endif
#ifdef CONFIG_TULIP
num += dc21x4x_initialize(bis);
#endif
#ifdef CONFIG_E1000
num += e1000_initialize(bis);
#endif
#ifdef CONFIG_PCNET
num += pcnet_initialize(bis);
#endif
#ifdef CONFIG_NATSEMI
num += natsemi_initialize(bis);
#endif
#ifdef CONFIG_NS8382X
num += ns8382x_initialize(bis);
#endif
#if defined(CONFIG_RTL8139)
num += rtl8139_initialize(bis);
#endif
#if defined(CONFIG_RTL8169)
num += rtl8169_initialize(bis);
#endif
#if defined(CONFIG_ULI526X)
num += uli526x_initialize(bis);
#endif
#endif /* CONFIG_PCI */
return num;
}
/*
* Boards with mv88e61xx switch can use this by defining
* CONFIG_MV88E61XX_SWITCH in respective board configheader file
* the stuct and enums here are used to specify switch configuration params
*/
#if defined(CONFIG_MV88E61XX_SWITCH)
enum mv88e61xx_cfg_vlan {
MV88E61XX_VLANCFG_DEFAULT,
MV88E61XX_VLANCFG_ROUTER
};
enum mv88e61xx_cfg_mdip {
MV88E61XX_MDIP_NOCHANGE,
MV88E61XX_MDIP_REVERSE
};
enum mv88e61xx_cfg_ledinit {
MV88E61XX_LED_INIT_DIS,
MV88E61XX_LED_INIT_EN
};
enum mv88e61xx_cfg_rgmiid {
MV88E61XX_RGMII_DELAY_DIS,
MV88E61XX_RGMII_DELAY_EN
};
enum mv88e61xx_cfg_prtstt {
MV88E61XX_PORTSTT_DISABLED,
MV88E61XX_PORTSTT_BLOCKING,
MV88E61XX_PORTSTT_LEARNING,
MV88E61XX_PORTSTT_FORWARDING
};
struct mv88e61xx_config {
char *name;
enum mv88e61xx_cfg_vlan vlancfg;
enum mv88e61xx_cfg_rgmiid rgmii_delay;
enum mv88e61xx_cfg_prtstt portstate;
enum mv88e61xx_cfg_ledinit led_init;
enum mv88e61xx_cfg_mdip mdip;
u32 ports_enabled;
u8 cpuport;
};
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
#endif /* CONFIG_MV88E61XX_SWITCH */
/*
* Allow FEC to fine-tune MII configuration on boards which require this.
*/
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
#endif /* _NETDEV_H_ */
|
1001-study-uboot
|
include/netdev.h
|
C
|
gpl3
| 5,965
|
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2000, 2001 Free Software Foundation, Inc.
*
* (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
* Pavel Bartusek <pba@sysgo.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* An implementation for the Ext2FS filesystem ported from GRUB.
* Some parts of this code (mainly the structures and defines) are
* from the original ext2 fs code, as found in the linux kernel.
*/
#define SECTOR_SIZE 0x200
#define SECTOR_BITS 9
/* Error codes */
typedef enum
{
ERR_NONE = 0,
ERR_BAD_FILENAME,
ERR_BAD_FILETYPE,
ERR_BAD_GZIP_DATA,
ERR_BAD_GZIP_HEADER,
ERR_BAD_PART_TABLE,
ERR_BAD_VERSION,
ERR_BELOW_1MB,
ERR_BOOT_COMMAND,
ERR_BOOT_FAILURE,
ERR_BOOT_FEATURES,
ERR_DEV_FORMAT,
ERR_DEV_VALUES,
ERR_EXEC_FORMAT,
ERR_FILELENGTH,
ERR_FILE_NOT_FOUND,
ERR_FSYS_CORRUPT,
ERR_FSYS_MOUNT,
ERR_GEOM,
ERR_NEED_LX_KERNEL,
ERR_NEED_MB_KERNEL,
ERR_NO_DISK,
ERR_NO_PART,
ERR_NUMBER_PARSING,
ERR_OUTSIDE_PART,
ERR_READ,
ERR_SYMLINK_LOOP,
ERR_UNRECOGNIZED,
ERR_WONT_FIT,
ERR_WRITE,
ERR_BAD_ARGUMENT,
ERR_UNALIGNED,
ERR_PRIVILEGED,
ERR_DEV_NEED_INIT,
ERR_NO_DISK_SPACE,
ERR_NUMBER_OVERFLOW,
MAX_ERR_NUM
} ext2fs_error_t;
extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part);
extern int ext2fs_ls (const char *dirname);
extern int ext2fs_open (const char *filename);
extern int ext2fs_read (char *buf, unsigned len);
extern int ext2fs_mount (unsigned part_length);
extern int ext2fs_close(void);
|
1001-study-uboot
|
include/ext2fs.h
|
C
|
gpl3
| 2,214
|
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
* @Author: Markus Pietrek
* @Descr: Definitions for Memory Control Module
* @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
***********************************************************************/
#ifndef FS_NS9750_MEM_H
#define FS_NS9750_SYS_H
#define NS9750_MEM_MODULE_BASE (0xA0700000)
#define get_mem_reg_addr(c) \
((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
/* the register addresses */
#define NS9750_MEM_CTRL (0x0000)
#define NS9750_MEM_STATUS (0x0004)
#define NS9750_MEM_CFG (0x0008)
#define NS9750_MEM_DYN_CTRL (0x0020)
#define NS9750_MEM_DYN_REFRESH (0x0024)
#define NS9750_MEM_DYN_READ_CFG (0x0028)
#define NS9750_MEM_DYN_TRP (0x0030)
#define NS9750_MEM_DYN_TRAS (0x0034)
#define NS9750_MEM_DYN_TSREX (0x0038)
#define NS9750_MEM_DYN_TAPR (0x003C)
#define NS9750_MEM_DYN_TDAL (0x0040)
#define NS9750_MEM_DYN_TWR (0x0044)
#define NS9750_MEM_DYN_TRC (0x0048)
#define NS9750_MEM_DYN_TRFC (0x004C)
#define NS9750_MEM_DYN_TXSR (0x0050)
#define NS9750_MEM_DYN_TRRD (0x0054)
#define NS9750_MEM_DYN_TMRD (0x0058)
#define NS9750_MEM_STAT_EXT_WAIT (0x0080)
#define NS9750_MEM_DYN_CFG_BASE (0x0100)
#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104)
#define NS9750_MEM_STAT_CFG_BASE (0x0200)
#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204)
#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208)
#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C)
#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210)
#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214)
#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218)
/* the vectored register addresses */
#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
/* register bit fields */
#define NS9750_MEM_CTRL_L (0x00000004)
#define NS9750_MEM_CTRL_M (0x00000002)
#define NS9750_MEM_CTRL_E (0x00000001)
#define NS9750_MEM_STAT_SA (0x00000004)
#define NS9750_MEM_STAT_S (0x00000002)
#define NS9750_MEM_STAT_B (0x00000001)
#define NS9750_MEM_CFG_CLK (0x00000010)
#define NS9750_MEM_CFG_N (0x00000001)
#define NS9750_MEM_DYN_CTRL_NRP (0x00004000)
#define NS9750_MEM_DYN_CTRL_DP (0x00002000)
#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180)
#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000)
#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080)
#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100)
#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180)
#define NS9750_MEM_DYN_CTRL_SR (0x00000002)
#define NS9750_MEM_DYN_CTRL_CE (0x00000001)
#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF)
#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003)
#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002)
#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003)
#define NS9750_MEM_DYN_TRP_MA (0x0000000F)
#define NS9750_MEM_DYN_TRAS_MA (0x0000000F)
#define NS9750_MEM_DYN_TSREX_MA (0x0000000F)
#define NS9750_MEM_DYN_TAPR_MA (0x0000000F)
#define NS9750_MEM_DYN_TDAL_MA (0x0000000F)
#define NS9750_MEM_DYN_TWR_MA (0x0000000F)
#define NS9750_MEM_DYN_TRC_MA (0x0000001F)
#define NS9750_MEM_DYN_TRFC_MA (0x0000001F)
#define NS9750_MEM_DYN_TXSR_MA (0x0000001F)
#define NS9750_MEM_DYN_TRRD_MA (0x0000000F)
#define NS9750_MEM_DYN_TMRD_MA (0x0000000F)
#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F)
#define NS9750_MEM_DYN_CFG_P (0x00100000)
#define NS9750_MEM_DYN_CFG_BDMC (0x00080000)
#define NS9750_MEM_DYN_CFG_AM (0x00004000)
#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80)
#define NS9750_MEM_DYN_CFG_MD (0x00000018)
#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300)
#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100)
#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200)
#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300)
#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003)
#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001)
#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002)
#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003)
#define NS9750_MEM_STAT_CFG_PSMC (0x00100000)
#define NS9750_MEM_STAT_CFG_BSMC (0x00080000)
#define NS9750_MEM_STAT_CFG_EW (0x00000100)
#define NS9750_MEM_STAT_CFG_PB (0x00000080)
#define NS9750_MEM_STAT_CFG_PC (0x00000040)
#define NS9750_MEM_STAT_CFG_PM (0x00000008)
#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003)
#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000)
#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001)
#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002)
#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F)
#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F)
#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F)
#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F)
#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F)
#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F)
#endif /* FS_NS9750_MEM_H */
|
1001-study-uboot
|
include/ns9750_mem.h
|
C
|
gpl3
| 6,181
|
#ifndef _MPC8XX_IRQ_H
#define _MPC8XX_IRQ_H
/* The MPC8xx cores have 16 possible interrupts. There are eight
* possible level sensitive interrupts assigned and generated internally
* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
* There are eight external interrupts (IRQs) that can be configured
* as either level or edge sensitive.
*
* On some implementations, there is also the possibility of an 8259
* through the PCI and PCI-ISA bridges.
*
* We don't support the 8259 (yet).
*/
#define NR_SIU_INTS 16
#define NR_8259_INTS 0
#define NR_IRQS (NR_SIU_INTS + NR_8259_INTS)
/* These values must be zero-based and map 1:1 with the SIU configuration.
* They are used throughout the 8xx I/O subsystem to generate
* interrupt masks, flags, and other control patterns. This is why the
* current kernel assumption of the 8259 as the base controller is such
* a pain in the butt.
*/
#define SIU_IRQ0 (0) /* Highest priority */
#define SIU_LEVEL0 (1)
#define SIU_IRQ1 (2)
#define SIU_LEVEL1 (3)
#define SIU_IRQ2 (4)
#define SIU_LEVEL2 (5)
#define SIU_IRQ3 (6)
#define SIU_LEVEL3 (7)
#define SIU_IRQ4 (8)
#define SIU_LEVEL4 (9)
#define SIU_IRQ5 (10)
#define SIU_LEVEL5 (11)
#define SIU_IRQ6 (12)
#define SIU_LEVEL6 (13)
#define SIU_IRQ7 (14)
#define SIU_LEVEL7 (15)
/* The internal interrupts we can configure as we see fit.
* My personal preference is CPM at level 2, which puts it above the
* MBX PCI/ISA/IDE interrupts.
*/
#ifdef CONFIG_SYS_CPM_INTERRUPT
# define CPM_INTERRUPT CONFIG_SYS_CPM_INTERRUPT
#else
# define CPM_INTERRUPT SIU_LEVEL2
#endif
/* Some internal interrupt registers use an 8-bit mask for the interrupt
* level instead of a number.
*/
#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
#endif /* _MPC8XX_IRQ_H */
|
1001-study-uboot
|
include/mpc8xx_irq.h
|
C
|
gpl3
| 1,779
|
/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _STDIO_DEV_H_
#define _STDIO_DEV_H_
#include <linux/list.h>
/*
* STDIO DEVICES
*/
#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */
#define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */
#define DEV_FLAGS_SYSTEM 0x80000000 /* Device is a system device */
#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */
/* Device information */
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
char name[16]; /* Device name */
/* GENERAL functions */
int (*start) (void); /* To start the device */
int (*stop) (void); /* To stop the device */
/* OUTPUT functions */
void (*putc) (const char c); /* To put a char */
void (*puts) (const char *s); /* To put a string (accelerator) */
/* INPUT functions */
int (*tstc) (void); /* To test if a char is ready... */
int (*getc) (void); /* To get that char */
/* Other functions */
void *priv; /* Private extensions */
struct list_head list;
};
/*
* VIDEO EXTENSIONS
*/
#define VIDEO_FORMAT_RGB_INDEXED 0x0000
#define VIDEO_FORMAT_RGB_DIRECTCOLOR 0x0001
#define VIDEO_FORMAT_YUYV_4_4_4 0x0010
#define VIDEO_FORMAT_YUYV_4_2_2 0x0011
typedef struct {
void *address; /* Address of framebuffer */
ushort width; /* Horizontal resolution */
ushort height; /* Vertical resolution */
uchar format; /* Format */
uchar colors; /* Colors number or color depth */
void (*setcolreg) (int, int, int, int);
void (*getcolreg) (int, void *);
} video_ext_t;
/*
* VARIABLES
*/
extern struct stdio_dev *stdio_devices[];
extern char *stdio_names[MAX_FILES];
/*
* PROTOTYPES
*/
int stdio_register (struct stdio_dev * dev);
int stdio_init (void);
void stdio_print_current_devices(void);
#ifdef CONFIG_SYS_STDIO_DEREGISTER
int stdio_deregister(const char *devname);
#endif
struct list_head* stdio_get_list(void);
struct stdio_dev* stdio_get_by_name(const char* name);
struct stdio_dev* stdio_clone(struct stdio_dev *dev);
#ifdef CONFIG_ARM_DCC_MULTI
int drv_arm_dcc_init(void);
#endif
#ifdef CONFIG_LCD
int drv_lcd_init (void);
#endif
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
int drv_video_init (void);
#endif
#ifdef CONFIG_KEYBOARD
int drv_keyboard_init (void);
#endif
#ifdef CONFIG_USB_TTY
int drv_usbtty_init (void);
#endif
#ifdef CONFIG_NETCONSOLE
int drv_nc_init (void);
#endif
#ifdef CONFIG_JTAG_CONSOLE
int drv_jtag_console_init (void);
#endif
#endif
|
1001-study-uboot
|
include/stdio_dev.h
|
C
|
gpl3
| 3,398
|
/*
* Copyright (C) 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Serial Presence Detect (SPD) EEPROM format according to the
* Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
* revision 1.2B, November 1999
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SPD_H_
#define _SPD_H_
typedef struct spd_eeprom_s {
unsigned char info_size; /* 0 # bytes written into serial memory */
unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
unsigned char mem_type; /* 2 Fundamental memory type */
unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
unsigned char nrows; /* 5 # of Module Rows on this assembly */
unsigned char dataw_lsb; /* 6 Data Width of this assembly */
unsigned char dataw_msb; /* 7 ... Data Width continuation */
unsigned char voltage; /* 8 Voltage intf std of this assembly */
unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */
unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */
unsigned char config; /* 11 DIMM Configuration type */
unsigned char refresh; /* 12 Refresh Rate/Type */
unsigned char primw; /* 13 Primary SDRAM Width */
unsigned char ecw; /* 14 Error Checking SDRAM width */
unsigned char min_delay; /* 15 for Back to Back Random Address */
unsigned char burstl; /* 16 Burst Lengths Supported */
unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */
unsigned char cas_lat; /* 18 CAS# Latencies Supported */
unsigned char cs_lat; /* 19 CS# Latency */
unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */
unsigned char mod_attr; /* 21 SDRAM Module Attributes */
unsigned char dev_attr; /* 22 SDRAM Device Attributes */
unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */
unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */
unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
unsigned char row_dens; /* 31 Density of each row on module */
unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */
unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */
unsigned char data_setup; /* 34 Data signal input setup time */
unsigned char data_hold; /* 35 Data signal input hold time */
unsigned char twr; /* 36 Write Recovery time tWR */
unsigned char twtr; /* 37 Int write to read delay tWTR */
unsigned char trtp; /* 38 Int read to precharge delay tRTP */
unsigned char mem_probe; /* 39 Mem analysis probe characteristics */
unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
unsigned char trfc; /* 42 Min Auto to Active period tRFC */
unsigned char tckmax; /* 43 Max device cycle time tCKmax */
unsigned char tdqsq; /* 44 Max DQS to DQ skew */
unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */
unsigned char pll_relock; /* 46 PLL Relock time */
unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */
unsigned char spd_rev; /* 62 SPD Data Revision Code */
unsigned char cksum; /* 63 Checksum for bytes 0-62 */
unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */
unsigned char mloc; /* 72 Manufacturing Location */
unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
unsigned char rev[2]; /* 91 Revision Code */
unsigned char mdate[2]; /* 93 Manufacturing Date */
unsigned char sernum[4]; /* 95 Assembly Serial Number */
unsigned char mspec[27]; /* 99 Manufacturer Specific Data */
/*
* Open for Customer Use starting with byte 128.
*/
unsigned char freq; /* 128 Intel spec: frequency */
unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */
} spd_eeprom_t;
/*
* Byte 2 Fundamental Memory Types.
*/
#define SPD_MEMTYPE_FPM (0x01)
#define SPD_MEMTYPE_EDO (0x02)
#define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
#define SPD_MEMTYPE_SDRAM (0x04)
#define SPD_MEMTYPE_ROM (0x05)
#define SPD_MEMTYPE_SGRAM (0x06)
#define SPD_MEMTYPE_DDR (0x07)
#define SPD_MEMTYPE_DDR2 (0x08)
#endif /* _SPD_H_ */
|
1001-study-uboot
|
include/spd.h
|
C
|
gpl3
| 5,270
|
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* Altera Nios2 Standard Peripherals
************************************************************************/
#ifndef __NIOS2IO_H__
#define __NIOS2IO_H__
/*------------------------------------------------------------------------
* UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_uart_t {
unsigned rxdata; /* Rx data reg */
unsigned txdata; /* Tx data reg */
unsigned status; /* Status reg */
unsigned control; /* Control reg */
unsigned divisor; /* Baud rate divisor reg */
unsigned endofpacket; /* End-of-packet reg */
}nios_uart_t;
/* status register */
#define NIOS_UART_PE (1 << 0) /* parity error */
#define NIOS_UART_FE (1 << 1) /* frame error */
#define NIOS_UART_BRK (1 << 2) /* break detect */
#define NIOS_UART_ROE (1 << 3) /* rx overrun */
#define NIOS_UART_TOE (1 << 4) /* tx overrun */
#define NIOS_UART_TMT (1 << 5) /* tx empty */
#define NIOS_UART_TRDY (1 << 6) /* tx ready */
#define NIOS_UART_RRDY (1 << 7) /* rx ready */
#define NIOS_UART_E (1 << 8) /* exception */
#define NIOS_UART_DCTS (1 << 10) /* cts change */
#define NIOS_UART_CTS (1 << 11) /* cts */
#define NIOS_UART_EOP (1 << 12) /* eop detected */
/* control register */
#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/
#define NIOS_UART_IFE (1 << 1) /* frame error int ena */
#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */
#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */
#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */
#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */
#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */
#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */
#define NIOS_UART_IE (1 << 8) /* exception int ena */
#define NIOS_UART_TBRK (1 << 9) /* transmit break */
#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */
#define NIOS_UART_RTS (1 << 11) /* rts */
#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */
/*------------------------------------------------------------------------
* TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_timer_t {
unsigned status; /* Timer status reg */
unsigned control; /* Timer control reg */
unsigned periodl; /* Timeout period low */
unsigned periodh; /* Timeout period high */
unsigned snapl; /* Snapshot low */
unsigned snaph; /* Snapshot high */
}nios_timer_t;
/* status register */
#define NIOS_TIMER_TO (1 << 0) /* Timeout */
#define NIOS_TIMER_RUN (1 << 1) /* Timer running */
/* control register */
#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */
#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */
#define NIOS_TIMER_START (1 << 2) /* Start timer */
#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
/*------------------------------------------------------------------------
* PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_pio_t {
unsigned int data; /* Data value at each PIO in/out */
unsigned int direction; /* Data direct. for each PIO bit */
unsigned int interruptmask; /* Per-bit IRQ enable/disable */
unsigned int edgecapture; /* Per-bit sync. edge detect & hold */
}nios_pio_t;
/* direction register */
#define NIOS_PIO_OUT (1) /* PIO bit is output */
#define NIOS_PIO_IN (0) /* PIO bit is input */
/*------------------------------------------------------------------------
* SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_spi_t {
unsigned rxdata; /* Rx data reg */
unsigned txdata; /* Tx data reg */
unsigned status; /* Status reg */
unsigned control; /* Control reg */
unsigned reserved; /* (master only) */
unsigned slaveselect; /* SPI slave select mask (master only) */
}nios_spi_t;
/* status register */
#define NIOS_SPI_ROE (1 << 3) /* rx overrun */
#define NIOS_SPI_TOE (1 << 4) /* tx overrun */
#define NIOS_SPI_TMT (1 << 5) /* tx empty */
#define NIOS_SPI_TRDY (1 << 6) /* tx ready */
#define NIOS_SPI_RRDY (1 << 7) /* rx ready */
#define NIOS_SPI_E (1 << 8) /* exception */
/* control register */
#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */
#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */
#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */
#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */
#define NIOS_SPI_IE (1 << 8) /* exception int ena */
#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */
/*------------------------------------------------------------------------
* JTAG UART
*----------------------------------------------------------------------*/
typedef volatile struct nios_jtag_t {
unsigned data; /* Data register */
unsigned control; /* Control register */
}nios_jtag_t;
/* data register */
#define NIOS_JTAG_RVALID (1<<15) /* Read valid */
#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */
#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */
/* control register */
#define NIOS_JTAG_RE (1 << 0) /* read intr enable */
#define NIOS_JTAG_WE (1 << 1) /* write intr enable */
#define NIOS_JTAG_RI (1 << 8) /* read intr pending */
#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/
#define NIOS_JTAG_AC (1 << 10) /* activity indicator */
#define NIOS_JTAG_RRDY (1 << 12) /* read available */
#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
/*------------------------------------------------------------------------
* SYSTEM ID
*----------------------------------------------------------------------*/
typedef volatile struct nios_sysid_t {
unsigned id; /* The system build id*/
unsigned timestamp; /* Timestamp */
}nios_sysid_t;
#endif /* __NIOS2IO_H__ */
|
1001-study-uboot
|
include/nios2-io.h
|
C
|
gpl3
| 6,932
|
/*
* (C) Copyright 2003
* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* File: mpc5xx.h
*
* Discription: mpc5xx specific definitions
*
*/
#ifndef __MPC5XX_H__
#define __MPC5XX_H__
/*-----------------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* ISB bit in IMMR to set internal memory map
*/
#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1)
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control Register
*/
#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration Register
*/
#define SIUMCR_EARB 0x80000000 /* External Arbitration */
#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
#define SIUMCR_DBGC01 0x00200000 /* - " - */
#define SIUMCR_DBGC10 0x00400000 /* - " - */
#define SIUMCR_DBGC11 0x00600000 /* - " - */
#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
#define SIUMCR_SC10 0x00004000 /* Single adress show */
#define SIUMCR_SC11 0x00006000 /* Single adress */
#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */
#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000c00 /* - " - */
#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register
*/
#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */
#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */
#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control Register
*/
#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
#define PISCR_PS 0x0080 /* Periodic Interrupt Status */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register
*/
#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */
#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */
#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */
#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register
*/
#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_TBS 0x02000000 /* Time Base Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
/*-----------------------------------------------------------------------
* MC - Memory Controller
*/
#define BR_V 0x00000001 /* Bank valid */
#define BR_BI 0x00000002 /* Burst inhibit */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_LBDIR 0x00000008 /* Late burst data in progess */
#define BR_SETA 0x00000004 /* External Data Acknowledge */
#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
#define OR_TRLX 0x00000001 /* Timing relaxed */
#define OR_BSCY 0x00000060 /* Burst beats length in clocks */
#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
#define OR_CSNT 0x00000800 /* Chip-select negotation time */
#define OR_ETHR 0x00000100 /* Extended hold time on read */
#define OR_ADDR_MK_FF 0xFF000000
#define OR_ADDR_MK_FFFF 0xFFFF0000
/*-----------------------------------------------------------------------
* UMCR - UIMB Module Configuration Register
*/
#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
#define UMCR_HSPEED 0x10000000 /* Half speed */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
*/
#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */
#define NR_IRQS 0 /* Place this later in a separate file */
/*-----------------------------------------------------------------------
* SCI - Serial communication interface
*/
#define SCI_TDRE 0x0100 /* Transmit data register empty */
#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_RE 0x0004 /* Receiver enabled */
#define SCI_RDRF 0x0040 /* Receive data register full */
#define SCI_PE 0x0400 /* Parity enable */
#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_M_11 0x0200 /* Frame size is 11 bit */
#define SCI_M_10 0x0000 /* Frame size is 10 bit */
#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_2 ((int)2)
#endif /* __MPC5XX_H__ */
|
1001-study-uboot
|
include/mpc5xx.h
|
C
|
gpl3
| 8,520
|
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Operating System Interface
*
* This provides access to useful OS routines from the sandbox architecture
*/
/**
* Access to the OS read() system call
*
* \param fd File descriptor as returned by os_open()
* \param buf Buffer to place data
* \param count Number of bytes to read
* \return number of bytes read, or -1 on error
*/
ssize_t os_read(int fd, void *buf, size_t count);
/**
* Access to the OS write() system call
*
* \param fd File descriptor as returned by os_open()
* \param buf Buffer containing data to write
* \param count Number of bytes to write
* \return number of bytes written, or -1 on error
*/
ssize_t os_write(int fd, const void *buf, size_t count);
/**
* Access to the OS open() system call
*
* \param pathname Pathname of file to open
* \param flags Flags, like O_RDONLY, O_RDWR
* \return file descriptor, or -1 on error
*/
int os_open(const char *pathname, int flags);
/**
* Access to the OS close() system call
*
* \param fd File descriptor to close
* \return 0 on success, -1 on error
*/
int os_close(int fd);
/**
* Access to the OS exit() system call
*
* This exits with the supplied return code, which should be 0 to indicate
* success.
*
* @param exit_code exit code for U-Boot
*/
void os_exit(int exit_code);
/**
* Put tty into raw mode to mimic serial console better
*/
void os_tty_raw(int fd);
/**
* Acquires some memory from the underlying os.
*
* \param length Number of bytes to be allocated
* \return Pointer to length bytes or NULL on error
*/
void *os_malloc(size_t length);
/**
* Access to the usleep function of the os
*
* \param usec Time to sleep in micro seconds
*/
void os_usleep(unsigned long usec);
/**
* Gets a monotonic increasing number of nano seconds from the OS
*
* \return A monotonic increasing time scaled in nano seconds
*/
u64 os_get_nsec(void);
|
1001-study-uboot
|
include/os.h
|
C
|
gpl3
| 2,715
|
/*
* (C) Copyright 2008
* Niklaus Giger, niklaus.giger@member.fsf.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VXWORKS_H_
#define _VXWORKS_H_
int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/*
* Use bootaddr to find the location in memory that VxWorks
* will look for the bootline string. The default value for
* PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which
* defaults to 0x4200
*/
#ifndef CONFIG_SYS_VXWORKS_BOOT_ADDR
#define CONFIG_SYS_VXWORKS_BOOT_ADDR 0x4200
#endif
#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE
#if defined(CONFIG_4xx)
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)"
#elif defined(CONFIG_IOP480)
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)"
#else
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)"
#endif
#endif
#ifndef CONFIG_SYS_VXWORKS_SERVERNAME
#define CONFIG_SYS_VXWORKS_SERVERNAME "srv"
#endif
#endif
|
1001-study-uboot
|
include/vxworks.h
|
C
|
gpl3
| 1,649
|
/*
* (C) Copyright 2005-2009
* Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __BUS_VCXK_H_
#define __BUS_VCXK_H_
extern int vcxk_init(unsigned long width, unsigned long height);
extern void vcxk_setpixel(int x, int y, unsigned long color);
extern int vcxk_acknowledge_wait(void);
extern int vcxk_request(void);
extern void vcxk_loadimage(ulong source);
extern int vcxk_display_bitmap(ulong addr, int x, int y);
extern void vcxk_setbrightness(unsigned int side, short brightness);
extern int video_display_bitmap(ulong addr, int x, int y);
#endif
|
1001-study-uboot
|
include/bus_vcxk.h
|
C
|
gpl3
| 1,382
|
/*
* NOTE: DAVICOM DM9000 ethernet driver interface
*
* Authors: Remy Bohmer <linux@bohmer.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __DM9000_H__
#define __DM9000_H__
/****************** function prototypes **********************/
#if !defined(CONFIG_DM9000_NO_SROM)
void dm9000_write_srom_word(int offset, u16 val);
void dm9000_read_srom_word(int offset, u8 *to);
#endif
#endif /* __DM9000_H__ */
|
1001-study-uboot
|
include/dm9000.h
|
C
|
gpl3
| 697
|
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
* @Author: Markus Pietrek
* @References: [1] NS9750 Hardware Reference, December 2003
* [2] Intel LXT971 Datasheet #249414 Rev. 02
* [3] NS7520 Linux Ethernet Driver
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
***********************************************************************/
#ifndef __LXT971A_H__
#define __LXT971A_H__
/* PHY definitions (LXT971A) [2] */
#define PHY_LXT971_PORT_CFG (0x10)
#define PHY_LXT971_STAT2 (0x11)
#define PHY_LXT971_INT_ENABLE (0x12)
#define PHY_LXT971_INT_STATUS (0x13)
#define PHY_LXT971_LED_CFG (0x14)
#define PHY_LXT971_DIG_CFG (0x1A)
#define PHY_LXT971_TX_CTRL (0x1E)
/* PORT_CFG Port Configuration Register Bit Fields */
#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
#define PHY_LXT971_PORT_CFG_SQE (0x0200)
#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
/* STAT2 Status Register #2 Bit Fields */
#define PHY_LXT971_STAT2_RES1 (0x8000)
#define PHY_LXT971_STAT2_100BTX (0x4000)
#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
#define PHY_LXT971_STAT2_LINK (0x0400)
#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
#define PHY_LXT971_STAT2_RES2 (0x0040)
#define PHY_LXT971_STAT2_POLARITY (0x0020)
#define PHY_LXT971_STAT2_PAUSE (0x0010)
#define PHY_LXT971_STAT2_ERROR (0x0008)
#define PHY_LXT971_STAT2_RES3 (0x0007)
/* INT_ENABLE Interrupt Enable Register Bit Fields */
#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
/* INT_STATUS Interrupt Status Register Bit Fields */
#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
/* LED_CFG Interrupt LED Configuration Register Bit Fields */
#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
#define PHY_LXT971_LED_CFG_RES1 (0x0001)
/* only one of these values must be shifted for each SHIFT_LED? */
#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
#define PHY_LXT971_LED_CFG_LINK (0x0004)
#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
#define PHY_LXT971_LED_CFG_SPEED (0x0000)
/* DIG_CFG Digitial Configuration Register Bit Fields */
#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
#define PHY_LXT971_MDIO_MAX_CLK (8000000)
#define PHY_MDIO_MAX_CLK (2500000)
/* TX_CTRL Transmit Control Register Bit Fields
documentation is buggy for this register, therefore setting not included */
typedef enum
{
PHY_NONE = 0x0000, /* no PHY detected yet */
PHY_LXT971A = 0x0013
} PhyType;
#endif /* __LXT971A_H__ */
|
1001-study-uboot
|
include/lxt971a.h
|
C
|
gpl3
| 6,016
|
/*----------------------------------------------------------------------------+
| This source code is dual-licensed. You may use it under the terms of the
| GNU General Public License version 2, or under the license below.
|
| This source code has been made available to you by IBM on an AS-IS
| basis. Anyone receiving this source is licensed under IBM
| copyrights to use it in any way he or she deems fit, including
| copying it, modifying it, compiling it, and redistributing it either
| with or without modifications. No license under IBM patents or
| patent applications is to be implied by the copyright license.
|
| Any user of this software should understand that IBM cannot provide
| technical support for this software and will not be responsible for
| any consequences resulting from the use of this software.
|
| Any person who transfers this source code or any derivative work
| must include the IBM copyright notice, this paragraph, and the
| preceding two paragraphs in the transferred software.
|
| COPYRIGHT I B M CORPORATION 1999
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
| Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|
| File Name: miiphy.h
|
| Function: Include file defining PHY registers.
|
| Author: Mark Wisner
|
+----------------------------------------------------------------------------*/
#ifndef _miiphy_h_
#define _miiphy_h_
#include <common.h>
#include <linux/mii.h>
#include <linux/list.h>
#include <net.h>
#include <phy.h>
struct legacy_mii_dev {
int (*read)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int (*write)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
};
int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset(const char *devname, unsigned char addr);
int miiphy_speed(const char *devname, unsigned char addr);
int miiphy_duplex(const char *devname, unsigned char addr);
int miiphy_is_1000base_x(const char *devname, unsigned char addr);
#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
int miiphy_link(const char *devname, unsigned char addr);
#endif
void miiphy_init(void);
void miiphy_register(const char *devname,
int (*read)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (*write)(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
int miiphy_set_current_dev(const char *devname);
const char *miiphy_get_current_dev(void);
struct mii_dev *mdio_get_current_dev(void);
struct mii_dev *miiphy_get_dev_by_name(const char *devname);
struct phy_device *mdio_phydev_for_ethname(const char *devname);
void miiphy_listdev(void);
struct mii_dev *mdio_alloc(void);
int mdio_register(struct mii_dev *bus);
void mdio_list_devices(void);
#ifdef CONFIG_BITBANGMII
#define BB_MII_DEVNAME "bb_miiphy"
struct bb_miiphy_bus {
char name[NAMESIZE];
int (*init)(struct bb_miiphy_bus *bus);
int (*mdio_active)(struct bb_miiphy_bus *bus);
int (*mdio_tristate)(struct bb_miiphy_bus *bus);
int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
int (*delay)(struct bb_miiphy_bus *bus);
#ifdef CONFIG_BITBANGMII_MULTI
void *priv;
#endif
};
extern struct bb_miiphy_bus bb_miiphy_buses[];
extern int bb_miiphy_buses_num;
void bb_miiphy_init(void);
int bb_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int bb_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
#endif
/* phy seed setup */
#define AUTO 99
#define _1000BASET 1000
#define _100BASET 100
#define _10BASET 10
#define HALF 22
#define FULL 44
/* phy register offsets */
#define MII_MIPSCR 0x11
/* MII_LPA */
#define PHY_ANLPAR_PSB_802_3 0x0001
#define PHY_ANLPAR_PSB_802_9 0x0002
/* MII_CTRL1000 masks */
#define PHY_1000BTCR_1000FD 0x0200
#define PHY_1000BTCR_1000HD 0x0100
/* MII_STAT1000 masks */
#define PHY_1000BTSR_MSCF 0x8000
#define PHY_1000BTSR_MSCR 0x4000
#define PHY_1000BTSR_LRS 0x2000
#define PHY_1000BTSR_RRS 0x1000
#define PHY_1000BTSR_1000FD 0x0800
#define PHY_1000BTSR_1000HD 0x0400
/* phy EXSR */
#define ESTATUS_1000XF 0x8000
#define ESTATUS_1000XH 0x4000
#endif
|
1001-study-uboot
|
include/miiphy.h
|
C
|
gpl3
| 4,783
|
/*
* NOTE: MICREL ethernet Physical layer
*
* Version: KS8721.h
*
* Authors: Eric Benard (based on dm9161.h)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */
#define KS8721_BMCR 0
#define KS8721_BMSR 1
#define KS8721_PHYID1 2
#define KS8721_PHYID2 3
#define KS8721_ANAR 4
#define KS8721_ANLPAR 5
#define KS8721_ANER 6
#define KS8721_RECR 15
#define KS8721_MDINTR 27
#define KS8721_100BT 31
/* --Bit definitions: KS8721_BMCR */
#define KS8721_RESET (1 << 15)
#define KS8721_LOOPBACK (1 << 14)
#define KS8721_SPEED_SELECT (1 << 13)
#define KS8721_AUTONEG (1 << 12)
#define KS8721_POWER_DOWN (1 << 11)
#define KS8721_ISOLATE (1 << 10)
#define KS8721_RESTART_AUTONEG (1 << 9)
#define KS8721_DUPLEX_MODE (1 << 8)
#define KS8721_COLLISION_TEST (1 << 7)
#define KS8721_DISABLE (1 << 0)
/*--Bit definitions: KS8721_BMSR */
#define KS8721_100BASE_T4 (1 << 15)
#define KS8721_100BASE_TX_FD (1 << 14)
#define KS8721_100BASE_T4_HD (1 << 13)
#define KS8721_10BASE_T_FD (1 << 12)
#define KS8721_10BASE_T_HD (1 << 11)
#define KS8721_MF_PREAMB_SUPPR (1 << 6)
#define KS8721_AUTONEG_COMP (1 << 5)
#define KS8721_REMOTE_FAULT (1 << 4)
#define KS8721_AUTONEG_ABILITY (1 << 3)
#define KS8721_LINK_STATUS (1 << 2)
#define KS8721_JABBER_DETECT (1 << 1)
#define KS8721_EXTEND_CAPAB (1 << 0)
/*--Bit definitions: KS8721_PHYID */
#define KS8721_PHYID_OUI 0x0885
#define KS8721_LSB_MASK 0x3F
#define KS8721BL_MODEL 0x21
#define KS8721_MODELMASK 0x3F0
#define KS8721BL_REV 0x9
#define KS8721_REVMASK 0xF
/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */
#define KS8721_NP (1 << 15)
#define KS8721_ACK (1 << 14)
#define KS8721_RF (1 << 13)
#define KS8721_PAUSE (1 << 10)
#define KS8721_T4 (1 << 9)
#define KS8721_TX_FDX (1 << 8)
#define KS8721_TX_HDX (1 << 7)
#define KS8721_10_FDX (1 << 6)
#define KS8721_10_HDX (1 << 5)
#define KS8721_AN_IEEE_802_3 0x0001
/****************** function prototypes **********************/
unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac);
unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac);
unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char ks8721_initphy(AT91PS_EMAC p_mac);
|
1001-study-uboot
|
include/ks8721.h
|
C
|
gpl3
| 2,425
|
/*
* (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _universe_h
#define _universe_h
typedef struct _UNIVERSE UNIVERSE;
typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
struct _SLAVE_IMAGE {
unsigned int ctl; /* Control */
unsigned int bs; /* Base */
unsigned int bd; /* Bound */
unsigned int to; /* Translation */
unsigned int reserved;
};
struct _UNIVERSE {
unsigned int pci_id;
unsigned int pci_csr;
unsigned int pci_class;
unsigned int pci_misc0;
unsigned int pci_bs;
unsigned int spare0[10];
unsigned int pci_misc1;
unsigned int spare1[48];
SLAVE_IMAGE lsi[4];
unsigned int spare2[8];
unsigned int scyc_ctl;
unsigned int scyc_addr;
unsigned int scyc_en;
unsigned int scyc_cmp;
unsigned int scyc_swp;
unsigned int lmisc;
unsigned int slsi;
unsigned int l_cmderr;
unsigned int laerr;
unsigned int spare3[27];
unsigned int dctl;
unsigned int dtbc;
unsigned int dla;
unsigned int spare4[1];
unsigned int dva;
unsigned int spare5[1];
unsigned int dcpp;
unsigned int spare6[1];
unsigned int dgcs;
unsigned int d_llue;
unsigned int spare7[54];
unsigned int lint_en;
unsigned int lint_stat;
unsigned int lint_map0;
unsigned int lint_map1;
unsigned int vint_en;
unsigned int vint_stat;
unsigned int vint_map0;
unsigned int vint_map1;
unsigned int statid;
unsigned int vx_statid[7];
unsigned int spare8[48];
unsigned int mast_ctl;
unsigned int misc_ctl;
unsigned int misc_stat;
unsigned int user_am;
unsigned int spare9[700];
SLAVE_IMAGE vsi[4];
unsigned int spare10[8];
unsigned int vrai_ctl;
unsigned int vrai_bs;
unsigned int spare11[2];
unsigned int vcsr_ctl;
unsigned int vcsr_to;
unsigned int v_amerr;
unsigned int vaerr;
unsigned int spare12[25];
unsigned int vcsr_clr;
unsigned int vcsr_set;
unsigned int vcsr_bs;
};
#define IRQ_VOWN 0x0001
#define IRQ_VIRQ1 0x0002
#define IRQ_VIRQ2 0x0004
#define IRQ_VIRQ3 0x0008
#define IRQ_VIRQ4 0x0010
#define IRQ_VIRQ5 0x0020
#define IRQ_VIRQ6 0x0040
#define IRQ_VIRQ7 0x0080
#define IRQ_DMA 0x0100
#define IRQ_LERR 0x0200
#define IRQ_VERR 0x0400
#define IRQ_res 0x0800
#define IRQ_IACK 0x1000
#define IRQ_SWINT 0x2000
#define IRQ_SYSFAIL 0x4000
#define IRQ_ACFAIL 0x8000
struct _TDMA_CMD_PACKET {
unsigned int dctl; /* DMA Control */
unsigned int dtbc; /* Transfer Byte Count */
unsigned int dlv; /* PCI Address */
unsigned int res1; /* Reserved */
unsigned int dva; /* Vme Address */
unsigned int res2; /* Reserved */
unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
unsigned int res3; /* Reserved */
};
#define VME_AM_A16 0x01
#define VME_AM_A24 0x02
#define VME_AM_A32 0x03
#define VME_AM_Axx 0x03
#define VME_AM_SUP 0x04
#define VME_AM_DATA 0x10
#define VME_AM_PROG 0x20
#define VME_AM_Mxx 0x30
#define VME_FLAG_D8 0x01
#define VME_FLAG_D16 0x02
#define VME_FLAG_D32 0x03
#define VME_FLAG_Dxx 0x03
#define PCI_MS_MEM 0x01
#define PCI_MS_IO 0x02
#define PCI_MS_CONFIG 0x03
#define PCI_MS_Mxx 0x03
#endif
|
1001-study-uboot
|
include/universe.h
|
C
|
gpl3
| 4,032
|
#ifndef __LINUX_PS2MULT_H
#define __LINUX_PS2MULT_H
#define kbd_request_region() ps2mult_init()
#define kbd_request_irq(handler) ps2mult_request_irq(handler)
#define kbd_read_input() ps2mult_read_input()
#define kbd_read_status() ps2mult_read_status()
#define kbd_write_output(val) ps2mult_write_output(val)
#define kbd_write_command(val) ps2mult_write_command(val)
#define aux_request_irq(hand, dev_id) 0
#define aux_free_irq(dev_id)
#define PS2MULT_KB_SELECTOR 0xA0
#define PS2MULT_MS_SELECTOR 0xA1
#define PS2MULT_ESCAPE 0x7D
#define PS2MULT_BSYNC 0x7E
#define PS2MULT_SESSION_START 0x55
#define PS2MULT_SESSION_END 0x56
#define PS2BUF_SIZE 512 /* power of 2, please */
#ifndef CONFIG_PS2MULT_DELAY
#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
#endif
/* PS/2 controller interface (include/asm/keyboard.h)
*/
extern int ps2mult_init (void);
extern int ps2mult_request_irq(void (*handler)(void *));
extern u_char ps2mult_read_input(void);
extern u_char ps2mult_read_status(void);
extern void ps2mult_write_output(u_char val);
extern void ps2mult_write_command(u_char val);
extern void ps2mult_early_init (void);
extern void ps2mult_callback (int in_cnt);
/* Simple serial interface
*/
extern int ps2ser_init(void);
extern void ps2ser_putc(int chr);
extern int ps2ser_getc(void);
extern int ps2ser_check(void);
/* Serial related stuff
*/
struct serial_state {
int baud_base;
int irq;
u8 *iomem_base;
};
#endif /* __LINUX_PS2MULT_H */
|
1001-study-uboot
|
include/ps2mult.h
|
C
|
gpl3
| 1,501
|
/*
* (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_NFC_H
#define __FSL_NFC_H
/*
* TODO: Use same register defs for nand_spl mxc nand driver
* and mtd mxc nand driver.
*
* Register map and bit definitions for the Freescale NAND Flash
* Controller present in various i.MX devices.
*
* MX31 and MX27 have version 1 which has
* 4 512 byte main buffers and
* 4 16 byte spare buffers
* to support up to 2K byte pagesize nand.
* Reading or writing a 2K page requires 4 FDI/FDO cycles.
*
* MX25 has version 1.1 which has
* 8 512 byte main buffers and
* 8 64 byte spare buffers
* to support up to 4K byte pagesize nand.
* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
* Also some of registers are moved and/or changed meaning as seen below.
*/
#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
#define MXC_NFC_V1
#elif defined(CONFIG_MX25)
#define MXC_NFC_V1_1
#else
#warning "MXC NFC version not defined"
#endif
#if defined(MXC_NFC_V1)
#define NAND_MXC_NR_BUFS 4
#define NAND_MXC_SPARE_BUF_SIZE 16
#define NAND_MXC_REG_OFFSET 0xe00
#define NAND_MXC_2K_MULTI_CYCLE 1
#elif defined(MXC_NFC_V1_1)
#define NAND_MXC_NR_BUFS 8
#define NAND_MXC_SPARE_BUF_SIZE 64
#define NAND_MXC_REG_OFFSET 0x1e00
#else
#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
#endif
struct fsl_nfc_regs {
u32 main_area[NAND_MXC_NR_BUFS][512/4];
u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
/*
* reserved size is offset of nfc registers
* minus total main and spare sizes
*/
u8 reserved1[NAND_MXC_REG_OFFSET
- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
#if defined(MXC_NFC_V1)
u16 bufsiz;
u16 reserved2;
u16 buffer_address;
u16 flash_add;
u16 flash_cmd;
u16 configuration;
u16 ecc_status_result;
u16 ecc_rslt_main_area;
u16 ecc_rslt_spare_area;
u16 nf_wr_prot;
u16 unlock_start_blk_add;
u16 unlock_end_blk_add;
u16 nand_flash_wr_pr_st;
u16 nand_flash_config1;
u16 nand_flash_config2;
#elif defined(MXC_NFC_V1_1)
u16 reserved2[2];
u16 buffer_address;
u16 flash_add;
u16 flash_cmd;
u16 configuration;
u16 ecc_status_result;
u16 ecc_status_result2;
u16 spare_area_size;
u16 nf_wr_prot;
u16 reserved3[2];
u16 nand_flash_wr_pr_st;
u16 nand_flash_config1;
u16 nand_flash_config2;
u16 reserved4;
u16 unlock_start_blk_add0;
u16 unlock_end_blk_add0;
u16 unlock_start_blk_add1;
u16 unlock_end_blk_add1;
u16 unlock_start_blk_add2;
u16 unlock_end_blk_add2;
u16 unlock_start_blk_add3;
u16 unlock_end_blk_add3;
#endif
};
/*
* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
* operation
*/
#define NFC_CMD 0x1
/*
* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
* operation
*/
#define NFC_ADDR 0x2
/*
* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
* operation
*/
#define NFC_INPUT 0x4
/*
* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
* Output operation
*/
#define NFC_OUTPUT 0x8
/*
* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
* operation
*/
#define NFC_ID 0x10
/*
* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
* Status operation
*/
#define NFC_STATUS 0x20
/*
* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
* operation
*/
#define NFC_INT 0x8000
#ifdef MXC_NFC_V1_1
#define NFC_4_8N_ECC (1 << 0)
#endif
#define NFC_SP_EN (1 << 2)
#define NFC_ECC_EN (1 << 3)
#define NFC_INT_MSK (1 << 4)
#define NFC_BIG (1 << 5)
#define NFC_RST (1 << 6)
#define NFC_CE (1 << 7)
#define NFC_ONE_CYCLE (1 << 8)
#endif /* __FSL_NFC_H */
|
1001-study-uboot
|
include/fsl_nfc.h
|
C
|
gpl3
| 4,437
|
/*
* (C) Copyright 2006, Imagos S.a.s <www.imagos.it>
* Renato Andreola <renato.andreola@imagos.it>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* Altera NiosII YANU serial interface by Imagos
* please see http://www.opencores.org/project,yanu for
* information/downloads
************************************************************************/
#ifndef __NIOS2_YANU_H__
#define __NIOS2_YANU_H__
#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */
#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */
#define YANU_FIFO_SIZE (16)
#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE)
#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE)
#define YANU_RXFIFO_DLY (10*11)
#define YANU_TXFIFO_THR (10)
#define YANU_DATA_CHAR_MASK (0xFF)
/* data register */
#define YANU_DATA_OFFSET (0) /* data register offset */
#define YANU_CONTROL_OFFSET (4) /* control register offset */
/* interrupt enable */
#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */
#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */
#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */
#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */
#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */
#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */
/* control bits */
#define YANU_CONTROL_BITS_POS (6) /* bits number pos */
#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */
#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */
#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */
#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */
#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */
#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */
#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */
/* tuning part */
#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */
#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */
#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */
#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */
#define YANU_BAUD_OFFSET (8) /* baud register offset */
#define YANU_BAUDM (1<<0) /* baud mantissa lsb */
#define YANU_BAUDM_N (12) /* ...its bit filed length */
#define YANU_BAUDE (1<<12) /* baud exponent lsb */
#define YANU_BAUDE_N (4) /* ...its bit field length */
#define YANU_ACTION_OFFSET (12) /* action register... write only */
#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */
#define YANU_ACTION_ROE (1<<1) /* reset oe */
#define YANU_ACTION_RBRK (1<<2) /* reset brk */
#define YANU_ACTION_RFE (1<<3) /* reset fe */
#define YANU_ACTION_RPE (1<<4) /* reset pe */
#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */
#define YANU_ACTION_SOE (1<<6) /* set oe */
#define YANU_ACTION_SBRK (1<<7) /* set brk */
#define YANU_ACTION_SFE (1<<8) /* set fe */
#define YANU_ACTION_SPE (1<<9) /* set pe */
#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */
#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */
#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */
#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */
#define YANU_ACTION_STRDY (1<<14) /* set trdy */
#define YANU_STATUS_OFFSET (16)
#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */
#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */
#define YANU_STATUS_OE (1<<2) /* rx overrun error */
#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */
#define YANU_STATUS_FE (1<<4) /* rx framing error flag */
#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */
#define YANU_RFIFO_CHARS_POS (6)
#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */
#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */
#define YANU_TFIFO_CHARS_POS (11)
#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */
#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */
typedef volatile struct yanu_uart_t {
volatile unsigned data;
volatile unsigned control; /* control register (RW) 32-bit */
volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */
volatile unsigned action; /* action register (W) 32-bit */
volatile unsigned status; /* status register (R) 32-bit */
volatile unsigned magic; /* magic register (R) 32-bit */
} yanu_uart_t;
#endif
|
1001-study-uboot
|
include/nios2-yanu.h
|
C
|
gpl3
| 5,543
|
/*
* Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __MPC83XX_H__
#define __MPC83XX_H__
#include <config.h>
#include <asm/fsl_lbc.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif
/*
* MPC83xx cpu provide RCR register to do reset thing specially
*/
#define MPC83xx_RESET
/*
* System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/*
* IMMRBAR - Internal Memory Register Base Address
*/
#ifndef CONFIG_DEFAULT_IMMR
/* Default IMMR base address */
#define CONFIG_DEFAULT_IMMR 0xFF400000
#endif
/* Register offset to immr */
#define IMMRBAR 0x0000
#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
/*
* LAWBAR - Local Access Window Base Address Register
*/
/* Register offset to immr */
#define LBLAWBAR0 0x0020
#define LBLAWAR0 0x0024
#define LBLAWBAR1 0x0028
#define LBLAWAR1 0x002C
#define LBLAWBAR2 0x0030
#define LBLAWAR2 0x0034
#define LBLAWBAR3 0x0038
#define LBLAWAR3 0x003C
#define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
/*
* SPRIDR - System Part and Revision ID Register
*/
#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
#if defined(CONFIG_MPC834x)
#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
#define REVID_MINOR(spridr) (spridr & 0x000000FF)
#else
#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
#define REVID_MINOR(spridr) (spridr & 0x0000000F)
#endif
#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
#define SPR_8308 0x8100
#define SPR_831X_FAMILY 0x80B
#define SPR_8311 0x80B2
#define SPR_8313 0x80B0
#define SPR_8314 0x80B6
#define SPR_8315 0x80B4
#define SPR_832X_FAMILY 0x806
#define SPR_8321 0x8066
#define SPR_8323 0x8062
#define SPR_834X_FAMILY 0x803
#define SPR_8343 0x8036
#define SPR_8347_TBGA_ 0x8032
#define SPR_8347_PBGA_ 0x8034
#define SPR_8349 0x8030
#define SPR_836X_FAMILY 0x804
#define SPR_8358_TBGA_ 0x804A
#define SPR_8358_PBGA_ 0x804E
#define SPR_8360 0x8048
#define SPR_837X_FAMILY 0x80C
#define SPR_8377 0x80C6
#define SPR_8378 0x80C4
#define SPR_8379 0x80C2
/*
* SPCR - System Priority Configuration Register
*/
/* PCI Highest Priority Enable */
#define SPCR_PCIHPE 0x10000000
#define SPCR_PCIHPE_SHIFT (31-3)
/* PCI bridge system bus request priority */
#define SPCR_PCIPR 0x03000000
#define SPCR_PCIPR_SHIFT (31-7)
#define SPCR_OPT 0x00800000 /* Optimize */
#define SPCR_OPT_SHIFT (31-8)
/* E300 PowerPC core time base unit enable */
#define SPCR_TBEN 0x00400000
#define SPCR_TBEN_SHIFT (31-9)
/* E300 PowerPC Core system bus request priority */
#define SPCR_COREPR 0x00300000
#define SPCR_COREPR_SHIFT (31-11)
#if defined(CONFIG_MPC834x)
/* SPCR bits - MPC8349 specific */
/* TSEC1 data priority */
#define SPCR_TSEC1DP 0x00003000
#define SPCR_TSEC1DP_SHIFT (31-19)
/* TSEC1 buffer descriptor priority */
#define SPCR_TSEC1BDP 0x00000C00
#define SPCR_TSEC1BDP_SHIFT (31-21)
/* TSEC1 emergency priority */
#define SPCR_TSEC1EP 0x00000300
#define SPCR_TSEC1EP_SHIFT (31-23)
/* TSEC2 data priority */
#define SPCR_TSEC2DP 0x00000030
#define SPCR_TSEC2DP_SHIFT (31-27)
/* TSEC2 buffer descriptor priority */
#define SPCR_TSEC2BDP 0x0000000C
#define SPCR_TSEC2BDP_SHIFT (31-29)
/* TSEC2 emergency priority */
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
/* TSEC buffer descriptor priority */
#define SPCR_TSECBDP 0x00000C00
#define SPCR_TSECBDP_SHIFT (31-21)
/* TSEC emergency priority */
#define SPCR_TSECEP 0x00000300
#define SPCR_TSECEP_SHIFT (31-23)
#endif
/* SICRL/H - System I/O Configuration Register Low/High
*/
#if defined(CONFIG_MPC834x)
/* SICRL bits - MPC8349 specific */
#define SICRL_LDP_A 0x80000000
#define SICRL_USB1 0x40000000
#define SICRL_USB0 0x20000000
#define SICRL_UART 0x0C000000
#define SICRL_GPIO1_A 0x02000000
#define SICRL_GPIO1_B 0x01000000
#define SICRL_GPIO1_C 0x00800000
#define SICRL_GPIO1_D 0x00400000
#define SICRL_GPIO1_E 0x00200000
#define SICRL_GPIO1_F 0x00180000
#define SICRL_GPIO1_G 0x00040000
#define SICRL_GPIO1_H 0x00020000
#define SICRL_GPIO1_I 0x00010000
#define SICRL_GPIO1_J 0x00008000
#define SICRL_GPIO1_K 0x00004000
#define SICRL_GPIO1_L 0x00003000
/* SICRH bits - MPC8349 specific */
#define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC1_C 0x04000000
#define SICRH_TSEC1_D 0x02000000
#define SICRH_TSEC1_E 0x01000000
#define SICRH_TSEC1_F 0x00800000
#define SICRH_TSEC2_A 0x00400000
#define SICRH_TSEC2_B 0x00200000
#define SICRH_TSEC2_C 0x00100000
#define SICRH_TSEC2_D 0x00080000
#define SICRH_TSEC2_E 0x00040000
#define SICRH_TSEC2_F 0x00020000
#define SICRH_TSEC2_G 0x00010000
#define SICRH_TSEC2_H 0x00008000
#define SICRH_GPIO2_A 0x00004000
#define SICRH_GPIO2_B 0x00002000
#define SICRH_GPIO2_C 0x00001000
#define SICRH_GPIO2_D 0x00000800
#define SICRH_GPIO2_E 0x00000400
#define SICRH_GPIO2_F 0x00000200
#define SICRH_GPIO2_G 0x00000180
#define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC8360)
/* SICRL bits - MPC8360 specific */
#define SICRL_LDP_A 0xC0000000
#define SICRL_LCLK_1 0x10000000
#define SICRL_LCLK_2 0x08000000
#define SICRL_SRCID_A 0x03000000
#define SICRL_IRQ_CKSTP_A 0x00C00000
/* SICRH bits - MPC8360 specific */
#define SICRH_DDR 0x80000000
#define SICRH_SECONDARY_DDR 0x40000000
#define SICRH_SDDROE 0x20000000
#define SICRH_IRQ3 0x10000000
#define SICRH_UC1EOBI 0x00000004
#define SICRH_UC2E1OBI 0x00000002
#define SICRH_UC2E2OBI 0x00000001
#elif defined(CONFIG_MPC832x)
/* SICRL bits - MPC832x specific */
#define SICRL_LDP_LCS_A 0x80000000
#define SICRL_IRQ_CKS 0x20000000
#define SICRL_PCI_MSRC 0x10000000
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
#elif defined(CONFIG_MPC8313)
/* SICRL bits - MPC8313 specific */
#define SICRL_LBC 0x30000000
#define SICRL_UART 0x0C000000
#define SICRL_SPI_A 0x03000000
#define SICRL_SPI_B 0x00C00000
#define SICRL_SPI_C 0x00300000
#define SICRL_SPI_D 0x000C0000
#define SICRL_USBDR_11 0x00000C00
#define SICRL_USBDR_10 0x00000800
#define SICRL_USBDR_01 0x00000400
#define SICRL_USBDR_00 0x00000000
#define SICRL_ETSEC1_A 0x0000000C
#define SICRL_ETSEC2_A 0x00000003
/* SICRH bits - MPC8313 specific */
#define SICRH_INTR_A 0x02000000
#define SICRH_INTR_B 0x00C00000
#define SICRH_IIC 0x00300000
#define SICRH_ETSEC2_B 0x000C0000
#define SICRH_ETSEC2_C 0x00030000
#define SICRH_ETSEC2_D 0x0000C000
#define SICRH_ETSEC2_E 0x00003000
#define SICRH_ETSEC2_F 0x00000C00
#define SICRH_ETSEC2_G 0x00000300
#define SICRH_ETSEC1_B 0x00000080
#define SICRH_ETSEC1_C 0x00000060
#define SICRH_GTX1_DLY 0x00000008
#define SICRH_GTX2_DLY 0x00000004
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC8315)
/* SICRL bits - MPC8315 specific */
#define SICRL_DMA_CH0 0xc0000000
#define SICRL_DMA_SPI 0x30000000
#define SICRL_UART 0x0c000000
#define SICRL_IRQ4 0x02000000
#define SICRL_IRQ5 0x01800000
#define SICRL_IRQ6_7 0x00400000
#define SICRL_IIC1 0x00300000
#define SICRL_TDM 0x000c0000
#define SICRL_TDM_SHARED 0x00030000
#define SICRL_PCI_A 0x0000c000
#define SICRL_ELBC_A 0x00003000
#define SICRL_ETSEC1_A 0x000000c0
#define SICRL_ETSEC1_B 0x00000030
#define SICRL_ETSEC1_C 0x0000000c
#define SICRL_TSEXPOBI 0x00000001
/* SICRH bits - MPC8315 specific */
#define SICRH_GPIO_0 0xc0000000
#define SICRH_GPIO_1 0x30000000
#define SICRH_GPIO_2 0x0c000000
#define SICRH_GPIO_3 0x03000000
#define SICRH_GPIO_4 0x00c00000
#define SICRH_GPIO_5 0x00300000
#define SICRH_GPIO_6 0x000c0000
#define SICRH_GPIO_7 0x00030000
#define SICRH_GPIO_8 0x0000c000
#define SICRH_GPIO_9 0x00003000
#define SICRH_GPIO_10 0x00000c00
#define SICRH_GPIO_11 0x00000300
#define SICRH_ETSEC2_A 0x000000c0
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC837x)
/* SICRL bits - MPC837x specific */
#define SICRL_USB_A 0xC0000000
#define SICRL_USB_B 0x30000000
#define SICRL_USB_B_SD 0x20000000
#define SICRL_UART 0x0C000000
#define SICRL_GPIO_A 0x02000000
#define SICRL_GPIO_B 0x01000000
#define SICRL_GPIO_C 0x00800000
#define SICRL_GPIO_D 0x00400000
#define SICRL_GPIO_E 0x00200000
#define SICRL_GPIO_F 0x00180000
#define SICRL_GPIO_G 0x00040000
#define SICRL_GPIO_H 0x00020000
#define SICRL_GPIO_I 0x00010000
#define SICRL_GPIO_J 0x00008000
#define SICRL_GPIO_K 0x00004000
#define SICRL_GPIO_L 0x00003000
#define SICRL_DMA_A 0x00000800
#define SICRL_DMA_B 0x00000400
#define SICRL_DMA_C 0x00000200
#define SICRL_DMA_D 0x00000100
#define SICRL_DMA_E 0x00000080
#define SICRL_DMA_F 0x00000040
#define SICRL_DMA_G 0x00000020
#define SICRL_DMA_H 0x00000010
#define SICRL_DMA_I 0x00000008
#define SICRL_DMA_J 0x00000004
#define SICRL_LDP_A 0x00000002
#define SICRL_LDP_B 0x00000001
/* SICRH bits - MPC837x specific */
#define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC2_A 0x00400000
#define SICRH_TSEC2_B 0x00200000
#define SICRH_TSEC2_C 0x00100000
#define SICRH_TSEC2_D 0x00080000
#define SICRH_TSEC2_E 0x00040000
#define SICRH_TMR 0x00010000
#define SICRH_GPIO2_A 0x00008000
#define SICRH_GPIO2_B 0x00004000
#define SICRH_GPIO2_C 0x00002000
#define SICRH_GPIO2_D 0x00001000
#define SICRH_GPIO2_E 0x00000C00
#define SICRH_GPIO2_E_SD 0x00000800
#define SICRH_GPIO2_F 0x00000300
#define SICRH_GPIO2_G 0x000000C0
#define SICRH_GPIO2_H 0x00000030
#define SICRH_SPI 0x00000003
#define SICRH_SPI_SD 0x00000001
#elif defined(CONFIG_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
#define SICRL_SPI_PF1 (1 << 28)
#define SICRL_SPI_PF3 (3 << 28)
#define SICRL_UART_PF0 (0 << 26)
#define SICRL_UART_PF1 (1 << 26)
#define SICRL_UART_PF3 (3 << 26)
#define SICRL_IRQ_PF0 (0 << 24)
#define SICRL_IRQ_PF1 (1 << 24)
#define SICRL_I2C2_PF0 (0 << 20)
#define SICRL_I2C2_PF1 (1 << 20)
#define SICRL_ETSEC1_TX_CLK (0 << 6)
#define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
/* SICRH bits - MPC8308 specific */
#define SICRH_ESDHC_A_SD (0 << 30)
#define SICRH_ESDHC_A_GTM (1 << 30)
#define SICRH_ESDHC_A_GPIO (3 << 30)
#define SICRH_ESDHC_B_SD (0 << 28)
#define SICRH_ESDHC_B_GTM (1 << 28)
#define SICRH_ESDHC_B_GPIO (3 << 28)
#define SICRH_ESDHC_C_SD (0 << 26)
#define SICRH_ESDHC_C_GTM (1 << 26)
#define SICRH_ESDHC_C_GPIO (3 << 26)
#define SICRH_GPIO_A_GPIO (0 << 24)
#define SICRH_GPIO_A_TSEC2 (1 << 24)
#define SICRH_GPIO_B_GPIO (0 << 22)
#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
#define SICRH_IEEE1588_A_TMR (1 << 20)
#define SICRH_IEEE1588_A_GPIO (3 << 20)
#define SICRH_USB (1 << 18)
#define SICRH_GTM_GTM (1 << 16)
#define SICRH_GTM_GPIO (3 << 16)
#define SICRH_IEEE1588_B_TMR (1 << 14)
#define SICRH_IEEE1588_B_GPIO (3 << 14)
#define SICRH_ETSEC2_CRS (1 << 12)
#define SICRH_ETSEC2_GPIO (3 << 12)
#define SICRH_GPIOSEL_0 (0 << 8)
#define SICRH_GPIOSEL_1 (1 << 8)
#define SICRH_TMROBI_V3P3 (0 << 4)
#define SICRH_TMROBI_V2P5 (1 << 4)
#define SICRH_TSOBI1_V3P3 (0 << 1)
#define SICRH_TSOBI1_V2P5 (1 << 1)
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
#endif
/*
* SWCRR - System Watchdog Control Register
*/
/* Register offset to immr */
#define SWCRR 0x0204
/* Software Watchdog Time Count */
#define SWCRR_SWTC 0xFFFF0000
/* Watchdog Enable bit */
#define SWCRR_SWEN 0x00000004
/* Software Watchdog Reset/Interrupt Select bit */
#define SWCRR_SWRI 0x00000002
/* Software Watchdog Counter Prescale bit */
#define SWCRR_SWPR 0x00000001
#define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
SWCRR_SWRI | SWCRR_SWPR))
/*
* SWCNR - System Watchdog Counter Register
*/
/* Register offset to immr */
#define SWCNR 0x0208
/* Software Watchdog Count mask */
#define SWCNR_SWCN 0x0000FFFF
#define SWCNR_RES ~(SWCNR_SWCN)
/*
* SWSRR - System Watchdog Service Register
*/
/* Register offset to immr */
#define SWSRR 0x020E
/*
* ACR - Arbiter Configuration Register
*/
#define ACR_COREDIS 0x10000000 /* Core disable */
#define ACR_COREDIS_SHIFT (31-7)
#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
#define ACR_PIPE_DEP_SHIFT (31-15)
#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
#define ACR_PCI_RPTCNT_SHIFT (31-19)
#define ACR_RPTCNT 0x00000700 /* Repeat count */
#define ACR_RPTCNT_SHIFT (31-23)
#define ACR_APARK 0x00000030 /* Address parking */
#define ACR_APARK_SHIFT (31-27)
#define ACR_PARKM 0x0000000F /* Parking master */
#define ACR_PARKM_SHIFT (31-31)
/*
* ATR - Arbiter Timers Register
*/
#define ATR_DTO 0x00FF0000 /* Data time out */
#define ATR_DTO_SHIFT 16
#define ATR_ATO 0x000000FF /* Address time out */
#define ATR_ATO_SHIFT 0
/*
* AER - Arbiter Event Register
*/
#define AER_ETEA 0x00000020 /* Transfer error */
/* Reserved transfer type */
#define AER_RES 0x00000010
/* External control word transfer type */
#define AER_ECW 0x00000008
/* Address Only transfer type */
#define AER_AO 0x00000004
#define AER_DTO 0x00000002 /* Data time out */
#define AER_ATO 0x00000001 /* Address time out */
/*
* AEATR - Arbiter Event Address Register
*/
#define AEATR_EVENT 0x07000000 /* Event type */
#define AEATR_EVENT_SHIFT 24
#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
#define AEATR_MSTR_ID_SHIFT 16
#define AEATR_TBST 0x00000800 /* Transfer burst */
#define AEATR_TBST_SHIFT 11
#define AEATR_TSIZE 0x00000700 /* Transfer Size */
#define AEATR_TSIZE_SHIFT 8
#define AEATR_TTYPE 0x0000001F /* Transfer Type */
#define AEATR_TTYPE_SHIFT 0
/*
* HRCWL - Hard Reset Configuration Word Low
*/
#define HRCWL_LBIUCM 0x80000000
#define HRCWL_LBIUCM_SHIFT 31
#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
#define HRCWL_DDRCM 0x40000000
#define HRCWL_DDRCM_SHIFT 30
#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
#define HRCWL_SPMF 0x0f000000
#define HRCWL_SPMF_SHIFT 24
#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
#define HRCWL_VCO_BYPASS 0x00000000
#define HRCWL_VCO_1X2 0x00000000
#define HRCWL_VCO_1X4 0x00200000
#define HRCWL_VCO_1X8 0x00400000
#define HRCWL_COREPLL 0x007F0000
#define HRCWL_COREPLL_SHIFT 16
#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
#define HRCWL_CORE_TO_CSB_1X1 0x00020000
#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
#define HRCWL_CORE_TO_CSB_2X1 0x00040000
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
#define HRCWL_CORE_TO_CSB_3X1 0x00060000
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
#define HRCWL_CEPDF 0x00000020
#define HRCWL_CEPDF_SHIFT 5
#define HRCWL_CE_PLL_DIV_1X1 0x00000000
#define HRCWL_CE_PLL_DIV_2X1 0x00000020
#define HRCWL_CEPMF 0x0000001F
#define HRCWL_CEPMF_SHIFT 0
#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
#define HRCWL_CE_TO_PLL_1X2 0x00000002
#define HRCWL_CE_TO_PLL_1X3 0x00000003
#define HRCWL_CE_TO_PLL_1X4 0x00000004
#define HRCWL_CE_TO_PLL_1X5 0x00000005
#define HRCWL_CE_TO_PLL_1X6 0x00000006
#define HRCWL_CE_TO_PLL_1X7 0x00000007
#define HRCWL_CE_TO_PLL_1X8 0x00000008
#define HRCWL_CE_TO_PLL_1X9 0x00000009
#define HRCWL_CE_TO_PLL_1X10 0x0000000A
#define HRCWL_CE_TO_PLL_1X11 0x0000000B
#define HRCWL_CE_TO_PLL_1X12 0x0000000C
#define HRCWL_CE_TO_PLL_1X13 0x0000000D
#define HRCWL_CE_TO_PLL_1X14 0x0000000E
#define HRCWL_CE_TO_PLL_1X15 0x0000000F
#define HRCWL_CE_TO_PLL_1X16 0x00000010
#define HRCWL_CE_TO_PLL_1X17 0x00000011
#define HRCWL_CE_TO_PLL_1X18 0x00000012
#define HRCWL_CE_TO_PLL_1X19 0x00000013
#define HRCWL_CE_TO_PLL_1X20 0x00000014
#define HRCWL_CE_TO_PLL_1X21 0x00000015
#define HRCWL_CE_TO_PLL_1X22 0x00000016
#define HRCWL_CE_TO_PLL_1X23 0x00000017
#define HRCWL_CE_TO_PLL_1X24 0x00000018
#define HRCWL_CE_TO_PLL_1X25 0x00000019
#define HRCWL_CE_TO_PLL_1X26 0x0000001A
#define HRCWL_CE_TO_PLL_1X27 0x0000001B
#define HRCWL_CE_TO_PLL_1X28 0x0000001C
#define HRCWL_CE_TO_PLL_1X29 0x0000001D
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
#define HRCWL_SVCOD_DIV_4 0x10000000
#define HRCWL_SVCOD_DIV_8 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
#elif defined(CONFIG_MPC837x)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/*
* HRCWH - Hardware Reset Configuration Word High
*/
#define HRCWH_PCI_HOST 0x80000000
#define HRCWH_PCI_HOST_SHIFT 31
#define HRCWH_PCI_AGENT 0x00000000
#if defined(CONFIG_MPC834x)
#define HRCWH_32_BIT_PCI 0x00000000
#define HRCWH_64_BIT_PCI 0x40000000
#endif
#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
#if defined(CONFIG_MPC834x)
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
#elif defined(CONFIG_MPC8360)
#define HRCWH_PCICKDRV_DISABLE 0x00000000
#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
#define HRCWH_CORE_DISABLE 0x08000000
#define HRCWH_CORE_ENABLE 0x00000000
#define HRCWH_FROM_0X00000100 0x00000000
#define HRCWH_FROM_0XFFF00100 0x04000000
#define HRCWH_BOOTSEQ_DISABLE 0x00000000
#define HRCWH_BOOTSEQ_NORMAL 0x01000000
#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000
#if defined(CONFIG_MPC834x)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
#if defined(CONFIG_MPC837x)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
#define HRCWH_RL_EXT_LEGACY 0x00000000
#define HRCWH_RL_EXT_NAND 0x00040000
#define HRCWH_TSEC1M_MASK 0x0000E000
#define HRCWH_TSEC1M_IN_MII 0x00000000
#define HRCWH_TSEC1M_IN_RMII 0x00002000
#define HRCWH_TSEC1M_IN_RGMII 0x00006000
#define HRCWH_TSEC1M_IN_RTBI 0x0000A000
#define HRCWH_TSEC1M_IN_SGMII 0x0000C000
#define HRCWH_TSEC2M_MASK 0x00001C00
#define HRCWH_TSEC2M_IN_MII 0x00000000
#define HRCWH_TSEC2M_IN_RMII 0x00000400
#define HRCWH_TSEC2M_IN_RGMII 0x00000C00
#define HRCWH_TSEC2M_IN_RTBI 0x00001400
#define HRCWH_TSEC2M_IN_SGMII 0x00001800
#endif
#if defined(CONFIG_MPC834x)
#define HRCWH_TSEC1M_IN_RGMII 0x00000000
#define HRCWH_TSEC1M_IN_RTBI 0x00004000
#define HRCWH_TSEC1M_IN_GMII 0x00008000
#define HRCWH_TSEC1M_IN_TBI 0x0000C000
#define HRCWH_TSEC2M_IN_RGMII 0x00000000
#define HRCWH_TSEC2M_IN_RTBI 0x00001000
#define HRCWH_TSEC2M_IN_GMII 0x00002000
#define HRCWH_TSEC2M_IN_TBI 0x00003000
#endif
#if defined(CONFIG_MPC8360)
#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
#endif
#define HRCWH_BIG_ENDIAN 0x00000000
#define HRCWH_LITTLE_ENDIAN 0x00000008
#define HRCWH_LALE_NORMAL 0x00000000
#define HRCWH_LALE_EARLY 0x00000004
#define HRCWH_LDP_SET 0x00000000
#define HRCWH_LDP_CLEAR 0x00000002
/*
* RSR - Reset Status Register
*/
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
#define RSR_RSTSRC 0xE0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 29
#endif
#define RSR_BSF 0x00010000 /* Boot seq. fail */
#define RSR_BSF_SHIFT 16
/* software soft reset */
#define RSR_SWSR 0x00002000
#define RSR_SWSR_SHIFT 13
/* software hard reset */
#define RSR_SWHR 0x00001000
#define RSR_SWHR_SHIFT 12
#define RSR_JHRS 0x00000200 /* jtag hreset */
#define RSR_JHRS_SHIFT 9
/* jtag sreset status */
#define RSR_JSRS 0x00000100
#define RSR_JSRS_SHIFT 8
/* checkstop reset status */
#define RSR_CSHR 0x00000010
#define RSR_CSHR_SHIFT 4
/* software watchdog reset status */
#define RSR_SWRS 0x00000008
#define RSR_SWRS_SHIFT 3
/* bus monitop reset status */
#define RSR_BMRS 0x00000004
#define RSR_BMRS_SHIFT 2
#define RSR_SRS 0x00000002 /* soft reset status */
#define RSR_SRS_SHIFT 1
#define RSR_HRS 0x00000001 /* hard reset status */
#define RSR_HRS_SHIFT 0
#define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
RSR_SWHR | RSR_JHRS | \
RSR_JSRS | RSR_CSHR | \
RSR_SWRS | RSR_BMRS | \
RSR_SRS | RSR_HRS))
/*
* RMR - Reset Mode Register
*/
/* checkstop reset enable */
#define RMR_CSRE 0x00000001
#define RMR_CSRE_SHIFT 0
#define RMR_RES ~(RMR_CSRE)
/*
* RCR - Reset Control Register
*/
/* software hard reset */
#define RCR_SWHR 0x00000002
/* software soft reset */
#define RCR_SWSR 0x00000001
#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
/*
* RCER - Reset Control Enable Register
*/
/* software hard reset */
#define RCER_CRE 0x00000001
#define RCER_RES ~(RCER_CRE)
/*
* SPMR - System PLL Mode Register
*/
#define SPMR_LBIUCM 0x80000000
#define SPMR_LBIUCM_SHIFT 31
#define SPMR_DDRCM 0x40000000
#define SPMR_DDRCM_SHIFT 30
#define SPMR_SPMF 0x0F000000
#define SPMR_SPMF_SHIFT 24
#define SPMR_CKID 0x00800000
#define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000
#define SPMR_COREPLL_SHIFT 16
#define SPMR_CEVCOD 0x000000C0
#define SPMR_CEVCOD_SHIFT 6
#define SPMR_CEPDF 0x00000020
#define SPMR_CEPDF_SHIFT 5
#define SPMR_CEPMF 0x0000001F
#define SPMR_CEPMF_SHIFT 0
/*
* OCCR - Output Clock Control Register
*/
#define OCCR_PCICOE0 0x80000000
#define OCCR_PCICOE1 0x40000000
#define OCCR_PCICOE2 0x20000000
#define OCCR_PCICOE3 0x10000000
#define OCCR_PCICOE4 0x08000000
#define OCCR_PCICOE5 0x04000000
#define OCCR_PCICOE6 0x02000000
#define OCCR_PCICOE7 0x01000000
#define OCCR_PCICD0 0x00800000
#define OCCR_PCICD1 0x00400000
#define OCCR_PCICD2 0x00200000
#define OCCR_PCICD3 0x00100000
#define OCCR_PCICD4 0x00080000
#define OCCR_PCICD5 0x00040000
#define OCCR_PCICD6 0x00020000
#define OCCR_PCICD7 0x00010000
#define OCCR_PCI1CR 0x00000002
#define OCCR_PCI2CR 0x00000001
#define OCCR_PCICR OCCR_PCI1CR
/*
* SCCR - System Clock Control Register
*/
#define SCCR_ENCCM 0x03000000
#define SCCR_ENCCM_SHIFT 24
#define SCCR_ENCCM_0 0x00000000
#define SCCR_ENCCM_1 0x01000000
#define SCCR_ENCCM_2 0x02000000
#define SCCR_ENCCM_3 0x03000000
#define SCCR_PCICM 0x00010000
#define SCCR_PCICM_SHIFT 16
#if defined(CONFIG_MPC834x)
/* SCCR bits - MPC834x specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_TSEC1CM_1 0x40000000
#define SCCR_TSEC1CM_2 0x80000000
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC2CM 0x30000000
#define SCCR_TSEC2CM_SHIFT 28
#define SCCR_TSEC2CM_0 0x00000000
#define SCCR_TSEC2CM_1 0x10000000
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
/* The MPH must have the same clock ratio as DR, unless its clock disabled */
#define SCCR_USBMPHCM 0x00c00000
#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM 0x00300000
#define SCCR_USBDRCM_SHIFT 20
#define SCCR_USBCM 0x00f00000
#define SCCR_USBCM_SHIFT 20
#define SCCR_USBCM_0 0x00000000
#define SCCR_USBCM_1 0x00500000
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
#elif defined(CONFIG_MPC8313)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_TSEC1CM_1 0x40000000
#define SCCR_TSEC1CM_2 0x80000000
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC1ON 0x20000000
#define SCCR_TSEC1ON_SHIFT 29
#define SCCR_TSEC2ON 0x10000000
#define SCCR_TSEC2ON_SHIFT 28
#define SCCR_USBDRCM 0x00300000
#define SCCR_USBDRCM_SHIFT 20
#define SCCR_USBDRCM_0 0x00000000
#define SCCR_USBDRCM_1 0x00100000
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_TSEC1CM_1 0x40000000
#define SCCR_TSEC1CM_2 0x80000000
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC2CM 0x30000000
#define SCCR_TSEC2CM_SHIFT 28
#define SCCR_TSEC2CM_0 0x00000000
#define SCCR_TSEC2CM_1 0x10000000
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
#define SCCR_SDHCCM 0x0c000000
#define SCCR_SDHCCM_SHIFT 26
#define SCCR_SDHCCM_0 0x00000000
#define SCCR_SDHCCM_1 0x04000000
#define SCCR_SDHCCM_2 0x08000000
#define SCCR_SDHCCM_3 0x0c000000
#define SCCR_USBDRCM 0x00c00000
#define SCCR_USBDRCM_SHIFT 22
#define SCCR_USBDRCM_0 0x00000000
#define SCCR_USBDRCM_1 0x00400000
#define SCCR_USBDRCM_2 0x00800000
#define SCCR_USBDRCM_3 0x00c00000
#define SCCR_SATA1CM 0x00003000
#define SCCR_SATA1CM_SHIFT 12
#define SCCR_SATACM 0x00003c00
#define SCCR_SATACM_SHIFT 10
#define SCCR_SATACM_0 0x00000000
#define SCCR_SATACM_1 0x00001400
#define SCCR_SATACM_2 0x00002800
#define SCCR_SATACM_3 0x00003c00
#define SCCR_TDMCM 0x00000030
#define SCCR_TDMCM_SHIFT 4
#define SCCR_TDMCM_0 0x00000000
#define SCCR_TDMCM_1 0x00000010
#define SCCR_TDMCM_2 0x00000020
#define SCCR_TDMCM_3 0x00000030
#elif defined(CONFIG_MPC837x)
/* SCCR bits - MPC837x specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_TSEC1CM_1 0x40000000
#define SCCR_TSEC1CM_2 0x80000000
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC2CM 0x30000000
#define SCCR_TSEC2CM_SHIFT 28
#define SCCR_TSEC2CM_0 0x00000000
#define SCCR_TSEC2CM_1 0x10000000
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
#define SCCR_SDHCCM 0x0c000000
#define SCCR_SDHCCM_SHIFT 26
#define SCCR_SDHCCM_0 0x00000000
#define SCCR_SDHCCM_1 0x04000000
#define SCCR_SDHCCM_2 0x08000000
#define SCCR_SDHCCM_3 0x0c000000
#define SCCR_USBDRCM 0x00c00000
#define SCCR_USBDRCM_SHIFT 22
#define SCCR_USBDRCM_0 0x00000000
#define SCCR_USBDRCM_1 0x00400000
#define SCCR_USBDRCM_2 0x00800000
#define SCCR_USBDRCM_3 0x00c00000
/* All of the four SATA controllers must have the same clock ratio */
#define SCCR_SATA1CM 0x000000c0
#define SCCR_SATA1CM_SHIFT 6
#define SCCR_SATACM 0x000000ff
#define SCCR_SATACM_SHIFT 0
#define SCCR_SATACM_0 0x00000000
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
#endif
#define SCCR_PCIEXP1CM 0x00300000
#define SCCR_PCIEXP1CM_SHIFT 20
#define SCCR_PCIEXP1CM_0 0x00000000
#define SCCR_PCIEXP1CM_1 0x00100000
#define SCCR_PCIEXP1CM_2 0x00200000
#define SCCR_PCIEXP1CM_3 0x00300000
#define SCCR_PCIEXP2CM 0x000c0000
#define SCCR_PCIEXP2CM_SHIFT 18
#define SCCR_PCIEXP2CM_0 0x00000000
#define SCCR_PCIEXP2CM_1 0x00040000
#define SCCR_PCIEXP2CM_2 0x00080000
#define SCCR_PCIEXP2CM_3 0x000c0000
/*
* CSn_BDNS - Chip Select memory Bounds Register
*/
#define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT 8
#define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT 24
/*
* CSn_CONFIG - Chip Select Configuration Register
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define CSCONFIG_ODT_RD_ALL 0x00400000
#define CSCONFIG_ODT_WR_NEVER 0x00000000
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ALL 0x00040000
#elif defined(CONFIG_MPC832x)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
#define CSCONFIG_ODT_RD_ALL 0x00400000
#define CSCONFIG_ODT_WR_NEVER 0x00000000
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
#define CSCONFIG_ODT_WR_ALL 0x00040000
#endif
#define CSCONFIG_BANK_BIT_3 0x00004000
#define CSCONFIG_ROW_BIT 0x00000700
#define CSCONFIG_ROW_BIT_12 0x00000000
#define CSCONFIG_ROW_BIT_13 0x00000100
#define CSCONFIG_ROW_BIT_14 0x00000200
#define CSCONFIG_COL_BIT 0x00000007
#define CSCONFIG_COL_BIT_8 0x00000000
#define CSCONFIG_COL_BIT_9 0x00000001
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
/*
* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
*/
#define TIMING_CFG0_RWT 0xC0000000
#define TIMING_CFG0_RWT_SHIFT 30
#define TIMING_CFG0_WRT 0x30000000
#define TIMING_CFG0_WRT_SHIFT 28
#define TIMING_CFG0_RRT 0x0C000000
#define TIMING_CFG0_RRT_SHIFT 26
#define TIMING_CFG0_WWT 0x03000000
#define TIMING_CFG0_WWT_SHIFT 24
#define TIMING_CFG0_ACT_PD_EXIT 0x00700000
#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
#define TIMING_CFG0_PRE_PD_EXIT 0x00070000
#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
#define TIMING_CFG0_MRS_CYC 0x0000000F
#define TIMING_CFG0_MRS_CYC_SHIFT 0
/*
* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
*/
#define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT 28
#define TIMING_CFG1_ACTTOPRE 0x0F000000
#define TIMING_CFG1_ACTTOPRE_SHIFT 24
#define TIMING_CFG1_ACTTORW 0x00700000
#define TIMING_CFG1_ACTTORW_SHIFT 20
#define TIMING_CFG1_CASLAT 0x00070000
#define TIMING_CFG1_CASLAT_SHIFT 16
#define TIMING_CFG1_REFREC 0x0000F000
#define TIMING_CFG1_REFREC_SHIFT 12
#define TIMING_CFG1_WRREC 0x00000700
#define TIMING_CFG1_WRREC_SHIFT 8
#define TIMING_CFG1_ACTTOACT 0x00000070
#define TIMING_CFG1_ACTTOACT_SHIFT 4
#define TIMING_CFG1_WRTORD 0x00000007
#define TIMING_CFG1_WRTORD_SHIFT 0
#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
/*
* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
*/
#define TIMING_CFG2_CPO 0x0F800000
#define TIMING_CFG2_CPO_SHIFT 23
#define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
/* default (= CASLAT + 1) */
#define TIMING_CFG2_CPO_DEF 0x00000000
#define TIMING_CFG2_ADD_LAT 0x70000000
#define TIMING_CFG2_ADD_LAT_SHIFT 28
#define TIMING_CFG2_WR_LAT_DELAY 0x00380000
#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
#define TIMING_CFG2_RD_TO_PRE 0x0000E000
#define TIMING_CFG2_RD_TO_PRE_SHIFT 13
#define TIMING_CFG2_CKE_PLS 0x000001C0
#define TIMING_CFG2_CKE_PLS_SHIFT 6
#define TIMING_CFG2_FOUR_ACT 0x0000003F
#define TIMING_CFG2_FOUR_ACT_SHIFT 0
/*
* TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
*/
#define TIMING_CFG3_EXT_REFREC 0x00070000
#define TIMING_CFG3_EXT_REFREC_SHIFT 16
/*
* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000
#else
#define SDRAM_CFG_32_BE 0x00080000
#endif
#if !defined(CONFIG_MPC8308)
#define SDRAM_CFG_8_BE 0x00040000
#endif
#define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_HSE 0x00000008
#define SDRAM_CFG_BI 0x00000001
/*
* DDR_SDRAM_MODE - DDR SDRAM Mode Register
*/
#define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0
/* select extended mode reg */
#define DDR_MODE_EXT_MODEREG 0x4000
/* operating mode, mask */
#define DDR_MODE_EXT_OPMODE 0x3FF8
#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
/* QFC / compatibility, mask */
#define DDR_MODE_QFC 0x0004
/* compatible to older SDRAMs */
#define DDR_MODE_QFC_COMP 0x0000
/* weak drivers */
#define DDR_MODE_WEAK 0x0002
/* disable DLL */
#define DDR_MODE_DLL_DIS 0x0001
/* CAS latency, mask */
#define DDR_MODE_CASLAT 0x0070
#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
/* sequential burst */
#define DDR_MODE_BTYPE_SEQ 0x0000
/* interleaved burst */
#define DDR_MODE_BTYPE_ILVD 0x0008
#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
/* exact value for 7.8125us */
#define DDR_REFINT_166MHZ_7US 1302
/* use 256 cycles as a starting point */
#define DDR_BSTOPRE 256
/* select mode register */
#define DDR_MODE_MODEREG 0x0000
/*
* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
*/
#define SDRAM_INTERVAL_REFINT 0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT 16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
/*
* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
*/
#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
/*
* ECC_ERR_INJECT - Memory data path error injection mask ECC
*/
/* ECC Mirror Byte */
#define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
/* Error Injection Enable */
#define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
/* ECC Erroe Injection Enable */
#define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
#define ECC_ERR_INJECT_EEIM_SHIFT 0
/*
* CAPTURE_ECC - Memory data path read capture ECC
*/
#define CAPTURE_ECC_ECE (0xff000000 >> 24)
#define CAPTURE_ECC_ECE_SHIFT 0
/*
* ERR_DETECT - Memory error detect
*/
/* Multiple Memory Errors */
#define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
/* Multiple-Bit Error */
#define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
/* Single-Bit ECC Error Pickup */
#define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
/* Memory Select Error */
#define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
/*
* ERR_DISABLE - Memory error disable
*/
/* Multiple-Bit ECC Error Disable */
#define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
/* Sinle-Bit ECC Error disable */
#define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
/* Memory Select Error Disable */
#define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
#define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
ECC_ERROR_DISABLE_SBED | \
ECC_ERROR_DISABLE_MBED))
/*
* ERR_INT_EN - Memory error interrupt enable
*/
/* Multiple-Bit ECC Error Interrupt Enable */
#define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
/* Single-Bit ECC Error Interrupt Enable */
#define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
/* Memory Select Error Interrupt Enable */
#define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
#define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
ECC_ERR_INT_EN_SBEE | \
ECC_ERR_INT_EN_MSEE))
/*
* CAPTURE_ATTRIBUTES - Memory error attributes capture
*/
/* Data Beat Num */
#define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
#define ECC_CAPT_ATTR_BNUM_SHIFT 28
/* Transaction Size */
#define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
/* Transaction Source */
#define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
#define ECC_CAPT_ATTR_TSRC_I2C 0x9
#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
#define ECC_CAPT_ATTR_TSRC_DMA 0xF
#define ECC_CAPT_ATTR_TSRC_SHIFT 16
/* Transaction Type */
#define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
#define ECC_CAPT_ATTR_TTYP_READ 0x2
#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
#define ECC_CAPT_ATTR_TTYP_SHIFT 12
#define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
/*
* ERR_SBE - Single bit ECC memory error management
*/
/* Single-Bit Error Threshold 0..255 */
#define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
#define ECC_ERROR_MAN_SBET_SHIFT 16
/* Single Bit Error Counter 0..255 */
#define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
#define ECC_ERROR_MAN_SBEC_SHIFT 0
/*
* CONFIG_ADDRESS - PCI Config Address Register
*/
#define PCI_CONFIG_ADDRESS_EN 0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
/*
* POTAR - PCI Outbound Translation Address Register
*/
#define POTAR_TA_MASK 0x000fffff
/*
* POBAR - PCI Outbound Base Address Register
*/
#define POBAR_BA_MASK 0x000fffff
/*
* POCMR - PCI Outbound Comparision Mask Register
*/
#define POCMR_EN 0x80000000
/* 0-memory space 1-I/O space */
#define POCMR_IO 0x40000000
#define POCMR_SE 0x20000000 /* streaming enable */
#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
#define POCMR_CM_MASK 0x000fffff
#define POCMR_CM_4G 0x00000000
#define POCMR_CM_2G 0x00080000
#define POCMR_CM_1G 0x000C0000
#define POCMR_CM_512M 0x000E0000
#define POCMR_CM_256M 0x000F0000
#define POCMR_CM_128M 0x000F8000
#define POCMR_CM_64M 0x000FC000
#define POCMR_CM_32M 0x000FE000
#define POCMR_CM_16M 0x000FF000
#define POCMR_CM_8M 0x000FF800
#define POCMR_CM_4M 0x000FFC00
#define POCMR_CM_2M 0x000FFE00
#define POCMR_CM_1M 0x000FFF00
#define POCMR_CM_512K 0x000FFF80
#define POCMR_CM_256K 0x000FFFC0
#define POCMR_CM_128K 0x000FFFE0
#define POCMR_CM_64K 0x000FFFF0
#define POCMR_CM_32K 0x000FFFF8
#define POCMR_CM_16K 0x000FFFFC
#define POCMR_CM_8K 0x000FFFFE
#define POCMR_CM_4K 0x000FFFFF
/*
* PITAR - PCI Inbound Translation Address Register
*/
#define PITAR_TA_MASK 0x000fffff
/*
* PIBAR - PCI Inbound Base/Extended Address Register
*/
#define PIBAR_MASK 0xffffffff
#define PIEBAR_EBA_MASK 0x000fffff
/*
* PIWAR - PCI Inbound Windows Attributes Register
*/
#define PIWAR_EN 0x80000000
#define PIWAR_PF 0x20000000
#define PIWAR_RTT_MASK 0x000f0000
#define PIWAR_RTT_NO_SNOOP 0x00040000
#define PIWAR_RTT_SNOOP 0x00050000
#define PIWAR_WTT_MASK 0x0000f000
#define PIWAR_WTT_NO_SNOOP 0x00004000
#define PIWAR_WTT_SNOOP 0x00005000
#define PIWAR_IWS_MASK 0x0000003F
#define PIWAR_IWS_4K 0x0000000B
#define PIWAR_IWS_8K 0x0000000C
#define PIWAR_IWS_16K 0x0000000D
#define PIWAR_IWS_32K 0x0000000E
#define PIWAR_IWS_64K 0x0000000F
#define PIWAR_IWS_128K 0x00000010
#define PIWAR_IWS_256K 0x00000011
#define PIWAR_IWS_512K 0x00000012
#define PIWAR_IWS_1M 0x00000013
#define PIWAR_IWS_2M 0x00000014
#define PIWAR_IWS_4M 0x00000015
#define PIWAR_IWS_8M 0x00000016
#define PIWAR_IWS_16M 0x00000017
#define PIWAR_IWS_32M 0x00000018
#define PIWAR_IWS_64M 0x00000019
#define PIWAR_IWS_128M 0x0000001A
#define PIWAR_IWS_256M 0x0000001B
#define PIWAR_IWS_512M 0x0000001C
#define PIWAR_IWS_1G 0x0000001D
#define PIWAR_IWS_2G 0x0000001E
/*
* PMCCR1 - PCI Configuration Register 1
*/
#define PMCCR1_POWER_OFF 0x00000020
/*
* DDRCDR - DDR Control Driver Register
*/
#define DDRCDR_DHC_EN 0x80000000
#define DDRCDR_EN 0x40000000
#define DDRCDR_PZ 0x3C000000
#define DDRCDR_PZ_MAXZ 0x00000000
#define DDRCDR_PZ_HIZ 0x20000000
#define DDRCDR_PZ_NOMZ 0x30000000
#define DDRCDR_PZ_LOZ 0x38000000
#define DDRCDR_PZ_MINZ 0x3C000000
#define DDRCDR_NZ 0x3C000000
#define DDRCDR_NZ_MAXZ 0x00000000
#define DDRCDR_NZ_HIZ 0x02000000
#define DDRCDR_NZ_NOMZ 0x03000000
#define DDRCDR_NZ_LOZ 0x03800000
#define DDRCDR_NZ_MINZ 0x03C00000
#define DDRCDR_ODT 0x00080000
#define DDRCDR_DDR_CFG 0x00040000
#define DDRCDR_M_ODR 0x00000002
#define DDRCDR_Q_DRN 0x00000001
/*
* PCIE Bridge Register
*/
#define PEX_CSB_CTRL_OBPIOE 0x00000001
#define PEX_CSB_CTRL_IBPIOE 0x00000002
#define PEX_CSB_CTRL_WDMAE 0x00000004
#define PEX_CSB_CTRL_RDMAE 0x00000008
#define PEX_CSB_OBCTRL_PIOE 0x00000001
#define PEX_CSB_OBCTRL_MEMWE 0x00000002
#define PEX_CSB_OBCTRL_IOWE 0x00000004
#define PEX_CSB_OBCTRL_CFGWE 0x00000008
#define PEX_CSB_IBCTRL_PIOE 0x00000001
#define PEX_OWAR_EN 0x00000001
#define PEX_OWAR_TYPE_CFG 0x00000000
#define PEX_OWAR_TYPE_IO 0x00000002
#define PEX_OWAR_TYPE_MEM 0x00000004
#define PEX_OWAR_RLXO 0x00000008
#define PEX_OWAR_NANP 0x00000010
#define PEX_OWAR_SIZE 0xFFFFF000
#define PEX_IWAR_EN 0x00000001
#define PEX_IWAR_TYPE_INT 0x00000000
#define PEX_IWAR_TYPE_PF 0x00000004
#define PEX_IWAR_TYPE_NO_PF 0x00000006
#define PEX_IWAR_NSOV 0x00000008
#define PEX_IWAR_NSNP 0x00000010
#define PEX_IWAR_SIZE 0xFFFFF000
#define PEX_IWAR_SIZE_1M 0x000FF000
#define PEX_IWAR_SIZE_2M 0x001FF000
#define PEX_IWAR_SIZE_4M 0x003FF000
#define PEX_IWAR_SIZE_8M 0x007FF000
#define PEX_IWAR_SIZE_16M 0x00FFF000
#define PEX_IWAR_SIZE_32M 0x01FFF000
#define PEX_IWAR_SIZE_64M 0x03FFF000
#define PEX_IWAR_SIZE_128M 0x07FFF000
#define PEX_IWAR_SIZE_256M 0x0FFFF000
#define PEX_GCLK_RATIO 0x440
#ifndef __ASSEMBLY__
struct pci_region;
void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
void mpc83xx_pcislave_unlock(int bus);
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
#endif
#endif /* __MPC83XX_H__ */
|
1001-study-uboot
|
include/mpc83xx.h
|
C
|
gpl3
| 44,912
|
/*
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* The original I2C interface was
* (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
* AIRVENT SAM s.p.a - RIMINI(ITALY)
* but has been changed substantially.
*/
#ifndef _I2C_H_
#define _I2C_H_
/*
* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
*
* The implementation MUST NOT use static or global variables if the
* I2C routines are used to read SDRAM configuration information
* because this is done before the memories are initialized. Limited
* use of stack-based variables are OK (the initial stack size is
* limited).
*
* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
*/
/*
* Configuration items.
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
#ifdef CONFIG_I2C_MULTI_BUS
#define MAX_I2C_BUS 2
#define I2C_MULTI_BUS 1
#else
#define MAX_I2C_BUS 1
#define I2C_MULTI_BUS 0
#endif
#if !defined(CONFIG_SYS_MAX_I2C_BUS)
#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS
#endif
/* define the I2C bus number for RTC and DTT if not already done */
#if !defined(CONFIG_SYS_RTC_BUS_NUM)
#define CONFIG_SYS_RTC_BUS_NUM 0
#endif
#if !defined(CONFIG_SYS_DTT_BUS_NUM)
#define CONFIG_SYS_DTT_BUS_NUM 0
#endif
#if !defined(CONFIG_SYS_SPD_BUS_NUM)
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
#ifndef I2C_SOFT_DECLARATIONS
# if defined(CONFIG_MPC8260)
# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
# elif defined(CONFIG_8xx)
# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
# elif (defined(CONFIG_AT91RM9200) || \
defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
# else
# define I2C_SOFT_DECLARATIONS
# endif
#endif
#ifdef CONFIG_8xx
/* Set default value for the I2C bus speed on 8xx. In the
* future, we'll define these in all 8xx board config files.
*/
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 50000
#endif
#endif
/*
* Many boards/controllers/drivers don't support an I2C slave interface so
* provide a default slave address for them for use in common code. A real
* value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
* support a slave interface.
*/
#ifndef CONFIG_SYS_I2C_SLAVE
#define CONFIG_SYS_I2C_SLAVE 0xfe
#endif
/*
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
*/
void i2c_init(int speed, int slaveaddr);
void i2c_init_board(void);
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
void i2c_board_late_init(void);
#endif
#if defined(CONFIG_I2C_MUX)
typedef struct _mux {
uchar chip;
uchar channel;
char *name;
struct _mux *next;
} I2C_MUX;
typedef struct _mux_device {
int busid;
I2C_MUX *mux; /* List of muxes, to reach the device */
struct _mux_device *next;
} I2C_MUX_DEVICE;
I2C_MUX_DEVICE *i2c_mux_search_device(int id);
I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
int i2x_mux_select_mux(int bus);
int i2c_mux_ident_muxstring_f (uchar *buf);
#endif
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
* not 0 on failure.
*/
int i2c_probe(uchar chip);
/*
* Read/Write interface:
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
/*
* Utility routines to read/write registers.
*/
static inline u8 i2c_reg_read(u8 addr, u8 reg)
{
u8 buf;
#ifdef CONFIG_8xx
/* MPC8xx needs this. Maybe one day we can get rid of it. */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#ifdef DEBUG
printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
#endif
i2c_read(addr, reg, 1, &buf, 1);
return buf;
}
static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
{
#ifdef CONFIG_8xx
/* MPC8xx needs this. Maybe one day we can get rid of it. */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
#ifdef DEBUG
printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
__func__, addr, reg, val);
#endif
i2c_write(addr, reg, 1, &val, 1);
}
/*
* Functions for setting the current I2C bus and its speed
*/
/*
* i2c_set_bus_num:
*
* Change the active I2C bus. Subsequent read/write calls will
* go to this one.
*
* bus - bus index, zero based
*
* Returns: 0 on success, not 0 on failure
*
*/
int i2c_set_bus_num(unsigned int bus);
/*
* i2c_get_bus_num:
*
* Returns index of currently active I2C bus. Zero-based.
*/
unsigned int i2c_get_bus_num(void);
/*
* i2c_set_bus_speed:
*
* Change the speed of the active I2C bus
*
* speed - bus speed in Hz
*
* Returns: 0 on success, not 0 on failure
*
*/
int i2c_set_bus_speed(unsigned int);
/*
* i2c_get_bus_speed:
*
* Returns speed of currently active I2C bus in Hz
*/
unsigned int i2c_get_bus_speed(void);
/* NOTE: These two functions MUST be always_inline to avoid code growth! */
static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
static inline unsigned int I2C_GET_BUS(void)
{
return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
}
static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
static inline void I2C_SET_BUS(unsigned int bus)
{
if (I2C_MULTI_BUS)
i2c_set_bus_num(bus);
}
#endif /* _I2C_H_ */
|
1001-study-uboot
|
include/i2c.h
|
C
|
gpl3
| 6,644
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <fpga.h>
#ifndef _XILINX_H_
#define _XILINX_H_
/* Xilinx Model definitions
*********************************************************************/
#define CONFIG_SYS_SPARTAN2 CONFIG_SYS_FPGA_DEV( 0x1 )
#define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 )
#define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 )
#define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 )
#define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
#define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
#define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
#define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
/* XXX - Add new models here */
/* Xilinx Interface definitions
*********************************************************************/
#define CONFIG_SYS_XILINX_IF_SS CONFIG_SYS_FPGA_IF( 0x1 ) /* slave serial */
#define CONFIG_SYS_XILINX_IF_MS CONFIG_SYS_FPGA_IF( 0x2 ) /* master serial */
#define CONFIG_SYS_XILINX_IF_SP CONFIG_SYS_FPGA_IF( 0x4 ) /* slave parallel */
#define CONFIG_SYS_XILINX_IF_JTAG CONFIG_SYS_FPGA_IF( 0x8 ) /* jtag */
#define CONFIG_SYS_XILINX_IF_MSM CONFIG_SYS_FPGA_IF( 0x10 ) /* master selectmap */
#define CONFIG_SYS_XILINX_IF_SSM CONFIG_SYS_FPGA_IF( 0x20 ) /* slave selectmap */
/* Xilinx types
*********************************************************************/
typedef enum { /* typedef Xilinx_iface */
min_xilinx_iface_type, /* low range check value */
slave_serial, /* serial data and external clock */
master_serial, /* serial data w/ internal clock (not used) */
slave_parallel, /* parallel data w/ external latch */
jtag_mode, /* jtag/tap serial (not used ) */
master_selectmap, /* master SelectMap (virtex2) */
slave_selectmap, /* slave SelectMap (virtex2) */
max_xilinx_iface_type /* insert all new types before this */
} Xilinx_iface; /* end, typedef Xilinx_iface */
typedef enum { /* typedef Xilinx_Family */
min_xilinx_type, /* low range check value */
Xilinx_Spartan2, /* Spartan-II Family */
Xilinx_VirtexE, /* Virtex-E Family */
Xilinx_Virtex2, /* Virtex2 Family */
Xilinx_Spartan3, /* Spartan-III Family */
max_xilinx_type /* insert all new types before this */
} Xilinx_Family; /* end, typedef Xilinx_Family */
typedef struct { /* typedef Xilinx_desc */
Xilinx_Family family; /* part type */
Xilinx_iface iface; /* interface type */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
int cookie; /* implementation specific cookie */
} Xilinx_desc; /* end, typedef Xilinx_desc */
/* Generic Xilinx Functions
*********************************************************************/
extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size);
extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
extern int xilinx_info(Xilinx_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie );
typedef int (*Xilinx_init_fn)( int cookie );
typedef int (*Xilinx_err_fn)( int cookie );
typedef int (*Xilinx_done_fn)( int cookie );
typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie );
typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie );
typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie );
typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie );
typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie );
typedef int (*Xilinx_busy_fn)( int cookie );
typedef int (*Xilinx_abort_fn)( int cookie );
typedef int (*Xilinx_pre_fn)( int cookie );
typedef int (*Xilinx_post_fn)( int cookie );
typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
#endif /* _XILINX_H_ */
|
1001-study-uboot
|
include/xilinx.h
|
C
|
gpl3
| 4,808
|
#ifndef _LIBFDT_H
#define _LIBFDT_H
/*
* libfdt - Flat Device Tree manipulation
* Copyright (C) 2006 David Gibson, IBM Corporation.
*
* libfdt is dual licensed: you can use it either under the terms of
* the GPL, or the BSD license, at your option.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this library; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Alternatively,
*
* b) Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* 1. Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <libfdt_env.h>
#include <fdt.h>
#define FDT_FIRST_SUPPORTED_VERSION 0x10
#define FDT_LAST_SUPPORTED_VERSION 0x11
/* Error codes: informative error codes */
#define FDT_ERR_NOTFOUND 1
/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
#define FDT_ERR_EXISTS 2
/* FDT_ERR_EXISTS: Attemped to create a node or property which
* already exists */
#define FDT_ERR_NOSPACE 3
/* FDT_ERR_NOSPACE: Operation needed to expand the device
* tree, but its buffer did not have sufficient space to
* contain the expanded tree. Use fdt_open_into() to move the
* device tree to a buffer with more space. */
/* Error codes: codes for bad parameters */
#define FDT_ERR_BADOFFSET 4
/* FDT_ERR_BADOFFSET: Function was passed a structure block
* offset which is out-of-bounds, or which points to an
* unsuitable part of the structure for the operation. */
#define FDT_ERR_BADPATH 5
/* FDT_ERR_BADPATH: Function was passed a badly formatted path
* (e.g. missing a leading / for a function which requires an
* absolute path) */
#define FDT_ERR_BADPHANDLE 6
/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
* value. phandle values of 0 and -1 are not permitted. */
#define FDT_ERR_BADSTATE 7
/* FDT_ERR_BADSTATE: Function was passed an incomplete device
* tree created by the sequential-write functions, which is
* not sufficiently complete for the requested operation. */
/* Error codes: codes for bad device tree blobs */
#define FDT_ERR_TRUNCATED 8
/* FDT_ERR_TRUNCATED: Structure block of the given device tree
* ends without an FDT_END tag. */
#define FDT_ERR_BADMAGIC 9
/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
* device tree at all - it is missing the flattened device
* tree magic number. */
#define FDT_ERR_BADVERSION 10
/* FDT_ERR_BADVERSION: Given device tree has a version which
* can't be handled by the requested operation. For
* read-write functions, this may mean that fdt_open_into() is
* required to convert the tree to the expected version. */
#define FDT_ERR_BADSTRUCTURE 11
/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
* structure block or other serious error (e.g. misnested
* nodes, or subnodes preceding properties). */
#define FDT_ERR_BADLAYOUT 12
/* FDT_ERR_BADLAYOUT: For read-write functions, the given
* device tree has it's sub-blocks in an order that the
* function can't handle (memory reserve map, then structure,
* then strings). Use fdt_open_into() to reorganize the tree
* into a form suitable for the read-write operations. */
/* "Can't happen" error indicating a bug in libfdt */
#define FDT_ERR_INTERNAL 13
/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
* Should never be returned, if it is, it indicates a bug in
* libfdt itself. */
#define FDT_ERR_MAX 13
/**********************************************************************/
/* Low-level functions (you probably don't need these) */
/**********************************************************************/
const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
{
return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
}
uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
/**********************************************************************/
/* Traversal functions */
/**********************************************************************/
int fdt_next_node(const void *fdt, int offset, int *depth);
/**********************************************************************/
/* General functions */
/**********************************************************************/
#define fdt_get_header(fdt, field) \
(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
#define fdt_magic(fdt) (fdt_get_header(fdt, magic))
#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize))
#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct))
#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings))
#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap))
#define fdt_version(fdt) (fdt_get_header(fdt, version))
#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version))
#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys))
#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings))
#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct))
#define __fdt_set_hdr(name) \
static inline void fdt_set_##name(void *fdt, uint32_t val) \
{ \
struct fdt_header *fdth = (struct fdt_header*)fdt; \
fdth->name = cpu_to_fdt32(val); \
}
__fdt_set_hdr(magic);
__fdt_set_hdr(totalsize);
__fdt_set_hdr(off_dt_struct);
__fdt_set_hdr(off_dt_strings);
__fdt_set_hdr(off_mem_rsvmap);
__fdt_set_hdr(version);
__fdt_set_hdr(last_comp_version);
__fdt_set_hdr(boot_cpuid_phys);
__fdt_set_hdr(size_dt_strings);
__fdt_set_hdr(size_dt_struct);
#undef __fdt_set_hdr
/**
* fdt_check_header - sanity check a device tree or possible device tree
* @fdt: pointer to data which might be a flattened device tree
*
* fdt_check_header() checks that the given buffer contains what
* appears to be a flattened device tree with sane information in its
* header.
*
* returns:
* 0, if the buffer appears to contain a valid device tree
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE, standard meanings, as above
*/
int fdt_check_header(const void *fdt);
/**
* fdt_move - move a device tree around in memory
* @fdt: pointer to the device tree to move
* @buf: pointer to memory where the device is to be moved
* @bufsize: size of the memory space at buf
*
* fdt_move() relocates, if possible, the device tree blob located at
* fdt to the buffer at buf of size bufsize. The buffer may overlap
* with the existing device tree blob at fdt. Therefore,
* fdt_move(fdt, fdt, fdt_totalsize(fdt))
* should always succeed.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE, standard meanings
*/
int fdt_move(const void *fdt, void *buf, int bufsize);
/**********************************************************************/
/* Read-only functions */
/**********************************************************************/
/**
* fdt_string - retrieve a string from the strings block of a device tree
* @fdt: pointer to the device tree blob
* @stroffset: offset of the string within the strings block (native endian)
*
* fdt_string() retrieves a pointer to a single string from the
* strings block of the device tree blob at fdt.
*
* returns:
* a pointer to the string, on success
* NULL, if stroffset is out of bounds
*/
const char *fdt_string(const void *fdt, int stroffset);
/**
* fdt_num_mem_rsv - retrieve the number of memory reserve map entries
* @fdt: pointer to the device tree blob
*
* Returns the number of entries in the device tree blob's memory
* reservation map. This does not include the terminating 0,0 entry
* or any other (0,0) entries reserved for expansion.
*
* returns:
* the number of entries
*/
int fdt_num_mem_rsv(const void *fdt);
/**
* fdt_get_mem_rsv - retrieve one memory reserve map entry
* @fdt: pointer to the device tree blob
* @address, @size: pointers to 64-bit variables
*
* On success, *address and *size will contain the address and size of
* the n-th reserve map entry from the device tree blob, in
* native-endian format.
*
* returns:
* 0, on success
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE, standard meanings
*/
int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
/**
* fdt_subnode_offset_namelen - find a subnode based on substring
* @fdt: pointer to the device tree blob
* @parentoffset: structure block offset of a node
* @name: name of the subnode to locate
* @namelen: number of characters of name to consider
*
* Identical to fdt_subnode_offset(), but only examine the first
* namelen characters of name for matching the subnode name. This is
* useful for finding subnodes based on a portion of a larger string,
* such as a full path.
*/
int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
const char *name, int namelen);
/**
* fdt_subnode_offset - find a subnode of a given node
* @fdt: pointer to the device tree blob
* @parentoffset: structure block offset of a node
* @name: name of the subnode to locate
*
* fdt_subnode_offset() finds a subnode of the node at structure block
* offset parentoffset with the given name. name may include a unit
* address, in which case fdt_subnode_offset() will find the subnode
* with that unit address, or the unit address may be omitted, in
* which case fdt_subnode_offset() will find an arbitrary subnode
* whose name excluding unit address matches the given name.
*
* returns:
* structure block offset of the requested subnode (>=0), on success
* -FDT_ERR_NOTFOUND, if the requested subnode does not exist
* -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings.
*/
int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
/**
* fdt_path_offset - find a tree node by its full path
* @fdt: pointer to the device tree blob
* @path: full path of the node to locate
*
* fdt_path_offset() finds a node of a given path in the device tree.
* Each path component may omit the unit address portion, but the
* results of this are undefined if any such path component is
* ambiguous (that is if there are multiple nodes at the relevant
* level matching the given component, differentiated only by unit
* address).
*
* returns:
* structure block offset of the node with the requested path (>=0), on success
* -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
* -FDT_ERR_NOTFOUND, if the requested node does not exist
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings.
*/
int fdt_path_offset(const void *fdt, const char *path);
/**
* fdt_get_name - retrieve the name of a given node
* @fdt: pointer to the device tree blob
* @nodeoffset: structure block offset of the starting node
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* fdt_get_name() retrieves the name (including unit address) of the
* device tree node at structure block offset nodeoffset. If lenp is
* non-NULL, the length of this name is also returned, in the integer
* pointed to by lenp.
*
* returns:
* pointer to the node's name, on success
* If lenp is non-NULL, *lenp contains the length of that name (>=0)
* NULL, on error
* if lenp is non-NULL *lenp contains an error code (<0):
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE, standard meanings
*/
const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
/**
* fdt_first_property_offset - find the offset of a node's first property
* @fdt: pointer to the device tree blob
* @nodeoffset: structure block offset of a node
*
* fdt_first_property_offset() finds the first property of the node at
* the given structure block offset.
*
* returns:
* structure block offset of the property (>=0), on success
* -FDT_ERR_NOTFOUND, if the requested node has no properties
* -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings.
*/
int fdt_first_property_offset(const void *fdt, int nodeoffset);
/**
* fdt_next_property_offset - step through a node's properties
* @fdt: pointer to the device tree blob
* @offset: structure block offset of a property
*
* fdt_next_property_offset() finds the property immediately after the
* one at the given structure block offset. This will be a property
* of the same node as the given property.
*
* returns:
* structure block offset of the next property (>=0), on success
* -FDT_ERR_NOTFOUND, if the given property is the last in its node
* -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings.
*/
int fdt_next_property_offset(const void *fdt, int offset);
/**
* fdt_get_property_by_offset - retrieve the property at a given offset
* @fdt: pointer to the device tree blob
* @offset: offset of the property to retrieve
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* fdt_get_property_by_offset() retrieves a pointer to the
* fdt_property structure within the device tree blob at the given
* offset. If lenp is non-NULL, the length of the property value is
* also returned, in the integer pointed to by lenp.
*
* returns:
* pointer to the structure representing the property
* if lenp is non-NULL, *lenp contains the length of the property
* value (>=0)
* NULL, on error
* if lenp is non-NULL, *lenp contains an error code (<0):
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
int offset,
int *lenp);
/**
* fdt_get_property_namelen - find a property based on substring
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to find
* @name: name of the property to find
* @namelen: number of characters of name to consider
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* Identical to fdt_get_property_namelen(), but only examine the first
* namelen characters of name for matching the property name.
*/
const struct fdt_property *fdt_get_property_namelen(const void *fdt,
int nodeoffset,
const char *name,
int namelen, int *lenp);
/**
* fdt_get_property - find a given property in a given node
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to find
* @name: name of the property to find
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* fdt_get_property() retrieves a pointer to the fdt_property
* structure within the device tree blob corresponding to the property
* named 'name' of the node at offset nodeoffset. If lenp is
* non-NULL, the length of the property value is also returned, in the
* integer pointed to by lenp.
*
* returns:
* pointer to the structure representing the property
* if lenp is non-NULL, *lenp contains the length of the property
* value (>=0)
* NULL, on error
* if lenp is non-NULL, *lenp contains an error code (<0):
* -FDT_ERR_NOTFOUND, node does not have named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
const char *name, int *lenp);
static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
const char *name,
int *lenp)
{
return (struct fdt_property *)(uintptr_t)
fdt_get_property(fdt, nodeoffset, name, lenp);
}
/**
* fdt_getprop_by_offset - retrieve the value of a property at a given offset
* @fdt: pointer to the device tree blob
* @ffset: offset of the property to read
* @namep: pointer to a string variable (will be overwritten) or NULL
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* fdt_getprop_by_offset() retrieves a pointer to the value of the
* property at structure block offset 'offset' (this will be a pointer
* to within the device blob itself, not a copy of the value). If
* lenp is non-NULL, the length of the property value is also
* returned, in the integer pointed to by lenp. If namep is non-NULL,
* the property's namne will also be returned in the char * pointed to
* by namep (this will be a pointer to within the device tree's string
* block, not a new copy of the name).
*
* returns:
* pointer to the property's value
* if lenp is non-NULL, *lenp contains the length of the property
* value (>=0)
* if namep is non-NULL *namep contiains a pointer to the property
* name.
* NULL, on error
* if lenp is non-NULL, *lenp contains an error code (<0):
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
const void *fdt_getprop_by_offset(const void *fdt, int offset,
const char **namep, int *lenp);
/**
* fdt_getprop_namelen - get property value based on substring
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to find
* @name: name of the property to find
* @namelen: number of characters of name to consider
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* Identical to fdt_getprop(), but only examine the first namelen
* characters of name for matching the property name.
*/
const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
const char *name, int namelen, int *lenp);
/**
* fdt_getprop - retrieve the value of a given property
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to find
* @name: name of the property to find
* @lenp: pointer to an integer variable (will be overwritten) or NULL
*
* fdt_getprop() retrieves a pointer to the value of the property
* named 'name' of the node at offset nodeoffset (this will be a
* pointer to within the device blob itself, not a copy of the value).
* If lenp is non-NULL, the length of the property value is also
* returned, in the integer pointed to by lenp.
*
* returns:
* pointer to the property's value
* if lenp is non-NULL, *lenp contains the length of the property
* value (>=0)
* NULL, on error
* if lenp is non-NULL, *lenp contains an error code (<0):
* -FDT_ERR_NOTFOUND, node does not have named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
const void *fdt_getprop(const void *fdt, int nodeoffset,
const char *name, int *lenp);
static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
const char *name, int *lenp)
{
return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
}
/**
* fdt_get_phandle - retrieve the phandle of a given node
* @fdt: pointer to the device tree blob
* @nodeoffset: structure block offset of the node
*
* fdt_get_phandle() retrieves the phandle of the device tree node at
* structure block offset nodeoffset.
*
* returns:
* the phandle of the node at nodeoffset, on success (!= 0, != -1)
* 0, if the node has no phandle, or another error occurs
*/
uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
/**
* fdt_get_alias_namelen - get alias based on substring
* @fdt: pointer to the device tree blob
* @name: name of the alias th look up
* @namelen: number of characters of name to consider
*
* Identical to fdt_get_alias(), but only examine the first namelen
* characters of name for matching the alias name.
*/
const char *fdt_get_alias_namelen(const void *fdt,
const char *name, int namelen);
/**
* fdt_get_alias - retreive the path referenced by a given alias
* @fdt: pointer to the device tree blob
* @name: name of the alias th look up
*
* fdt_get_alias() retrieves the value of a given alias. That is, the
* value of the property named 'name' in the node /aliases.
*
* returns:
* a pointer to the expansion of the alias named 'name', of it exists
* NULL, if the given alias or the /aliases node does not exist
*/
const char *fdt_get_alias(const void *fdt, const char *name);
/**
* fdt_get_path - determine the full path of a node
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose path to find
* @buf: character buffer to contain the returned path (will be overwritten)
* @buflen: size of the character buffer at buf
*
* fdt_get_path() computes the full path of the node at offset
* nodeoffset, and records that path in the buffer at buf.
*
* NOTE: This function is expensive, as it must scan the device tree
* structure from the start to nodeoffset.
*
* returns:
* 0, on success
* buf contains the absolute path of the node at
* nodeoffset, as a NUL-terminated string.
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
* characters and will not fit in the given buffer.
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
/**
* fdt_supernode_atdepth_offset - find a specific ancestor of a node
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose parent to find
* @supernodedepth: depth of the ancestor to find
* @nodedepth: pointer to an integer variable (will be overwritten) or NULL
*
* fdt_supernode_atdepth_offset() finds an ancestor of the given node
* at a specific depth from the root (where the root itself has depth
* 0, its immediate subnodes depth 1 and so forth). So
* fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
* will always return 0, the offset of the root node. If the node at
* nodeoffset has depth D, then:
* fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
* will return nodeoffset itself.
*
* NOTE: This function is expensive, as it must scan the device tree
* structure from the start to nodeoffset.
*
* returns:
* structure block offset of the node at node offset's ancestor
* of depth supernodedepth (>=0), on success
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
int supernodedepth, int *nodedepth);
/**
* fdt_node_depth - find the depth of a given node
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose parent to find
*
* fdt_node_depth() finds the depth of a given node. The root node
* has depth 0, its immediate subnodes depth 1 and so forth.
*
* NOTE: This function is expensive, as it must scan the device tree
* structure from the start to nodeoffset.
*
* returns:
* depth of the node at nodeoffset (>=0), on success
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_node_depth(const void *fdt, int nodeoffset);
/**
* fdt_parent_offset - find the parent of a given node
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose parent to find
*
* fdt_parent_offset() locates the parent node of a given node (that
* is, it finds the offset of the node which contains the node at
* nodeoffset as a subnode).
*
* NOTE: This function is expensive, as it must scan the device tree
* structure from the start to nodeoffset, *twice*.
*
* returns:
* structure block offset of the parent of the node at nodeoffset
* (>=0), on success
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_parent_offset(const void *fdt, int nodeoffset);
/**
* fdt_node_offset_by_prop_value - find nodes with a given property value
* @fdt: pointer to the device tree blob
* @startoffset: only find nodes after this offset
* @propname: property name to check
* @propval: property value to search for
* @proplen: length of the value in propval
*
* fdt_node_offset_by_prop_value() returns the offset of the first
* node after startoffset, which has a property named propname whose
* value is of length proplen and has value equal to propval; or if
* startoffset is -1, the very first such node in the tree.
*
* To iterate through all nodes matching the criterion, the following
* idiom can be used:
* offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
* propval, proplen);
* while (offset != -FDT_ERR_NOTFOUND) {
* ... other code here ...
* offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
* propval, proplen);
* }
*
* Note the -1 in the first call to the function, if 0 is used here
* instead, the function will never locate the root node, even if it
* matches the criterion.
*
* returns:
* structure block offset of the located node (>= 0, >startoffset),
* on success
* -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
* tree after startoffset
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
const char *propname,
const void *propval, int proplen);
/**
* fdt_node_offset_by_phandle - find the node with a given phandle
* @fdt: pointer to the device tree blob
* @phandle: phandle value
*
* fdt_node_offset_by_phandle() returns the offset of the node
* which has the given phandle value. If there is more than one node
* in the tree with the given phandle (an invalid tree), results are
* undefined.
*
* returns:
* structure block offset of the located node (>= 0), on success
* -FDT_ERR_NOTFOUND, no node with that phandle exists
* -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
/**
* fdt_node_check_compatible: check a node's compatible property
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of a tree node
* @compatible: string to match against
*
*
* fdt_node_check_compatible() returns 0 if the given node contains a
* 'compatible' property with the given string as one of its elements,
* it returns non-zero otherwise, or on error.
*
* returns:
* 0, if the node has a 'compatible' property listing the given string
* 1, if the node has a 'compatible' property, but it does not list
* the given string
* -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
* -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_node_check_compatible(const void *fdt, int nodeoffset,
const char *compatible);
/**
* fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
* @fdt: pointer to the device tree blob
* @startoffset: only find nodes after this offset
* @compatible: 'compatible' string to match against
*
* fdt_node_offset_by_compatible() returns the offset of the first
* node after startoffset, which has a 'compatible' property which
* lists the given compatible string; or if startoffset is -1, the
* very first such node in the tree.
*
* To iterate through all nodes matching the criterion, the following
* idiom can be used:
* offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
* while (offset != -FDT_ERR_NOTFOUND) {
* ... other code here ...
* offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
* }
*
* Note the -1 in the first call to the function, if 0 is used here
* instead, the function will never locate the root node, even if it
* matches the criterion.
*
* returns:
* structure block offset of the located node (>= 0, >startoffset),
* on success
* -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
* tree after startoffset
* -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE, standard meanings
*/
int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
const char *compatible);
/**********************************************************************/
/* Write-in-place functions */
/**********************************************************************/
/**
* fdt_setprop_inplace - change a property's value, but not its size
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @val: pointer to data to replace the property value with
* @len: length of the property value
*
* fdt_setprop_inplace() replaces the value of a given property with
* the data in val, of length len. This function cannot change the
* size of a property, and so will only work if len is equal to the
* current length of the property.
*
* This function will alter only the bytes in the blob which contain
* the given property value, and will not alter or move any other part
* of the tree.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, if len is not equal to the property's current length
* -FDT_ERR_NOTFOUND, node does not have the named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
const void *val, int len);
/**
* fdt_setprop_inplace_cell - change the value of a single-cell property
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @val: cell (32-bit integer) value to replace the property with
*
* fdt_setprop_inplace_cell() replaces the value of a given property
* with the 32-bit integer cell value in val, converting val to
* big-endian if necessary. This function cannot change the size of a
* property, and so will only work if the property already exists and
* has length 4.
*
* This function will alter only the bytes in the blob which contain
* the given property value, and will not alter or move any other part
* of the tree.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, if the property's length is not equal to 4
* -FDT_ERR_NOTFOUND, node does not have the named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
const char *name, uint32_t val)
{
val = cpu_to_fdt32(val);
return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
}
/**
* fdt_nop_property - replace a property with nop tags
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to nop
* @name: name of the property to nop
*
* fdt_nop_property() will replace a given property's representation
* in the blob with FDT_NOP tags, effectively removing it from the
* tree.
*
* This function will alter only the bytes in the blob which contain
* the property, and will not alter or move any other part of the
* tree.
*
* returns:
* 0, on success
* -FDT_ERR_NOTFOUND, node does not have the named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
/**
* fdt_nop_node - replace a node (subtree) with nop tags
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node to nop
*
* fdt_nop_node() will replace a given node's representation in the
* blob, including all its subnodes, if any, with FDT_NOP tags,
* effectively removing it from the tree.
*
* This function will alter only the bytes in the blob which contain
* the node and its properties and subnodes, and will not alter or
* move any other part of the tree.
*
* returns:
* 0, on success
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_nop_node(void *fdt, int nodeoffset);
/**********************************************************************/
/* Sequential write functions */
/**********************************************************************/
int fdt_create(void *buf, int bufsize);
int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
int fdt_finish_reservemap(void *fdt);
int fdt_begin_node(void *fdt, const char *name);
int fdt_property(void *fdt, const char *name, const void *val, int len);
static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
{
val = cpu_to_fdt32(val);
return fdt_property(fdt, name, &val, sizeof(val));
}
#define fdt_property_string(fdt, name, str) \
fdt_property(fdt, name, str, strlen(str)+1)
int fdt_end_node(void *fdt);
int fdt_finish(void *fdt);
/**********************************************************************/
/* Read-write functions */
/**********************************************************************/
int fdt_open_into(const void *fdt, void *buf, int bufsize);
int fdt_pack(void *fdt);
/**
* fdt_add_mem_rsv - add one memory reserve map entry
* @fdt: pointer to the device tree blob
* @address, @size: 64-bit values (native endian)
*
* Adds a reserve map entry to the given blob reserving a region at
* address address of length size.
*
* This function will insert data into the reserve map and will
* therefore change the indexes of some entries in the table.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
* contain the new reservation entry
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
/**
* fdt_del_mem_rsv - remove a memory reserve map entry
* @fdt: pointer to the device tree blob
* @n: entry to remove
*
* fdt_del_mem_rsv() removes the n-th memory reserve map entry from
* the blob.
*
* This function will delete data from the reservation table and will
* therefore change the indexes of some entries in the table.
*
* returns:
* 0, on success
* -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
* are less than n+1 reserve map entries)
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_del_mem_rsv(void *fdt, int n);
/**
* fdt_set_name - change the name of a given node
* @fdt: pointer to the device tree blob
* @nodeoffset: structure block offset of a node
* @name: name to give the node
*
* fdt_set_name() replaces the name (including unit address, if any)
* of the given node with the given string. NOTE: this function can't
* efficiently check if the new name is unique amongst the given
* node's siblings; results are undefined if this function is invoked
* with a name equal to one of the given node's siblings.
*
* This function may insert or delete data from the blob, and will
* therefore change the offsets of some existing nodes.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, there is insufficient free space in the blob
* to contain the new name
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE, standard meanings
*/
int fdt_set_name(void *fdt, int nodeoffset, const char *name);
/**
* fdt_setprop - create or change a property
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @val: pointer to data to set the property value to
* @len: length of the property value
*
* fdt_setprop() sets the value of the named property in the given
* node to the given value and length, creating the property if it
* does not already exist.
*
* This function may insert or delete data from the blob, and will
* therefore change the offsets of some existing nodes.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
* contain the new property value
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_setprop(void *fdt, int nodeoffset, const char *name,
const void *val, int len);
/**
* fdt_setprop_cell - set a property to a single cell value
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @val: 32-bit integer value for the property (native endian)
*
* fdt_setprop_cell() sets the value of the named property in the
* given node to the given cell value (converting to big-endian if
* necessary), or creates a new property with that value if it does
* not already exist.
*
* This function may insert or delete data from the blob, and will
* therefore change the offsets of some existing nodes.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
* contain the new property value
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_TRUNCATED, standard meanings
*/
static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
uint32_t val)
{
val = cpu_to_fdt32(val);
return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
}
/**
* fdt_setprop_string - set a property to a string value
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @str: string value for the property
*
* fdt_setprop_string() sets the value of the named property in the
* given node to the given string value (using the length of the
* string to determine the new length of the property), or creates a
* new property with that value if it does not already exist.
*
* This function may insert or delete data from the blob, and will
* therefore change the offsets of some existing nodes.
*
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
* contain the new property value
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_TRUNCATED, standard meanings
*/
#define fdt_setprop_string(fdt, nodeoffset, name, str) \
fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
/**
* fdt_delprop - delete a property
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to nop
* @name: name of the property to nop
*
* fdt_del_property() will delete the given property.
*
* This function will delete data from the blob, and will therefore
* change the offsets of some existing nodes.
*
* returns:
* 0, on success
* -FDT_ERR_NOTFOUND, node does not have the named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_delprop(void *fdt, int nodeoffset, const char *name);
/**
* fdt_add_subnode_namelen - creates a new node based on substring
* @fdt: pointer to the device tree blob
* @parentoffset: structure block offset of a node
* @name: name of the subnode to locate
* @namelen: number of characters of name to consider
*
* Identical to fdt_add_subnode(), but use only the first namelen
* characters of name as the name of the new node. This is useful for
* creating subnodes based on a portion of a larger string, such as a
* full path.
*/
int fdt_add_subnode_namelen(void *fdt, int parentoffset,
const char *name, int namelen);
/**
* fdt_add_subnode - creates a new node
* @fdt: pointer to the device tree blob
* @parentoffset: structure block offset of a node
* @name: name of the subnode to locate
*
* fdt_add_subnode() creates a new node as a subnode of the node at
* structure block offset parentoffset, with the given name (which
* should include the unit address, if any).
*
* This function will insert data into the blob, and will therefore
* change the offsets of some existing nodes.
* returns:
* structure block offset of the created nodeequested subnode (>=0), on success
* -FDT_ERR_NOTFOUND, if the requested subnode does not exist
* -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
* -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
* the given name
* -FDT_ERR_NOSPACE, if there is insufficient free space in the
* blob to contain the new node
* -FDT_ERR_NOSPACE
* -FDT_ERR_BADLAYOUT
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings.
*/
int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
/**
* fdt_del_node - delete a node (subtree)
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node to nop
*
* fdt_del_node() will remove the given node, including all its
* subnodes if any, from the blob.
*
* This function will delete data from the blob, and will therefore
* change the offsets of some existing nodes.
*
* returns:
* 0, on success
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTATE,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
int fdt_del_node(void *fdt, int nodeoffset);
/**********************************************************************/
/* Debugging / informational functions */
/**********************************************************************/
const char *fdt_strerror(int errval);
#endif /* _LIBFDT_H */
|
1001-study-uboot
|
include/libfdt.h
|
C
|
gpl3
| 46,496
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MCD_API_H
#define _MCD_API_H
/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
#undef MCD_INCLUDE_EU
/* Number of DMA channels */
#define NCHANNELS 16
/* Total number of variants */
#ifdef MCD_INCLUDE_EU
#define NUMOFVARIANTS 6
#else
#define NUMOFVARIANTS 4
#endif
/* Define sizes of the various tables */
#define TASK_TABLE_SIZE (NCHANNELS*32)
#define VAR_TAB_SIZE (128)
#define CONTEXT_SAVE_SIZE (128)
#define FUNCDESC_TAB_SIZE (256)
#ifdef MCD_INCLUDE_EU
#define FUNCDESC_TAB_NUM 16
#else
#define FUNCDESC_TAB_NUM 1
#endif
#ifndef DEFINESONLY
/* Portability typedefs */
#if 1
#include "common.h"
#else
#ifndef s32
typedef int s32;
#endif
#ifndef u32
typedef unsigned int u32;
#endif
#ifndef s16
typedef short s16;
#endif
#ifndef u16
typedef unsigned short u16;
#endif
#ifndef s8
typedef char s8;
#endif
#ifndef u8
typedef unsigned char u8;
#endif
#endif
/*
* These structures represent the internal registers of the
* multi-channel DMA
*/
struct dmaRegs_s {
u32 taskbar; /* task table base address */
u32 currPtr;
u32 endPtr;
u32 varTablePtr;
u16 dma_rsvd0;
u16 ptdControl; /* ptd control */
u32 intPending; /* interrupt pending */
u32 intMask; /* interrupt mask */
u16 taskControl[16]; /* task control */
u8 priority[32]; /* priority */
u32 initiatorMux; /* initiator mux control */
u32 taskSize0; /* task size control 0. */
u32 taskSize1; /* task size control 1. */
u32 dma_rsvd1; /* reserved */
u32 dma_rsvd2; /* reserved */
u32 debugComp1; /* debug comparator 1 */
u32 debugComp2; /* debug comparator 2 */
u32 debugControl; /* debug control */
u32 debugStatus; /* debug status */
u32 ptdDebug; /* priority task decode debug */
u32 dma_rsvd3[31]; /* reserved */
};
typedef volatile struct dmaRegs_s dmaRegs;
#endif
/* PTD contrl reg bits */
#define PTD_CTL_TSK_PRI 0x8000
#define PTD_CTL_COMM_PREFETCH 0x0001
/* Task Control reg bits and field masks */
#define TASK_CTL_EN 0x8000
#define TASK_CTL_VALID 0x4000
#define TASK_CTL_ALWAYS 0x2000
#define TASK_CTL_INIT_MASK 0x1f00
#define TASK_CTL_ASTRT 0x0080
#define TASK_CTL_HIPRITSKEN 0x0040
#define TASK_CTL_HLDINITNUM 0x0020
#define TASK_CTL_ASTSKNUM_MASK 0x000f
/* Priority reg bits and field masks */
#define PRIORITY_HLD 0x80
#define PRIORITY_PRI_MASK 0x07
/* Debug Control reg bits and field masks */
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
#define DBG_CTL_AUTO_ARM 0x00008000
#define DBG_CTL_BREAK 0x00004000
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
#define DBG_CTL_EXT_BREAK 0x00000004
#define DBG_CTL_INT_BREAK 0x00000002
/*
* PTD Debug reg selector addresses
* This reg must be written with a value to show the contents of
* one of the desired internal register.
*/
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
have initiators asserted */
/* General return values */
#define MCD_OK 0
#define MCD_ERROR -1
#define MCD_TABLE_UNALIGNED -2
#define MCD_CHANNEL_INVALID -3
/* MCD_initDma input flags */
#define MCD_RELOC_TASKS 0x00000001
#define MCD_NO_RELOC_TASKS 0x00000000
#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
/*
* MCD_dmaStatus Status Values for each channel:
* MCD_NO_DMA - No DMA has been requested since reset
* MCD_IDLE - DMA active, but the initiator is currently inactive
* MCD_RUNNING - DMA active, and the initiator is currently active
* MCD_PAUSED - DMA active but it is currently paused
* MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
* MCD_DONE - the most recent DMA has completed
*/
#define MCD_NO_DMA 1
#define MCD_IDLE 2
#define MCD_RUNNING 3
#define MCD_PAUSED 4
#define MCD_HALTED 5
#define MCD_DONE 6
/* MCD_startDma parameter defines */
/* Constants for the funcDesc parameter */
/*
* MCD_NO_BYTE_SWAP - to disable byte swapping
* MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
* MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
* value being DMAed
* MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
* each 32-bit data value DMAed
* MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
* MCD_BIT_REV - reverse the bits of each byte DMAed
* MCD_CRC16 - to perform CRC-16 on DMAed data
* MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
* MCD_CRC32 - to perform CRC-32 on DMAed data
* MCD_CSUMINET - to perform internet checksums on DMAed data
* MCD_NO_CSUM - to perform no checksumming
*/
#define MCD_NO_BYTE_SWAP 0x00045670
#define MCD_BYTE_REVERSE 0x00076540
#define MCD_U16_REVERSE 0x00067450
#define MCD_U16_BYTE_REVERSE 0x00054760
#define MCD_NO_BIT_REV 0x00000000
#define MCD_BIT_REV 0x00088880
/* CRCing: */
#define MCD_CRC16 0xc0100000
#define MCD_CRCCCITT 0xc0200000
#define MCD_CRC32 0xc0300000
#define MCD_CSUMINET 0xc0400000
#define MCD_NO_CSUM 0xa0000000
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
MCD_NO_CSUM)
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
/* Constants for the flags parameter */
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
#define MCD_TT_FLAGS_MASK 0x000000ff
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
#define MCD_CHAIN_DMA /* TBD */
#define MCD_EU_DMA /* TBD */
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
/*
* MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
* MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
* MCD_INTERRUPT - to generate an interrupt after completion of the DMA
* MCD_END_FRAME - tell the DMA to end the frame when transferring
* last byte of data in buffer
* MCD_CRC_RESTART - to empty out the accumulated checksum prior to
* performing the DMA
*/
#define MCD_BUF_READY 0x80000000
#define MCD_WRAP 0x20000000
#define MCD_INTERRUPT 0x10000000
#define MCD_END_FRAME 0x08000000
#define MCD_CRC_RESTART 0x40000000
/* Defines for the FEC buffer descriptor control/status word*/
#define MCD_FEC_BUF_READY 0x8000
#define MCD_FEC_WRAP 0x2000
#define MCD_FEC_INTERRUPT 0x1000
#define MCD_FEC_END_FRAME 0x0800
/* Defines for general intuitiveness */
#define MCD_TRUE 1
#define MCD_FALSE 0
/* Three different cases for destination and source. */
#define MINUS1 -1
#define ZERO 0
#define PLUS1 1
#ifndef DEFINESONLY
/* Task Table Entry struct*/
typedef struct {
u32 TDTstart; /* task descriptor table start */
u32 TDTend; /* task descriptor table end */
u32 varTab; /* variable table start */
u32 FDTandFlags; /* function descriptor table start & flags */
volatile u32 descAddrAndStatus;
volatile u32 modifiedVarTab;
u32 contextSaveSpace; /* context save space start */
u32 literalBases;
} TaskTableEntry;
/* Chained buffer descriptor:
* flags - flags describing the DMA
* csumResult - checksum performed since last checksum reset
* srcAddr - the address to move data from
* destAddr - the address to move data to
* lastDestAddr - the last address written to
* dmaSize - the no of bytes to xfer independent of the xfer sz
* next - next buffer descriptor in chain
* info - private info about this descriptor; DMA does not affect it
*/
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
u32 flags;
u32 csumResult;
s8 *srcAddr;
s8 *destAddr;
s8 *lastDestAddr;
u32 dmaSize;
MCD_bufDesc *next;
u32 info;
};
/* Progress Query struct:
* lastSrcAddr - the most-recent or last, post-increment source address
* lastDestAddr - the most-recent or last, post-increment destination address
* dmaSize - the amount of data transferred for the current buffer
* currBufDesc - pointer to the current buffer descriptor being DMAed
*/
typedef volatile struct MCD_XferProg_struct {
s8 *lastSrcAddr;
s8 *lastDestAddr;
u32 dmaSize;
MCD_bufDesc *currBufDesc;
} MCD_XferProg;
/* FEC buffer descriptor */
typedef volatile struct MCD_bufDescFec_struct {
u16 statCtrl;
u16 length;
u32 dataPointer;
} MCD_bufDescFec;
/*************************************************************************/
/* API function Prototypes - see MCD_dmaApi.c for further notes */
/* MCD_startDma starts a particular kind of DMA:
* srcAddr - the channel on which to run the DMA
* srcIncr - the address to move data from, or buffer-descriptor address
* destAddr - the amount to increment the source address per transfer
* destIncr - the address to move data to
* dmaSize - the amount to increment the destination address per transfer
* xferSize - the number bytes in of each data movement (1, 2, or 4)
* initiator - what device initiates the DMA
* priority - priority of the DMA
* flags - flags describing the DMA
* funcDesc - description of byte swapping, bit swapping, and CRC actions
*/
int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
int priority, u32 flags, u32 funcDesc);
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
* setting up some global settings
*/
int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
int MCD_dmaStatus(int channel);
/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
/*
* MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA.
*/
int MCD_killDma(int channel);
/*
* MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor.
*/
int MCD_continDma(int channel);
/*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel).
*/
int MCD_pauseDma(int channel);
/*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel).
*/
int MCD_resumeDma(int channel);
/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
int MCD_csumQuery(int channel, u32 * csum);
/*
* MCD_getCodeSize provides the packed size required by the microcoded task
* and structures.
*/
int MCD_getCodeSize(void);
/*
* MCD_getVersion provides a pointer to a version string and returns a
* version number.
*/
int MCD_getVersion(char **longVersion);
/* macro for setting a location in the variable table */
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
so I'm avoiding surrounding it with "do {} while(0)" */
#endif /* DEFINESONLY */
#endif /* _MCD_API_H */
|
1001-study-uboot
|
include/MCD_dma.h
|
C
|
gpl3
| 11,954
|
/*
* Porting to U-Boot:
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Lattice's ispVME Embedded Tool to load Lattice's FPGA:
*
* Lattice Semiconductor Corp. Copyright 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _VME_OPCODE_H
#define _VME_OPCODE_H
#define VME_VERSION_NUMBER "12.1"
/* Maximum declarations. */
#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */
#define SCANMAX 64000L /* The maximum SDR/SIR burst. */
/*
*
* Supported JTAG state transitions.
*
*/
#define RESET 0x00
#define IDLE 0x01
#define IRPAUSE 0x02
#define DRPAUSE 0x03
#define SHIFTIR 0x04
#define SHIFTDR 0x05
/* 11/15/05 Nguyen changed to support DRCAPTURE*/
#define DRCAPTURE 0x06
/*
* Flow control register bit definitions. A set bit indicates
* that the register currently exhibits the corresponding mode.
*/
#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */
#define CASCADE 0x0002 /* Currently splitting large SDR. */
#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */
#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */
#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */
#define VERIFYUES 0x0200 /* Continue if fail is in effect. */
/*
* DataType register bit definitions. A set bit indicates
* that the register currently holds the corresponding type of data.
*/
#define EXPRESS 0x0001 /* Simultaneous program and verify. */
#define SIR_DATA 0x0002 /* SIR is the active SVF command. */
#define SDR_DATA 0x0004 /* SDR is the active SVF command. */
#define COMPRESS 0x0008 /* Data is compressed. */
#define TDI_DATA 0x0010 /* TDI data is present. */
#define TDO_DATA 0x0020 /* TDO data is present. */
#define MASK_DATA 0x0040 /* MASK data is present. */
#define HEAP_IN 0x0080 /* Data is from the heap. */
#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */
#define VARIABLE 0x0400 /* Data is from a declared variable. */
#define CRC_DATA 0x0800 /* CRC data is pressent. */
#define CMASK_DATA 0x1000 /* CMASK data is pressent. */
#define RMASK_DATA 0x2000 /* RMASK data is pressent. */
#define READ_DATA 0x4000 /* READ data is pressent. */
#define DMASK_DATA 0x8000 /* DMASK data is pressent. */
/*
*
* Pin opcodes.
*
*/
#define signalENABLE 0x1C /* ispENABLE pin. */
#define signalTMS 0x1D /* TMS pin. */
#define signalTCK 0x1E /* TCK pin. */
#define signalTDI 0x1F /* TDI pin. */
#define signalTRST 0x20 /* TRST pin. */
/*
*
* Supported vendors.
*
*/
#define VENDOR 0x56
#define LATTICE 0x01
#define ALTERA 0x02
#define XILINX 0x03
/*
* Opcode definitions.
*
* Note: opcodes must be unique.
*/
#define ENDDATA 0x00 /* The end of the current SDR data stream. */
#define RUNTEST 0x01 /* The duration to stay at the stable state. */
#define ENDDR 0x02 /* The stable state after SDR. */
#define ENDIR 0x03 /* The stable state after SIR. */
#define ENDSTATE 0x04 /* The stable state after RUNTEST. */
#define TRST 0x05 /* Assert the TRST pin. */
#define HIR 0x06 /*
* The sum of the IR bits of the
* leading devices.
*/
#define TIR 0x07 /*
* The sum of the IR bits of the trailing
* devices.
*/
#define HDR 0x08 /* The number of leading devices. */
#define TDR 0x09 /* The number of trailing devices. */
#define ispEN 0x0A /* Assert the ispEN pin. */
#define FREQUENCY 0x0B /*
* The maximum clock rate to run the JTAG state
* machine.
*/
#define STATE 0x10 /* Move to the next stable state. */
#define SIR 0x11 /* The instruction stream follows. */
#define SDR 0x12 /* The data stream follows. */
#define TDI 0x13 /* The following data stream feeds into
the device. */
#define TDO 0x14 /*
* The following data stream is compared against
* the device.
*/
#define MASK 0x15 /* The following data stream is used as mask. */
#define XSDR 0x16 /*
* The following data stream is for simultaneous
* program and verify.
*/
#define XTDI 0x17 /* The following data stream is for shift in
* only. It must be stored for the next
* XSDR.
*/
#define XTDO 0x18 /*
* There is not data stream. The data stream
* was stored from the previous XTDI.
*/
#define MEM 0x19 /*
* The maximum memory needed to allocate in
* order hold one row of data.
*/
#define WAIT 0x1A /* The duration of delay to observe. */
#define TCK 0x1B /* The number of TCK pulses. */
#define SHR 0x23 /*
* Set the flow control register for
* right shift
*/
#define SHL 0x24 /*
* Set the flow control register for left shift.
*/
#define HEAP 0x32 /* The memory size needed to hold one loop. */
#define REPEAT 0x33 /* The beginning of the loop. */
#define LEFTPAREN 0x35 /* The beginning of data following the loop. */
#define VAR 0x55 /* Plac holder for loop data. */
#define SEC 0x1C /*
* The delay time in seconds that must be
* observed.
*/
#define SMASK 0x1D /* The mask for TDI data. */
#define MAX_WAIT 0x1E /* The absolute maximum wait time. */
#define ON 0x1F /* Assert the targeted pin. */
#define OFF 0x20 /* Dis-assert the targeted pin. */
#define SETFLOW 0x30 /* Change the flow control register. */
#define RESETFLOW 0x31 /* Clear the flow control register. */
#define CRC 0x47 /*
* The following data stream is used for CRC
* calculation.
*/
#define CMASK 0x48 /*
* The following data stream is used as mask
* for CRC calculation.
*/
#define RMASK 0x49 /*
* The following data stream is used as mask
* for read and save.
*/
#define READ 0x50 /*
* The following data stream is used for read
* and save.
*/
#define ENDLOOP 0x59 /* The end of the repeat loop. */
#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */
#define VUES 0x61 /* Support continue if fail. */
#define DMASK 0x62 /*
* The following data stream is used for dynamic
* I/O.
*/
#define COMMENT 0x63 /* Support SVF comments in the VME file. */
#define HEADER 0x64 /* Support header in VME file. */
#define FILE_CRC 0x65 /* Support crc-protected VME file. */
#define LCOUNT 0x66 /* Support intelligent programming. */
#define LDELAY 0x67 /* Support intelligent programming. */
#define LSDR 0x68 /* Support intelligent programming. */
#define LHEAP 0x69 /*
* Memory needed to hold intelligent data
* buffer
*/
#define CONTINUE 0x70 /* Allow continuation. */
#define LVDS 0x71 /* Support LVDS. */
#define ENDVME 0x7F /* End of the VME file. */
#define ENDFILE 0xFF /* End of file. */
/*
*
* ispVM Embedded Return Codes.
*
*/
#define VME_VERIFICATION_FAILURE -1
#define VME_FILE_READ_FAILURE -2
#define VME_VERSION_FAILURE -3
#define VME_INVALID_FILE -4
#define VME_ARGUMENT_FAILURE -5
#define VME_CRC_FAILURE -6
#define g_ucPinTDI 0x01
#define g_ucPinTCK 0x02
#define g_ucPinTMS 0x04
#define g_ucPinENABLE 0x08
#define g_ucPinTRST 0x10
/*
*
* Type definitions.
*
*/
/* Support LVDS */
typedef struct {
unsigned short usPositiveIndex;
unsigned short usNegativeIndex;
unsigned char ucUpdate;
} LVDSPair;
typedef enum {
min_lattice_iface_type, /* insert all new types after this */
lattice_jtag_mode, /* jtag/tap */
max_lattice_iface_type /* insert all new types before this */
} Lattice_iface;
typedef enum {
min_lattice_type,
Lattice_XP2, /* Lattice XP2 Family */
max_lattice_type /* insert all new types before this */
} Lattice_Family;
typedef struct {
Lattice_Family family; /* part type */
Lattice_iface iface; /* interface type */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
void *base; /* base interface address */
int cookie; /* implementation specific cookie */
char *desc; /* description string */
} Lattice_desc; /* end, typedef Altera_desc */
/* Lattice Model Type */
#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1)
/* Board specific implementation specific function types */
typedef void (*Lattice_jtag_init)(void);
typedef void (*Lattice_jtag_set_tdi)(int v);
typedef void (*Lattice_jtag_set_tms)(int v);
typedef void (*Lattice_jtag_set_tck)(int v);
typedef int (*Lattice_jtag_get_tdo)(void);
typedef struct {
Lattice_jtag_init jtag_init;
Lattice_jtag_set_tdi jtag_set_tdi;
Lattice_jtag_set_tms jtag_set_tms;
Lattice_jtag_set_tck jtag_set_tck;
Lattice_jtag_get_tdo jtag_get_tdo;
} lattice_board_specific_func;
void writePort(unsigned char pins, unsigned char value);
unsigned char readPort(void);
void sclock(void);
void ispVMDelay(unsigned short int a_usMicroSecondDelay);
void calibration(void);
int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize);
int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize);
int lattice_info(Lattice_desc *desc);
void ispVMStart(void);
void ispVMEnd(void);
extern void ispVMFreeMem(void);
signed char ispVMCode(void);
void ispVMDelay(unsigned short int a_usMicroSecondDelay);
void ispVMCalculateCRC32(unsigned char a_ucData);
unsigned char GetByte(void);
void writePort(unsigned char pins, unsigned char value);
unsigned char readPort(void);
void sclock(void);
#endif
|
1001-study-uboot
|
include/lattice.h
|
C
|
gpl3
| 10,007
|
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: Part of this code has been derived from linux
*
*/
#ifndef _USB_H_
#define _USB_H_
#include <usb_defs.h>
#include <usbdescriptors.h>
/* Everything is aribtrary */
#define USB_ALTSETTINGALLOC 4
#define USB_MAXALTSETTING 128 /* Hard limit */
#define USB_MAX_DEVICE 32
#define USB_MAXCONFIG 8
#define USB_MAXINTERFACES 8
#define USB_MAXENDPOINTS 16
#define USB_MAXCHILDREN 8 /* This is arbitrary */
#define USB_MAX_HUB 16
#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
/*
* This is the timeout to allow for submitting an urb in ms. We allow more
* time for a BULK device to react - some are slow.
*/
#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 1000)
/* device request (setup) */
struct devrequest {
unsigned char requesttype;
unsigned char request;
unsigned short value;
unsigned short index;
unsigned short length;
} __attribute__ ((packed));
/* All standard descriptors have these 2 fields in common */
struct usb_descriptor_header {
unsigned char bLength;
unsigned char bDescriptorType;
} __attribute__ ((packed));
/* Interface */
struct usb_interface {
struct usb_interface_descriptor desc;
unsigned char no_of_ep;
unsigned char num_altsetting;
unsigned char act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));
/* Configuration information.. */
struct usb_config {
struct usb_configuration_descriptor desc;
unsigned char no_of_if; /* number of interfaces */
struct usb_interface if_desc[USB_MAXINTERFACES];
} __attribute__ ((packed));
enum {
/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
PACKET_SIZE_8 = 0,
PACKET_SIZE_16 = 1,
PACKET_SIZE_32 = 2,
PACKET_SIZE_64 = 3,
};
struct usb_device {
int devnum; /* Device number on USB bus */
int speed; /* full/low/high */
char mf[32]; /* manufacturer */
char prod[32]; /* product */
char serial[32]; /* serial number */
/* Maximum packet size; one of: PACKET_SIZE_* */
int maxpacketsize;
/* one bit for each endpoint ([0] = IN, [1] = OUT) */
unsigned int toggle[2];
/* endpoint halts; one bit per endpoint # & direction;
* [0] = IN, [1] = OUT
*/
unsigned int halted[2];
int epmaxpacketin[16]; /* INput endpoint specific maximums */
int epmaxpacketout[16]; /* OUTput endpoint specific maximums */
int configno; /* selected config number */
struct usb_device_descriptor descriptor; /* Device Descriptor */
struct usb_config config; /* config descriptor */
int have_langid; /* whether string_langid is valid yet */
int string_langid; /* language ID for strings */
int (*irq_handle)(struct usb_device *dev);
unsigned long irq_status;
int irq_act_len; /* transfered bytes */
void *privptr;
/*
* Child devices - if this is a hub device
* Each instance needs its own set of data structures.
*/
unsigned long status;
int act_len; /* transfered bytes */
int maxchild; /* Number of ports if hub */
int portnr;
struct usb_device *parent;
struct usb_device *children[USB_MAXCHILDREN];
};
/**********************************************************************
* this is how the lowlevel part communicate with the outer world
*/
#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X)
int usb_lowlevel_init(void);
int usb_lowlevel_stop(void);
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len);
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, struct devrequest *setup);
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval);
void usb_event_poll(void);
/* Defines */
#define USB_UHCI_VEND_ID 0x8086
#define USB_UHCI_DEV_ID 0x7112
#else
#error USB Lowlevel not defined
#endif
#ifdef CONFIG_USB_STORAGE
#define USB_MAX_STOR_DEV 5
block_dev_desc_t *usb_stor_get_dev(int index);
int usb_stor_scan(int mode);
int usb_stor_info(void);
#endif
#ifdef CONFIG_USB_HOST_ETHER
#define USB_MAX_ETH_DEV 5
int usb_host_eth_scan(int mode);
#endif
#ifdef CONFIG_USB_KEYBOARD
int drv_usb_kbd_init(void);
int usb_kbd_deregister(void);
#endif
/* routines */
int usb_init(void); /* initialize the USB Controller */
int usb_stop(void); /* stop the USB Controller */
int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
int usb_set_idle(struct usb_device *dev, int ifnum, int duration,
int report_id);
struct usb_device *usb_get_dev_index(int index);
int usb_control_msg(struct usb_device *dev, unsigned int pipe,
unsigned char request, unsigned char requesttype,
unsigned short value, unsigned short index,
void *data, unsigned short size, int timeout);
int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
void *data, int len, int *actual_length, int timeout);
int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len, int interval);
int usb_disable_asynch(int disable);
int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
inline void wait_ms(unsigned long ms);
int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
int cfgno);
int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
unsigned char id, void *buf, int size);
int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
unsigned char type, unsigned char id, void *buf,
int size);
int usb_clear_halt(struct usb_device *dev, int pipe);
int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
int usb_set_interface(struct usb_device *dev, int interface, int alternate);
/* big endian -> little endian conversion */
/* some CPUs are already little endian e.g. the ARM920T */
#define __swap_16(x) \
({ unsigned short x_ = (unsigned short)x; \
(unsigned short)( \
((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
})
#define __swap_32(x) \
({ unsigned long x_ = (unsigned long)x; \
(unsigned long)( \
((x_ & 0x000000FFUL) << 24) | \
((x_ & 0x0000FF00UL) << 8) | \
((x_ & 0x00FF0000UL) >> 8) | \
((x_ & 0xFF000000UL) >> 24)); \
})
#ifdef __LITTLE_ENDIAN
# define swap_16(x) (x)
# define swap_32(x) (x)
#else
# define swap_16(x) __swap_16(x)
# define swap_32(x) __swap_32(x)
#endif
/*
* Calling this entity a "pipe" is glorifying it. A USB pipe
* is something embarrassingly simple: it basically consists
* of the following information:
* - device number (7 bits)
* - endpoint number (4 bits)
* - current Data0/1 state (1 bit)
* - direction (1 bit)
* - speed (2 bits)
* - max packet size (2 bits: 8, 16, 32 or 64)
* - pipe type (2 bits: control, interrupt, bulk, isochronous)
*
* That's 18 bits. Really. Nothing more. And the USB people have
* documented these eighteen bits as some kind of glorious
* virtual data structure.
*
* Let's not fall in that trap. We'll just encode it as a simple
* unsigned int. The encoding is:
*
* - max size: bits 0-1 (00 = 8, 01 = 16, 10 = 32, 11 = 64)
* - direction: bit 7 (0 = Host-to-Device [Out],
* (1 = Device-to-Host [In])
* - device: bits 8-14
* - endpoint: bits 15-18
* - Data0/1: bit 19
* - speed: bit 26 (0 = Full, 1 = Low Speed, 2 = High)
* - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt,
* 10 = control, 11 = bulk)
*
* Why? Because it's arbitrary, and whatever encoding we select is really
* up to us. This one happens to share a lot of bit positions with the UHCI
* specification, so that much of the uhci driver can just mask the bits
* appropriately.
*/
/* Create various pipes... */
#define create_pipe(dev,endpoint) \
(((dev)->devnum << 8) | ((endpoint) << 15) | \
((dev)->speed << 26) | (dev)->maxpacketsize)
#define default_pipe(dev) ((dev)->speed << 26)
#define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \
create_pipe(dev, endpoint))
#define usb_rcvctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_sndisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \
create_pipe(dev, endpoint))
#define usb_rcvisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_sndbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \
create_pipe(dev, endpoint))
#define usb_rcvbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_sndintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \
create_pipe(dev, endpoint))
#define usb_rcvintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | \
default_pipe(dev))
#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | \
default_pipe(dev) | \
USB_DIR_IN)
/* The D0/D1 toggle bits */
#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep))
#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
((dev)->toggle[out] & \
~(1 << ep)) | ((bit) << ep))
/* Endpoint halt control/status */
#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1)
#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : \
USB_PID_OUT)
#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1)
#define usb_pipein(pipe) (((pipe) >> 7) & 1)
#define usb_pipedevice(pipe) (((pipe) >> 8) & 0x7f)
#define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff)
#define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf)
#define usb_pipedata(pipe) (((pipe) >> 19) & 1)
#define usb_pipespeed(pipe) (((pipe) >> 26) & 3)
#define usb_pipeslow(pipe) (usb_pipespeed(pipe) == USB_SPEED_LOW)
#define usb_pipetype(pipe) (((pipe) >> 30) & 3)
#define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
#define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT)
#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL)
#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK)
/*************************************************************************
* Hub Stuff
*/
struct usb_port_status {
unsigned short wPortStatus;
unsigned short wPortChange;
} __attribute__ ((packed));
struct usb_hub_status {
unsigned short wHubStatus;
unsigned short wHubChange;
} __attribute__ ((packed));
/* Hub descriptor */
struct usb_hub_descriptor {
unsigned char bLength;
unsigned char bDescriptorType;
unsigned char bNbrPorts;
unsigned short wHubCharacteristics;
unsigned char bPwrOn2PwrGood;
unsigned char bHubContrCurrent;
unsigned char DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
bitmaps that hold max 255 entries. (bit0 is ignored) */
} __attribute__ ((packed));
struct usb_hub_device {
struct usb_device *pusb_dev;
struct usb_hub_descriptor desc;
};
#endif /*_USB_H_ */
|
1001-study-uboot
|
include/usb.h
|
C
|
gpl3
| 12,367
|
#ifndef _MII_PHY_H_
#define _MII_PHY_H_
void mii_discover_phy(void);
unsigned short mii_phy_read(unsigned short reg);
void mii_phy_write(unsigned short reg, unsigned short val);
#endif
|
1001-study-uboot
|
include/mii_phy.h
|
C
|
gpl3
| 187
|
/*
* (C) Copyright 2002
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FDC_H_
#define _FDC_H_
/* Functions prototype */
int fdc_fdos_init (int drive);
int fdc_fdos_seek (int where);
int fdc_fdos_read (void *buffer, int len);
int dos_open(char *name);
int dos_read (ulong addr);
int dos_dir (void);
#endif
|
1001-study-uboot
|
include/fdc.h
|
C
|
gpl3
| 1,205
|
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License Version 2. This file is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _CONFIG_CMD_ALL_H
#define _CONFIG_CMD_ALL_H
/*
* Alphabetical list of all possible commands.
*/
#define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */
#define CONFIG_CMD_ASKENV /* ask for env variable */
#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_DIAG /* Diagnostics */
#define CONFIG_CMD_DISPLAY /* Display support */
#define CONFIG_CMD_DOC /* Disk-On-Chip Support */
#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EDITENV /* editenv */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
#define CONFIG_CMD_FDOS /* Floppy DOS support */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_IDE /* IDE harddisk support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_IMMAP /* IMMR dump support */
#define CONFIG_CMD_IRQ /* irqinfo */
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_KGDB /* kgdb */
#define CONFIG_CMD_LICENSE /* console license display */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
#define CONFIG_CMD_MG_DISK /* mGine m(g)flash IO node support */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_MTDPARTS /* mtd parts support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_ONENAND /* OneNAND support */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_CMD_PCMCIA /* PCMCIA support */
#define CONFIG_CMD_PING /* ping support */
#define CONFIG_CMD_PORTIO /* Port I/O */
#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_REISER /* Reiserfs support */
#define CONFIG_CMD_RARP /* rarpboot support */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
#define CONFIG_CMD_SETEXPR /* setexpr support */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SNTP /* SNTP support */
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_SPI /* SPI utility */
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
#define CONFIG_CMD_UBI /* UBI Support */
#define CONFIG_CMD_UBIFS /* UBIFS Support */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
#define CONFIG_CMD_UNZIP /* unzip from memory to memory */
#define CONFIG_CMD_USB /* USB Support */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#endif /* _CONFIG_CMD_ALL_H */
|
1001-study-uboot
|
include/config_cmd_all.h
|
C
|
gpl3
| 4,181
|
#ifndef _RADEON_H
#define _RADEON_H
#define RADEON_REGSIZE 0x4000
#define MM_INDEX 0x0000
#define MM_DATA 0x0004
#define BUS_CNTL 0x0030
#define HI_STAT 0x004C
#define BUS_CNTL1 0x0034
#define I2C_CNTL_1 0x0094
#define CONFIG_CNTL 0x00E0
#define CONFIG_MEMSIZE 0x00F8
#define CONFIG_APER_0_BASE 0x0100
#define CONFIG_APER_1_BASE 0x0104
#define CONFIG_APER_SIZE 0x0108
#define CONFIG_REG_1_BASE 0x010C
#define CONFIG_REG_APER_SIZE 0x0110
#define PAD_AGPINPUT_DELAY 0x0164
#define PAD_CTLR_STRENGTH 0x0168
#define PAD_CTLR_UPDATE 0x016C
#define PAD_CTLR_MISC 0x0aa0
#define AGP_CNTL 0x0174
#define BM_STATUS 0x0160
#define CAP0_TRIG_CNTL 0x0950
#define CAP1_TRIG_CNTL 0x09c0
#define VIPH_CONTROL 0x0C40
#define VENDOR_ID 0x0F00
#define DEVICE_ID 0x0F02
#define COMMAND 0x0F04
#define STATUS 0x0F06
#define REVISION_ID 0x0F08
#define REGPROG_INF 0x0F09
#define SUB_CLASS 0x0F0A
#define BASE_CODE 0x0F0B
#define CACHE_LINE 0x0F0C
#define LATENCY 0x0F0D
#define HEADER 0x0F0E
#define BIST 0x0F0F
#define REG_MEM_BASE 0x0F10
#define REG_IO_BASE 0x0F14
#define REG_REG_BASE 0x0F18
#define ADAPTER_ID 0x0F2C
#define BIOS_ROM 0x0F30
#define CAPABILITIES_PTR 0x0F34
#define INTERRUPT_LINE 0x0F3C
#define INTERRUPT_PIN 0x0F3D
#define MIN_GRANT 0x0F3E
#define MAX_LATENCY 0x0F3F
#define ADAPTER_ID_W 0x0F4C
#define PMI_CAP_ID 0x0F50
#define PMI_NXT_CAP_PTR 0x0F51
#define PMI_PMC_REG 0x0F52
#define PM_STATUS 0x0F54
#define PMI_DATA 0x0F57
#define AGP_CAP_ID 0x0F58
#define AGP_STATUS 0x0F5C
#define AGP_COMMAND 0x0F60
#define AIC_CTRL 0x01D0
#define AIC_STAT 0x01D4
#define AIC_PT_BASE 0x01D8
#define AIC_LO_ADDR 0x01DC
#define AIC_HI_ADDR 0x01E0
#define AIC_TLB_ADDR 0x01E4
#define AIC_TLB_DATA 0x01E8
#define DAC_CNTL 0x0058
#define DAC_CNTL2 0x007c
#define CRTC_GEN_CNTL 0x0050
#define MEM_CNTL 0x0140
#define MC_CNTL 0x0140
#define EXT_MEM_CNTL 0x0144
#define MC_TIMING_CNTL 0x0144
#define MC_AGP_LOCATION 0x014C
#define MEM_IO_CNTL_A0 0x0178
#define MEM_REFRESH_CNTL 0x0178
#define MEM_INIT_LATENCY_TIMER 0x0154
#define MC_INIT_GFX_LAT_TIMER 0x0154
#define MEM_SDRAM_MODE_REG 0x0158
#define AGP_BASE 0x0170
#define MEM_IO_CNTL_A1 0x017C
#define MC_READ_CNTL_AB 0x017C
#define MEM_IO_CNTL_B0 0x0180
#define MC_INIT_MISC_LAT_TIMER 0x0180
#define MEM_IO_CNTL_B1 0x0184
#define MC_IOPAD_CNTL 0x0184
#define MC_DEBUG 0x0188
#define MC_STATUS 0x0150
#define MEM_IO_OE_CNTL 0x018C
#define MC_CHIP_IO_OE_CNTL_AB 0x018C
#define MC_FB_LOCATION 0x0148
/* #define MC_FB_LOCATION 0x0188 */
#define HOST_PATH_CNTL 0x0130
#define MEM_VGA_WP_SEL 0x0038
#define MEM_VGA_RP_SEL 0x003C
#define HDP_DEBUG 0x0138
#define SW_SEMAPHORE 0x013C
#define CRTC2_GEN_CNTL 0x03f8
#define CRTC2_DISPLAY_BASE_ADDR 0x033c
#define SURFACE_CNTL 0x0B00
#define SURFACE0_LOWER_BOUND 0x0B04
#define SURFACE1_LOWER_BOUND 0x0B14
#define SURFACE2_LOWER_BOUND 0x0B24
#define SURFACE3_LOWER_BOUND 0x0B34
#define SURFACE4_LOWER_BOUND 0x0B44
#define SURFACE5_LOWER_BOUND 0x0B54
#define SURFACE6_LOWER_BOUND 0x0B64
#define SURFACE7_LOWER_BOUND 0x0B74
#define SURFACE0_UPPER_BOUND 0x0B08
#define SURFACE1_UPPER_BOUND 0x0B18
#define SURFACE2_UPPER_BOUND 0x0B28
#define SURFACE3_UPPER_BOUND 0x0B38
#define SURFACE4_UPPER_BOUND 0x0B48
#define SURFACE5_UPPER_BOUND 0x0B58
#define SURFACE6_UPPER_BOUND 0x0B68
#define SURFACE7_UPPER_BOUND 0x0B78
#define SURFACE0_INFO 0x0B0C
#define SURFACE1_INFO 0x0B1C
#define SURFACE2_INFO 0x0B2C
#define SURFACE3_INFO 0x0B3C
#define SURFACE4_INFO 0x0B4C
#define SURFACE5_INFO 0x0B5C
#define SURFACE6_INFO 0x0B6C
#define SURFACE7_INFO 0x0B7C
#define SURFACE_ACCESS_FLAGS 0x0BF8
#define SURFACE_ACCESS_CLR 0x0BFC
#define GEN_INT_CNTL 0x0040
#define GEN_INT_STATUS 0x0044
#define CRTC_EXT_CNTL 0x0054
#define RB3D_CNTL 0x1C3C
#define WAIT_UNTIL 0x1720
#define ISYNC_CNTL 0x1724
#define RBBM_GUICNTL 0x172C
#define RBBM_STATUS 0x0E40
#define RBBM_STATUS_alt_1 0x1740
#define RBBM_CNTL 0x00EC
#define RBBM_CNTL_alt_1 0x0E44
#define RBBM_SOFT_RESET 0x00F0
#define RBBM_SOFT_RESET_alt_1 0x0E48
#define NQWAIT_UNTIL 0x0E50
#define RBBM_DEBUG 0x0E6C
#define RBBM_CMDFIFO_ADDR 0x0E70
#define RBBM_CMDFIFO_DATAL 0x0E74
#define RBBM_CMDFIFO_DATAH 0x0E78
#define RBBM_CMDFIFO_STAT 0x0E7C
#define CRTC_STATUS 0x005C
#define GPIO_VGA_DDC 0x0060
#define GPIO_DVI_DDC 0x0064
#define GPIO_MONID 0x0068
#define GPIO_CRT2_DDC 0x006c
#define PALETTE_INDEX 0x00B0
#define PALETTE_DATA 0x00B4
#define PALETTE_30_DATA 0x00B8
#define CRTC_H_TOTAL_DISP 0x0200
#define CRTC_H_SYNC_STRT_WID 0x0204
#define CRTC_H_SYNC_POL (1 << 23)
#define CRTC_V_TOTAL_DISP 0x0208
#define CRTC_V_SYNC_STRT_WID 0x020C
#define CRTC_V_SYNC_POL (1 << 23)
#define CRTC_VLINE_CRNT_VLINE 0x0210
#define CRTC_CRNT_FRAME 0x0214
#define CRTC_GUI_TRIG_VLINE 0x0218
#define CRTC_DEBUG 0x021C
#define CRTC_OFFSET_RIGHT 0x0220
#define CRTC_OFFSET 0x0224
#define CRTC_OFFSET_CNTL 0x0228
#define CRTC_PITCH 0x022C
#define OVR_CLR 0x0230
#define OVR_WID_LEFT_RIGHT 0x0234
#define OVR_WID_TOP_BOTTOM 0x0238
#define DISPLAY_BASE_ADDR 0x023C
#define SNAPSHOT_VH_COUNTS 0x0240
#define SNAPSHOT_F_COUNT 0x0244
#define N_VIF_COUNT 0x0248
#define SNAPSHOT_VIF_COUNT 0x024C
#define FP_CRTC_H_TOTAL_DISP 0x0250
#define FP_CRTC_V_TOTAL_DISP 0x0254
#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
#define CUR_OFFSET 0x0260
#define CUR_HORZ_VERT_POSN 0x0264
#define CUR_HORZ_VERT_OFF 0x0268
#define CUR_CLR0 0x026C
#define CUR_CLR1 0x0270
#define FP_HORZ_VERT_ACTIVE 0x0278
#define CRTC_MORE_CNTL 0x027C
#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
#define DAC_EXT_CNTL 0x0280
#define FP_GEN_CNTL 0x0284
#define FP_HORZ_STRETCH 0x028C
#define FP_VERT_STRETCH 0x0290
#define FP_H_SYNC_STRT_WID 0x02C4
#define FP_V_SYNC_STRT_WID 0x02C8
#define AUX_WINDOW_HORZ_CNTL 0x02D8
#define AUX_WINDOW_VERT_CNTL 0x02DC
/* #define DDA_CONFIG 0x02e0 */
/* #define DDA_ON_OFF 0x02e4 */
#define DVI_I2C_CNTL_1 0x02e4
#define GRPH_BUFFER_CNTL 0x02F0
#define GRPH2_BUFFER_CNTL 0x03F0
#define VGA_BUFFER_CNTL 0x02F4
#define OV0_Y_X_START 0x0400
#define OV0_Y_X_END 0x0404
#define OV0_PIPELINE_CNTL 0x0408
#define OV0_REG_LOAD_CNTL 0x0410
#define OV0_SCALE_CNTL 0x0420
#define OV0_V_INC 0x0424
#define OV0_P1_V_ACCUM_INIT 0x0428
#define OV0_P23_V_ACCUM_INIT 0x042C
#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
#define OV0_BASE_ADDR 0x043C
#define OV0_VID_BUF0_BASE_ADRS 0x0440
#define OV0_VID_BUF1_BASE_ADRS 0x0444
#define OV0_VID_BUF2_BASE_ADRS 0x0448
#define OV0_VID_BUF3_BASE_ADRS 0x044C
#define OV0_VID_BUF4_BASE_ADRS 0x0450
#define OV0_VID_BUF5_BASE_ADRS 0x0454
#define OV0_VID_BUF_PITCH0_VALUE 0x0460
#define OV0_VID_BUF_PITCH1_VALUE 0x0464
#define OV0_AUTO_FLIP_CNTRL 0x0470
#define OV0_DEINTERLACE_PATTERN 0x0474
#define OV0_SUBMIT_HISTORY 0x0478
#define OV0_H_INC 0x0480
#define OV0_STEP_BY 0x0484
#define OV0_P1_H_ACCUM_INIT 0x0488
#define OV0_P23_H_ACCUM_INIT 0x048C
#define OV0_P1_X_START_END 0x0494
#define OV0_P2_X_START_END 0x0498
#define OV0_P3_X_START_END 0x049C
#define OV0_FILTER_CNTL 0x04A0
#define OV0_FOUR_TAP_COEF_0 0x04B0
#define OV0_FOUR_TAP_COEF_1 0x04B4
#define OV0_FOUR_TAP_COEF_2 0x04B8
#define OV0_FOUR_TAP_COEF_3 0x04BC
#define OV0_FOUR_TAP_COEF_4 0x04C0
#define OV0_FLAG_CNTRL 0x04DC
#define OV0_SLICE_CNTL 0x04E0
#define OV0_VID_KEY_CLR_LOW 0x04E4
#define OV0_VID_KEY_CLR_HIGH 0x04E8
#define OV0_GRPH_KEY_CLR_LOW 0x04EC
#define OV0_GRPH_KEY_CLR_HIGH 0x04F0
#define OV0_KEY_CNTL 0x04F4
#define OV0_TEST 0x04F8
#define SUBPIC_CNTL 0x0540
#define SUBPIC_DEFCOLCON 0x0544
#define SUBPIC_Y_X_START 0x054C
#define SUBPIC_Y_X_END 0x0550
#define SUBPIC_V_INC 0x0554
#define SUBPIC_H_INC 0x0558
#define SUBPIC_BUF0_OFFSET 0x055C
#define SUBPIC_BUF1_OFFSET 0x0560
#define SUBPIC_LC0_OFFSET 0x0564
#define SUBPIC_LC1_OFFSET 0x0568
#define SUBPIC_PITCH 0x056C
#define SUBPIC_BTN_HLI_COLCON 0x0570
#define SUBPIC_BTN_HLI_Y_X_START 0x0574
#define SUBPIC_BTN_HLI_Y_X_END 0x0578
#define SUBPIC_PALETTE_INDEX 0x057C
#define SUBPIC_PALETTE_DATA 0x0580
#define SUBPIC_H_ACCUM_INIT 0x0584
#define SUBPIC_V_ACCUM_INIT 0x0588
#define DISP_MISC_CNTL 0x0D00
#define DAC_MACRO_CNTL 0x0D04
#define DISP_PWR_MAN 0x0D08
#define DISP_TEST_DEBUG_CNTL 0x0D10
#define DISP_HW_DEBUG 0x0D14
#define DAC_CRC_SIG1 0x0D18
#define DAC_CRC_SIG2 0x0D1C
#define OV0_LIN_TRANS_A 0x0D20
#define OV0_LIN_TRANS_B 0x0D24
#define OV0_LIN_TRANS_C 0x0D28
#define OV0_LIN_TRANS_D 0x0D2C
#define OV0_LIN_TRANS_E 0x0D30
#define OV0_LIN_TRANS_F 0x0D34
#define OV0_GAMMA_0_F 0x0D40
#define OV0_GAMMA_10_1F 0x0D44
#define OV0_GAMMA_20_3F 0x0D48
#define OV0_GAMMA_40_7F 0x0D4C
#define OV0_GAMMA_380_3BF 0x0D50
#define OV0_GAMMA_3C0_3FF 0x0D54
#define DISP_MERGE_CNTL 0x0D60
#define DISP_OUTPUT_CNTL 0x0D64
#define DISP_LIN_TRANS_GRPH_A 0x0D80
#define DISP_LIN_TRANS_GRPH_B 0x0D84
#define DISP_LIN_TRANS_GRPH_C 0x0D88
#define DISP_LIN_TRANS_GRPH_D 0x0D8C
#define DISP_LIN_TRANS_GRPH_E 0x0D90
#define DISP_LIN_TRANS_GRPH_F 0x0D94
#define DISP_LIN_TRANS_VID_A 0x0D98
#define DISP_LIN_TRANS_VID_B 0x0D9C
#define DISP_LIN_TRANS_VID_C 0x0DA0
#define DISP_LIN_TRANS_VID_D 0x0DA4
#define DISP_LIN_TRANS_VID_E 0x0DA8
#define DISP_LIN_TRANS_VID_F 0x0DAC
#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
#define RMX_HORZ_PHASE 0x0DBC
#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
#define DAC_BROAD_PULSE 0x0DC4
#define DAC_SKEW_CLKS 0x0DC8
#define DAC_INCR 0x0DCC
#define DAC_NEG_SYNC_LEVEL 0x0DD0
#define DAC_POS_SYNC_LEVEL 0x0DD4
#define DAC_BLANK_LEVEL 0x0DD8
#define CLOCK_CNTL_INDEX 0x0008
#define CLOCK_CNTL_DATA 0x000C
#define CP_RB_CNTL 0x0704
#define CP_RB_BASE 0x0700
#define CP_RB_RPTR_ADDR 0x070C
#define CP_RB_RPTR 0x0710
#define CP_RB_WPTR 0x0714
#define CP_RB_WPTR_DELAY 0x0718
#define CP_IB_BASE 0x0738
#define CP_IB_BUFSZ 0x073C
#define SCRATCH_REG0 0x15E0
#define GUI_SCRATCH_REG0 0x15E0
#define SCRATCH_REG1 0x15E4
#define GUI_SCRATCH_REG1 0x15E4
#define SCRATCH_REG2 0x15E8
#define GUI_SCRATCH_REG2 0x15E8
#define SCRATCH_REG3 0x15EC
#define GUI_SCRATCH_REG3 0x15EC
#define SCRATCH_REG4 0x15F0
#define GUI_SCRATCH_REG4 0x15F0
#define SCRATCH_REG5 0x15F4
#define GUI_SCRATCH_REG5 0x15F4
#define SCRATCH_UMSK 0x0770
#define SCRATCH_ADDR 0x0774
#define DP_BRUSH_FRGD_CLR 0x147C
#define DP_BRUSH_BKGD_CLR 0x1478
#define DST_LINE_START 0x1600
#define DST_LINE_END 0x1604
#define SRC_OFFSET 0x15AC
#define SRC_PITCH 0x15B0
#define SRC_TILE 0x1704
#define SRC_PITCH_OFFSET 0x1428
#define SRC_X 0x1414
#define SRC_Y 0x1418
#define SRC_X_Y 0x1590
#define SRC_Y_X 0x1434
#define DST_Y_X 0x1438
#define DST_WIDTH_HEIGHT 0x1598
#define DST_HEIGHT_WIDTH 0x143c
#define DST_OFFSET 0x1404
#define SRC_CLUT_ADDRESS 0x1780
#define SRC_CLUT_DATA 0x1784
#define SRC_CLUT_DATA_RD 0x1788
#define HOST_DATA0 0x17C0
#define HOST_DATA1 0x17C4
#define HOST_DATA2 0x17C8
#define HOST_DATA3 0x17CC
#define HOST_DATA4 0x17D0
#define HOST_DATA5 0x17D4
#define HOST_DATA6 0x17D8
#define HOST_DATA7 0x17DC
#define HOST_DATA_LAST 0x17E0
#define DP_SRC_ENDIAN 0x15D4
#define DP_SRC_FRGD_CLR 0x15D8
#define DP_SRC_BKGD_CLR 0x15DC
#define SC_LEFT 0x1640
#define SC_RIGHT 0x1644
#define SC_TOP 0x1648
#define SC_BOTTOM 0x164C
#define SRC_SC_RIGHT 0x1654
#define SRC_SC_BOTTOM 0x165C
#define DP_CNTL 0x16C0
#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
#define DP_DATATYPE 0x16C4
#define DP_MIX 0x16C8
#define DP_WRITE_MSK 0x16CC
#define DP_XOP 0x17F8
#define CLR_CMP_CLR_SRC 0x15C4
#define CLR_CMP_CLR_DST 0x15C8
#define CLR_CMP_CNTL 0x15C0
#define CLR_CMP_MSK 0x15CC
#define DSTCACHE_MODE 0x1710
#define DSTCACHE_CTLSTAT 0x1714
#define DEFAULT_PITCH_OFFSET 0x16E0
#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
#define DEFAULT_SC_TOP_LEFT 0x16EC
#define SRC_PITCH_OFFSET 0x1428
#define DST_PITCH_OFFSET 0x142C
#define DP_GUI_MASTER_CNTL 0x146C
#define SC_TOP_LEFT 0x16EC
#define SC_BOTTOM_RIGHT 0x16F0
#define SRC_SC_BOTTOM_RIGHT 0x16F4
#define RB2D_DSTCACHE_MODE 0x3428
#define RB2D_DSTCACHE_CTLSTAT 0x342C
#define LVDS_GEN_CNTL 0x02d0
#define LVDS_PLL_CNTL 0x02d4
#define FP2_GEN_CNTL 0x0288
#define TMDS_CNTL 0x0294
#define TMDS_CRC 0x02a0
#define TMDS_TRANSMITTER_CNTL 0x02a4
#define MPP_TB_CONFIG 0x01c0
#define PAMAC0_DLY_CNTL 0x0a94
#define PAMAC1_DLY_CNTL 0x0a98
#define PAMAC2_DLY_CNTL 0x0a9c
#define FW_CNTL 0x0118
#define FCP_CNTL 0x0910
#define VGA_DDA_ON_OFF 0x02ec
#define TV_MASTER_CNTL 0x0800
/* #define BASE_CODE 0x0f0b */
#define BIOS_0_SCRATCH 0x0010
#define BIOS_1_SCRATCH 0x0014
#define BIOS_2_SCRATCH 0x0018
#define BIOS_3_SCRATCH 0x001c
#define BIOS_4_SCRATCH 0x0020
#define BIOS_5_SCRATCH 0x0024
#define BIOS_6_SCRATCH 0x0028
#define BIOS_7_SCRATCH 0x002c
#define HDP_SOFT_RESET (1 << 26)
#define TV_DAC_CNTL 0x088c
#define GPIOPAD_MASK 0x0198
#define GPIOPAD_A 0x019c
#define GPIOPAD_EN 0x01a0
#define GPIOPAD_Y 0x01a4
#define ZV_LCDPAD_MASK 0x01a8
#define ZV_LCDPAD_A 0x01ac
#define ZV_LCDPAD_EN 0x01b0
#define ZV_LCDPAD_Y 0x01b4
/* PLL Registers */
#define CLK_PIN_CNTL 0x0001
#define PPLL_CNTL 0x0002
#define PPLL_REF_DIV 0x0003
#define PPLL_DIV_0 0x0004
#define PPLL_DIV_1 0x0005
#define PPLL_DIV_2 0x0006
#define PPLL_DIV_3 0x0007
#define VCLK_ECP_CNTL 0x0008
#define HTOTAL_CNTL 0x0009
#define M_SPLL_REF_FB_DIV 0x000a
#define AGP_PLL_CNTL 0x000b
#define SPLL_CNTL 0x000c
#define SCLK_CNTL 0x000d
#define MPLL_CNTL 0x000e
#define MDLL_CKO 0x000f
#define MDLL_RDCKA 0x0010
#define MCLK_CNTL 0x0012
#define AGP_PLL_CNTL 0x000b
#define PLL_TEST_CNTL 0x0013
#define CLK_PWRMGT_CNTL 0x0014
#define PLL_PWRMGT_CNTL 0x0015
#define MCLK_MISC 0x001f
#define P2PLL_CNTL 0x002a
#define P2PLL_REF_DIV 0x002b
#define PIXCLKS_CNTL 0x002d
#define SCLK_MORE_CNTL 0x0035
/* MCLK_CNTL bit constants */
#define FORCEON_MCLKA (1 << 16)
#define FORCEON_MCLKB (1 << 17)
#define FORCEON_YCLKA (1 << 18)
#define FORCEON_YCLKB (1 << 19)
#define FORCEON_MC (1 << 20)
#define FORCEON_AIC (1 << 21)
/* SCLK_CNTL bit constants */
#define DYN_STOP_LAT_MASK 0x00007ff8
#define CP_MAX_DYN_STOP_LAT 0x0008
#define SCLK_FORCEON_MASK 0xffff8000
/* SCLK_MORE_CNTL bit constants */
#define SCLK_MORE_FORCEON 0x0700
/* BUS_CNTL bit constants */
#define BUS_DBL_RESYNC 0x00000001
#define BUS_MSTR_RESET 0x00000002
#define BUS_FLUSH_BUF 0x00000004
#define BUS_STOP_REQ_DIS 0x00000008
#define BUS_ROTATION_DIS 0x00000010
#define BUS_MASTER_DIS 0x00000040
#define BUS_ROM_WRT_EN 0x00000080
#define BUS_DIS_ROM 0x00001000
#define BUS_PCI_READ_RETRY_EN 0x00002000
#define BUS_AGP_AD_STEPPING_EN 0x00004000
#define BUS_PCI_WRT_RETRY_EN 0x00008000
#define BUS_MSTR_RD_MULT 0x00100000
#define BUS_MSTR_RD_LINE 0x00200000
#define BUS_SUSPEND 0x00400000
#define LAT_16X 0x00800000
#define BUS_RD_DISCARD_EN 0x01000000
#define BUS_RD_ABORT_EN 0x02000000
#define BUS_MSTR_WS 0x04000000
#define BUS_PARKING_DIS 0x08000000
#define BUS_MSTR_DISCONNECT_EN 0x10000000
#define BUS_WRT_BURST 0x20000000
#define BUS_READ_BURST 0x40000000
#define BUS_RDY_READ_DLY 0x80000000
/* PIXCLKS_CNTL */
#define PIX2CLK_SRC_SEL_MASK 0x03
#define PIX2CLK_SRC_SEL_CPUCLK 0x00
#define PIX2CLK_SRC_SEL_PSCANCLK 0x01
#define PIX2CLK_SRC_SEL_BYTECLK 0x02
#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
#define PIX2CLK_ALWAYS_ONb (1<<6)
#define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
#define PIXCLK_TV_SRC_SEL (1 << 8)
#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
/* CLOCK_CNTL_INDEX bit constants */
#define PLL_WR_EN 0x00000080
/* CONFIG_CNTL bit constants */
#define CONFIG_SYS_VGA_RAM_EN 0x00000100
#define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16)
#define CONFIG_SYS_ATI_REV_A11 (0 << 16)
#define CONFIG_SYS_ATI_REV_A12 (1 << 16)
#define CONFIG_SYS_ATI_REV_A13 (2 << 16)
/* CRTC_EXT_CNTL bit constants */
#define VGA_ATI_LINEAR 0x00000008
#define VGA_128KAP_PAGING 0x00000010
#define XCRT_CNT_EN (1 << 6)
#define CRTC_HSYNC_DIS (1 << 8)
#define CRTC_VSYNC_DIS (1 << 9)
#define CRTC_DISPLAY_DIS (1 << 10)
#define CRTC_CRT_ON (1 << 15)
/* DSTCACHE_CTLSTAT bit constants */
#define RB2D_DC_FLUSH (3 << 0)
#define RB2D_DC_FLUSH_ALL 0xf
#define RB2D_DC_BUSY (1 << 31)
/* CRTC_GEN_CNTL bit constants */
#define CRTC_DBL_SCAN_EN 0x00000001
#define CRTC_CUR_EN 0x00010000
#define CRTC_INTERLACE_EN (1 << 1)
#define CRTC_BYPASS_LUT_EN (1 << 14)
#define CRTC_EXT_DISP_EN (1 << 24)
#define CRTC_EN (1 << 25)
#define CRTC_DISP_REQ_EN_B (1 << 26)
/* CRTC_STATUS bit constants */
#define CRTC_VBLANK 0x00000001
/* CRTC2_GEN_CNTL bit constants */
#define CRT2_ON (1 << 7)
#define CRTC2_DISPLAY_DIS (1 << 23)
#define CRTC2_EN (1 << 25)
#define CRTC2_DISP_REQ_EN_B (1 << 26)
/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
#define CUR_LOCK 0x80000000
/* GPIO bit constants */
#define GPIO_A_0 (1 << 0)
#define GPIO_A_1 (1 << 1)
#define GPIO_Y_0 (1 << 8)
#define GPIO_Y_1 (1 << 9)
#define GPIO_EN_0 (1 << 16)
#define GPIO_EN_1 (1 << 17)
#define GPIO_MASK_0 (1 << 24)
#define GPIO_MASK_1 (1 << 25)
#define VGA_DDC_DATA_OUTPUT GPIO_A_0
#define VGA_DDC_CLK_OUTPUT GPIO_A_1
#define VGA_DDC_DATA_INPUT GPIO_Y_0
#define VGA_DDC_CLK_INPUT GPIO_Y_1
#define VGA_DDC_DATA_OUT_EN GPIO_EN_0
#define VGA_DDC_CLK_OUT_EN GPIO_EN_1
/* FP bit constants */
#define FP_CRTC_H_TOTAL_MASK 000003ff
#define FP_CRTC_H_DISP_MASK 0x01ff0000
#define FP_CRTC_V_TOTAL_MASK 0x00000fff
#define FP_CRTC_V_DISP_MASK 0x0fff0000
#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
#define FP_H_SYNC_WID_MASK 0x003f0000
#define FP_V_SYNC_STRT_MASK 0x00000fff
#define FP_V_SYNC_WID_MASK 0x001f0000
#define FP_CRTC_H_TOTAL_SHIFT 0x00000000
#define FP_CRTC_H_DISP_SHIFT 0x00000010
#define FP_CRTC_V_TOTAL_SHIFT 0x00000000
#define FP_CRTC_V_DISP_SHIFT 0x00000010
#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
#define FP_H_SYNC_WID_SHIFT 0x00000010
#define FP_V_SYNC_STRT_SHIFT 0x00000000
#define FP_V_SYNC_WID_SHIFT 0x00000010
/* FP_GEN_CNTL bit constants */
#define FP_FPON (1 << 0)
#define FP_TMDS_EN (1 << 2)
#define FP_PANEL_FORMAT (1 << 3)
#define FP_EN_TMDS (1 << 7)
#define FP_DETECT_SENSE (1 << 8)
#define R200_FP_SOURCE_SEL_MASK (3 << 10)
#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
#define R200_FP_SOURCE_SEL_RMX (2 << 10)
#define R200_FP_SOURCE_SEL_TRANS (3 << 10)
#define FP_SEL_CRTC1 (0 << 13)
#define FP_SEL_CRTC2 (1 << 13)
#define FP_USE_VGA_HSYNC (1 << 14)
#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
#define FP_CRTC_USE_SHADOW_VEND (1 << 18)
#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
#define FP_DFP_SYNC_SEL (1 << 21)
#define FP_CRTC_LOCK_8DOT (1 << 22)
#define FP_CRT_SYNC_SEL (1 << 23)
#define FP_USE_SHADOW_EN (1 << 24)
#define FP_CRT_SYNC_ALT (1 << 26)
/* FP2_GEN_CNTL bit constants */
#define FP2_BLANK_EN (1 << 1)
#define FP2_ON (1 << 2)
#define FP2_PANEL_FORMAT (1 << 3)
#define FP2_SOURCE_SEL_MASK (3 << 10)
#define FP2_SOURCE_SEL_CRTC2 (1 << 10)
#define FP2_SRC_SEL_MASK (3 << 13)
#define FP2_SRC_SEL_CRTC2 (1 << 13)
#define FP2_FP_POL (1 << 16)
#define FP2_LP_POL (1 << 17)
#define FP2_SCK_POL (1 << 18)
#define FP2_LCD_CNTL_MASK (7 << 19)
#define FP2_PAD_FLOP_EN (1 << 22)
#define FP2_CRC_EN (1 << 23)
#define FP2_CRC_READ_EN (1 << 24)
#define FP2_DV0_EN (1 << 25)
#define FP2_DV0_RATE_SEL_SDR (1 << 26)
/* LVDS_GEN_CNTL bit constants */
#define LVDS_ON (1 << 0)
#define LVDS_DISPLAY_DIS (1 << 1)
#define LVDS_PANEL_TYPE (1 << 2)
#define LVDS_PANEL_FORMAT (1 << 3)
#define LVDS_EN (1 << 7)
#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
#define LVDS_BL_MOD_LEVEL_SHIFT 8
#define LVDS_BL_MOD_EN (1 << 16)
#define LVDS_DIGON (1 << 18)
#define LVDS_BLON (1 << 19)
#define LVDS_SEL_CRTC2 (1 << 23)
#define LVDS_STATE_MASK \
(LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
/* LVDS_PLL_CNTL bit constatns */
#define HSYNC_DELAY_SHIFT 0x1c
#define HSYNC_DELAY_MASK (0xf << 0x1c)
/* TMDS_TRANSMITTER_CNTL bit constants */
#define TMDS_PLL_EN (1 << 0)
#define TMDS_PLLRST (1 << 1)
#define TMDS_RAN_PAT_RST (1 << 7)
#define TMDS_ICHCSEL (1 << 28)
/* FP_HORZ_STRETCH bit constants */
#define HORZ_STRETCH_RATIO_MASK 0xffff
#define HORZ_STRETCH_RATIO_MAX 4096
#define HORZ_PANEL_SIZE (0x1ff << 16)
#define HORZ_PANEL_SHIFT 16
#define HORZ_STRETCH_PIXREP (0 << 25)
#define HORZ_STRETCH_BLEND (1 << 26)
#define HORZ_STRETCH_ENABLE (1 << 25)
#define HORZ_AUTO_RATIO (1 << 27)
#define HORZ_FP_LOOP_STRETCH (0x7 << 28)
#define HORZ_AUTO_RATIO_INC (1 << 31)
/* FP_VERT_STRETCH bit constants */
#define VERT_STRETCH_RATIO_MASK 0xfff
#define VERT_STRETCH_RATIO_MAX 4096
#define VERT_PANEL_SIZE (0xfff << 12)
#define VERT_PANEL_SHIFT 12
#define VERT_STRETCH_LINREP (0 << 26)
#define VERT_STRETCH_BLEND (1 << 26)
#define VERT_STRETCH_ENABLE (1 << 25)
#define VERT_AUTO_RATIO_EN (1 << 27)
#define VERT_FP_LOOP_STRETCH (0x7 << 28)
#define VERT_STRETCH_RESERVED 0xf1000000
/* DAC_CNTL bit constants */
#define DAC_8BIT_EN 0x00000100
#define DAC_4BPP_PIX_ORDER 0x00000200
#define DAC_CRC_EN 0x00080000
#define DAC_MASK_ALL (0xff << 24)
#define DAC_PDWN (1 << 15)
#define DAC_EXPAND_MODE (1 << 14)
#define DAC_VGA_ADR_EN (1 << 13)
#define DAC_RANGE_CNTL (3 << 0)
#define DAC_RANGE_CNTL_MASK 0x03
#define DAC_BLANKING (1 << 2)
#define DAC_CMP_EN (1 << 3)
#define DAC_CMP_OUTPUT (1 << 7)
/* DAC_CNTL2 bit constants */
#define DAC2_EXPAND_MODE (1 << 14)
#define DAC2_CMP_EN (1 << 7)
#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
/* DAC_EXT_CNTL bit constants */
#define DAC_FORCE_BLANK_OFF_EN (1 << 4)
#define DAC_FORCE_DATA_EN (1 << 5)
#define DAC_FORCE_DATA_SEL_MASK (3 << 6)
#define DAC_FORCE_DATA_MASK 0x0003ff00
#define DAC_FORCE_DATA_SHIFT 8
/* GEN_RESET_CNTL bit constants */
#define SOFT_RESET_GUI 0x00000001
#define SOFT_RESET_VCLK 0x00000100
#define SOFT_RESET_PCLK 0x00000200
#define SOFT_RESET_ECP 0x00000400
#define SOFT_RESET_DISPENG_XCLK 0x00000800
/* MEM_CNTL bit constants */
#define MEM_CTLR_STATUS_IDLE 0x00000000
#define MEM_CTLR_STATUS_BUSY 0x00100000
#define MEM_SEQNCR_STATUS_IDLE 0x00000000
#define MEM_SEQNCR_STATUS_BUSY 0x00200000
#define MEM_ARBITER_STATUS_IDLE 0x00000000
#define MEM_ARBITER_STATUS_BUSY 0x00400000
#define MEM_REQ_UNLOCK 0x00000000
#define MEM_REQ_LOCK 0x00800000
#define MEM_NUM_CHANNELS_MASK 0x00000001
#define MEM_USE_B_CH_ONLY 0x00000002
#define RV100_MEM_HALF_MODE 0x00000008
#define R300_MEM_NUM_CHANNELS_MASK 0x00000003
#define R300_MEM_USE_CD_CH_ONLY 0x00000004
/* RBBM_SOFT_RESET bit constants */
#define SOFT_RESET_CP (1 << 0)
#define SOFT_RESET_HI (1 << 1)
#define SOFT_RESET_SE (1 << 2)
#define SOFT_RESET_RE (1 << 3)
#define SOFT_RESET_PP (1 << 4)
#define SOFT_RESET_E2 (1 << 5)
#define SOFT_RESET_RB (1 << 6)
#define SOFT_RESET_HDP (1 << 7)
/* SURFACE_CNTL bit consants */
#define SURF_TRANSLATION_DIS (1 << 8)
#define NONSURF_AP0_SWP_16BPP (1 << 20)
#define NONSURF_AP0_SWP_32BPP (1 << 21)
#define NONSURF_AP1_SWP_16BPP (1 << 22)
#define NONSURF_AP1_SWP_32BPP (1 << 23)
#define R200_SURF_TILE_COLOR_MACRO (1 << 16)
/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
/* MM_INDEX bit constants */
#define MM_APER 0x80000000
/* CLR_CMP_CNTL bit constants */
#define COMPARE_SRC_FALSE 0x00000000
#define COMPARE_SRC_TRUE 0x00000001
#define COMPARE_SRC_NOT_EQUAL 0x00000004
#define COMPARE_SRC_EQUAL 0x00000005
#define COMPARE_SRC_EQUAL_FLIP 0x00000007
#define COMPARE_DST_FALSE 0x00000000
#define COMPARE_DST_TRUE 0x00000100
#define COMPARE_DST_NOT_EQUAL 0x00000400
#define COMPARE_DST_EQUAL 0x00000500
#define COMPARE_DESTINATION 0x00000000
#define COMPARE_SOURCE 0x01000000
#define COMPARE_SRC_AND_DST 0x02000000
/* DP_CNTL bit constants */
#define DST_X_RIGHT_TO_LEFT 0x00000000
#define DST_X_LEFT_TO_RIGHT 0x00000001
#define DST_Y_BOTTOM_TO_TOP 0x00000000
#define DST_Y_TOP_TO_BOTTOM 0x00000002
#define DST_X_MAJOR 0x00000000
#define DST_Y_MAJOR 0x00000004
#define DST_X_TILE 0x00000008
#define DST_Y_TILE 0x00000010
#define DST_LAST_PEL 0x00000020
#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
#define DST_BRES_SIGN 0x00000100
#define DST_HOST_BIG_ENDIAN_EN 0x00000200
#define DST_POLYLINE_NONLAST 0x00008000
#define DST_RASTER_STALL 0x00010000
#define DST_POLY_EDGE 0x00040000
/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
#define DST_X_MAJOR_S 0x00000000
#define DST_Y_MAJOR_S 0x00000001
#define DST_Y_BOTTOM_TO_TOP_S 0x00000000
#define DST_Y_TOP_TO_BOTTOM_S 0x00008000
#define DST_X_RIGHT_TO_LEFT_S 0x00000000
#define DST_X_LEFT_TO_RIGHT_S 0x80000000
/* DP_DATATYPE bit constants */
#define DST_8BPP 0x00000002
#define DST_15BPP 0x00000003
#define DST_16BPP 0x00000004
#define DST_24BPP 0x00000005
#define DST_32BPP 0x00000006
#define DST_8BPP_RGB332 0x00000007
#define DST_8BPP_Y8 0x00000008
#define DST_8BPP_RGB8 0x00000009
#define DST_16BPP_VYUY422 0x0000000b
#define DST_16BPP_YVYU422 0x0000000c
#define DST_32BPP_AYUV444 0x0000000e
#define DST_16BPP_ARGB4444 0x0000000f
#define BRUSH_SOLIDCOLOR 0x00000d00
#define SRC_MONO 0x00000000
#define SRC_MONO_LBKGD 0x00010000
#define SRC_DSTCOLOR 0x00030000
#define BYTE_ORDER_MSB_TO_LSB 0x00000000
#define BYTE_ORDER_LSB_TO_MSB 0x40000000
#define DP_CONVERSION_TEMP 0x80000000
#define HOST_BIG_ENDIAN_EN (1 << 29)
/* DP_GUI_MASTER_CNTL bit constants */
#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
#define GMC_SRC_CLIP_DEFAULT 0x00000000
#define GMC_SRC_CLIP_LEAVE 0x00000004
#define GMC_DST_CLIP_DEFAULT 0x00000000
#define GMC_DST_CLIP_LEAVE 0x00000008
#define GMC_BRUSH_8x8MONO 0x00000000
#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
#define GMC_BRUSH_8x1MONO 0x00000020
#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
#define GMC_BRUSH_1x8MONO 0x00000040
#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
#define GMC_BRUSH_32x1MONO 0x00000060
#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
#define GMC_BRUSH_32x32MONO 0x00000080
#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
#define GMC_BRUSH_8x8COLOR 0x000000a0
#define GMC_BRUSH_8x1COLOR 0x000000b0
#define GMC_BRUSH_1x8COLOR 0x000000c0
#define GMC_BRUSH_SOLID_COLOR 0x000000d0
#define GMC_DST_8BPP 0x00000200
#define GMC_DST_15BPP 0x00000300
#define GMC_DST_16BPP 0x00000400
#define GMC_DST_24BPP 0x00000500
#define GMC_DST_32BPP 0x00000600
#define GMC_DST_8BPP_RGB332 0x00000700
#define GMC_DST_8BPP_Y8 0x00000800
#define GMC_DST_8BPP_RGB8 0x00000900
#define GMC_DST_16BPP_VYUY422 0x00000b00
#define GMC_DST_16BPP_YVYU422 0x00000c00
#define GMC_DST_32BPP_AYUV444 0x00000e00
#define GMC_DST_16BPP_ARGB4444 0x00000f00
#define GMC_SRC_MONO 0x00000000
#define GMC_SRC_MONO_LBKGD 0x00001000
#define GMC_SRC_DSTCOLOR 0x00003000
#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
#define GMC_DP_SRC_RECT 0x02000000
#define GMC_DP_SRC_HOST 0x03000000
#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
#define GMC_3D_FCN_EN_CLR 0x00000000
#define GMC_3D_FCN_EN_SET 0x08000000
#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
#define GMC_AUX_CLIP_LEAVE 0x00000000
#define GMC_AUX_CLIP_CLEAR 0x20000000
#define GMC_WRITE_MASK_LEAVE 0x00000000
#define GMC_WRITE_MASK_SET 0x40000000
#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
#define GMC_SRC_DATATYPE_COLOR (3 << 12)
#define ROP3_S 0x00cc0000
#define ROP3_SRCCOPY 0x00cc0000
#define ROP3_P 0x00f00000
#define ROP3_PATCOPY 0x00f00000
#define DP_SRC_SOURCE_MASK (7 << 24)
#define GMC_BRUSH_NONE (15 << 4)
#define DP_SRC_SOURCE_MEMORY (2 << 24)
#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
/* DP_MIX bit constants */
#define DP_SRC_RECT 0x00000200
#define DP_SRC_HOST 0x00000300
#define DP_SRC_HOST_BYTEALIGN 0x00000400
/* MPLL_CNTL bit constants */
#define MPLL_RESET 0x00000001
/* MDLL_CKO bit constants */
#define MCKOA_SLEEP 0x00000001
#define MCKOA_RESET 0x00000002
#define MCKOA_REF_SKEW_MASK 0x00000700
#define MCKOA_FB_SKEW_MASK 0x00007000
/* MDLL_RDCKA bit constants */
#define MRDCKA0_SLEEP 0x00000001
#define MRDCKA0_RESET 0x00000002
#define MRDCKA1_SLEEP 0x00010000
#define MRDCKA1_RESET 0x00020000
/* VCLK_ECP_CNTL constants */
#define VCLK_SRC_SEL_MASK 0x03
#define VCLK_SRC_SEL_CPUCLK 0x00
#define VCLK_SRC_SEL_PSCANCLK 0x01
#define VCLK_SRC_SEL_BYTECLK 0x02
#define VCLK_SRC_SEL_PPLLCLK 0x03
#define PIXCLK_ALWAYS_ONb 0x00000040
#define PIXCLK_DAC_ALWAYS_ONb 0x00000080
/* BUS_CNTL1 constants */
#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
#define BUS_CNTL1_AGPCLK_VALID 0x80000000
/* PLL_PWRMGT_CNTL constants */
#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
/* TV_DAC_CNTL constants */
#define TV_DAC_CNTL_BGSLEEP 0x00000040
#define TV_DAC_CNTL_DETECT 0x00000010
#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
#define TV_DAC_CNTL_BGADJ__SHIFT 16
#define TV_DAC_CNTL_DACADJ__SHIFT 20
#define TV_DAC_CNTL_RDACPD 0x01000000
#define TV_DAC_CNTL_GDACPD 0x02000000
#define TV_DAC_CNTL_BDACPD 0x04000000
/* DISP_MISC_CNTL constants */
#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
/* DISP_PWR_MAN constants */
#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
/* masks */
#define CONFIG_MEMSIZE_MASK 0x1f000000
#define MEM_CFG_TYPE 0x40000000
#define DST_OFFSET_MASK 0x003fffff
#define DST_PITCH_MASK 0x3fc00000
#define DEFAULT_TILE_MASK 0xc0000000
#define PPLL_DIV_SEL_MASK 0x00000300
#define PPLL_RESET 0x00000001
#define PPLL_SLEEP 0x00000002
#define PPLL_ATOMIC_UPDATE_EN 0x00010000
#define PPLL_REF_DIV_MASK 0x000003ff
#define PPLL_FB3_DIV_MASK 0x000007ff
#define PPLL_POST3_DIV_MASK 0x00070000
#define PPLL_ATOMIC_UPDATE_R 0x00008000
#define PPLL_ATOMIC_UPDATE_W 0x00008000
#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
#define R300_PPLL_REF_DIV_ACC_SHIFT 18
#define GUI_ACTIVE 0x80000000
#define MC_IND_INDEX 0x01F8
#define MC_IND_DATA 0x01FC
/* PAD_CTLR_STRENGTH */
#define PAD_MANUAL_OVERRIDE 0x80000000
/* pllCLK_PIN_CNTL */
#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
#define CLK_PIN_CNTL__OSC_EN 0x00000001L
#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
#define CLK_PIN_CNTL__CG_SPARE 0x00004000L
#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
/* pllCLK_PWRMGT_CNTL */
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
/* pllP2PLL_CNTL */
#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
#define P2PLL_CNTL__P2PLL_RESET 0x00000001L
#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
/* pllPIXCLKS_CNTL */
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
/* pllPIXCLKS_CNTL */
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
/* pllP2PLL_DIV_0 */
#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
/* pllSCLK_CNTL */
#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
#define SCLK_CNTL__FORCE_DISP2 0x00008000L
#define SCLK_CNTL__FORCE_CP 0x00010000L
#define SCLK_CNTL__FORCE_HDP 0x00020000L
#define SCLK_CNTL__FORCE_DISP1 0x00040000L
#define SCLK_CNTL__FORCE_TOP 0x00080000L
#define SCLK_CNTL__FORCE_E2 0x00100000L
#define SCLK_CNTL__FORCE_SE 0x00200000L
#define SCLK_CNTL__FORCE_IDCT 0x00400000L
#define SCLK_CNTL__FORCE_VIP 0x00800000L
#define SCLK_CNTL__FORCE_RE 0x01000000L
#define SCLK_CNTL__FORCE_PB 0x02000000L
#define SCLK_CNTL__FORCE_TAM 0x04000000L
#define SCLK_CNTL__FORCE_TDM 0x08000000L
#define SCLK_CNTL__FORCE_RB 0x10000000L
#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
#define SCLK_CNTL__FORCE_OV0 0x80000000L
#define SCLK_CNTL__R300_FORCE_VAP (1<<21)
#define SCLK_CNTL__R300_FORCE_SR (1<<25)
#define SCLK_CNTL__R300_FORCE_PX (1<<26)
#define SCLK_CNTL__R300_FORCE_TX (1<<27)
#define SCLK_CNTL__R300_FORCE_US (1<<28)
#define SCLK_CNTL__R300_FORCE_SU (1<<30)
#define SCLK_CNTL__FORCEON_MASK 0xffff8000L
/* pllSCLK_CNTL2 */
#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
#define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
#define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
#define SCLK_CNTL2__R300_FORCE_GA (1<<15)
/* SCLK_MORE_CNTL */
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
#define SCLK_MORE_CNTL__FORCEON 0x00000700L
/* MCLK_CNTL */
#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
#define MCLK_CNTL__FORCE_MCLKA 0x00010000L
#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
#define MCLK_CNTL__FORCE_MCLKB 0x00020000L
#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
#define MCLK_CNTL__FORCE_YCLKA 0x00040000L
#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
#define MCLK_CNTL__FORCE_YCLKB 0x00080000L
#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
#define MCLK_CNTL__FORCE_MC 0x00100000L
#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
#define MCLK_CNTL__FORCE_AIC 0x00200000L
#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
/* MCLK_MISC */
#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
#define MCLK_MISC__DLL_READY_LAT 0x00000100L
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
/* VCLK_ECP_CNTL */
#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
/* PLL_PWRMGT_CNTL */
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
/* CLK_PWRMGT_CNTL */
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
/* BUS_CNTL1 */
#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
#define BUS_CNTL1__AGPCLK_VALID 0x80000000L
/* BUS_CNTL1 */
#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
/* CRTC_OFFSET_CNTL */
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
/* CRTC_GEN_CNTL */
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
/* CRTC2_GEN_CNTL */
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
/* AGP_CNTL */
#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
#define AGP_CNTL__EN_2X_STBB 0x00000400L
#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
#define AGP_CNTL__SBA_DIS_MASK 0x00001000L
#define AGP_CNTL__SBA_DIS 0x00001000L
#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
#define AGP_CNTL__AGP_REV_ID 0x00002000L
#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
#define AGP_CNTL__FORCE_INT_VREF 0x00010000L
#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
#define AGP_CNTL__EN_RBFCALM 0x00800000L
#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
#define AGP_CNTL__DIS_RBF_MASK 0x02000000L
#define AGP_CNTL__DIS_RBF 0x02000000L
#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
/* AGP_CNTL */
#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
/* DISP_MISC_CNTL */
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
/* DISP_PWR_MAN */
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
/* MC_IND_INDEX */
#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
/* MC_IND_DATA */
#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
/* MC_CHP_IO_CNTL_A1 */
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
/* MC_CHP_IO_CNTL_B1 */
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
/* MC_CHP_IO_CNTL_A1 */
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
/* MC_CHP_IO_CNTL_B1 */
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
/* MEM_SDRAM_MODE_REG */
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
/* MEM_SDRAM_MODE_REG */
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
/* MEM_REFRESH_CNTL */
#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
/* MC_STATUS */
#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
#define MC_STATUS__MC_IDLE_MASK 0x00000004L
#define MC_STATUS__MC_IDLE 0x00000004L
#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
/* MDLL_CKO */
#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
#define MDLL_CKO__MCKOA_RESET 0x00000002L
#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
#define MDLL_CKO__MCKOB_SLEEP 0x00010000L
#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
#define MDLL_CKO__MCKOB_RESET 0x00020000L
#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
/* MDLL_RDCKA */
#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
/* MDLL_RDCKB */
#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
#define pllCLK_PIN_CNTL 0x0001
#define pllPPLL_CNTL 0x0002
#define pllPPLL_REF_DIV 0x0003
#define pllPPLL_DIV_0 0x0004
#define pllPPLL_DIV_1 0x0005
#define pllPPLL_DIV_2 0x0006
#define pllPPLL_DIV_3 0x0007
#define pllVCLK_ECP_CNTL 0x0008
#define pllHTOTAL_CNTL 0x0009
#define pllM_SPLL_REF_FB_DIV 0x000A
#define pllAGP_PLL_CNTL 0x000B
#define pllSPLL_CNTL 0x000C
#define pllSCLK_CNTL 0x000D
#define pllMPLL_CNTL 0x000E
#define pllMDLL_CKO 0x000F
#define pllMDLL_RDCKA 0x0010
#define pllMDLL_RDCKB 0x0011
#define pllMCLK_CNTL 0x0012
#define pllPLL_TEST_CNTL 0x0013
#define pllCLK_PWRMGT_CNTL 0x0014
#define pllPLL_PWRMGT_CNTL 0x0015
#define pllCG_TEST_MACRO_RW_WRITE 0x0016
#define pllCG_TEST_MACRO_RW_READ 0x0017
#define pllCG_TEST_MACRO_RW_DATA 0x0018
#define pllCG_TEST_MACRO_RW_CNTL 0x0019
#define pllDISP_TEST_MACRO_RW_WRITE 0x001A
#define pllDISP_TEST_MACRO_RW_READ 0x001B
#define pllDISP_TEST_MACRO_RW_DATA 0x001C
#define pllDISP_TEST_MACRO_RW_CNTL 0x001D
#define pllSCLK_CNTL2 0x001E
#define pllMCLK_MISC 0x001F
#define pllTV_PLL_FINE_CNTL 0x0020
#define pllTV_PLL_CNTL 0x0021
#define pllTV_PLL_CNTL1 0x0022
#define pllTV_DTO_INCREMENTS 0x0023
#define pllSPLL_AUX_CNTL 0x0024
#define pllMPLL_AUX_CNTL 0x0025
#define pllP2PLL_CNTL 0x002A
#define pllP2PLL_REF_DIV 0x002B
#define pllP2PLL_DIV_0 0x002C
#define pllPIXCLKS_CNTL 0x002D
#define pllHTOTAL2_CNTL 0x002E
#define pllSSPLL_CNTL 0x0030
#define pllSSPLL_REF_DIV 0x0031
#define pllSSPLL_DIV_0 0x0032
#define pllSS_INT_CNTL 0x0033
#define pllSS_TST_CNTL 0x0034
#define pllSCLK_MORE_CNTL 0x0035
#define ixMC_PERF_CNTL 0x0000
#define ixMC_PERF_SEL 0x0001
#define ixMC_PERF_REGION_0 0x0002
#define ixMC_PERF_REGION_1 0x0003
#define ixMC_PERF_COUNT_0 0x0004
#define ixMC_PERF_COUNT_1 0x0005
#define ixMC_PERF_COUNT_2 0x0006
#define ixMC_PERF_COUNT_3 0x0007
#define ixMC_PERF_COUNT_MEMCH_A 0x0008
#define ixMC_PERF_COUNT_MEMCH_B 0x0009
#define ixMC_IMP_CNTL 0x000A
#define ixMC_CHP_IO_CNTL_A0 0x000B
#define ixMC_CHP_IO_CNTL_A1 0x000C
#define ixMC_CHP_IO_CNTL_B0 0x000D
#define ixMC_CHP_IO_CNTL_B1 0x000E
#define ixMC_IMP_CNTL_0 0x000F
#define ixTC_MISMATCH_1 0x0010
#define ixTC_MISMATCH_2 0x0011
#define ixMC_BIST_CTRL 0x0012
#define ixREG_COLLAR_WRITE 0x0013
#define ixREG_COLLAR_READ 0x0014
#define ixR300_MC_IMP_CNTL 0x0018
#define ixR300_MC_CHP_IO_CNTL_A0 0x0019
#define ixR300_MC_CHP_IO_CNTL_A1 0x001a
#define ixR300_MC_CHP_IO_CNTL_B0 0x001b
#define ixR300_MC_CHP_IO_CNTL_B1 0x001c
#define ixR300_MC_CHP_IO_CNTL_C0 0x001d
#define ixR300_MC_CHP_IO_CNTL_C1 0x001e
#define ixR300_MC_CHP_IO_CNTL_D0 0x001f
#define ixR300_MC_CHP_IO_CNTL_D1 0x0020
#define ixR300_MC_IMP_CNTL_0 0x0021
#define ixR300_MC_ELPIDA_CNTL 0x0022
#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
#define ixR300_MC_READ_CNTL_CD 0x0024
#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
#define ixR300_MC_DEBUG_CNTL 0x0026
#define ixR300_MC_BIST_CNTL_0 0x0028
#define ixR300_MC_BIST_CNTL_1 0x0029
#define ixR300_MC_BIST_CNTL_2 0x002a
#define ixR300_MC_BIST_CNTL_3 0x002b
#define ixR300_MC_BIST_CNTL_4 0x002c
#define ixR300_MC_BIST_CNTL_5 0x002d
#define ixR300_MC_IMP_STATUS 0x002e
#define ixR300_MC_DLL_CNTL 0x002f
#define NB_TOM 0x15C
#endif /* _RADEON_H */
|
1001-study-uboot
|
include/radeon.h
|
C
|
gpl3
| 81,765
|
/*
* (C) Copyright 2003
* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ACEX1K_H_
#define _ACEX1K_H_
#include <altera.h>
extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size);
extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize);
extern int ACEX1K_info(Altera_desc *desc);
extern int CYC2_load(Altera_desc *desc, const void *image, size_t size);
extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize);
extern int CYC2_info(Altera_desc *desc);
/* Slave Serial Implementation function table */
typedef struct {
Altera_pre_fn pre;
Altera_config_fn config;
Altera_clk_fn clk;
Altera_status_fn status;
Altera_done_fn done;
Altera_data_fn data;
Altera_abort_fn abort;
Altera_post_fn post;
} Altera_ACEX1K_Passive_Serial_fns;
/* Slave Serial Implementation function table */
typedef struct {
Altera_pre_fn pre;
Altera_config_fn config;
Altera_status_fn status;
Altera_done_fn done;
Altera_write_fn write;
Altera_abort_fn abort;
Altera_post_fn post;
} Altera_CYC2_Passive_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* ACEX1K */
/* FIXME: Which size do we mean?
* Datasheet says 1337000/8=167125Bytes,
* Filesize of an *.rbf file is 166965 Bytes
*/
#if 0
#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */
#endif
#define Altera_EP1K100_SIZE (166965*8)
#define Altera_EP2C8_SIZE 247942
#define Altera_EP2C20_SIZE 586562
#define Altera_EP2C35_SIZE 883905
#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */
/* Descriptor Macros
*********************************************************************/
/* ACEX1K devices */
#define Altera_EP1K100_DESC(iface, fn_table, cookie) \
{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie }
#endif /* _ACEX1K_H_ */
|
1001-study-uboot
|
include/ACEX1K.h
|
C
|
gpl3
| 2,747
|
#ifndef _NODE_INFO
#define _NODE_INFO
/*
* Info we use to search for a flash node in DTB.
*/
struct node_info {
const char *compat; /* compatible string */
int type; /* mtd flash type */
};
#endif
|
1001-study-uboot
|
include/mtd_node.h
|
C
|
gpl3
| 203
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _IDE_H
#define _IDE_H
#define IDE_BUS(dev) (dev >> 1)
#define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
#ifdef CONFIG_IDE_LED
/*
* LED Port
*/
#define LED_PORT ((uchar *)(PER8_BASE + 0x3000))
#define LED_IDE1 0x01
#define LED_IDE2 0x02
#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
#endif /* CONFIG_IDE_LED */
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
#else
typedef ulong lbaint_t;
#endif
/*
* Function Prototypes
*/
void ide_init(void);
ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer);
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev);
#endif
#if defined(CONFIG_IDE_AHB)
unsigned char ide_read_register(int dev, unsigned int port);
void ide_write_register(int dev, unsigned int port, unsigned char val);
void ide_read_data(int dev, ulong *sect_buf, int words);
void ide_write_data(int dev, ulong *sect_buf, int words);
#endif
#endif /* _IDE_H */
|
1001-study-uboot
|
include/ide.h
|
C
|
gpl3
| 1,950
|
/*
* libfdt - Flat Device Tree manipulation (build/run environment adaptation)
* Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
* Original version written by David Gibson, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public License
* as published by the Free Software Foundation; either version 2.1 of
* the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _LIBFDT_ENV_H
#define _LIBFDT_ENV_H
#include "compiler.h"
extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
#define fdt32_to_cpu(x) be32_to_cpu(x)
#define cpu_to_fdt32(x) cpu_to_be32(x)
#define fdt64_to_cpu(x) be64_to_cpu(x)
#define cpu_to_fdt64(x) cpu_to_be64(x)
#endif /* _LIBFDT_ENV_H */
|
1001-study-uboot
|
include/libfdt_env.h
|
C
|
gpl3
| 1,289
|
/*
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __CIRCBUF_H__
#define __CIRCBUF_H__
typedef struct circbuf {
unsigned int size; /* current number of bytes held */
unsigned int totalsize; /* number of bytes allocated */
char *top; /* pointer to current buffer start */
char *tail; /* pointer to space for next element */
char *data; /* all data */
char *end; /* end of data buffer */
} circbuf_t;
int buf_init (circbuf_t * buf, unsigned int size);
int buf_free (circbuf_t * buf);
int buf_pop (circbuf_t * buf, char *dest, unsigned int len);
int buf_push (circbuf_t * buf, const char *src, unsigned int len);
#endif
|
1001-study-uboot
|
include/circbuf.h
|
C
|
gpl3
| 1,384
|
/*
* PCI Class, Vendor and Device IDs
*
* Please keep sorted.
*
* Do not add new entries to this file unless the definitions
* are shared between multiple drivers.
*/
/* Device classes and subclasses */
#define PCI_CLASS_NOT_DEFINED 0x0000
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
#define PCI_BASE_CLASS_STORAGE 0x01
#define PCI_CLASS_STORAGE_SCSI 0x0100
#define PCI_CLASS_STORAGE_IDE 0x0101
#define PCI_CLASS_STORAGE_FLOPPY 0x0102
#define PCI_CLASS_STORAGE_IPI 0x0103
#define PCI_CLASS_STORAGE_RAID 0x0104
#define PCI_CLASS_STORAGE_SATA 0x0106
#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
#define PCI_CLASS_STORAGE_SAS 0x0107
#define PCI_CLASS_STORAGE_OTHER 0x0180
#define PCI_BASE_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
#define PCI_CLASS_NETWORK_FDDI 0x0202
#define PCI_CLASS_NETWORK_ATM 0x0203
#define PCI_CLASS_NETWORK_OTHER 0x0280
#define PCI_BASE_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_CLASS_DISPLAY_XGA 0x0301
#define PCI_CLASS_DISPLAY_3D 0x0302
#define PCI_CLASS_DISPLAY_OTHER 0x0380
#define PCI_BASE_CLASS_MULTIMEDIA 0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
#define PCI_BASE_CLASS_MEMORY 0x05
#define PCI_CLASS_MEMORY_RAM 0x0500
#define PCI_CLASS_MEMORY_FLASH 0x0501
#define PCI_CLASS_MEMORY_OTHER 0x0580
#define PCI_BASE_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_EISA 0x0602
#define PCI_CLASS_BRIDGE_MC 0x0603
#define PCI_CLASS_BRIDGE_PCI 0x0604
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
#define PCI_CLASS_BRIDGE_NUBUS 0x0606
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_BASE_CLASS_COMMUNICATION 0x07
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
#define PCI_BASE_CLASS_SYSTEM 0x08
#define PCI_CLASS_SYSTEM_PIC 0x0800
#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
#define PCI_CLASS_SYSTEM_DMA 0x0801
#define PCI_CLASS_SYSTEM_TIMER 0x0802
#define PCI_CLASS_SYSTEM_RTC 0x0803
#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
#define PCI_CLASS_SYSTEM_SDHCI 0x0805
#define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_BASE_CLASS_INPUT 0x09
#define PCI_CLASS_INPUT_KEYBOARD 0x0900
#define PCI_CLASS_INPUT_PEN 0x0901
#define PCI_CLASS_INPUT_MOUSE 0x0902
#define PCI_CLASS_INPUT_SCANNER 0x0903
#define PCI_CLASS_INPUT_GAMEPORT 0x0904
#define PCI_CLASS_INPUT_OTHER 0x0980
#define PCI_BASE_CLASS_DOCKING 0x0a
#define PCI_CLASS_DOCKING_GENERIC 0x0a00
#define PCI_CLASS_DOCKING_OTHER 0x0a80
#define PCI_BASE_CLASS_PROCESSOR 0x0b
#define PCI_CLASS_PROCESSOR_386 0x0b00
#define PCI_CLASS_PROCESSOR_486 0x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
#define PCI_CLASS_PROCESSOR_CO 0x0b40
#define PCI_BASE_CLASS_SERIAL 0x0c
#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
#define PCI_CLASS_SERIAL_ACCESS 0x0c01
#define PCI_CLASS_SERIAL_SSA 0x0c02
#define PCI_CLASS_SERIAL_USB 0x0c03
#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300
#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310
#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
#define PCI_CLASS_SERIAL_USB_XHCI 0x0c0330
#define PCI_CLASS_SERIAL_FIBER 0x0c04
#define PCI_CLASS_SERIAL_SMBUS 0x0c05
#define PCI_BASE_CLASS_WIRELESS 0x0d
#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
#define PCI_CLASS_WIRELESS_WHCI 0x0d1010
#define PCI_BASE_CLASS_INTELLIGENT 0x0e
#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
#define PCI_BASE_CLASS_SATELLITE 0x0f
#define PCI_CLASS_SATELLITE_TV 0x0f00
#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
#define PCI_CLASS_SATELLITE_VOICE 0x0f03
#define PCI_CLASS_SATELLITE_DATA 0x0f04
#define PCI_BASE_CLASS_CRYPT 0x10
#define PCI_CLASS_CRYPT_NETWORK 0x1000
#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
#define PCI_CLASS_CRYPT_OTHER 0x1080
#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
#define PCI_CLASS_SP_DPIO 0x1100
#define PCI_CLASS_SP_OTHER 0x1180
#define PCI_CLASS_OTHERS 0xff
/* Vendors and devices. Sort key: vendor first, device next. */
#define PCI_VENDOR_ID_TTTECH 0x0357
#define PCI_DEVICE_ID_TTTECH_MC322 0x000a
#define PCI_VENDOR_ID_DYNALINK 0x0675
#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702
#define PCI_VENDOR_ID_BERKOM 0x0871
#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1
#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2
#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4
#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8
#define PCI_VENDOR_ID_COMPAQ 0x0e11
#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508
#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc
#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10
#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32
#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34
#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35
#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40
#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43
#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011
#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060
#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178
#define PCI_DEVICE_ID_COMPAQ_CISSC 0x46
#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130
#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150
#define PCI_VENDOR_ID_NCR 0x1000
#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
#define PCI_DEVICE_ID_NCR_53C810 0x0001
#define PCI_DEVICE_ID_NCR_53C820 0x0002
#define PCI_DEVICE_ID_NCR_53C825 0x0003
#define PCI_DEVICE_ID_NCR_53C815 0x0004
#define PCI_DEVICE_ID_LSI_53C810AP 0x0005
#define PCI_DEVICE_ID_NCR_53C860 0x0006
#define PCI_DEVICE_ID_LSI_53C1510 0x000a
#define PCI_DEVICE_ID_NCR_53C896 0x000b
#define PCI_DEVICE_ID_NCR_53C895 0x000c
#define PCI_DEVICE_ID_NCR_53C885 0x000d
#define PCI_DEVICE_ID_NCR_53C875 0x000f
#define PCI_DEVICE_ID_NCR_53C1510 0x0010
#define PCI_DEVICE_ID_LSI_53C895A 0x0012
#define PCI_DEVICE_ID_LSI_53C875A 0x0013
#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020
#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021
#define PCI_DEVICE_ID_LSI_53C1030 0x0030
#define PCI_DEVICE_ID_LSI_1030_53C1035 0x0032
#define PCI_DEVICE_ID_LSI_53C1035 0x0040
#define PCI_DEVICE_ID_NCR_53C875J 0x008f
#define PCI_DEVICE_ID_LSI_FC909 0x0621
#define PCI_DEVICE_ID_LSI_FC929 0x0622
#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623
#define PCI_DEVICE_ID_LSI_FC919 0x0624
#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625
#define PCI_DEVICE_ID_LSI_FC929X 0x0626
#define PCI_DEVICE_ID_LSI_FC939X 0x0642
#define PCI_DEVICE_ID_LSI_FC949X 0x0640
#define PCI_DEVICE_ID_LSI_FC949ES 0x0646
#define PCI_DEVICE_ID_LSI_FC919X 0x0628
#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701
#define PCI_DEVICE_ID_LSI_61C102 0x0901
#define PCI_DEVICE_ID_LSI_63C815 0x1000
#define PCI_DEVICE_ID_LSI_SAS1064 0x0050
#define PCI_DEVICE_ID_LSI_SAS1064R 0x0411
#define PCI_DEVICE_ID_LSI_SAS1066 0x005E
#define PCI_DEVICE_ID_LSI_SAS1068 0x0054
#define PCI_DEVICE_ID_LSI_SAS1064A 0x005C
#define PCI_DEVICE_ID_LSI_SAS1064E 0x0056
#define PCI_DEVICE_ID_LSI_SAS1066E 0x005A
#define PCI_DEVICE_ID_LSI_SAS1068E 0x0058
#define PCI_DEVICE_ID_LSI_SAS1078 0x0060
#define PCI_VENDOR_ID_ATI 0x1002
/* Mach64 */
#define PCI_DEVICE_ID_ATI_68800 0x4158
#define PCI_DEVICE_ID_ATI_215CT222 0x4354
#define PCI_DEVICE_ID_ATI_210888CX 0x4358
#define PCI_DEVICE_ID_ATI_215ET222 0x4554
/* Mach64 / Rage */
#define PCI_DEVICE_ID_ATI_215GB 0x4742
#define PCI_DEVICE_ID_ATI_215GD 0x4744
#define PCI_DEVICE_ID_ATI_215GI 0x4749
#define PCI_DEVICE_ID_ATI_215GP 0x4750
#define PCI_DEVICE_ID_ATI_215GQ 0x4751
#define PCI_DEVICE_ID_ATI_215XL 0x4752
#define PCI_DEVICE_ID_ATI_215GT 0x4754
#define PCI_DEVICE_ID_ATI_215GTB 0x4755
#define PCI_DEVICE_ID_ATI_215_IV 0x4756
#define PCI_DEVICE_ID_ATI_215_IW 0x4757
#define PCI_DEVICE_ID_ATI_215_IZ 0x475A
#define PCI_DEVICE_ID_ATI_210888GX 0x4758
#define PCI_DEVICE_ID_ATI_215_LB 0x4c42
#define PCI_DEVICE_ID_ATI_215_LD 0x4c44
#define PCI_DEVICE_ID_ATI_215_LG 0x4c47
#define PCI_DEVICE_ID_ATI_215_LI 0x4c49
#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D
#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E
#define PCI_DEVICE_ID_ATI_215_LR 0x4c52
#define PCI_DEVICE_ID_ATI_215_LS 0x4c53
#define PCI_DEVICE_ID_ATI_264_LT 0x4c54
/* Mach64 VT */
#define PCI_DEVICE_ID_ATI_264VT 0x5654
#define PCI_DEVICE_ID_ATI_264VU 0x5655
#define PCI_DEVICE_ID_ATI_264VV 0x5656
/* Rage128 GL */
#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245
#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246
#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x5247
/* Rage128 VR */
#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b
#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c
#define PCI_DEVICE_ID_ATI_RAGE128_SE 0x5345
#define PCI_DEVICE_ID_ATI_RAGE128_SF 0x5346
#define PCI_DEVICE_ID_ATI_RAGE128_SG 0x5347
#define PCI_DEVICE_ID_ATI_RAGE128_SH 0x5348
#define PCI_DEVICE_ID_ATI_RAGE128_SK 0x534b
#define PCI_DEVICE_ID_ATI_RAGE128_SL 0x534c
#define PCI_DEVICE_ID_ATI_RAGE128_SM 0x534d
#define PCI_DEVICE_ID_ATI_RAGE128_SN 0x534e
/* Rage128 Ultra */
#define PCI_DEVICE_ID_ATI_RAGE128_TF 0x5446
#define PCI_DEVICE_ID_ATI_RAGE128_TL 0x544c
#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452
#define PCI_DEVICE_ID_ATI_RAGE128_TS 0x5453
#define PCI_DEVICE_ID_ATI_RAGE128_TT 0x5454
#define PCI_DEVICE_ID_ATI_RAGE128_TU 0x5455
/* Rage128 M3 */
#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45
#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46
/* Rage128 M4 */
#define PCI_DEVICE_ID_ATI_RAGE128_MF 0x4d46
#define PCI_DEVICE_ID_ATI_RAGE128_ML 0x4d4c
/* Rage128 Pro GL */
#define PCI_DEVICE_ID_ATI_RAGE128_PA 0x5041
#define PCI_DEVICE_ID_ATI_RAGE128_PB 0x5042
#define PCI_DEVICE_ID_ATI_RAGE128_PC 0x5043
#define PCI_DEVICE_ID_ATI_RAGE128_PD 0x5044
#define PCI_DEVICE_ID_ATI_RAGE128_PE 0x5045
#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
/* Rage128 Pro VR */
#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047
#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048
#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049
#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A
#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B
#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C
#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D
#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E
#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F
#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050
#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051
#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052
#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053
#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054
#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055
#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056
#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057
#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058
/* Rage128 M4 */
/* Radeon R100 */
#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144
#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145
#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146
#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147
/* Radeon RV100 (VE) */
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a
/* Radeon R200 (8500) */
#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c
#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e
#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f
#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c
#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242
/* Radeon R200 (9100) */
#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d
/* Radeon RV200 (7500) */
#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157
#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158
/* Radeon NV-100 */
/* Radeon RV250 (9000) */
#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964
#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965
#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966
#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967
/* Radeon RV280 (9200) */
#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961
#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964
/* Radeon R300 (9500) */
/* Radeon R300 (9700) */
#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44
#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45
#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46
#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47
/* Radeon R350 (9800) */
/* Radeon RV350 (9600) */
/* Radeon M6 */
#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59
#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a
/* Radeon M7 */
#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57
#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58
/* Radeon M9 */
#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64
#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65
#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66
#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67
/* Radeon */
/* RadeonIGP */
#define PCI_DEVICE_ID_ATI_RS100 0xcab0
#define PCI_DEVICE_ID_ATI_RS200 0xcab2
#define PCI_DEVICE_ID_ATI_RS200_B 0xcbb2
#define PCI_DEVICE_ID_ATI_RS250 0xcab3
#define PCI_DEVICE_ID_ATI_RS300_100 0x5830
#define PCI_DEVICE_ID_ATI_RS300_133 0x5831
#define PCI_DEVICE_ID_ATI_RS300_166 0x5832
#define PCI_DEVICE_ID_ATI_RS300_200 0x5833
#define PCI_DEVICE_ID_ATI_RS350_100 0x7830
#define PCI_DEVICE_ID_ATI_RS350_133 0x7831
#define PCI_DEVICE_ID_ATI_RS350_166 0x7832
#define PCI_DEVICE_ID_ATI_RS350_200 0x7833
#define PCI_DEVICE_ID_ATI_RS400_100 0x5a30
#define PCI_DEVICE_ID_ATI_RS400_133 0x5a31
#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32
#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33
#define PCI_DEVICE_ID_ATI_RS480 0x5950
/* ATI IXP Chipset */
#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349
#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353
#define PCI_DEVICE_ID_ATI_IXP300_SMBUS 0x4363
#define PCI_DEVICE_ID_ATI_IXP300_IDE 0x4369
#define PCI_DEVICE_ID_ATI_IXP300_SATA 0x436e
#define PCI_DEVICE_ID_ATI_IXP400_SMBUS 0x4372
#define PCI_DEVICE_ID_ATI_IXP400_IDE 0x4376
#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379
#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a
#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380
#define PCI_DEVICE_ID_ATI_SBX00_SMBUS 0x4385
#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c
#define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390
#define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c
#define PCI_VENDOR_ID_VLSI 0x1004
#define PCI_DEVICE_ID_VLSI_82C592 0x0005
#define PCI_DEVICE_ID_VLSI_82C593 0x0006
#define PCI_DEVICE_ID_VLSI_82C594 0x0007
#define PCI_DEVICE_ID_VLSI_82C597 0x0009
#define PCI_DEVICE_ID_VLSI_82C541 0x000c
#define PCI_DEVICE_ID_VLSI_82C543 0x000d
#define PCI_DEVICE_ID_VLSI_82C532 0x0101
#define PCI_DEVICE_ID_VLSI_82C534 0x0102
#define PCI_DEVICE_ID_VLSI_82C535 0x0104
#define PCI_DEVICE_ID_VLSI_82C147 0x0105
#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702
/* AMD RD890 Chipset */
#define PCI_DEVICE_ID_RD890_IOMMU 0x5a23
#define PCI_VENDOR_ID_ADL 0x1005
#define PCI_DEVICE_ID_ADL_2301 0x2301
#define PCI_VENDOR_ID_NS 0x100b
#define PCI_DEVICE_ID_NS_87415 0x0002
#define PCI_DEVICE_ID_NS_87560_LIO 0x000e
#define PCI_DEVICE_ID_NS_87560_USB 0x0012
#define PCI_DEVICE_ID_NS_83815 0x0020
#define PCI_DEVICE_ID_NS_83820 0x0022
#define PCI_DEVICE_ID_NS_CS5535_ISA 0x002b
#define PCI_DEVICE_ID_NS_CS5535_IDE 0x002d
#define PCI_DEVICE_ID_NS_CS5535_AUDIO 0x002e
#define PCI_DEVICE_ID_NS_CS5535_USB 0x002f
#define PCI_DEVICE_ID_NS_GX_VIDEO 0x0030
#define PCI_DEVICE_ID_NS_SATURN 0x0035
#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500
#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501
#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502
#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503
#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504
#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505
#define PCI_DEVICE_ID_NS_SC1100_BRIDGE 0x0510
#define PCI_DEVICE_ID_NS_SC1100_SMI 0x0511
#define PCI_DEVICE_ID_NS_SC1100_XBUS 0x0515
#define PCI_DEVICE_ID_NS_87410 0xd001
#define PCI_DEVICE_ID_NS_GX_HOST_BRIDGE 0x0028
#define PCI_VENDOR_ID_TSENG 0x100c
#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202
#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205
#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206
#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207
#define PCI_DEVICE_ID_TSENG_ET6000 0x3208
#define PCI_VENDOR_ID_WEITEK 0x100e
#define PCI_DEVICE_ID_WEITEK_P9000 0x9001
#define PCI_DEVICE_ID_WEITEK_P9100 0x9100
#define PCI_VENDOR_ID_DEC 0x1011
#define PCI_DEVICE_ID_DEC_BRD 0x0001
#define PCI_DEVICE_ID_DEC_TULIP 0x0002
#define PCI_DEVICE_ID_DEC_TGA 0x0004
#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009
#define PCI_DEVICE_ID_DEC_TGA2 0x000D
#define PCI_DEVICE_ID_DEC_FDDI 0x000F
#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014
#define PCI_DEVICE_ID_DEC_21142 0x0019
#define PCI_DEVICE_ID_DEC_21052 0x0021
#define PCI_DEVICE_ID_DEC_21150 0x0022
#define PCI_DEVICE_ID_DEC_21152 0x0024
#define PCI_DEVICE_ID_DEC_21153 0x0025
#define PCI_DEVICE_ID_DEC_21154 0x0026
#define PCI_DEVICE_ID_DEC_21285 0x1065
#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046
#define PCI_VENDOR_ID_CIRRUS 0x1013
#define PCI_DEVICE_ID_CIRRUS_7548 0x0038
#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0
#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4
#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8
#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac
#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8
#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc
#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0
#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4
#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6
#define PCI_DEVICE_ID_CIRRUS_6729 0x1100
#define PCI_DEVICE_ID_CIRRUS_6832 0x1110
#define PCI_DEVICE_ID_CIRRUS_7543 0x1202
#define PCI_DEVICE_ID_CIRRUS_4610 0x6001
#define PCI_DEVICE_ID_CIRRUS_4612 0x6003
#define PCI_DEVICE_ID_CIRRUS_4615 0x6004
#define PCI_VENDOR_ID_IBM 0x1014
#define PCI_DEVICE_ID_IBM_TR 0x0018
#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e
#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc
#define PCI_DEVICE_ID_IBM_405GP 0x0156
#define PCI_DEVICE_ID_IBM_SNIPE 0x0180
#define PCI_DEVICE_ID_IBM_CITRINE 0x028C
#define PCI_DEVICE_ID_IBM_GEMSTONE 0xB166
#define PCI_DEVICE_ID_IBM_OBSIDIAN 0x02BD
#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1 0x0031
#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219
#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX 0x021A
#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM 0x0251
#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252
#define PCI_SUBVENDOR_ID_IBM 0x1014
#define PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT 0x03d4
#define PCI_VENDOR_ID_UNISYS 0x1018
#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C
#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */
#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005
#define PCI_VENDOR_ID_WD 0x101c
#define PCI_DEVICE_ID_WD_90C 0xc24a
#define PCI_VENDOR_ID_AMI 0x101e
#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960
#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010
#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060
#define PCI_VENDOR_ID_AMD 0x1022
#define PCI_DEVICE_ID_AMD_K8_NB 0x1100
#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101
#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL 0x1102
#define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
#define PCI_DEVICE_ID_AMD_10H_NB_MAP 0x1201
#define PCI_DEVICE_ID_AMD_10H_NB_DRAM 0x1202
#define PCI_DEVICE_ID_AMD_10H_NB_MISC 0x1203
#define PCI_DEVICE_ID_AMD_10H_NB_LINK 0x1204
#define PCI_DEVICE_ID_AMD_11H_NB_HT 0x1300
#define PCI_DEVICE_ID_AMD_11H_NB_MAP 0x1301
#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
#define PCI_DEVICE_ID_AMD_SCSI 0x2020
#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0
#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007
#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E
#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401
#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409
#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B
#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410
#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411
#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413
#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440
#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441
#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443
#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443
#define PCI_DEVICE_ID_AMD_OPUS_7445 0x7445
#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460
#define PCI_DEVICE_ID_AMD_8111_LPC 0x7468
#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469
#define PCI_DEVICE_ID_AMD_8111_SMBUS2 0x746a
#define PCI_DEVICE_ID_AMD_8111_SMBUS 0x746b
#define PCI_DEVICE_ID_AMD_8111_AUDIO 0x746d
#define PCI_DEVICE_ID_AMD_8151_0 0x7454
#define PCI_DEVICE_ID_AMD_8131_BRIDGE 0x7450
#define PCI_DEVICE_ID_AMD_8131_APIC 0x7451
#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458
#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS 0x780b
#define PCI_DEVICE_ID_AMD_CS5535_IDE 0x208F
#define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090
#define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091
#define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093
#define PCI_DEVICE_ID_AMD_CS5536_OHC 0x2094
#define PCI_DEVICE_ID_AMD_CS5536_EHC 0x2095
#define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096
#define PCI_DEVICE_ID_AMD_CS5536_UOC 0x2097
#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A
#define PCI_DEVICE_ID_AMD_LX_VIDEO 0x2081
#define PCI_DEVICE_ID_AMD_LX_AES 0x2082
#define PCI_DEVICE_ID_AMD_HUDSON2_IDE 0x780c
#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE 0x7800
#define PCI_VENDOR_ID_TRIDENT 0x1023
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
#define PCI_DEVICE_ID_TRIDENT_9320 0x9320
#define PCI_DEVICE_ID_TRIDENT_9388 0x9388
#define PCI_DEVICE_ID_TRIDENT_9397 0x9397
#define PCI_DEVICE_ID_TRIDENT_939A 0x939A
#define PCI_DEVICE_ID_TRIDENT_9520 0x9520
#define PCI_DEVICE_ID_TRIDENT_9525 0x9525
#define PCI_DEVICE_ID_TRIDENT_9420 0x9420
#define PCI_DEVICE_ID_TRIDENT_9440 0x9440
#define PCI_DEVICE_ID_TRIDENT_9660 0x9660
#define PCI_DEVICE_ID_TRIDENT_9750 0x9750
#define PCI_DEVICE_ID_TRIDENT_9850 0x9850
#define PCI_DEVICE_ID_TRIDENT_9880 0x9880
#define PCI_DEVICE_ID_TRIDENT_8400 0x8400
#define PCI_DEVICE_ID_TRIDENT_8420 0x8420
#define PCI_DEVICE_ID_TRIDENT_8500 0x8500
#define PCI_VENDOR_ID_AI 0x1025
#define PCI_DEVICE_ID_AI_M1435 0x1435
#define PCI_VENDOR_ID_DELL 0x1028
#define PCI_DEVICE_ID_DELL_RACIII 0x0008
#define PCI_DEVICE_ID_DELL_RAC4 0x0012
#define PCI_DEVICE_ID_DELL_PERC5 0x0015
#define PCI_VENDOR_ID_MATROX 0x102B
#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518
#define PCI_DEVICE_ID_MATROX_MIL 0x0519
#define PCI_DEVICE_ID_MATROX_MYS 0x051A
#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b
#define PCI_DEVICE_ID_MATROX_MYS_AGP 0x051e
#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f
#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10
#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000
#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001
#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520
#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521
#define PCI_DEVICE_ID_MATROX_G400 0x0525
#define PCI_DEVICE_ID_MATROX_G200EV_PCI 0x0530
#define PCI_DEVICE_ID_MATROX_G550 0x2527
#define PCI_DEVICE_ID_MATROX_VIA 0x4536
#define PCI_VENDOR_ID_CT 0x102c
#define PCI_DEVICE_ID_CT_69000 0x00c0
#define PCI_DEVICE_ID_CT_65545 0x00d8
#define PCI_DEVICE_ID_CT_65548 0x00dc
#define PCI_DEVICE_ID_CT_65550 0x00e0
#define PCI_DEVICE_ID_CT_65554 0x00e4
#define PCI_DEVICE_ID_CT_65555 0x00e5
#define PCI_DEVICE_ID_CT_69030 0x0c30
#define PCI_VENDOR_ID_MIRO 0x1031
#define PCI_DEVICE_ID_MIRO_36050 0x5601
#define PCI_DEVICE_ID_MIRO_DC10PLUS 0x7efe
#define PCI_DEVICE_ID_MIRO_DC30PLUS 0xd801
#define PCI_VENDOR_ID_NEC 0x1033
#define PCI_DEVICE_ID_NEC_CBUS_1 0x0001 /* PCI-Cbus Bridge */
#define PCI_DEVICE_ID_NEC_LOCAL 0x0002 /* Local Bridge */
#define PCI_DEVICE_ID_NEC_ATM 0x0003 /* ATM LAN Controller */
#define PCI_DEVICE_ID_NEC_R4000 0x0004 /* R4000 Bridge */
#define PCI_DEVICE_ID_NEC_486 0x0005 /* 486 Like Peripheral Bus Bridge */
#define PCI_DEVICE_ID_NEC_ACCEL_1 0x0006 /* Graphic Accelerator */
#define PCI_DEVICE_ID_NEC_UXBUS 0x0007 /* UX-Bus Bridge */
#define PCI_DEVICE_ID_NEC_ACCEL_2 0x0008 /* Graphic Accelerator */
#define PCI_DEVICE_ID_NEC_GRAPH 0x0009 /* PCI-CoreGraph Bridge */
#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */
#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */
#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */
#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */
#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b
#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e
#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */
#define PCI_DEVICE_ID_NEC_VRC5476 0x009b
#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5
#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6
#define PCI_DEVICE_ID_NEC_PC9821CS01 0x800c /* PC-9821-CS01 */
#define PCI_DEVICE_ID_NEC_PC9821NRB06 0x800d /* PC-9821NR-B06 */
#define PCI_VENDOR_ID_FD 0x1036
#define PCI_DEVICE_ID_FD_36C70 0x0000
#define PCI_VENDOR_ID_SI 0x1039
#define PCI_DEVICE_ID_SI_5591_AGP 0x0001
#define PCI_DEVICE_ID_SI_6202 0x0002
#define PCI_DEVICE_ID_SI_503 0x0008
#define PCI_DEVICE_ID_SI_ACPI 0x0009
#define PCI_DEVICE_ID_SI_SMBUS 0x0016
#define PCI_DEVICE_ID_SI_LPC 0x0018
#define PCI_DEVICE_ID_SI_5597_VGA 0x0200
#define PCI_DEVICE_ID_SI_6205 0x0205
#define PCI_DEVICE_ID_SI_501 0x0406
#define PCI_DEVICE_ID_SI_496 0x0496
#define PCI_DEVICE_ID_SI_300 0x0300
#define PCI_DEVICE_ID_SI_315H 0x0310
#define PCI_DEVICE_ID_SI_315 0x0315
#define PCI_DEVICE_ID_SI_315PRO 0x0325
#define PCI_DEVICE_ID_SI_530 0x0530
#define PCI_DEVICE_ID_SI_540 0x0540
#define PCI_DEVICE_ID_SI_550 0x0550
#define PCI_DEVICE_ID_SI_540_VGA 0x5300
#define PCI_DEVICE_ID_SI_550_VGA 0x5315
#define PCI_DEVICE_ID_SI_620 0x0620
#define PCI_DEVICE_ID_SI_630 0x0630
#define PCI_DEVICE_ID_SI_633 0x0633
#define PCI_DEVICE_ID_SI_635 0x0635
#define PCI_DEVICE_ID_SI_640 0x0640
#define PCI_DEVICE_ID_SI_645 0x0645
#define PCI_DEVICE_ID_SI_646 0x0646
#define PCI_DEVICE_ID_SI_648 0x0648
#define PCI_DEVICE_ID_SI_650 0x0650
#define PCI_DEVICE_ID_SI_651 0x0651
#define PCI_DEVICE_ID_SI_655 0x0655
#define PCI_DEVICE_ID_SI_661 0x0661
#define PCI_DEVICE_ID_SI_730 0x0730
#define PCI_DEVICE_ID_SI_733 0x0733
#define PCI_DEVICE_ID_SI_630_VGA 0x6300
#define PCI_DEVICE_ID_SI_735 0x0735
#define PCI_DEVICE_ID_SI_740 0x0740
#define PCI_DEVICE_ID_SI_741 0x0741
#define PCI_DEVICE_ID_SI_745 0x0745
#define PCI_DEVICE_ID_SI_746 0x0746
#define PCI_DEVICE_ID_SI_755 0x0755
#define PCI_DEVICE_ID_SI_760 0x0760
#define PCI_DEVICE_ID_SI_900 0x0900
#define PCI_DEVICE_ID_SI_961 0x0961
#define PCI_DEVICE_ID_SI_962 0x0962
#define PCI_DEVICE_ID_SI_963 0x0963
#define PCI_DEVICE_ID_SI_965 0x0965
#define PCI_DEVICE_ID_SI_966 0x0966
#define PCI_DEVICE_ID_SI_968 0x0968
#define PCI_DEVICE_ID_SI_1180 0x1180
#define PCI_DEVICE_ID_SI_5511 0x5511
#define PCI_DEVICE_ID_SI_5513 0x5513
#define PCI_DEVICE_ID_SI_5517 0x5517
#define PCI_DEVICE_ID_SI_5518 0x5518
#define PCI_DEVICE_ID_SI_5571 0x5571
#define PCI_DEVICE_ID_SI_5581 0x5581
#define PCI_DEVICE_ID_SI_5582 0x5582
#define PCI_DEVICE_ID_SI_5591 0x5591
#define PCI_DEVICE_ID_SI_5596 0x5596
#define PCI_DEVICE_ID_SI_5597 0x5597
#define PCI_DEVICE_ID_SI_5598 0x5598
#define PCI_DEVICE_ID_SI_5600 0x5600
#define PCI_DEVICE_ID_SI_7012 0x7012
#define PCI_DEVICE_ID_SI_7013 0x7013
#define PCI_DEVICE_ID_SI_7016 0x7016
#define PCI_DEVICE_ID_SI_7018 0x7018
#define PCI_VENDOR_ID_HP 0x103c
#define PCI_DEVICE_ID_HP_VISUALIZE_EG 0x1005
#define PCI_DEVICE_ID_HP_VISUALIZE_FX6 0x1006
#define PCI_DEVICE_ID_HP_VISUALIZE_FX4 0x1008
#define PCI_DEVICE_ID_HP_VISUALIZE_FX2 0x100a
#define PCI_DEVICE_ID_HP_TACHYON 0x1028
#define PCI_DEVICE_ID_HP_TACHLITE 0x1029
#define PCI_DEVICE_ID_HP_J2585A 0x1030
#define PCI_DEVICE_ID_HP_J2585B 0x1031
#define PCI_DEVICE_ID_HP_J2973A 0x1040
#define PCI_DEVICE_ID_HP_J2970A 0x1042
#define PCI_DEVICE_ID_HP_DIVA 0x1048
#define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049
#define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A
#define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B
#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1
#define PCI_DEVICE_ID_HP_VISUALIZE_FXE 0x108b
#define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223
#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226
#define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227
#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a
#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e
#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c
#define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282
#define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290
#define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301
#define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a
#define PCI_DEVICE_ID_HP_CISSA 0x3220
#define PCI_DEVICE_ID_HP_CISSC 0x3230
#define PCI_DEVICE_ID_HP_CISSD 0x3238
#define PCI_DEVICE_ID_HP_CISSE 0x323a
#define PCI_DEVICE_ID_HP_CISSF 0x323b
#define PCI_DEVICE_ID_HP_ZX2_IOC 0x4031
#define PCI_VENDOR_ID_PCTECH 0x1042
#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000
#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001
#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
#define PCI_VENDOR_ID_ASUSTEK 0x1043
#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675
#define PCI_VENDOR_ID_DPT 0x1044
#define PCI_DEVICE_ID_DPT 0xa400
#define PCI_VENDOR_ID_OPTI 0x1045
#define PCI_DEVICE_ID_OPTI_82C558 0xc558
#define PCI_DEVICE_ID_OPTI_82C621 0xc621
#define PCI_DEVICE_ID_OPTI_82C700 0xc700
#define PCI_DEVICE_ID_OPTI_82C825 0xd568
#define PCI_VENDOR_ID_ELSA 0x1048
#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000
#define PCI_DEVICE_ID_ELSA_QS3000 0x3000
#define PCI_VENDOR_ID_STMICRO 0x104A
#define PCI_VENDOR_ID_BUSLOGIC 0x104B
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040
#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130
#define PCI_VENDOR_ID_TI 0x104c
#define PCI_DEVICE_ID_TI_TVP4020 0x3d07
#define PCI_DEVICE_ID_TI_4450 0x8011
#define PCI_DEVICE_ID_TI_XX21_XX11 0x8031
#define PCI_DEVICE_ID_TI_XX21_XX11_FM 0x8033
#define PCI_DEVICE_ID_TI_XX21_XX11_SD 0x8034
#define PCI_DEVICE_ID_TI_X515 0x8036
#define PCI_DEVICE_ID_TI_XX12 0x8039
#define PCI_DEVICE_ID_TI_XX12_FM 0x803b
#define PCI_DEVICE_ID_TI_XIO2000A 0x8231
#define PCI_DEVICE_ID_TI_1130 0xac12
#define PCI_DEVICE_ID_TI_1031 0xac13
#define PCI_DEVICE_ID_TI_1131 0xac15
#define PCI_DEVICE_ID_TI_1250 0xac16
#define PCI_DEVICE_ID_TI_1220 0xac17
#define PCI_DEVICE_ID_TI_1221 0xac19
#define PCI_DEVICE_ID_TI_1210 0xac1a
#define PCI_DEVICE_ID_TI_1450 0xac1b
#define PCI_DEVICE_ID_TI_1225 0xac1c
#define PCI_DEVICE_ID_TI_1251A 0xac1d
#define PCI_DEVICE_ID_TI_1211 0xac1e
#define PCI_DEVICE_ID_TI_1251B 0xac1f
#define PCI_DEVICE_ID_TI_4410 0xac41
#define PCI_DEVICE_ID_TI_4451 0xac42
#define PCI_DEVICE_ID_TI_4510 0xac44
#define PCI_DEVICE_ID_TI_4520 0xac46
#define PCI_DEVICE_ID_TI_7510 0xac47
#define PCI_DEVICE_ID_TI_7610 0xac48
#define PCI_DEVICE_ID_TI_7410 0xac49
#define PCI_DEVICE_ID_TI_1410 0xac50
#define PCI_DEVICE_ID_TI_1420 0xac51
#define PCI_DEVICE_ID_TI_1451A 0xac52
#define PCI_DEVICE_ID_TI_1620 0xac54
#define PCI_DEVICE_ID_TI_1520 0xac55
#define PCI_DEVICE_ID_TI_1510 0xac56
#define PCI_DEVICE_ID_TI_X620 0xac8d
#define PCI_DEVICE_ID_TI_X420 0xac8e
#define PCI_DEVICE_ID_TI_XX20_FM 0xac8f
#define PCI_VENDOR_ID_SONY 0x104d
/* Winbond have two vendor IDs! See 0x10ad as well */
#define PCI_VENDOR_ID_WINBOND2 0x1050
#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a
#define PCI_DEVICE_ID_WINBOND2_6692 0x6692
#define PCI_VENDOR_ID_ANIGMA 0x1051
#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100
#define PCI_VENDOR_ID_EFAR 0x1055
#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130
#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463
#define PCI_VENDOR_ID_MOTOROLA 0x1057
#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004
#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
#define PCI_DEVICE_ID_MOTOROLA_HARRIER 0x480b
#define PCI_DEVICE_ID_MOTOROLA_MPC5200 0x5803
#define PCI_DEVICE_ID_MOTOROLA_MPC5200B 0x5809
#define PCI_VENDOR_ID_PROMISE 0x105a
#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
#define PCI_DEVICE_ID_PROMISE_20267 0x4d30
#define PCI_DEVICE_ID_PROMISE_20246 0x4d33
#define PCI_DEVICE_ID_PROMISE_20262 0x4d38
#define PCI_DEVICE_ID_PROMISE_20263 0x0D38
#define PCI_DEVICE_ID_PROMISE_20268 0x4d68
#define PCI_DEVICE_ID_PROMISE_20269 0x4d69
#define PCI_DEVICE_ID_PROMISE_20270 0x6268
#define PCI_DEVICE_ID_PROMISE_20271 0x6269
#define PCI_DEVICE_ID_PROMISE_20275 0x1275
#define PCI_DEVICE_ID_PROMISE_20276 0x5275
#define PCI_DEVICE_ID_PROMISE_20277 0x7275
#define PCI_VENDOR_ID_FOXCONN 0x105b
#define PCI_VENDOR_ID_UMC 0x1060
#define PCI_DEVICE_ID_UMC_UM8673F 0x0101
#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a
#define PCI_DEVICE_ID_UMC_UM8886A 0x886a
#define PCI_VENDOR_ID_PICOPOWER 0x1066
#define PCI_DEVICE_ID_PICOPOWER_PT86C523 0x0002
#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP 0x8002
#define PCI_VENDOR_ID_MYLEX 0x1069
#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001
#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002
#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010
#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020
#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050
#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56
#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166
#define PCI_VENDOR_ID_APPLE 0x106b
#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001
#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e
#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021
#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15 0x002e
#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2 0x0032
#define PCI_DEVICE_ID_APPLE_UNI_N_ATA 0x0033
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2 0x0034
#define PCI_DEVICE_ID_APPLE_IPID_ATA100 0x003b
#define PCI_DEVICE_ID_APPLE_K2_ATA100 0x0043
#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b
#define PCI_DEVICE_ID_APPLE_K2_GMAC 0x004c
#define PCI_DEVICE_ID_APPLE_SH_ATA 0x0050
#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051
#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058
#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059
#define PCI_DEVICE_ID_APPLE_U4_PCIE 0x005b
#define PCI_DEVICE_ID_APPLE_IPID2_AGP 0x0066
#define PCI_DEVICE_ID_APPLE_IPID2_ATA 0x0069
#define PCI_DEVICE_ID_APPLE_IPID2_FW 0x006a
#define PCI_DEVICE_ID_APPLE_IPID2_GMAC 0x006b
#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645
#define PCI_VENDOR_ID_YAMAHA 0x1073
#define PCI_DEVICE_ID_YAMAHA_724 0x0004
#define PCI_DEVICE_ID_YAMAHA_724F 0x000d
#define PCI_DEVICE_ID_YAMAHA_740 0x000a
#define PCI_DEVICE_ID_YAMAHA_740C 0x000c
#define PCI_DEVICE_ID_YAMAHA_744 0x0010
#define PCI_DEVICE_ID_YAMAHA_754 0x0012
#define PCI_VENDOR_ID_QLOGIC 0x1077
#define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016
#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020
#define PCI_DEVICE_ID_QLOGIC_ISP1080 0x1080
#define PCI_DEVICE_ID_QLOGIC_ISP12160 0x1216
#define PCI_DEVICE_ID_QLOGIC_ISP1240 0x1240
#define PCI_DEVICE_ID_QLOGIC_ISP1280 0x1280
#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100
#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200
#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300
#define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312
#define PCI_DEVICE_ID_QLOGIC_ISP2322 0x2322
#define PCI_DEVICE_ID_QLOGIC_ISP6312 0x6312
#define PCI_DEVICE_ID_QLOGIC_ISP6322 0x6322
#define PCI_DEVICE_ID_QLOGIC_ISP2422 0x2422
#define PCI_DEVICE_ID_QLOGIC_ISP2432 0x2432
#define PCI_DEVICE_ID_QLOGIC_ISP2512 0x2512
#define PCI_DEVICE_ID_QLOGIC_ISP2522 0x2522
#define PCI_DEVICE_ID_QLOGIC_ISP5422 0x5422
#define PCI_DEVICE_ID_QLOGIC_ISP5432 0x5432
#define PCI_VENDOR_ID_CYRIX 0x1078
#define PCI_DEVICE_ID_CYRIX_5510 0x0000
#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001
#define PCI_DEVICE_ID_CYRIX_5520 0x0002
#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102
#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103
#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104
#define PCI_VENDOR_ID_CONTAQ 0x1080
#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693
#define PCI_VENDOR_ID_OLICOM 0x108d
#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
#define PCI_VENDOR_ID_SUN 0x108e
#define PCI_DEVICE_ID_SUN_EBUS 0x1000
#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001
#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100
#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101
#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102
#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103
#define PCI_DEVICE_ID_SUN_GEM 0x2bad
#define PCI_DEVICE_ID_SUN_SIMBA 0x5000
#define PCI_DEVICE_ID_SUN_PBM 0x8000
#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001
#define PCI_DEVICE_ID_SUN_SABRE 0xa000
#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001
#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801
#define PCI_DEVICE_ID_SUN_CASSINI 0xabba
#define PCI_VENDOR_ID_NI 0x1093
#define PCI_DEVICE_ID_NI_PCI2322 0xd130
#define PCI_DEVICE_ID_NI_PCI2324 0xd140
#define PCI_DEVICE_ID_NI_PCI2328 0xd150
#define PCI_DEVICE_ID_NI_PXI8422_2322 0xd190
#define PCI_DEVICE_ID_NI_PXI8422_2324 0xd1a0
#define PCI_DEVICE_ID_NI_PXI8420_2322 0xd1d0
#define PCI_DEVICE_ID_NI_PXI8420_2324 0xd1e0
#define PCI_DEVICE_ID_NI_PXI8420_2328 0xd1f0
#define PCI_DEVICE_ID_NI_PXI8420_23216 0xd1f1
#define PCI_DEVICE_ID_NI_PCI2322I 0xd250
#define PCI_DEVICE_ID_NI_PCI2324I 0xd270
#define PCI_DEVICE_ID_NI_PCI23216 0xd2b0
#define PCI_DEVICE_ID_NI_PXI8430_2322 0x7080
#define PCI_DEVICE_ID_NI_PCI8430_2322 0x70db
#define PCI_DEVICE_ID_NI_PXI8430_2324 0x70dd
#define PCI_DEVICE_ID_NI_PCI8430_2324 0x70df
#define PCI_DEVICE_ID_NI_PXI8430_2328 0x70e2
#define PCI_DEVICE_ID_NI_PCI8430_2328 0x70e4
#define PCI_DEVICE_ID_NI_PXI8430_23216 0x70e6
#define PCI_DEVICE_ID_NI_PCI8430_23216 0x70e7
#define PCI_DEVICE_ID_NI_PXI8432_2322 0x70e8
#define PCI_DEVICE_ID_NI_PCI8432_2322 0x70ea
#define PCI_DEVICE_ID_NI_PXI8432_2324 0x70ec
#define PCI_DEVICE_ID_NI_PCI8432_2324 0x70ee
#define PCI_VENDOR_ID_CMD 0x1095
#define PCI_DEVICE_ID_CMD_643 0x0643
#define PCI_DEVICE_ID_CMD_646 0x0646
#define PCI_DEVICE_ID_CMD_648 0x0648
#define PCI_DEVICE_ID_CMD_649 0x0649
#define PCI_VENDOR_ID_SILICONIMAGE 0x1095
#define PCI_DEVICE_ID_SII_1210SA 0x0240
#define PCI_DEVICE_ID_SII_680 0x0680
#define PCI_DEVICE_ID_SII_3112 0x3112
#define PCI_DEVICE_ID_SIL3124 0x3124
#define PCI_DEVICE_ID_SIL3131 0x3131
#define PCI_DEVICE_ID_SIL3132 0x3132
#define PCI_VENDOR_ID_BROOKTREE 0x109e
#define PCI_DEVICE_ID_BROOKTREE_878 0x0878
#define PCI_DEVICE_ID_BROOKTREE_879 0x0879
#define PCI_VENDOR_ID_SGI 0x10a9
#define PCI_DEVICE_ID_SGI_IOC3 0x0003
#define PCI_DEVICE_ID_SGI_LITHIUM 0x1002
#define PCI_DEVICE_ID_SGI_IOC4 0x100a
#define PCI_VENDOR_ID_WINBOND 0x10ad
#define PCI_DEVICE_ID_WINBOND_82C105 0x0105
#define PCI_DEVICE_ID_WINBOND_83C553 0x0565
#define PCI_VENDOR_ID_PLX 0x10b5
#define PCI_DEVICE_ID_PLX_R685 0x1030
#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a
#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076
#define PCI_DEVICE_ID_PLX_1077 0x1077
#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103
#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
#define PCI_DEVICE_ID_PLX_R753 0x1152
#define PCI_DEVICE_ID_PLX_OLITEC 0x1187
#define PCI_DEVICE_ID_PLX_PCI200SYN 0x3196
#define PCI_DEVICE_ID_PLX_9030 0x9030
#define PCI_DEVICE_ID_PLX_9050 0x9050
#define PCI_DEVICE_ID_PLX_9056 0x9056
#define PCI_DEVICE_ID_PLX_9080 0x9080
#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001
#define PCI_VENDOR_ID_MADGE 0x10b6
#define PCI_DEVICE_ID_MADGE_MK2 0x0002
#define PCI_VENDOR_ID_3COM 0x10b7
#define PCI_DEVICE_ID_3COM_3C985 0x0001
#define PCI_DEVICE_ID_3COM_3C940 0x1700
#define PCI_DEVICE_ID_3COM_3C339 0x3390
#define PCI_DEVICE_ID_3COM_3C359 0x3590
#define PCI_DEVICE_ID_3COM_3C940B 0x80eb
#define PCI_DEVICE_ID_3COM_3CR990 0x9900
#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902
#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903
#define PCI_DEVICE_ID_3COM_3CR990B 0x9904
#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905
#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908
#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909
#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a
#define PCI_VENDOR_ID_AL 0x10b9
#define PCI_DEVICE_ID_AL_M1533 0x1533
#define PCI_DEVICE_ID_AL_M1535 0x1535
#define PCI_DEVICE_ID_AL_M1541 0x1541
#define PCI_DEVICE_ID_AL_M1563 0x1563
#define PCI_DEVICE_ID_AL_M1621 0x1621
#define PCI_DEVICE_ID_AL_M1631 0x1631
#define PCI_DEVICE_ID_AL_M1632 0x1632
#define PCI_DEVICE_ID_AL_M1641 0x1641
#define PCI_DEVICE_ID_AL_M1644 0x1644
#define PCI_DEVICE_ID_AL_M1647 0x1647
#define PCI_DEVICE_ID_AL_M1651 0x1651
#define PCI_DEVICE_ID_AL_M1671 0x1671
#define PCI_DEVICE_ID_AL_M1681 0x1681
#define PCI_DEVICE_ID_AL_M1683 0x1683
#define PCI_DEVICE_ID_AL_M1689 0x1689
#define PCI_DEVICE_ID_AL_M5219 0x5219
#define PCI_DEVICE_ID_AL_M5228 0x5228
#define PCI_DEVICE_ID_AL_M5229 0x5229
#define PCI_DEVICE_ID_AL_M5451 0x5451
#define PCI_DEVICE_ID_AL_M7101 0x7101
#define PCI_VENDOR_ID_NEOMAGIC 0x10c8
#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
#define PCI_VENDOR_ID_TCONRAD 0x10da
#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
#define PCI_VENDOR_ID_NVIDIA 0x10de
#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029
#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN 0x002a
#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C
#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS 0x0034
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE 0x0035
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA 0x0036
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2 0x003e
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800 0x0041
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE 0x0042
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x0045
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000 0x004E
#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS 0x0052
#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE 0x0053
#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA 0x0054
#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2 0x0055
#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005d
#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS 0x0064
#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065
#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069
#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS 0x0084
#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085
#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089
#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT 0x0090
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX 0x0091
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800 0x0098
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099
#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0
#define PCI_DEVICE_ID_GEFORCE_6800A 0x00c1
#define PCI_DEVICE_ID_GEFORCE_6800A_LE 0x00c2
#define PCI_DEVICE_ID_GEFORCE_GO_6800 0x00c8
#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA 0x00c9
#define PCI_DEVICE_ID_QUADRO_FX_GO1400 0x00cc
#define PCI_DEVICE_ID_QUADRO_FX_1400 0x00ce
#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1
#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS 0x00d4
#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5
#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9
#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1
#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3
#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS 0x00e4
#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5
#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee
#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0
#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1
#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2
#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3
#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT 0x00f9
#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280 0x00fd
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101
#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112
#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT 0x0140
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600 0x0141
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL 0x0145
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540 0x014E
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200 0x014F
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151
#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152
#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200 0x0164
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250 0x0166
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1 0x0167
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1 0x0168
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE 0x0173
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO 0x0177
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000 0x0185
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC 0x0189
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B
#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0
#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4
#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO 0x01b1
#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS 0x01b4
#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc
#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM 0x01c1
#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202
#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B 0x0211
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE 0x0212
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT 0x0215
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600 0x0250
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400 0x0251
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200 0x0253
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS 0x0264
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE 0x0265
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS 0x0368
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE 0x036E
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA 0x037E
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2 0x037F
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282
#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO 0x0286
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL 0x0288
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL 0x0289
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL 0x028C
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA 0x0301
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA 0x0311
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA 0x0321
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1 0x0322
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500 0x0326
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100 0x0327
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32 0x0328
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200 0x0329
#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA 0x0330
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA 0x0333
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT 0x0334
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700 0x033F
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA 0x0341
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1 0x0347
#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2 0x0348
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E
#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0 0x0360
#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4 0x0364
#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA 0x03E7
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS 0x03EB
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE 0x03EC
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2 0x03F6
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3 0x03F7
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS 0x0446
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE 0x0448
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS 0x0542
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE 0x0560
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE 0x056C
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS 0x0752
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE 0x0759
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS 0x07D8
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS 0x0AA2
#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA 0x0D85
#define PCI_VENDOR_ID_IMS 0x10e0
#define PCI_DEVICE_ID_IMS_TT128 0x9128
#define PCI_DEVICE_ID_IMS_TT3D 0x9135
#define PCI_VENDOR_ID_TUNDRA 0x10e3
#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000
#define PCI_VENDOR_ID_INTERG 0x10ea
#define PCI_DEVICE_ID_INTERG_1682 0x1682
#define PCI_DEVICE_ID_INTERG_2000 0x2000
#define PCI_DEVICE_ID_INTERG_2010 0x2010
#define PCI_DEVICE_ID_INTERG_5000 0x5000
#define PCI_DEVICE_ID_INTERG_5050 0x5050
#define PCI_VENDOR_ID_REALTEK 0x10ec
#define PCI_DEVICE_ID_REALTEK_8139 0x8139
#define PCI_VENDOR_ID_XILINX 0x10ee
#define PCI_DEVICE_ID_RME_DIGI96 0x3fc0
#define PCI_DEVICE_ID_RME_DIGI96_8 0x3fc1
#define PCI_DEVICE_ID_RME_DIGI96_8_PRO 0x3fc2
#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
#define PCI_VENDOR_ID_INIT 0x1101
#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */
#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
#define PCI_DEVICE_ID_CREATIVE_20K1 0x0005
#define PCI_DEVICE_ID_CREATIVE_20K2 0x000b
#define PCI_SUBDEVICE_ID_CREATIVE_SB0760 0x0024
#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041
#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042
#define PCI_SUBDEVICE_ID_CREATIVE_SB08803 0x0043
#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX 0x6000
#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */
#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
#define PCI_VENDOR_ID_TTI 0x1103
#define PCI_DEVICE_ID_TTI_HPT343 0x0003
#define PCI_DEVICE_ID_TTI_HPT366 0x0004
#define PCI_DEVICE_ID_TTI_HPT372 0x0005
#define PCI_DEVICE_ID_TTI_HPT302 0x0006
#define PCI_DEVICE_ID_TTI_HPT371 0x0007
#define PCI_DEVICE_ID_TTI_HPT374 0x0008
#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* apparently a 372N variant? */
#define PCI_VENDOR_ID_VIA 0x1106
#define PCI_DEVICE_ID_VIA_8763_0 0x0198
#define PCI_DEVICE_ID_VIA_8380_0 0x0204
#define PCI_DEVICE_ID_VIA_3238_0 0x0238
#define PCI_DEVICE_ID_VIA_PT880 0x0258
#define PCI_DEVICE_ID_VIA_PT880ULTRA 0x0308
#define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259
#define PCI_DEVICE_ID_VIA_3269_0 0x0269
#define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282
#define PCI_DEVICE_ID_VIA_3296_0 0x0296
#define PCI_DEVICE_ID_VIA_8363_0 0x0305
#define PCI_DEVICE_ID_VIA_P4M800CE 0x0314
#define PCI_DEVICE_ID_VIA_P4M890 0x0327
#define PCI_DEVICE_ID_VIA_VT3324 0x0324
#define PCI_DEVICE_ID_VIA_VT3336 0x0336
#define PCI_DEVICE_ID_VIA_VT3351 0x0351
#define PCI_DEVICE_ID_VIA_VT3364 0x0364
#define PCI_DEVICE_ID_VIA_8371_0 0x0391
#define PCI_DEVICE_ID_VIA_6415 0x0415
#define PCI_DEVICE_ID_VIA_8501_0 0x0501
#define PCI_DEVICE_ID_VIA_82C561 0x0561
#define PCI_DEVICE_ID_VIA_82C586_1 0x0571
#define PCI_DEVICE_ID_VIA_82C576 0x0576
#define PCI_DEVICE_ID_VIA_82C586_0 0x0586
#define PCI_DEVICE_ID_VIA_82C596 0x0596
#define PCI_DEVICE_ID_VIA_82C597_0 0x0597
#define PCI_DEVICE_ID_VIA_82C598_0 0x0598
#define PCI_DEVICE_ID_VIA_8601_0 0x0601
#define PCI_DEVICE_ID_VIA_8605_0 0x0605
#define PCI_DEVICE_ID_VIA_82C686 0x0686
#define PCI_DEVICE_ID_VIA_82C691_0 0x0691
#define PCI_DEVICE_ID_VIA_82C576_1 0x1571
#define PCI_DEVICE_ID_VIA_82C586_2 0x3038
#define PCI_DEVICE_ID_VIA_82C586_3 0x3040
#define PCI_DEVICE_ID_VIA_82C596_3 0x3050
#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051
#define PCI_DEVICE_ID_VIA_82C686_4 0x3057
#define PCI_DEVICE_ID_VIA_82C686_5 0x3058
#define PCI_DEVICE_ID_VIA_8233_5 0x3059
#define PCI_DEVICE_ID_VIA_8233_0 0x3074
#define PCI_DEVICE_ID_VIA_8633_0 0x3091
#define PCI_DEVICE_ID_VIA_8367_0 0x3099
#define PCI_DEVICE_ID_VIA_8653_0 0x3101
#define PCI_DEVICE_ID_VIA_8622 0x3102
#define PCI_DEVICE_ID_VIA_8235_USB_2 0x3104
#define PCI_DEVICE_ID_VIA_8233C_0 0x3109
#define PCI_DEVICE_ID_VIA_8361 0x3112
#define PCI_DEVICE_ID_VIA_XM266 0x3116
#define PCI_DEVICE_ID_VIA_612X 0x3119
#define PCI_DEVICE_ID_VIA_862X_0 0x3123
#define PCI_DEVICE_ID_VIA_8753_0 0x3128
#define PCI_DEVICE_ID_VIA_8233A 0x3147
#define PCI_DEVICE_ID_VIA_8703_51_0 0x3148
#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149
#define PCI_DEVICE_ID_VIA_XN266 0x3156
#define PCI_DEVICE_ID_VIA_6410 0x3164
#define PCI_DEVICE_ID_VIA_8754C_0 0x3168
#define PCI_DEVICE_ID_VIA_8235 0x3177
#define PCI_DEVICE_ID_VIA_8385_0 0x3188
#define PCI_DEVICE_ID_VIA_8377_0 0x3189
#define PCI_DEVICE_ID_VIA_8378_0 0x3205
#define PCI_DEVICE_ID_VIA_8783_0 0x3208
#define PCI_DEVICE_ID_VIA_8237 0x3227
#define PCI_DEVICE_ID_VIA_8251 0x3287
#define PCI_DEVICE_ID_VIA_8261 0x3402
#define PCI_DEVICE_ID_VIA_8237A 0x3337
#define PCI_DEVICE_ID_VIA_8237S 0x3372
#define PCI_DEVICE_ID_VIA_SATA_EIDE 0x5324
#define PCI_DEVICE_ID_VIA_8231 0x8231
#define PCI_DEVICE_ID_VIA_8231_4 0x8235
#define PCI_DEVICE_ID_VIA_8365_1 0x8305
#define PCI_DEVICE_ID_VIA_CX700 0x8324
#define PCI_DEVICE_ID_VIA_CX700_IDE 0x0581
#define PCI_DEVICE_ID_VIA_VX800 0x8353
#define PCI_DEVICE_ID_VIA_VX855 0x8409
#define PCI_DEVICE_ID_VIA_8371_1 0x8391
#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
#define PCI_DEVICE_ID_VIA_838X_1 0xB188
#define PCI_DEVICE_ID_VIA_83_87XX_1 0xB198
#define PCI_DEVICE_ID_VIA_VX855_IDE 0xC409
#define PCI_DEVICE_ID_VIA_ANON 0xFFFF
#define PCI_VENDOR_ID_SIEMENS 0x110A
#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102
#define PCI_VENDOR_ID_VORTEX 0x1119
#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000
#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001
#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002
#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003
#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004
#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005
#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006
#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007
#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008
#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009
#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a
#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b
#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c
#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d
#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100
#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101
#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102
#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103
#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104
#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105
#define PCI_VENDOR_ID_EF 0x111a
#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000
#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002
#define PCI_DEVICE_ID_EF_ATM_LANAI2 0x0003
#define PCI_DEVICE_ID_EF_ATM_LANAIHB 0x0005
#define PCI_VENDOR_ID_IDT 0x111d
#define PCI_DEVICE_ID_IDT_IDT77201 0x0001
#define PCI_VENDOR_ID_FORE 0x1127
#define PCI_DEVICE_ID_FORE_PCA200E 0x0300
#define PCI_VENDOR_ID_PHILIPS 0x1131
#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146
#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730
#define PCI_VENDOR_ID_EICON 0x1133
#define PCI_DEVICE_ID_EICON_DIVA20 0xe002
#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004
#define PCI_DEVICE_ID_EICON_DIVA201 0xe005
#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b
#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010
#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012
#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013
#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014
#define PCI_VENDOR_ID_CISCO 0x1137
#define PCI_VENDOR_ID_ZIATECH 0x1138
#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550
#define PCI_VENDOR_ID_SYSKONNECT 0x1148
#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200
#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300
#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320
#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400
#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500
#define PCI_VENDOR_ID_DIGI 0x114f
#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070
#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071
#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072
#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073
#define PCI_DEVICE_ID_DIGI_NEO_8 0x00B1
#define PCI_DEVICE_ID_NEO_2DB9 0x00C8
#define PCI_DEVICE_ID_NEO_2DB9PRI 0x00C9
#define PCI_DEVICE_ID_NEO_2RJ45 0x00CA
#define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB
#define PCIE_DEVICE_ID_NEO_4_IBM 0x00F4
#define PCI_VENDOR_ID_XIRCOM 0x115d
#define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101
#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103
#define PCI_VENDOR_ID_SERVERWORKS 0x1166
#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008
#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009
#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
#define PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB 0x0036
#define PCI_DEVICE_ID_SERVERWORKS_EPB 0x0103
#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200
#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201
#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203
#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205
#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
#define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
#define PCI_VENDOR_ID_SBE 0x1176
#define PCI_DEVICE_ID_SBE_WANXL100 0x0301
#define PCI_DEVICE_ID_SBE_WANXL200 0x0302
#define PCI_DEVICE_ID_SBE_WANXL400 0x0104
#define PCI_SUBDEVICE_ID_SBE_T3E3 0x0009
#define PCI_SUBDEVICE_ID_SBE_2T3E3_P0 0x0901
#define PCI_SUBDEVICE_ID_SBE_2T3E3_P1 0x0902
#define PCI_VENDOR_ID_TOSHIBA 0x1179
#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1 0x0101
#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2 0x0102
#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_3 0x0103
#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_5 0x0105
#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a
#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f
#define PCI_DEVICE_ID_TOSHIBA_TOPIC100 0x0617
#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
#define PCI_DEVICE_ID_TOSHIBA_TC35815_NWU 0x0031
#define PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939 0x0032
#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE 0x0105
#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC 0x0108
#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
#define PCI_VENDOR_ID_ATTO 0x117c
#define PCI_VENDOR_ID_RICOH 0x1180
#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465
#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466
#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475
#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476
#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478
#define PCI_DEVICE_ID_RICOH_R5C822 0x0822
#define PCI_DEVICE_ID_RICOH_R5C832 0x0832
#define PCI_DEVICE_ID_RICOH_R5C843 0x0843
#define PCI_VENDOR_ID_DLINK 0x1186
#define PCI_DEVICE_ID_DLINK_8139 0x1300
#define PCI_DEVICE_ID_DLINK_DGE510T 0x4c00
#define PCI_VENDOR_ID_ARTOP 0x1191
#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005
#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006
#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007
#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008
#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009
#define PCI_DEVICE_ID_ARTOP_ATP867A 0x000A
#define PCI_DEVICE_ID_ARTOP_ATP867B 0x000B
#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002
#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010
#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020
#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030
#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040
#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050
#define PCI_DEVICE_ID_ARTOP_8060 0x8060
#define PCI_VENDOR_ID_ZEITNET 0x1193
#define PCI_DEVICE_ID_ZEITNET_1221 0x0001
#define PCI_DEVICE_ID_ZEITNET_1225 0x0002
#define PCI_VENDOR_ID_FUJITSU_ME 0x119e
#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001
#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003
#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9
#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
#define PCI_VENDOR_ID_MARVELL 0x11ab
#define PCI_DEVICE_ID_MARVELL_GT64111 0x4146
#define PCI_DEVICE_ID_MARVELL_GT64260 0x6430
#define PCI_DEVICE_ID_MARVELL_MV64360 0x6460
#define PCI_DEVICE_ID_MARVELL_MV64460 0x6480
#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND 0x4100
#define PCI_DEVICE_ID_MARVELL_88ALP01_SD 0x4101
#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC 0x4102
#define PCI_VENDOR_ID_V3 0x11b0
#define PCI_DEVICE_ID_V3_V960 0x0001
#define PCI_DEVICE_ID_V3_V351 0x0002
#define PCI_VENDOR_ID_ATT 0x11c1
#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480
#define PCI_VENDOR_ID_SPECIALIX 0x11cb
#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000
#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000
#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4
#define PCI_DEVICE_ID_AD1889JS 0x1889
#define PCI_DEVICE_ID_SEGA_BBA 0x1234
#define PCI_VENDOR_ID_ZORAN 0x11de
#define PCI_DEVICE_ID_ZORAN_36057 0x6057
#define PCI_DEVICE_ID_ZORAN_36120 0x6120
#define PCI_VENDOR_ID_COMPEX 0x11f6
#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
#define PCI_VENDOR_ID_PMC_Sierra 0x11f8
#define PCI_VENDOR_ID_RP 0x11fe
#define PCI_DEVICE_ID_RP32INTF 0x0001
#define PCI_DEVICE_ID_RP8INTF 0x0002
#define PCI_DEVICE_ID_RP16INTF 0x0003
#define PCI_DEVICE_ID_RP4QUAD 0x0004
#define PCI_DEVICE_ID_RP8OCTA 0x0005
#define PCI_DEVICE_ID_RP8J 0x0006
#define PCI_DEVICE_ID_RP4J 0x0007
#define PCI_DEVICE_ID_RP8SNI 0x0008
#define PCI_DEVICE_ID_RP16SNI 0x0009
#define PCI_DEVICE_ID_RPP4 0x000A
#define PCI_DEVICE_ID_RPP8 0x000B
#define PCI_DEVICE_ID_RP4M 0x000D
#define PCI_DEVICE_ID_RP2_232 0x000E
#define PCI_DEVICE_ID_RP2_422 0x000F
#define PCI_DEVICE_ID_URP32INTF 0x0801
#define PCI_DEVICE_ID_URP8INTF 0x0802
#define PCI_DEVICE_ID_URP16INTF 0x0803
#define PCI_DEVICE_ID_URP8OCTA 0x0805
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C
#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D
#define PCI_DEVICE_ID_CRP16INTF 0x0903
#define PCI_VENDOR_ID_CYCLADES 0x120e
#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100
#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101
#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102
#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103
#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104
#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105
#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200
#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201
#define PCI_DEVICE_ID_PC300_RX_2 0x0300
#define PCI_DEVICE_ID_PC300_RX_1 0x0301
#define PCI_DEVICE_ID_PC300_TE_2 0x0310
#define PCI_DEVICE_ID_PC300_TE_1 0x0311
#define PCI_DEVICE_ID_PC300_TE_M_2 0x0320
#define PCI_DEVICE_ID_PC300_TE_M_1 0x0321
#define PCI_VENDOR_ID_ESSENTIAL 0x120f
#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001
#define PCI_VENDOR_ID_O2 0x1217
#define PCI_DEVICE_ID_O2_6729 0x6729
#define PCI_DEVICE_ID_O2_6730 0x673a
#define PCI_DEVICE_ID_O2_6832 0x6832
#define PCI_DEVICE_ID_O2_6836 0x6836
#define PCI_DEVICE_ID_O2_6812 0x6872
#define PCI_DEVICE_ID_O2_6933 0x6933
#define PCI_DEVICE_ID_O2_8120 0x8120
#define PCI_DEVICE_ID_O2_8220 0x8220
#define PCI_DEVICE_ID_O2_8221 0x8221
#define PCI_DEVICE_ID_O2_8320 0x8320
#define PCI_DEVICE_ID_O2_8321 0x8321
#define PCI_VENDOR_ID_3DFX 0x121a
#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001
#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002
#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003
#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005
#define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009
#define PCI_VENDOR_ID_AVM 0x1244
#define PCI_DEVICE_ID_AVM_B1 0x0700
#define PCI_DEVICE_ID_AVM_C4 0x0800
#define PCI_DEVICE_ID_AVM_A1 0x0a00
#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00
#define PCI_DEVICE_ID_AVM_C2 0x1100
#define PCI_DEVICE_ID_AVM_T1 0x1200
#define PCI_VENDOR_ID_STALLION 0x124d
/* Allied Telesyn */
#define PCI_VENDOR_ID_AT 0x1259
#define PCI_SUBDEVICE_ID_AT_2700FX 0x2701
#define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
#define PCI_VENDOR_ID_ESS 0x125d
#define PCI_DEVICE_ID_ESS_ESS1968 0x1968
#define PCI_DEVICE_ID_ESS_ESS1978 0x1978
#define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988
#define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989
#define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990
#define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992
#define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998
#define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999
#define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a
#define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b
#define PCI_VENDOR_ID_SATSAGEM 0x1267
#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016
#define PCI_VENDOR_ID_SMI 0x126f
#define PCI_DEVICE_ID_SMI_710 0x0710
#define PCI_DEVICE_ID_SMI_712 0x0712
#define PCI_DEVICE_ID_SMI_810 0x0810
#define PCI_DEVICE_ID_SMI_501 0x0501
#define PCI_VENDOR_ID_ENSONIQ 0x1274
#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
#define PCI_VENDOR_ID_TRANSMETA 0x1279
#define PCI_DEVICE_ID_EFFICEON 0x0060
#define PCI_VENDOR_ID_ROCKWELL 0x127A
#define PCI_VENDOR_ID_DAVICOM 0x1282
#define PCI_DEVICE_ID_DAVICOM_DM9102A 0x9102
#define PCI_VENDOR_ID_ITE 0x1283
#define PCI_DEVICE_ID_ITE_8172 0x8172
#define PCI_DEVICE_ID_ITE_8211 0x8211
#define PCI_DEVICE_ID_ITE_8212 0x8212
#define PCI_DEVICE_ID_ITE_8213 0x8213
#define PCI_DEVICE_ID_ITE_8152 0x8152
#define PCI_DEVICE_ID_ITE_8872 0x8872
#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
/* formerly Platform Tech */
#define PCI_DEVICE_ID_ESS_ESS0100 0x0100
#define PCI_VENDOR_ID_ALTEON 0x12ae
#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ 0x000C
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM 0x000D
#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI 0x0100
#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2 0x0201
#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4 0x0202
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232 0x0300
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232 0x0301
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232 0x0302
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1 0x0310
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2 0x0311
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4 0x0312
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2 0x0320
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4 0x0321
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8 0x0322
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485 0x0330
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332
#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2
#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0
#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031
#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021
#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011
#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041
#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D
#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001
#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010
#define PCI_VENDOR_ID_AUREAL 0x12eb
#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001
#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002
#define PCI_DEVICE_ID_AUREAL_ADVANTAGE 0x0003
#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
#define PCI_DEVICE_ID_LML_33R10 0x8a02
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
#define PCI_VENDOR_ID_SIIG 0x131f
#define PCI_SUBVENDOR_ID_SIIG 0x131f
#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001
#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002
#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010
#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011
#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012
#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020
#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021
#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030
#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031
#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032
#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034
#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035
#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036
#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050
#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051
#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052
#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000
#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001
#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002
#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020
#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021
#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030
#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031
#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032
#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040
#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041
#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042
#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010
#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011
#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012
#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050
#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051
#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052
#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060
#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061
#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062
#define PCI_DEVICE_ID_SIIG_8S_20x_550 0x2080
#define PCI_DEVICE_ID_SIIG_8S_20x_650 0x2081
#define PCI_DEVICE_ID_SIIG_8S_20x_850 0x2082
#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL 0x2050
#define PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL 0x2530
#define PCI_VENDOR_ID_RADISYS 0x1331
#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332
#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415
#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425
#define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155
#define PCI_VENDOR_ID_DOMEX 0x134a
#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001
#define PCI_VENDOR_ID_INTASHIELD 0x135a
#define PCI_DEVICE_ID_INTASHIELD_IS200 0x0d80
#define PCI_DEVICE_ID_INTASHIELD_IS400 0x0dc0
#define PCI_VENDOR_ID_QUATECH 0x135C
#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
#define PCI_VENDOR_ID_SEALEVEL 0x135e
#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101
#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201
#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402
#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202
#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401
#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801
#define PCI_DEVICE_ID_SEALEVEL_7803 0x7803
#define PCI_DEVICE_ID_SEALEVEL_UCOMM8 0x7804
#define PCI_VENDOR_ID_HYPERCOPE 0x1365
#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050
#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104
#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106
#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107
#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108
#define PCI_VENDOR_ID_DIGIGRAM 0x1369
#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM 0xc001
#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM 0xc002
#define PCI_VENDOR_ID_KAWASAKI 0x136b
#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01
#define PCI_VENDOR_ID_CNET 0x1371
#define PCI_DEVICE_ID_CNET_GIGACARD 0x434e
#define PCI_VENDOR_ID_LMC 0x1376
#define PCI_DEVICE_ID_LMC_HSSI 0x0003
#define PCI_DEVICE_ID_LMC_DS3 0x0004
#define PCI_DEVICE_ID_LMC_SSI 0x0005
#define PCI_DEVICE_ID_LMC_T1 0x0006
#define PCI_VENDOR_ID_NETGEAR 0x1385
#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
#define PCI_VENDOR_ID_APPLICOM 0x1389
#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
#define PCI_VENDOR_ID_MOXA 0x1393
#define PCI_DEVICE_ID_MOXA_RC7000 0x0001
#define PCI_DEVICE_ID_MOXA_CP102 0x1020
#define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
#define PCI_DEVICE_ID_MOXA_CP102U 0x1022
#define PCI_DEVICE_ID_MOXA_C104 0x1040
#define PCI_DEVICE_ID_MOXA_CP104U 0x1041
#define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
#define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
#define PCI_DEVICE_ID_MOXA_CT114 0x1140
#define PCI_DEVICE_ID_MOXA_CP114 0x1141
#define PCI_DEVICE_ID_MOXA_CP118U 0x1180
#define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
#define PCI_DEVICE_ID_MOXA_CP132 0x1320
#define PCI_DEVICE_ID_MOXA_CP132U 0x1321
#define PCI_DEVICE_ID_MOXA_CP134U 0x1340
#define PCI_DEVICE_ID_MOXA_C168 0x1680
#define PCI_DEVICE_ID_MOXA_CP168U 0x1681
#define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
#define PCI_DEVICE_ID_MOXA_CP204J 0x2040
#define PCI_DEVICE_ID_MOXA_C218 0x2180
#define PCI_DEVICE_ID_MOXA_C320 0x3200
#define PCI_VENDOR_ID_CCD 0x1397
#define PCI_DEVICE_ID_CCD_HFC4S 0x08B4
#define PCI_SUBDEVICE_ID_CCD_PMX2S 0x1234
#define PCI_DEVICE_ID_CCD_HFC8S 0x16B8
#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0
#define PCI_DEVICE_ID_CCD_HFCE1 0x30B1
#define PCI_SUBDEVICE_ID_CCD_SPD4S 0x3136
#define PCI_SUBDEVICE_ID_CCD_SPDE1 0x3137
#define PCI_DEVICE_ID_CCD_B000 0xb000
#define PCI_DEVICE_ID_CCD_B006 0xb006
#define PCI_DEVICE_ID_CCD_B007 0xb007
#define PCI_DEVICE_ID_CCD_B008 0xb008
#define PCI_DEVICE_ID_CCD_B009 0xb009
#define PCI_DEVICE_ID_CCD_B00A 0xb00a
#define PCI_DEVICE_ID_CCD_B00B 0xb00b
#define PCI_DEVICE_ID_CCD_B00C 0xb00c
#define PCI_DEVICE_ID_CCD_B100 0xb100
#define PCI_SUBDEVICE_ID_CCD_IOB4ST 0xB520
#define PCI_SUBDEVICE_ID_CCD_IOB8STR 0xB521
#define PCI_SUBDEVICE_ID_CCD_IOB8ST 0xB522
#define PCI_SUBDEVICE_ID_CCD_IOB1E1 0xB523
#define PCI_SUBDEVICE_ID_CCD_SWYX4S 0xB540
#define PCI_SUBDEVICE_ID_CCD_JH4S20 0xB550
#define PCI_SUBDEVICE_ID_CCD_IOB8ST_1 0xB552
#define PCI_SUBDEVICE_ID_CCD_JHSE1 0xB553
#define PCI_SUBDEVICE_ID_CCD_JH8S 0xB55B
#define PCI_SUBDEVICE_ID_CCD_BN4S 0xB560
#define PCI_SUBDEVICE_ID_CCD_BN8S 0xB562
#define PCI_SUBDEVICE_ID_CCD_BNE1 0xB563
#define PCI_SUBDEVICE_ID_CCD_BNE1D 0xB564
#define PCI_SUBDEVICE_ID_CCD_BNE1DP 0xB565
#define PCI_SUBDEVICE_ID_CCD_BN2S 0xB566
#define PCI_SUBDEVICE_ID_CCD_BN1SM 0xB567
#define PCI_SUBDEVICE_ID_CCD_BN4SM 0xB568
#define PCI_SUBDEVICE_ID_CCD_BN2SM 0xB569
#define PCI_SUBDEVICE_ID_CCD_BNE1M 0xB56A
#define PCI_SUBDEVICE_ID_CCD_BN8SP 0xB56B
#define PCI_SUBDEVICE_ID_CCD_HFC4S 0xB620
#define PCI_SUBDEVICE_ID_CCD_HFC8S 0xB622
#define PCI_DEVICE_ID_CCD_B700 0xb700
#define PCI_DEVICE_ID_CCD_B701 0xb701
#define PCI_SUBDEVICE_ID_CCD_HFCE1 0xC523
#define PCI_SUBDEVICE_ID_CCD_OV2S 0xE884
#define PCI_SUBDEVICE_ID_CCD_OV4S 0xE888
#define PCI_SUBDEVICE_ID_CCD_OV8S 0xE998
#define PCI_VENDOR_ID_EXAR 0x13a8
#define PCI_DEVICE_ID_EXAR_XR17C152 0x0152
#define PCI_DEVICE_ID_EXAR_XR17C154 0x0154
#define PCI_DEVICE_ID_EXAR_XR17C158 0x0158
#define PCI_VENDOR_ID_MICROGATE 0x13c0
#define PCI_DEVICE_ID_MICROGATE_USC 0x0010
#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030
#define PCI_VENDOR_ID_3WARE 0x13C1
#define PCI_DEVICE_ID_3WARE_1000 0x1000
#define PCI_DEVICE_ID_3WARE_7000 0x1001
#define PCI_DEVICE_ID_3WARE_9000 0x1002
#define PCI_VENDOR_ID_IOMEGA 0x13ca
#define PCI_DEVICE_ID_IOMEGA_BUZ 0x4231
#define PCI_VENDOR_ID_ABOCOM 0x13D1
#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1
#define PCI_VENDOR_ID_SUNDANCE 0x13f0
#define PCI_VENDOR_ID_CMEDIA 0x13f6
#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
#define PCI_VENDOR_ID_LAVA 0x1407
#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */
#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */
#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */
#define PCI_DEVICE_ID_LAVA_QUATTRO_A 0x0120 /* 2x 16550A, half of 4 port */
#define PCI_DEVICE_ID_LAVA_QUATTRO_B 0x0121 /* 2x 16550A, half of 4 port */
#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */
#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */
#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */
#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */
#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */
#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */
#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */
#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000
#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */
#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */
#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800
#define PCI_VENDOR_ID_TIMEDIA 0x1409
#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168
#define PCI_VENDOR_ID_ICE 0x1412
#define PCI_DEVICE_ID_ICE_1712 0x1712
#define PCI_DEVICE_ID_VT1724 0x1724
#define PCI_VENDOR_ID_OXSEMI 0x1415
#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403
#define PCI_DEVICE_ID_OXSEMI_PCIe840 0xC000
#define PCI_DEVICE_ID_OXSEMI_PCIe840_G 0xC004
#define PCI_DEVICE_ID_OXSEMI_PCIe952_0 0xC100
#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G 0xC104
#define PCI_DEVICE_ID_OXSEMI_PCIe952_1 0xC110
#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G 0xC114
#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U 0xC118
#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU 0xC11C
#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501
#define PCI_DEVICE_ID_OXSEMI_C950 0x950B
#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511
#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521
#define PCI_DEVICE_ID_OXSEMI_16PCI952PP 0x9523
#define PCI_SUBDEVICE_ID_OXSEMI_C950 0x0001
#define PCI_VENDOR_ID_CHELSIO 0x1425
#define PCI_VENDOR_ID_SAMSUNG 0x144d
#define PCI_VENDOR_ID_GIGABYTE 0x1458
#define PCI_VENDOR_ID_AMBIT 0x1468
#define PCI_VENDOR_ID_MYRICOM 0x14c1
#define PCI_VENDOR_ID_TITAN 0x14D2
#define PCI_DEVICE_ID_TITAN_010L 0x8001
#define PCI_DEVICE_ID_TITAN_100L 0x8010
#define PCI_DEVICE_ID_TITAN_110L 0x8011
#define PCI_DEVICE_ID_TITAN_200L 0x8020
#define PCI_DEVICE_ID_TITAN_210L 0x8021
#define PCI_DEVICE_ID_TITAN_400L 0x8040
#define PCI_DEVICE_ID_TITAN_800L 0x8080
#define PCI_DEVICE_ID_TITAN_100 0xA001
#define PCI_DEVICE_ID_TITAN_200 0xA005
#define PCI_DEVICE_ID_TITAN_400 0xA003
#define PCI_DEVICE_ID_TITAN_800B 0xA004
#define PCI_VENDOR_ID_PANACOM 0x14d4
#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
#define PCI_VENDOR_ID_SIPACKETS 0x14d9
#define PCI_DEVICE_ID_SP1011 0x0010
#define PCI_VENDOR_ID_AFAVLAB 0x14db
#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180
#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
#define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
#define PCI_VENDOR_ID_BCM_GVC 0x14a4
#define PCI_VENDOR_ID_BROADCOM 0x14e4
#define PCI_DEVICE_ID_TIGON3_5752 0x1600
#define PCI_DEVICE_ID_TIGON3_5752M 0x1601
#define PCI_DEVICE_ID_NX2_5709 0x1639
#define PCI_DEVICE_ID_NX2_5709S 0x163a
#define PCI_DEVICE_ID_TIGON3_5700 0x1644
#define PCI_DEVICE_ID_TIGON3_5701 0x1645
#define PCI_DEVICE_ID_TIGON3_5702 0x1646
#define PCI_DEVICE_ID_TIGON3_5703 0x1647
#define PCI_DEVICE_ID_TIGON3_5704 0x1648
#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
#define PCI_DEVICE_ID_NX2_5706 0x164a
#define PCI_DEVICE_ID_NX2_5708 0x164c
#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
#define PCI_DEVICE_ID_NX2_57710 0x164e
#define PCI_DEVICE_ID_NX2_57711 0x164f
#define PCI_DEVICE_ID_NX2_57711E 0x1650
#define PCI_DEVICE_ID_TIGON3_5705 0x1653
#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
#define PCI_DEVICE_ID_TIGON3_5721 0x1659
#define PCI_DEVICE_ID_TIGON3_5722 0x165a
#define PCI_DEVICE_ID_TIGON3_5723 0x165b
#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
#define PCI_DEVICE_ID_TIGON3_5714 0x1668
#define PCI_DEVICE_ID_TIGON3_5714S 0x1669
#define PCI_DEVICE_ID_TIGON3_5780 0x166a
#define PCI_DEVICE_ID_TIGON3_5780S 0x166b
#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
#define PCI_DEVICE_ID_TIGON3_5754 0x167a
#define PCI_DEVICE_ID_TIGON3_5755 0x167b
#define PCI_DEVICE_ID_TIGON3_5751M 0x167d
#define PCI_DEVICE_ID_TIGON3_5751F 0x167e
#define PCI_DEVICE_ID_TIGON3_5787F 0x167f
#define PCI_DEVICE_ID_TIGON3_5761E 0x1680
#define PCI_DEVICE_ID_TIGON3_5761 0x1681
#define PCI_DEVICE_ID_TIGON3_5764 0x1684
#define PCI_DEVICE_ID_TIGON3_5787M 0x1693
#define PCI_DEVICE_ID_TIGON3_5782 0x1696
#define PCI_DEVICE_ID_TIGON3_5784 0x1698
#define PCI_DEVICE_ID_TIGON3_5786 0x169a
#define PCI_DEVICE_ID_TIGON3_5787 0x169b
#define PCI_DEVICE_ID_TIGON3_5788 0x169c
#define PCI_DEVICE_ID_TIGON3_5789 0x169d
#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
#define PCI_DEVICE_ID_NX2_5706S 0x16aa
#define PCI_DEVICE_ID_NX2_5708S 0x16ac
#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
#define PCI_DEVICE_ID_TIGON3_5781 0x16dd
#define PCI_DEVICE_ID_TIGON3_5753 0x16f7
#define PCI_DEVICE_ID_TIGON3_5753M 0x16fd
#define PCI_DEVICE_ID_TIGON3_5753F 0x16fe
#define PCI_DEVICE_ID_TIGON3_5901 0x170d
#define PCI_DEVICE_ID_BCM4401B1 0x170c
#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
#define PCI_DEVICE_ID_TIGON3_5906 0x1712
#define PCI_DEVICE_ID_TIGON3_5906M 0x1713
#define PCI_DEVICE_ID_BCM4401 0x4401
#define PCI_DEVICE_ID_BCM4401B0 0x4402
#define PCI_VENDOR_ID_TOPIC 0x151f
#define PCI_DEVICE_ID_TOPIC_TP560 0x0000
#define PCI_VENDOR_ID_MAINPINE 0x1522
#define PCI_DEVICE_ID_MAINPINE_PBRIDGE 0x0100
#define PCI_VENDOR_ID_ENE 0x1524
#define PCI_DEVICE_ID_ENE_CB710_FLASH 0x0510
#define PCI_DEVICE_ID_ENE_CB712_SD 0x0550
#define PCI_DEVICE_ID_ENE_CB712_SD_2 0x0551
#define PCI_DEVICE_ID_ENE_CB714_SD 0x0750
#define PCI_DEVICE_ID_ENE_CB714_SD_2 0x0751
#define PCI_DEVICE_ID_ENE_1211 0x1211
#define PCI_DEVICE_ID_ENE_1225 0x1225
#define PCI_DEVICE_ID_ENE_1410 0x1410
#define PCI_DEVICE_ID_ENE_710 0x1411
#define PCI_DEVICE_ID_ENE_712 0x1412
#define PCI_DEVICE_ID_ENE_1420 0x1420
#define PCI_DEVICE_ID_ENE_720 0x1421
#define PCI_DEVICE_ID_ENE_722 0x1422
#define PCI_SUBVENDOR_ID_PERLE 0x155f
#define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001
#define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010
#define PCI_VENDOR_ID_SYBA 0x1592
#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782
#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783
#define PCI_VENDOR_ID_MORETON 0x15aa
#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000
#define PCI_VENDOR_ID_ZOLTRIX 0x15b0
#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0
#define PCI_VENDOR_ID_MELLANOX 0x15b3
#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46
#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282
#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274
#define PCI_VENDOR_ID_DFI 0x15bd
#define PCI_VENDOR_ID_QUICKNET 0x15e2
#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500
/*
* ADDI-DATA GmbH communication cards <info@addi-data.com>
*/
#define PCI_VENDOR_ID_ADDIDATA_OLD 0x10E8
#define PCI_VENDOR_ID_ADDIDATA 0x15B8
#define PCI_DEVICE_ID_ADDIDATA_APCI7500 0x7000
#define PCI_DEVICE_ID_ADDIDATA_APCI7420 0x7001
#define PCI_DEVICE_ID_ADDIDATA_APCI7300 0x7002
#define PCI_DEVICE_ID_ADDIDATA_APCI7800 0x818E
#define PCI_DEVICE_ID_ADDIDATA_APCI7500_2 0x7009
#define PCI_DEVICE_ID_ADDIDATA_APCI7420_2 0x700A
#define PCI_DEVICE_ID_ADDIDATA_APCI7300_2 0x700B
#define PCI_DEVICE_ID_ADDIDATA_APCI7500_3 0x700C
#define PCI_DEVICE_ID_ADDIDATA_APCI7420_3 0x700D
#define PCI_DEVICE_ID_ADDIDATA_APCI7300_3 0x700E
#define PCI_DEVICE_ID_ADDIDATA_APCI7800_3 0x700F
#define PCI_DEVICE_ID_ADDIDATA_APCIe7300 0x7010
#define PCI_DEVICE_ID_ADDIDATA_APCIe7420 0x7011
#define PCI_DEVICE_ID_ADDIDATA_APCIe7500 0x7012
#define PCI_DEVICE_ID_ADDIDATA_APCIe7800 0x7013
#define PCI_VENDOR_ID_PDC 0x15e9
#define PCI_VENDOR_ID_FARSITE 0x1619
#define PCI_DEVICE_ID_FARSITE_T2P 0x0400
#define PCI_DEVICE_ID_FARSITE_T4P 0x0440
#define PCI_DEVICE_ID_FARSITE_T1U 0x0610
#define PCI_DEVICE_ID_FARSITE_T2U 0x0620
#define PCI_DEVICE_ID_FARSITE_T4U 0x0640
#define PCI_DEVICE_ID_FARSITE_TE1 0x1610
#define PCI_DEVICE_ID_FARSITE_TE1C 0x1612
#define PCI_VENDOR_ID_ARIMA 0x161f
#define PCI_VENDOR_ID_BROCADE 0x1657
#define PCI_DEVICE_ID_BROCADE_CT 0x0014
#define PCI_DEVICE_ID_BROCADE_FC_8G1P 0x0017
#define PCI_DEVICE_ID_BROCADE_CT_FC 0x0021
#define PCI_VENDOR_ID_SIBYTE 0x166d
#define PCI_DEVICE_ID_BCM1250_PCI 0x0001
#define PCI_DEVICE_ID_BCM1250_HT 0x0002
#define PCI_VENDOR_ID_ATHEROS 0x168c
#define PCI_VENDOR_ID_NETCELL 0x169c
#define PCI_DEVICE_ID_REVOLUTION 0x0044
#define PCI_VENDOR_ID_CENATEK 0x16CA
#define PCI_DEVICE_ID_CENATEK_IDE 0x0001
#define PCI_VENDOR_ID_VITESSE 0x1725
#define PCI_DEVICE_ID_VITESSE_VSC7174 0x7174
#define PCI_VENDOR_ID_LINKSYS 0x1737
#define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064
#define PCI_VENDOR_ID_ALTIMA 0x173b
#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8
#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9
#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea
#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb
#define PCI_VENDOR_ID_BELKIN 0x1799
#define PCI_DEVICE_ID_BELKIN_F5D7010V7 0x701f
#define PCI_VENDOR_ID_RDC 0x17f3
#define PCI_DEVICE_ID_RDC_R6020 0x6020
#define PCI_DEVICE_ID_RDC_R6030 0x6030
#define PCI_DEVICE_ID_RDC_R6040 0x6040
#define PCI_DEVICE_ID_RDC_R6060 0x6060
#define PCI_DEVICE_ID_RDC_R6061 0x6061
#define PCI_DEVICE_ID_RDC_D1010 0x1010
#define PCI_VENDOR_ID_LENOVO 0x17aa
#define PCI_VENDOR_ID_ARECA 0x17d3
#define PCI_DEVICE_ID_ARECA_1110 0x1110
#define PCI_DEVICE_ID_ARECA_1120 0x1120
#define PCI_DEVICE_ID_ARECA_1130 0x1130
#define PCI_DEVICE_ID_ARECA_1160 0x1160
#define PCI_DEVICE_ID_ARECA_1170 0x1170
#define PCI_DEVICE_ID_ARECA_1200 0x1200
#define PCI_DEVICE_ID_ARECA_1201 0x1201
#define PCI_DEVICE_ID_ARECA_1202 0x1202
#define PCI_DEVICE_ID_ARECA_1210 0x1210
#define PCI_DEVICE_ID_ARECA_1220 0x1220
#define PCI_DEVICE_ID_ARECA_1230 0x1230
#define PCI_DEVICE_ID_ARECA_1260 0x1260
#define PCI_DEVICE_ID_ARECA_1270 0x1270
#define PCI_DEVICE_ID_ARECA_1280 0x1280
#define PCI_DEVICE_ID_ARECA_1380 0x1380
#define PCI_DEVICE_ID_ARECA_1381 0x1381
#define PCI_DEVICE_ID_ARECA_1680 0x1680
#define PCI_DEVICE_ID_ARECA_1681 0x1681
#define PCI_VENDOR_ID_S2IO 0x17d5
#define PCI_DEVICE_ID_S2IO_WIN 0x5731
#define PCI_DEVICE_ID_S2IO_UNI 0x5831
#define PCI_DEVICE_ID_HERC_WIN 0x5732
#define PCI_DEVICE_ID_HERC_UNI 0x5832
#define PCI_VENDOR_ID_SITECOM 0x182d
#define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069
#define PCI_VENDOR_ID_TOPSPIN 0x1867
#define PCI_VENDOR_ID_SILAN 0x1904
#define PCI_VENDOR_ID_RENESAS 0x1912
#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001
#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002
#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004
#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007
#define PCI_DEVICE_ID_RENESAS_SH7786 0x0010
#define PCI_VENDOR_ID_TDI 0x192E
#define PCI_DEVICE_ID_TDI_EHCI 0x0101
#define PCI_VENDOR_ID_FREESCALE 0x1957
#define PCI_DEVICE_ID_MPC8308 0xc006
#define PCI_DEVICE_ID_MPC8315E 0x00b4
#define PCI_DEVICE_ID_MPC8315 0x00b5
#define PCI_DEVICE_ID_MPC8314E 0x00b6
#define PCI_DEVICE_ID_MPC8314 0x00b7
#define PCI_DEVICE_ID_MPC8378E 0x00c4
#define PCI_DEVICE_ID_MPC8378 0x00c5
#define PCI_DEVICE_ID_MPC8377E 0x00c6
#define PCI_DEVICE_ID_MPC8377 0x00c7
#define PCI_DEVICE_ID_MPC8548E 0x0012
#define PCI_DEVICE_ID_MPC8548 0x0013
#define PCI_DEVICE_ID_MPC8543E 0x0014
#define PCI_DEVICE_ID_MPC8543 0x0015
#define PCI_DEVICE_ID_MPC8547E 0x0018
#define PCI_DEVICE_ID_MPC8545E 0x0019
#define PCI_DEVICE_ID_MPC8545 0x001a
#define PCI_DEVICE_ID_MPC8569E 0x0061
#define PCI_DEVICE_ID_MPC8569 0x0060
#define PCI_DEVICE_ID_MPC8568E 0x0020
#define PCI_DEVICE_ID_MPC8568 0x0021
#define PCI_DEVICE_ID_MPC8567E 0x0022
#define PCI_DEVICE_ID_MPC8567 0x0023
#define PCI_DEVICE_ID_MPC8533E 0x0030
#define PCI_DEVICE_ID_MPC8533 0x0031
#define PCI_DEVICE_ID_MPC8544E 0x0032
#define PCI_DEVICE_ID_MPC8544 0x0033
#define PCI_DEVICE_ID_MPC8572E 0x0040
#define PCI_DEVICE_ID_MPC8572 0x0041
#define PCI_DEVICE_ID_MPC8536E 0x0050
#define PCI_DEVICE_ID_MPC8536 0x0051
#define PCI_DEVICE_ID_P2020E 0x0070
#define PCI_DEVICE_ID_P2020 0x0071
#define PCI_DEVICE_ID_P2010E 0x0078
#define PCI_DEVICE_ID_P2010 0x0079
#define PCI_DEVICE_ID_P1020E 0x0100
#define PCI_DEVICE_ID_P1020 0x0101
#define PCI_DEVICE_ID_P1021E 0x0102
#define PCI_DEVICE_ID_P1021 0x0103
#define PCI_DEVICE_ID_P1011E 0x0108
#define PCI_DEVICE_ID_P1011 0x0109
#define PCI_DEVICE_ID_P1022E 0x0110
#define PCI_DEVICE_ID_P1022 0x0111
#define PCI_DEVICE_ID_P1013E 0x0118
#define PCI_DEVICE_ID_P1013 0x0119
#define PCI_DEVICE_ID_P4080E 0x0400
#define PCI_DEVICE_ID_P4080 0x0401
#define PCI_DEVICE_ID_P4040E 0x0408
#define PCI_DEVICE_ID_P4040 0x0409
#define PCI_DEVICE_ID_P2040E 0x0410
#define PCI_DEVICE_ID_P2040 0x0411
#define PCI_DEVICE_ID_P3041E 0x041E
#define PCI_DEVICE_ID_P3041 0x041F
#define PCI_DEVICE_ID_P5020E 0x0420
#define PCI_DEVICE_ID_P5020 0x0421
#define PCI_DEVICE_ID_P5010E 0x0428
#define PCI_DEVICE_ID_P5010 0x0429
#define PCI_DEVICE_ID_MPC8641 0x7010
#define PCI_DEVICE_ID_MPC8641D 0x7011
#define PCI_DEVICE_ID_MPC8610 0x7018
#define PCI_VENDOR_ID_PASEMI 0x1959
#define PCI_VENDOR_ID_ATTANSIC 0x1969
#define PCI_DEVICE_ID_ATTANSIC_L1 0x1048
#define PCI_DEVICE_ID_ATTANSIC_L2 0x2048
#define PCI_VENDOR_ID_JMICRON 0x197B
#define PCI_DEVICE_ID_JMICRON_JMB360 0x2360
#define PCI_DEVICE_ID_JMICRON_JMB361 0x2361
#define PCI_DEVICE_ID_JMICRON_JMB362 0x2362
#define PCI_DEVICE_ID_JMICRON_JMB363 0x2363
#define PCI_DEVICE_ID_JMICRON_JMB364 0x2364
#define PCI_DEVICE_ID_JMICRON_JMB365 0x2365
#define PCI_DEVICE_ID_JMICRON_JMB366 0x2366
#define PCI_DEVICE_ID_JMICRON_JMB368 0x2368
#define PCI_DEVICE_ID_JMICRON_JMB369 0x2369
#define PCI_DEVICE_ID_JMICRON_JMB38X_SD 0x2381
#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
#define PCI_DEVICE_ID_JMICRON_JMB38X_MS 0x2383
#define PCI_DEVICE_ID_JMICRON_JMB385_MS 0x2388
#define PCI_DEVICE_ID_JMICRON_JMB388_SD 0x2391
#define PCI_DEVICE_ID_JMICRON_JMB388_ESD 0x2392
#define PCI_DEVICE_ID_JMICRON_JMB390_MS 0x2393
#define PCI_VENDOR_ID_KORENIX 0x1982
#define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600
#define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff
#define PCI_DEVICE_ID_KORENIX_JETCARDF2 0x1700
#define PCI_DEVICE_ID_KORENIX_JETCARDF3 0x17ff
#define PCI_VENDOR_ID_QMI 0x1a32
#define PCI_VENDOR_ID_AZWAVE 0x1a3b
#define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
#define PCI_VENDOR_ID_TEHUTI 0x1fc9
#define PCI_DEVICE_ID_TEHUTI_3009 0x3009
#define PCI_DEVICE_ID_TEHUTI_3010 0x3010
#define PCI_DEVICE_ID_TEHUTI_3014 0x3014
#define PCI_VENDOR_ID_HINT 0x3388
#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
#define PCI_VENDOR_ID_3DLABS 0x3d3d
#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007
#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
#define PCI_VENDOR_ID_NETXEN 0x4040
#define PCI_DEVICE_ID_NX2031_10GXSR 0x0001
#define PCI_DEVICE_ID_NX2031_10GCX4 0x0002
#define PCI_DEVICE_ID_NX2031_4GCU 0x0003
#define PCI_DEVICE_ID_NX2031_IMEZ 0x0004
#define PCI_DEVICE_ID_NX2031_HMEZ 0x0005
#define PCI_DEVICE_ID_NX2031_XG_MGMT 0x0024
#define PCI_DEVICE_ID_NX2031_XG_MGMT2 0x0025
#define PCI_DEVICE_ID_NX3031 0x0100
#define PCI_VENDOR_ID_AKS 0x416c
#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100
#define PCI_VENDOR_ID_ACCESSIO 0x494f
#define PCI_DEVICE_ID_ACCESSIO_WDG_CSM 0x22c0
#define PCI_VENDOR_ID_S3 0x5333
#define PCI_DEVICE_ID_S3_TRIO 0x8811
#define PCI_DEVICE_ID_S3_868 0x8880
#define PCI_DEVICE_ID_S3_968 0x88f0
#define PCI_DEVICE_ID_S3_SAVAGE4 0x8a25
#define PCI_DEVICE_ID_S3_PROSAVAGE8 0x8d04
#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
#define PCI_VENDOR_ID_DUNORD 0x5544
#define PCI_DEVICE_ID_DUNORD_I3000 0x0001
#define PCI_VENDOR_ID_DCI 0x6666
#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001
#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002
#define PCI_DEVICE_ID_DCI_PCCOM2 0x0004
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
#define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320
#define PCI_DEVICE_ID_INTEL_PXHD_1 0x0321
#define PCI_DEVICE_ID_INTEL_PXH_0 0x0329
#define PCI_DEVICE_ID_INTEL_PXH_1 0x032A
#define PCI_DEVICE_ID_INTEL_PXHV 0x032C
#define PCI_DEVICE_ID_INTEL_80332_0 0x0330
#define PCI_DEVICE_ID_INTEL_80332_1 0x0332
#define PCI_DEVICE_ID_INTEL_80333_0 0x0370
#define PCI_DEVICE_ID_INTEL_80333_1 0x0372
#define PCI_DEVICE_ID_INTEL_82375 0x0482
#define PCI_DEVICE_ID_INTEL_82424 0x0483
#define PCI_DEVICE_ID_INTEL_82378 0x0484
#define PCI_DEVICE_ID_INTEL_MRST_SD0 0x0807
#define PCI_DEVICE_ID_INTEL_MRST_SD1 0x0808
#define PCI_DEVICE_ID_INTEL_MFD_SD 0x0820
#define PCI_DEVICE_ID_INTEL_MFD_SDIO1 0x0821
#define PCI_DEVICE_ID_INTEL_MFD_SDIO2 0x0822
#define PCI_DEVICE_ID_INTEL_MFD_EMMC0 0x0823
#define PCI_DEVICE_ID_INTEL_MFD_EMMC1 0x0824
#define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000
#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
#define PCI_DEVICE_ID_INTEL_82544EI_COPPER 0x1008
#define PCI_DEVICE_ID_INTEL_82544EI_FIBER 0x1009
#define PCI_DEVICE_ID_INTEL_82544GC_COPPER 0x100C
#define PCI_DEVICE_ID_INTEL_82544GC_LOM 0x100D
#define PCI_DEVICE_ID_INTEL_82540EM 0x100E
#define PCI_DEVICE_ID_INTEL_82545EM_COPPER 0x100F
#define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010
#define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011
#define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012
#define PCI_DEVICE_ID_INTEL_82546GB_COPPER 0x1079
#define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015
#define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026
#define PCI_DEVICE_ID_INTEL_82559 0x1030
#define PCI_DEVICE_ID_INTEL_82559ER 0x1209
#define PCI_DEVICE_ID_INTEL_82557 0x1229
#define PCI_DEVICE_ID_INTEL_82562ET 0x1031
#define PCI_DEVICE_ID_INTEL_82571EB_COPPER 0x105E
#define PCI_DEVICE_ID_INTEL_82571EB_FIBER 0x105F
#define PCI_DEVICE_ID_INTEL_82571EB_SERDES 0x1060
#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER 0x10A4
#define PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER 0x10D5
#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER 0x10A5
#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL 0x10D9
#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD 0x10DA
#define PCI_DEVICE_ID_INTEL_82572EI_COPPER 0x107D
#define PCI_DEVICE_ID_INTEL_82572EI_FIBER 0x107E
#define PCI_DEVICE_ID_INTEL_82572EI_SERDES 0x107F
#define PCI_DEVICE_ID_INTEL_82572EI 0x10B9
#define PCI_DEVICE_ID_INTEL_82573E 0x108B
#define PCI_DEVICE_ID_INTEL_82573E_IAMT 0x108C
#define PCI_DEVICE_ID_INTEL_82573L 0x109A
#define PCI_DEVICE_ID_INTEL_82574L 0x10D3
#define PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3 0x10B5
#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT 0x1096
#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT 0x1098
#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT 0x10BA
#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT 0x10BB
#define PCI_DEVICE_ID_INTEL_8257X_SOL 0x1062
#define PCI_DEVICE_ID_INTEL_82573E_SOL 0x1085
#define PCI_DEVICE_ID_INTEL_82573L_SOL 0x108F
#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130
#define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
#define PCI_DEVICE_ID_INTEL_82437 0x122d
#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e
#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230
#define PCI_DEVICE_ID_INTEL_82371MX 0x1234
#define PCI_DEVICE_ID_INTEL_82441 0x1237
#define PCI_DEVICE_ID_INTEL_82380FB 0x124b
#define PCI_DEVICE_ID_INTEL_82439 0x1250
#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416
#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418
#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420
#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421
#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423
#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425
#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426
#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428
#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440
#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443
#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445
#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448
#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a
#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b
#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c
#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450
#define PCI_DEVICE_ID_INTEL_82801E_11 0x245b
#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480
#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485
#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486
#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a
#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b
#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c
#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0
#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1
#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2
#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5
#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6
#define PCI_DEVICE_ID_INTEL_82801DB_9 0x24c9
#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca
#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb
#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc
#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0
#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1
#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5
#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6
#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
#define PCI_DEVICE_ID_INTEL_82801EB_12 0x24dc
#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
#define PCI_DEVICE_ID_INTEL_ESB_10 0x25ac
#define PCI_DEVICE_ID_INTEL_82820_HB 0x2500
#define PCI_DEVICE_ID_INTEL_82820_UP_HB 0x2501
#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530
#define PCI_DEVICE_ID_INTEL_82860_HB 0x2531
#define PCI_DEVICE_ID_INTEL_E7501_MCH 0x254c
#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560
#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562
#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570
#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572
#define PCI_DEVICE_ID_INTEL_82875_HB 0x2578
#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580
#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582
#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590
#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592
#define PCI_DEVICE_ID_INTEL_5000_ERR 0x25F0
#define PCI_DEVICE_ID_INTEL_5000_FBD0 0x25F5
#define PCI_DEVICE_ID_INTEL_5000_FBD1 0x25F6
#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770
#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772
#define PCI_DEVICE_ID_INTEL_3000_HB 0x2778
#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0
#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2
#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640
#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641
#define PCI_DEVICE_ID_INTEL_ICH6_2 0x2642
#define PCI_DEVICE_ID_INTEL_ICH6_16 0x266a
#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d
#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f
#define PCI_DEVICE_ID_INTEL_ESB2_0 0x2670
#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
#define PCI_DEVICE_ID_INTEL_ESB2_17 0x269b
#define PCI_DEVICE_ID_INTEL_ESB2_18 0x269e
#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8
#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9
#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd
#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df
#define PCI_DEVICE_ID_INTEL_ICH8_0 0x2810
#define PCI_DEVICE_ID_INTEL_ICH8_1 0x2811
#define PCI_DEVICE_ID_INTEL_ICH8_2 0x2812
#define PCI_DEVICE_ID_INTEL_ICH8_3 0x2814
#define PCI_DEVICE_ID_INTEL_ICH8_4 0x2815
#define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e
#define PCI_DEVICE_ID_INTEL_ICH8_6 0x2850
#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910
#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917
#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912
#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913
#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914
#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919
#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
#define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18
#define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19
#define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a
#define PCI_DEVICE_ID_INTEL_I7_MC_TEST 0x2c1c
#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL 0x2c20
#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR 0x2c21
#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK 0x2c22
#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC 0x2c23
#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL 0x2c28
#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR 0x2c29
#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK 0x2c2a
#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC 0x2c2b
#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL 0x2c30
#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR 0x2c31
#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK 0x2c32
#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC 0x2c33
#define PCI_DEVICE_ID_INTEL_I7_NONCORE 0x2c41
#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE 0x2c50
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2 0x2c70
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_SAD 0x2c81
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0 0x2c90
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_PHY0 0x2c91
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR 0x2c98
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD 0x2c99
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST 0x2c9C
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL 0x2ca0
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR 0x2ca1
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK 0x2ca2
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC 0x2ca3
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL 0x2ca8
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR 0x2ca9
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK 0x2caa
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC 0x2cab
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2 0x2d98
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2 0x2d99
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2 0x2d9a
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2 0x2d9c
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2 0x2da0
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2 0x2da1
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2 0x2da2
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2 0x2da3
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2 0x2da8
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2 0x2da9
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2 0x2daa
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2 0x2dab
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2 0x2db0
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2 0x2db1
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2 0x2db2
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2 0x2db3
#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
#define PCI_DEVICE_ID_INTEL_IOAT_TBG4 0x3429
#define PCI_DEVICE_ID_INTEL_IOAT_TBG5 0x342a
#define PCI_DEVICE_ID_INTEL_IOAT_TBG6 0x342b
#define PCI_DEVICE_ID_INTEL_IOAT_TBG7 0x342c
#define PCI_DEVICE_ID_INTEL_X58_HUB_MGMT 0x342e
#define PCI_DEVICE_ID_INTEL_IOAT_TBG0 0x3430
#define PCI_DEVICE_ID_INTEL_IOAT_TBG1 0x3431
#define PCI_DEVICE_ID_INTEL_IOAT_TBG2 0x3432
#define PCI_DEVICE_ID_INTEL_IOAT_TBG3 0x3433
#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575
#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577
#define PCI_DEVICE_ID_INTEL_82854_HB 0x358c
#define PCI_DEVICE_ID_INTEL_82854_IG 0x358e
#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580
#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582
#define PCI_DEVICE_ID_INTEL_E7520_MCH 0x3590
#define PCI_DEVICE_ID_INTEL_E7320_MCH 0x3592
#define PCI_DEVICE_ID_INTEL_MCH_PA 0x3595
#define PCI_DEVICE_ID_INTEL_MCH_PA1 0x3596
#define PCI_DEVICE_ID_INTEL_MCH_PB 0x3597
#define PCI_DEVICE_ID_INTEL_MCH_PB1 0x3598
#define PCI_DEVICE_ID_INTEL_MCH_PC 0x3599
#define PCI_DEVICE_ID_INTEL_MCH_PC1 0x359a
#define PCI_DEVICE_ID_INTEL_E7525_MCH 0x359e
#define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c
#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f
#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610
#define PCI_DEVICE_ID_INTEL_IOAT_CNB 0x360b
#define PCI_DEVICE_ID_INTEL_FBD_CNB 0x360c
#define PCI_DEVICE_ID_INTEL_IOAT_JSF0 0x3710
#define PCI_DEVICE_ID_INTEL_IOAT_JSF1 0x3711
#define PCI_DEVICE_ID_INTEL_IOAT_JSF2 0x3712
#define PCI_DEVICE_ID_INTEL_IOAT_JSF3 0x3713
#define PCI_DEVICE_ID_INTEL_IOAT_JSF4 0x3714
#define PCI_DEVICE_ID_INTEL_IOAT_JSF5 0x3715
#define PCI_DEVICE_ID_INTEL_IOAT_JSF6 0x3716
#define PCI_DEVICE_ID_INTEL_IOAT_JSF7 0x3717
#define PCI_DEVICE_ID_INTEL_IOAT_JSF8 0x3718
#define PCI_DEVICE_ID_INTEL_IOAT_JSF9 0x3719
#define PCI_DEVICE_ID_INTEL_ICH10_0 0x3a14
#define PCI_DEVICE_ID_INTEL_ICH10_1 0x3a16
#define PCI_DEVICE_ID_INTEL_ICH10_2 0x3a18
#define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a
#define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30
#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
#define PCI_DEVICE_ID_INTEL_5100_22 0x65f6
#define PCI_DEVICE_ID_INTEL_5400_ERR 0x4030
#define PCI_DEVICE_ID_INTEL_5400_FBD0 0x4035
#define PCI_DEVICE_ID_INTEL_5400_FBD1 0x4036
#define PCI_DEVICE_ID_INTEL_IOAT_SCNB 0x65ff
#define PCI_DEVICE_ID_INTEL_EP80579_0 0x5031
#define PCI_DEVICE_ID_INTEL_EP80579_1 0x5032
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
#define PCI_DEVICE_ID_INTEL_82437VX 0x7030
#define PCI_DEVICE_ID_INTEL_82439TX 0x7100
#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120
#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121
#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122
#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123
#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124
#define PCI_DEVICE_ID_INTEL_82810E_IG 0x7125
#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180
#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181
#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190
#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191
#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192
#define PCI_DEVICE_ID_INTEL_440MX 0x7195
#define PCI_DEVICE_ID_INTEL_440MX_6 0x7196
#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198
#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199
#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b
#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0
#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2
#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a
#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb
#define PCI_DEVICE_ID_INTEL_84460GX 0x84ea
#define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500
#define PCI_DEVICE_ID_INTEL_IXP2800 0x9004
#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
#define PCI_VENDOR_ID_SCALEMP 0x8686
#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL 0x1010
#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302
#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e
#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001
#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002
#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003
#define PCI_VENDOR_ID_KTI 0x8e2e
#define PCI_VENDOR_ID_ADAPTEC 0x9004
#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078
#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178
#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860
#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078
#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578
#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038
#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075
#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078
#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178
#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078
#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178
#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278
#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378
#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478
#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895
#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078
#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178
#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278
#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378
#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478
#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578
#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678
#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778
#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878
#define PCI_VENDOR_ID_ADAPTEC2 0x9005
#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010
#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011
#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013
#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f
#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050
#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051
#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f
#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080
#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081
#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083
#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f
#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0
#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1
#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3
#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf
#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN 0x0500
#define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503
#define PCI_VENDOR_ID_HOLTEK 0x9412
#define PCI_DEVICE_ID_HOLTEK_6565 0x6565
#define PCI_VENDOR_ID_NETMOS 0x9710
#define PCI_DEVICE_ID_NETMOS_9705 0x9705
#define PCI_DEVICE_ID_NETMOS_9715 0x9715
#define PCI_DEVICE_ID_NETMOS_9735 0x9735
#define PCI_DEVICE_ID_NETMOS_9745 0x9745
#define PCI_DEVICE_ID_NETMOS_9755 0x9755
#define PCI_DEVICE_ID_NETMOS_9805 0x9805
#define PCI_DEVICE_ID_NETMOS_9815 0x9815
#define PCI_DEVICE_ID_NETMOS_9835 0x9835
#define PCI_DEVICE_ID_NETMOS_9845 0x9845
#define PCI_DEVICE_ID_NETMOS_9855 0x9855
#define PCI_DEVICE_ID_NETMOS_9865 0x9865
#define PCI_DEVICE_ID_NETMOS_9901 0x9901
#define PCI_VENDOR_ID_3COM_2 0xa727
#define PCI_VENDOR_ID_DIGIUM 0xd161
#define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410
#define PCI_SUBVENDOR_ID_EXSYS 0xd84d
#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014
#define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055
#define PCI_VENDOR_ID_TIGERJET 0xe159
#define PCI_DEVICE_ID_TIGERJET_300 0x0001
#define PCI_DEVICE_ID_TIGERJET_100 0x0002
#define PCI_VENDOR_ID_XILINX_RME 0xea60
#define PCI_DEVICE_ID_RME_DIGI32 0x9896
#define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897
#define PCI_DEVICE_ID_RME_DIGI32_8 0x9898
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
|
1001-study-uboot
|
include/pci_ids.h
|
C
|
gpl3
| 115,059
|
/*
* (C) Copyright 2004
*
* Pantelis Antoniou <panto@intracom.gr>
* Intracom S.A.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Video support for Epson SED156x chipset(s) */
#ifndef SED156X_H
#define SED156X_H
void sed156x_init(void);
void sed156x_clear(void);
void sed156x_output_at(int x, int y, const char *str, int size);
void sed156x_reverse_at(int x, int y, int size);
void sed156x_sync(void);
void sed156x_scroll(int dx, int dy);
/* export display */
extern const int sed156x_text_width;
extern const int sed156x_text_height;
#endif /* SED156X_H */
|
1001-study-uboot
|
include/sed156x.h
|
C
|
gpl3
| 1,321
|
/*
* (C) Copyright 2007
* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
*/
#ifndef _MB862XX_H_
#define _MB862XX_H_
#define PCI_VENDOR_ID_FUJITSU 0x10CF
#define PCI_DEVICE_ID_CORAL_P 0x2019
#define PCI_DEVICE_ID_CORAL_PA 0x201E
#define MB862XX_TYPE_LIME 0x1
#define GC_HOST_BASE 0x01fc0000
#define GC_DISP_BASE 0x01fd0000
#define GC_DRAW_BASE 0x01ff0000
/* Host interface registers */
#define GC_SRST 0x0000002c
#define GC_CCF 0x00000038
#define GC_CID 0x000000f0
#define GC_MMR 0x0000fffc
/*
* Display Controller registers
* _A means the offset is aligned, we use these for boards
* with 8-/16-bit GDC access not working or buggy.
*/
#define GC_DCM0 0x00000000
#define GC_HTP_A 0x00000004
#define GC_HTP 0x00000006
#define GC_HDB_HDP_A 0x00000008
#define GC_HDP 0x00000008
#define GC_HDB 0x0000000a
#define GC_VSW_HSW_HSP_A 0x0000000c
#define GC_HSP 0x0000000c
#define GC_HSW 0x0000000e
#define GC_VSW 0x0000000f
#define GC_VTR_A 0x00000010
#define GC_VTR 0x00000012
#define GC_VDP_VSP_A 0x00000014
#define GC_VSP 0x00000014
#define GC_VDP 0x00000016
#define GC_WY_WX 0x00000018
#define GC_WH_WW 0x0000001c
#define GC_L0M 0x00000020
#define GC_L0OA0 0x00000024
#define GC_L0DA0 0x00000028
#define GC_L0DY_L0DX 0x0000002c
#define GC_L2M 0x00000040
#define GC_L2OA0 0x00000044
#define GC_L2DA0 0x00000048
#define GC_L2OA1 0x0000004c
#define GC_L2DA1 0x00000050
#define GC_L2DX 0x00000054
#define GC_L2DY 0x00000056
#define GC_DCM1 0x00000100
#define GC_DCM2 0x00000104
#define GC_DCM3 0x00000108
#define GC_L0EM 0x00000110
#define GC_L0WY_L0WX 0x00000114
#define GC_L0WH_L0WW 0x00000118
#define GC_L2EM 0x00000130
#define GC_L2WX 0x00000134
#define GC_L2WY 0x00000136
#define GC_L2WW 0x00000138
#define GC_L2WH 0x0000013a
#define GC_L0PAL0 0x00000400
/* Drawing registers */
#define GC_CTR 0x00000400
#define GC_IFCNT 0x00000408
#define GC_FBR 0x00000440
#define GC_XRES 0x00000444
#define GC_CXMIN 0x00000454
#define GC_CXMAX 0x00000458
#define GC_CYMIN 0x0000045c
#define GC_CYMAX 0x00000460
#define GC_FC 0x00000480
#define GC_BC 0x00000484
#define GC_FIFO 0x000004a0
#define GC_REV 0x00008084
#define GC_GEO_FIFO 0x00008400
typedef struct {
unsigned int index;
unsigned int value;
} gdc_regs;
int mb862xx_probe(unsigned int addr);
const gdc_regs *board_get_regs (void);
unsigned int board_video_init (void);
void board_backlight_switch(int);
#endif /* _MB862XX_H_ */
|
1001-study-uboot
|
include/mb862xx.h
|
C
|
gpl3
| 3,356
|
/*
* linux/include/asm-arm/hardware/clps7111.h
*
* This file contains the hardware definitions of the CLPS7111 internal
* registers.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_CLPS7111_H
#define __ASM_HARDWARE_CLPS7111_H
#define CLPS7111_PHYS_BASE (0x80000000)
#ifndef __ASSEMBLY__
#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
#endif
#define PADR (0x0000)
#define PBDR (0x0001)
#define PDDR (0x0003)
#define PADDR (0x0040)
#define PBDDR (0x0041)
#define PDDDR (0x0043)
#define PEDR (0x0080)
#define PEDDR (0x00c0)
#define SYSCON1 (0x0100)
#define SYSFLG1 (0x0140)
#define MEMCFG1 (0x0180)
#define MEMCFG2 (0x01c0)
#define DRFPR (0x0200)
#define INTSR1 (0x0240)
#define INTMR1 (0x0280)
#define LCDCON (0x02c0)
#define TC1D (0x0300)
#define TC2D (0x0340)
#define RTCDR (0x0380)
#define RTCMR (0x03c0)
#define PMPCON (0x0400)
#define CODR (0x0440)
#define UARTDR1 (0x0480)
#define UBRLCR1 (0x04c0)
#define SYNCIO (0x0500)
#define PALLSW (0x0540)
#define PALMSW (0x0580)
#define STFCLR (0x05c0)
#define BLEOI (0x0600)
#define MCEOI (0x0640)
#define TEOI (0x0680)
#define TC1EOI (0x06c0)
#define TC2EOI (0x0700)
#define RTCEOI (0x0740)
#define UMSEOI (0x0780)
#define COEOI (0x07c0)
#define HALT (0x0800)
#define STDBY (0x0840)
#define FBADDR (0x1000)
#define SYSCON2 (0x1100)
#define SYSFLG2 (0x1140)
#define INTSR2 (0x1240)
#define INTMR2 (0x1280)
#define UARTDR2 (0x1480)
#define UBRLCR2 (0x14c0)
#define SS2DR (0x1500)
#define SRXEOF (0x1600)
#define SS2POP (0x16c0)
#define KBDEOI (0x1700)
/* common bits: SYSCON1 / SYSCON2 */
#define SYSCON_UARTEN (1 << 8)
#define SYSCON1_KBDSCAN(x) ((x) & 15)
#define SYSCON1_KBDSCANMASK (15)
#define SYSCON1_TC1M (1 << 4)
#define SYSCON1_TC1S (1 << 5)
#define SYSCON1_TC2M (1 << 6)
#define SYSCON1_TC2S (1 << 7)
#define SYSCON1_UART1EN SYSCON_UARTEN
#define SYSCON1_BZTOG (1 << 9)
#define SYSCON1_BZMOD (1 << 10)
#define SYSCON1_DBGEN (1 << 11)
#define SYSCON1_LCDEN (1 << 12)
#define SYSCON1_CDENTX (1 << 13)
#define SYSCON1_CDENRX (1 << 14)
#define SYSCON1_SIREN (1 << 15)
#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
#define SYSCON1_ADCKSEL_MASK (3 << 16)
#define SYSCON1_EXCKEN (1 << 18)
#define SYSCON1_WAKEDIS (1 << 19)
#define SYSCON1_IRTXM (1 << 20)
/* common bits: SYSFLG1 / SYSFLG2 */
#define SYSFLG_UBUSY (1 << 11)
#define SYSFLG_URXFE (1 << 22)
#define SYSFLG_UTXFF (1 << 23)
#define SYSFLG1_MCDR (1 << 0)
#define SYSFLG1_DCDET (1 << 1)
#define SYSFLG1_WUDR (1 << 2)
#define SYSFLG1_WUON (1 << 3)
#define SYSFLG1_CTS (1 << 8)
#define SYSFLG1_DSR (1 << 9)
#define SYSFLG1_DCD (1 << 10)
#define SYSFLG1_UBUSY SYSFLG_UBUSY
#define SYSFLG1_NBFLG (1 << 12)
#define SYSFLG1_RSTFLG (1 << 13)
#define SYSFLG1_PFFLG (1 << 14)
#define SYSFLG1_CLDFLG (1 << 15)
#define SYSFLG1_URXFE SYSFLG_URXFE
#define SYSFLG1_UTXFF SYSFLG_UTXFF
#define SYSFLG1_CRXFE (1 << 24)
#define SYSFLG1_CTXFF (1 << 25)
#define SYSFLG1_SSIBUSY (1 << 26)
#define SYSFLG1_ID (1 << 29)
#define SYSFLG2_SSRXOF (1 << 0)
#define SYSFLG2_RESVAL (1 << 1)
#define SYSFLG2_RESFRM (1 << 2)
#define SYSFLG2_SS2RXFE (1 << 3)
#define SYSFLG2_SS2TXFF (1 << 4)
#define SYSFLG2_SS2TXUF (1 << 5)
#define SYSFLG2_CKMODE (1 << 6)
#define SYSFLG2_UBUSY SYSFLG_UBUSY
#define SYSFLG2_URXFE SYSFLG_URXFE
#define SYSFLG2_UTXFF SYSFLG_UTXFF
#define LCDCON_GSEN (1 << 30)
#define LCDCON_GSMD (1 << 31)
#define SYSCON2_SERSEL (1 << 0)
#define SYSCON2_KBD6 (1 << 1)
#define SYSCON2_DRAMZ (1 << 2)
#define SYSCON2_KBWEN (1 << 3)
#define SYSCON2_SS2TXEN (1 << 4)
#define SYSCON2_PCCARD1 (1 << 5)
#define SYSCON2_PCCARD2 (1 << 6)
#define SYSCON2_SS2RXEN (1 << 7)
#define SYSCON2_UART2EN SYSCON_UARTEN
#define SYSCON2_SS2MAEN (1 << 9)
#define SYSCON2_OSTB (1 << 12)
#define SYSCON2_CLKENSL (1 << 13)
#define SYSCON2_BUZFREQ (1 << 14)
/* common bits: UARTDR1 / UARTDR2 */
#define UARTDR_FRMERR (1 << 8)
#define UARTDR_PARERR (1 << 9)
#define UARTDR_OVERR (1 << 10)
/* common bits: UBRLCR1 / UBRLCR2 */
#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
#define UBRLCR_BREAK (1 << 12)
#define UBRLCR_PRTEN (1 << 13)
#define UBRLCR_EVENPRT (1 << 14)
#define UBRLCR_XSTOP (1 << 15)
#define UBRLCR_FIFOEN (1 << 16)
#define UBRLCR_WRDLEN5 (0 << 17)
#define UBRLCR_WRDLEN6 (1 << 17)
#define UBRLCR_WRDLEN7 (2 << 17)
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
#define SYNCIO_SMCKEN (1 << 13)
#define SYNCIO_TXFRMEN (1 << 14)
#define SYSCON3 0x2200 /* System Control register 3 ----------------------- */
#define ADCCON 0x00000001 /* ADC configuration */
#define CLKCTL 0x00000006 /* processor clock control */
#define CLKCTL_18 0x0 /* 18.432 MHz */
#define CLKCTL_36 0x2 /* 36.864 MHz */
#define CLKCTL_49 0x4 /* 49.152 MHz */
#define CLKCTL_73 0x6 /* 73.728 MHz */
#define MCPSEL 0x00000008 /* MCP select */
#define ADCCKNSEN 0x000010 /* ADC clock sense */
#define VERSN 0x000000e0 /* additional version bits */
#define VERSN_SHIFT 5
#define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */
#define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */
#define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */
#define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */
#define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */
#define LEDFLSH_RATE 0x03 /* flash rate */
#define LEDFLSH_RATE_SHIFT 0
#define LEDFLSH_DUTY 0x3c /* duty ratio */
#define LEDFLSH_DUTY_SHIFT 2
#define LEDFLSH_ENABLE 0x40 /* enable */
#define IO_START CLPS7111_PHYS_BASE
#define IO(offset) (IO_START + (offset))
#define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset)))
#define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset)))
#define IO_PADR IO_BYTE(PADR)
#define IO_PBDR IO_BYTE(PBDR)
#define IO_PDDR IO_BYTE(PDDR)
#define IO_PADDR IO_BYTE(PADDR)
#define IO_PBDDR IO_BYTE(PBDDR)
#define IO_PDDDR IO_BYTE(PDDDR)
#define IO_PEDR IO_BYTE(PEDR)
#define IO_PEDDR IO_BYTE(PEDDR)
#define IO_SYSCON IO_WORD(SYSCON)
#define IO_SYSFLG IO_WORD(SYSFLG)
#define IO_MEMCFG1 IO_WORD(MEMCFG1)
#define IO_MEMCFG2 IO_WORD(MEMCFG2)
#define IO_DRFPR IO_WORD(DRFPR)
#define IO_INTSR IO_WORD(INTSR)
#define IO_INTMR IO_WORD(INTMR)
#define IO_LCDCON IO_WORD(LCDCON)
#define IO_TC1D IO_WORD(TC1D)
#define IO_TC2D IO_WORD(TC2D)
#define IO_RTCDR IO_WORD(RTCDR)
#define IO_RTCMR IO_WORD(RTCMR)
#define IO_PMPCON IO_WORD(PMPCON)
#define IO_CODR IO_BYTE(CODR)
#define IO_UARTDR IO_WORD(UARTDR)
#define IO_UBRLCR IO_WORD(UBRLCR)
#define IO_SYNCIO IO_WORD(SYNCIO)
#define IO_PALLSW IO_WORD(PALLSW)
#define IO_PALMSW IO_WORD(PALMSW)
#define IO_STFCLR IO_WORD(STFCLR)
#define IO_BLEOI IO_WORD(BLEOI)
#define IO_MCEOI IO_WORD(MCEOI)
#define IO_TEOI IO_WORD(TEOI)
#define IO_TC1EOI IO_WORD(TC1EOI)
#define IO_TC2EOI IO_WORD(TC2EOI)
#define IO_RTCEOI IO_WORD(RTCEOI)
#define IO_UMSEOI IO_WORD(UMSEOI)
#define IO_COEOI IO_WORD(COEOI)
#define IO_HALT IO_WORD(HALT)
#define IO_STDBY IO_WORD(STDBY)
#define IO_SYSCON1 IO_WORD(SYSCON1)
#define IO_SYSFLG1 IO_WORD(SYSFLG1)
#define IO_INTSR1 IO_WORD(INTSR1)
#define IO_INTMR1 IO_WORD(INTMR1)
#define IO_UARTDR1 IO_WORD(UARTDR1)
#define IO_UBRLCR1 IO_WORD(UBRLCR1)
#define IO_FRBADDR IO_WORD(FRBADDR)
#define IO_SYSCON2 IO_WORD(SYSCON2)
#define IO_SYSFLG2 IO_WORD(SYSFLG2)
#define IO_INTSR2 IO_WORD(INTSR2)
#define IO_INTMR2 IO_WORD(INTMR2)
#define IO_UARTDR2 IO_WORD(UARTDR2)
#define IO_UBRLCR2 IO_WORD(UBRLCR2)
#define IO_KBDEOI IO_WORD(KBDEOI)
#define IO_MCCR IO_WORD(MCCR)
#define IO_MCDR0 IO_WORD(MCDR0)
#define IO_MCDR1 IO_WORD(MCDR1)
#define IO_MCDR2 IO_WORD(MCDR2)
#define IO_MCSR IO_WORD(MCSR)
#define IO_SYSCON3 IO_WORD(SYSCON3)
#define IO_INTSR3 IO_WORD(INTSR3)
#define IO_INTMR3 IO_WORD(INTMR3)
#define IO_LEDFLSH IO_WORD(LEDFLSH)
#endif /* __ASM_HARDWARE_CLPS7111_H */
|
1001-study-uboot
|
include/clps7111.h
|
C
|
gpl3
| 8,862
|
/* Rubin encoder/decoder header */
/* work started at : aug 3, 1994 */
/* last modification : aug 15, 1994 */
/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */
#define RUBIN_REG_SIZE 16
#define UPPER_BIT_RUBIN (((long) 1)<<(RUBIN_REG_SIZE-1))
#define LOWER_BITS_RUBIN ((((long) 1)<<(RUBIN_REG_SIZE-1))-1)
void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
unsigned long sourcelen, unsigned long dstlen);
|
1001-study-uboot
|
include/jffs2/compr_rubin.h
|
C
|
gpl3
| 467
|
u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
u32 jffs2_1pass_info(struct part_info *part);
|
1001-study-uboot
|
include/jffs2/jffs2_1pass.h
|
C
|
gpl3
| 184
|
/*-------------------------------------------------------------------------
* Filename: mini_inflate.h
* Version: $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
* Copyright: Copyright (C) 2001, Russ Dill
* Author: Russ Dill <Russ.Dill@asu.edu>
* Description: Mini deflate implementation
*-----------------------------------------------------------------------*/
/*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
typedef __SIZE_TYPE__ size;
#define NO_ERROR 0
#define COMP_UNKNOWN 1 /* The specififed bytype is invalid */
#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */
#define TOO_MANY_BITS 3 /* pull_bits was passed an argument that is too
* large */
/* This struct represents an entire huffman code set. It has various lookup
* tables to speed decoding */
struct huffman_set {
int bits; /* maximum bit length */
int num_symbols; /* Number of symbols this code can represent */
int *lengths; /* The bit length of symbols */
int *symbols; /* All of the symbols, sorted by the huffman code */
int *count; /* the number of codes of this bit length */
int *first; /* the first code of this bit length */
int *pos; /* the symbol that first represents (in the symbols
* array) */
};
struct bitstream {
unsigned char *data; /* increments as we move from byte to byte */
unsigned char bit; /* 0 to 7 */
void *(*memcpy)(void *, const void *, size);
unsigned long decoded; /* The number of bytes decoded */
int error;
int distance_count[16];
int distance_first[16];
int distance_pos[16];
int distance_lengths[32];
int distance_symbols[32];
int code_count[8];
int code_first[8];
int code_pos[8];
int code_lengths[19];
int code_symbols[19];
int length_count[16];
int length_first[16];
int length_pos[16];
int length_lengths[288];
int length_symbols[288];
struct huffman_set codes;
struct huffman_set lengths;
struct huffman_set distance;
};
#define NO_COMP 0
#define FIXED_COMP 1
#define DYNAMIC_COMP 2
long decompress_block(unsigned char *dest, unsigned char *source,
void *(*inflate_memcpy)(void *dest, const void *src, size n));
|
1001-study-uboot
|
include/jffs2/mini_inflate.h
|
C
|
gpl3
| 2,854
|
#ifndef load_kernel_h
#define load_kernel_h
/*-------------------------------------------------------------------------
* Filename: load_kernel.h
* Version: $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $
* Copyright: Copyright (C) 2001, Russ Dill
* Author: Russ Dill <Russ.Dill@asu.edu>
* Description: header for load kernel modules
*-----------------------------------------------------------------------*/
/*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/list.h>
/* mtd device types */
#define MTD_DEV_TYPE_NOR 0x0001
#define MTD_DEV_TYPE_NAND 0x0002
#define MTD_DEV_TYPE_ONENAND 0x0004
#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : \
(type == MTD_DEV_TYPE_ONENAND) ? "onenand" : "nor")
struct mtd_device {
struct list_head link;
struct mtdids *id; /* parent mtd id entry */
u16 num_parts; /* number of partitions on this device */
struct list_head parts; /* partitions */
};
struct part_info {
struct list_head link;
char *name; /* partition name */
u8 auto_name; /* set to 1 for generated name */
u32 size; /* total size of the partition */
u32 offset; /* offset within device */
void *jffs2_priv; /* used internaly by jffs2 */
u32 mask_flags; /* kernel MTD mask flags */
u32 sector_size; /* size of sector */
struct mtd_device *dev; /* parent device */
};
struct mtdids {
struct list_head link;
u8 type; /* device type */
u8 num; /* device number */
u32 size; /* device size */
char *mtd_id; /* linux kernel device id */
};
#define ldr_strlen strlen
#define ldr_strncmp strncmp
#define ldr_memcpy memcpy
#define putstr(x) printf("%s", x)
#define mmalloc malloc
#define UDEBUG printf
#define putnstr(str, size) printf("%*.*s", size, size, str)
#define ldr_output_string(x) puts(x)
#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y)
#define led_blink(x, y, z, a)
/* common/cmd_jffs2.c */
extern int mtdparts_init(void);
extern int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part);
extern struct mtd_device *device_find(u8 type, u8 num);
#endif /* load_kernel_h */
|
1001-study-uboot
|
include/jffs2/load_kernel.h
|
C
|
gpl3
| 2,850
|
/*
* JFFS2 -- Journalling Flash File System, Version 2.
*
* Copyright (C) 2001 Red Hat, Inc.
*
* Created by David Woodhouse <dwmw2@cambridge.redhat.com>
*
* The original JFFS, from which the design for JFFS2 was derived,
* was designed and implemented by Axis Communications AB.
*
* The contents of this file are subject to the Red Hat eCos Public
* License Version 1.1 (the "Licence"); you may not use this file
* except in compliance with the Licence. You may obtain a copy of
* the Licence at http://www.redhat.com/
*
* Software distributed under the Licence is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
* See the Licence for the specific language governing rights and
* limitations under the Licence.
*
* The Original Code is JFFS2 - Journalling Flash File System, version 2
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the RHEPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the RHEPL or the GPL.
*
* $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
*
*/
#ifndef __LINUX_JFFS2_H__
#define __LINUX_JFFS2_H__
#include <asm/types.h>
#include <jffs2/load_kernel.h>
#define JFFS2_SUPER_MAGIC 0x72b6
/* Values we may expect to find in the 'magic' field */
#define JFFS2_OLD_MAGIC_BITMASK 0x1984
#define JFFS2_MAGIC_BITMASK 0x1985
#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */
#define JFFS2_EMPTY_BITMASK 0xffff
#define JFFS2_DIRTY_BITMASK 0x0000
/* Summary node MAGIC marker */
#define JFFS2_SUM_MAGIC 0x02851885
/* We only allow a single char for length, and 0xFF is empty flash so
we don't want it confused with a real length. Hence max 254.
*/
#define JFFS2_MAX_NAME_LEN 254
/* How small can we sensibly write nodes? */
#define JFFS2_MIN_DATA_LEN 128
#define JFFS2_COMPR_NONE 0x00
#define JFFS2_COMPR_ZERO 0x01
#define JFFS2_COMPR_RTIME 0x02
#define JFFS2_COMPR_RUBINMIPS 0x03
#define JFFS2_COMPR_COPY 0x04
#define JFFS2_COMPR_DYNRUBIN 0x05
#define JFFS2_COMPR_ZLIB 0x06
#if defined(CONFIG_JFFS2_LZO)
#define JFFS2_COMPR_LZO 0x07
#define JFFS2_NUM_COMPR 8
#else
#define JFFS2_NUM_COMPR 7
#endif
/* Compatibility flags. */
#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */
#define JFFS2_NODE_ACCURATE 0x2000
/* INCOMPAT: Fail to mount the filesystem */
#define JFFS2_FEATURE_INCOMPAT 0xc000
/* ROCOMPAT: Mount read-only */
#define JFFS2_FEATURE_ROCOMPAT 0x8000
/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */
#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000
/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */
#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000
#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6)
/* Maybe later... */
/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */
/* Same as the non_ECC versions, but with extra space for real
* ECC instead of just the checksum. For use on NAND flash
*/
/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */
/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */
#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at
mount time, don't wait for it to
happen later */
#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific
compression type */
struct jffs2_unknown_node
{
/* All start like this */
__u16 magic;
__u16 nodetype;
__u32 totlen; /* So we can skip over nodes we don't grok */
__u32 hdr_crc;
} __attribute__((packed));
struct jffs2_raw_dirent
{
__u16 magic;
__u16 nodetype; /* == JFFS_NODETYPE_DIRENT */
__u32 totlen;
__u32 hdr_crc;
__u32 pino;
__u32 version;
__u32 ino; /* == zero for unlink */
__u32 mctime;
__u8 nsize;
__u8 type;
__u8 unused[2];
__u32 node_crc;
__u32 name_crc;
__u8 name[0];
} __attribute__((packed));
/* The JFFS2 raw inode structure: Used for storage on physical media. */
/* The uid, gid, atime, mtime and ctime members could be longer, but
are left like this for space efficiency. If and when people decide
they really need them extended, it's simple enough to add support for
a new type of raw node.
*/
struct jffs2_raw_inode
{
__u16 magic; /* A constant magic number. */
__u16 nodetype; /* == JFFS_NODETYPE_INODE */
__u32 totlen; /* Total length of this node (inc data, etc.) */
__u32 hdr_crc;
__u32 ino; /* Inode number. */
__u32 version; /* Version number. */
__u32 mode; /* The file's type or mode. */
__u16 uid; /* The file's owner. */
__u16 gid; /* The file's group. */
__u32 isize; /* Total resultant size of this inode (used for truncations) */
__u32 atime; /* Last access time. */
__u32 mtime; /* Last modification time. */
__u32 ctime; /* Change time. */
__u32 offset; /* Where to begin to write. */
__u32 csize; /* (Compressed) data size */
__u32 dsize; /* Size of the node's data. (after decompression) */
__u8 compr; /* Compression algorithm used */
__u8 usercompr; /* Compression algorithm requested by the user */
__u16 flags; /* See JFFS2_INO_FLAG_* */
__u32 data_crc; /* CRC for the (compressed) data. */
__u32 node_crc; /* CRC for the raw inode (excluding data) */
/* __u8 data[dsize]; */
} __attribute__((packed));
struct jffs2_raw_summary
{
__u16 magic;
__u16 nodetype; /* = JFFS2_NODETYPE_SUMMARY */
__u32 totlen;
__u32 hdr_crc;
__u32 sum_num; /* number of sum entries*/
__u32 cln_mkr; /* clean marker size, 0 = no cleanmarker */
__u32 padded; /* sum of the size of padding nodes */
__u32 sum_crc; /* summary information crc */
__u32 node_crc; /* node crc */
__u32 sum[0]; /* inode summary info */
};
union jffs2_node_union {
struct jffs2_raw_inode i;
struct jffs2_raw_dirent d;
struct jffs2_raw_summary s;
struct jffs2_unknown_node u;
} __attribute__((packed));
enum
{
DT_UNKNOWN = 0,
# define DT_UNKNOWN DT_UNKNOWN
DT_FIFO = 1,
# define DT_FIFO DT_FIFO
DT_CHR = 2,
# define DT_CHR DT_CHR
DT_DIR = 4,
# define DT_DIR DT_DIR
DT_BLK = 6,
# define DT_BLK DT_BLK
DT_REG = 8,
# define DT_REG DT_REG
DT_LNK = 10,
# define DT_LNK DT_LNK
DT_SOCK = 12,
# define DT_SOCK DT_SOCK
DT_WHT = 14
# define DT_WHT DT_WHT
};
u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
u32 jffs2_1pass_info(struct part_info *part);
void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
u32 srclen, u32 destlen);
void rubin_do_decompress(unsigned char *bits, unsigned char *in,
unsigned char *page_out, __u32 destlen);
void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
unsigned long sourcelen, unsigned long dstlen);
long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
__u32 srclen, __u32 destlen);
#if defined(CONFIG_JFFS2_LZO)
int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
u32 srclen, u32 destlen);
#endif
char *mkmodestr(unsigned long mode, char *str);
#endif /* __LINUX_JFFS2_H__ */
|
1001-study-uboot
|
include/jffs2/jffs2.h
|
C
|
gpl3
| 8,204
|
#ifndef __KEYBOARD_H
#define __KEYBOARD_H
#ifdef CONFIG_PS2MULT
#include <ps2mult.h>
#endif
#if !defined(kbd_request_region) || \
!defined(kbd_request_irq) || \
!defined(kbd_read_input) || \
!defined(kbd_read_status) || \
!defined(kbd_write_output) || \
!defined(kbd_write_command)
#error PS/2 low level routines not defined
#endif
extern int kbd_init (void);
extern void handle_scancode(unsigned char scancode);
extern int kbd_init_hw(void);
extern void pckbd_leds(unsigned char leds);
#endif /* __KEYBOARD_H */
|
1001-study-uboot
|
include/keyboard.h
|
C
|
gpl3
| 537
|
/* (C) Copyright 2002
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************/
/* ** Layout of a bmp file */
/************************************************************************/
#ifndef _BMP_H_
#define _BMP_H_
typedef struct bmp_color_table_entry {
__u8 blue;
__u8 green;
__u8 red;
__u8 reserved;
} __attribute__ ((packed)) bmp_color_table_entry_t;
/* When accessing these fields, remember that they are stored in little
endian format, so use linux macros, e.g. le32_to_cpu(width) */
typedef struct bmp_header {
/* Header */
char signature[2];
__u32 file_size;
__u32 reserved;
__u32 data_offset;
/* InfoHeader */
__u32 size;
__u32 width;
__u32 height;
__u16 planes;
__u16 bit_count;
__u32 compression;
__u32 image_size;
__u32 x_pixels_per_m;
__u32 y_pixels_per_m;
__u32 colors_used;
__u32 colors_important;
/* ColorTable */
} __attribute__ ((packed)) bmp_header_t;
typedef struct bmp_image {
bmp_header_t header;
/* We use a zero sized array just as a placeholder for variable
sized array */
bmp_color_table_entry_t color_table[0];
} bmp_image_t;
/* Data in the bmp_image is aligned to this length */
#define BMP_DATA_ALIGN 4
/* Constants for the compression field */
#define BMP_BI_RGB 0
#define BMP_BI_RLE8 1
#define BMP_BI_RLE4 2
#endif /* _BMP_H_ */
|
1001-study-uboot
|
include/bmp_layout.h
|
C
|
gpl3
| 2,197
|
#ifndef DO_DEPS_ONLY
#include <generated/generic-asm-offsets.h>
/* #include <generated/asm-offsets.h> */
#endif
|
1001-study-uboot
|
include/asm-offsets.h
|
C
|
gpl3
| 114
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <fpga.h>
#ifndef _ALTERA_H_
#define _ALTERA_H_
/* Altera Model definitions
*********************************************************************/
#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 )
#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 )
#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 )
#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
/* Add new models here */
/* Altera Interface definitions
*********************************************************************/
#define CONFIG_SYS_ALTERA_IF_PS CONFIG_SYS_FPGA_IF( 0x1 ) /* passive serial */
#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast passive parallel */
/* Add new interfaces here */
typedef enum { /* typedef Altera_iface */
min_altera_iface_type, /* insert all new types after this */
passive_serial, /* serial data and external clock */
passive_parallel_synchronous, /* parallel data */
passive_parallel_asynchronous, /* parallel data */
passive_serial_asynchronous, /* serial data w/ internal clock (not used) */
altera_jtag_mode, /* jtag/tap serial (not used ) */
fast_passive_parallel, /* fast passive parallel (FPP) */
fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */
max_altera_iface_type /* insert all new types before this */
} Altera_iface; /* end, typedef Altera_iface */
typedef enum { /* typedef Altera_Family */
min_altera_type, /* insert all new types after this */
Altera_ACEX1K, /* ACEX1K Family */
Altera_CYC2, /* CYCLONII Family */
Altera_StratixII, /* StratixII Familiy */
/* Add new models here */
max_altera_type /* insert all new types before this */
} Altera_Family; /* end, typedef Altera_Family */
typedef struct { /* typedef Altera_desc */
Altera_Family family; /* part type */
Altera_iface iface; /* interface type */
size_t size; /* bytes of data part can accept */
void * iface_fns;/* interface function table */
void * base; /* base interface address */
int cookie; /* implementation specific cookie */
} Altera_desc; /* end, typedef Altera_desc */
/* Generic Altera Functions
*********************************************************************/
extern int altera_load(Altera_desc *desc, const void *image, size_t size);
extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
extern int altera_info(Altera_desc *desc);
/* Board specific implementation specific function types
*********************************************************************/
typedef int (*Altera_pre_fn)( int cookie );
typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
typedef int (*Altera_status_fn)( int cookie );
typedef int (*Altera_done_fn)( int cookie );
typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
typedef int (*Altera_abort_fn)( int cookie );
typedef int (*Altera_post_fn)( int cookie );
typedef struct {
Altera_pre_fn pre;
Altera_config_fn config;
Altera_status_fn status;
Altera_done_fn done;
Altera_clk_fn clk;
Altera_data_fn data;
Altera_abort_fn abort;
Altera_post_fn post;
} altera_board_specific_func;
#endif /* _ALTERA_H_ */
|
1001-study-uboot
|
include/altera.h
|
C
|
gpl3
| 4,372
|
/*****************************************************************************
* (C) Copyright 2003; Tundra Semiconductor Corp.
* (C) Copyright 2006; Freescale Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*****************************************************************************/
/*
* FILENAME: tsi108.h
*
* Originator: Alex Bounine
*
* DESCRIPTION:
* Common definitions for the Tundra Tsi108 bridge chip
*
*/
#ifndef _TSI108_H_
#define _TSI108_H_
#define TSI108_HLP_REG_OFFSET (0x0000)
#define TSI108_PCI_REG_OFFSET (0x1000)
#define TSI108_CLK_REG_OFFSET (0x2000)
#define TSI108_PB_REG_OFFSET (0x3000)
#define TSI108_SD_REG_OFFSET (0x4000)
#define TSI108_MPIC_REG_OFFSET (0x7400)
#define PB_ID (0x000)
#define PB_RSR (0x004)
#define PB_BUS_MS_SELECT (0x008)
#define PB_ISR (0x00C)
#define PB_ARB_CTRL (0x018)
#define PB_PVT_CTRL2 (0x034)
#define PB_SCR (0x400)
#define PB_ERRCS (0x404)
#define PB_AERR (0x408)
#define PB_REG_BAR (0x410)
#define PB_OCN_BAR1 (0x414)
#define PB_OCN_BAR2 (0x418)
#define PB_SDRAM_BAR1 (0x41C)
#define PB_SDRAM_BAR2 (0x420)
#define PB_MCR (0xC00)
#define PB_MCMD (0xC04)
#define HLP_B0_ADDR (0x000)
#define HLP_B1_ADDR (0x010)
#define HLP_B2_ADDR (0x020)
#define HLP_B3_ADDR (0x030)
#define HLP_B0_MASK (0x004)
#define HLP_B1_MASK (0x014)
#define HLP_B2_MASK (0x024)
#define HLP_B3_MASK (0x034)
#define HLP_B0_CTRL0 (0x008)
#define HLP_B1_CTRL0 (0x018)
#define HLP_B2_CTRL0 (0x028)
#define HLP_B3_CTRL0 (0x038)
#define HLP_B0_CTRL1 (0x00C)
#define HLP_B1_CTRL1 (0x01C)
#define HLP_B2_CTRL1 (0x02C)
#define HLP_B3_CTRL1 (0x03C)
#define PCI_CSR (0x004)
#define PCI_P2O_BAR0 (0x010)
#define PCI_P2O_BAR0_UPPER (0x014)
#define PCI_P2O_BAR2 (0x018)
#define PCI_P2O_BAR2_UPPER (0x01C)
#define PCI_P2O_BAR3 (0x020)
#define PCI_P2O_BAR3_UPPER (0x024)
#define PCI_MISC_CSR (0x040)
#define PCI_P2O_PAGE_SIZES (0x04C)
#define PCI_PCIX_STAT (0x0F4)
#define PCI_IRP_STAT (0x184)
#define PCI_PFAB_BAR0 (0x204)
#define PCI_PFAB_BAR0_UPPER (0x208)
#define PCI_PFAB_IO (0x20C)
#define PCI_PFAB_IO_UPPER (0x210)
#define PCI_PFAB_MEM32 (0x214)
#define PCI_PFAB_MEM32_REMAP (0x218)
#define PCI_PFAB_MEM32_MASK (0x21C)
#define CG_PLL0_CTRL0 (0x210)
#define CG_PLL0_CTRL1 (0x214)
#define CG_PLL1_CTRL0 (0x220)
#define CG_PLL1_CTRL1 (0x224)
#define CG_PWRUP_STATUS (0x234)
#define MPIC_CSR(n) (0x30C + (n * 0x40))
#define SD_CTRL (0x000)
#define SD_STATUS (0x004)
#define SD_TIMING (0x008)
#define SD_REFRESH (0x00C)
#define SD_INT_STATUS (0x010)
#define SD_INT_ENABLE (0x014)
#define SD_INT_SET (0x018)
#define SD_D0_CTRL (0x020)
#define SD_D1_CTRL (0x024)
#define SD_D0_BAR (0x028)
#define SD_D1_BAR (0x02C)
#define SD_ECC_CTRL (0x040)
#define SD_DLL_STATUS (0x250)
#define TS_SD_CTRL_ENABLE (1 << 31)
#define PB_ERRCS_ES (1 << 1)
#define PB_ISR_PBS_RD_ERR (1 << 8)
#define PCI_IRP_STAT_P_CSR (1 << 23)
/*
* I2C : Register address offset definitions
*/
#define I2C_CNTRL1 (0x00000000)
#define I2C_CNTRL2 (0x00000004)
#define I2C_RD_DATA (0x00000008)
#define I2C_TX_DATA (0x0000000c)
/*
* I2C : Register Bit Masks and Reset Values
* definitions for every register
*/
/* I2C_CNTRL1 : Reset Value */
#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
/* I2C_CNTRL1 : Register Bits Masks Definitions */
#define I2C_CNTRL1_DEVCODE (0x0000000f)
#define I2C_CNTRL1_PAGE (0x00000700)
#define I2C_CNTRL1_BYTADDR (0x00ff0000)
#define I2C_CNTRL1_I2CWRITE (0x01000000)
/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
#define I2C_CNTRL1_RWMASK (0x01ff070f)
/* I2C_CNTRL1 : Unused/Reserved bits Definition */
#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
/* I2C_CNTRL2 : Reset Value */
#define I2C_CNTRL2_RESET_VALUE (0x00000000)
/* I2C_CNTRL2 : Register Bits Masks Definitions */
#define I2C_CNTRL2_SIZE (0x00000003)
#define I2C_CNTRL2_LANE (0x0000000c)
#define I2C_CNTRL2_MULTIBYTE (0x00000010)
#define I2C_CNTRL2_START (0x00000100)
#define I2C_CNTRL2_WR_STATUS (0x00010000)
#define I2C_CNTRL2_RD_STATUS (0x00020000)
#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
#define I2C_CNTRL2_RWMASK (0x0000011f)
/* I2C_CNTRL2 : Unused/Reserved bits Definition */
#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
/* I2C_RD_DATA : Reset Value */
#define I2C_RD_DATA_RESET_VALUE (0x00000000)
/* I2C_RD_DATA : Register Bits Masks Definitions */
#define I2C_RD_DATA_RBYTE0 (0x000000ff)
#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
#define I2C_RD_DATA_RBYTE3 (0xff000000)
/* I2C_RD_DATA : Read/Write Bit Mask Definition */
#define I2C_RD_DATA_RWMASK (0x00000000)
/* I2C_RD_DATA : Unused/Reserved bits Definition */
#define I2C_RD_DATA_RESERVED (0x00000000)
/* I2C_TX_DATA : Reset Value */
#define I2C_TX_DATA_RESET_VALUE (0x00000000)
/* I2C_TX_DATA : Register Bits Masks Definitions */
#define I2C_TX_DATA_TBYTE0 (0x000000ff)
#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
#define I2C_TX_DATA_TBYTE3 (0xff000000)
/* I2C_TX_DATA : Read/Write Bit Mask Definition */
#define I2C_TX_DATA_RWMASK (0xffffffff)
/* I2C_TX_DATA : Unused/Reserved bits Definition */
#define I2C_TX_DATA_RESERVED (0x00000000)
#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
/* I2C status codes */
#define TSI108_I2C_SUCCESS 0
#define TSI108_I2C_PARAM_ERR 1
#define TSI108_I2C_TIMEOUT_ERR 2
#define TSI108_I2C_IF_BUSY 3
#define TSI108_I2C_IF_ERROR 4
#endif /* _TSI108_H_ */
|
1001-study-uboot
|
include/tsi108.h
|
C
|
gpl3
| 6,507
|
/*
* (C) Copyright 2001
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Watchdog functions and macros.
*/
#ifndef _WATCHDOG_H_
#define _WATCHDOG_H_
#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG)
# error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
#endif
/*
* Hardware watchdog
*/
#ifdef CONFIG_HW_WATCHDOG
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET bl hw_watchdog_reset
#else
extern void hw_watchdog_reset(void);
#define WATCHDOG_RESET hw_watchdog_reset
#endif /* __ASSEMBLY__ */
#else
/*
* Maybe a software watchdog?
*/
#if defined(CONFIG_WATCHDOG)
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET bl watchdog_reset
#else
extern void watchdog_reset(void);
#define WATCHDOG_RESET watchdog_reset
#endif
#else
/*
* No hardware or software watchdog.
*/
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET /*XXX DO_NOT_DEL_THIS_COMMENT*/
#else
#define WATCHDOG_RESET() {}
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
#endif /* CONFIG_HW_WATCHDOG */
/*
* Prototypes from $(CPU)/cpu.c.
*/
/* MPC 8xx */
#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__)
void reset_8xx_watchdog(volatile immap_t *immr);
#endif
/* MPC 5xx */
#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__)
void reset_5xx_watchdog(volatile immap_t *immr);
#endif
/* MPC 5xxx */
#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__)
void reset_5xxx_watchdog(void);
#endif
/* AMCC 4xx */
#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
void reset_4xx_watchdog(void);
#endif
#endif /* _WATCHDOG_H_ */
|
1001-study-uboot
|
include/watchdog.h
|
C
|
gpl3
| 2,462
|