hash stringlengths 32 32 | doc_id stringlengths 7 13 | section stringlengths 3 121 | content stringlengths 0 2.2M |
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78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.3 Ethernet & Power over Coax system block diagram | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.3.1 rDEV (Receiver Device) definition | An E&PoC receiver device, or rDEV, is an E&PoC device having receiver capability. An E&PoC receiver device (rDEV) shall provide coaxial cable connectivity. An rDEV is in charge of receiving video streams from one or more eDEV it is connected to, while supplying power to these eDEV through a Coax cable. An rDEV may embed one or more rSTAs (see also clause 4.3.3). A typical Receiver Device is a PoC switch device, which is compliant with the present specification document. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 11 Figure 2: E&PoC system block diagram |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.3.2 eDEV (Edge Device) / eSYS definition | An E&PoC edge device, or eDEV, is an E&PoC device connected to an rDEV device through a coaxial cable, through one of the topologies defined in clause 4.4. An E&PoC edge device (eDEV) shall provide coaxial cable connectivity. An eDEV embeds exactly one eSTA (see also clause 4.3.4). A Typical Edge Device may be a PoC adapter, connected to a PoE camera, or a PoC camera (as displayed in Figure 1), which are compliant with the present specification document. An eDEV shall belong to one of the two following eDEV types: • Adapter eDEV. An adapter eDEV is in charge of forwarding data content - e.g. video stream(s) - from a communication device (e.g. an IP camera) to the rDEV it is connected to, while receiving power from this rDEV through the coaxial cable. An Adapter eDEV shall be capable of forwarding power to its connected communication device. NOTE: Local powering of the connected communication device, even if not prevented, is out of the scope of the present document and should be addressed in a future specification revision. • Terminal eDEV. A Terminal eDEV is in charge of transmitting data content - e.g. video stream(s) for a camera - to the rDEV it is connected to, while receiving power from this rDEV through the coaxial cable. Terminal eDEV devices are IP devices implementing an IPv4 or an IPv6 stack. The entity composed of an Adapter eDEV and the communication device (e.g. an IP camera) connected to this Adapter eDEV, is referred to as an eSYS. A Terminal eDEV is also considered as an eSYS. Therefore, in the following clauses of the present document, eSYS refers to either an entity composed of an Adapter eDEV and the communication device (e.g. an IP camera) connected to this Adapter eDEV or a Terminal eDEV. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.3.3 rSTA (Receiver Station) definition | An rSTA is an E&PoC station (E&PoC STA) embedded in an rDEV. An rSTA is typically an IEEE 1901 (as defined in [1]) or a HomePlugAV (as defined in [2] or [3]) chipset embedded in an rDEV. The communication network mode of an rSTA shall be compliant with the requirement of Table 1. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 12 An rSTA may be physically connected to one or more Edge Stations (eSTAs), through one or more rDEV ports. One or more rSTAs may belong to one same rDEV. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.3.4 eSTA (Edge Station) definition | An eSTA is an E&PoC station (E&PoC STA) embedded in an eDEV. An eSTA is typically an IEEE1901 (as defined in [1]) or a HomePlugAV (as defined in [2] or [3]) chipset embedded in an eDEV. The communication network mode of an eSTA should be compliant with the requirement of Table 1. An eSTA shall be physically connected to one single rSTA, through one single rDEV port, which provides power supply to the connected eDEV. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.4 Supported topologies | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.4.1 Forewords on supported topologies | The present E&PoC specification is addressing the topologies described in clauses 4.4.2 and 4.4.3. Any other topology is out of the scope of the present document. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.4.2 Linear Bus topology | In a linear bus topology (as depicted in Figure 1), at least two eDEV / eSYS are connected to a same rDEV port, using T-connectors. It is recommended to limit the length of the cable connecting the T-connector to the eDEV / eSYS to no more than 3 m. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 4.4.3 Point-to-point topology | In a point-to-point topology (as depicted in Figure 1), only one eDEV / eSYS is connected to an rDEV port. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5 Interoperability requirements for an E&PoC system | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.1 Communication mode background | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.1.1 Specification context | The E&PoC network consists of several E&PoC edge stations (eSTA) connected to an E&PoC receiver station (rSTA) that interact over a coaxial cable medium to provide a power distribution and video data transport network, which supports station portability transparently to upper layers as well as service across a broad area. An E&PoC station (STA), either eSTA or rSTA, is one of the followings: • An IEEE 1901 STA operated in In-Home / FFT mode, as defined in [1] • A HomePlugAV 1.1 STA, as defined in [2] • A HomePlugAV 2.1 STA, as defined in [3] Inside an E&PoC system, the wiring topology may be constrained in terms of number of eSTA connected to an rSTA / number of eSTA connected to one port of an rSTA. Clauses 6 and 7 provide requirements on power management and data transmission in relation with such topology constraints. An E&PoC system is made of one or more logical networks, or E&PoC Basic Service Set (BSS). ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 13 Figure 1 shows how coax cable network configuration for a given E&PoC system can vary depending on how the wiring is laid out, what is connected to the coaxial cable segment, and where it is connected. In general, each segment has either a star-topology wiring or a linear bus topology originating from the rSTA. In order to ensure interoperability between E&PoC stations (both eSTA and rSTA) and HomePlugAV stations, an E&PoC STA shall be either a HomePlugAV 1.1 STA, a HomePlugAV 2.1 STA or an IEEE1901 FFT STA [1]. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.1.2 Requirements | Table 1: Communication network mode E&PoC Receiver Station (rSTA) / E&PoC Edge Station (eSTA) Requirement 5.1.1 An E&PoC STA shall be compliant with one of the following modes: • In-Home mode, as described in [1]. In such case, the E&PoC BSS shall be operated as an In-home BSS, as described in [1]. • HomePlugAV 1.1 STA, as defined in [2]. In such case, the E&PoC BSS shall be operated as an AVLN, as described in [2]. • HomePlugAV 2.1 STA, as defined in [3]. In such case, the E&PoC BSS shall be operated as an AVLN, as described in [3]. Table 2: E&PoC Physical/MAC layer for IEEE1901-compliant devices E&PoC Receiver Station (rSTA) / E&PoC Edge Station (eSTA) Requirement 5.1.2 An E&PoC STA that operates the In-Home mode, as described in [1], shall behave as an IEEE 1901 FFT STA, therefore implementing the IEEE 1901 Fast Fourier transform (FFT) (orthogonal frequency division multiplexing (OFDM) physical layer (PHY)/medium access control (MAC), as defined in [1]. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.2 E&PoC System and BSS | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.2.1 Specification context | An E&PoC network is referred as a single E&PoC basic Service Set (E&PoC BSS). An E&PoC system is made of one or more rSTA and one or more eSTA (i.e. multiple E&PoC BSSs). An E&PoC BSS is managed by a single E&PoC STA, also referred as the "E&PoC BSS manager" (E&PoC BM). Any further reference to a "BM" in the present document implicitly refers to an E&PoC BM. The E&PoC BM of an E&PoC BSS may be either an rSTA or an eSTA. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 14 Figure 3: E&PoC BSSs |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.2.2 Requirements | Table 3: E&PoC System and BSS E&PoC Receiver Station (rSTA) / E&PoC Edge Station (eSTA) Requirement 5.2.1 An E&PoC STA shall join all the other E&PoC STAs it is physically connected to, so as to form an E&PoC BSS, provided they share the same E&PoC password / NMK. Any two E&PoC STAs that are part of the same E&PoC BSS shall be capable of communicating with each other. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.3 Neighbour networks | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.3.1 Specification context | An E&PoC BSS may need to operate in the presence of neighbour networks of other compatible E&PoC devices. Neighbour Network (NN) is an entirely autonomous association of E&PoC devices, which are operated autonomously. Typically, an E&PoC BSS involving several rSTA belonging to one same device - e.g. multi-chipset switch device embedding several IEEE 1901 / HomePlugAV chipset - may experience substantial inter-network signal crosstalk - i.e. signals from one E&PoC BSS may be detectable on adjacent E&PoC BSSs. In case of multi-chipset switch device, signal crosstalk may result from coupling between the device chipsets. This Crosstalk Interference (CI) leads to substantial performance degradation resulting in: • wrong STA association, i.e. as outside network signals may appear as valid signals to the adjacent networks, one eSTA may associate to an rSTA it is not actually connected; • significantly reduced throughput; or • even loss of service at specific STAs or even network wide. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 15 In order to mitigate the effects of crosstalk interference (CI) while not affecting the overall E&PoC BSS performance, the following measures should be considered: • Any two receiver stations (rSTAs) belonging to a same receiver device (rDEV) shall never associate with each other and, therefore, join the same E&PoC BSS. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.3.2 Requirements | Table 4: Neighbour networks E&PoC Receiver Device (rDEV) Requirement 5.3.1 Any two receiver stations (rSTAs) belonging to a same receiver device (rDEV) shall never join the same E&PoC BSS. Requirement 5.3.2 Any two receiver stations (rSTAs) belonging to different receiver devices (rDEV) shall never join the same E&PoC BSS. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.4 Security in E&PoC system | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.4.1 Specification context | A typical E&PoC system may be made of hundreds of camera devices. One should keep in mind that changing the Password/NMK of some of the STAs in the system may significantly increase the overall system maintenance, as the list of the several Password/NMK used in the system should be recorded and maintained. Therefore, an E&PoC STA, either eSTA or rSTA, shall implement the default Password/NMK value provided in Table 6 or Table 7. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.4.2 Requirements | Table 5: Default Password/NMK E&PoC Receiver Station (rSTA) / E&PoC Edge Station (eSTA) Requirement 5.4.1 An E&PoC STA (both rSTA and eSTA) shall implement the default E&PoC Password/NMK value provided in Table 6 or Table 7. Table 6: E&PoC default Password Item Parameter Symbol Value 1 E&PoC Default Password 0 PasswordE&PoC0 HomePlugAV Table 7: E&PoC default NMK Item Parameter Symbol Value 1 E&PoC Default NMK0 NMKE&PoC0 50:D3:E4:93:3F:85:5B:70:40:78:4D:F8:15:AA:8D:B7 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.5 Receiver Device (rDEV) per-port PoC reset | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.5.1 Specification context | In case an eDEV software is stalled, it may be valuable to perform a hardware reset of this device. Such hardware reset may be performed remotely by performing rDEV port power OFF / power ON. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 16 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.5.2 Requirements | Table 8: Receiver Device (rDEV) per-port PoC reset (Conditional) E&PoC Receiver Device (rDEV) Requirement 5.5.1 When the Power over Coax (PoC) supply is turned off for one port of an rSTA connecting one or more eSTAs, in an initial E&PoC BSS, all the other E&PoC STAs (both the rSTA and eSTAs connected on the remaining ports of the rSTA) from this initial E&PoC BSS shall keep effective connectivity. This requirement assumes all the eSTAs are powered through the Coax cable (i.e. eSTA local powering is excluded from this requirement). Requirement 5.5.2 When the Power over Coax (PoC) supply is turned on for one port of an rSTA connecting one or more eSTAs, all these eSTAs shall join the E&PoC BSS made of the E&PoC STAs they are physically connected to the other ports of the rSTA, so as to form an E&PoC BSS that provides effective connectivity between all these E&PoC STAs. This requirement assumes all the eSTAs are powered through the Coax cable (i.e. eSTA local powering is excluded from this requirement). |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.6 Support to installation (Optional) | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.6.1 Specification context | Installing one or more E&PoC Terminal eDEVs according to a daisy-chain topology requires for the installer some minimum knowledge on the eDEV's typical and maximum power consumption. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.6.2 Requirements | Table 9: Support to installation (Optional) E&PoC Edge Device (eDEV) Requirement 5.6.1 The eDEV vendor shall provide the nominal power consumption and the maximum power consumption of the eDEV, along with the associated eDEV operating mode configurations. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.7 Hot-Plug support | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.7.1 Specification context | The data streaming - such as video streaming - sent by the eDEV to the rDEV is considered as a highly critical information. Losing some of this information, even temporarily, would have significant impact on the user experience and is therefore considered as not acceptable. This is why the addition of a new eDEV to any existing E&PoC network should not impact the performance of any eDEV already operated in the network. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 5.7.2 Requirements | Table 10: Hot-Plug support E&PoC Edge System (eSYS) Requirement 5.7.1 Adding a new eSYS to an existing E&PoC BSS shall not cause any data communication error to the existing data communication currently operated over this E&PoC BSS. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 17 6 Power distribution requirements for an E&PoC system |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.1 Edge DEV (eDEV) / Edge System (eSYS) power | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.1.1 Specification context | In order to limit current consumption over the cable medium, it is important that an eDEV, or an eSYS, operates within a bounded range of input voltage. In this respect, as described in Figure 4. • The eDEV (resp. eSYS) shall turn on at a voltage less than or equal to VONmax and greater than VOFFmin. • The eDEV (resp. eSYS) shall turn off at a voltage less than VOFFmin. The eDEV (resp. eSYS) shall never turn off at a voltage greater than VOFFmax. • When the voltage of an eDEV (resp. eSYS) is less than VOFFmin, the power consumption of this eDEV (resp. eSYS) shall not exceed PSTANDBYmax range. Figure 4: eDEV power limits The following eDEV Types shall be considered: • Type-0 eDEV. A Type-0 eDEV is an Adapter eDEV. A Type-0 eDEV shall ensure that it meets the above requirements. A Type-0 eDEV may not ensure that the eSYS it is part of meets the above requirements. Type-0 eDEVs introduce potential risk of power failure and line instability in daisy-chain topologies. • Type-I eDEV. A Type-I eDEV may be either an Adapter eDEV or a Terminal eDEV. A Type-I eDEV shall ensure that itself, as well as the eSYS it is part of, meets the above requirements. Therefore, Type-I eDEVs are well-suited, and therefore recommended, for linear bus topologies connecting several eDEVs powered through the coax cable. • Type-I+ eDEV. A Type-I+ eDEV may be either an Adapter eDEV or a Terminal eDEV. A Type-I+ eDEV shall ensure that itself, as well as the eSYS it is part of, meets the above requirements. Therefore, Type-I+ eDEVs are well-suited, and therefore recommended, for linear bus topologies connecting several eDEVs powered through the coax cable. Moreover, adding a new Type-I+ eDEV/eSYS to an existing E&PoC BSS shall not cause any eDEV/eSYS already operated on this BSS to interrupt its service due to a lack of power. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 18 Based on the above considerations, the following recommendations should be considered: • The use of Type-0 adapters should be limited to point-to-point topologies (see also clause 4.4.3). • A Type-0 adapter should rely on local powering when operated in a linear bus topology (see also clause 4.4.2). The eDEV (resp. eSYS) may be capable of drawing power from a local power source. When a local power source is provided, the eSTA may draw some, none, or all of its power from the eDEV (resp. eSYS). |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.1.2 Requirements | Table 11: eDEV Type-I / Type-I+ power E&PoC Edge Device (eDEV) Type-I / Type-I+ Requirement 6.1.1 The power supply of a Type-I eDEV shall operate within the characteristics in Table 13 hereafter. A Type-I eDEV shall ensure that the power supply of the eSYS it is part of operates within the characteristics in Table 13 hereafter. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.1.3 Requirements | Table 12: eDEV Type-0 power E&PoC Edge Device (eDEV) Type-0 Requirement 6.1.2 The power supply of a Type-0 eDEV shall operate within the characteristics in Table 13 hereafter. A Type-0 eDEV may not ensure that the eSYS it is part of operates within the characteristics in Table 13 hereafter. Requirement 6.1.3 A Type-0 eDEV shall provide connectivity for local powering. It is highly recommended to limit the usage of Type-0 eDEVs to point-to-point topology. It is highly recommended to rely on local powering when using a Type-0 eDEV in a linear bus topology. Table 13: eDEV power limits Item Parameter Symbol Unit Value 1 Max eDEV input voltage VeSTAmax V 57 2 Max eDEV Power supply turn on voltage VONmax V 44 3 Min eDEV Power supply turn off voltage VOFFmin V 32 4 Max eDEV Power supply turn off voltage VOFFmax V 39 5 Max standby power consumption PSTANDBYmax W 4 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.1.4 Requirements | Table 14: eDEV Type-I+ Hot-Plug support (Optional) E&PoC Edge Device (eDEV) Type-I+ Requirement 6.1.4 Adding a new eDEV/eSYS to an existing E&PoC BSS shall not cause any eDEV/eSYS already operated on this E&PoC BSS to interrupt its service due to a lack of power. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 19 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.2 Receiver Device (rDEV) per-port PoC | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.2.1 Specification context | In order an rDEV to accommodate several eSYSs over a linear bus for one given rDEV port, relying on a cable type having significant resistance, it is required to have the rDEV generating a minimum output Power PrDEV, (i.e. a minimum output power per rDEV port) and associated voltage VrDEVOn on the line, according to one of the several rDEV power classes defined in Table 16. In this respect: • The specification for PrDEV and VrDEVOn in Table 16 is for the rDEV output power and output voltage range for an active rDEV port. • The maximum power PrDEV of an rDEV, regardless of its power class, shall not exceed 99,9 W. The E&POC system defined in the present document uses floating ground. It is therefore required that the negative potential is connected to the outer shield of the coaxial cable for each of the rDEV ports. |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.2.2 Requirements | Table 15: rDEV power E&PoC Receiver Device (rDEV) Requirement 6.2.1 A Receiver Device (rDEV) shall be capable of supplying an output Power PrDEV and an output voltage VrDEVOn over any of its port, with PrDEV and VrDEVOn having the characteristics specified in Table 16. Requirement 6.2.2 The maximum power PrDEV of an rDEV, regardless of its power class, shall not exceed 99,9 W Requirement 6.2.3 The negative potential shall be located onto the outer shield of the coaxial cable for each port of a Receiver Device (rDEV) Table 16: rDEV power on supply limits rDEV class rDEV Output Power PrDEV (W) rDEV Output Voltage VrDEVOn (V) PrDEVmin VrDEVOnmin VrDEVOnmax 1 4 53,5 57,0 2 7 53,5 57,0 3 15,4 53,5 57,0 4 30 53,5 57,0 5 45 53,5 57,0 6 60 53,5 57,0 7 75 53,5 57,0 8 90 53,5 57,0 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.3 Receiver Device (rDEV) per-port PoC control (Optional) | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.3.1 Specification context | One or more eSTA devices connected to one same port of an rDEV may experience some issues that require a reboot of such eSTA devices. Such reboot can be achieved by turning the power off on the rDEV port where such faulty device(s) is connected. In case the port of a manageable rDEV is set to off, the voltage VrDEVoff of this port under high impedance should follow the specification of Table 18. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 20 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 6.3.2 Requirements | Table 17: Receiver Device (rDEV) per-port PoC control (Conditional) E&PoC Receiver Device (rDEV) Requirement 6.3.1 A multi-port rDEV may provide either a User Interface (UI) or connectivity for a User Interface Station (UIS) that allows monitoring the value of the output voltage VrDEV (OR the level of PoC) on any of its ports. Requirement 6.3.2 A multi-port rDEV may provide either a User Interface (UI) or connectivity for a User Interface Station (UIS) that allows setting the output voltage to either VrDEVOn or VrDEVOff on any of its ports. Requirement 6.3.3 When a Receiver Device (rDEV) port is powered off, the voltage VrDEVoff of this port under high impedance shall not exceed a maximum value VrDEVoffmax as specified in Table 18. Table 18: rDEV power off supply limits Item Parameter Symbol Unit Value 1 Max output voltage per inactive rDEV port under high impedance VrDEVoffmax V 0,5 V 7 Data transmission requirements for an E&PoC system |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.1 Receiver Station / Device throughput capability | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.1.1 Specification context | An rDEV may embed a plurality of rSTAs (e.g. a 16-port PoC switch may embed 4 rSTAs), each rSTA being in charge of connecting one or more eSTAs arranged in a linear bus topology over one or more ports. Each connected eSTA should send video stream, to its connected rSTA. In this respect, some eSYS have the ability to generate several video streams simultaneously (e.g. multi-stream IP cameras). An rDEV is also in charge of forwarding all the video streams received from each of its connected eSYS to a remote client (e.g. VMS) or recording device over a LAN. Therefore, an rSTA shall be capable of: • Processing all the streams it receives over any of its ports from the connected eSTAs. • Processing all the streams it receives simultaneously over all of its ports from the connected eSTAs. Similarly, an rDEV shall be capable of: • Processing all the streams it receives simultaneously over all of its ports from the connected eSTAs. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 21 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.1.2 Requirements | Table 19: rSTA throughput capability E&PoC Receiver Station (rSTA) / Device (rDEV) Requirement 7.1.1 Each port of an rSTA shall be capable of handling a global stream bit rate per port that is at least equal to BrSTAPortmin1 for throughput class 1, 2 or 3 as defined in Table 20. Requirement 7.1.2 All ports of an rSTA shall be capable of handling simultaneously a global stream bit rate per port that is at least equal to BrSTAPortmin2 for throughput class 1, 2 or 3 as defined in Table 20. Requirement 7.1.3 All ports of all rSTAs of an rDEV shall be capable of handling simultaneously a global stream bit rate per port that is at least equal to BrSTAPortmin3 for throughput class 1, 2 or 3 as defined in Table 20. Table 20: rSTA / rDEV throughput constraints Item Parameter Symbol Unit Class 1 Class 2 Class 3 1 Minimum rSTA Port supported throughput for Requirement 7.1.1 BrSTAPortmin1 Mbps 80 200 240 2 Minimum rSTA Port supported throughput for Requirement 7.1.2 BrSTAPortmin2 Mbps 20 50 60 3 Minimum rSTA Port supported throughput for Requirement 7.1.3 BrSTAPortmin3 Mbps 20 50 60 Table 21: Network extension capability E&PoC Receiver Station (rSTA) / Device (rDEV) Requirement 7.1.4 Each port of an rSTA shall be capable of handling simultaneously a minimum of NeSTAperPortmin eSYS connected according to a linear bus topology (see Table 22) with a global stream bit rate per port that is at least equal to BrSTAPortmin3 for throughput class 1, 2 or 3 as defined in Table 20. Table 22: Network extension constraint Item Parameter Symbol Unit Min 1 Minimum number of eSTA per rDEV/rSTA port NeSTAperPortmin - 2 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.2 Adapter eDEV throughput & streaming capability | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.2.1 Specification context | An Adapter eDEV is in charge of forwarding the video stream it receives from a connected communication device, e.g. an IP camera, to an rSTA it is connected to through a coaxial cable. In this respect, some communication devices, e.g. multi-stream IP cameras, have the ability to generate several video streams simultaneously. Therefore, an Adapter eDEV shall be capable of processing all the streams it receives from a connected communication device, e.g. an IP camera. ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 22 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.2.2 Requirements | Table 23: Adapter eDEV throughput capability E&PoC Adapter Edge Device (Adapter eDEV) Requirement 7.2.1 The eSYS formed by the Adapter eDEV connected to a communication device (e.g. an IP camera), shall be capable of transmitting towards an rSTA a stream with a throughput up to BAdaptEDEV1 for throughput class 1, 2 or 3 as defined in Table 24. Requirement 7.2.2 The eSYS formed by the Adapter eDEV connected to a communication device (e.g. an IP camera), shall be capable of transmitting towards an rSTA a stream with a throughput up to BAdaptEDEV2 for throughput class 1, 2 or 3 as defined in Table 24 when each port of the rSTA is connected to a minimum of NeSTAperPortmin eSYS in a linear bus topology (see Table 22). Table 24: Adapter eDEV throughput constraints Item Parameter Symbol Unit Class 1 Class 2 Class 3 1 Adapter eDEV supported throughput for Req. 7.2.1 BAdaptEDEV1 Mbps 80 200 240 2 Adapter eDEV supported throughput for Req. 7.2.2 BAdaptEDEV2 Mbps 10 25 30 Table 25: Adapter eDEV streaming capability E&PoC Adapter Edge Device (Adapter eDEV) Requirement 7.2.3 An Adapter eDEV shall be capable of transmitting towards an rSTA a minimum of NAdaptEDEVStreammin streams, with an aggregated throughput up to BAdaptEDEV1 for throughput class 1, 2 or 3 as defined in Table 24, received from a communication device (see Table 26). Table 26: Adapter eDEV streaming constraint Item Parameter Symbol Unit Min 1 Minimum number of streams supported by an Adapter eDEV NAdaptEDEVStreammin - 2 |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.3 Terminal eDEV throughput & streaming capability | |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.3.1 Specification context | A Terminal eDEV, e.g. a PoC camera, is in charge of sending video stream to an rSTA it is connected to through a coaxial cable. In this respect, some Terminal eDEVs have the ability to generate several video streams simultaneously (e.g. multi-stream IP cameras). |
78562718753e0d19d95686376ba8abd8 | 105 176-2 | 7.3.2 Requirements | Table 27: Terminal eDEV throughput capability E&PoC Terminal Edge Device (Terminal eDEV) Requirement 7.3.1 A Terminal eDEV shall be capable of transmitting a stream with a throughput up to BTerminalEDEV1 for throughput class 1, 2 or 3, as defined in Table 30, towards an rSTA when each port of the rSTA is connected to a minimum of NeSTAperPortmin eSYS in a linear bus topology (see Table 22). ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 23 Table 28: Terminal eDEV streaming capability (conditional) E&PoC Terminal Edge Device (Terminal eDEV) Requirement 7.3.2 A Terminal eDEV shall be capable of transmitting towards an rSTA a minimum of NTerminalEDEVStreammin streams, as defined in Table 29, with an aggregated throughput up to BTerminalEDEV2 for throughput class 1, 2 or 3 as defined in Table 30. This requirement applies only to Terminal eDEVs having the ability to generate and transmit more than one stream simultaneously. Table 29: Terminal eDEV streaming constraint (conditional) Item Parameter Symbol Unit Min 1 Minimum number of streams supported by a Terminal eDEV NTerminalEDEVStr eammin - 2 Table 30: Terminal eDEV throughput constraints Item Parameter Symbol Unit Class 1 Class 2 Class 3 1 Terminal eDEV supported throughput for Requirement 7.3.1 BTerminalEDEV1 Mbps 10 25 30 2 Terminal eDEV supported throughput for Requirement 7.3.2 BTerminalEDEV2 Mbps 80 200 240 ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 24 Annex A (normative): Requirements summary All the requirements listed in the previous clauses of the present document are gathered in Table Table hereafter. Table A.1: Requirements summary Requirement E&PoC device Type Req. ID Req. Status Adapter eDEV Type-0 Adapter eDEV Type-1 Terminal eDEV rDEV Requirement 5.1.1 - Communication network mode Mandatory Requirement 5.1.2 - E&PoC Physical/MAC layer Mandatory Requirement 5.2.1 - E&PoC System and BSS Mandatory Requirement 5.3.1 - Neighbour Networks Mandatory Requirement 5.3.2 - Neighbour Networks Mandatory Requirement 5.4.1 - Default Password/NMK Mandatory Requirement 5.5.1 - Receiver Device (rDEV) per-port PoC reset Conditional Requirement 5.5.2 - Receiver Device (rDEV) per-port PoC reset Conditional Requirement 5.6.1 - Support to installation Optional Requirement 5.7.1 - Hot-Plug support Mandatory Requirement 6.1.1 - eDEV Type-I / Type-I+ power Mandatory Requirement 6.1.2 - Type-0 power Mandatory Requirement 6.1.3 - Type-0 power Mandatory Requirement 6.1.4 - eDEV Type-I+ Hot-Plug support (applicable for eDEV Type-I+ only) Optional Requirement 6.2.1 - rDEV power Mandatory Requirement 6.2.2 - rDEV power Mandatory Requirement 6.2.3 - rDEV power Mandatory Requirement 6.3.1 - Receiver Device (rDEV) per-port PoC control Conditional Requirement 6.3.2 - Receiver Device (rDEV) per-port PoC control Conditional Requirement 6.3.3 - Receiver Device (rDEV) per-port PoC control Conditional Requirement 7.1.1 - rSTA throughput capability Mandatory Requirement 7.1.2 - rSTA throughput capability Mandatory Requirement 7.1.3 - rSTA throughput capability Mandatory Requirement 7.1.4 - Network extension capability Mandatory Requirement 7.2.1 - Adapter eDEV throughput capability Mandatory Requirement 7.2.2 - Adapter eDEV throughput capability Mandatory Requirement 7.2.3 - Adapter eDEV streaming capability Mandatory Requirement 7.3.1 - Terminal eDEV throughput capability Mandatory Requirement 7.3.2 - Terminal eDEV streaming capability Conditional ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 25 Annex B (informative): Change History Date Version Information about changes 2019-04-08 0.0.3 Annex A: changed from informative to normative 2019-04-11 0.0.4 Clause 6.2.1: Added clarification that "The E&POC system defined in the present document uses floating ground." ETSI ETSI TS 105 176-2 V1.1.1 (2019-06) 26 History Document history V1.1.1 June 2019 Publication |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 1 Scope | The present document provides a description of an OSI physical networking layer to communicate data over plastic optical fibre at 100 Mbit/s and 1 000 Mbit/s. A full duplex physical layer is described. Multi data type interface is proposed, as well as its encapsulation, coding and modulation needed to achieve 1 Gbit/s link over a bandwidth limited optical channel like the plastic optical fibre. Multiple link speeds are handled by this physical layer. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 2 References | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 2.1 Normative references | References are either specific (identified by date of publication and/or edition number or version number) or non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the reference document (including any amendments) applies. Referenced documents which are not found to be publicly available in the expected location might be found at http://docbox.etsi.org/Reference. NOTE: While any hyperlinks included in this clause were valid at the time of publication, ETSI cannot guarantee their long term validity. The following referenced documents are necessary for the application of the present document. [1] IEC 60793-2-40: "Optical fibres - Part 2-40: Product specifications - Sectional specification for category A4 multimode fibres". [2] ANSI/EIA/TIA-455-127-1991, FOTP-127/61.1 :"Spectral Characterization of Multimode Laser Diodes". [3] IEC 61754-20: "Fibre optic interconnecting devices and passive components - Fibre optic connector interfaces - Part 20: Type LC connector family". |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 2.2 Informative references | References are either specific (identified by date of publication and/or edition number or version number) or non-specific. For specific references, only the cited version applies. For non-specific references, the latest version of the reference document (including any amendments) applies. NOTE: While any hyperlinks included in this clause were valid at the time of publication, ETSI cannot guarantee their long term validity. The following referenced documents are not necessary for the application of the present document but they assist the user with regard to a particular subject area. [i.1] ISO/IEC 11801: "Information technology - Generic cabling for customer premises". |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 3 Definitions and abbreviations | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 3.1 Definitions | For the purposes of the present document, the following terms and definitions apply: adaptive bit rate: capacity of PHY to adapt the bit rate as a function of the channel conditions and signal quality in coordination with the link partner bose, ray-chaudhurim hocquenghem: in coding theory the BCH codes form a class of parameterized error-correcting codes, being its main advantage the ease with which they can be decoded using elegant algebraic methods cyclic redundancy check: error detecting code designed to detect accidental changes to raw data ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 8 control cyclic redundancy check: CRC employed to check the integrity of data in PDB.CTRL blocks data cyclic redundancy check: CRC employed to check the integrity of an encapsulated data packet and which is included in the PDB.CTRL block signalling the end of packet error vector magnitude: measure of the deviation between the actual signals compared to the ideal signals, commonly defined in statistical terms extinction ratio: ratio between the maximum and the minimum power of a given optical signal forward error correction: technique used for controlling errors in data transmission over unreliable or noisy communication channels jitter: time deviations of the signal arrival from its nominal timing link: transmission path between any two interfaces of generic cabling, see ISO/IEC 11801 [i.1] low power idle: time periods where the Physical Layer transmission is switched off to reduce the energy consumption, when no user data is available to transmit multi-level cosset code: forward error correcting technique consisting on splitting the information bit stream among several levels, for each one a binary component code is employed with an error correction capability according to the reliability experienced by each level in data transmission over noisy channels optical modulation amplitude: difference between the maximum and the minimum power of a given optical signal pulse amplitude modulation: form of signal modulation where the message information is encoded in the amplitude of a series of signal pulses physical data block: minimum data unit of 65 bits used to encapsulate the user information received from any PHY interface physical control data block: special case of PDB used to carry control information between encapsulator and de-encapsulator to identify parameters of a data packet like length or protocol, and to check the data integrity physical idle data block: special PDB.CTRL blocks used by encapsulator for continuous transmission over the physical communication channel when no user data are available for encapsulation received from the data interface physical padding data block: special case of PDB.CTRL block inserted in user data encapsulation to carry out the rate matching between the PHY interfaces and PHY bit-rate, when PHY bit-rate is greater than the interface bit-rate physical header data: information carried by the header sub-blocks inside the frame structure and used for control and negotiation of PHY parameters between both link ends physical header subframe: block of 128 symbols prepended and appended by 16 zeroes that represents the minimum transmit unit in which the PHD is divided after encoding and modulation and used to spread the PHD information along one frame signal to noise ratio: ratio between the average power of signal and the average power of noise in a given point tomlinson-harashima precoding: coding technique by which the communication transmit signal pre-equalizes a known inter-symbol interference without power penalty, providing communication signal at the output of channel without post-cursor inter-symbol interference |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 3.2 Abbreviations | For the purposes of the present document, the following abbreviations apply: ABR Adaptive Bit Rate AC Alternate Current AOP Average Optical Power BCH bose, ray-chaudhurim hocquenghem BER Bit Error Rate BPSK Binary Phase Shift Keying CCRC CRC of current PDB CMB Physical Coding and Modulation Blocks ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 9 CRC Cyclic Redundancy Code CW Code Word DAC Digital to Analogue Converter DCRC CRC of Data PDB EO Electro Optical Interface ER Extinction Ratio EVM Error Vector Magnitude FEC Forward Error Correction FER Frame Error Rate FS Symbol Frequency IDLE Idle IEC International Electrotechnical Commission IL Insertion Losses ISO International Organization for Standardization IT Information Technology LC Little Connector LED Light Emitting LFSR Linear Feedback Shift Register LPI Low Power Idle LSB Less Significant Bit MLCC Multi Level Cosset Code MLS Maximum Length Sequence NMLCC Length of the MLCC code word in 1D (PAM) symbols OFF Off state OMA Optical Modulation Amplitude ON On state OSI Open Systems Interconnection PAD Padding PAM Pulse Amplitude Modulation PDB Physical Data Block PDB-ER PDB Error Rate PHD Physical Header Data PHS Physical Header Subframe PHY Physical POF Plastic Optical Fibre PSD Power Spectral Density QAM Quadrature Amplitude Modulation RMS Root-Mean-Square RX Reception SF Scaling Factor SNR Signal to Noise Ratio TH Tomlinson-Harashima THP Tomlinson-Harashima Precoder TIA Trans Impedance Amplifier TX Transmission VCSEL Vertical Cavity Surface-Emitting Laser 4 1 Gbit/s and 100 Mbit/s data rate physical layer for plastic optical fibre |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 4.1 Physical layer objectives | The following are the objectives of the PHY: • Provide 1 Gbit/s and 100 Mbit/s full duplex data transmission. • Provide speeds less than 1 Gbit/s and 100 Mbit/s with adaptive bit rate functionality if communication channel does not provide enough capacity. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 10 • Support operation over Plastic Optical Fibres defined in IEC 60793-2-40 [1] types A4a.2 with the parameters specified in the respective annexes for each PHY. • Provide a Bit Error Rate (BER) less than or equal to 10-12. • Provide low power operation mode for power management. Figure 1: Link topology Data to be transmitted is provided to the PHY via de TX interface. The PHY generates the linear electrical signal which is converted into optical by the light source via the driver. Optical signal is sent through the fibre and received in the receiver of the other side of the link. In the receiver the Photo receiver transforms the optical signal into a linear electrical signal with a trans-impedance amplifier (TIA). The PHY transforms back this signal into the transmitted data, and provides it in the Rx interface. Baseband PAM signalling with a modulation rate that varies with the PHY speed is used. For example, when the speed is 1 000 Mbit/s, the symbol rate is 312,5 MSymbols/s, which results in a symbol period of 3,2 ns. The incoming bits are mapped to PAM symbols using a three level Multi-Level Cosset Code (MLCC). In the first two levels, blocks of bits are encoded using a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code with different coding rates while in the third level bits are not coded. The PHY can be divided into the following parts: • Coding and Modulation Blocks (CMB). • Electro Optical Interface (EO). |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 4.2 Coding and Modulation Blocks (CMB) | The PHY CMB couples the information in the data interface, to the Electro Optical interface (EO). The functions performed by the CMB comprise the generation of frames and the mapping of the bits in those frames to PAM symbols using the Multi-Level Cosset Coding technique, and to send them into a Tomlinson-Harashima Precoder (THP), which maps the PAM input into a quasi-continuous discrete time value. Then a power-scaling factor is applied to the symbols and this THP-processed symbol stream is then passed onto a Digital to Analogue Converter (DAC). Finally the analogue signal is sent to the EO interface. Frames are composed of pilots, a header and data blocks, all of them of fixed length. The pilots are intended to facilitate the receiver initialization and continuous tracking. The header is used to convey physical layer control information. Frames are transmitted continuously to ensure that the receivers are synchronized and the equalizers are aligned to the channel conditions. When no data is being received from the data interface, the blocks of data send the PDB.IDLE pattern described in clause 5.2.3.2. Optionally, the Low Power Idle (LPI) mode can be used together with the PDB.IDLE pattern to reduce energy consumption. The LPI mode is described in clause 5.2.2. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 11 The incoming data is mapped to PAM symbols using a Multi-Level Cosset Coding technique. Depending on the configuration, the bits are divided in up to three levels. In the first two, the incoming bits are encoded using a BCH code while in the third level the bits are left uncoded. Then the resulting bits are mapped to PAM symbols, scrambled and passed to the THP pre-coder and the power adaptation block. In the transmit direction the CMB receives data packets through the data interface and constructs CMB frames that are then mapped to PAM symbols. In the receive direction, the CMB extracts the information from the received CMB frames and maps them to data packets on the data interface. The receiver is responsible for acquiring symbol timing and equalizing the signal. Both linear and non-linear equalization may be used in the receiver. The reliability of the link is ensured by the CMB Link Monitor function. The CMB PHY Control function controls the CMB operations. PHY Control provides the start-up functions required for successful operation. Figure 2: PHY functional block diagram In figure 2 a block level description of the PHY is shown. Communication between different blocks is also shown. Three different areas are clearly described: the electro optical interface (EO), the coding and modulation blocks (CMB) and the data interface. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 4.3 Electro Optical Interface (EO) | The EO specifications detail the characteristics of the optical transmitter and receiver and also of the optical cabling. These are specific for each PHY and are defined in the annexes from A to D specifying each particular PHY. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 4.4 Signalling | PHY signalling is performed by the CMB generating symbols to be transmitted on to the EO interface. The signalling scheme achieves a number of objectives including: a) Forward error correction (FEC) coded symbol mapping for data. b) Uncorrelated symbols in the transmitted symbol stream. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 12 c) Block framing and other control signals. d) Energy Efficient operation through the use of the Low Power Idle (LPI) mode. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 4.5 Data Interfaces | Several data interfaces can be implemented over the described PHY. The present document does not specify any interface. The present document assumes data transmitted through the data interface is packet oriented vs. continuous stream. On the other hand, there is no limitation on this aspect in the PHY description of the present document. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5 Coding Blocks (CMB) | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.1 CMB introduction | The CMB comprises two functions: CMB transmit and CMB receive. The CMB couples the data interface to the EO interface. The CMB is defined only in abstract terms and does not imply any particular implementation. Regardless of the implementation used, the optical specifications at the optical output described in clause 7.2 and annexes from A to D shall be met. The CMB comprises the following functions: a) CMB Transmit. b) CMB Receive. c) PHY Control. d) Link Monitor. e) Clock Recovery. The CMB Receive function receives an electrical signal from the EO and extracts the PAM symbols for the payload and the physical header of the frame. The CMB Receive function is also in charge of equalizing the signal received from the EO. The CMB receive function shall map incoming PAM symbols, decode and unpack the data to be sent to the data interface. The PHY control function controls the operation of the PHY implementing the state machines for THP coefficients adaptation as well as the optional adaptive bit rate (ABR) to adapt the PHY rate to the channel conditions. The Link Monitor function determines the status of the link as a function of the local and remote CMB receive status as well as PHY control. The Clock recovery function is in charge of recovering the transmit clock of the remote PHY from the signal received from the EO, providing a recovered clock valid to properly sample the signal given by the EO_UNITDATA.indication(rx_signal) message. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2 CMB transmit function | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.1 Introduction to the CMB transmit function | The CMB transmit function maps the incoming data from the data interface onto PAM symbols that are sent to the THP precoder and to the power scaler. The transmission of data at the CMB is structured in frames. The CMB frames consist of pilots, a header and a payload that encodes the user data. All of them are of fixed length. The pilots are intended to aid in the receiver initialization and continuous tracking. The header provides mechanisms for PHY layer signalling between the local and remote devices. The incoming data from the data interface is encapsulated prior to transmission. Due to the use of the pilots and header, incoming data may need to be buffered before it can be transmitted. The encapsulated data is then scrambled and mapped to PAM symbols using the multilevel cosset coding (MLCC) technique. The CMB Transmit function then, performs THP filtering on the incoming PAM symbols that correspond to the payload data of a frame. Then power scaling is performed to ensure that the Optical Modulation Amplitude (OMA) is the same across the entire frame. Finally, the resulting signal is mapped to an electrical signal that is sent to the EO. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 13 Frames are transmitted continuously in both directions. When there is no data from the data interface the PDB.IDLE pattern is transmitted in the payload of the frame. Optionally, the Low Power Idle (LPI) mode can be used concurrently with the PDB.IDLE pattern to reduce energy consumption. The CMB Transmit function also carries out the power scaling of all the parts composing the frame, as S1, S2, PHS and payload, as well as the frame building and ordering. Then the resulting signal is mapped to an electrical signal that is sent to the EO. In addition, the CMB transmit function is in charge of generating the EO_TXPWR.request(tx_pwr) message to the EO, in order to turn off and turn on the transmit optical power when the CMB requests the CMB_DATATYPE.request(PAYLOAD_OFF) message. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.2 Frame structure | A frame comprises pilots, a header and a fixed payload of 225 792 symbols. The pilots and header are divided in sub- blocks and inserted in between the payload sub-blocks. Each header or pilot sub-block is composed of 160 symbols. For pilot and header sub-blocks, the first 16 symbols and the last 16 symbols take value zero. Each payload sub-block is composed of 8 064 symbols that extend an integer number of MLCC code words. The transmission of MLCC code words is aligned with the start of the payload sub-blocks. The code word has a length of 2 016 PAM symbols by default, although this may be configured before CMB initiates the transmission. Other lengths different from 2 016 symbols are reserved for future extensions (see clause 5.2.4.2). For 2 016 symbols length, every payload sub-block consists of 4 MLCC code words. The frame structure is illustrated in figure 3. The frame is composed of one S1 pilot sub-block, 13 S2 pilot sub-blocks, 14 header sub-blocks and 28 payload sub-blocks. This gives a total of 230 272 symbols. For a symbol frequency of 312,5 MHz the transmission of a frame requires 736,870 4 µs. Figure 3: Illustration of the frame structure As illustrated in figure 3, the pilot (S1, S2x) and header (PHSx) sub-blocks are transmitted once per payload sub-block. The frame always follows the same pattern starting by a S1 block and alternating S2 and PHS sub-blocks, even when the Low Power Idle mode is used. When both link ends have signalled support for the Low Power Idle mode using the procedure described in clause 5.3.2 the Low Power Idle mode may be used when there is no user data to transmit. The Low Power Idle (LPI) mode shall be signalled by CMB transmit function with parameter tx_type with value PAYLOAD_OFF. The frame with Low Power Idle is illustrated in figure 4. When LPI mode is used all pilot and header sub-blocks are transmitted, but the transmission can be stopped during the payload sub-block frames. This mode always affects complete payload sub-blocks so it is not possible to stop or restart the transmission in the middle of a payload sub-block. The algorithms to determine when to signal LPI as a function of incoming user data from the data interface are left to the implementer. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 14 Figure 4: Illustration of the Low Power Idle (LPI) mode All the sub-blocks of a frame are mapped to PAM symbols for transmission but a different mapping is used in each case. Figure 5 illustrates the process of building a frame showing the mapping for each of the parts of the frame. The figure 5 also shows which sub-clause (CMB or EO) defines each function needed to build a frame. Figure 5: Illustration of the frame building process and the different functional blocks |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3 Payload encoding | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.1 Introduction to payload encoding | The incoming data from the data interface is first encapsulated for transmission. Then the data is scrambled and mapped to PAM symbols using the MLCC technique. The parameters of the MLCC mapping depend on the speed and reach of the PHY. They are specified for each particular PHY in the corresponding annexes from A to D. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.2 Data encapsulation | The incoming data is encapsulated using the two kinds of blocks illustrated in figure 6. The input data is segmented and encapsulated in blocks of 64 bits. One control bit is added at the beginning of each block to mark it as a control or data block. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 15 Figure 6: Data encapsulation data blocks The control blocks (PDB.CTRL) are used to signal the start and the end of data packets. There are also special PDB.CTRL blocks that do not signal start/end of data packets and are used for other purposes. The PDB.CTRL block has the PDB.TYPE bit set to 1 and it is specified in table 1. Table 1: PDB.CTRL block definition for data encapsulation control Symbol Description # of bits Valid values PDB.TYPE Indicates the type of PDB (for control or user data) 1 1: The current PDB is PDB.CTRL PDB.CTRL.EOP.FLG Indicates a packet end in the next PDB.DATA block. Offset where the packet ends is indicated by PDB.CTRL.EOP.OFFSET. 1 0: No end of packet in the next PDB.DATA 1: End of packet in the next PDB.DATA PDB.CTRL.EOP.OFFSET When PDB.CTRL.EOP.FLG is 1, this field indicates offset in number of bits to the last bit of the packet in the next PDB.DATA. PDB.TYPE is not counted. 6 0x00 to 0x3F PDB.CTRL.DCRC When PDB.CTRL.EOP.FLG is 1, this field indicates the CRC8 of data (contained in PDB.DATA units) corresponding to the packet referred by PDB.CTRL.EOP.FLG and PDB.CTRL.EOP.OFFSET. 8 0x00 to 0xFF PDB.CTRL.SOP.FLG Indicates a packet start in the next PDB.DATA block. Offset where the packet starts is indicated by PDB.CTRL.SOP.OFFSET. 1 0: No start of packet in the next PDB.DATA 1: Start of packet in the next PDB.DATA PDB.CTRL.SOP.OFFSET When PDB.CTRL.SOP.FLG is 1, this field indicates offset in number of bits to the first bit of the packet in the next PDB.DATA. PDB.TYPE is not counted. The value 0x40 indicates a packet start two PDB.DATA packets after the current PDB.CTRL. This allows for a more efficient back-to-back packet encapsulation, when PDB.CTRL.EOP.OFFSET of the previous packet takes value 0x3F. 7 0x00 to 0x40 ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 16 Symbol Description # of bits Valid values PDB.CTRL.PROTOCOL When PDB.CTRL.SOP.FLG is 1, this field indicates the encapsulated protocol identifier of the packet referred by PDB.CTRL.SOP.FLG and PDB.CTRL.SOP.OFFSET. 8 0x00: reserved for future extensions 0x01: Ethernet 0x02 to 0xFF: reserved for future extensions When both PDB.CTRL.SOP.FLG and PDB.CTRL.EOP.FLG are 0 this field identifies the type of special PDB.CTRL packet. 8 0x00: reserved for IDLE PDBs 0x01 to 0xFE: reserved for future extensions 0xFF: reserved for PAD PDBs PDB.CTRL.LEN.FLG When PDB.CTRL.SOP.FLG is 1, this field indicates that the length of encapsulated packet is known a priori, so the receiver can use it. The length is announced in PDB.CTRL.LEN.VAL. This information refers to the next data packet that will be encapsulated and indicated by PDB.CTRL.SOP.FLG and PDB.CTRL.SOP.OFFSET. 1 0: Encapsulated packet length is not indicated 1: Encapsulated packet length is announced PDB.CTRL.LEN.VAL When PDB.CTRL.SOP.FLG is 1, this field indicates the length of encapsulated packet in number of bits. This information refers to the packet referred by PDB.CTRL.SOP.FLG and PDB.CTRL.SOP.OFFSET. 17 0 to 131 071 Only valid if PDB.CTRL.LEN.FLG = 1 PDB.CTRL.PROTSPEC When PDB.CTRL.SOP.FLG is 1, protocol specific information. 7 0x00 to 0x7F: reserved for future extensions CCRC CRC8 of the current PDB.CTRL, from PDB.TYPE to PDB.CTRL.PROTSPEC 8 0x00 to 0xFF Total (bits) 65 The PDB.CTRL.EOP.FLAG and PDB.CTRL.EOP.OFFSET fields are used to signal the end of a data packet in the next PDB.DATA block. A PDB.CTRL shall always be inserted before the last PDB.DATA carrying data belonging to a data packet, to indicate where the data packet ends. If data of next packet is already available, it is possible to perform back- to-back packet encapsulation by indicating in the PDB.CTRL block where the next packet starts. For each data-packet being transmitted, a cyclic redundancy check is calculated and sent at the PDB.CTRL.DCRC field of the PDB.CTRL that signals the end of the packet. Similarly, the PDB.CTRL.SOP.FLAG and PDB.CTRL.SOP.OFFSET are used to signal the start of a packet in the next PDB.DATA block. The value 0x40 in PDB.CTRL.SOP.OFFSET indicates a packet start two PDB.DATA packets after the current PDB.CTRL. The PDB.CTRL.PROTOCOL is an identifier of the protocol to be encapsulated in the next PDB.DATA blocks representing a data packet. The PDB.CTRL as defined in table 1 is able to encapsulate several different protocols from different interfaces over a single POF link. Values of PDB.CTRL.PROTOCOL 0x00 and 0x02 to 0xFF as well as the field PDB.CTRL.PROTSPEC are reserved for future extensions. The PDB.CTRL.LEN.FLG and PDB.CTRL.LEN.VAL are used to convey the data packet length if it is known a priori. As it will be explained later on, the length information is useful for reducing the latency and buffering of de-encapsulation in the cases when the PHY data-rate is less than the data interface data-rate. Finally, the field PDB.CTRL.CCRC contains the CRC8 calculated for the current PDB.CTRL and allows validating the integrity of each PDB.CTRL block in de-encapsulation. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 17 Figure 7: Illustration of the data encapsulation scheme Additionally, a pointer PHD.TX.NEXT.PDB.OFFSET to the first PDB block that starts in every frame is included in the frame header. This pointer gives the position for the first bit of the first PDB that starts in the next frame. This information is intended to provide fast encapsulation alignment in the receiver. The overall encapsulation scheme is illustrated in the figure 7. The use of packet sizes less than 64 bits is also shown. In that case the PDB.DATA block following the PDB.CTRL block shall contain the whole packet and the rest of the bits shall be set to zero. Similarly, when a packet ends in the middle of a PDB.DATA block and no other packet follows, the rest of the block shall be set to zero. When there is no user data to transmit the PDB.IDLE block is transmitted continuously. The PDB.IDLE is a special case of PDB.CTRL where both PDB.CTRL.SOP and PDB.CTRL.EOP are 0 and PDB.CTRL.PROTOCOL = 0x00 as it is specified in table 2. Table 2: PDB.IDLE block definition used for data encapsulation Symbol Description # of bits Valid values PDB.TYPE Indicates the type of PDB (for control or user data) 1 1: The current PDB is PDB.CTRL PDB.CTRL.EOP.FLG (Described in table 1) 1 0: No end of packet in next PDB.DATA PDB.CTRL.EOP.OFFSET (Described in table 1) 6 0x00 PDB.CTRL.DCRC (Described in table 1) 8 0x00 PDB.CTRL.SOP.FLG (Described in table 1) 1 0: No start of packet in next PDB.DATA PDB.CTRL.SOP.OFFSET (Described in table 1) 7 0x00 PDB.CTRL.PROTOCOL (Described in table 1) 8 0x00 PDB.CTRL.LEN.FLG (Described in table 1) 1 0: Encapsulated packet length is not indicated PDB.CTRL.LEN.VAL (Described in table 1) 17 0 PDB.CTRL.PROTSPEC (Described in table 1) 7 0x00 CCRC CRC8 of PDB.CTRL including from PDB.TYPE to PDB.CTRL.PROTSPEC 8 0x87 Total (bits) 65 Another special PDB.CTRL is defined as PDB.PAD. PDB.PAD blocks shall be inserted by the transmitter between consecutive PDB.DATA blocks to carry out the rate matching between the data interface and PHY when PHY data-rate is greater than interface data-rate. The PDB.PAD is specified in table 3 as special case of PDB.CTRL block where both PDB.CTRL.SOP and PDB.CTRL.EOP are 0 and PDB.CTRL.PROTOCOL = 0xFF. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 18 Table 3: PDB.PAD block used for data encapsulation and rate matching Symbol Description # of bits Valid values PDB.TYPE Indicates the type of PDB (for control or user data) 1 1: The current PDB is PDB.CTRL PDB.CTRL.EOP.FLG (Described in table 1) 1 0: No end of packet in next PDB.DATA PDB.CTRL.EOP.OFFSET (Described in table 1) 6 0x00 PDB.CTRL.DCRC (Described in table 1) 8 0x00 PDB.CTRL.SOP.FLG (Described in table 1) 1 0: No start of packet in next PDB.DATA PDB.CTRL.SOP.OFFSET (Described in table 1) 7 0x00 PDB.CTRL.PROTOCOL (Described in table 1) 8 0xFF PDB.CTRL.LEN.FLG (Described in table 1) 1 0: Encapsulated packet length is not indicated PDB.CTRL.LEN.VAL (Described in table 1) 17 0 PDB.CTRL.PROTSPEC (Described in table 1) 7 0x00 CCRC CRC8 of PDB.CTRL including from PDB.TYPE to PDB.CTRL.PROTSPEC 8 0x90 Total (bits) 65 The user data received from the interface is encapsulated in PDB.DATA blocks. The PDB.DATA block has the PDB.TYPE bit set to 0 and it is specified in table 4. Table 4: PDB.DATA block used for data encapsulation Symbol Description # of bits Valid values PDB.TYPE Indicates the type of PDB (for control or user data) 1 0: The current PDB is PDB.DATA PDB.DATA.D0 First data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D1 Second data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D2 Third data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D3 Fourth data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D4 Fifth data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D5 Sixth data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D6 Seventh data octet of PDB.DATA 8 0x00 to 0xFF PDB.DATA.D7 Eighth data octet of PDB.DATA 8 0x00 to 0xFF Total (bits) 65 The encapsulation method defined allows that a data packet may start and/or end in any bit of the PDB.DATA.D[0..7] fields. Therefore, the packet length is not required to be multiple of 8 bits (octet), making possible bit aligned packets. However, it can be useful for other kind of interfaces where bit-alignment enables a reduction in data encapsulation latency. Decisions about when to insert PDB.PAD blocks as well as PDB.IDLE blocks are left to the implementer. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.3 DCRC | The DCRC cyclic redundancy parity check bits for each data packet are generated using the following cyclic generator polynomial. 1+ x + x 3 + x 4 + x 7 + x 8 The DCRC implementation shall produce the same result as the implementation shown in figure 8. In figure 8, there are eight delay elements: S0 to S7. They shall be initialized to zero. Afterwards the data packet is used as serial data input to compute the DCRC with the switch connected, which is setting DCRCgen in figure 8. After all the data packet bits have been processed, the switch is disconnected (setting DCRCout) and the eight values stored in the delay elements are transmitted in the order illustrated, i.e. first S7, followed by S6, and so on until the final value S0. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 19 Figure 8: DCRC reference implementation |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.4 CCRC | The CCRC cyclic redundancy parity check bits for PDB.CTRL are generated using the following cyclic generator polynomial. 1+ x + x 5 + x 6 + x 8 The CCRC implementation shall produce the same result as the implementation shown in figure 9. In figure 9 there are eight delay elements: S0 to S7. They shall be initialized to zero. Afterwards the PDB-CTRL block, from bit 0 (PDB.TYPE) to bit 56 (PDB.CTRL.PROTSPEC), is used as serial data input to compute the CCRC with the switch connected, which is setting CCRCgen. After all the PDB.CTRL bits have been processed, the switch is disconnected (setting CCRCout) and the eight values stored in the delay elements are transmitted in the order illustrated, i.e. first S7, followed by S6, and so on until the final value S0. Figure 9: CCRC reference implementation |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.5 Data packet encapsulation | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.5.1 Data packet transmit encapsulation | The physical layer device defined in the present document is able to optionally receive data packets from any generic data interface. Conditions in the PHY data interface Idle, Start, Terminate, Normal data transmission and Transmit Error propagation shall be considered by the PHY. The PHY shall propagate the Transmit Error by deliberately corrupting data or DCRC when data is encapsulated, as defined in clause 5.2.3.3. It is left to the implementer how to corrupt the data for error propagation, as long as the receiver is able to detect it by means of DCRC checking. The net physical rate is that obtained once the overheads caused by both header and pilots (160/8 224) as well as PDB.DATA encapsulation (1/65) are eliminated. The data packets may include information about its length. This information shall be included in the PDB.CTRL block that precedes the data packet. The PDB.CTRL.LEN.FLAG shall be set to 1 and the PDB.CTRL.LEN.VAL to the number of bits equivalent to the total number of bits of the data packet. Examples of data packets encapsulations are illustrated in figure 10 and figure 11. In figure 10, the encapsulation of a single frame is shown, while the figure 11 illustrates the encapsulation of back-to-back frames. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 20 Figure 10: Encapsulation of a single data packet Figure 11: Encapsulation of back-to-back data packets |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.5.2 Rate matching | 5.2.3.5.2.1 Introduction to rate matching As defined in successive clauses, the PHYs defined in the present document and its annexes optionally support adaptive bit rate, being possible to have a PHY data rate greater or lower than the data interface. The PHY data rate shall depend on channel conditions and physical layer parameters negotiated by both communication endpoints. In addition, the PHY data-rate in many MLCC configurations does not exactly match the data interface rate. The rate matching functionality, matches the PHY data rate with the rate at the data interface. Three different rate-matching cases are considered in the following subclauses. 5.2.3.5.2.2 Rate matching when PHY data rate is greater than data interface data rate It shall be solved by means of PDB.PAD blocks insertion between consecutive PDB.DATA blocks. Minimum buffers are required in the CMB transmit function to implement the 64/65 encapsulation defined in clause 5.2.3.2 and the MLCC encoding defined in clause 5.2.3.7. Algorithms for PDB.PAD insertion are left to the implementer. 5.2.3.5.2.3 Rate matching when PHY data rate is equal to data interface data rate Only PDB.IDLE insertion between data packets shall be needed, being data packet transmission done in consecutive PDB.DATA blocks. Algorithms for PDB.IDLE insertion are left to the implementer. 5.2.3.5.2.4 Rate matching when PHY data rate is less than data interface data rate A mechanism based on local false pause packets generation to stop the data interface transmission is defined in order to avoid the overflow of PHY buffers. Pause packets as special case of Control Packets. Pause Packets are defined for flow control between two sides of a data communication link. Pause Packets are local to a link, being not retransmitted by any external device. The data interface transmits data at a rate of 100 Mbit/s or 1 000 Mbit/s, which is buffered by the CMB before being transmitted onto the medium. The CMB transmit function shall generate a false Pause Packets to the external transmitter locally connected by using the CMB reception function. Therefore, the locally connected external transmitter shall receive this Pause Packet as if sent by the other side of communication link. Reception of a Pause Packet stops the external transmission during the time defined in Pause Time field in the Pause Packet. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 21 The Pause Packet content (Pause Time) shall be calculated by the CMB transmit function as function of CMB buffer space and the difference between the data interface data rate and actual PHY data rate, to avoid packet loss due to buffer overflow. A Pause Packet with Time = 0 may be generated and sent to the local transmitter to resume the transmission during a Pause period generated by a previous Pause Packet. The Flow control algorithms and the values of the Pause Time should be selected to minimize frame transmission latency and ensure that the link can be fully utilized. Flow control algorithms using pause frames are left to the implementer. The CMB receive function shall intercept the Pause frames received from the other side of the link, being Pause Time value overwritten when the actual value is less than the one currently calculated by CMB transmit function. In links where the PHY rate is not symmetric, being the PHY rate greater than or equal to the data interface rate in one direction and less than the data interface rate in the other direction, the transmitting end on the slower direction shall set a maximum data rate limit on the data interface, in order to allow the receiving end introducing the Pause Packets required for flow control. The data interface rate limit shall be selected to avoid losing any frame in the slower direction in a worst-case scenario with maximum Pause Packet rate. The maximum Pause Packet rate mainly depends on the PHY rate on the slower direction and the maximum data packet length of the data interface. Algorithms needed to perform the data interface rate limitation are left to the implementer. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.6 Binary Scrambler | The incoming data after encapsulation is scrambled using a Maximum Length Sequence (MLS) generator defined by the following polynomial 25 22 1 x x + + . The implementation shall produce the same result as the implementation in figure 12. The scrambler shall be initialized to 0x17C_9C58 (given in hexadecimal base representation) where the left most digit corresponds to the initial value of register 0. Figure 12: Binary scrambler reference implementation |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7 Multi-Level Cosset Coding | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.1 Introduction to Multi-Level Cosset Coding | The scrambled data is mapped to PAM symbols using the MLCC technique. The overall scheme is shown in figure 13. Depending on the configuration used by a particular PHY, the data bits are divided in up to three groups. The first group is coded with a (2 016, 1 664) BCH code. The second is coded with a (2 016, 1 994) or a (1 008, 986) BCH code depending on the configuration and the last group is not coded. The resulting bits are then mapped to PAM symbols using a number of processing steps as shown in figure 13. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 22 Figure 13: Multi-Level Cosset Coding block diagram The terms in figure 13 are defined as follows: a) NMLCC: length of the MLCC code word in 1D (PAM) symbols, i.e. 2 016. b) nb(i): nº of coded bits per dimension for the ith level; it defines constellation; i = 1..3. c) nc(i): nº of bits per code-word for the ith binary component code. d) kc(i): nº of information bits per code-word for the ith binary component code; kc(i) = nc(i) for i = 3. e) ξ: total number of coded bits per dimension: . f) kPAM: nº of bits per PAM constellation at the encoder output: . g) αMLCC: nº of information bits per MLCC code word. h) β(i): nº of information bits per MLCC code-word for ith level; β(i) = kc(i) for i = 1..2 and β(i) = nc(i) for i = 3. i) rc(i): code-rate for the ith level: . j) η: spectral efficiency per dimension: . k) Fs: symbol frequency (baud-rate). By design nb(1) = 1 and nb(2) = 0,5 or 1 bits/dim. The encoder shown in figure 13 can be configured to provide a number of data bits per symbol. The possible options are given in table 5. The selected option determines the number of levels of the PAM symbol to be sent. Each particular PHY type may use one or a number of those configurations. The parameters for each PHY type are defined in the corresponding annexes from A to D. ξ = nb(i) i=1 3 ∑ kPAM = ξ ⎡⎢⎤⎥ rc(i) = kc(i) / nc(i) η = nb(i)rc(i) i=1 3 ∑ ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 23 Table 5: Configurations for the Multi-Level Cosset Coding NMLCC (1D symbols) α (bits/cod e-word) β(1) (bits/code -word) β(2) (bits/code -word) β(3) (bits/code -word) η (bits/s/ Hz/D) M- PAM nb(1) (bits/1D) nb(2) (bits/1D) nb(3) (bits/1D) 2 016 1 664 1 664 0 0 0,825 4 2 1 0 0 2 016 2 650 1 664 986 0 1,314 5 4 1 0,5 0 2 016 3 658 1 664 1 994 0 1,814 5 4 1 1 0 2 016 4 666 1 664 1 994 1 008 2,314 5 8 1 1 0,5 2 016 5 674 1 664 1 994 2 016 2,814 5 8 1 1 1,0 2 016 6 682 1 664 1 994 3 024 3,314 5 16 1 1 1,5 2 016 7 690 1 664 1 994 4 032 3,814 5 16 1 1 2,0 2 016 8 698 1 664 1 994 5 040 4,314 5 32 1 1 2,5 2 016 9 706 1 664 1 994 6 048 4,814 5 32 1 1 3,0 2 016 10 714 1 664 1 994 7 056 5,314 5 64 1 1 3,5 2 016 11 722 1 664 1 994 8 064 5,814 5 64 1 1 4,0 |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.2 MLCC Demultiplexer | The MLCC encoder processes blocks of αMLCC bits. The size of the block depends on the particular configuration as shown in table 5. In the first step of processing those bits are divided into three MLCC levels. The number of bits assigned to each level are denoted as β(1), β(2) and β(3). Then for an input block x = [x0x1LxαMLCC−1] the sub-blocks assigned to each level are as follows: y1 = [x0x1Lxβ(1)−1], y2 =[xβ(1)xβ (1)+1Lxβ (1)+β(2)−1] and y3 =[xβ(1)+β(2)xβ(1)+β(2)+1LxαMLCC−1]. The sub-indexes also denote time ordering. The demultiplexing process is illustrated in figure 14. Figure 14: MLCC demultiplexing process |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.3 BCH Encoders | The sub-blocks y1 and y2 are encoded with BCH codes. For y1 the BCH encoding takes a 1 664 input block and shall generate a 2 016 bit code word c1. Prior to the BCH encoding 31 zeroes are added at the beginning of the input block. The resulting 1 695 bit block is then encoded. For both y1 and c1 the encoder shall follow the convention that the LSB (leftmost element of the vectors y1 and c1) is the first bit in time. The BCH code is specified by the coefficients of its generator polynomial, which are: 0x0001_E29B_5C67_999C_F994_D38A_6AFF_BF44_78C7_B5F1_8669_0A41_5AFD_FE3C_5497_E86F_B13E_F3 29_0634_9A49_61D2_D63A_14A3, being g(0) the rightmost bit. For y2 the BCH encoding takes either a 1 994 or 986 bits input block and shall generate a 2 016 or a 1 008 bits code word c2. For both y2 and c2 the encoder shall follow the convention that the LSB (leftmost element of the vectors y2 and c2) is the first bit to transmit. ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 24 Prior to the BCH encoding 31 zeroes are added at the beginning of the input block in the first case. In the second case, 1 039 zeroes are added. The resulting 2 025 bit block is then encoded. The BCH code is specified by the coefficients of its generator polynomial which are: 0x0049_05B1, being g(0) the rightmost bit. The BCH encoders shall produce the same result that the implementation in figure 15. All the elements Sx are initialized to zero. After the information bits block has been serially processed with the switch connected to BCHgen, the Sx bits shall be transmitted from Sp - 1 to S0 starting with Sp - 1, with switch unconnected (BCHCout). Figure 15: BCH reference encoder |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.4 Gray mapping | For each level, the nc (i) bits blocks are mapped to NMLCC / 2 = 1 008 two-dimensional symbols using a mapper. The mapper for the ith level (i = 1, 2 or 3) is defined in terms of the parameter kQAM (i) = 2 nb (i), where nb (i) is defined as the number of coded bits mapped per dimension. When kQAM is greater than one, the mapping shall be performed as illustrated in figure 16. The input bit stream is demultiplexed into two substreams. One of the substreams maps onto the In-phase (I) component of the two-dimensional constellation and the other substream maps onto the quadrature (Q) component of the constellation. The In-phase component corresponds to the real part of a complex symbol and the Quadrature part corresponds to the imaginary part of a complex symbol. The consecutive input bits in din are assigned to the respective components in accordance with the configuration of kQAM. The demultiplexer A is controlled by the least significant bit of a free counter B counting from 0 to kQAM-1 clocked at the same input bit rate. If kQAM is even, the same number of bits is assigned to each component. If it is odd, the In-phase component receives more bits that the Quadrature component. Thus, the number of bits per dimension assigned to each component is and wherein ⎡⎤. denotes rounding up and ⎣⎦. denotes rounding down. In the two substreams, the bits are then converted from serial to parallel (S/P) to symbols with kI and kQ bits in the In-phase and Quadrature component, respectively. The most right bit is the most significant bit. kI = kQAM ⎡⎢ ⎤⎥ kQ = kQAM ⎢⎣ ⎥⎦ ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 25 Figure 16: Gray mapper block diagram for kQAM > 1 After the serial to parallel conversion a Gray-to-Binary converter (G2B) is applied. The converter transforms an input vector g of k bits into an output vector b also of k bits by performing the following operations: where . The vectors obtained in the G2B conversion are then processed as shown in Figure 17. The vectors are considered integers and both components are multiplied by 2. The least significant bit b0 output from the G2B in the In-phase component is used to control the multiplexer C, which sets 1 or -1 to the input of the last adder. Finally, the last multiplexer D outputs symbols to the Quadrature branch. For constellations where , the arithmetic operations carried out on both branches (In-phase and Quadrature) are the same. For , the quadrature component is transformed to generate a rotated pseudo-Gray mapped QAM constellation, required to map an odd number of bits per two dimensions. When kQAM is one the mapping is implemented as shown in figure 17. As it can be seen in this configuration the components SI and SQ take the same value. Figure 17: Gray mapper block diagram for kQAM = 1 5.2.3.7.5 First Lattice transformation The symbol SI and the symbol SQ are transformed by a lattice transformation to carry out, together with the next addition operation, the so-called cosset partitioning. For this purpose, I and Q components are considered as the real and imaginary parts of a complex number S. b[k −1]= g[k −1] b[k −1−j]= g[k −1−j] xor b[k −j] j ∈1,k −1 [ ] kI = kQ kI > kQ Λ1 t(l)(x) ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 26 Then at each level l the transformation is applied to S(l) to obtain L(l) as: L(l) = 1 2 × S(l)+(1+ j)×(2 nb (l) ⎡⎢ ⎤⎥−1) ( )×2 nb (i) ⎡⎢ ⎤⎥ i=1 l−1 ∑ × 1+ j 2 ⎛ ⎝⎜ ⎞ ⎠⎟ rem(2×nb (l),2) Where and rem denotes remainder after integer division. In particular, in the above formula, rem is the remainder of division of the first operand (i.e. 2nb(l)) by the second operand (i.e. 2). The entire transformation is composed of three sub-operations: a) The lattice is translated to allow the constellation to be contained within the first two-dimensional quadrants. b) The lattice is scaled to enable the cosset partitioning by vector addition with the constellation of the other levels. c) The lattice is rotated by 45 degrees before the vector addition for constellations with an odd number of bits per two dimensions. The translation, denoted here as , is defined for each x ∈ ℂ (x is a complex number), wherein and l denotes level of the MLCC, as: Λ1,1 t (l)(x) = 1 2 x + 1+ j ( )× 2 nb(l) ⎡⎢ ⎤⎥−1 ( ) ( ). Scaling and rotation are grouped into a single sub-operation denoted and defined for each x ∈ ℂ as: Λ1,2 t (l)(x) = x × 2 nb (l) ⎡⎢ ⎤⎥ i=1 l−1 ∑ × 1+ j 2 ⎛ ⎝⎜ ⎞ ⎠⎟ rem 2×nb (l),2 ( ) , where the operation rem denotes the remainder after an integer division. The complete lattice transformation including translation, scaling and rotation is defined as: . The lattice transformation for the first level does not include scaling and rotation since =1 bit/dim. The corresponding lattice transformation architecture is shown in figure 18. Figure 18: First Lattice transformation for the first MLCC level The input and output signals for each component branch are considered integer numbers and arithmetic operations are defined with natural bus width increase. The output of the mapper, symbol SI and symbol SQ are the input to the lattice transformation. L(l) = Λ1 t(l) S(l) ( ) 1 − = j ) ( 1,1 l tΛ 1 − = j ) ( 2 ,1 l t Λ ) ( 1 l tΛ ( )) )( ( ) ( ) )( ( 1,1 2 ,1 1 x l l x l t t t Λ Λ = Λ )1( bn ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 27 For the second level, two different cases are distinguished. For = 1 bit/dim, rotation is not performed. For = 0,5 bit/dim rotation is required since the corresponding 2D constellation maps one bit per two dimensions (odd number). The second level lattice transformation architecture is illustrated in figure 19. As it can be seen from the figure 19, the value of controls the multiplexers whether or not to perform the rotation. Figure 19: First Lattice transformation for the second MLCC level The lattice transformation for the third level is shown in figure 20. Rotation is implemented for the following values of : 0,5 bits/dim, 1,5 bits/dim, 2,5 bits/dim and 3,5 bits/dim. For = 1 bits/dim, 2 bits/dim, 3 bits/dim and 4 bits/dim the rotation is disabled. Figure 20: First Lattice transformation for the third MLCC level |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.6 Lattice addition | After performing the first lattice transformations for each active level, the lattice transformed symbols from each of the three levels are added, performing the cosset partitioning over lattice Z2 and the final partitioning. In particular, the in- phase and the quadrature components from the three levels are added separately to generate a respective new in-phase component and quadrature component as illustrated in figure 21. ) 2 ( bn ) 2 ( bn ) 2 ( bn )3 ( bn )3 ( bn a IS a Q S ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 28 Figure 21: Lattice addition for cosset partitioning The outputs of the lattice transformations for each level are finally added to obtain a complex number SIa + j·SQa. 5.2.3.7.7 Second Lattice transformation The symbols with in-phase component and quadrature component output from the lattice adder are then further transformed in order to obtain the final zero-mean two-dimensional square constellation over Z2 or RZ2. The second step lattice transformation includes the following three steps: a) rotation by -45 degrees for =1,5 bits, 2,5 bits, 3,5 bits, 4,5 bits and 5,5 bits per dimension (where ); b) modulo operation which constraints the constellation symbols to a square region within the first 2D quadrant; c) centring and scaling. The transformation can be defined analytically as per the equation below where ξ is the total number of bits per dimension for PAM constellation generated by the MLCC encoder. ( ) ( ) ⎡⎤ ( ) ( ) ⎡⎤ ( ) ξ ξ ξ 2 1 1 2, 1 mod 2 ) ( 2 , 2 rem 2 − × + + − × × = Λ j j x x t ∀ x ∈ ℂ, 1 − = j In particular, the modulo operation is defined as mod(x,z) = x - n × z, where , and where z is an integer power of two, and x is real. Since , the modulo operation may be implemented by means of a logic "and" operation. This lattice transformation is illustrated in figure 22. As it can be seen in figure 22, the first part implements the rotation by -45 degrees as a function of the value of ξ . The modulo operation is applied afterwards to constraint the symbols to a square constellation in the first 2D quadrant. Then the scaling and centring of the constellation is performed, resulting in the final zero-mean square or rotated QAM constellation with the minimum distance of 2 or , respectively. The transformed symbol components and take odd values. Λ2 t (x) a IS a IS Λ2 t (x) ξ ξ = nb(i) i=1 3 ∑ ⎣ ⎦ z x n / = ⎡⎤ ξ 2 = z 2 2 ) ( 2 a I t S Λ ) ( 2 a Q t S Λ ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 29 Figure 22: Second Lattice transformation |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.8 Mapping to PAM symbols | The in-phase and the quadrature components ) ( 2 a I t S Λ and ) ( 2 a Q t S Λ of the 2D symbols output from the second-step lattice transformation are then time domain multiplexed resulting in a sequence of 1D symbols belonging to a ⎡⎤ ξ 2 - PAM constellation. The multiplexing operation is illustrated in figure 23. A free counter from 0 to 1 is clocked at the 1D symbol rate and controls the input of the multiplexer to take alternatively the in-phase and quadrature input symbols. The M-PAM Symbols belong to the set −M +1,−M + 3,L, M −3, M −1 { } , where M = 2 ξ ⎡⎢⎤⎥. Figure 23: Multiplexer for mapping to PAM symbols from MLCC encoded QAM symbols |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.3.7.9 Symbol scrambler | The PAM symbols are then scrambled to ensure that nonlinear distortion affects all PAM levels equally. Jointly with non-linear compensation that may be implemented by receiver, the symbol scrambler will provide the same symbol error probability for all the constellation points. The symbol scrambler is divided in two sub-blocks. The first one, illustrated in figure 24, is in charge of generating a pair of pseudo random signals (v and s) per PAM symbol from a binary MLS generator, with polynomial . The second one, illustrated in figure 25, operates these two signals over the input PAM symbols to generate the scrambled PAM symbols. 1+ x22 + x25 ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 30 Figure 24: Symbol scrambler: v and s signals generation Figure 25: PAM symbols scrambling The MLS generator is equal to that defined in figure 12 and is initialized to a known state at the beginning of the frame described in clause 5.2.1, with an initial state 0x0155_D559, where the left most digit corresponds to the initial value of register 0. The modulo operation reduces the scrambled symbols to the same Voronoi region of the Tomlinson- Harashima precoder defined in CMB transmit function (clause 5.2.7). As it can be seen in figures 24 and 25, the symbol scrambler is configured according to the MLCC encoder in terms of M-PAM. Therefore, in figure 24 and figure 25, as it was defined in clause 5.2.3.7. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4 Physical header encoding | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.1 Introduction to physical header encoding | The header bits carry control information for the CMB. Those bits are arranged in a block of 720 bits as described in clause 5.2.4.2. The block is then encoded using a BCH code to obtain a block of 896 bits that are mapped to 1 792 PAM symbols with two levels. Then the symbols are divided in 14 groups of 128 and 16 zero symbols are added at the beginning and end to obtain a sub-block of 160 symbols. The sub-blocks are transmitted at different points in the frame as specified in clause 5.2.2. The transmission scheme for the physical header is designed to provide a robust communication channel such that control information can be exchanged between both link ends under worst channel conditions. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.2 Physical header data (PHD) | The Physical header data is divided in fields that are defined in table 6. The field PHD.TX.CODING.LEN specifies the code-word length of the MLCC, given in number of M-PAM symbols per MLCC code word. This configuration cannot change dynamically once the PHY has initiated the CMB transmission. This information shall be decoded by the remote PHY to configure accordingly the MLCC decoding in CMB receive function. Only the setting of 2 016 is permitted for this field, although several bits are reserved for future extensions. k = ξ ⎡⎢⎤⎥ ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 31 The field PHD.TX.NEXT.CODING.SE specifies the MLCC configuration in terms of spectral efficiency that is used in the next frame. This enables a dynamic adaptation of the PHY rate to the channel conditions. In the same way PHD.RX.REQ.CODING.SE enables a receiver to request a particular MLCC configuration for the next frame. PHD.RX.REQ.CODING.SE = 0 indicates that no request is performed. A number of fields in the header are used for THP pre-coding. PHD.TX.NEXT.THP.SETID > 0 enables the use of THP in the next frame. When THP is enabled, PHD.TX.NEXT.THP.SETID specifies the set of coefficients that is used for the transmission of the next frame. PHD.RX.REQ.THP.SETID specifies a set of THP coefficients that the receiver requests the transmitter to use. The values of the requested coefficients are specified in PHD.RX.REQ.THP.COEF[0..8]. The THP coefficients are transmitted in order from the least significant bit of PHD.RX.REQ.THP.COEF[0] to the most significant bit of PHD.RX.REQ.THP.COEF[8]. The PHD.RX.REQ.THP.COEF[0..8] coefficients are real numbers in signed fix-point format of 12 bits width. Of these 12 bits, the 2 most significant bits are used to represent the sign and integer part, and the 10 least significant bits represent the decimal part. The THP coefficients can take values in the interval [-2, 2) with a precision of 9,7656 × 10-4. THP pre-coding is done per frame so that it may be possible to change the coefficients in each frame to adapt to channel conditions. PHD.TX.NEXT.PDB.OFFSET is a pointer to the first bit of the first PDB in the payload of the next frame. This information is intended to help the receiver in delimiting the PDBs in the frame payload. PHD.TX.FRAMEID and PHD.RX.LASTFRAMEID are used to provide a sequence number of both TX and RX frames, for debugging tasks. PHD.RX.STATUS indicates to the link partner the local CMB receive function is ready to provide reliable PAM symbols to the rest of the CMB receive function. PHD.CAP fields inform about the capacity of the PHY to support optional features. PHD.CAP.LPI informs that PHY is able to receive frames implementing Low Power Idles, so that the remote PHY can turn off the optical power during the payload sub-blocks to reduce energy consumption. PHD.CAP.ABR informs about the capability to make adaptive bit rate, both making requests for coding configuration to remote PHY and accepting requests from the remote PHY. PHD.DEVID fields are defined to identify the PHY. Identification procedure is undefined and unique identifiers have not been assigned. However, a number of bits for device identification are reserved for future extensions. PHD.DEVID.FLG indicates that the PHD carries device identification in the field PHD.DEVID.INFO. PHD.DEVID.INFO shall take value 0 when PHD.DEVID.FLG = 0. PHD.VENDOR fields are reserved in PHD to provide a low bit rate auxiliary communication channel to implement proprietary control tasks and signalling of the CMB between both link partners. PHD.VENDOR.FLG signals if vendor proprietary information is included in PHD.VENDOR.INFO field. The field PHD.VENDOR.INFO shall take a value with all the bits equal to 0 for PHD.VENDOR.FLG = 0. Otherwise, the encoding PHD.VENDOR.INFO is left to the implementer as well as the methods to decode and reliably distinguish the encoded information of other possible implementations. All the PHD fields are ordered from least to most significant bit and transmitted from top to bottom according to table 6. For PHD.CRC16 the bit ordering is specified in clause 5.2.4.3. Table 6: Physical Header Data (PHD) definition Symbol Description # of bits Valid values PHD.TX.FRAMEID Current TX frame counter 8 0 to 255 PHD.TX.CODING.LEN MLCC code-word length, given in M-PAM symbols. 3 0x00: 2 016 symbols / CW 0x01 to 0x07: reserved for future use PHD.TX.NEXT.CODING.SE Next frame MLCC spectral efficiency configuration (in number of coded bits per dimension) 4 0: reserved 1: 1,0 2: 1,5 3: 2,0 4: 2,5 5: 3,0 6: 3,5 7: 4,0 8: 4,5 9: 5,0 ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 32 Symbol Description # of bits Valid values 10: 5,5 11: 6,0 12 to 15: reserved for future use PHD.TX.NEXT.THP.SETID THP coefficients set Id that will be used in the next frame 2 0: the next frame is not TH precoded: 1 to 3 PHD.TX.NEXT.PDB.OFFSET Offset of the first PDB in Payload of the next frame 7 0x00 to 0x40 PHD.RX.LASTFRAMEID Last frame counter received in return channel before current TX frame 8 0 to 255 PHD.RX.REQ.CODING.SE Requested MLCC configuration (in number of coded bits per dimension) by RX based on quality measurements 4 0: request for changing the MLCC configuration is not performed 1: 1,0 2: 1,5 3: 2,0 4: 2,5 5: 3,0 6: 3,5 7: 4,0 8: 4,5 9: 5,0 10: 5,5 11: 6,0 12 to 15: reserved for future extensions PHD.RX.REQ.THP.SETID Requested THP coefficients set Id 2 0: no request for changing the THP coefficients is performed: 1 to 3 PHD.RX.REQ.THP.COEF[0..8 ] Requested THP coefficients set when PHD.RX.REQ.THP.SETID is not equal to 0. 9 b(k) coefficients of 12 bits 108 Each b(k) is formatted (12, 2) Ordered from b(0) to b(8) PHD.RX.STATUS Indicates that local CMB receive function is able to make the reception of PAM symbols with reliability. This corresponds to the content of variable loc_rcvr_status. The CMB receive function shall use this PHD field to determine the rem_rcvr_status. 1 0: NOT_OK 1: OK PHD.CAP.LPI Signals the capacity of the PHY to support the reception of Low Power Idles during the payload sub-blocks 3 0: LPI is not supported 1: LPI is supported 2 to 7: reserved PHD.CAP.ABR Signals the capacity of PHY to implement Adaptive Bit Rate (ABR), so that the PHY is able to request and accept adaptive MLCC configuration 2 0: ABR is not supported 1: ABR is supported 2 to 3: reserved PHD.DEVID.FLG Indicates the PHD carries device identifier information encoded in PHD.DEVID.INFO 1 0 1: reserved for future extensions PHD.DEVID.INFO Device identifier The identification procedure is left undefined, and this field is reserved for future extensions 48 0 1 to 248 - 1: reserved for future extensions Reserved bits for future extensions. These bits shall be set to 0. 128 0 1 to 2128 - 1: reserved for future extensions PHD.VENDOR.FLG Indicates the PHD carries vendor proprietary information encoded in PHD.VENDOR.INFO 1 0: no vendor information is included 1: PHD carries vendor proprietary information PHD.VENDOR.INFO Vendor proprietary information used for application specific implementations and extensions. In case of PHD.VENDOR.FLG = 0, this field shall take the value zero for all the bits. 374 0 to 2373 - 1 PHD.CRC16 Cyclic redundancy code of 16 bits. Specified in clause 5.2.4.3 16 0x0000 to 0xFFFF Total (bits) 720 ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 33 |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.3 Physical Header CRC16 | The header is protected with a CRC16 cyclic redundancy parity check code. The CRC16 is described in figure 26. The 16 CRC bits are sent at the end of the 720 bits PHD block. The CRC16 shall be generated using the following generator polynomial: . The implementation shall produce the same result as that in figure 26. The first 704 PHD bits are used to compute the CRC16 with the switch connected (CRCgen setting). The 16 delay elements S0 to S15, shall be initialized to 0. After the 704 bits have been serially processed, the switch is disconnected (CRCout setting) and the 16 stored values (S0 to S15) are the CRC16. CRC16 is transmitted in order from S15 to S0. Figure 26: Physical Header CRC |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.4 Physical Header scrambler | The header block is scrambled prior to transmission. The original bits are XORed with a pseudorandom sequence; this sequence shall be generated using a LFSR with polynomial: (MLS generator). The LFSR is initialized to a value of 0x0068_D332 at the beginning of the frame, where the left most digit corresponds to the initial value of register 0. The header bits are then scrambled prior to transmission. The implementation of the scrambler shall produce the same results as that shown in figure 27. Figure 27: Physical Header scrambler reference block diagram |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.5 Physical Header BCH encoding | A (896,720) BCH code is used to encode the header. The code is described by the generator polynomial G(x): 0x0001_A3E8_171D_BCA4_EE1E_7CDC_A7DA_FB8D_8F39_8072_8516_6007, being g(0) the rightmost bit. To obtain the parity bits, 1 151 zero bits are prepended to the 720 bits prior to the BCH encoding. The BCH encoder shall produce the same result that the implementation of figure 15. All the elements Sx are initialized to zero before encoding. After the 1 871 bits block has been serially processed with switch connect to BCHgen, the Sx bits shall be transmitted from Sp - 1 to S0 starting with Sp - 1, with switch unconnected (BCHCout). 1+ x2 + x5 + x6 + x8 + x10 + x11 + x12 + x13 + x16 1+ x22 + x25 ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 34 |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.6 Physical Header mapping to PAM symbols | The incoming 896 bits are mapped into 1 792 2-PAM symbols. The mapping of BCH encoded bits in 2-PAM symbols based on a two-dimensional BPSK constellation is illustrated in figure 28. Figure 28: Physical Header PAM mapping |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.4.7 Physical Header Subframes (PHS) | The 1 792 symbols block is divided in 14 sub-blocks of 128 symbols each, denoted as Physical Header Subframe (PHS). Prior to transmission, 16 zero symbols are added at the beginning and the end of the PHS as it is illustrated in figure 29. Consecutive PHS blocks extended with zeroes are transmitted at the corresponding locations of the frame as defined in clause 5.2.2. Figure 29: Physical Header Subframe (PHS) with zeroes insertion |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.5 Physical pilots encoding | |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.5.1 Introduction to physical pilots | The pilot signals S1 and S2 carry information to aid the receiver initialization and continuous tracking. The S1 pilot signal is transmitted at the beginning of each frame as shown in figure 3 and is designed to facilitate frame and symbol synchronization. The S2 pilot signal is transmitted in sub-blocks that are distributed over the frame as shown in figure 3. The S2 pilot is designed to facilitate channel estimation and equalization by the receiver as well as continuous clock recovery. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.5.2 S1 pilot symbols generation | The S1 pilot signal is composed of 128 two level PAM symbols that are transmitted at the beginning of each frame. These symbols are generated after mapping a 128 bits sequence generated using a Linear Feedback Shift Register (LFSR). ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 35 The generator polynomial is . The implementation shall produce the same result as the implementation illustrated in figure 12. The register shall be initialized with a value of 0x00AC_2B4B at the beginning of each frame, where the left most digit corresponds to the initial value of register 0. The bits generated by the LFSR are then mapped to 2 level PAM symbols using the scheme in figure 30. The output symbols belong to the set {-1, 1}. Figure 30: S1 pilot symbols generation The S1 pilot starts and ends with a sequence of zero symbols as shown in figure 31. Each sequence of zero symbols is composed of 16 symbols. Figure 31: S1 pilot zeroes insertion |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.5.3 S2 pilot symbols generation | The S2 pilot signal is composed of 1 664 symbols that are transmitted in 13 sub-blocks of 128 symbols each. The bits are generated using a Linear Feedback Shift Register (LFSR) and mapped to PAM symbols with 256 levels. A sequence of zero symbols is inserted at the beginning and end of each S2 pilot sub-block. The generator polynomial is . The implementation shall produce the same result as the implementation illustrated in figure 12. The register shall be initialized with a value of 0x00AC_2B4B at the beginning of each frame, where the left most digit corresponds to the initial value of the register 0. The bits generated by the LFSR are then mapped to 256 level PAM symbols using the scheme in figure 32. After LFSR generation, the bits are converted from serial to parallel (S/P) to symbols with 8 bits. The right most bit is the most significant bit. Figure 32: S2 pilot symbols generation After PAM mapping, the S2 pilot is divided in 13 sub-blocks of 128 symbols each. Each S2 pilot sub-block starts and ends with a sequence of zero symbols as shown in figure 33. Each sequence of zero symbols is composed of 16 symbols. Figure 33: S2 pilot sub-blocks zeroes insertion |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.6 Power scaling | Prior to transmission, the signal is scaled to ensure that the OMA is approximately the same across the entire frame. Power scaling for payload PAM symbols is implemented as illustrated in figure 34. 1+ x22 + x25 1+ x22 + x25 ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 36 Figure 34: Power scaling for PAM payload symbols The scaling factor SF(k) depends on the number of PAM levels used and on whether THP is active or not. The factors for different configurations of the payload data MLCC encoding are shown in table 7. Table 7: Scaling factor configurations for payload PAM symbols M-PAM SF(k) THP enabled SF(k) THP disabled 1 2 128 255 2 4 64 85 3 8 32 36 4 16 16 17 5 32 8 8 6 64 4 4 The scaling factor for Physical Header sub-blocks is SFH = 255, since they are modulated with 2-PAM. For S1 pilot the scaling factor is SFS1 = 255 as well. For S2 sub-blocks the scaling factor is SFS2 = 1, since 256-PAM symbols are used. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.2.7 Tomlinson-Harashima Precoding (THP) | The PAM symbols to be transmitted, corresponding to the payload data of a frame, are precoded using THP as shown in figure 35. The coefficients b(i) are transmitted from the remote device in the Physical Header Data (PHD) of a previous frame as described in clause 5.2.4. The coefficient b(i) used for precoding corresponds to PHD.RX.REQ.THP.COEF[i] transmitted by the remote PHY. At the beginning of each payload sub-block (i.e. after either S1, S2 or PHS sub-blocks are transmitted) the state of feedback filter b(i) shall be reset (i.e. assuming all the previous symbols entering the TH precoder are zero). The zero symbols at the beginning and at the end of each S1, S2 and PHS sub-block make possible the TH precoding of payload symbols without inter-symbol interference in reception. Figure 35: Tomlinson-Harashima precoding, functional block diagram The precoder is defined by the following mathematical equations: , , , ξ ⎡⎢⎤⎥ v(m) = b(i)y(m −i −1) i=0 Nb−1 ∑ u(m) = x(m)−v(m) y(m) = mod u(m)+ M ( ),2M ( ) −M ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 37 where and produces symbols that are distributed in the region [-M, M) and where denotes the rounding down to an integer of a real number. , where ξ is defined in clause 5.2.3.7. When the PHY powers on and while PHD.RX.REQ.THP request information is not received, all the coefficients b(i) shall be set to zero. The precoding is disabled when all b(i) are set to zero. |
65f6ec82a1f2dba7e17c26a7e3a90b4f | 105 175-1-2 | 5.3 CMB receive function | The CMB receive function shall map incoming PAM symbols from the EO interface. The CMB receive function shall indicate to the CMB the type of received PAM symbol by means of the CMB_DATATYPE.indication message. For CMB_DATATYPE.indication(PAYLOAD), the CMB receive function shall perform the symbol level descrambling, the MLCC decoding to correct the errors that channel impairments may produce to the communication signal and the binary descrambling. After this, the PDB.CTRL and PDB.DATA blocks shall be used to extract the frames from the received bits. Finally, the recovered data shall be de-encapsulated and sent out via the data interface. A number of error situations can occur during the de-encapsulation. The CMB receive implementation shall check the CCRC for PDB.CTRL blocks and the DCRC field associated to data packets to detect errors. In case of error, the error can be signalled to the data interface. The implementation shall not send an erroneous data packet without signalling the error. As an example, the following error situations are discussed: a) An error in a PDB.DATA affecting a bit other than PDB.TYPE. b) An error in a PDB.DATA affecting PDB.TYPE. c) An error in a PDB.CTRL affecting a bit other than PDB.TYPE. d) An error in a PDB.CTRL affecting PDB.TYPE. An error in a PDB.DATA that affects a bit other than PDB.TYPE is detected when checking the DCRC associated with the data packet. When the error affects the PDB.TYPE bit, the error is detected when checking the CCRC field as the block will be interpreted as a control block due to the error. When the error in a PDB.CTRL affects a bit other than PDB.TYPE it is detected when checking the CCRC. Finally, an error in the PDB.TYPE bit of a control frame causes it to be interpreted as a PDB.DATA block. The error is apparent to the CMB receive function if it occurs when no frame is being received as a data PDB shall be preceded by the corresponding PDB.CTRL. If it occurs in a PDB.CTRL block that is in the middle of back-to-back data packets (as illustrated in figure 12) then both data packets appear as one to the CMB receive function. The error is detected when checking the DCRC of the frame, also an error is detected if the frame length is checked by the CMB receive function. In any case a frame which data or associated control blocks are in error are considered erroneous. On the other hand, for CMB_DATATYPE.indication(HEADER) the CMB receive function shall perform the physical header decoding enabling the transfer of CMB parameters between both link partners. Finally, for CMB_DATATYPE.indication(PAYLOAD_OFF) message, the CMB receive function may disable the decoding circuits that are not used in order to reduce the energy consumption. The CMB Receive function also comprises a receiver for pulse-amplitude modulated signals. It is able to both detect symbol sequences from the signal received from the EO. The signals received from the EO are described mathematically in clause 5.7.3. mod(y, x) = y −x y x ⎢ ⎣⎢ ⎥ ⎦⎥ ·⎢⎣⎥⎦ M = 2 ξ ⎡⎢⎤⎥ ETSI ETSI TS 105 175-1-2 V1.1.1 (2015-04) 38 When both link ends have signalled support for the LPI mode, the CMB receive function is also in charge of sensing the rx_signal from EO to determine the use of the Low Power Idle mode in payload sub-blocks, indicating to the CMB the proper data type by means of CMB_DATATYPE.indication(PAYLOAD_OFF) message. When this condition is detected, the CMB shall generate the EO_RXPWR.request message to the EO taking into account the implementation dependent delays of sleep and wake times of the EO receive implementation. The CMB may also disable the unused demodulation circuits to reduce the energy consumption. After BCH decoding and block alignment at the CMB receive function, the quality of the PAM symbols already equalized shall allow a PDB block error rate (PDB-ER, which is measured for the PDB.CTRL blocks) of less than 6,5 × 10-9 over a channel that meets the channel specifications and the EO receiver optical specifications provided in clause 7 and the respective annexes form annex A to D. The PDB-ER can be measured by checking the CCRC of the received PDB.CTRL blocks. For a PHY providing a speed of 1 000 Mbit/s with a transmit symbol rate of 312,5 Msymb/s, the PDB-ER shall be less than 6,5 × 10-9 if the CMB receive function collects less than 100 erroneous PDB.CTRL blocks during 17 minutes, assuming LPI mode is disabled and no PDB.DATA blocks are transmitted. In this scenario, all the PDB.CTRL blocks shall be PDB.IDLE (see clause 5.2.3.2). For PDB.DATA blocks, the data packet Error Rate (FER) shall be less than L × 10-10 where L is the frame length in bits. The FER can be measured by checking the DCRC associated with the data packet. When frames of different lengths are transmitted, the average frame length can be used for the estimation of the FER. To achieve the indicated performance, it is highly recommended that the CMB receive sub-clause includes the functions of signal equalization, both linear and non-linear (see clause 5.7.3 for signals received from EO). |
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