text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>T_SOURCE \
DT_PROP(NXP_KINETIS_SIM_NODE, clkout_source)
#endif
#if DT_NODE_HAS_PROP(NXP_KINETIS_SIM_NODE, clkout_divider)
#define NXP_KINETIS_SIM_CLKOUT_DIVIDER \
DT_PROP(NXP_KINETIS_SIM_NODE, clkout_divider)
#endif
static int mcux_sim_init(const struct device *dev)
{
#ifdef NXP_KINETIS_SIM_CLKOUT_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IG_SOC_FAMILY_MCXA */
break;
#endif
#ifdef CONFIG_PTP_CLOCK_NXP_ENET_QOS
case MCUX_ENET_QOS_PTP_CLK:
*rate = CLOCK_GetEnetPtpRefClkFreq();
break;
#endif
#ifdef CONFIG_ETH_NXP_ENET
case MCUX_ENET_CLK:
#ifdef CONFIG_SOC_SERIES_RW6XX
*rate = CLOCK_GetTddrMciEnetClkFreq();
#endif
break;
#endif
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Texas Instruments
* Copyright (c) 2025 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
#include <ti/driverlib/driverlib.h>
#include <string.h>
#define MSPM0_ULPCLK_DIV... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcm_pcc
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/npcm_clock.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_pcc
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/npcx_clock.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016-2020 Nordic Semiconductor ASA
* Copyright (c) 2016 Vinayak Kariappa Chettimada
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <zephyr/sys/onoff.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include "clock_control_nrf2_common.h"
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF2_COMMON_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF2_COMMON_H_
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> struct onoff_transitions transitions = {
.start = onoff_start_hfxo,
.stop = onoff_stop_hfxo
};
uint32_t start_up_time;
int rc;
rc = onoff_manager_init(&dev_data->mgr, &transitions);
if (rc < 0) {
return rc;
}
start_up_time = nrf_bicr_hfxo_startup_time_us_get(BICR);
if (start_up_time == NR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_auxpll
#include <errno.h>
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>us = FLL16M_OPEN_LOOP_STARTUP_TIME_US;
return 0;
case FLL16M_MODE_BYPASS:
*startup_time_us = dev_data->bypass_startup_time_us;
return 0;
default:
break;
}
return -EINVAL;
}
static struct onoff_manager *fll16m_get_mgr_by_idx(const struct device *dev, uint8_t idx)
{
struct fll16m_dev_data *... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_hsfll_global
#include "clock_control_nrf2_common.h"
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <nrfs_gdfs.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ister_freq_setting_applied_callback(
freq_setting_applied_cb);
#endif
return 0;
}
static DEVICE_API(nrf_clock_control, hsfll_drv_api) = {
.std_api = {
.on = api_nosys_on_off,
.off = api_nosys_on_off,
},
.request = api_request_hsfll,
.release = api_release_hsfll,
.cancel_or_release = api_canc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_iron_hsfll_local
#include "clock_control_nrf2_common.h"
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/logging/log.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>a->max_accuracy;
clock_option->precision = 1;
clock_option->src = NRFS_CLOCK_SRC_LFCLK_XO_PIERCE_HP;
dev_data->clock_options_cnt++;
break;
case NRF_BICR_LFOSC_MODE_EXTSINE:
clock_option = &clock_options[dev_data->clock_options_cnt];
clock_option->accuracy = dev_data->max_accuracy;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrfs_audiopll
#include "clock_control_nrf2_common.h"
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/clock/nrfs-audiopll.h>
#include <zephyr/drivers/clock_control/nrf_clo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_numaker_scc
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/logging/log.h>
#include <NuMicro.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>"Failed to get LIRC stable");
}
}
if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hxt))) {
ret = numicro_scc_start_clock_source(config, CLK_PWRCTL_HXTEN_Pos,
CLK_STATUS_HXTSTB_Pos);
if (ret < 0) {
LOG_WRN("Failed to get HXT stable");
}
}
if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(cl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025, 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_mc_cgm
#include <errno.h>
#include <zephyr/drivers/clock_control/nxp_clock_controller_sources.h>
#include <zephyr/dt-bindings/clock/nxp_mc_cgm.h>
#include <zephyr/sys/util.h>
#include <fsl_clock.h>
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/dt-bindings/clock/nxp_mcxw7x_clock.h>
#include <fsl_clock.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>bleModuleClock(clock_name);
return 0;
}
static int nxp_s32_clock_get_rate(const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
ret... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Andriy Gelman <andriy.gelman@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT pwm_clock
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pwm.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
rcar_cpg_build_clock_relationship(dev);
rcar_cpg_update_all_in_out_freq(dev);
return 0;
}
static DEVICE_API(clock_control, r8a7795_cpg_mssr_api) = {
.on = r8a7795_cpg_mssr_start,
.off = r8a7795_cpg_mssr_stop,
.get_rate = rcar_cpg_get_rate,
.set_rate = r... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>A779F0_CLK_SD0_DIV_MASK) + 1));
default:
return RCAR_CPG_NONE;
}
}
static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask)
{
switch (module) {
case CLK_SDSRC:
/* divider has to be in range 4-6 */
if (*divider > 3 && *divider < 7) {
/* we can write to regis... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 EPAM Systems
* Copyright (c) 2023 IoT.bzh
* Copyright (c) 2025 Renesas Electronics Corporati<|fim_suffix|>divider) || *divider > 16) {
return -EINVAL;
}
/* 1,2,4,8,16 have to be converted to 0,1,2,3,4 and then shifted */
*divider = (find_lsb_set(*divider) - 1) << R8A779... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020-2022 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include "clock_control_rene... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022-2023 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
#define ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
#include <zephyr/spinlock.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lk_src_rate;
uint32_t clk_div_val;
if (!rate) {
return -EINVAL;
}
clk_src_rate = R_BSP_SourceClockHzGet(config->clk_src);
clk_div_val = config->clk_div;
*rate = clk_src_rate / clk_div_val;
return 0;
}
static DEVICE_API(clock_control, clock_control_renesas_ra_api) = {
.on = clock_control_renes... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier<|fim_suffix|> clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
ARG_UNUSED(sys);
return -ENOTSUP;
}
static int clock_control_renesas_ra_subclk_get_rate(const struct device *dev,
clock_control_subsys_t sys, u... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rx_cgc_pclk
#include <string.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/dt-bindings/clock/rx_clock.<|fim_suff... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rx_cgc_pll
#include <string.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/renesas_rx_cgc.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rx_cgc_root_clock
#include <string.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/renesas_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/renesas_rztn_clock.h>
#include <zephyr/kernel.h>
#include "bsp_api.h"
#define DT_DRV_COMPAT renesas_rz_cgc
static int clock_control_renes... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ase RZ_IP_DMAC:
R_BSP_MODULE_START(FSP_IP_DMAC_NS, ch);
break;
#endif
default:
return -EINVAL; /* Invalid FSP IP Module */
}
return 0;
}
static int clock_control_renesas_rz_off(const struct device *dev, clock_control_subsys_t sys)
{
if (!dev || !sys) {
return -EINVAL;
}
uint32_t *clock_id... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rate)
{
int ret;
enum rza2m_cp_sub_clock clock_name = (enum rza2m_cp_sub_clock)sys;
uint32_t clock_rate = (uint32_t)rate;
ret = rza2m_cpg_set_sub_clock_divider(dev, clock_name, clock_rate);
return ret;
}
static int clock_control_renesas_rza2m_init(const struct device *dev)
{
const struct rza2m_cp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rn 0;
}
static int rza2m_cpg_modify_frqcr(const struct device *dev, enum rza2m_cp_sub_clock clk_sub_src,
uint32_t sub_clk_frequency_hz, uint16_t *p_frqcr)
{
struct rza2m_cpg_clock_data *data = dev->data;
uint16_t div_d;
uint16_t fc;
/* Avoid divide by zero */
if (sub_clk_frequency_hz == 0) {
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_STBCR9_MSTP96 0x40UL
#define CPG_STBCR9_MSTP97 0x80UL
#define CPG_STBCR10_MSTP100 0x01UL
#define CPG_STBCR10_MSTP101 0x02UL
#define CPG_STBCR10_MSTP102 0x04UL
#define CPG_STBCR10_MSTP103 0x08UL
#define CPG_STBCR10_MSTP104 0x10UL
#define CPG_STBCR10_MSTP107 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andrei-Edward Popa
* Copyright (c) 2023 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT raspberrypi_pico_clock_controller
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#if defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>uct device *dev, const struct clk_rlx *clk, uint32_t rate)
{
struct rts_fp_clock_data *data = dev->data;
uint32_t divider;
uint32_t reg;
k_spinlock_key_t key;
if (clk->ops->get_rate(dev, clk) == rate) {
return 0;
}
reg = rts_fp_clk_read_reg(dev, clk->clkreg);
switch (rate) {
case MHZ(240):
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek Semiconductor, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_RTS5817_CONTROL_REG_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_RTS5817_CONTROL_REG_H_
#define R_SYS_CLK_CHANGE 0x00
#define R_SYS_BUS_CLK_CFG_REG 0x04
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek Semiconductor, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_RTS5817_GPLL_REG_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_RTS5817_GPLL_REG_H_
#define R_SYSPLL_CFG 0x0
#define R_SYSPLL_NF_CODE 0x4
#define R_SYSPLL_CTL 0x8
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> LOG_ERR("Unknown peripheral group #%d", clk_grp);
return -EINVAL;
}
*rate = freq;
return 0;
}
static DEVICE_API(clock_control, rts5912_clock_control_api) = {
.on = rts5912_clock_control_on,
.off = rts5912_clock_control_off,
.get_rate = rts5912_clock_control_get_rate,
};
static int rts5912_clo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Foundries.io
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_pcc
#include <errno.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <fsl_clock.h>
#define LOG_<|fim_suffix|> \
DEVICE_DT_INST_DEFINE(inst, \
NULL, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_pmc
#include <stdint.h>
#includ<|fim_suffix|> LOG_ERR("The PMC config can not be NULL.");
return -ENXIO;
}
LOG_DBG("Type: %x, Id: %d", cfg->clock_type, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_sam_pmc
#include <pmc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mchp_sam_pmc.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&sckc_api);
<|fim_prefix|>/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_sama7g5_sckc
#include <soc.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Core Devices LLC
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifli_sf32lb_hxt48
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <register.h>
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_DLLXCR_STG_Msk | HPSYS_RCC_DLLXCR_OUT_DIV2_EN);
val |= FIELD_PREP(HPSYS_RCC_DLLXCR_STG_Msk, (freq / HPSYS_RCC_DLLXCR_STG_STEP) - 1U) |
HPSYS_RCC_DLLXCR_IN_DIV2_EN | HPSYS_RCC_DLLXCR_EN;
sys_write32(val, config->base + dllxcr);
do {
val = sys_read32(config->base + dllxcr);
} while ((val & H... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>000000) {
spmd = 2;
} else if (config->freq > 26000000) {
spmd = 1;
} else {
spmd = 0;
}
SI32_FLASHCTRL_A_select_flash_speed_mode(SI32_FLASHCTRL_0, spmd);
/* TODO: support other clock sources */
SI32_CLKCTRL_A_select_ahb_source_pll(SI32_CLKCTRL_0);
}
return 0;
}
static const stru... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 GARDENA GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_si32_apb
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <SI32_CLKCTRL_A_Type.h>
#include <si32_device.h>
s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 GARDENA GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_si32_pll
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <SI32_CLKCTRL_A_Type.h>
#include <SI32_PLL_A_Type.h... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_series_clock
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_silabs.h>
#include <zephyr/sys/util.h>
#include <soc.h>
#include "sl_clock_manager.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2024 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*
* Poor man driver for 917 clocks. 917 includes High Performance (HP) clock
* (@46000000), Ultra Lower Power (ULP) clock (@24041400) and ULP VBAT (@24048000)
*
*/
#include <zephyr/dt-bindings/clock/silabs/siwx91x-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>= smartbond_clock_set_pll_status(false);
#else
da1469x_clock_sys_pll_disable();
#endif
} else {
ret = -EPERM;
}
}
break;
default:
return -ENOTSUP;
}
return ret;
}
static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk)
{
static const enum smartbond_clock lp_c... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Synaptics, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/syna_sr100_clock.h>
#include <zephyr/arch/common/sys_io.h>
#define DT_DRV_COMPAT syna_sr100_clock
#define PLL0_RATE CONFIG_SYS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>LOCK_CONTROL_STATUS_UNKNOWN;
}
if (curr_state) {
return CLOCK_CONTROL_STATUS_OFF;
}
return CLOCK_CONTROL_STATUS_UNKNOWN;
}
static DEVICE_API(clock_control, tisci_clock_driver_api) = {
.get_rate = tisci_get_rate,
.set_rate = tisci_set_rate,
.get_status = tisci_get_status
};
#define TI_K2G_SCI_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_rcc
#include <stdint.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util_macro.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_system.h>
#include <zephyr/arch/cpu.h>
#inc<|fim_suffix|> STM32_DT_CLKS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017-2022 Linaro Limited.
* Copyright (c) 2017 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_system.h>
#include <stm32_ll_util... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
#include <stm32_ll_utils.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2022 Thomas Stranger
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> /* Set sysclk source to HSE */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() !=
LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
}
} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
/* Set sysclk source to HSI */
stm32_clock_switch_to_hsi();
} else if (IS_ENABLED(STM32_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
/**
* @brie... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright <|fim_suffix|>BEL(rcc)) + pclken->bus + RCC_CLR_OFFSET);
/* Ensure that the write operation is completed */
temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus + RCC_CLR_OFFSET);
UNUSED(temp);
return 0;
}
static int stm32_clock_control_configure(const struct device *dev,
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>K_PERIPH_I3C2:
*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C12_I3C12_CLKSOURCE);
break;
#endif
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c4)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c6))
case STM32_CLOCK_PERIPH_I2C4:
case STM32_CLOCK_PERIPH_I2C6:
*rate = LL_RCC_GetI2CClockFreq(LL_RCC_I2C46_CLKSO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_system.h>
#include <zephyr/arch/cpu.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_system.h>
#include <zephyr/arch/cpu.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2022 Thomas Stranger
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <stm32_ll_system.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NODE DT_NODELABEL(clk_lsi)
/* Device tree properties definitions */
#define STM32_WB0_CLKSYS_PRESCALER \
DT_PROP(STM32_CLOCK_CONTROL_NODE, clksys_prescaler)
#if DT_NODE_HAS_PROP(STM32_CLOCK_CONTROL_NODE, slow_clock)
# if !DT_NODE_HAS_STATUS_OKAY(DT_RCC_SLOWCLK_NODE)
# error slow-clock source is not... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_system.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_contro... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>G_ADDR(DT_NODELABEL(rcc)) + reg),
STM32_DT_CLKSEL_MASK_GET(enr) << shift,
STM32_DT_CLKSEL_VAL_GET(enr) << shift);
#if defined(CONFIG_CLOCK_STM32_MCO_HAS_ENABLE_BIT)
/* MCO enable */
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + clken->bus, clken->enr);
#endif /* defined(CONFIG_CLOCK_S... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2022, Linaro Ltd
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#define DT_DRV_COMPAT st_stm32_clock_mux
LOG_MOD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> "clock_stm32_ll_common.h"
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
/* Enable the power interface clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
#if IS_ENABLED(STM32_HSI48_CRS_USB_SOF)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
LL_CRS_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#ifndef CONFIG_SOC_SERIES_STM32F3X
#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
/* Enable System Configuration Controller clock. */
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
#endif
#else
#if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
/* Enable System ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>re PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
#if defined(RCC_CFGR2_PREDIV1SRC)
} else if (IS_ENABLED(STM32_PLL_SRC_PLL2)) {
pll_source = LL_RCC_PLLSOURCE_PLL2... | fim | zephyrproject-rtos/zephyr | c |
/*
*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>crs.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
#if defined(STM32_PLL_ENABLED)
/**
* @brief Return PLL source
*/
__unused... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> "Invalid source");
return 0;
}
/**
* @brief Set up pll configuration
*/
__unused
void config_pll_sysclock(void)
{
/* set power boost mode for sys clock greater than 150MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
LL_PWR_EnableRange1BoostMode();
}
LL_RCC_PLL_ConfigDomain_SYS(get_pll_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_ASSERT(0, "Invalid source");
return 0;
}
/**
* @brief Set up pll configuration
*/
__unused
void config_pll_sysclock(void)
{
LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
pll_mul(STM32_PLL_MULTIPLIER),
pll_div(STM32_PLL_DIVISOR));
}
/**
* @brief Return pllout frequency
*/
__unused
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>M32_PLL_N_MULTIPLIER,
pllr(STM32_PLL_R_DIVISOR));
LL_RCC_PLL_EnableDomain_SYS();
#endif /* STM32_PLL_R_ENABLED */
}
#endif /* STM32_PLL_ENABLED */
#if defined(STM32_PLLSAI1_ENABLED)
/**
* @brief Return PLLSAI1 source
*/
__unused
static uint32_t get_pllsai1_source(void)
{
/* Configure PLL s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lock is probably running but it is requested to ensure
* that it is not released while calibration process in ongoing.
* If system releases the clock during calibration process it
* will be released at the end of calibration process and
* stopped in consequence.
*/
lf_request();
}
}
sta... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CALIBRATION_H_
#define ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CALIBRATION_H_
#include <zephyr/sys/onoff.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_trigger_is_pending,
};
#ifdef CONFIG_ZTEST
static void fake_comp_reset_rule_before(const struct ztest_unit_test *test, void *fixture)
{
ARG_UNUSED(test);
ARG_UNUSED(fixture);
RESET_FAKE(comp_fake_comp_get_output);
RESET_FAKE(comp_fake_comp_set_trigger);
RESET_FAKE(comp_fake_comp_set_trigger_callba... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/comparator.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_comparator_get_output(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_COMPARATOR(dev, get_output))... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> .initial_negative_mux = (uint8_t)DT_INST_PROP(n, negative_mux), \
}; \
\
DEVICE_DT_INST_DEFINE(n,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ce *dev)
{
const struct ifx_lpcomp_channel_config *config = dev->config;
if (config != NULL) {
struct ifx_lpcomp_data *data = dev->data;
if (data != NULL) {
/* Check if the trigger is pending and clear it atomically */
if (atomic_cas(&data->pending, 1, 0)) {
return 1;
}
}
}
return... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it51xxx_vcmp
#include <zephyr/device.h>
#include <zephyr/devicetree/io-channels.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/comparator.h>
#include <zephyr/dt-bindi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.comparator_clock.clock_dev = DEVICE_DT_GET(DT_NODELABEL(clock)), \
.comparator_clock.mclk_sys = \
(void *)(DT_INST_CLOCKS_CEL... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Vestas Wind Systems A/S
* Copyright (c) 2022 NXP
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <fsl_acmp.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/comp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_mspm0_comparator
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/comparator.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/regulator.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>start();
}
return 0;
}
static int shim_nrf_comp_set_trigger_callback(const struct device *dev,
comparator_callback_t callback,
void *user_data)
{
shim_nrf_comp_stop();
shim_nrf_comp_data0.callback = callback;
shim_nrf_comp_data0.user_data = user_data;
if (callback != NULL &... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nrfx_lpcomp.h>
#include <zephyr/drivers/comparator/nrf_lpcomp.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <string.h>
#define DT_DRV_COMPAT nordic_nrf_lpcomp
#define SHIM_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/comparator.h>
#include <zephyr/pm/device.h>
LOG_MODULE_REGISTER(nxp_acomp, C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/irq.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/comparator.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control.h>
LOG_MODULE_REGISTER(nxp_cmp, CONFIG_COMPARATOR_LOG_LEVEL);
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DLE(inst, nxp_references))), (NULL)), \
.ref_supply_val = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, nxp_references), \
(DT_INST_PHA(inst, nxp_references, vref_mv)), (0)), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, nxp_hscmp_init, HSCMP_PM_DEVICE_GET, \
&_CONCAT(data, inst), &_CO... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/irq.h>
#include <zephyr/pm/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/comparator.h>
#include <zephyr/drivers/clock_control.h>
LOG_MODULE_REGISTER(nxp_lpcmp, CONFIG_COMPARATOR_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra_acmphs
#include <zephyr/drivers/comparator.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/kernel.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra_lvd
#include <soc.h>
#include <zephyr/drivers/comparator.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/atom... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
\
static struct lvd_renesas_rx_data lvd_renesas_rx_data_##index = { \
.lvd_config = \
{ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/comparator.h>
#include <zephyr/shell/shell.h>
#include <zephyr/kernel.h>
#include <stdlib.h>
#define AWAIT_TRIGGER_DEFAULT_TIMEOUT \
CONFIG_COMPARATOR_SHELL_AWAIT_TRIGGER_DEFAULT_TI... | fim | zephyrproject-rtos/zephyr | c |
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