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346 Chapter 4 The Processor There are, however, two exceptions to this left-to-right flow of instructions: ■ ■The write-back stage, which places the result back into the register file in the middle of the datapath ■ ■The selection of the next value of the PC, choosing between the incremented PC and the branch address f... | clipped_hennesy_Page_344_Chunk5701 |
Figure 4.34 seems to suggest that three instructions need three datapaths. Instead, we add registers to hold data so that portions of a single datapath can be shared during instruction execution. For example, as Figure 4.34 shows, the instruction memory is used during only one of the five stages of an instruction, allo... | clipped_hennesy_Page_345_Chunk5702 |
348 Chapter 4 The Processor Notice that there is no pipeline register at the end of the write-back stage. All instructions must update some state in the processor—the register file, memory, or the PC—so a separate pipeline register is redundant to the state that is updated. For example, a load instruction will place it... | clipped_hennesy_Page_346_Chunk5703 |
FIGURE 4.36 IF and ID: First and second pipe stages of an instruction, with the active portions of the datapath in Figure 4.35 highlighted. The highlighting convention is the same as that used in Figure 4.28. As in Section 4.2, there is no confusion when reading and writing registers, because the contents change only o... | clipped_hennesy_Page_347_Chunk5704 |
350 Chapter 4 The Processor 3. Execute or address calculation: Figure 4.37 shows that the load instruction reads the contents of register 1 and the sign-extended immediate from the ID/EX pipeline register and adds them using the ALU. That sum is placed in the EX/MEM pipeline register. 4. Memory access: The top portion ... | clipped_hennesy_Page_348_Chunk5705 |
FIGURE 4.38 MEM and WB: The fourth and fifth pipe stages of a load instruction, highlighting the portions of the datapath in Figure 4.35 used in this pipe stage. Data memory is read using the address in the EX/MEM pipeline registers, and the data is placed in the MEM/WB pipeline register. Next, data is read from the ME... | clipped_hennesy_Page_349_Chunk5706 |
352 Chapter 4 The Processor 1. Instruction fetch: The instruction is read from memory using the address in the PC and then is placed in the IF/ID pipeline register. This stage occurs before the instruction is identified, so the top portion of Figure 4.36 works for store as well as load. 2. Instruction decode and regist... | clipped_hennesy_Page_350_Chunk5707 |
FIGURE 4.39 EX: The third pipe stage of a store instruction. Unlike the third stage of the load instruction in Figure 4.37, the second register value is loaded into the EX/MEM pipeline register to be used in the next stage. Although it wouldn’t hurt to always write this second register into the EX/MEM pipeline registe... | clipped_hennesy_Page_351_Chunk5708 |
354 Chapter 4 The Processor FIGURE 4.40 MEM and WB: The fourth and fifth pipe stages of a store instruction. In the fourth stage, the data is written into data memory for the store. Note that the data comes from the EX/MEM pipeline register and that nothing is changed in the MEM/WB pipeline register. Once the data is w... | clipped_hennesy_Page_352_Chunk5709 |
FIGURE 4.41 The corrected pipelined datapath to handle the load instruction properly. The write register number now comes from the MEM/WB pipeline register along with the data. The register number is passed from the ID pipe stage until it reaches the MEM/WB pipeline register, adding five more bits to the last three pi... | clipped_hennesy_Page_353_Chunk5710 |
356 Chapter 4 The Processor Graphically Representing Pipelines Pipelining can be difficult to understand, since many instructions are simulta neously executing in a single datapath in every clock cycle. To aid understanding, there are two basic styles of pipeline figures: multiple-clock-cycle pipeline diagrams, such ... | clipped_hennesy_Page_354_Chunk5711 |
FIGURE 4.43 Multiple-clock-cycle pipeline diagram of five instructions. This style of pipeline representation shows the complete execution of instructions in a single figure. Instructions are listed in instruction execution order from top to bottom, and clock cycles move from left to right. Unlike Figure 4.28, here we... | clipped_hennesy_Page_355_Chunk5712 |
358 Chapter 4 The Processor A group of students were debating the efficiency of the five-stage pipeline when one student pointed out that not all instructions are active in every stage of the pipeline. After deciding to ignore the effects of hazards, they made the following five statements. Which ones are correct? 1. A... | clipped_hennesy_Page_356_Chunk5713 |
Pipelined Control Just as we added control to the single-cycle datapath in Section 4.3, we now add control to the pipelined datapath. We start with a simple design that views the problem through rose-colored glasses; in Sections 4.7 through 4.9, we remove these glasses to reveal the pipeline hazards of the real world. ... | clipped_hennesy_Page_357_Chunk5714 |
360 Chapter 4 The Processor Instruction opcode ALUOp Instruction operation Function code Desired ALU action ALU control input LW 00 load word XXXXXX add 0010 SW 00 store word XXXXXX add 0010 Branch equal 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010 R-type 10 subtract 100010 subtract 0110 R-type 10... | clipped_hennesy_Page_358_Chunk5715 |
As was the case for the single-cycle implementation, we assume that the PC is written on each clock cycle, so there is no separate write signal for the PC. By the same argument, there are no separate write signals for the pipeline registers (IF/ID, ID/EX, EX/MEM, and MEM/WB), since the pipeline registers are also writt... | clipped_hennesy_Page_359_Chunk5716 |
362 Chapter 4 The Processor 4. Memory access: The control lines set in this stage are Branch, MemRead, and MemWrite. These signals are set by the branch equal, load, and store instructions, respectively. Recall that PCSrc in Figure 4.48 selects the next sequential address unless control asserts Branch and the ALU resul... | clipped_hennesy_Page_360_Chunk5717 |
Implementing control means setting the nine control lines to these values in each stage for each instruction. The simplest way to do this is to extend the pipeline registers to include control information. Since the control lines start with the EX stage, we can create the control infor mation during instruction decod... | clipped_hennesy_Page_361_Chunk5718 |
364 Chapter 4 The Processor Figure 4.52 shows that the values read for register $2 would not be the result of the sub instruction unless the read occurred during clock cycle 5 or later. Thus, the instructions that would get the correct value of -20 are add and sw; the AND and OR instructions would get the incorrect val... | clipped_hennesy_Page_362_Chunk5719 |
an instruction tries to use a register in its EX stage that an earlier instruction intends to write in its WB stage, we actually need the values as inputs to the ALU. A notation that names the fields of the pipeline registers allows for a more pre cise notation of dependences. For example, “ID/EX.RegisterRs” refers to... | clipped_hennesy_Page_363_Chunk5720 |
366 Chapter 4 The Processor Because some instructions do not write registers, this policy is inaccurate; sometimes it would forward when it shouldn’t. One solution is simply to check to see if the RegWrite signal will be active: examining the WB control field of the pipeline register during the EX and MEM stages determ... | clipped_hennesy_Page_364_Chunk5721 |
Note that the EX/MEM.RegisterRd field is the register destination for either an ALU instruction (which comes from the Rd field of the instruction) or a load (which comes from the Rt field). This case forwards the result from the previous instruction to either input of the ALU. If the previous instruction is going to wr... | clipped_hennesy_Page_365_Chunk5722 |
368 Chapter 4 The Processor FIGURE 4.54 On the top are the ALU and pipeline registers before adding forwarding. On the bottom, the multiplexors have been expanded to add the forwarding paths, and we show the forwarding unit. The new hardware is shown in color. This figure is a stylized drawing, however, leaving out de... | clipped_hennesy_Page_366_Chunk5723 |
it is not register 0, then steer the multiplexor to pick the value instead from the pipeline register EX/MEM. 2. MEM hazard: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt... | clipped_hennesy_Page_367_Chunk5724 |
370 Chapter 4 The Processor register destination for either an ALU instruction (which comes from the Rd field of the instruction) or a load (which comes from the Rt field). Section 4.12 on the CD shows two pieces of MIPS code with hazards that cause forwarding, if you would like to see more illustrated examples using s... | clipped_hennesy_Page_368_Chunk5725 |
Elaboration: Forwarding can also help with hazards when store instructions are dependent on other instructions. Since they use just one data value during the MEM stage, forwarding is easy. However, consider loads immediately followed by stores, useful when performing memory-to-memory copies in the MIPS architecture. S... | clipped_hennesy_Page_369_Chunk5726 |
372 Chapter 4 The Processor Data Hazards and Stalls As we said in Section 4.5, one case where forwarding cannot save the day is when an instruction tries to read a register following a load instruction that writes the same register. Figure 4.58 illustrates the problem. The data is still being read from memory in clock ... | clipped_hennesy_Page_370_Chunk5727 |
The first line tests to see if the instruction is a load: the only instruction that reads data memory is a load. The next two lines check to see if the destination register field of the load in the EX stage matches either source register of the instruction in the ID stage. If the condition holds, the instruction stalls... | clipped_hennesy_Page_371_Chunk5728 |
374 Chapter 4 The Processor FIGURE 4.59 The way stalls are really inserted into the pipeline. A bubble is inserted beginning in clock cycle 4, by changing the and instruction to a nop. Note that the and instruction is really fetched and decoded in clock cycles 2 and 3, but its EX stage is delayed until clock cycle 5 (v... | clipped_hennesy_Page_372_Chunk5729 |
FIGURE 4.60 Pipelined control overview, showing the two multiplexors for forwarding, the hazard detection unit, and the forwarding unit. Although the ID and EX stages have been simplified—the sign-extended immediate and branch logic are missing— this drawing gives the essence of the forwarding hardware requirements. 0 ... | clipped_hennesy_Page_373_Chunk5730 |
376 Chapter 4 The Processor at every clock cycle to sustain the pipeline, yet in our design the decision about whether to branch doesn’t occur until the MEM pipeline stage. As mentioned in Section 4.5, this delay in determining the proper instruction to fetch is called a control hazard or branch hazard, in contrast to ... | clipped_hennesy_Page_374_Chunk5731 |
Assume Branch Not Taken As we saw in Section 4.5, stalling until the branch is complete is too slow. A com mon improvement over branch stalling is to assume that the branch will not be taken and thus continue execution down the sequential instruction stream. If the branch is taken, the instructions that are being fetc... | clipped_hennesy_Page_375_Chunk5732 |
378 Chapter 4 The Processor 1. During ID, we must decode the instruction, decide whether a bypass to the equality unit is needed, and complete the equality comparison so that if the instruction is a branch, we can set the PC to the branch target address. For warding for the operands of branches was formerly handled by... | clipped_hennesy_Page_376_Chunk5733 |
FIGURE 4.62 The ID stage of clock cycle 3 determines that a branch must be taken, so it selects 72 as the next PC address and zeros the instruction fetched for the next clock cycle. Clock cycle 4 shows the instruction at location 72 being fetched and the single bubble or nop instruction in the pipeline as a result of t... | clipped_hennesy_Page_377_Chunk5734 |
380 Chapter 4 The Processor Dynamic Branch Prediction Assuming a branch is not taken is one simple form of branch prediction. In that case, we predict that branches are untaken, flushing the pipeline when we are wrong. For the simple five-stage pipeline, such an approach, possibly coupled with compiler-based prediction... | clipped_hennesy_Page_378_Chunk5735 |
Ideally, the accuracy of the predictor would match the taken branch frequency for these highly regular branches. To remedy this weakness, 2-bit prediction schemes are often used. In a 2-bit scheme, a prediction must be wrong twice before it is changed. Figure 4.63 shows the finite-state machine for a 2-bit predictio... | clipped_hennesy_Page_379_Chunk5736 |
382 Chapter 4 The Processor Delayed branching was a simple and effective solution for a five-stage pipeline issuing one instruction each clock cycle. As processors go to both longer pipelines and issuing multiple instructions per clock cycle (see Section 4.10), the branch delay becomes longer, and a single delay slot i... | clipped_hennesy_Page_380_Chunk5737 |
one approach to eliminate that penalty. Another approach is to use a cache to hold the destination program counter or destination instruction using a branch target buffer. The 2-bit dynamic prediction scheme uses only information about a particular branch. Researchers noticed that using information about both a local b... | clipped_hennesy_Page_381_Chunk5738 |
384 Chapter 4 The Processor 4.9 Exceptions Control is the most challenging aspect of processor design: it is both the hardest part to get right and the hardest part to make fast. One of the hardest parts of con trol is implementing exceptions and interrupts—events other than branches or jumps that change the normal fl... | clipped_hennesy_Page_382_Chunk5739 |
the term exception to refer to any unexpected change in control flow without distinguishing whether the cause is internal or external; we use the term interrupt only when the event is externally caused. Here are five examples showing whether the situation is internally generated by the processor or externally generated... | clipped_hennesy_Page_383_Chunk5740 |
386 Chapter 4 The Processor methods used to communicate the reason for an exception. The method used in the MIPS architecture is to include a status register (called the Cause register), which holds a field that indicates the reason for the exception. A second method, is to use vectored interrupts. In a vectored interr... | clipped_hennesy_Page_384_Chunk5741 |
A new control signal, called ID.Flush, is ORed with the stall signal from the hazard detection unit to flush during ID. To flush the instruction in the EX phase, we use a new signal called EX.Flush to cause new multiplexors to zero the control lines. To start fetching instructions from location 8000 0180hex, which is... | clipped_hennesy_Page_385_Chunk5742 |
388 Chapter 4 The Processor The final step is to save the address of the offending instruction in the exception program counter (EPC). In reality, we save the address + 4, so the exception handling routine must first subtract 4 from the saved value. Figure 4.66 shows a stylized version of the datapath, including the b... | clipped_hennesy_Page_386_Chunk5743 |
FIGURE 4.67 The result of an exception due to arithmetic overflow in the add instruction. The overflow is detected during the EX stage of clock 6, saving the address following the add in the EPC register (4C + 4 = 50hex). Overflow causes all the Flush signals to be set near the end of this clock cycle, deasserting cont... | clipped_hennesy_Page_387_Chunk5744 |
390 Chapter 4 The Processor The EPC captures the address of the interrupted instructions, and the MIPS Cause register records all possible exceptions in a clock cycle, so the exception software must match the exception to the instruction. An important clue is know ing in which pipeline stage a type of exception can oc... | clipped_hennesy_Page_388_Chunk5745 |
Which exception should be recognized first in this sequence? 1. add $1, $2, $1 # arithmetic overflow 2. XXX $1, $2, $1 # undefined instruction 3. sub $1, $2, $1 # hardware error 4.10 Parallelism and Advanced Instruction- Level Parallelism Be forewarned: this section is a brief overview of fascinating but advanced topi... | clipped_hennesy_Page_389_Chunk5746 |
392 Chapter 4 The Processor There are two major ways to implement a multiple-issue processor, with the major difference being the division of work between the compiler and the hardware. Because the division of work dictates whether decisions are being made statically (that is, at compile time) or dynamically (that is... | clipped_hennesy_Page_390_Chunk5747 |
a branch or a load across a store. The processor hardware can perform the same transformation at runtime using techniques we discuss later in this section. The recovery mechanisms used for incorrect speculation are rather different. In the case of speculation in software, the compiler usually inserts additional instruc... | clipped_hennesy_Page_391_Chunk5748 |
394 Chapter 4 The Processor An Example: Static Multiple Issue with the MIPS ISA To give a flavor of static multiple issue, we consider a simple two-issue MIPS pro cessor, where one of the instructions can be an integer ALU operation or branch and the other can be a load or store. Such a design is like that used in so... | clipped_hennesy_Page_392_Chunk5749 |
two registers for the ALU operation and two more for a store, and also one write port for an ALU operation and one write port for a load. Since the ALU is tied up for the ALU operation, we also need a separate adder to calculate the effective address for data transfers. Without these extra resources, our two-issue pipe... | clipped_hennesy_Page_393_Chunk5750 |
396 Chapter 4 The Processor one-instruction use latency, since the results cannot be used in the paired load or store. To effectively exploit the parallelism available in a multiple-issue processor, more ambitious compiler or hardware scheduling techniques are needed, and static multiple issue requires that the compile... | clipped_hennesy_Page_394_Chunk5751 |
An important compiler technique to get more performance from loops is loop unrolling, where multiple copies of the loop body are made. After unrolling, there is more ILP available by overlapping instructions from different iterations. Loop Unrolling for Multiple-Issue Pipelines See how well loop unrolling and schedulin... | clipped_hennesy_Page_395_Chunk5752 |
398 Chapter 4 The Processor in a given clock cycle. Obviously, achieving good performance on such a processor still requires the compiler to try to schedule instructions to move dependences apart and thereby improve the instruction issue rate. Even with such compiler scheduling, there is an important difference between... | clipped_hennesy_Page_396_Chunk5753 |
Dynamic Pipeline Scheduling Dynamic pipeline scheduling chooses which instructions to execute next, possibly reordering them to avoid stalls. In such processors, the pipeline is divided into three major units: an instruction fetch and issue unit, multiple functional units (a dozen or more in high-end designs in 2008), ... | clipped_hennesy_Page_397_Chunk5754 |
400 Chapter 4 The Processor The combination of buffering operands in the reservation stations and results in the reorder buffer provides a form of register renaming, just like that used by the compiler in our earlier loop-unrolling example on page 397. To see how this conceptually works, consider the following steps: 1... | clipped_hennesy_Page_398_Chunk5755 |
Given that compilers can also schedule code around data dependences, you might ask why a superscalar processor would use dynamic scheduling. There are three major reasons. First, not all stalls are predictable. In particular, cache misses (see Chapter 5) cause unpredictable stalls. Dynamic scheduling allows the process... | clipped_hennesy_Page_399_Chunk5756 |
402 Chapter 4 The Processor Modern, high-performance microprocessors are capable of issuing several instructions per clock; unfortunately, sustaining that issue rate is very difficult. For example, despite the existence of processors with four to six issues per clock, very few applications can sustain more than two ins... | clipped_hennesy_Page_400_Chunk5757 |
of a register until the instruction updating the register is no longer speculative. Other processors buffer the result, typically in a structure called a reorder buffer, and the actual update to the register file occurs later as part of the commit. Stores to memory must be buffered until commit time either in a store b... | clipped_hennesy_Page_401_Chunk5758 |
404 Chapter 4 The Processor 4.11 Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline Like most modern computers, x86 microprocessors employ sophisticated pipelining approaches. These processors, however, are still faced with the challenge of implementing the complex x86 instruction set, described in Chapter 2. Both AM... | clipped_hennesy_Page_402_Chunk5759 |
3. The X4 microarchitecture has many more registers than x86 requires. 4. X4 uses less than half the pipeline stages of the earlier Pentium 4 Prescott (see Figure 4.73). FIGURE 4.74 The microarchitecture of AMD Opteron X4. The extensive queues allow up to 106 RISC operations to be outstanding, including 24 integer ope... | clipped_hennesy_Page_403_Chunk5760 |
406 Chapter 4 The Processor The Opteron X4 combines a 12-stage pipeline and aggressive multiple issue to achieve high performance. By keeping the latencies for back-to-back operations low, the impact of data dependences is reduced. What are the most serious potential performance bottlenecks for programs running on thi... | clipped_hennesy_Page_404_Chunk5761 |
form suitable for hardware synthesis. It then provides a series of behavioral models in Verilog of the MIPS five-stage pipeline. The initial model ignores hazards, and additions to the model highlight the changes for forwarding, data hazards, and branch hazards. We then provide about a dozen illustrations using the sin... | clipped_hennesy_Page_405_Chunk5762 |
408 Chapter 4 The Processor addressing modes that require multiple memory accesses substantially complicate pipeline control and make it difficult to keep the pipeline flowing smoothly. Perhaps the best example is the DEC Alpha and the DEC NVAX. In comparable technology, the newer instruction set architecture of the ... | clipped_hennesy_Page_406_Chunk5763 |
of some of the inventions since the mid-1990s, resulting in a simplification of pipelines in the more recent versions of microarchitectures. To sustain the advances in processing performance via parallel processors, Amdahl’s law suggests that another part of the system will become the bottleneck. That bottleneck is th... | clipped_hennesy_Page_407_Chunk5764 |
410 Chapter 4 The Processor Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Laten- cies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruc... | clipped_hennesy_Page_408_Chunk5765 |
Improvement Latency Cost Benefit a. Add Multiplier to ALU +300ps for ALU +600 for ALU Lets us add MUL instruction. Allows us to execute 5% fewer instructions (MUL no longer emulated). b. Simpler Control +100ps for Control –400 for Control Control becomes slower but cheaper logic. 4.2.4 [10] <4.1> What is the clock cycl... | clipped_hennesy_Page_409_Chunk5766 |
412 Chapter 4 The Processor 4.3.4 [5] <4.1, 4.2> What is the latency of your implementation from 4.3.2? 4.3.5 [5] <4.1, 4.2> What is the cost of your implementation from 4.3.2? 4.3.6 [20] <4.1, 4.2> Change your design to minimize the latency, then to mini- mize the cost. Compare the cost and latency of these two optimi... | clipped_hennesy_Page_410_Chunk5767 |
4.4.6 [10] <4.2> What fraction of the cost was saved in your circuit from 4.4.3 by implementing these two control signals together instead of separately? Exercise 4.5 The goal of this exercise is to help you familiarize yourself with the design and operation of sequential logical circuits. Problems in this exercise ref... | clipped_hennesy_Page_411_Chunk5768 |
414 Chapter 4 The Processor 4.5.5 [10] <4.2> Compute the cost for the circuit you designed in 4.5.1, and then for the circuit you designed in 4.5.2. 4.5.6 [5] <4.2> Compare cost/performance ratios for the two circuits you designed in 4.5.1 and 4.5.2. For this problem, performance of a circuit is the inverse of the time... | clipped_hennesy_Page_412_Chunk5769 |
Exercise 4.7 In this exercise we examine how latencies of individual components of the data- path affect the clock cycle time of the entire datapath, and how these components are utilized by instructions. For problems in this exercise, assume the following latencies for logic blocks in the datapath: I-Mem Add Mux ALU R... | clipped_hennesy_Page_413_Chunk5770 |
416 Chapter 4 The Processor cross-talk faults is when a signal is connected to a wire that has a constant logical value (e.g., a power supply wire). In this case we have a stuck-at-0 or a stuck-at-1 fault, and the affected signal always has a logical value of 0 or 1, respectively. The following problems refer to the fo... | clipped_hennesy_Page_414_Chunk5771 |
4.8.6 [40] <4.3, 4.4> Using a single test described in 4.8.1, we can test for faults in several different signals, but typically not all of them. Describe a series of tests to look for this fault in all Mux outputs (every output bit from each of the five Muxes). Try to do this with as few single-instruction tests as po... | clipped_hennesy_Page_415_Chunk5772 |
418 Chapter 4 The Processor Exercise 4.10 In this exercise we examine how the clock cycle time of the processor affects the design of the control unit, and vice versa. Problems in this exercise assume that the logic blocks used to implement the datapath have the following latencies: I-Mem Add Mux ALU Regs D-Mem Sign-Ex... | clipped_hennesy_Page_416_Chunk5773 |
Exercise 4.11 In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: Instruction word a. 10101100011000100000000000010100 b. 00000000100000100000100000101010 4.11.1 [... | clipped_hennesy_Page_417_Chunk5774 |
420 Chapter 4 The Processor 4.12.1 [5] <4.5> What is the clock cycle time in a pipelined and non-pipelined processor? 4.12.2 [10] <4.5> What is the total latency of an LW instruction in a pipelined and non-pipelined processor? 4.12.3 [10] <4.5> If we can split one stage of the pipelined datapath into two new stages, ea... | clipped_hennesy_Page_418_Chunk5775 |
4.13.1 [10] <4.5> Indicate dependences and their type. 4.13.2 [10] <4.5> Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to eliminate them. 4.13.3 [10] <4.5> Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them. Without Forward... | clipped_hennesy_Page_419_Chunk5776 |
422 Chapter 4 The Processor only have one memory (for both instructions and data), there is a structural haz- ard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that a... | clipped_hennesy_Page_420_Chunk5777 |
computation is moved to the MEM stage? What is the speedup from this change? Assume that the latency of the EX stage is reduced by 20ps and the latency of the MEM stage is unchanged when branch outcome resolution is moved from EX to MEM. Exercise 4.15 In this exercise, we examine how the ISA affects pipeline design. Pr... | clipped_hennesy_Page_421_Chunk5778 |
424 Chapter 4 The Processor Exercise 4.16 The first three problems in this exercise refer to the following MIPS instruction: Instruction a. SW R16,–100(R6) b. OR R2,R1,R0 4.16.1 [5] <4.6> As this instruction executes, what is kept in each register located between two pipeline stages? 4.16.2 [5] <4.6> Which registers ne... | clipped_hennesy_Page_422_Chunk5779 |
Exercise 4.17 Problems in this exercise assume that instructions executed by a pipelined proces- sor are broken down as follows: ADD BEQ LW SW a. 40% 30% 25% 5% b. 60% 10% 20% 10% 4.17.1 [5] <4.6> Assuming there are no stalls and that 60% of all conditional branches are taken, in what percentage of clock cycles does th... | clipped_hennesy_Page_423_Chunk5780 |
426 Chapter 4 The Processor Exercise 4.18 The first three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4.51, and assume the following clock cycle time, ALU latency, and Mux latency: Instruction Clock Cycle Time ALU Latency Mux Latency a. LW R1,32(R2... | clipped_hennesy_Page_424_Chunk5781 |
have a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the instruction that consumes the result (1st instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register ... | clipped_hennesy_Page_425_Chunk5782 |
428 Chapter 4 The Processor hazards? Assume that the yet-to-be-invented time-travel circuitry adds 100ps to the latency of the full-forwarding EX stage. 4.19.6 [20] <4.7> Repeat 4.19.3 but this time determine which of the two options results in shorter time per instruction. Exercise 4.20 Problems in this exercise refe... | clipped_hennesy_Page_426_Chunk5783 |
4.20.6 [10] <4.7> For the design described in 4.20.5, add NOPs to this instruction sequence to ensure correct execution in spite of missing support for forwarding. Exercise 4.21 This exercise is intended to help you understand the relationship between forward- ing, hazard detection, and ISA design. Problems in this exe... | clipped_hennesy_Page_427_Chunk5784 |
430 Chapter 4 The Processor Exercise 4.22 This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exer- cise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full f... | clipped_hennesy_Page_428_Chunk5785 |
4.22.5 [10] <4.8> For the given code, what is the speedup achieved by moving branch execution into the ID stage? Explain your answer. In your speedup calcula- tion, assume that the additional comparison in the ID stage does not affect clock cycle time. 4.22.6 [10] <4.8> Using the first branch instruction in the given c... | clipped_hennesy_Page_429_Chunk5786 |
432 Chapter 4 The Processor 4.23.5 [10] <4.8> With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaced each branch instruction with two ALU instructions? Assume that correctly and incorrectly pre- dicted instructions have the same chance of bein... | clipped_hennesy_Page_430_Chunk5787 |
Exercise 4.25 This exercise explores how exception handling affects pipeline design. The first three problems in this exercise refer to the following two instructions: Instruction 1 Instruction 2 a. BNE R1,R2,Label LW R1,0(R1) b. JUMP Label SW R5,0(R1) 4.25.1 [5] <4.9> Which exceptions can each of these instructions tr... | clipped_hennesy_Page_431_Chunk5788 |
434 Chapter 4 The Processor Exercise 4.26 This exercise explores how exception handling affects control unit design and pro- cessor clock cycle time. The first three problems in this exercise refer to the follow- ing MIPS instruction that triggers an exception: Instruction Exception a. BNE R1,R2,Label Invalid target ad... | clipped_hennesy_Page_432_Chunk5789 |
Exercise 4.27 This exercise examines how exception handling interacts with branch and load/ store instructions. Problems in this exercise refer to the following branch instruc- tion and the corresponding delay slot instruction: Branch and Delay Slot a. BEQ R5,R4,Label SLT R5,R15,R4 b. BEQ R1,R0,Label LW R1,0(R1) 4.27.1... | clipped_hennesy_Page_433_Chunk5790 |
436 Chapter 4 The Processor value equal to WVAL is about to be written to address WADDR. How would you change the pipeline to implement this? How would this SW instruction be handled by your modified datapath? Exercise 4.28 In this exercise we compare the performance of 1-issue and 2-issue processors, tak- ing into acc... | clipped_hennesy_Page_434_Chunk5791 |
4.28.2, assume that the processor has perfect branch predictions, and that a 2-issue processor can fetch any two instructions in the same cycle. 4.28.6 [10] <4.10> Repeat 4.28.5, but this time assume that in the 2-issue pro- cessor one of the instructions to be executed in a cycle can be of any kind, and the other must... | clipped_hennesy_Page_435_Chunk5792 |
438 Chapter 4 The Processor iterations. You can use registers R10 through R20 when changing the code to elimi- nate dependences. 4.29.5 [20] <4.10> What is the speedup of using your code from 4.29.4 instead of the original code with a 2-issue static superscalar processor? Assume that the loop has many (e.g., 1,000,000)... | clipped_hennesy_Page_436_Chunk5793 |
conclusion can you draw about the importance of good branch prediction when the pipeline depth of the processor is increased? Exercise 4.31 Problems in this exercise refer to the following loop, which is given as x86 code and also as an MIPS translation of that code. You can assume that this loop executes many itera- t... | clipped_hennesy_Page_437_Chunk5794 |
440 Chapter 4 The Processor the operation, and WB writes the result to register or memory. The data memory has a read port (for instructions in the MRD stage) and a separate write port (for instructions in the WB stage). 4.31.3 [20] <4.11> What CPI would be achieved if the X86 version of this loop is executed on a proc... | clipped_hennesy_Page_438_Chunk5795 |
The remaining problems in this exercise assume the following pipeline depth and that the branch outcome is determined in the following pipeline stage (counting from stage 1): Pipeline Depth Branch Outcome Known in Stage a. 15 12 b. 30 20 4.32.2 [5] <4.11> In a 4-issue processor with these pipeline parameters, how many ... | clipped_hennesy_Page_439_Chunk5796 |
442 Chapter 4 The Processor 4.33.3 [10] <4.11> Repeat 4.33.2, but this time every executed instruction has a RAW data dependence to the instruction that executes right after it. You can assume that no stall cycles are needed, i.e., forwarding allows consecutive instruc- tions to execute in back-to-back cycles. For the ... | clipped_hennesy_Page_440_Chunk5797 |
4.34.3 [10] <4.13> What needs to be done to support undefined instruction exceptions in your datapath from 4.34.1? Note that the undefined instruction exception should be triggered whenever the processor encounters any other kind of instruction. The remaining two problems in this exercise also refer to this MIPS instru... | clipped_hennesy_Page_441_Chunk5798 |
444 Chapter 4 The Processor 4.35.3 [10] <4.8, 4.13> Repeat 4.35.2, but now assume that 10% of executed branches have all four delay slots filled with useful instruction, 20% have only three useful instructions in delay slots (the fourth delay slot is an NOP), 30% have only two useful instructions in delay slots, and 40... | clipped_hennesy_Page_442_Chunk5799 |
4.36.3 [20] <4.13> If we want to add this instruction to the MIPS ISA, discuss the changes to the pipeline (which stages, which structures in which stage) that are needed to directly (without micro-ops) support this instruction. 4.36.4 [10] <4.13> How often do you expect this instruction can be used? Do you think that ... | clipped_hennesy_Page_443_Chunk5800 |
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