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446 Chapter 4 The Processor 4.37.1 [5] <4.3, 4.14> Which parts of the basic single-cycle datapath are used by all of these instructions? Which parts are the least utilized? 4.37.2 [10] <4.6, 4.14> What is the utilization for the read and for the write port of the data memory unit? 4.37.3 [10] <4.6, 4.14> Assume that we... | clipped_hennesy_Page_444_Chunk5801 |
4.38.2 [10] <4.6, 4.14> What is the worst-case MIPS instruction in terms of energy consumption, and what is the energy spent to execute it? 4.38.3 [10] <4.6, 4.14> If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LW instruction after... | clipped_hennesy_Page_445_Chunk5802 |
448 Chapter 4 The Processor to do its work within the given latency. Note that no energy is spent in the MEM stage during a cycle in which there is no memory access. Similarly, no energy is spent in the WB stage in a cycle in which there is no register write. In several of the following problems, we make assumptions ab... | clipped_hennesy_Page_446_Chunk5803 |
§4.10, page 403: 1. Both. 2. Both. 3. Software. 4. Hardware. 5. Hardware. 6. Hardware. 7. Both. 8. Hardware. 9. Both. §4.11, page 404: First two are false and last two are true. §4.12, page 4.12-3: Statements 1 and 3 are both true. §4.12, page 4.12-5: The best answer is 2 (see the Elaboration on page 371) 4.16 Exercise... | clipped_hennesy_Page_447_Chunk5804 |
5 Ideally one would desire an indefinitely large memory capacity such that any particular . . . word would be immediately available. . . . We are . . . forced to recognize the possibility of constructing a hierarchy of memories, each of which has greater capacity than the preceding but which is less quickly accessible... | clipped_hennesy_Page_448_Chunk5805 |
5.7 Using a Finite-State Machine to Control a Simple Cache 529 5.8 Parallelism and Memory Hierarchies: Cache Coherence 534 5.9 Advanced Material: Implementing Cache Controllers 538 5.10 Real Stuff: the AMD Opteron X4 (Barcelona) and Intel Nehalem Memory Hierarchies 539 5.11 Fallacies and Pitfalls 543 5.12 Concluding R... | clipped_hennesy_Page_449_Chunk5806 |
452 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.1 Introduction From the earliest days of computing, programmers have wanted unlimited amounts of fast memory. The topics in this chapter aid programmers by creating that illusion. Before we look at creating the illusion, let’s consider a simple analogy that il... | clipped_hennesy_Page_450_Chunk5807 |
you brought out the book on early English computers to find out about the EDSAC, you also noticed that there was another book shelved next to it about early mechanical computers, so you also brought back that book and, later on, found something useful in that book. Libraries put books on the same topic together on the ... | clipped_hennesy_Page_451_Chunk5808 |
454 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The data is similarly hierarchical: a level closer to the processor is generally a subset of any level further away, and all the data is stored at the lowest level. By analogy, the books on your desk form a subset of the library you are working in, which is in t... | clipped_hennesy_Page_452_Chunk5809 |
Since performance is the major reason for having a memory hierarchy, the time to service hits and misses is important. Hit time is the time to access the upper level of the memory hierarchy, which includes the time needed to determine whether the access is a hit or a miss (that is, the time needed to look through the b... | clipped_hennesy_Page_453_Chunk5810 |
456 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Programs exhibit both temporal locality, the tendency to reuse recently accessed data items, and spatial locality, the tendency to reference data items that are close to other recently accessed items. Memory hierarchies take advantage of temporal locality by kee... | clipped_hennesy_Page_454_Chunk5811 |
Which of the following statements are generally true? 1. Caches take advantage of temporal locality. 2. On a read, the value returned depends on which blocks are in the cache. 3. Most of the cost of the memory hierarchy is at the highest level. 4. Most of the capacity of the memory hierarchy is at the lowest level. 5.2... | clipped_hennesy_Page_455_Chunk5812 |
458 Chapter 5 Large and Fast: Exploiting Memory Hierarchy If the number of entries in the cache is a power of 2, then modulo can be computed simply by using the low-order log2 (cache size in blocks) bits of the address. Thus, an 8-block cache uses the three lowest bits (8 = 23) of the block address. For example, Figur... | clipped_hennesy_Page_456_Chunk5813 |
For the rest of this section, we will focus on explaining how a cache deals with reads. In general, handling reads is a little simpler than handling writes, since reads do not have to change the contents of the cache. After seeing the basics of how reads work and how cache misses can be handled, we’ll examine the cache... | clipped_hennesy_Page_457_Chunk5814 |
460 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Decimal address of reference Binary address of reference Hit or miss in cache Assigned cache block (where found or placed) 22 10110two miss (5.6b) (10110two mod 8) = 110two 26 11010two miss (5.6c) (11010two mod 8) = 010two 22 10110two hit (10110two mod 8) = 110t... | clipped_hennesy_Page_458_Chunk5815 |
Index V Tag Data Index V Tag Data 000 N 000 N 001 N 001 N 010 N 010 N 011 N 011 N 100 N 100 N 101 N 101 N 110 N 110 Y 10two Memory (10110two) 111 N 111 N a. The initial state of the cache after power-on b. After handling a miss of address (10110two) Index V Tag Data Index V Tag Data 000 N 000 Y 10two Memory (10000two) ... | clipped_hennesy_Page_459_Chunk5816 |
462 Chapter 5 Large and Fast: Exploiting Memory Hierarchy ■ ■32-bit byte addresses ■ ■A direct-mapped cache ■ ■The cache size is 2n blocks, so n bits are used for the index ■ ■The block size is 2m words (2m+2 bytes), so m bits are used for the word within the block, and two bits are used for the byte part of the addres... | clipped_hennesy_Page_460_Chunk5817 |
The total number of bits in a direct-mapped cache is 2n × (block size + tag size + valid field size). Since the block size is 2m words (2m+5 bits), and we need 1 bit for the valid field, the number of bits in such a cache is 2n × (2m × 32 + (32 - n - m - 2) + 1) = 2n × (2m × 32 + 31 - n - m). Although this is the actua... | clipped_hennesy_Page_461_Chunk5818 |
464 Chapter 5 Large and Fast: Exploiting Memory Hierarchy where the address of the block is Byte address Bytes per block Notice that this block address is the block containing all addresses between Byte address Bytes per block × Bytes per block and Byte address Bytes per block × Bytes p... | clipped_hennesy_Page_462_Chunk5819 |
Elaboration: Although it is hard to do anything about the longer latency component of the miss penalty for large blocks, we may be able to hide some of the transfer time so that the miss penalty is effectively smaller. The simplest method for doing this, called early restart, is simply to resume execution as soon as t... | clipped_hennesy_Page_463_Chunk5820 |
466 Chapter 5 Large and Fast: Exploiting Memory Hierarchy from memory (or, as we shall see, a lower-level cache). If the cache reports a hit, the computer continues using the data as if nothing happened. Modifying the control of a processor to handle a hit is trivial; misses, however, require some extra work. The cach... | clipped_hennesy_Page_464_Chunk5821 |
to keep the main memory and the cache consistent is always to write the data into both the memory and the cache. This scheme is called write-through. The other key aspect of writes is what occurs on a write miss. We first fetch the words of the block from memory. After the block is fetched and placed into the cache, we... | clipped_hennesy_Page_465_Chunk5822 |
468 Chapter 5 Large and Fast: Exploiting Memory Hierarchy that sometimes programs write entire blocks of data, such as when the operating system zeros a page of memory. In such cases, the fetch associated with the initial write miss may be unnecessary. Some computers allow the write allocation policy to be changed on ... | clipped_hennesy_Page_466_Chunk5823 |
each cache. (Remember that we need to update the instruction cache when a miss occurs.) Thus, the steps for a read request to either cache are as follows: 1. Send the address to the appropriate cache. The address comes either from the PC (for an instruction) or from the ALU (for data). 2. If the cache signals hit, the ... | clipped_hennesy_Page_467_Chunk5824 |
470 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 3. If the cache signals miss, we send the address to the main memory. When the memory returns with the data, we write it into the cache and then read it to fulfill the request. For writes, the Intrinsity FastMATH offers both write-through and write-back, leaving... | clipped_hennesy_Page_468_Chunk5825 |
Designing the Memory System to Support Caches Cache misses are satisfied from main memory, which is constructed from DRAMs. In Section 5.1, we saw that the primary emphasis with DRAMs is on cost and density. Although it is difficult to reduce the latency to fetch the first word from memory, we can reduce the miss penal... | clipped_hennesy_Page_469_Chunk5826 |
472 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Instead of making the entire path between the memory and cache wider, the memory chips can be organized in banks to read or write multiple words in one access time rather than reading or writing a single word each time. Each bank could be one word wide so that t... | clipped_hennesy_Page_470_Chunk5827 |
Banks are also valuable on writes. Each bank can write independently, quadrupling the write bandwidth and leading to fewer stalls in a write-through cache. As we will see, an alternative strategy for writes makes interleaving even more attractive. Because of the ubiquity of caches and the desire for larger block sizes... | clipped_hennesy_Page_471_Chunk5828 |
474 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Year introduced Chip size $ per GB Total access time to a new row/column Column access time to existing row 1980 64 Kbit $1,500,000 250 ns 150 ns 1983 256 Kbit $500,000 185 ns 100 ns 1985 1 Mbit $200,000 135 ns 40 ns 1989 4 Mbit $50,000 110 ns 40 ns 1992 16 Mbit... | clipped_hennesy_Page_472_Chunk5829 |
The speed of the memory system affects the designer’s decision on the size of the cache block. Which of the following cache designer guidelines are generally valid? 1. The shorter the memory latency, the smaller the cache block 2. The shorter the memory latency, the larger the cache block 3. The higher the memory bandw... | clipped_hennesy_Page_473_Chunk5830 |
476 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The read-stall cycles can be defined in terms of the number of read accesses per program, the miss penalty in clock cycles for a read, and the read miss rate: Read-stall cycles = Reads Program × Read miss rate × Read miss penalty Writes are more complicate... | clipped_hennesy_Page_474_Chunk5831 |
Calculating Cache Performance Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 100 cycles for all misses, determine how much faster a pro cessor would run with a perfect cache that never missed.... | clipped_hennesy_Page_475_Chunk5832 |
478 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 4.44 1 = 4.44 times faster. The amount of execution time spent on memory stalls would have risen from 3.44 5.44 = 63% to 3.44 4.44 = 77%. Similarly, increasing the clock rate without changing the memory system also increases the performance los... | clipped_hennesy_Page_476_Chunk5833 |
The average memory access time per instruction is AMAT = Time for a hit + Miss rate × Miss penalty = 1 + 0.05 × 20 = 2 clock cycles or 2 ns. The next subsection discusses alternative cache organizations that decrease miss rate but may sometimes increase hit time; additional examples appear in Section 5.11, Fallacies an... | clipped_hennesy_Page_477_Chunk5834 |
480 Chapter 5 Large and Fast: Exploiting Memory Hierarchy placement and fully associative placement: a block is directly mapped into a set, and then all the blocks in the set are searched for a match. For example, Figure 5.13 shows where block 12 may be placed in a cache with eight blocks total, according to the three... | clipped_hennesy_Page_478_Chunk5835 |
We can also think of all block placement strategies as a variation on set associativity. Figure 5.14 shows the possible associativity structures for an eight- block cache. A direct-mapped cache is simply a one-way set-associative cache: each cache entry holds one block and each set has one element. A fully associative ... | clipped_hennesy_Page_479_Chunk5836 |
482 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Misses and Associativity in Caches Assume there are three small caches, each consisting of four one-word blocks. One cache is fully associative, a second is two-way set-associative, and the third is direct-mapped. Find the number of misses for each cache organiz... | clipped_hennesy_Page_480_Chunk5837 |
Because we have a choice of which entry in a set to replace on a miss, we need a replacement rule. Set-associative caches usually replace the least recently used block within a set; that is, the block that was used furthest in the past is replaced. (We will discuss other replacement rules in more detail shortly.) Using... | clipped_hennesy_Page_481_Chunk5838 |
484 Chapter 5 Large and Fast: Exploiting Memory Hierarchy How much of a reduction in the miss rate is achieved by associativity? Figure 5.15 shows the improvement for a 64 KB data cache with a 16-word block, and associa tivity ranging from direct mapped to eight-way. Going from one-way to two- way associativity decrea... | clipped_hennesy_Page_482_Chunk5839 |
In a direct-mapped cache, only a single comparator is needed, because the entry can be in only one block, and we access the cache simply by indexing. Figure 5.17 shows that in a four-way set-associative cache, four comparators are needed, together with a 4‑to-1 multiplexor to choose among the four potential members of ... | clipped_hennesy_Page_483_Chunk5840 |
486 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Size of Tags versus Set Associativity Increasing associativity requires more comparators and more tag bits per cache block. Assuming a cache of 4K blocks, a 4-word block size, and a 32‑bit address, find the total number of sets and the total number of tag bits f... | clipped_hennesy_Page_484_Chunk5841 |
Since there are 16 (= 24) bytes per block, a 32-bit address yields 32 - 4 = 28 bits to be used for index and tag. The direct-mapped cache has the same number of sets as blocks, and hence 12 bits of index, since log2(4K) = 12; hence, the total number is (28 - 12) × 4K = 16 × 4K = 64 K tag bits. Each degree of associativ... | clipped_hennesy_Page_485_Chunk5842 |
488 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The effective CPI with one level of caching is given by Total CPI = Base CPI + Memory-stall cycles per instruction For the processor with one level of caching, Total CPI = 1.0 + Memory-stall cycles per instruction = 1.0 + 2% × 400 = 9 With two levels of caching,... | clipped_hennesy_Page_486_Chunk5843 |
The effect of these changes on the two caches can be seen by comparing each cache to the optimal design for a single level of cache. In comparison to a single- level cache, the primary cache of a multilevel cache is often smaller. Furthermore, the primary cache may use a smaller block size, to go with the smaller cach... | clipped_hennesy_Page_487_Chunk5844 |
490 Chapter 5 Large and Fast: Exploiting Memory Hierarchy FIGURE 5.18 Comparing Quicksort and Radix Sort by (a) instructions executed per item sorted, (b) time per item sorted, and (c) cache misses per item sorted. This data is from a paper by LaMarca and Ladner [1996]. Although the numbers would change for newer compu... | clipped_hennesy_Page_488_Chunk5845 |
There is no general way to calculate overlapped miss latency, so evaluations of memory hierarchies for out-of-order processors inevitably require simulation of the processor and memory hierarchy. Only by seeing the execution of the processor during each miss can we see if the processor stalls waiting for data or simpl... | clipped_hennesy_Page_489_Chunk5846 |
492 Chapter 5 Large and Fast: Exploiting Memory Hierarchy large. The secondary cache, which is often ten or more times larger than the primary cache, handles many accesses that miss in the primary cache. In such cases, the miss penalty is that of the access time to the secondary cache (typically < 10 processor cycles)... | clipped_hennesy_Page_490_Chunk5847 |
both code and data. Calls between procedures in different modules would lead to overlaying of one module with another. As you can well imagine, this responsibility was a substantial burden on pro grammers. Virtual memory, which was invented to relieve programmers of this difficulty, automatically manages the two level... | clipped_hennesy_Page_491_Chunk5848 |
494 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Virtual memory also simplifies loading the program for execution by providing relocation. Relocation maps the virtual addresses used by a program to different physical addresses before the addresses are used to access memory. This relocation allows us to load ... | clipped_hennesy_Page_492_Chunk5849 |
penalty, dominated by the time to get the first word for typical page sizes, leads to several key decisions in designing virtual memory systems: ■ ■Pages should be large enough to try to amortize the high access time. Sizes from 4 KB to 16 KB are typical today. New desktop and server systems are being developed to supp... | clipped_hennesy_Page_493_Chunk5850 |
496 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Placing a Page and Finding It Again Because of the incredibly high penalty for a page fault, designers reduce page fault frequency by optimizing page placement. If we allow a virtual page to be mapped to any physical page, the operating system can then choose to... | clipped_hennesy_Page_494_Chunk5851 |
Figure 5.21 uses the page table register, the virtual address, and the indicated page table to show how the hardware can form a physical address. A valid bit is used in each page table entry, just as we did in a cache. If the bit is off, the page is not present in main memory and a page fault occurs. If the bit is on, ... | clipped_hennesy_Page_495_Chunk5852 |
498 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Because the page table contains a mapping for every possible virtual page, no tags are required. In cache terminology, the index that is used to access the page table consists of the full block address, which is the virtual page number. Page Faults If the vali... | clipped_hennesy_Page_496_Chunk5853 |
Implementing a completely accurate LRU scheme is too expensive, since it requires updating a data structure on every memory reference. Instead, most operating systems approximate LRU by keeping track of which pages have and which pages have not been recently used. To help the operating system estimate the LRU pages, so... | clipped_hennesy_Page_497_Chunk5854 |
500 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Elaboration: With a 32-bit virtual address, 4 KB pages, and 4 bytes per page table entry, we can compute the total page table size: Number of page table entries = 232 212 = 220 Size of page table = 220 page table entries × 22 bytes page table entry ... | clipped_hennesy_Page_498_Chunk5855 |
segments are again invisible to the user. Each entry in the segment table indicates whether any pages in that segment are allocated and, if so, points to a page table for that segment. Address translation happens by first looking in the segment table, using the highest-order bits of the address. If the segment addre... | clipped_hennesy_Page_499_Chunk5856 |
502 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Making Address Translation Fast: the TLB Since the page tables are stored in main memory, every memory access by a program can take at least twice as long: one memory access to obtain the physical address and a second access to get the data. The key to improving... | clipped_hennesy_Page_500_Chunk5857 |
we access the TLB instead of the page table on every reference, the TLB will need to include other status bits, such as the dirty and the reference bits. On every reference, we look up the virtual page number in the TLB. If we get a hit, the physical page number is used to form the address, and the corresponding refere... | clipped_hennesy_Page_501_Chunk5858 |
504 Chapter 5 Large and Fast: Exploiting Memory Hierarchy faults. As a result, many systems provide some support for randomly choosing an entry to replace. We’ll examine replacement schemes in a little more detail in Section 5.5. The Intrinsity FastMATH TLB To see these ideas in a real processor, let’s take a closer lo... | clipped_hennesy_Page_502_Chunk5859 |
FIGURE 5.24 The TLB and cache implement the process of going from a virtual address to a data item in the Intrinsity FastMATH. This figure shows the organization of the TLB and the data cache, assuming a 4 KB page size. This diagram focuses on a read; Figure 5.25 describes how to handle writes. Note that unlike Figure... | clipped_hennesy_Page_503_Chunk5860 |
506 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Yes Write access bit on? No Yes Cache hit? No Write data into cache, update the dirty bit, and put the data and the address into the write buffer Yes TLB hit? Virtual address TLB access Try to read data from cache No Yes Write? No Cache miss stall while read blo... | clipped_hennesy_Page_504_Chunk5861 |
Under the best of circumstances, a virtual address is translated by the TLB and sent to the cache where the appropriate data is found, retrieved, and sent back to the processor. In the worst case, a reference can miss in all three components of the memory hierarchy: the TLB, the page table, and the cache. The following... | clipped_hennesy_Page_505_Chunk5862 |
508 Chapter 5 Large and Fast: Exploiting Memory Hierarchy assuming a cache hit, must accommodate both a TLB access and a cache access; of course, these accesses can be pipelined. Alternatively, the processor can index the cache with an address that is completely or partially virtual. This is called a virtually address... | clipped_hennesy_Page_506_Chunk5863 |
To enable the operating system to implement protection in the virtual memory system, the hardware must provide at least the three basic capabilities summarized below. 1. Support at least two modes that indicate whether the running process is a user process or an operating system process, variously called a supervisor ... | clipped_hennesy_Page_507_Chunk5864 |
510 Chapter 5 Large and Fast: Exploiting Memory Hierarchy When processes want to share information in a limited way, the operating system must assist them, since accessing the information of another process requires changing the page table of the accessing process. The write access bit can be used to restrict the shari... | clipped_hennesy_Page_508_Chunk5865 |
How do we know which of these two circumstances has occurred? When we process the TLB miss, we will look for a page table entry to bring into the TLB. If the matching page table entry has a valid bit that is turned off, then the corresponding page is not in memory and we have a page fault, rather than just a TLB miss. ... | clipped_hennesy_Page_509_Chunk5866 |
512 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Between the time we begin executing the exception handler in the operating system and the time that the operating system has saved all the state of the process, the operating system is particularly vulnerable. For example, if another exception occurred when we ... | clipped_hennesy_Page_510_Chunk5867 |
Page fault exceptions for data accesses are difficult to implement properly in a processor because of a combination of three characteristics: 1. They occur in the middle of instructions, unlike instruction page faults. 2. The instruction cannot be completed before handling the exception. 3. After handling the exception... | clipped_hennesy_Page_511_Chunk5868 |
514 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Note that the TLB miss handler does not check to see if the page table entry is valid. Because the exception for TLB entry missing is much more frequent than a page fault, the operating system loads the TLB from the page table without exam ining the entry and r... | clipped_hennesy_Page_512_Chunk5869 |
Save state Save GPR addi $k1,$sp, -XCPSIZE # save space on stack for state sw $sp, XCT_SP($k1) # save $sp on stack sw $v0, XCT_V0($k1) # save $v0 on stack ... # save $v1, $ai, $si, $ti,... on stack sw $ra, XCT_RA($k1) # save $ra on stack Save hi, lo mfhi $v0 # copy Hi mflo $v1 # copy Lo sw $v0, XCT_HI($k1) # save Hi va... | clipped_hennesy_Page_513_Chunk5870 |
516 Chapter 5 Large and Fast: Exploiting Memory Hierarchy from the beginning, as we do for MIPS instructions. Instead, the instruction must be interrupted and later continued midstream in its execution. Resuming an instruction in the middle of its execution usually requires saving some special state, processing the exc... | clipped_hennesy_Page_514_Chunk5871 |
Although virtual memory was invented to enable a small memory to act as a large one, the performance difference between disk and memory means that if a program routinely accesses more virtual memory than it has physical memory, it will run very slowly. Such a program would be continuously swapping pages between memory... | clipped_hennesy_Page_515_Chunk5872 |
518 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.5 A Common Framework for Memory Hierarchies By now, you’ve recognized that the different types of memory hierarchies share a great deal in common. Although many of the aspects of memory hierarchies differ quantitatively, many of the policies and features tha... | clipped_hennesy_Page_516_Chunk5873 |
look at how much improvement is gained. Figure 5.30 shows the miss rates for several cache sizes as associativity varies from direct mapped to eight-way set asso ciative. The largest gains are obtained in going from direct mapped to two-way set associative, which yields between a 20% and 30% reduction in the miss rat... | clipped_hennesy_Page_517_Chunk5874 |
520 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Associativity Location method Comparisons required Direct mapped Index 1 Set associative Index the set, search among elements Degree of associativity Full Search all cache entries Size of the cache Separate lookup table 0 The choice among direct-mapped, set-asso... | clipped_hennesy_Page_518_Chunk5875 |
There are the two primary strategies for replacement in set-associative or fully associative caches: ■ ■Random: Candidate blocks are randomly selected, possibly using some hardware assistance. For example, MIPS supports random replacement for TLB misses. ■ ■Least recently used (LRU): The block replaced is the one that ... | clipped_hennesy_Page_519_Chunk5876 |
522 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Both write-back and write-through have their advantages. The key advantages of write-back are the following: ■ ■Individual words can be written by the processor at the rate that the cache, rather than the memory, can accept them. ■ ■Multiple writes within a bloc... | clipped_hennesy_Page_520_Chunk5877 |
5.5 A Common Framework for Memory Hierarchies 523 The Three Cs: An Intuitive Model for Understanding the Behavior of Memory Hierarchies In this section, we look at a model that provides insight into the sources of misses in a memory hierarchy and how the misses will be affected by changes in the hier archy. We will ex... | clipped_hennesy_Page_521_Chunk5878 |
524 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The challenge in designing memory hierarchies is that every change that potentially improves the miss rate can also negatively affect overall perfor mance, as Figure 5.32 summarizes. This combination of positive and nega tive effects is what makes the design ... | clipped_hennesy_Page_522_Chunk5879 |
Design change Effect on miss rate Possible negative performance effect Increase cache size Decreases capacity misses May increase access time Increase associativity Decreases miss rate due to conflict misses May increase access time Increase block size Decreases miss rate for a wide range of block sizes due to spatial ... | clipped_hennesy_Page_523_Chunk5880 |
526 Chapter 5 Large and Fast: Exploiting Memory Hierarchy System virtual machines present the illusion that the users have an entire computer to themselves, including a copy of the operating system. A single com puter runs multiple VMs and can support a number of different operating systems (OSes). On a conventional ... | clipped_hennesy_Page_524_Chunk5881 |
Requirements of a Virtual Machine Monitor What must a VM monitor do? It presents a software interface to guest software, it must isolate the state of guests from each other, and it must protect itself from guest software (including guest OSes). The qualitative requirements are: ■ ■Guest software should behave on a VM e... | clipped_hennesy_Page_525_Chunk5882 |
528 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Because the VMM must ensure that the guest system only interacts with virtual resources, a conventional guest OS runs as a user mode program on top of the VMM. Then, if a guest OS attempts to access or modify information related to hardware resources via a privi... | clipped_hennesy_Page_526_Chunk5883 |
Elaboration: In addition to virtualizing the instruction set, another challenge is virtualization of virtual memory, as each guest OS in every VM manages its own set of page tables. To make this work, the VMM separates the notions of real and physical memory (which are often treated synonymously), and makes real memor... | clipped_hennesy_Page_527_Chunk5884 |
530 Chapter 5 Large and Fast: Exploiting Memory Hierarchy ■ ■Direct-mapped cache ■ ■Write-back using write allocate ■ ■Block size is 4 words (16 bytes or 128 bits) ■ ■Cache size is 16 KB, so it holds 1024 blocks ■ ■32-bit byte addresses ■ ■The cache includes a valid bit and dirty bit per block From Section 5.2, we can ... | clipped_hennesy_Page_528_Chunk5885 |
Note that the interface to memory is not a fixed number of cycles. We assume a memory controller that will notify the cache via the Ready signal when the mem ory read or write is finished. Before describing the cache controller, we need to review finite-state machines, which allow us to control an operation that can t... | clipped_hennesy_Page_529_Chunk5886 |
532 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Elaboration: The style of finite-state machine in this book is called a Moore machines, after Edward Moore. Its identifying characteristic is that the output depends only on the current state. For a Moore machine, the box labeled combinational control logic can ... | clipped_hennesy_Page_530_Chunk5887 |
FSM for a Simple Cache Controller Figure 5.34 shows the four states of our simple cache controller: ■ ■Idle: This state waits for a valid read or write request from the processor, which moves the FSM to the Compare Tag state. ■ ■Compare Tag: As the name suggests, this state tests to see if the requested read or write i... | clipped_hennesy_Page_531_Chunk5888 |
534 Chapter 5 Large and Fast: Exploiting Memory Hierarchy ■ ■Write-Back: This state writes the 128-bit block to memory using the address composed from the tag and cache index. We remain in this state waiting for the Ready signal from memory. When the memory write is complete, the FSM goes to the Allocate state. ■ ■Allo... | clipped_hennesy_Page_532_Chunk5889 |
The second aspect, called consistency, determines when a written value will be returned by a read. Let’s look at coherence first. A memory system is coherent if 1. A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by... | clipped_hennesy_Page_533_Chunk5890 |
536 Chapter 5 Large and Fast: Exploiting Memory Hierarchy write done by P2 at some point. If we did not serialize the writes, it might be the case that some processor could see the write of P2 first and then see the write of P1, maintaining the value written by P1 indefinitely. The simplest way to avoid such difficulti... | clipped_hennesy_Page_534_Chunk5891 |
Figure 5.36 shows an example of an invalidation protocol for a snooping bus with write-back caches in action. To see how this protocol ensures coherence, consider a write followed by a read by another processor: since the write requires exclu sive access, any copy held by the reading processor must be invalidated (h... | clipped_hennesy_Page_535_Chunk5892 |
538 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Elaboration: Although the three properties on page 535 are sufficient to ensure coherence, the question of when a written value will be seen is also important. To see why, observe that we cannot require that a read of X in Figure 5.35 instantaneously sees the va... | clipped_hennesy_Page_536_Chunk5893 |
5.10 Real Stuff 539 FIGURE 5.37 An Intel Nehalem die processor photo with the components labeled. This 13.5 by 19.6 mm die has 731 million transistors. It contains four processors that each have private 32-KB instruction and 32-LKB instruction caches and a 512-KB L2 cache. The four cores share an 8-MB L3 cache. The two... | clipped_hennesy_Page_537_Chunk5894 |
540 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The Memory Hierarchies of the Nehalem and Opteron Figure 5.38 summarizes the address sizes and TLBs of the two processors. Note that the AMD Opteron X4 (Barcelona) has four TLBs and that the virtual and physical addresses do not have to match the word size. The ... | clipped_hennesy_Page_538_Chunk5895 |
Characteristic Intel Nehalem AMD Opteron X4 (Barcelona) L1 cache organization Split instruction and data caches Split instruction and data caches L1 cache size 32 KB each for instructions/data per core 64 KB each for instructions/data per core L1 cache associativity 4-way (I), 8-way (D) set associative 2-way set associ... | clipped_hennesy_Page_539_Chunk5896 |
542 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Both microprocessors prefetch instructions and have a built-in hardware prefetch mechanism for data accesses. They look at a pattern of data misses and use this information to try to predict the next address to start fetching the data before the miss occurs. Suc... | clipped_hennesy_Page_540_Chunk5897 |
The sophisticated memory hierarchies of these chips and the large fraction of the dies dedicated to caches and TLBs show the significant design effort expended to try to close the gap between processor cycle times and memory latency. Elaboration: The shared L3 cache of Opteron X4 does not always follow exclusion. Sinc... | clipped_hennesy_Page_541_Chunk5898 |
544 Chapter 5 Large and Fast: Exploiting Memory Hierarchy On the other hand, if address 36 is a word address, then it maps into block (36 mod 8) = 4. Make sure the problem clearly states the base of the address. In like fashion, we must account for the block size. Suppose we have a cache with 256 bytes and a block size... | clipped_hennesy_Page_542_Chunk5899 |
Pitfall: Having less set associativity for a shared cache than the number of cores or threads sharing that cache. Without extra care, a parallel program running on 2n processors or threads can easily allocate data structures to addresses that would map to the same set of a shared L2 cache. If the cache is at least 2n-w... | clipped_hennesy_Page_543_Chunk5900 |
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