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of a register until the instruction updating the register is no longer speculative. Other processors buffer the result, typically in a structure called a reorder buffer, and the actual update to the register file occurs later as part of the commit. Stores to memory must be buffered until commit time either in a store b... | Hennesey_Page_401_Chunk401 |
404 Chapter 4 The Processor 4.11 Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline Like most modern computers, x86 microprocessors employ sophisticated pipelining approaches. These processors, however, are still faced with the challenge of implementing the complex x86 instruction set, described in Chapter 2. Both AM... | Hennesey_Page_402_Chunk402 |
3. The X4 microarchitecture has many more registers than x86 requires. 4. X4 uses less than half the pipeline stages of the earlier Pentium 4 Prescott (see Figure 4.73). FIGURE 4.74 The microarchitecture of AMD Opteron X4. The extensive queues allow up to 106 RISC operations to be outstanding, including 24 integer ope... | Hennesey_Page_403_Chunk403 |
406 Chapter 4 The Processor The Opteron X4 combines a 12-stage pipeline and aggressive multiple issue to achieve high performance. By keeping the latencies for back-to-back operations low, the impact of data dependences is reduced. What are the most serious potential performance bottlenecks for programs running on thi... | Hennesey_Page_404_Chunk404 |
form suitable for hardware synthesis. It then provides a series of behavioral models in Verilog of the MIPS five-stage pipeline. The initial model ignores hazards, and additions to the model highlight the changes for forwarding, data hazards, and branch hazards. We then provide about a dozen illustrations using the sin... | Hennesey_Page_405_Chunk405 |
408 Chapter 4 The Processor addressing modes that require multiple memory accesses substantially complicate pipeline control and make it difficult to keep the pipeline flowing smoothly. Perhaps the best example is the DEC Alpha and the DEC NVAX. In comparable technology, the newer instruction set architecture of the ... | Hennesey_Page_406_Chunk406 |
of some of the inventions since the mid-1990s, resulting in a simplification of pipelines in the more recent versions of microarchitectures. To sustain the advances in processing performance via parallel processors, Amdahl’s law suggests that another part of the system will become the bottleneck. That bottleneck is th... | Hennesey_Page_407_Chunk407 |
410 Chapter 4 The Processor Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Laten- cies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruc... | Hennesey_Page_408_Chunk408 |
Improvement Latency Cost Benefit a. Add Multiplier to ALU +300ps for ALU +600 for ALU Lets us add MUL instruction. Allows us to execute 5% fewer instructions (MUL no longer emulated). b. Simpler Control +100ps for Control –400 for Control Control becomes slower but cheaper logic. 4.2.4 [10] <4.1> What is the clock cycl... | Hennesey_Page_409_Chunk409 |
412 Chapter 4 The Processor 4.3.4 [5] <4.1, 4.2> What is the latency of your implementation from 4.3.2? 4.3.5 [5] <4.1, 4.2> What is the cost of your implementation from 4.3.2? 4.3.6 [20] <4.1, 4.2> Change your design to minimize the latency, then to mini- mize the cost. Compare the cost and latency of these two optimi... | Hennesey_Page_410_Chunk410 |
4.4.6 [10] <4.2> What fraction of the cost was saved in your circuit from 4.4.3 by implementing these two control signals together instead of separately? Exercise 4.5 The goal of this exercise is to help you familiarize yourself with the design and operation of sequential logical circuits. Problems in this exercise ref... | Hennesey_Page_411_Chunk411 |
414 Chapter 4 The Processor 4.5.5 [10] <4.2> Compute the cost for the circuit you designed in 4.5.1, and then for the circuit you designed in 4.5.2. 4.5.6 [5] <4.2> Compare cost/performance ratios for the two circuits you designed in 4.5.1 and 4.5.2. For this problem, performance of a circuit is the inverse of the time... | Hennesey_Page_412_Chunk412 |
Exercise 4.7 In this exercise we examine how latencies of individual components of the data- path affect the clock cycle time of the entire datapath, and how these components are utilized by instructions. For problems in this exercise, assume the following latencies for logic blocks in the datapath: I-Mem Add Mux ALU R... | Hennesey_Page_413_Chunk413 |
416 Chapter 4 The Processor cross-talk faults is when a signal is connected to a wire that has a constant logical value (e.g., a power supply wire). In this case we have a stuck-at-0 or a stuck-at-1 fault, and the affected signal always has a logical value of 0 or 1, respectively. The following problems refer to the fo... | Hennesey_Page_414_Chunk414 |
4.8.6 [40] <4.3, 4.4> Using a single test described in 4.8.1, we can test for faults in several different signals, but typically not all of them. Describe a series of tests to look for this fault in all Mux outputs (every output bit from each of the five Muxes). Try to do this with as few single-instruction tests as po... | Hennesey_Page_415_Chunk415 |
418 Chapter 4 The Processor Exercise 4.10 In this exercise we examine how the clock cycle time of the processor affects the design of the control unit, and vice versa. Problems in this exercise assume that the logic blocks used to implement the datapath have the following latencies: I-Mem Add Mux ALU Regs D-Mem Sign-Ex... | Hennesey_Page_416_Chunk416 |
Exercise 4.11 In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: Instruction word a. 10101100011000100000000000010100 b. 00000000100000100000100000101010 4.11.1 [... | Hennesey_Page_417_Chunk417 |
420 Chapter 4 The Processor 4.12.1 [5] <4.5> What is the clock cycle time in a pipelined and non-pipelined processor? 4.12.2 [10] <4.5> What is the total latency of an LW instruction in a pipelined and non-pipelined processor? 4.12.3 [10] <4.5> If we can split one stage of the pipelined datapath into two new stages, ea... | Hennesey_Page_418_Chunk418 |
4.13.1 [10] <4.5> Indicate dependences and their type. 4.13.2 [10] <4.5> Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to eliminate them. 4.13.3 [10] <4.5> Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them. Without Forward... | Hennesey_Page_419_Chunk419 |
422 Chapter 4 The Processor only have one memory (for both instructions and data), there is a structural haz- ard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that a... | Hennesey_Page_420_Chunk420 |
computation is moved to the MEM stage? What is the speedup from this change? Assume that the latency of the EX stage is reduced by 20ps and the latency of the MEM stage is unchanged when branch outcome resolution is moved from EX to MEM. Exercise 4.15 In this exercise, we examine how the ISA affects pipeline design. Pr... | Hennesey_Page_421_Chunk421 |
424 Chapter 4 The Processor Exercise 4.16 The first three problems in this exercise refer to the following MIPS instruction: Instruction a. SW R16,–100(R6) b. OR R2,R1,R0 4.16.1 [5] <4.6> As this instruction executes, what is kept in each register located between two pipeline stages? 4.16.2 [5] <4.6> Which registers ne... | Hennesey_Page_422_Chunk422 |
Exercise 4.17 Problems in this exercise assume that instructions executed by a pipelined proces- sor are broken down as follows: ADD BEQ LW SW a. 40% 30% 25% 5% b. 60% 10% 20% 10% 4.17.1 [5] <4.6> Assuming there are no stalls and that 60% of all conditional branches are taken, in what percentage of clock cycles does th... | Hennesey_Page_423_Chunk423 |
426 Chapter 4 The Processor Exercise 4.18 The first three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4.51, and assume the following clock cycle time, ALU latency, and Mux latency: Instruction Clock Cycle Time ALU Latency Mux Latency a. LW R1,32(R2... | Hennesey_Page_424_Chunk424 |
have a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the instruction that consumes the result (1st instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register ... | Hennesey_Page_425_Chunk425 |
428 Chapter 4 The Processor hazards? Assume that the yet-to-be-invented time-travel circuitry adds 100ps to the latency of the full-forwarding EX stage. 4.19.6 [20] <4.7> Repeat 4.19.3 but this time determine which of the two options results in shorter time per instruction. Exercise 4.20 Problems in this exercise refe... | Hennesey_Page_426_Chunk426 |
4.20.6 [10] <4.7> For the design described in 4.20.5, add NOPs to this instruction sequence to ensure correct execution in spite of missing support for forwarding. Exercise 4.21 This exercise is intended to help you understand the relationship between forward- ing, hazard detection, and ISA design. Problems in this exe... | Hennesey_Page_427_Chunk427 |
430 Chapter 4 The Processor Exercise 4.22 This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exer- cise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full f... | Hennesey_Page_428_Chunk428 |
4.22.5 [10] <4.8> For the given code, what is the speedup achieved by moving branch execution into the ID stage? Explain your answer. In your speedup calcula- tion, assume that the additional comparison in the ID stage does not affect clock cycle time. 4.22.6 [10] <4.8> Using the first branch instruction in the given c... | Hennesey_Page_429_Chunk429 |
432 Chapter 4 The Processor 4.23.5 [10] <4.8> With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaced each branch instruction with two ALU instructions? Assume that correctly and incorrectly pre- dicted instructions have the same chance of bein... | Hennesey_Page_430_Chunk430 |
Exercise 4.25 This exercise explores how exception handling affects pipeline design. The first three problems in this exercise refer to the following two instructions: Instruction 1 Instruction 2 a. BNE R1,R2,Label LW R1,0(R1) b. JUMP Label SW R5,0(R1) 4.25.1 [5] <4.9> Which exceptions can each of these instructions tr... | Hennesey_Page_431_Chunk431 |
434 Chapter 4 The Processor Exercise 4.26 This exercise explores how exception handling affects control unit design and pro- cessor clock cycle time. The first three problems in this exercise refer to the follow- ing MIPS instruction that triggers an exception: Instruction Exception a. BNE R1,R2,Label Invalid target ad... | Hennesey_Page_432_Chunk432 |
Exercise 4.27 This exercise examines how exception handling interacts with branch and load/ store instructions. Problems in this exercise refer to the following branch instruc- tion and the corresponding delay slot instruction: Branch and Delay Slot a. BEQ R5,R4,Label SLT R5,R15,R4 b. BEQ R1,R0,Label LW R1,0(R1) 4.27.1... | Hennesey_Page_433_Chunk433 |
436 Chapter 4 The Processor value equal to WVAL is about to be written to address WADDR. How would you change the pipeline to implement this? How would this SW instruction be handled by your modified datapath? Exercise 4.28 In this exercise we compare the performance of 1-issue and 2-issue processors, tak- ing into acc... | Hennesey_Page_434_Chunk434 |
4.28.2, assume that the processor has perfect branch predictions, and that a 2-issue processor can fetch any two instructions in the same cycle. 4.28.6 [10] <4.10> Repeat 4.28.5, but this time assume that in the 2-issue pro- cessor one of the instructions to be executed in a cycle can be of any kind, and the other must... | Hennesey_Page_435_Chunk435 |
438 Chapter 4 The Processor iterations. You can use registers R10 through R20 when changing the code to elimi- nate dependences. 4.29.5 [20] <4.10> What is the speedup of using your code from 4.29.4 instead of the original code with a 2-issue static superscalar processor? Assume that the loop has many (e.g., 1,000,000)... | Hennesey_Page_436_Chunk436 |
conclusion can you draw about the importance of good branch prediction when the pipeline depth of the processor is increased? Exercise 4.31 Problems in this exercise refer to the following loop, which is given as x86 code and also as an MIPS translation of that code. You can assume that this loop executes many itera- t... | Hennesey_Page_437_Chunk437 |
440 Chapter 4 The Processor the operation, and WB writes the result to register or memory. The data memory has a read port (for instructions in the MRD stage) and a separate write port (for instructions in the WB stage). 4.31.3 [20] <4.11> What CPI would be achieved if the X86 version of this loop is executed on a proc... | Hennesey_Page_438_Chunk438 |
The remaining problems in this exercise assume the following pipeline depth and that the branch outcome is determined in the following pipeline stage (counting from stage 1): Pipeline Depth Branch Outcome Known in Stage a. 15 12 b. 30 20 4.32.2 [5] <4.11> In a 4-issue processor with these pipeline parameters, how many ... | Hennesey_Page_439_Chunk439 |
442 Chapter 4 The Processor 4.33.3 [10] <4.11> Repeat 4.33.2, but this time every executed instruction has a RAW data dependence to the instruction that executes right after it. You can assume that no stall cycles are needed, i.e., forwarding allows consecutive instruc- tions to execute in back-to-back cycles. For the ... | Hennesey_Page_440_Chunk440 |
4.34.3 [10] <4.13> What needs to be done to support undefined instruction exceptions in your datapath from 4.34.1? Note that the undefined instruction exception should be triggered whenever the processor encounters any other kind of instruction. The remaining two problems in this exercise also refer to this MIPS instru... | Hennesey_Page_441_Chunk441 |
444 Chapter 4 The Processor 4.35.3 [10] <4.8, 4.13> Repeat 4.35.2, but now assume that 10% of executed branches have all four delay slots filled with useful instruction, 20% have only three useful instructions in delay slots (the fourth delay slot is an NOP), 30% have only two useful instructions in delay slots, and 40... | Hennesey_Page_442_Chunk442 |
4.36.3 [20] <4.13> If we want to add this instruction to the MIPS ISA, discuss the changes to the pipeline (which stages, which structures in which stage) that are needed to directly (without micro-ops) support this instruction. 4.36.4 [10] <4.13> How often do you expect this instruction can be used? Do you think that ... | Hennesey_Page_443_Chunk443 |
446 Chapter 4 The Processor 4.37.1 [5] <4.3, 4.14> Which parts of the basic single-cycle datapath are used by all of these instructions? Which parts are the least utilized? 4.37.2 [10] <4.6, 4.14> What is the utilization for the read and for the write port of the data memory unit? 4.37.3 [10] <4.6, 4.14> Assume that we... | Hennesey_Page_444_Chunk444 |
4.38.2 [10] <4.6, 4.14> What is the worst-case MIPS instruction in terms of energy consumption, and what is the energy spent to execute it? 4.38.3 [10] <4.6, 4.14> If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LW instruction after... | Hennesey_Page_445_Chunk445 |
448 Chapter 4 The Processor to do its work within the given latency. Note that no energy is spent in the MEM stage during a cycle in which there is no memory access. Similarly, no energy is spent in the WB stage in a cycle in which there is no register write. In several of the following problems, we make assumptions ab... | Hennesey_Page_446_Chunk446 |
§4.10, page 403: 1. Both. 2. Both. 3. Software. 4. Hardware. 5. Hardware. 6. Hardware. 7. Both. 8. Hardware. 9. Both. §4.11, page 404: First two are false and last two are true. §4.12, page 4.12-3: Statements 1 and 3 are both true. §4.12, page 4.12-5: The best answer is 2 (see the Elaboration on page 371) 4.16 Exercise... | Hennesey_Page_447_Chunk447 |
5 Ideally one would desire an indefinitely large memory capacity such that any particular . . . word would be immediately available. . . . We are . . . forced to recognize the possibility of constructing a hierarchy of memories, each of which has greater capacity than the preceding but which is less quickly accessible... | Hennesey_Page_448_Chunk448 |
5.7 Using a Finite-State Machine to Control a Simple Cache 529 5.8 Parallelism and Memory Hierarchies: Cache Coherence 534 5.9 Advanced Material: Implementing Cache Controllers 538 5.10 Real Stuff: the AMD Opteron X4 (Barcelona) and Intel Nehalem Memory Hierarchies 539 5.11 Fallacies and Pitfalls 543 5.12 Concluding R... | Hennesey_Page_449_Chunk449 |
452 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.1 Introduction From the earliest days of computing, programmers have wanted unlimited amounts of fast memory. The topics in this chapter aid programmers by creating that illusion. Before we look at creating the illusion, let’s consider a simple analogy that il... | Hennesey_Page_450_Chunk450 |
you brought out the book on early English computers to find out about the EDSAC, you also noticed that there was another book shelved next to it about early mechanical computers, so you also brought back that book and, later on, found something useful in that book. Libraries put books on the same topic together on the ... | Hennesey_Page_451_Chunk451 |
454 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The data is similarly hierarchical: a level closer to the processor is generally a subset of any level further away, and all the data is stored at the lowest level. By analogy, the books on your desk form a subset of the library you are working in, which is in t... | Hennesey_Page_452_Chunk452 |
Since performance is the major reason for having a memory hierarchy, the time to service hits and misses is important. Hit time is the time to access the upper level of the memory hierarchy, which includes the time needed to determine whether the access is a hit or a miss (that is, the time needed to look through the b... | Hennesey_Page_453_Chunk453 |
456 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Programs exhibit both temporal locality, the tendency to reuse recently accessed data items, and spatial locality, the tendency to reference data items that are close to other recently accessed items. Memory hierarchies take advantage of temporal locality by kee... | Hennesey_Page_454_Chunk454 |
Which of the following statements are generally true? 1. Caches take advantage of temporal locality. 2. On a read, the value returned depends on which blocks are in the cache. 3. Most of the cost of the memory hierarchy is at the highest level. 4. Most of the capacity of the memory hierarchy is at the lowest level. 5.2... | Hennesey_Page_455_Chunk455 |
458 Chapter 5 Large and Fast: Exploiting Memory Hierarchy If the number of entries in the cache is a power of 2, then modulo can be computed simply by using the low-order log2 (cache size in blocks) bits of the address. Thus, an 8-block cache uses the three lowest bits (8 = 23) of the block address. For example, Figur... | Hennesey_Page_456_Chunk456 |
For the rest of this section, we will focus on explaining how a cache deals with reads. In general, handling reads is a little simpler than handling writes, since reads do not have to change the contents of the cache. After seeing the basics of how reads work and how cache misses can be handled, we’ll examine the cache... | Hennesey_Page_457_Chunk457 |
460 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Decimal address of reference Binary address of reference Hit or miss in cache Assigned cache block (where found or placed) 22 10110two miss (5.6b) (10110two mod 8) = 110two 26 11010two miss (5.6c) (11010two mod 8) = 010two 22 10110two hit (10110two mod 8) = 110t... | Hennesey_Page_458_Chunk458 |
Index V Tag Data Index V Tag Data 000 N 000 N 001 N 001 N 010 N 010 N 011 N 011 N 100 N 100 N 101 N 101 N 110 N 110 Y 10two Memory (10110two) 111 N 111 N a. The initial state of the cache after power-on b. After handling a miss of address (10110two) Index V Tag Data Index V Tag Data 000 N 000 Y 10two Memory (10000two) ... | Hennesey_Page_459_Chunk459 |
462 Chapter 5 Large and Fast: Exploiting Memory Hierarchy ■ ■32-bit byte addresses ■ ■A direct-mapped cache ■ ■The cache size is 2n blocks, so n bits are used for the index ■ ■The block size is 2m words (2m+2 bytes), so m bits are used for the word within the block, and two bits are used for the byte part of the addres... | Hennesey_Page_460_Chunk460 |
The total number of bits in a direct-mapped cache is 2n × (block size + tag size + valid field size). Since the block size is 2m words (2m+5 bits), and we need 1 bit for the valid field, the number of bits in such a cache is 2n × (2m × 32 + (32 - n - m - 2) + 1) = 2n × (2m × 32 + 31 - n - m). Although this is the actua... | Hennesey_Page_461_Chunk461 |
464 Chapter 5 Large and Fast: Exploiting Memory Hierarchy where the address of the block is Byte address Bytes per block Notice that this block address is the block containing all addresses between Byte address Bytes per block × Bytes per block and Byte address Bytes per block × Bytes p... | Hennesey_Page_462_Chunk462 |
Elaboration: Although it is hard to do anything about the longer latency component of the miss penalty for large blocks, we may be able to hide some of the transfer time so that the miss penalty is effectively smaller. The simplest method for doing this, called early restart, is simply to resume execution as soon as t... | Hennesey_Page_463_Chunk463 |
466 Chapter 5 Large and Fast: Exploiting Memory Hierarchy from memory (or, as we shall see, a lower-level cache). If the cache reports a hit, the computer continues using the data as if nothing happened. Modifying the control of a processor to handle a hit is trivial; misses, however, require some extra work. The cach... | Hennesey_Page_464_Chunk464 |
to keep the main memory and the cache consistent is always to write the data into both the memory and the cache. This scheme is called write-through. The other key aspect of writes is what occurs on a write miss. We first fetch the words of the block from memory. After the block is fetched and placed into the cache, we... | Hennesey_Page_465_Chunk465 |
468 Chapter 5 Large and Fast: Exploiting Memory Hierarchy that sometimes programs write entire blocks of data, such as when the operating system zeros a page of memory. In such cases, the fetch associated with the initial write miss may be unnecessary. Some computers allow the write allocation policy to be changed on ... | Hennesey_Page_466_Chunk466 |
each cache. (Remember that we need to update the instruction cache when a miss occurs.) Thus, the steps for a read request to either cache are as follows: 1. Send the address to the appropriate cache. The address comes either from the PC (for an instruction) or from the ALU (for data). 2. If the cache signals hit, the ... | Hennesey_Page_467_Chunk467 |
470 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 3. If the cache signals miss, we send the address to the main memory. When the memory returns with the data, we write it into the cache and then read it to fulfill the request. For writes, the Intrinsity FastMATH offers both write-through and write-back, leaving... | Hennesey_Page_468_Chunk468 |
Designing the Memory System to Support Caches Cache misses are satisfied from main memory, which is constructed from DRAMs. In Section 5.1, we saw that the primary emphasis with DRAMs is on cost and density. Although it is difficult to reduce the latency to fetch the first word from memory, we can reduce the miss penal... | Hennesey_Page_469_Chunk469 |
472 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Instead of making the entire path between the memory and cache wider, the memory chips can be organized in banks to read or write multiple words in one access time rather than reading or writing a single word each time. Each bank could be one word wide so that t... | Hennesey_Page_470_Chunk470 |
Banks are also valuable on writes. Each bank can write independently, quadrupling the write bandwidth and leading to fewer stalls in a write-through cache. As we will see, an alternative strategy for writes makes interleaving even more attractive. Because of the ubiquity of caches and the desire for larger block sizes... | Hennesey_Page_471_Chunk471 |
474 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Year introduced Chip size $ per GB Total access time to a new row/column Column access time to existing row 1980 64 Kbit $1,500,000 250 ns 150 ns 1983 256 Kbit $500,000 185 ns 100 ns 1985 1 Mbit $200,000 135 ns 40 ns 1989 4 Mbit $50,000 110 ns 40 ns 1992 16 Mbit... | Hennesey_Page_472_Chunk472 |
The speed of the memory system affects the designer’s decision on the size of the cache block. Which of the following cache designer guidelines are generally valid? 1. The shorter the memory latency, the smaller the cache block 2. The shorter the memory latency, the larger the cache block 3. The higher the memory bandw... | Hennesey_Page_473_Chunk473 |
476 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The read-stall cycles can be defined in terms of the number of read accesses per program, the miss penalty in clock cycles for a read, and the read miss rate: Read-stall cycles = Reads Program × Read miss rate × Read miss penalty Writes are more complicate... | Hennesey_Page_474_Chunk474 |
Calculating Cache Performance Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 100 cycles for all misses, determine how much faster a pro cessor would run with a perfect cache that never missed.... | Hennesey_Page_475_Chunk475 |
478 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 4.44 1 = 4.44 times faster. The amount of execution time spent on memory stalls would have risen from 3.44 5.44 = 63% to 3.44 4.44 = 77%. Similarly, increasing the clock rate without changing the memory system also increases the performance los... | Hennesey_Page_476_Chunk476 |
The average memory access time per instruction is AMAT = Time for a hit + Miss rate × Miss penalty = 1 + 0.05 × 20 = 2 clock cycles or 2 ns. The next subsection discusses alternative cache organizations that decrease miss rate but may sometimes increase hit time; additional examples appear in Section 5.11, Fallacies an... | Hennesey_Page_477_Chunk477 |
480 Chapter 5 Large and Fast: Exploiting Memory Hierarchy placement and fully associative placement: a block is directly mapped into a set, and then all the blocks in the set are searched for a match. For example, Figure 5.13 shows where block 12 may be placed in a cache with eight blocks total, according to the three... | Hennesey_Page_478_Chunk478 |
We can also think of all block placement strategies as a variation on set associativity. Figure 5.14 shows the possible associativity structures for an eight- block cache. A direct-mapped cache is simply a one-way set-associative cache: each cache entry holds one block and each set has one element. A fully associative ... | Hennesey_Page_479_Chunk479 |
482 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Misses and Associativity in Caches Assume there are three small caches, each consisting of four one-word blocks. One cache is fully associative, a second is two-way set-associative, and the third is direct-mapped. Find the number of misses for each cache organiz... | Hennesey_Page_480_Chunk480 |
Because we have a choice of which entry in a set to replace on a miss, we need a replacement rule. Set-associative caches usually replace the least recently used block within a set; that is, the block that was used furthest in the past is replaced. (We will discuss other replacement rules in more detail shortly.) Using... | Hennesey_Page_481_Chunk481 |
484 Chapter 5 Large and Fast: Exploiting Memory Hierarchy How much of a reduction in the miss rate is achieved by associativity? Figure 5.15 shows the improvement for a 64 KB data cache with a 16-word block, and associa tivity ranging from direct mapped to eight-way. Going from one-way to two- way associativity decrea... | Hennesey_Page_482_Chunk482 |
In a direct-mapped cache, only a single comparator is needed, because the entry can be in only one block, and we access the cache simply by indexing. Figure 5.17 shows that in a four-way set-associative cache, four comparators are needed, together with a 4‑to-1 multiplexor to choose among the four potential members of ... | Hennesey_Page_483_Chunk483 |
486 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Size of Tags versus Set Associativity Increasing associativity requires more comparators and more tag bits per cache block. Assuming a cache of 4K blocks, a 4-word block size, and a 32‑bit address, find the total number of sets and the total number of tag bits f... | Hennesey_Page_484_Chunk484 |
Since there are 16 (= 24) bytes per block, a 32-bit address yields 32 - 4 = 28 bits to be used for index and tag. The direct-mapped cache has the same number of sets as blocks, and hence 12 bits of index, since log2(4K) = 12; hence, the total number is (28 - 12) × 4K = 16 × 4K = 64 K tag bits. Each degree of associativ... | Hennesey_Page_485_Chunk485 |
488 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The effective CPI with one level of caching is given by Total CPI = Base CPI + Memory-stall cycles per instruction For the processor with one level of caching, Total CPI = 1.0 + Memory-stall cycles per instruction = 1.0 + 2% × 400 = 9 With two levels of caching,... | Hennesey_Page_486_Chunk486 |
The effect of these changes on the two caches can be seen by comparing each cache to the optimal design for a single level of cache. In comparison to a single- level cache, the primary cache of a multilevel cache is often smaller. Furthermore, the primary cache may use a smaller block size, to go with the smaller cach... | Hennesey_Page_487_Chunk487 |
490 Chapter 5 Large and Fast: Exploiting Memory Hierarchy FIGURE 5.18 Comparing Quicksort and Radix Sort by (a) instructions executed per item sorted, (b) time per item sorted, and (c) cache misses per item sorted. This data is from a paper by LaMarca and Ladner [1996]. Although the numbers would change for newer compu... | Hennesey_Page_488_Chunk488 |
There is no general way to calculate overlapped miss latency, so evaluations of memory hierarchies for out-of-order processors inevitably require simulation of the processor and memory hierarchy. Only by seeing the execution of the processor during each miss can we see if the processor stalls waiting for data or simpl... | Hennesey_Page_489_Chunk489 |
492 Chapter 5 Large and Fast: Exploiting Memory Hierarchy large. The secondary cache, which is often ten or more times larger than the primary cache, handles many accesses that miss in the primary cache. In such cases, the miss penalty is that of the access time to the secondary cache (typically < 10 processor cycles)... | Hennesey_Page_490_Chunk490 |
both code and data. Calls between procedures in different modules would lead to overlaying of one module with another. As you can well imagine, this responsibility was a substantial burden on pro grammers. Virtual memory, which was invented to relieve programmers of this difficulty, automatically manages the two level... | Hennesey_Page_491_Chunk491 |
494 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Virtual memory also simplifies loading the program for execution by providing relocation. Relocation maps the virtual addresses used by a program to different physical addresses before the addresses are used to access memory. This relocation allows us to load ... | Hennesey_Page_492_Chunk492 |
penalty, dominated by the time to get the first word for typical page sizes, leads to several key decisions in designing virtual memory systems: ■ ■Pages should be large enough to try to amortize the high access time. Sizes from 4 KB to 16 KB are typical today. New desktop and server systems are being developed to supp... | Hennesey_Page_493_Chunk493 |
496 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Placing a Page and Finding It Again Because of the incredibly high penalty for a page fault, designers reduce page fault frequency by optimizing page placement. If we allow a virtual page to be mapped to any physical page, the operating system can then choose to... | Hennesey_Page_494_Chunk494 |
Figure 5.21 uses the page table register, the virtual address, and the indicated page table to show how the hardware can form a physical address. A valid bit is used in each page table entry, just as we did in a cache. If the bit is off, the page is not present in main memory and a page fault occurs. If the bit is on, ... | Hennesey_Page_495_Chunk495 |
498 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Because the page table contains a mapping for every possible virtual page, no tags are required. In cache terminology, the index that is used to access the page table consists of the full block address, which is the virtual page number. Page Faults If the vali... | Hennesey_Page_496_Chunk496 |
Implementing a completely accurate LRU scheme is too expensive, since it requires updating a data structure on every memory reference. Instead, most operating systems approximate LRU by keeping track of which pages have and which pages have not been recently used. To help the operating system estimate the LRU pages, so... | Hennesey_Page_497_Chunk497 |
500 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Elaboration: With a 32-bit virtual address, 4 KB pages, and 4 bytes per page table entry, we can compute the total page table size: Number of page table entries = 232 212 = 220 Size of page table = 220 page table entries × 22 bytes page table entry ... | Hennesey_Page_498_Chunk498 |
segments are again invisible to the user. Each entry in the segment table indicates whether any pages in that segment are allocated and, if so, points to a page table for that segment. Address translation happens by first looking in the segment table, using the highest-order bits of the address. If the segment addre... | Hennesey_Page_499_Chunk499 |
502 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Making Address Translation Fast: the TLB Since the page tables are stored in main memory, every memory access by a program can take at least twice as long: one memory access to obtain the physical address and a second access to get the data. The key to improving... | Hennesey_Page_500_Chunk500 |
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