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we access the TLB instead of the page table on every reference, the TLB will need to include other status bits, such as the dirty and the reference bits. On every reference, we look up the virtual page number in the TLB. If we get a hit, the physical page number is used to form the address, and the corresponding refere... | Hennesey_Page_501_Chunk501 |
504 Chapter 5 Large and Fast: Exploiting Memory Hierarchy faults. As a result, many systems provide some support for randomly choosing an entry to replace. We’ll examine replacement schemes in a little more detail in Section 5.5. The Intrinsity FastMATH TLB To see these ideas in a real processor, let’s take a closer lo... | Hennesey_Page_502_Chunk502 |
FIGURE 5.24 The TLB and cache implement the process of going from a virtual address to a data item in the Intrinsity FastMATH. This figure shows the organization of the TLB and the data cache, assuming a 4 KB page size. This diagram focuses on a read; Figure 5.25 describes how to handle writes. Note that unlike Figure... | Hennesey_Page_503_Chunk503 |
506 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Yes Write access bit on? No Yes Cache hit? No Write data into cache, update the dirty bit, and put the data and the address into the write buffer Yes TLB hit? Virtual address TLB access Try to read data from cache No Yes Write? No Cache miss stall while read blo... | Hennesey_Page_504_Chunk504 |
Under the best of circumstances, a virtual address is translated by the TLB and sent to the cache where the appropriate data is found, retrieved, and sent back to the processor. In the worst case, a reference can miss in all three components of the memory hierarchy: the TLB, the page table, and the cache. The following... | Hennesey_Page_505_Chunk505 |
508 Chapter 5 Large and Fast: Exploiting Memory Hierarchy assuming a cache hit, must accommodate both a TLB access and a cache access; of course, these accesses can be pipelined. Alternatively, the processor can index the cache with an address that is completely or partially virtual. This is called a virtually address... | Hennesey_Page_506_Chunk506 |
To enable the operating system to implement protection in the virtual memory system, the hardware must provide at least the three basic capabilities summarized below. 1. Support at least two modes that indicate whether the running process is a user process or an operating system process, variously called a supervisor ... | Hennesey_Page_507_Chunk507 |
510 Chapter 5 Large and Fast: Exploiting Memory Hierarchy When processes want to share information in a limited way, the operating system must assist them, since accessing the information of another process requires changing the page table of the accessing process. The write access bit can be used to restrict the shari... | Hennesey_Page_508_Chunk508 |
How do we know which of these two circumstances has occurred? When we process the TLB miss, we will look for a page table entry to bring into the TLB. If the matching page table entry has a valid bit that is turned off, then the corresponding page is not in memory and we have a page fault, rather than just a TLB miss. ... | Hennesey_Page_509_Chunk509 |
512 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Between the time we begin executing the exception handler in the operating system and the time that the operating system has saved all the state of the process, the operating system is particularly vulnerable. For example, if another exception occurred when we ... | Hennesey_Page_510_Chunk510 |
Page fault exceptions for data accesses are difficult to implement properly in a processor because of a combination of three characteristics: 1. They occur in the middle of instructions, unlike instruction page faults. 2. The instruction cannot be completed before handling the exception. 3. After handling the exception... | Hennesey_Page_511_Chunk511 |
514 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Note that the TLB miss handler does not check to see if the page table entry is valid. Because the exception for TLB entry missing is much more frequent than a page fault, the operating system loads the TLB from the page table without exam ining the entry and r... | Hennesey_Page_512_Chunk512 |
Save state Save GPR addi $k1,$sp, -XCPSIZE # save space on stack for state sw $sp, XCT_SP($k1) # save $sp on stack sw $v0, XCT_V0($k1) # save $v0 on stack ... # save $v1, $ai, $si, $ti,... on stack sw $ra, XCT_RA($k1) # save $ra on stack Save hi, lo mfhi $v0 # copy Hi mflo $v1 # copy Lo sw $v0, XCT_HI($k1) # save Hi va... | Hennesey_Page_513_Chunk513 |
516 Chapter 5 Large and Fast: Exploiting Memory Hierarchy from the beginning, as we do for MIPS instructions. Instead, the instruction must be interrupted and later continued midstream in its execution. Resuming an instruction in the middle of its execution usually requires saving some special state, processing the exc... | Hennesey_Page_514_Chunk514 |
Although virtual memory was invented to enable a small memory to act as a large one, the performance difference between disk and memory means that if a program routinely accesses more virtual memory than it has physical memory, it will run very slowly. Such a program would be continuously swapping pages between memory... | Hennesey_Page_515_Chunk515 |
518 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.5 A Common Framework for Memory Hierarchies By now, you’ve recognized that the different types of memory hierarchies share a great deal in common. Although many of the aspects of memory hierarchies differ quantitatively, many of the policies and features tha... | Hennesey_Page_516_Chunk516 |
look at how much improvement is gained. Figure 5.30 shows the miss rates for several cache sizes as associativity varies from direct mapped to eight-way set asso ciative. The largest gains are obtained in going from direct mapped to two-way set associative, which yields between a 20% and 30% reduction in the miss rat... | Hennesey_Page_517_Chunk517 |
520 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Associativity Location method Comparisons required Direct mapped Index 1 Set associative Index the set, search among elements Degree of associativity Full Search all cache entries Size of the cache Separate lookup table 0 The choice among direct-mapped, set-asso... | Hennesey_Page_518_Chunk518 |
There are the two primary strategies for replacement in set-associative or fully associative caches: ■ ■Random: Candidate blocks are randomly selected, possibly using some hardware assistance. For example, MIPS supports random replacement for TLB misses. ■ ■Least recently used (LRU): The block replaced is the one that ... | Hennesey_Page_519_Chunk519 |
522 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Both write-back and write-through have their advantages. The key advantages of write-back are the following: ■ ■Individual words can be written by the processor at the rate that the cache, rather than the memory, can accept them. ■ ■Multiple writes within a bloc... | Hennesey_Page_520_Chunk520 |
5.5 A Common Framework for Memory Hierarchies 523 The Three Cs: An Intuitive Model for Understanding the Behavior of Memory Hierarchies In this section, we look at a model that provides insight into the sources of misses in a memory hierarchy and how the misses will be affected by changes in the hier archy. We will ex... | Hennesey_Page_521_Chunk521 |
524 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The challenge in designing memory hierarchies is that every change that potentially improves the miss rate can also negatively affect overall perfor mance, as Figure 5.32 summarizes. This combination of positive and nega tive effects is what makes the design ... | Hennesey_Page_522_Chunk522 |
Design change Effect on miss rate Possible negative performance effect Increase cache size Decreases capacity misses May increase access time Increase associativity Decreases miss rate due to conflict misses May increase access time Increase block size Decreases miss rate for a wide range of block sizes due to spatial ... | Hennesey_Page_523_Chunk523 |
526 Chapter 5 Large and Fast: Exploiting Memory Hierarchy System virtual machines present the illusion that the users have an entire computer to themselves, including a copy of the operating system. A single com puter runs multiple VMs and can support a number of different operating systems (OSes). On a conventional ... | Hennesey_Page_524_Chunk524 |
Requirements of a Virtual Machine Monitor What must a VM monitor do? It presents a software interface to guest software, it must isolate the state of guests from each other, and it must protect itself from guest software (including guest OSes). The qualitative requirements are: ■ ■Guest software should behave on a VM e... | Hennesey_Page_525_Chunk525 |
528 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Because the VMM must ensure that the guest system only interacts with virtual resources, a conventional guest OS runs as a user mode program on top of the VMM. Then, if a guest OS attempts to access or modify information related to hardware resources via a privi... | Hennesey_Page_526_Chunk526 |
Elaboration: In addition to virtualizing the instruction set, another challenge is virtualization of virtual memory, as each guest OS in every VM manages its own set of page tables. To make this work, the VMM separates the notions of real and physical memory (which are often treated synonymously), and makes real memor... | Hennesey_Page_527_Chunk527 |
530 Chapter 5 Large and Fast: Exploiting Memory Hierarchy ■ ■Direct-mapped cache ■ ■Write-back using write allocate ■ ■Block size is 4 words (16 bytes or 128 bits) ■ ■Cache size is 16 KB, so it holds 1024 blocks ■ ■32-bit byte addresses ■ ■The cache includes a valid bit and dirty bit per block From Section 5.2, we can ... | Hennesey_Page_528_Chunk528 |
Note that the interface to memory is not a fixed number of cycles. We assume a memory controller that will notify the cache via the Ready signal when the mem ory read or write is finished. Before describing the cache controller, we need to review finite-state machines, which allow us to control an operation that can t... | Hennesey_Page_529_Chunk529 |
532 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Elaboration: The style of finite-state machine in this book is called a Moore machines, after Edward Moore. Its identifying characteristic is that the output depends only on the current state. For a Moore machine, the box labeled combinational control logic can ... | Hennesey_Page_530_Chunk530 |
FSM for a Simple Cache Controller Figure 5.34 shows the four states of our simple cache controller: ■ ■Idle: This state waits for a valid read or write request from the processor, which moves the FSM to the Compare Tag state. ■ ■Compare Tag: As the name suggests, this state tests to see if the requested read or write i... | Hennesey_Page_531_Chunk531 |
534 Chapter 5 Large and Fast: Exploiting Memory Hierarchy ■ ■Write-Back: This state writes the 128-bit block to memory using the address composed from the tag and cache index. We remain in this state waiting for the Ready signal from memory. When the memory write is complete, the FSM goes to the Allocate state. ■ ■Allo... | Hennesey_Page_532_Chunk532 |
The second aspect, called consistency, determines when a written value will be returned by a read. Let’s look at coherence first. A memory system is coherent if 1. A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by... | Hennesey_Page_533_Chunk533 |
536 Chapter 5 Large and Fast: Exploiting Memory Hierarchy write done by P2 at some point. If we did not serialize the writes, it might be the case that some processor could see the write of P2 first and then see the write of P1, maintaining the value written by P1 indefinitely. The simplest way to avoid such difficulti... | Hennesey_Page_534_Chunk534 |
Figure 5.36 shows an example of an invalidation protocol for a snooping bus with write-back caches in action. To see how this protocol ensures coherence, consider a write followed by a read by another processor: since the write requires exclu sive access, any copy held by the reading processor must be invalidated (h... | Hennesey_Page_535_Chunk535 |
538 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Elaboration: Although the three properties on page 535 are sufficient to ensure coherence, the question of when a written value will be seen is also important. To see why, observe that we cannot require that a read of X in Figure 5.35 instantaneously sees the va... | Hennesey_Page_536_Chunk536 |
5.10 Real Stuff 539 FIGURE 5.37 An Intel Nehalem die processor photo with the components labeled. This 13.5 by 19.6 mm die has 731 million transistors. It contains four processors that each have private 32-KB instruction and 32-LKB instruction caches and a 512-KB L2 cache. The four cores share an 8-MB L3 cache. The two... | Hennesey_Page_537_Chunk537 |
540 Chapter 5 Large and Fast: Exploiting Memory Hierarchy The Memory Hierarchies of the Nehalem and Opteron Figure 5.38 summarizes the address sizes and TLBs of the two processors. Note that the AMD Opteron X4 (Barcelona) has four TLBs and that the virtual and physical addresses do not have to match the word size. The ... | Hennesey_Page_538_Chunk538 |
Characteristic Intel Nehalem AMD Opteron X4 (Barcelona) L1 cache organization Split instruction and data caches Split instruction and data caches L1 cache size 32 KB each for instructions/data per core 64 KB each for instructions/data per core L1 cache associativity 4-way (I), 8-way (D) set associative 2-way set associ... | Hennesey_Page_539_Chunk539 |
542 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Both microprocessors prefetch instructions and have a built-in hardware prefetch mechanism for data accesses. They look at a pattern of data misses and use this information to try to predict the next address to start fetching the data before the miss occurs. Suc... | Hennesey_Page_540_Chunk540 |
The sophisticated memory hierarchies of these chips and the large fraction of the dies dedicated to caches and TLBs show the significant design effort expended to try to close the gap between processor cycle times and memory latency. Elaboration: The shared L3 cache of Opteron X4 does not always follow exclusion. Sinc... | Hennesey_Page_541_Chunk541 |
544 Chapter 5 Large and Fast: Exploiting Memory Hierarchy On the other hand, if address 36 is a word address, then it maps into block (36 mod 8) = 4. Make sure the problem clearly states the base of the address. In like fashion, we must account for the block size. Suppose we have a cache with 256 bytes and a block size... | Hennesey_Page_542_Chunk542 |
Pitfall: Having less set associativity for a shared cache than the number of cores or threads sharing that cache. Without extra care, a parallel program running on 2n processors or threads can easily allocate data structures to addresses that would map to the same set of a shared L2 cache. If the cache is at least 2n-w... | Hennesey_Page_543_Chunk543 |
546 Chapter 5 Large and Fast: Exploiting Memory Hierarchy were privileged. This laissez-faire attitude causes problems for VMMs for all of these architectures, including the x86, which we use here as an example. Figure 5.41 describes the 18 instructions that cause problems for virtualization [Robin and Irvine, 2000]. T... | Hennesey_Page_544_Chunk544 |
technique is called paravirtualization, and the open source Xen VMM is a good example. The Xen VMM provides a guest OS with a virtual machine abstraction that uses only the easy-to-virtualize parts of the physical x86 hardware on which the VMM runs. 5.12 Concluding Remarks The difficulty of building a memory system to ... | Hennesey_Page_545_Chunk545 |
548 Chapter 5 Large and Fast: Exploiting Memory Hierarchy As we will see in Chapter 7, memory systems are a central design issue for parallel processors. The growing importance of the memory hierarchy in determining system performance means that this important area will continue to be a focus of both designers and rese... | Hennesey_Page_546_Chunk546 |
5.1.4 [10] <5.1, 5.2> Communication bandwidth and server processing band width are two important factors to consider when designing a memory hierarchy. How can the bandwidths be improved? What is the cost of improving them? 5.1.5 [5] <5.1, 5.8> Now consider multiple clients simultaneously accessing the server. Will su... | Hennesey_Page_547_Chunk547 |
550 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.2.4 [10] <5.1> How many 16-byte cache lines are needed to store all 32-bit matrix elements being referenced? 5.2.5 [5] <5.1> References to which variables exhibit temporal locality? 5.2.6 [5] <5.1> References to which variables exhibit spatial locality? Exerci... | Hennesey_Page_548_Chunk548 |
of the closest direct-mapped cache with 16-word blocks of equal size or greater. Explain why the second cache, despite its larger data size, might provide slower performance than the first cache. 5.3.5 [20] <5.2, 5.3> Generate a series of read requests that have a lower miss rate on a 2 KB 2-way set associative cache t... | Hennesey_Page_549_Chunk549 |
552 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.4.6 [20] <5.2> List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. Exercise 5.5 Recall that we have two write policies and write allocation policies, and their com binations can be implemented either in L1 o... | Hennesey_Page_550_Chunk550 |
Exercise 5.6 Media applications that play audio or video files are part of a class of workloads called “streaming” workloads; i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KB working set sequentially with the following address stream: 0, 2... | Hennesey_Page_551_Chunk551 |
554 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Exercise 5.7 In this exercise, we will look at the different ways capacity affects overall perfor mance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions.... | Hennesey_Page_552_Chunk552 |
Exercise 5.8 This exercise examines the impact of different cache designs, specifically compar ing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3. 5.8.1 [10] <5.3> Using the references from Exercise 5.3, show the final c... | Hennesey_Page_553_Chunk553 |
556 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.8.5 [10] <5.3> It is possible to have an even greater cache hierarchy than two levels. Given the processor above with a second level, direct-mapped cache, a designer wants to add a third level cache that takes 50 cycles to access and will reduce the global mis... | Hennesey_Page_554_Chunk554 |
Keeping “frequently used” (or “hot”) pages in DRAM can save disk accesses, but how do we determine the exact meaning of “frequently used” for a given system? Data engineers use the cost ratio between DRAM and disk access to quantify the reuse time threshold for hot pages. The cost of a disk access is $Disk /accesses_pe... | Hennesey_Page_555_Chunk555 |
558 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Page table Valid Physical Page or in Disk 1 5 0 Disk 0 Disk 1 6 1 9 1 11 0 Disk 1 4 0 Disk 0 Disk 1 3 1 12 5.10.1 [10] <5.4> Given the address stream in the table, and the initial TLB and page table states shown above, show the final state of the system. Also li... | Hennesey_Page_556_Chunk556 |
5.10.5 [10] <5.4> Given the parameters in the table above, calculate the total page table size for a system running 5 applications that utilize half of the memory available, given a two level page table approach with 256 entries. Assume each entry of the main page table is 6 bytes. Calculate the minimum and maximum amo... | Hennesey_Page_557_Chunk557 |
560 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.11.4 [5] <5.4> Under what scenarios would entry 2’s valid bit be set to zero? 5.11.5 [5] <5.4> What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB? 5.11.6 [5] <5.4> What happens when an... | Hennesey_Page_558_Chunk558 |
5.12.4 [10] <5.3, 5.5> Which address should be evicted at each replacement to maximize the number of hits? How many hits does this address sequence exhibit if you follow this “optimal” policy? 5.12.5 [10] <5.3, 5.5> Describe why it is difficult to implement a cache replacement policy that is optimal for all address seq... | Hennesey_Page_559_Chunk559 |
562 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.13.4 [10] <5.6> For a benchmark with native execution CPI of 1, what are the CPI numbers if using shadow page tables vs. NPT (assuming only page table virtualization overhead)? 5.13.5 [10] <5.6> What techniques can be used to reduce page table shadowing induce... | Hennesey_Page_560_Chunk560 |
5.14.4 [20] <5.6> Section 5.6 discusses virtualization under the assumption that the virtualized system is running the same ISA as the underlying hardware. However, one possible use of virtualization is to emulate non-native ISAs. An example of this is QEMU, which emulates a variety of ISAs such as MIPS, SPARC, and Pow... | Hennesey_Page_561_Chunk561 |
564 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.16.1 [15] <5.8> List the possible values of the given cache block for a correct cache coherence protocol implementation. List at least one more possible value of the block if the protocol doesn’t ensure cache coherency. 5.16.2 [15] <5.8> For a snooping protoco... | Hennesey_Page_562_Chunk562 |
The next table shows hit latencies. Private Cache Shared Cache Memory a. 5 20 180 b. 10 50 120 5.17.1 [15] <5.10> Which cache design is better for each of these benchmarks? Use data to support your conclusion. 5.17.2 [15] <5.10> Shared cache latency increases with the CMP size. Choose the best design if the shared cach... | Hennesey_Page_563_Chunk563 |
566 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Some processing functions on a log are: a. topK_sourceIP (int hour); b. browser_histogram (int srcIP); // browsers of a given IP 5.18.1 [5] <5.11> Which fields in a log entry will be accessed for the given log processing function? Assuming 64-byte cache blocks a... | Hennesey_Page_564_Chunk564 |
§5.1, page 457: 1 and 4. (3 is false because the cost of the memory hierarchy varies per computer, but in 2008 the highest cost is usually the DRAM.) §5.2, page 475: 1 and 4: A lower miss penalty can enable smaller blocks, since you don’t have that much latency to amortize, yet higher memory bandwidth usually leads to ... | Hennesey_Page_565_Chunk565 |
6 Combining bandwidth and storage . . . enables swift and reliable access to the ever-expanding troves of content on the proliferating disks and . . . repositories of the Internet. George Gilder The End Is Drawing Nigh, 2000 Storage and Other I/O Topics 6.1 Introduction 570 6.2 Dependability, Reliability, and Availabi... | Hennesey_Page_566_Chunk566 |
6.7 I/O Performance Measures: Examples from Disk and File Systems 596 6.8 Designing an I/O System 598 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 599 6.10 Real Stuff: Sun Fire x4150 Server 606 6.11 Advanced Topics: Networks 612 6.12 Fallacies and Pitfalls 613 6.13 Concluding Remarks 617 6.14 Historic... | Hennesey_Page_567_Chunk567 |
570 Chapter 6 Storage and Other I/O Topics 6.1 Introduction Although users can get frustrated if their computer hangs and must be rebooted, they become apoplectic if their storage system crashes and they lose information. Thus, the standard for dependability is much higher for storage than for computa tion. Networks a... | Hennesey_Page_568_Chunk568 |
with others throughput is crucial. Furthermore, performance depends on many aspects of the system: the device characteristics, the connection between the device and the rest of the system, the memory hierarchy, and the operating system. All of the components, from the individual I/O devices to the processor to the sys... | Hennesey_Page_569_Chunk569 |
572 Chapter 6 Storage and Other I/O Topics In Chapter 1, we briefly discussed four important I/O devices: mice, graphics displays, disks, and networks. In this chapter we go into much more depth on storage and related items. On the CD, there is an advanced topics section on networks, which are well covered in other bo... | Hennesey_Page_570_Chunk570 |
6.2 Dependability, Reliability, and Availability Users crave dependable storage, but how do you define it? In the computer indus try, it is harder than looking it up in the dictionary. After considerable debate, the following is considered the standard definition [Laprie, 1985]: Computer system dependability is the qu... | Hennesey_Page_571_Chunk571 |
574 Chapter 6 Storage and Other I/O Topics Note that reliability and availability are actually quantifiable measures, rather than just synonyms for dependability. What is the cause of failures? Figure 6.3 summarizes many papers that have col lected data on reasons for computer systems and telecommunications systems to... | Hennesey_Page_572_Chunk572 |
Which of the following are true about dependability? 1. If a system is up, then all its components are accomplishing their expected service. 2. Availability is a quantitative measure of the percentage of time a system is accomplishing its expected service. 3. Reliability is a quantitative measure of continuous service ... | Hennesey_Page_573_Chunk573 |
576 Chapter 6 Storage and Other I/O Topics Disk manufacturers report minimum seek time, maximum seek time, and average seek time in their manuals. The first two are easy to measure, but the aver age is open to wide interpretation because it depends on the seek distance. The industry has decided to calculate average se... | Hennesey_Page_574_Chunk574 |
Disk Read Time What is the average time to read or write a 512-byte sector for a typical disk rotating at 15,000 RPM? The advertised average seek time is 4 ms, the transfer rate is 100 MB/sec, and the controller overhead is 0.2 ms. Assume that the disk is idle so that there is no waiting time. Average disk access time ... | Hennesey_Page_575_Chunk575 |
578 Chapter 6 Storage and Other I/O Topics FIGURE 6.4 Six magnetic disks, varying in diameter from 14 inches down to 1.8 inches. The pictured disks were introduced over more than 15 years ago and hence are not intended to be represen tative of the best capacity of modern disks of these diameters. This photograph does,... | Hennesey_Page_576_Chunk576 |
Characteristics Seagate ST33000655SS Seagate ST31000340NS Seagate ST973451SS Seagate ST9160821AS Disk diameter (inches) 3.50 3.50 2.50 2.50 Formatted data capacity (GB) 147 1000 73 160 Number of disk surfaces (heads) 2 4 2 2 Rotation speed (RPM) 15,000 7200 15,000 5400 Internal disk cache size (MB) 16 32 16 8 External ... | Hennesey_Page_577_Chunk577 |
580 Chapter 6 Storage and Other I/O Topics 6.4 Flash Storage. Many have tried to invent a technology to replace disks, and many have failed: CCD memory, bubble memory, and holographic memory were all found wanting. By the time a new technology would ship, disks made advances as predicted earlier, costs dropped accordi... | Hennesey_Page_578_Chunk578 |
diameter hard disks are disappearing from some embedded markets. For example, in 2008 the Apple iPod Shuffle MP3 player sold for $50 and held 1 GB, while the smallest disk holds 4 GB and sells for more than the whole MP3 player. Flash memory is a type of electrically erasable programmable read-only mem ory (EEPROM). ... | Hennesey_Page_579_Chunk579 |
582 Chapter 6 Storage and Other I/O Topics gigabyte continues to decline, it will be interesting to see whether the higher performance and energy efficiency of flash memory will yield opportunities in the desktop and server markets as well. Which of the following are true about flash memory? 1. Like DRAM, flash is a se... | Hennesey_Page_580_Chunk580 |
need to support a range of devices with widely varying latencies and data transfer rates also makes bus design challenging. As it became difficult to run many parallel wires at high speed due to clock skew and reflection (see Appendix C), the industry transitioned from parallel shared buses to high-speed serial point-... | Hennesey_Page_581_Chunk581 |
584 Chapter 6 Storage and Other I/O Topics clock skew or synchronization problems. All the examples in Figure 6.8 are asynchronous. To coordinate the transmission of data between sender and receiver, an asyn chronous bus uses a handshaking protocol. A handshaking protocol consists of a series of steps in which the se... | Hennesey_Page_582_Chunk582 |
include the north bridge inside the microprocessor, and the south bridge chip of the Intel 975 includes a RAID controller (see Section 6.9). These I/O interconnects provide electrical connectivity among I/O devices, processors, and memory, and also define the lowest-level protocol for commu nication. Above this basic ... | Hennesey_Page_583_Chunk583 |
586 Chapter 6 Storage and Other I/O Topics 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System A bus or network protocol defines how a word or block of data should be commu nicated on a set of wires. This still leaves several other tasks that must be performed to actually cause data to be tran... | Hennesey_Page_584_Chunk584 |
As we will see in answering these questions, the operating system plays a major role in handling I/O, acting as the interface between the hardware and the program that requests I/O. The responsibilities of the operating system arise from three characteristics of I/O systems: 1. Multiple programs using the processor sh... | Hennesey_Page_585_Chunk585 |
588 Chapter 6 Storage and Other I/O Topics 2. The device must be able to notify the OS when the I/O device has completed an operation or has encountered an error. For example, when a disk completes a seek, it will notify the OS. 3. Data must be transferred between memory and an I/O device. For example, the block being... | Hennesey_Page_586_Chunk586 |
Elaboration: The alternative to memory-mapped I/O is to use dedicated I/O instructions in the processor. These I/O instructions can specify both the device number and the command word (or the location of the command word in memory). The processor communicates the device address via a set of wires normally included as ... | Hennesey_Page_587_Chunk587 |
590 Chapter 6 Storage and Other I/O Topics 2. In addition to the fact that an I/O interrupt has occurred, we would like to convey further information, such as the identity of the device generating the interrupt. Furthermore, the interrupts represent devices that may have dif ferent priorities and whose interrupt reque... | Hennesey_Page_588_Chunk588 |
3. Save the interrupt mask field of the Status register. 4. Change the interrupt mask field to disable all interrupts of equal or lower priority. 5. Save the processor state needed to handle the interrupt. 6. To allow higher-priority interrupts, set the interrupt enable bit of the Cause register to 1. 7. Call the appro... | Hennesey_Page_589_Chunk589 |
592 Chapter 6 Storage and Other I/O Topics Elaboration: The two least significant bits of the pending interrupt and interrupt mask fields are for software interrupts, which are lower priority. These are typically used by higher-priority interrupts to leave work for lower-priority interrupts to do once the immedi- ate r... | Hennesey_Page_590_Chunk590 |
becomes the master and directs the reads or writes between itself and memory. There are three steps in a DMA transfer: 1. The processor sets up the DMA by supplying the identity of the device, the operation to perform on the device, the memory address that is the source or destination of the data to be transferred, an... | Hennesey_Page_591_Chunk591 |
594 Chapter 6 Storage and Other I/O Topics Direct Memory Access and the Memory System When DMA is incorporated into an I/O system, the relationship between the memory system and processor changes. Without DMA, all accesses to the memory system come from the processor and thus proceed through address translation and ... | Hennesey_Page_592_Chunk592 |
In a system with virtual memory, should DMA work with virtual addresses or physical addresses? The obvious problem with virtual addresses is that the DMA unit will need to translate the virtual addresses to physical addresses. The major problem with the use of a physical address in a DMA transfer is that the transfer c... | Hennesey_Page_593_Chunk593 |
596 Chapter 6 Storage and Other I/O Topics 6.7 I/O Performance Measures: Examples from Disk and File Systems How should we compare I/O systems? This is a complex question, because I/O performance depends on many aspects of the system, and different applications stress different aspects of the I/O system. Furthermore, ... | Hennesey_Page_594_Chunk594 |
as well as gracefully handling certain types of failures. These applications are extremely critical and cost-sensitive. For example, banks normally use TP systems because they are concerned about a range of characteristics. These include making sure transactions aren’t lost, handling transactions quickly, and minimizin... | Hennesey_Page_595_Chunk595 |
598 Chapter 6 Storage and Other I/O Topics Are the following true or false? Unlike processor benchmarks, I/O benchmarks 1. concentrate on throughput rather than latency 2. can require that the data set scale in size or number of users to achieve per formance milestones 3. often report cost performance 6.8 Designing an... | Hennesey_Page_596_Chunk596 |
The easiest way to understand this methodology is with an example. We’ll do a simple analysis of the I/O system of the Sun Fire x4150 server in Section 6.10 to show how this methodology works. 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks Amdahl’s law in Chapter 1 reminds us that neglecting I/O in thi... | Hennesey_Page_597_Chunk597 |
600 Chapter 6 Storage and Other I/O Topics The improvement in CPU performance after six years is 90 11 = 8 However, the improvement in elapsed time is only 100 21 = 4.7 and the I/O time has increased from 10% to 47% of the elapsed time. Hence, the parallel revolution needs to come to I/O as well as to compu... | Hennesey_Page_598_Chunk598 |
Figure 6.12 shows the evolution and example cost in number of extra check disks. To keep track of the evolution, the authors numbered the stages of RAID, and they are still used today. No Redundancy (RAID 0) Simply spreading data over multiple disks, called striping, automatically forces accesses to several disks. Stri... | Hennesey_Page_599_Chunk599 |
602 Chapter 6 Storage and Other I/O Topics Mirroring (RAID 1) This traditional scheme for tolerating disk failure, called mirroring or shadowing, uses twice as many disks as does RAID 0. Whenever data is written to one disk, that data is also written to a redundant disk, so that there are always two copies of the infor... | Hennesey_Page_600_Chunk600 |
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