text stringlengths 41 20k |
|---|
/*
# Ilkka Hautala
# ithauta@ee.oulu.fi
# Center for Machine Vision and Signal Analysis (CMVS)
# University of Oulu, Finland
SystemC implementation of Memory arbiter
Based on VHDL implementation of avalon mem arbiter authored by AK (TCE project)
*/
#ifndef TTA_MEM_ARBITER_H_
#define TTA_MEM_ARBITER_H_
#i... |
#include <iostream>
#include <systemc.h>
#define NORTH 0
#define EAST 1
#define SOUTH 2
#define WEST 3
#define LOCAL 4
class Arbitro
{
public:
sc_uint<32> portaDestino;
int buffercircular[5];
Arbitro();
~Arbitro();
void setPrioridade();
int checkPrioridade();
}; |
/*
HardwareSerial.h - Hardware serial library for Wiring
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of ... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef _TLM_ROUTER_H__
#define _TLM_ROUTER_H__
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/peq_with_cb_and_phase.... |
/**
* Author: Anubhav Tomar
*
* Library Definition
**/
#ifndef LIB_H
#define LIB_H
#include<systemc.h>
#include <map>
struct point {
double x;
double y;
};
std::map<int , point> leftPointMap ();
std::map<int , point> rightPointMap ();
std::map<int , int> northMap ();
std::map<int , int> southtMap ();
s... |
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#include <systemc.h>
#include "hwcore/dsp/imfilter.h"
#include "hwcore/tb/scfileio.h"
#define TB_IMFILTER_W W_WIDTH
SC_MODULE(filter_load)
{
SC_MODULE_CLK_RESET_SIGNAL;
sc_out<sc_fixed<W_WIDTH,P_DATA> > Wout[3*3];
SC... |
/*
* Copyright (c) 2015, University of Kaiserslautern
* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistri... |
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* ... |
#ifndef __SC_VPI_MODULE_H__
#define __SC_VPI_MODULE_H__
#include <systemc.h>
#include <assert.h>
#include <vpi_user.h>
static int sc_vpi_module_value_change(p_cb_data cb_data);
#define sc_vpi_module_read_output_int(obj, name) \
{ \
s_vpi_value value_s; \
s_vpi_ti... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
******... |
/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
******... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
#ifndef __COMMON_H__
#define __COMMON_H__
#include <list>
#include <sstream>
#include "Request.h"
#include "systemc.h"
std::ostream& operator<<(std::ostream &os, const ramulator::Request::Type &type);
// This macro is used to locate the code position.
#define HERE do {std::cout <<"File: " << __FILE__ << " Line: " <<... |
/* Copyright 2017 Columbia University, SLD Group */
//
// globals.h - Robert Margelli
// This file several defines and constants: number of registers, data width, opcodes etc.
//
#ifndef GLOBALS_H
#define GLOBALS_H
#include "systemc.h"
// Miscellanous sizes. Most of these can be changed to obtain new architectures.... |
#ifndef SDRAM_IO_H
#define SDRAM_IO_H
#include <systemc.h>
//----------------------------------------------------------------
// Interface (master)
//----------------------------------------------------------------
class sdram_io_master
{
public:
// Members
sc_uint <1> CLK;
sc_uint <1> CKE;
sc_uint <1... |
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* ... |
----------------------
//// Run the index-th ANN k time on random input and return the number of error
////-----------------------------------------------------------------------------
//int annTest(int index, int k)
//{
// int x0; int x1; int y;
// double x[2];
// double xor_ex;
// int error = 0;
//
// if ( annCheck(i... |
/*
* cache.h
*
* Created on: Sep 16, 2014
* Author: lloyd23
*/
#ifndef CACHE_H_
#define CACHE_H_
//------------------ Cache ------------------//
// cache management on host and accelerator
/* NOTE: if invalidate is used on non-cache aligned and sized allocations, */
/* it can corrupt the heap. */
#ifdef ... |
#include <systemc.h>
#include "interfaces.cpp"
#include "fila.h"
#include "flit.h"
/* portas/sinais feitos de acordo com a imagem do roteador SoCIN.
* Dúvidas: como posso acionar os outros métodos via SC_METHOD? Pq a lista de sensibilidade está ok, mas não está acionando o método de leitura do buffer (apenas adição)
... |
// Copyright (c) 2011-2024 Columbia University, System Level Design Group
// SPDX-License-Identifier: MIT
#ifndef __ESP_UTILS_HPP__
#define __ESP_UTILS_HPP__
#include "esp_data.hpp"
#include "esp_systemc.hpp"
#define ESP_REPORT_INFO(...) \
fprintf(stderr, "Info: %s: ", sc_object::basename()); \
fprintf(stderr, ... |
#ifndef __ROM_3840_32_H__
#define __ROM_3840_32_H__
#include <fstream>
#include <systemc.h>
class rom_3840x32_t : public sc_module
{
public:
sc_in<uint32_t> addr1;
sc_in<uint32_t> addr2;
sc_out<uint32_t> data1;
sc_out<uint32_t> data2;
uint32_t data[3840];
void port1() {
while(true) {
... |
#ifndef TOP_HPP
#define TOP_HPP
#include <systemc.h>
#include "scheduler.hpp"
#include "processing_engine.hpp"
#include "verbose.hpp"
#define CORE_BIND(NAME, INDEX) \
NAME.clk(clk); \
NAME.reset(reset); \
NAME.from_scheduler_i... |
#define SC_INCLUDE_FX
#include <systemc.h>
#include "MAC.h"
#include <iostream>
#include <vector>
using namespace std;
SC_MODULE(ALEXNET)
{
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_... |
/**
* Author: Anubhav Tomar
*
* Library Definition
**/
#ifndef LIB_H
#define LIB_H
#include<systemc.h>
#include <map>
#define TOTAL_TX_PACKETS 30
#define TUPLES_PER_PACKETS 20
struct roiTuple {
int roi;
int startTime;
int endTime;
roiTuple();
roiTuple(int _r , int _s , int _e) : roi(_r) , s... |
//-----Module definition for Quantize hardware block -------------
//-----You must modify this file as indicated by TODO comments----
#include "systemc.h"
#include "Block.h"
#define INT_PULSE_WIDTH sc_time(1, SC_US)
//module
SC_MODULE(HW_Quant)
{
public:
//constructor
SC_CTOR(HW_Quant) {
//instantiate the Quant... |
#include "systemc.h"
#include "run_mode.h"
#include<iostream>
#include<fstream>
using namespace std;
SC_MODULE(lenet)
{
sc_in_clk clock;
sc_in<bool> reset;
sc_out<bool> rom_rd;
sc_out<bool> ram_wr;
sc_out<sc_uint<16> > rom_addr;
sc_out<sc_uint<16> > ram_addr;
sc_in<TYPE > rom_data_in; // TYPE
sc_in<TYPE >... |
/*
* Copyright (c) 2019 Sekhar Bhattacharya
*
* SPDX-License-Identifier: MIT
*/
#include <systemc.h>
#include "utils.h"
template <int sram_size>
SC_MODULE(Sram) {
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we... |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the ... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
#ifndef IEEE_H
#define IEEE_H
#include "systemc.h"
//-----------------------------------------------------------------------------
// IEEE floating-point type
//-----------------------------------------------------------------------------
template<int E, int F>
struct fp_t {
static constexpr int ebits = E; // ex... |
#ifndef SDRAM_IO_H
#define SDRAM_IO_H
#include <systemc.h>
//----------------------------------------------------------------
// Interface (master)
//----------------------------------------------------------------
class sdram_io_master
{
public:
// Members
sc_uint <1> CLK;
sc_uint <1> CKE;
sc_uint <1... |
#include <systemc.h>
#include "interfaces.cpp"
#include "fila.h"
#include "flit.h"
/* portas/sinais feitos de acordo com a imagem do roteador SoCIN.
* Dúvidas: como posso acionar os outros métodos via SC_METHOD? Pq a lista de sensibilidade está ok, mas não está acionando o método de leitura do buffer (apenas adição)
... |
/******************************************************************************
* *
* Copyright (C) 2023 MachineWare GmbH *
* All Rights Reserved *
... |
#ifndef _TB_QVM_H_
#define _TB_QVM_H_
#include <systemc.h>
#include <iomanip>
#include <iostream>
#include "global_json.h"
#include "logger_wrapper.h"
#include "q_data_type.h"
#include "quma_tb_base.h"
#include "qvm.h"
using namespace sc_core;
using namespace sc_dt;
namespace cactus {
using sc_core::sc_in;
using s... |
#ifndef xtea_RTL_TESTBENCH_H
#define xtea_RTL_TESTBENCH_H
#include <systemc.h>
SC_MODULE(xtea_RTL_testbench) {
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _dct_HH_
#define... |
sc_signal< sc_logic > buf_2d_out_t_empty_n;
sc_signal< sc_logic > ap_sync_done;
sc_signal< sc_logic > ap_sync_ready;
sc_signal< sc_logic > read_data_U0_start_full_n;
sc_signal< sc_logic > read_data_U0_start_write;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_start_full_n;
sc_signal< sc_log... |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gran... |
// **************************************************************************************
// User-defined memory manager, which maintains a pool of transactions
// From TLM Duolos tutorials
// **************************************************************************************
#ifndef TRANSACTION_MEMORY_MANAGER_CPP
#... |
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
... |
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the ... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _memcachedPipeline_mer... |
/*
* fetch.h
*
* Created on: 4 de mai de 2017
* Author: drcfts
*/
#ifndef FETCH_H_
#define FETCH_H_
#include <systemc.h>
#include "shared.h"
#include "mem_if.h"
#include "breg_if.h"
#define RASTREIA_PC
//Criar uma classe memoria que implementa interface com metodos de leitura
//e escrita para ser acessad... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pqcrystals_dilit... |
1> > add_ln85_fu_3774_p2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter0;
sc_signal< sc_lv<3> > select_ln86_1_fu_3800_p3;
sc_signal< sc_lv<3> > select_ln86_1_reg_5207;
sc_signal< sc_lv<10> > z_vec_coeffs_addr_5_reg_5217;
sc_signal< sc_lv<9> > i_45_fu_3836_p2;
sc_signal< sc_lv<1> > icmp_ln53_fu_38... |
nal< sc_lv<10> > grp_pqcrystals_dilithium_19_fu_1841_a_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_a_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_a_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_19_fu_1841_a_d0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilith... |
_lv<8> > add_ln543_fu_2688_p2;
sc_signal< sc_lv<6> > or_ln544_fu_2699_p2;
sc_signal< sc_lv<8> > zext_ln544_fu_2704_p1;
sc_signal< sc_lv<8> > add_ln544_fu_2708_p2;
sc_signal< sc_lv<6> > or_ln545_fu_2719_p2;
sc_signal< sc_lv<8> > zext_ln545_fu_2724_p1;
sc_signal< sc_lv<8> > add_ln545_fu_2728_p2;
... |
_23;
static const sc_lv<7> ap_const_lv7_24;
static const sc_lv<7> ap_const_lv7_25;
static const sc_lv<7> ap_const_lv7_26;
static const sc_lv<7> ap_const_lv7_27;
static const sc_lv<3> ap_const_lv3_7;
static const sc_lv<64> ap_const_lv64_58;
static const sc_lv<4> ap_const_lv4_B;
static con... |
oid thread_or_ln546_1_fu_3599_p2();
void thread_or_ln546_fu_2739_p2();
void thread_or_ln547_1_fu_3609_p2();
void thread_or_ln547_fu_2759_p2();
void thread_or_ln548_1_fu_3619_p2();
void thread_or_ln548_fu_2779_p2();
void thread_or_ln69_1_fu_4277_p2();
void thread_or_ln69_fu_4271_p2();
voi... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _contact_discove... |
m_state286;
sc_signal< sc_logic > ap_CS_fsm_state287;
sc_signal< sc_logic > ap_CS_fsm_state288;
sc_signal< sc_logic > ap_CS_fsm_state289;
sc_signal< sc_logic > ap_CS_fsm_state290;
sc_signal< sc_logic > ap_CS_fsm_state291;
sc_signal< sc_logic > ap_CS_fsm_state292;
sc_signal< sc_logic > ap_CS_... |
ap_CS_fsm_state243;
sc_signal< sc_logic > ap_CS_fsm_state245;
sc_signal< sc_logic > ap_CS_fsm_state247;
sc_signal< sc_logic > ap_CS_fsm_state249;
sc_signal< sc_logic > ap_CS_fsm_state251;
sc_signal< sc_logic > ap_CS_fsm_state253;
sc_signal< sc_logic > ap_CS_fsm_state255;
sc_signal< sc_logic ... |
te307;
static const sc_lv<568> ap_ST_fsm_state308;
static const sc_lv<568> ap_ST_fsm_state309;
static const sc_lv<568> ap_ST_fsm_state310;
static const sc_lv<568> ap_ST_fsm_state311;
static const sc_lv<568> ap_ST_fsm_state312;
static const sc_lv<568> ap_ST_fsm_state313;
static const sc_lv<56... |
2> ap_const_lv32_123;
static const sc_lv<32> ap_const_lv32_124;
static const sc_lv<32> ap_const_lv32_125;
static const sc_lv<32> ap_const_lv32_126;
static const sc_lv<32> ap_const_lv32_127;
static const sc_lv<32> ap_const_lv32_128;
static const sc_lv<32> ap_const_lv32_129;
static const sc_lv... |
const sc_lv<8> ap_const_lv8_26;
static const sc_lv<8> ap_const_lv8_27;
static const sc_lv<8> ap_const_lv8_28;
static const sc_lv<8> ap_const_lv8_29;
static const sc_lv<8> ap_const_lv8_2A;
static const sc_lv<8> ap_const_lv8_2B;
static const sc_lv<8> ap_const_lv8_2C;
static const sc_lv<8> ap_... |
();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state150();
void thread_ap_CS_fsm_state151();
void thread_ap_CS_fsm_state152();
void thread_ap_CS_fsm_state153();
void thread_ap_CS_fsm_state154();
void thread_ap_CS_fsm_state155();
void thread_ap_CS_fsm_state156();
void thre... |
hread_database_index_1_fu_6447_p2();
void thread_database_index_cast_fu_6438_p1();
void thread_database_size_out_1_ack_in();
void thread_database_size_out_1_data_in();
void thread_database_size_out_1_vld_in();
void thread_database_we0();
void thread_error_out_1_ack_in();
void thread_error_ou... |
/*
* Copyright 2021 Chair of EDA, Technical University of Munich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required b... |
/*******************************************************************************
* gndemux.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple gnmuxin for GN logic use in testbenches.
**************... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Mat2AXIvideo_HH_... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _acorn128_dec_onebyte_... |
/*
* Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
* University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apac... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
#ifndef RGB2GRAY_TLM_HPP
#define RGB2GRAY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "rgb2gray_pv_mod... |
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Add_Rectangle_HH... |
/**
* @file lzss_enc_dut.h
* @brief
*
* @par Copyright
* (C) 2012 Taichi Ishitani All Rights Reserved.
*
* @author Taichi Ishitani
*
* @date 0.0.00 2012/07/07 T. Ishitani coding start
*/
#ifndef LZSS_ENC_DUT_H_
#define LZSS_ENC_DUT_H_
#include <string>
#include <stdint.h>
#include "system... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _CvtColor_1_HH_
... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _blobsCount_HH_
... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
#include "systemc.h"
#include "system.h"
#include "checksum.h"
#include "application.h"
#include "noc_adapter_if.h"
#ifndef NOC_TILE_H
#define NOC_TILE_H
// =================================
// ===== TILE TYPES AND STATES =====
// =================================
/** Command structure. */
struct noc_cmd_t {
u... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: arp@poshtkohi.info
Website: http://www.poshtkohi.info
*/
#ifndef __pe_work_stealing_scheduler_sc__h__
#define __pe_work_stealing_scheduler_sc__h__
#include <systemc.h>
#include "globals.h"
... |
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include "hwcore/hw/singleportram.h"
#include "hwcore/pipes/data_types.h"
#include <systemc.h>
template <int W = 16, bool stream_while_write = false, int L = (((18 * 1024... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _dct_2d_HH_
#def... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pqcrystals_dilit... |
#ifndef blocking_IFS
#define blocking_IFS
#include "systemc.h"
template<typename T>
class blocking_in_if : virtual public sc_interface
{
public:
virtual void read(T & out) = 0;
virtual bool nb_read(T & out) = 0;
};
template<typename T>
class blocking_out_if : virtual public sc_interface
{
publ... |
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
******... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the ... |
// The last statement disables all reports to the global context (uvm_top)
// having the ID "TransDump". Note that it is currently not possible to
// set filters for reports for several contexts at once using wildcards. Also,
// the hierarchical separator for SC may be configurable in your simulator, and
// thus coul... |
----------------------------------------------------
// Function: uvmc_set_config_int
//
// Set an integral configuration value
//
void uvmc_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
// Function: uvmc_set_config_string
//
// Set ... |
//****************************************************************************************
// MIT License
//****************************************************************************************
// Copyright (c) 2012-2020 University of Bremen, Germany.
// Copyright (c) 2015-2020 DFKI GmbH Bremen, Germany.
// Cop... |
#include <systemc.h>
SC_MODULE( or_gate )
{
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
};
int sc_main( int argc, char * argv[... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
/*
* Copyright (c) 2010 TIMA Laboratory
*
* This file is part of Rabbits.
*
* Rabbits is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any la... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _FBTA64_theta_HH... |
read_alloc_addr_ap_vld();
void thread_alloc_addr_blk_n();
void thread_alloc_cmd_ap_ack();
void thread_alloc_cmd_blk_n();
void thread_alloc_free_target_ap_ack();
void thread_alloc_free_target_blk_n();
void thread_alloc_size_ap_ack();
void thread_alloc_size_blk_n();
void thread_ans_V_2_fu_... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Detecteur_HH_
#d... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _foo_HH_
#define... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pqcrystals_dilit... |
/* Copyright (c) 2015 Convey Computer Corporation
*
* This file is part of the OpenHT toolset located at:
*
* https://github.com/TonyBrewer/OpenHT
*
* Use and distribution licensed under the BSD 3-clause license.
* See the LICENSE file for the complete license text.
*/
#pragma once
#include <stdio.h>
#include ... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.