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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
/*
* Copyright EPFL 2021
* Rafael Medina Morillas
*
* Description of a generic 3 port (2 read, 1 write) register file.
*
*/
#ifndef RF_THREEPORT_H_
#define RF_THREEPORT_H_
#include "systemc.h"
template<class T, uint size>
class rf_threeport: public sc_module {
public:
sc_in_clk clk;
sc_in<bool> rst;
... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
#include <systemc.h>
SC_MODULE( or_gate )
{
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
};
int sc_main( int argc, char * argv[... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _dct_HH_
#define... |
sc_signal< sc_logic > buf_2d_out_t_empty_n;
sc_signal< sc_logic > ap_sync_done;
sc_signal< sc_logic > ap_sync_ready;
sc_signal< sc_logic > read_data_U0_start_full_n;
sc_signal< sc_logic > read_data_U0_start_write;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_start_full_n;
sc_signal< sc_log... |
/******************************************************
* Architecture Module header file. *
* This file is automatically generated by ArchC *
* WITHOUT WARRANTY OF ANY KIND, either express *
* or implied. *
* For more information on ArchC, please... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the ... |
// The last statement disables all reports to the global context (uvm_top)
// having the ID "TransDump". Note that it is currently not possible to
// set filters for reports for several contexts at once using wildcards. Also,
// the hierarchical separator for SC may be configurable in your simulator, and
// thus coul... |
----------------------------------------------------
// Function: uvmc_set_config_int
//
// Set an integral configuration value
//
void uvmc_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
// Function: uvmc_set_config_string
//
// Set ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (ALU) {
sc_in <sc_int<8>> in1; // A
sc_in <sc_int<8>> in2; // B
sc_in <bool> c; // Carry Out // in this project, this signal is always 1
// ALUOP // has 5 bits by merging: opselect (4bits) and first LSB bit of opcode (1bit)
sc_in <sc_uint<5>... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
... |
#pragma once
#include <systemc.h>
#include <unordered_map>
#include "../../UTIL/debug_util.h"
#define RAM_SIZE 6000 //0xFFFF FFFF -> max size
SC_MODULE(RAM)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
... |
#ifndef TESTBENCH_VBASE_H
#define TESTBENCH_VBASE_H
#include <systemc.h>
#include "verilated.h"
#include "verilated_vcd_sc.h"
#define verilator_trace_enable(vcd_filename, dut) \
if (waves_enabled()) \
{ \
Verilated::traceEverOn(true); \
VerilatedVcdC *v_vcd = new VerilatedVcdC;... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _convolve_kernel... |
> ap_CS_fsm_pp0_stage24;
sc_signal< bool > ap_block_state34_pp0_stage24_iter0;
sc_signal< bool > ap_block_pp0_stage24_flag00011001;
sc_signal< bool > ap_block_pp0_stage24_flag00000000;
sc_signal< bool > ap_block_pp0_stage1_flag00000000;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage16;
sc_signal< boo... |
k_state22_pp0_stage12_iter0();
void thread_ap_block_state23_pp0_stage13_iter0();
void thread_ap_block_state24_pp0_stage14_iter0();
void thread_ap_block_state25_pp0_stage15_iter0();
void thread_ap_block_state26_pp0_stage16_iter0();
void thread_ap_block_state27_pp0_stage17_iter0();
void thread_ap_... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _doCorner_HH_
#d... |
#include "systemc.h"
#include "../cnm_base.h"
class pch_driver: public sc_module {
public:
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> RD; // DRAM read command
sc_out<sc_logic> WR; // DRAM write command
sc_out<sc_logic> ACT; // DRAM a... |
#include <systemc.h>
class sc_mutexx : public sc_prim_channel
{
public:
sc_event _free;
bool _locked;
// blocks until mutex could be locked
void lock()
{
while( _locked ) {
wait( _free );
}
_locked = true;
}
// returns false if mutex could not be lock... |
#ifndef TESTBENCH_H
#define TESTBENCH_H
#include <systemc.h>
#include <iostream>
using namespace std;
template <class DataType>
class Testbench : public sc_module
{
private:
void test()
{
print();
en_out = 1;
data_out = 1234;
wait();
print();
data_out.write(data_i... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _memcachedPipeline_spl... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Ext_KWTA64k_HH_... |
gnal< sc_lv<32> > tmp_37_reg_6171;
sc_signal< sc_lv<1> > cond1_fu_5095_p2;
sc_signal< sc_lv<1> > cond1_reg_6180;
sc_signal< sc_logic > ap_CS_fsm_state58;
sc_signal< sc_lv<32> > tmp_39_fu_5128_p2;
sc_signal< sc_lv<32> > tmp_39_reg_6185;
sc_signal< sc_logic > ap_CS_fsm_state59;
sc_signal< sc_l... |
u_4887_p6;
sc_signal< sc_lv<32> > tmp_64_fu_4887_p7;
sc_signal< sc_lv<1> > p_Repl2_1_fu_4915_p2;
sc_signal< sc_lv<11> > r_V_7_fu_4936_p2;
sc_signal< sc_lv<1> > sel_tmp4_fu_4963_p2;
sc_signal< sc_lv<1> > sel_tmp2_fu_4957_p2;
sc_signal< sc_lv<1> > sel_tmp_fu_4951_p2;
sc_signal< sc_lv<1> > or_c... |
oid thread_group_tree_tmp_maske_fu_4040_p2();
void thread_grp_fu_2243_p2();
void thread_grp_fu_2249_p2();
void thread_grp_fu_2255_p4();
void thread_grp_fu_2284_p2();
void thread_heap_tree_V_0_address0();
void thread_heap_tree_V_0_ce0();
void thread_heap_tree_V_0_d0();
void thread_heap_tr... |
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
******... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _foo_HH_
#define... |
/*
* Copyright (c) 2016 Baptiste Roux.
* email: <baptiste.roux AT inria.fr>.
*/
/*
* File: amba_GP.h
* SystemC TLM2.0 component for simulating amba general purpose memory map bus
* One tlm_socket master for Cpu
* nb_Msk tlm_socket slave for hw accelerators
*/
#ifndef _AMBA_GP
#define _AMBA_GP
#include "system... |
#ifndef RISCV_TOP_H
#define RISCV_TOP_H
#include <systemc.h>
#include "axi4.h"
#include "axi4.h"
class Vriscv_top;
class VerilatedVcdC;
//-------------------------------------------------------------
// riscv_top: RTL wrapper class
//-------------------------------------------------------------
class riscv_top: pub... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Duplicate_HH_
#... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
#ifndef TOP_H_
#define TOP_H_
#include "systemc.h"
class top : public sc_module {
public:
SC_HAS_PROCESS(top);
top(sc_module_name name_):
sc_module(name_)
, m_phase(0.0)
, clock("CLOCK", 10, 0.5, 0.0)
, sig_sin("sig_sin")
, sig_cos("sig_cos")
, sig_steps("sig_steps... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pooling2d_cl_1_... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Block_myproject_... |
#ifndef IMG_TRANSMITER_HPP
#define IMG_TRANSMITER_HPP
#include <systemc.h>
#include "address_map.hpp"
SC_MODULE(img_transmiter)
{
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
... |
/*
This file is part of wireworld_systemc
Copyright (C) 2015 Julien Thevenon ( julien_thevenon at yahoo.fr )
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of t... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the ... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _DoMemInit_HH_
#... |
V_27_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_27_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_28_address0;
sc_out< sc_logic > weights1_m_weights_V_28_ce0;
sc_out< sc_logic > weights1_m_weights_V_28_we0;
sc_out< sc_lv<32> > weights1_m_weights_V_28_d0;
sc_out< sc_lv<9> > weights1_m_weights_V_2... |
10_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_10_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_9_address0;
sc_out< sc_logic > threshs1_m_threshold_9_ce0;
sc_out< sc_logic > threshs1_m_threshold_9_we0;
sc_out< sc_lv<16> > threshs1_m_threshold_9_d0;
sc_out< sc_lv<4> > threshs1_m_threshold_8_addre... |
c > threshs3_m_threshold_1_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_1_d0;
sc_out< sc_lv<2> > threshs3_m_threshold_address0;
sc_out< sc_logic > threshs3_m_threshold_ce0;
sc_out< sc_logic > threshs3_m_threshold_we0;
sc_out< sc_lv<16> > threshs3_m_threshold_d0;
sc_out< sc_lv<2> > threshs3_m_th... |
ress0();
void thread_threshs1_m_threshold_38_ce0();
void thread_threshs1_m_threshold_38_d0();
void thread_threshs1_m_threshold_38_we0();
void thread_threshs1_m_threshold_39_address0();
void thread_threshs1_m_threshold_39_ce0();
void thread_threshs1_m_threshold_39_d0();
void thread_threshs1_m... |
id thread_weights0_m_weights_V_27_we0();
void thread_weights0_m_weights_V_28_address0();
void thread_weights0_m_weights_V_28_ce0();
void thread_weights0_m_weights_V_28_d0();
void thread_weights0_m_weights_V_28_we0();
void thread_weights0_m_weights_V_29_address0();
void thread_weights0_m_weights_... |
id thread_weights2_m_weights_V_6_d0();
void thread_weights2_m_weights_V_6_we0();
void thread_weights2_m_weights_V_7_address0();
void thread_weights2_m_weights_V_7_ce0();
void thread_weights2_m_weights_V_7_d0();
void thread_weights2_m_weights_V_7_we0();
void thread_weights2_m_weights_V_8_address0... |
#pragma once
/*******************************************************************************
* Apache License, Version 2.0
* Copyright (c) 2023 chciken/Niko
********************************************************************************/
#include <cstdint>
#include <string>
#include "systemc.h"
#include "sysc/ker... |
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux3) {
sc_in <bool> sel;
sc_in <sc_uint<3>> in0;
sc_in <sc_uint<3>> in1;
sc_out <sc_uint<3>> out;
/*
** module global variables
*/
SC_CTOR (Mux3){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
/*******************************************************************************
* i2c.h -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Models a single ESP32 I2C
**************************************************... |
//------------------------------------------------------------------------------
//! @file CppEmitter.h
//! @brief C++ Emitter classes
//
// SPDX-FileCopyrightText: Michael Popoloski
// SPDX-License-Identifier: MIT
//------------------------------------------------------------------------------
#pragma once
#include ... |
#ifndef _IF_QUANTUMSIM_H_
#define _IF_QUANTUMSIM_H_
#include <systemc.h>
#include <map>
#include <string>
#include <vector>
#include "global_json.h"
#include "interface_lib.h"
#include "telf_module.h"
#ifdef _DEBUG
#undef _DEBUG
#include <Python.h>
#define _DEBUG
#else
#include <Python.h>
#endif
namespace cactus {... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
#pragma once
#include <systemc.h>
#define BUF_SIZE 32
#define MAX_BUF_IDX (BUF_SIZE - 1)
SC_MODULE(FIFO) {
enum ic_addresses {
ICCONF = 0x18,
ICBUF = 0x1C
};
sc_in<bool> clk_i;
sc_in<sc_uint<32>> addr_bi;
sc_in<sc_uint<32>> data_bi;
sc_out<sc_uint<32>> data_bo;
... |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef AESL_COMP_H... |
c_lv<DOUT_WIDTH> > dout;
AESLFUMultiCycle<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>*
mMCModule;
SC_CTOR( FUMOBinaryOp ) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH+DIN1_WIDTH, DOUT_WIDTH>("mb_U");
mMCModule->opcode(opcode... |
char* mname) :
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH>(mname) {
sanity_check();
}
virtual void sanity_check() {
}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1) {
if(in0.is_01() && in1.is_01()) {
Op... |
#ifndef PE_H
#define PE_H
#include <iostream>
#include <fstream>
#include <cstdlib>
#include <iomanip>
#include <algorithm>
#include <vector>
#include "systemc.h"
using namespace std;
#define DEBUG_MODE true // You can change this value to get more information
#define TOTAL_PACKET_NUM 1 // Please don't change t... |
#include "systemc.h"
#include "define.h"
#include <iostream>
using namespace std;
SC_MODULE( Monitor ) {
sc_in_clk clk;
sc_in < bool > rst;
sc_in < DATA_TYPE > data_in;
sc_in < bool > data_valid;
void monitor();
int x, cycle;
SC_CTOR( Monitor )
{
x = 0;
cycle = 0;
SC_METHOD( monitor );
sensi... |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gran... |
#include <systemc.h>
//
// Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
//
// .. hwt-autodoc::
//
SC_MODULE(Showcase0) {
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_o... |
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Seuil_calc_do_ge... |
signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter11_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter12_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter13_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter14_reg;
sc_signal< sc_lv<32> > buffer_load_4_reg_1029_pp0_iter15_re... |
oad_13_reg_1100_pp0_iter22_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter23_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_13_reg_1100_pp0_iter26_reg;
sc_signal< sc_lv... |
_18_reg_1142_pp0_iter24_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter25_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter26_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter27_reg;
sc_signal< sc_lv<32> > buffer_load_18_reg_1142_pp0_iter28_reg;
sc_signal< sc_lv<32... |
al< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter96_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter97_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter98_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter99_reg;
sc_signal< sc_lv<32> > buffer_load_21_reg_1172_pp0_iter100_... |
;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter35_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter36_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter37_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211_pp0_iter38_reg;
sc_signal< sc_lv<32> > buffer_load_25_reg_1211... |
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter130_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter131_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter132_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233_pp0_iter133_reg;
sc_signal< sc_lv<32> > buffer_load_27_reg_1233... |
buffer_load_30_reg_1266_pp0_iter56_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter57_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter58_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter59_reg;
sc_signal< sc_lv<32> > buffer_load_30_reg_1266_pp0_iter60_reg;
sc_sign... |
58_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter159_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter160_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter161_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter162_reg;
sc_signal< sc_lv<32> > ps_reg_1433_pp0_iter163_reg;
sc_signal< sc_lv<32> > grp_f... |
2> ap_ST_fsm_pp0_stage0;
static const bool ap_const_boolean_1;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_41000000;
static const sc_lv<32> ap_const_lv32_3F4CCCCD;
static const sc_l... |
/*******************************************************************************
* gpio_mf.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC model of a generic multi-function GPIO.
***********... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.1
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _AXIvideo2Mat_HH... |
/*
* Copyright (c) 2016 Baptiste Roux.
* email: <baptiste.roux AT inria.fr>.
*/
/*
* File: nocIpc.h
* Noc for inter systemC kernel communication
*/
#ifndef _NOC_BASE
#define _NOC_BASE
//nocCtrl primitives
#include "noc_helper.h"
//configuration struct
#include "models/utility/socConfigStruct.h"
// list of task... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _axis_timestampe... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _acc4kmau_HH_
#d... |
#define SC_INCLUDE_FX
#include <systemc.h>
#include<fstream>
#include <iostream>
#include <vector>
using namespace std;
//--------------------------------------------------------
// CONV_RELU_1
// - in_feature_map: 150528 (3, 224, 224)
// - out_feature_map: 193600 (64, 55, 55)
//--------------------------------------... |
TH + ocol] = (sc_fixed_fast<45,17>)(partial_sum);
}
else{
out_feature_map[oc*OUT_HEIGHT*OUT_WIDTH + orow*OUT_WIDTH + ocol] = 0;
}
}
}
}
out_valid.write(1);
//std::cout<<"conv5_result[0,0,0]"<<out_feature_map[0]<<std::endl;
}
}
SC_CTOR(CONV_RELU_5)
{
SC_METHOD... |
#pragma once
#include "systemc.hpp"
#include "tlm.hpp"
#include "common.hpp"
struct Observer_module : sc_core::sc_module
{
sc_core::sc_export<sc_core::sc_signal_out_if<Data_t>> actual_export { "actual_export" };
sc_core::sc_port<sc_core::sc_signal_in_if<Data_t>> expect_port { "expect_port" };
sc_core::sc_p... |
#include <systemc.h>
#include "memory.cpp"
int sc_main (int argc, char* argv[]) {
int data;
ram mem("MEM", 1024);
// Open VCD file
sc_trace_file *wf = sc_create_vcd_trace_file("memory");
wf->set_time_unit(1, SC_NS);
// Dump the desired signals
sc_trace(wf, data, "data");
sc_start... |
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
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