text stringlengths 41 20k |
|---|
#include "systemc.h"
#include <bitset>
#include "../cnm_base.h"
SC_MODULE(pch_monitor) {
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logi... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _memcachedPipeline_bp_... |
/*
* Created on: 24. OCT. 2019
* Author: Jonathan Horsted Schougaard
*/
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include "hwcore/pipes/data_types.h"
#include <systemc.h>
#ifndef __tag
#warning __tag not defined!!!
#undef _sc_stream_stitching
#else
#define _sc_stream_stitching JOIN(_sc_stream_s... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _contact_discove... |
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
... |
/*******************************************************************************
* espintr.cpp -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC module for the ESP32 interrupt management.
********... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gran... |
#ifndef POWERBUTTON_H_
#define POWERBUTTON_H_
#include "systemc.h"
#include "interface.h"
using namespace std;
SC_MODULE(PowerButton){
//port(s) connected to outside
sc_in<bool> pt_pressed;
//port(s) inside the phone
sc_out<bool> shortPress;
sc_out<bool> longPress;
//internal variables
sc_time lastTimeStam... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
#ifndef TESTBENCH_VBASE_H
#define TESTBENCH_VBASE_H
#include <systemc.h>
#include "verilated.h"
#include "verilated_vcd_sc.h"
#define verilator_trace_enable(vcd_filename, dut) \
if (waves_enabled()) \
{ \
Verilated::traceEverOn(true); \
VerilatedVcdC *v_vcd = new VerilatedVcdC;... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _doCorner_HH_
#d... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Block_myproject_... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Block_myproject_... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
/// \file
/// Implementation of the class Ilator.
#include <ilang/target-sc/ilator.h>
#include <fstream>
#include <fmt/format.h>
#include <z3++.h>
#include <ilang/config.h>
#include <ilang/ila-mngr/pass.h>
#include <ilang/ila-mngr/u_abs_knob.h>
#include <ilang/ila/ast_hub.h>
#include <ilang/target-smt/z3_expr_adapt... |
ator::GenerateBuildSupport(const std::string& dir) {
// CMakeLists.txt
static const char* kCmakeRecipeTemplate =
"# CMakeLists.txt for {project}\n"
"cmake_minimum_required(VERSION 3.14.0)\n"
"project({project} LANGUAGES CXX)\n"
"\n"
"option(ILATOR_VERBOSE \"Enable instruction sequence ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _axis_timestampe... |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef AESL_PKG_HH... |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef AESL_PKG_HH... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _sparse_mm_HH_
#define... |
#include <vector>
#include "systemc.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#ifndef INC_MEMORY_H_
#define INC_MEMORY_H_
class MEMORY : public sc_module
{
public:
MEMORY(sc_module_name name);
tlm_utils::simple_target_socket<MEMORY> memory_socket;
private:
void... |
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
*... |
// Copyright (c) 2011-2024 Columbia University, System Level Design Group
// SPDX-License-Identifier: MIT
#ifndef __ESP_SYSTEMC_HPP__
#define __ESP_SYSTEMC_HPP__
// Fixed point
#if defined(SC_FIXED_POINT) || defined(SC_FIXED_POINT_FAST)
// Using SystemC fixed point
#define SC_INCLUDE_FX
#include <systemc.h>
#else... |
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* ... |
er of error
////-----------------------------------------------------------------------------
//int annTest(int index, int k)
//{
// int x0; int x1; int y;
// double x[2];
// double xor_ex;
// int error = 0;
//
// if ( annCheck(index) != EXIT_SUCCESS )
// return( -1 ); // less than zero errors <==> the ANN isn't c... |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gra... |
#ifndef SYSC_TYPES_H
#define SYSC_TYPES_H
#include <iomanip>
#include <iostream>
#include <systemc.h>
#include "secda_hw_utils.sc.h"
#ifndef DWAIT
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#endif
#define INITSIGPORT(X, SID) X((std::string(#X) + std::to_string(SID)).c_str())
// Har... |
// sub.h: interface for the sub class.
//
//////////////////////////////////////////////////////////////////////
#ifndef _SUB_H_
#define _SUB_H_
#include "systemc.h"
#ifdef INI_CHANNEL
#undef INI_CHANNEL
#endif
#define INI_CHANNEL , clock("clock")\
, in_bool("in_bool")\
, in_float("in_float")\
, in_doub... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Detecteur2_HH_
#... |
/**
* @license MIT
* @brief Print stuff for types and structs.
*/
#ifndef HUFFMAN_CODING_PRINT_H
#define HUFFMAN_CODING_PRINT_H
///////////////////////////////////////////////////////////////////////////////
#include <ostream>
#include <vector>
#include <deque>
#include <systemc.h>
/////////////////////////////... |
#ifndef RISCV_TOP_H
#define RISCV_TOP_H
#include <systemc.h>
#include "axi4.h"
#include "axi4.h"
class Vriscv_top;
class VerilatedVcdC;
//-------------------------------------------------------------
// riscv_top: RTL wrapper class
//-------------------------------------------------------------
class riscv_top: pub... |
/******************************************************************************
* *
* Copyright (C) 2024 MachineWare GmbH *
* All Rights Reserved *
... |
/*
* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gran... |
// Copyright 2019 Glenn Ramalho - RFIDo Design
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law o... |
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
if(!spi->dev->ctrl.wr_bit_order){
data = __spiTranslate32(data);
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = ... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _karastuba_mul_... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Seuil_calc2_do_g... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _DoCompute_HH_
#... |
hts_V_31_q1;
sc_out< sc_logic > weights0_m_weights_V_31_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_31_address0;
sc_out< sc_logic > threshs0_m_threshold_31_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_31_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_31_q0;
sc_out< sc_logic > threshs0_m_threshold... |
logic > weights1_m_weights_V_6_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_6_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_6_q0;
sc_out< sc_logic > weights1_m_weights_V_6_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_6_address1;
sc_out< sc_logic > weights1_m_weights_V_6_ce1;
sc_out< sc_lv<32> > w... |
address0;
sc_out< sc_logic > weights1_m_weights_V_44_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_44_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_44_q0;
sc_out< sc_logic > weights1_m_weights_V_44_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_44_address1;
sc_out< sc_logic > weights1_m_weights_V_44... |
_53_address0;
sc_out< sc_logic > threshs1_m_threshold_53_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_53_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_53_q0;
sc_out< sc_logic > threshs1_m_threshold_53_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_53_address1;
sc_out< sc_logic > threshs1_m_threshol... |
_m_threshold_12_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_11_address0;
sc_out< sc_logic > threshs1_m_threshold_11_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_11_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_11_q0;
sc_out< sc_logic > threshs1_m_threshold_11_we0;
sc_out< sc_lv<4> > threshs1_m_t... |
hts_V_30_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_30_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_30_q0;
sc_out< sc_logic > weights2_m_weights_V_30_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_30_address1;
sc_out< sc_logic > weights2_m_weights_V_30_ce1;
sc_out< sc_lv<64> > weights2_m_weights... |
> weights3_m_weights_V_4_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_4_address1;
sc_out< sc_logic > weights3_m_weights_V_4_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_4_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_4_q1;
sc_out< sc_logic > weights3_m_weights_V_4_we1;
sc_out< sc_lv<9> > weights3_m... |
c_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_1_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_2_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_3_address0;
sc_signal<... |
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_55_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_55_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_56_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_... |
ix_Vector_Activa_2_U0_threshs2_m_threshold_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_29_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_28_ce0;
sc_signal< s... |
ector_Activa_U0_ap_start();
void thread_ap_sync_Mem2Stream_Batch12_U0_ap_ready();
void thread_ap_sync_Mem2Stream_Batch12_U0_ap_start();
void thread_m_axi_in_V_ARADDR();
void thread_m_axi_in_V_ARBURST();
void thread_m_axi_in_V_ARCACHE();
void thread_m_axi_in_V_ARID();
void thread_m_axi_in_V_A... |
d_25_d0();
void thread_threshs1_m_threshold_25_d1();
void thread_threshs1_m_threshold_25_we0();
void thread_threshs1_m_threshold_25_we1();
void thread_threshs1_m_threshold_26_address0();
void thread_threshs1_m_threshold_26_address1();
void thread_threshs1_m_threshold_26_ce0();
void thread_th... |
threshs2_m_threshold_14_we1();
void thread_threshs2_m_threshold_15_address0();
void thread_threshs2_m_threshold_15_address1();
void thread_threshs2_m_threshold_15_ce0();
void thread_threshs2_m_threshold_15_ce1();
void thread_threshs2_m_threshold_15_d0();
void thread_threshs2_m_threshold_15_d1();... |
1();
void thread_weights0_m_weights_V_19_d0();
void thread_weights0_m_weights_V_19_d1();
void thread_weights0_m_weights_V_19_we0();
void thread_weights0_m_weights_V_19_we1();
void thread_weights0_m_weights_V_1_address0();
void thread_weights0_m_weights_V_1_address1();
void thread_weights0_m_... |
void thread_weights1_m_weights_V_37_we1();
void thread_weights1_m_weights_V_38_address0();
void thread_weights1_m_weights_V_38_address1();
void thread_weights1_m_weights_V_38_ce0();
void thread_weights1_m_weights_V_38_ce1();
void thread_weights1_m_weights_V_38_d0();
void thread_weights1_m_we... |
ts2_m_weights_V_27_address1();
void thread_weights2_m_weights_V_27_ce0();
void thread_weights2_m_weights_V_27_ce1();
void thread_weights2_m_weights_V_27_d0();
void thread_weights2_m_weights_V_27_d1();
void thread_weights2_m_weights_V_27_we0();
void thread_weights2_m_weights_V_27_we1();
void ... |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the ... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
/*
** This file is part of gSysC.
**
** gSysC is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** gSysC is distributed in the hope... |
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define AP_INT_MAX_W 2048 // Size of "sc_bv<W> data" exceed limit (1024) for ALexNet layer 11x11
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include <iostream>
#include <string>
#include <systemc.h>
#define SC_STR... |
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
******... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Sobel_HH_
#defi... |
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (... |
#include <systemc.h>
#include <stdio.h>
#include <vector>
#include <string>
#include <stdlib.h>
#include <gtkmm.h>
#include <random>
#include <boost/thread.hpp>
using namespace std;
using namespace Gtk;
using namespace boost;
#include "../gladicapi/data_recorder.h"
#include "../gladicapi/data_check.h"
bool EEP_EOP;... |
_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
data_col_store.push_back(" ");
COMPARE_SPW->compare_test(&data_col_store);
data_iteration++;
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
case 3:
data_col_store.push_back("EEP");
int... |
/*
* Adder.h
* SystemC_SimpleAdder
*
* Created by Le Gal on 07/05/07.
* Copyright 2007 __MyCompanyName__. All rights reserved.
*
*/
#ifndef _BitsToBytes_
#define _BitsToBytes_
#include "systemc.h"
#include <cstdint>
SC_MODULE(BitsToBytes)
{
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _trames_separ2_do... |
//
// Created by tobias on 09.03.17.
//
#ifndef PROJECT_SLAVEAGENT_H
#define PROJECT_SLAVEAGENT_H
#include "systemc.h"
#include "../../Interfaces/Interfaces.h"
#include "types_reduced.h"
struct SlaveAgent : public sc_module {
//Sections
enum Sections {
IDLE, READ, WRITE,DONE
};
Sections secti... |
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// D... |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gran... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _FAST_t_opr_HH_
... |
_p2;
sc_signal< sc_lv<1> > not_or_cond11_reg_4828;
sc_signal< sc_lv<1> > tmp6_fu_3209_p2;
sc_signal< sc_lv<1> > tmp6_reg_4834;
sc_signal< sc_lv<1> > tmp10_fu_3215_p2;
sc_signal< sc_lv<1> > tmp10_reg_4839;
sc_signal< sc_lv<32> > flag_d_assign_8_fu_3221_p1;
sc_signal< sc_lv<32> > flag_d_assign... |
_int_s_fu_1083_ap_ready;
sc_signal< sc_lv<32> > a0_1_max_int_s_fu_1083_ap_return;
sc_signal< sc_logic > a0_s_max_int_s_fu_1091_ap_ready;
sc_signal< sc_lv<32> > a0_s_max_int_s_fu_1091_ap_return;
sc_signal< sc_logic > a0_1_1_max_int_s_fu_1099_ap_ready;
sc_signal< sc_lv<32> > a0_1_1_max_int_s_fu_1099_a... |
ock_state11_pp0_stage0_iter8_ignore_call35;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call35;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp612;
sc_signal< sc_logic > grp_reg_int_s_fu_3859_ap_ce;
sc_signal< bool > ap_predicate_op614_call_state7;
sc_signal< bool > ap_block_... |
_ignore_call79;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call79;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call79;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call79;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call79;
sc_signal< bool > ... |
signal< sc_lv<1> > tmp8_fu_3203_p2;
sc_signal< sc_lv<1> > tmp7_fu_3197_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_1_fu_3073_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_2_fu_3135_p2;
sc_signal< sc_lv<1> > not_or_cond13_demorg_fu_3290_p2;
sc_signal< sc_lv<1> > tmp_73_3_fu_3285_p2;
sc_signal< sc_lv<1> >... |
_iter0_ignore_call11();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call13();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call15();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call17();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call19();
void thread_ap_block_state3_... |
ate9_pp0_stage0_iter6_ignore_call31();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call33();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call35();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call37();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call39();
void thread_a... |
2123_p2();
void thread_tmp_64_3_fu_2211_p2();
void thread_tmp_64_4_fu_2299_p2();
void thread_tmp_64_5_fu_2387_p2();
void thread_tmp_64_6_fu_2475_p2();
void thread_tmp_64_7_fu_2563_p2();
void thread_tmp_65_1_fu_2041_p2();
void thread_tmp_65_2_fu_2129_p2();
void thread_tmp_65_3_fu_2217_p2(... |
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef __HOST_BASE_H__
#define __HOST_BASE_H__
#include <cstdlib>
#include <systemc.h>
#include <queue>
#include <tlm.h>
#inclu... |
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