system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* ECE 5720 Parallel Computing Final Project
* KMP parallel on MPI
* Feng Qi, fq26
* Ying Zong, yz887
* Cornell University
*
* Compile : /usr/local/cuda-8.0/bin/nvcc -arch=compute_35 -o cuda kmp-cuda.cu
* Run : ./cuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
// build the kmp table for the subsequent operations
void preKMP(char* pattern, int func[]) {
int m = strlen(pattern);
int k;
func[0] = -1;
for (int i = 1; i < m; i++) {
k = func[i - 1];
while (k >= 0) {
if (pattern[k] == pattern[i - 1]) {
break;
}
else {
k = func[k];
}
}
func[i] = k + 1;
}
}
// Kernel function. Implement the KMP algorithm
__global__ void KMP(char* pattern, char* target, int func[], int answer[], int pattern_length, int target_length) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int i = pattern_length * index;
int j = pattern_length * (index + 2) - 1;
if(i > target_length) {
return;
}
if(j > target_length) {
j = target_length;
}
int k = 0;
while (i < j) {
if (k == -1) {
i++;
k = 0;
} else if (target[i] == pattern[k]) {
i++;
k++;
if (k == pattern_length) {
answer[i - pattern_length] = i - pattern_length;
i = i - k + 1;
}
}
else {
k = func[k];
}
}
return;
}
int main(int argc, char* argv[]) {
int M = 4;
int n = 100000;
int m = 3;
char* target = (char*)malloc(n * sizeof(char));
char* pattern = (char*)malloc(m * sizeof(char));
printf("----- This is parallel results using KMP Algo on CUDA. -----\n");
FILE * file = fopen( "data.txt" , "r");
int CurrentIndex = 0;
while (CurrentIndex < 2) {
if (CurrentIndex == 0) {
fgets(target, n+1, file);
} else if (CurrentIndex == 1) {
fgets(pattern, m+1, file);
}
CurrentIndex++;
}
int target_length = strlen(target);
int pattern_length = strlen(pattern);
fclose(file);
char *d_target;
char *d_pattern;
int *func;
int *answer;
func = new int[target_length];
answer = new int[target_length];
int *d_func;
int *d_answer;
for(int i = 0; i < target_length; i++) {
answer[i] = -1;
}
preKMP(pattern, func);
cudaEvent_t start, stop;
float elapsedTime;
cudaEventCreate( &start );
cudaEventCreate( &stop );
cudaEventRecord( start, 0 );
cudaMalloc((void **)&d_target, target_length * sizeof(char));
cudaMalloc((void **)&d_pattern, pattern_length * sizeof(char));
cudaMalloc((void **)&d_func, target_length * sizeof(int));
cudaMalloc((void **)&d_answer, target_length * sizeof(int));
cudaMemcpy(d_target, target, target_length * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_pattern, pattern, pattern_length * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_func, func, target_length * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_answer, answer, target_length * sizeof(int), cudaMemcpyHostToDevice);
KMP<<<(target_length / pattern_length + M)/M, M>>>(d_pattern, d_target ,d_func, d_answer, pattern_length, target_length);
cudaMemcpy(answer, d_answer, target_length * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsedTime, start, stop );
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n", target_length, pattern_length, elapsedTime);
for(int i = 0; i < target_length; i++) {
if (answer[i] != -1) {
printf("Find a matching substring starting at: %d.\n", i);
}
}
cudaFree(d_target);
cudaFree(d_pattern);
cudaFree(d_func);
cudaFree(d_answer);
free(target);
free(pattern);
return 0;
} | code for sm_80
Function : _Z3KMPPcS_PiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD R2, R3, 0x2, R0 ; /* 0x0000000203027824 */
/* 0x000fca00078e0200 */
/*0090*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ IMNMX R7, R2, c[0x0][0x184], PT ; /* 0x0000610002077a17 */
/* 0x000fc80003800200 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x020fe20003f05270 */
/*0100*/ BSSY B0, 0x2d0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*0110*/ @!P0 BRA 0x2a0 ; /* 0x0000018000008947 */
/* 0x001fea0003800000 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe40007f1e0ff */
/*0130*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fe40000011406 */
/*0140*/ IADD3 R2, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fe40007f3e0ff */
/*0150*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe400000f0eff */
/*0160*/ IADD3.X R3, R9, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590009037a10 */
/* 0x000fc80000ffe4ff */
/*0170*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1100 */
/*0180*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0190*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*01a0*/ @!P0 BRA 0x1f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01b0*/ LEA R2, P0, R6, c[0x0][0x170], 0x2 ; /* 0x00005c0006027a11 */
/* 0x000fc800078010ff */
/*01c0*/ LEA.HI.X R3, R6, c[0x0][0x174], R9, 0x2, P0 ; /* 0x00005d0006037a11 */
/* 0x000fca00000f1409 */
/*01d0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*01e0*/ BRA 0x2c0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0200*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x2c0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R5, R0, -c[0x0][0x180], RZ ; /* 0x8000600000057a10 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*0260*/ IADD3 R0, R5.reuse, 0x1, RZ ; /* 0x0000000105007810 */
/* 0x040fe20007ffe0ff */
/*0270*/ IMAD.WIDE R2, R5, R2, c[0x0][0x178] ; /* 0x00005e0005027625 */
/* 0x000fca00078e0202 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0290*/ BRA 0x2c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06270 */
/*02e0*/ @!P0 BRA 0xf0 ; /* 0xfffffe0000008947 */
/* 0x000fea000383ffff */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* ECE 5720 Parallel Computing Final Project
* KMP parallel on MPI
* Feng Qi, fq26
* Ying Zong, yz887
* Cornell University
*
* Compile : /usr/local/cuda-8.0/bin/nvcc -arch=compute_35 -o cuda kmp-cuda.cu
* Run : ./cuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
// build the kmp table for the subsequent operations
void preKMP(char* pattern, int func[]) {
int m = strlen(pattern);
int k;
func[0] = -1;
for (int i = 1; i < m; i++) {
k = func[i - 1];
while (k >= 0) {
if (pattern[k] == pattern[i - 1]) {
break;
}
else {
k = func[k];
}
}
func[i] = k + 1;
}
}
// Kernel function. Implement the KMP algorithm
__global__ void KMP(char* pattern, char* target, int func[], int answer[], int pattern_length, int target_length) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int i = pattern_length * index;
int j = pattern_length * (index + 2) - 1;
if(i > target_length) {
return;
}
if(j > target_length) {
j = target_length;
}
int k = 0;
while (i < j) {
if (k == -1) {
i++;
k = 0;
} else if (target[i] == pattern[k]) {
i++;
k++;
if (k == pattern_length) {
answer[i - pattern_length] = i - pattern_length;
i = i - k + 1;
}
}
else {
k = func[k];
}
}
return;
}
int main(int argc, char* argv[]) {
int M = 4;
int n = 100000;
int m = 3;
char* target = (char*)malloc(n * sizeof(char));
char* pattern = (char*)malloc(m * sizeof(char));
printf("----- This is parallel results using KMP Algo on CUDA. -----\n");
FILE * file = fopen( "data.txt" , "r");
int CurrentIndex = 0;
while (CurrentIndex < 2) {
if (CurrentIndex == 0) {
fgets(target, n+1, file);
} else if (CurrentIndex == 1) {
fgets(pattern, m+1, file);
}
CurrentIndex++;
}
int target_length = strlen(target);
int pattern_length = strlen(pattern);
fclose(file);
char *d_target;
char *d_pattern;
int *func;
int *answer;
func = new int[target_length];
answer = new int[target_length];
int *d_func;
int *d_answer;
for(int i = 0; i < target_length; i++) {
answer[i] = -1;
}
preKMP(pattern, func);
cudaEvent_t start, stop;
float elapsedTime;
cudaEventCreate( &start );
cudaEventCreate( &stop );
cudaEventRecord( start, 0 );
cudaMalloc((void **)&d_target, target_length * sizeof(char));
cudaMalloc((void **)&d_pattern, pattern_length * sizeof(char));
cudaMalloc((void **)&d_func, target_length * sizeof(int));
cudaMalloc((void **)&d_answer, target_length * sizeof(int));
cudaMemcpy(d_target, target, target_length * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_pattern, pattern, pattern_length * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_func, func, target_length * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_answer, answer, target_length * sizeof(int), cudaMemcpyHostToDevice);
KMP<<<(target_length / pattern_length + M)/M, M>>>(d_pattern, d_target ,d_func, d_answer, pattern_length, target_length);
cudaMemcpy(answer, d_answer, target_length * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsedTime, start, stop );
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n", target_length, pattern_length, elapsedTime);
for(int i = 0; i < target_length; i++) {
if (answer[i] != -1) {
printf("Find a matching substring starting at: %d.\n", i);
}
}
cudaFree(d_target);
cudaFree(d_pattern);
cudaFree(d_func);
cudaFree(d_answer);
free(target);
free(pattern);
return 0;
} | .file "tmpxft_00189291_00000000-6_kmp-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6preKMPPcPi
.type _Z6preKMPPcPi, @function
_Z6preKMPPcPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rsi, %rbx
call strlen@PLT
movl $-1, (%rbx)
cmpl $1, %eax
jle .L3
leal -2(%rax), %edi
movl $0, %esi
jmp .L7
.L5:
addl $1, %eax
movl %eax, 4(%rbx,%rsi,4)
leaq 1(%rsi), %rax
cmpq %rdi, %rsi
je .L3
movq %rax, %rsi
.L7:
movl (%rbx,%rsi,4), %eax
testl %eax, %eax
js .L5
movzbl 0(%rbp,%rsi), %ecx
.L6:
movslq %eax, %rdx
cmpb %cl, 0(%rbp,%rdx)
je .L5
movl (%rbx,%rdx,4), %eax
testl %eax, %eax
jns .L6
jmp .L5
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6preKMPPcPi, .-_Z6preKMPPcPi
.globl _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
.type _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii, @function
_Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3KMPPcS_PiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii, .-_Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
.globl _Z3KMPPcS_PiS0_ii
.type _Z3KMPPcS_PiS0_ii, @function
_Z3KMPPcS_PiS0_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3KMPPcS_PiS0_ii, .-_Z3KMPPcS_PiS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "----- This is parallel results using KMP Algo on CUDA. -----\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "data.txt"
.section .rodata.str1.8
.align 8
.LC3:
.string "When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n"
.align 8
.LC4:
.string "Find a matching substring starting at: %d.\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $100000, %edi
call malloc@PLT
movq %rax, %r14
movl $3, %edi
call malloc@PLT
movq %rax, %r12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rcx
movl $100001, %edx
movl $100000, %esi
movq %r14, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
movl $4, %edx
movl $3, %esi
movq %r12, %rdi
call __fgets_chk@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rbp
movl %eax, (%rsp)
movq %r12, %rdi
call strlen@PLT
movq %rax, 16(%rsp)
movl %eax, 4(%rsp)
movq %rbx, %rdi
call fclose@PLT
movslq %ebp, %r15
movabsq $2305843009213693950, %rax
cmpq %r15, %rax
jb .L20
leaq 0(,%r15,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbx
testl %ebp, %ebp
jle .L22
leal -1(%rbp), %edx
leaq 4(%rax,%rdx,4), %rdx
.L24:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
.L22:
movq 8(%rsp), %rsi
movq %r12, %rdi
call _Z6preKMPPcPi
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movslq 16(%rsp), %rax
leaq 40(%rsp), %rdi
movq %rax, 24(%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 24(%rsp), %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl (%rsp), %eax
cltd
idivl 4(%rsp)
leal 7(%rax), %edx
addl $4, %eax
cmovns %eax, %edx
sarl $2, %edx
movl %edx, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
movl $2, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L26
leal -1(%rbp), %r13d
movl $0, %ebp
leaq .LC4(%rip), %r15
jmp .L28
.L20:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movl %ebp, %r9d
movl 16(%rsp), %r8d
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
jmp .L25
.L27:
leaq 1(%rbp), %rax
cmpq %r13, %rbp
je .L26
movq %rax, %rbp
.L28:
cmpl $-1, (%rbx,%rbp,4)
je .L27
movl %ebp, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L26:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3KMPPcS_PiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3KMPPcS_PiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* ECE 5720 Parallel Computing Final Project
* KMP parallel on MPI
* Feng Qi, fq26
* Ying Zong, yz887
* Cornell University
*
* Compile : /usr/local/cuda-8.0/bin/nvcc -arch=compute_35 -o cuda kmp-cuda.cu
* Run : ./cuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
// build the kmp table for the subsequent operations
void preKMP(char* pattern, int func[]) {
int m = strlen(pattern);
int k;
func[0] = -1;
for (int i = 1; i < m; i++) {
k = func[i - 1];
while (k >= 0) {
if (pattern[k] == pattern[i - 1]) {
break;
}
else {
k = func[k];
}
}
func[i] = k + 1;
}
}
// Kernel function. Implement the KMP algorithm
__global__ void KMP(char* pattern, char* target, int func[], int answer[], int pattern_length, int target_length) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int i = pattern_length * index;
int j = pattern_length * (index + 2) - 1;
if(i > target_length) {
return;
}
if(j > target_length) {
j = target_length;
}
int k = 0;
while (i < j) {
if (k == -1) {
i++;
k = 0;
} else if (target[i] == pattern[k]) {
i++;
k++;
if (k == pattern_length) {
answer[i - pattern_length] = i - pattern_length;
i = i - k + 1;
}
}
else {
k = func[k];
}
}
return;
}
int main(int argc, char* argv[]) {
int M = 4;
int n = 100000;
int m = 3;
char* target = (char*)malloc(n * sizeof(char));
char* pattern = (char*)malloc(m * sizeof(char));
printf("----- This is parallel results using KMP Algo on CUDA. -----\n");
FILE * file = fopen( "data.txt" , "r");
int CurrentIndex = 0;
while (CurrentIndex < 2) {
if (CurrentIndex == 0) {
fgets(target, n+1, file);
} else if (CurrentIndex == 1) {
fgets(pattern, m+1, file);
}
CurrentIndex++;
}
int target_length = strlen(target);
int pattern_length = strlen(pattern);
fclose(file);
char *d_target;
char *d_pattern;
int *func;
int *answer;
func = new int[target_length];
answer = new int[target_length];
int *d_func;
int *d_answer;
for(int i = 0; i < target_length; i++) {
answer[i] = -1;
}
preKMP(pattern, func);
cudaEvent_t start, stop;
float elapsedTime;
cudaEventCreate( &start );
cudaEventCreate( &stop );
cudaEventRecord( start, 0 );
cudaMalloc((void **)&d_target, target_length * sizeof(char));
cudaMalloc((void **)&d_pattern, pattern_length * sizeof(char));
cudaMalloc((void **)&d_func, target_length * sizeof(int));
cudaMalloc((void **)&d_answer, target_length * sizeof(int));
cudaMemcpy(d_target, target, target_length * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_pattern, pattern, pattern_length * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_func, func, target_length * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_answer, answer, target_length * sizeof(int), cudaMemcpyHostToDevice);
KMP<<<(target_length / pattern_length + M)/M, M>>>(d_pattern, d_target ,d_func, d_answer, pattern_length, target_length);
cudaMemcpy(answer, d_answer, target_length * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
cudaEventElapsedTime( &elapsedTime, start, stop );
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n", target_length, pattern_length, elapsedTime);
for(int i = 0; i < target_length; i++) {
if (answer[i] != -1) {
printf("Find a matching substring starting at: %d.\n", i);
}
}
cudaFree(d_target);
cudaFree(d_pattern);
cudaFree(d_func);
cudaFree(d_answer);
free(target);
free(pattern);
return 0;
} | /*
* ECE 5720 Parallel Computing Final Project
* KMP parallel on MPI
* Feng Qi, fq26
* Ying Zong, yz887
* Cornell University
*
* Compile : /usr/local/cuda-8.0/bin/nvcc -arch=compute_35 -o cuda kmp-cuda.cu
* Run : ./cuda
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
// build the kmp table for the subsequent operations
void preKMP(char* pattern, int func[]) {
int m = strlen(pattern);
int k;
func[0] = -1;
for (int i = 1; i < m; i++) {
k = func[i - 1];
while (k >= 0) {
if (pattern[k] == pattern[i - 1]) {
break;
}
else {
k = func[k];
}
}
func[i] = k + 1;
}
}
// Kernel function. Implement the KMP algorithm
__global__ void KMP(char* pattern, char* target, int func[], int answer[], int pattern_length, int target_length) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int i = pattern_length * index;
int j = pattern_length * (index + 2) - 1;
if(i > target_length) {
return;
}
if(j > target_length) {
j = target_length;
}
int k = 0;
while (i < j) {
if (k == -1) {
i++;
k = 0;
} else if (target[i] == pattern[k]) {
i++;
k++;
if (k == pattern_length) {
answer[i - pattern_length] = i - pattern_length;
i = i - k + 1;
}
}
else {
k = func[k];
}
}
return;
}
int main(int argc, char* argv[]) {
int M = 4;
int n = 100000;
int m = 3;
char* target = (char*)malloc(n * sizeof(char));
char* pattern = (char*)malloc(m * sizeof(char));
printf("----- This is parallel results using KMP Algo on CUDA. -----\n");
FILE * file = fopen( "data.txt" , "r");
int CurrentIndex = 0;
while (CurrentIndex < 2) {
if (CurrentIndex == 0) {
fgets(target, n+1, file);
} else if (CurrentIndex == 1) {
fgets(pattern, m+1, file);
}
CurrentIndex++;
}
int target_length = strlen(target);
int pattern_length = strlen(pattern);
fclose(file);
char *d_target;
char *d_pattern;
int *func;
int *answer;
func = new int[target_length];
answer = new int[target_length];
int *d_func;
int *d_answer;
for(int i = 0; i < target_length; i++) {
answer[i] = -1;
}
preKMP(pattern, func);
hipEvent_t start, stop;
float elapsedTime;
hipEventCreate( &start );
hipEventCreate( &stop );
hipEventRecord( start, 0 );
hipMalloc((void **)&d_target, target_length * sizeof(char));
hipMalloc((void **)&d_pattern, pattern_length * sizeof(char));
hipMalloc((void **)&d_func, target_length * sizeof(int));
hipMalloc((void **)&d_answer, target_length * sizeof(int));
hipMemcpy(d_target, target, target_length * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_pattern, pattern, pattern_length * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_func, func, target_length * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_answer, answer, target_length * sizeof(int), hipMemcpyHostToDevice);
KMP<<<(target_length / pattern_length + M)/M, M>>>(d_pattern, d_target ,d_func, d_answer, pattern_length, target_length);
hipMemcpy(answer, d_answer, target_length * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsedTime, start, stop );
hipEventDestroy(start);
hipEventDestroy(stop);
printf("When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n", target_length, pattern_length, elapsedTime);
for(int i = 0; i < target_length; i++) {
if (answer[i] != -1) {
printf("Find a matching substring starting at: %d.\n", i);
}
}
hipFree(d_target);
hipFree(d_pattern);
hipFree(d_func);
hipFree(d_answer);
free(target);
free(pattern);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* ECE 5720 Parallel Computing Final Project
* KMP parallel on MPI
* Feng Qi, fq26
* Ying Zong, yz887
* Cornell University
*
* Compile : /usr/local/cuda-8.0/bin/nvcc -arch=compute_35 -o cuda kmp-cuda.cu
* Run : ./cuda
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
// build the kmp table for the subsequent operations
void preKMP(char* pattern, int func[]) {
int m = strlen(pattern);
int k;
func[0] = -1;
for (int i = 1; i < m; i++) {
k = func[i - 1];
while (k >= 0) {
if (pattern[k] == pattern[i - 1]) {
break;
}
else {
k = func[k];
}
}
func[i] = k + 1;
}
}
// Kernel function. Implement the KMP algorithm
__global__ void KMP(char* pattern, char* target, int func[], int answer[], int pattern_length, int target_length) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int i = pattern_length * index;
int j = pattern_length * (index + 2) - 1;
if(i > target_length) {
return;
}
if(j > target_length) {
j = target_length;
}
int k = 0;
while (i < j) {
if (k == -1) {
i++;
k = 0;
} else if (target[i] == pattern[k]) {
i++;
k++;
if (k == pattern_length) {
answer[i - pattern_length] = i - pattern_length;
i = i - k + 1;
}
}
else {
k = func[k];
}
}
return;
}
int main(int argc, char* argv[]) {
int M = 4;
int n = 100000;
int m = 3;
char* target = (char*)malloc(n * sizeof(char));
char* pattern = (char*)malloc(m * sizeof(char));
printf("----- This is parallel results using KMP Algo on CUDA. -----\n");
FILE * file = fopen( "data.txt" , "r");
int CurrentIndex = 0;
while (CurrentIndex < 2) {
if (CurrentIndex == 0) {
fgets(target, n+1, file);
} else if (CurrentIndex == 1) {
fgets(pattern, m+1, file);
}
CurrentIndex++;
}
int target_length = strlen(target);
int pattern_length = strlen(pattern);
fclose(file);
char *d_target;
char *d_pattern;
int *func;
int *answer;
func = new int[target_length];
answer = new int[target_length];
int *d_func;
int *d_answer;
for(int i = 0; i < target_length; i++) {
answer[i] = -1;
}
preKMP(pattern, func);
hipEvent_t start, stop;
float elapsedTime;
hipEventCreate( &start );
hipEventCreate( &stop );
hipEventRecord( start, 0 );
hipMalloc((void **)&d_target, target_length * sizeof(char));
hipMalloc((void **)&d_pattern, pattern_length * sizeof(char));
hipMalloc((void **)&d_func, target_length * sizeof(int));
hipMalloc((void **)&d_answer, target_length * sizeof(int));
hipMemcpy(d_target, target, target_length * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_pattern, pattern, pattern_length * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_func, func, target_length * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_answer, answer, target_length * sizeof(int), hipMemcpyHostToDevice);
KMP<<<(target_length / pattern_length + M)/M, M>>>(d_pattern, d_target ,d_func, d_answer, pattern_length, target_length);
hipMemcpy(answer, d_answer, target_length * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsedTime, start, stop );
hipEventDestroy(start);
hipEventDestroy(stop);
printf("When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n", target_length, pattern_length, elapsedTime);
for(int i = 0; i < target_length; i++) {
if (answer[i] != -1) {
printf("Find a matching substring starting at: %d.\n", i);
}
}
hipFree(d_target);
hipFree(d_pattern);
hipFree(d_func);
hipFree(d_answer);
free(target);
free(pattern);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3KMPPcS_PiS0_ii
.globl _Z3KMPPcS_PiS0_ii
.p2align 8
.type _Z3KMPPcS_PiS0_ii,@function
_Z3KMPPcS_PiS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_mul_lo_u32 v3, v1, s8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s9, v3
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v2, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s8, -1
v_min_i32_e32 v2, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s9, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v2
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_14
.LBB0_4:
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 -1, v0
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v5, 31, v3
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
global_load_u8 v4, v[4:5], off
global_load_u8 v5, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v4, v5
s_and_saveexec_b32 s11, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off
.LBB0_7:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v0
v_add_nc_u32_e32 v1, 1, v3
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_eq_u32_e64 s8, v4
s_cbranch_execz .LBB0_10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s8, v1
v_sub_nc_u32_e32 v0, v3, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, 1, v0
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v3, v1
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, v4
.LBB0_12:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, 1, v3
s_branch .LBB0_3
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3KMPPcS_PiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3KMPPcS_PiS0_ii, .Lfunc_end0-_Z3KMPPcS_PiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3KMPPcS_PiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3KMPPcS_PiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* ECE 5720 Parallel Computing Final Project
* KMP parallel on MPI
* Feng Qi, fq26
* Ying Zong, yz887
* Cornell University
*
* Compile : /usr/local/cuda-8.0/bin/nvcc -arch=compute_35 -o cuda kmp-cuda.cu
* Run : ./cuda
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
// build the kmp table for the subsequent operations
void preKMP(char* pattern, int func[]) {
int m = strlen(pattern);
int k;
func[0] = -1;
for (int i = 1; i < m; i++) {
k = func[i - 1];
while (k >= 0) {
if (pattern[k] == pattern[i - 1]) {
break;
}
else {
k = func[k];
}
}
func[i] = k + 1;
}
}
// Kernel function. Implement the KMP algorithm
__global__ void KMP(char* pattern, char* target, int func[], int answer[], int pattern_length, int target_length) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int i = pattern_length * index;
int j = pattern_length * (index + 2) - 1;
if(i > target_length) {
return;
}
if(j > target_length) {
j = target_length;
}
int k = 0;
while (i < j) {
if (k == -1) {
i++;
k = 0;
} else if (target[i] == pattern[k]) {
i++;
k++;
if (k == pattern_length) {
answer[i - pattern_length] = i - pattern_length;
i = i - k + 1;
}
}
else {
k = func[k];
}
}
return;
}
int main(int argc, char* argv[]) {
int M = 4;
int n = 100000;
int m = 3;
char* target = (char*)malloc(n * sizeof(char));
char* pattern = (char*)malloc(m * sizeof(char));
printf("----- This is parallel results using KMP Algo on CUDA. -----\n");
FILE * file = fopen( "data.txt" , "r");
int CurrentIndex = 0;
while (CurrentIndex < 2) {
if (CurrentIndex == 0) {
fgets(target, n+1, file);
} else if (CurrentIndex == 1) {
fgets(pattern, m+1, file);
}
CurrentIndex++;
}
int target_length = strlen(target);
int pattern_length = strlen(pattern);
fclose(file);
char *d_target;
char *d_pattern;
int *func;
int *answer;
func = new int[target_length];
answer = new int[target_length];
int *d_func;
int *d_answer;
for(int i = 0; i < target_length; i++) {
answer[i] = -1;
}
preKMP(pattern, func);
hipEvent_t start, stop;
float elapsedTime;
hipEventCreate( &start );
hipEventCreate( &stop );
hipEventRecord( start, 0 );
hipMalloc((void **)&d_target, target_length * sizeof(char));
hipMalloc((void **)&d_pattern, pattern_length * sizeof(char));
hipMalloc((void **)&d_func, target_length * sizeof(int));
hipMalloc((void **)&d_answer, target_length * sizeof(int));
hipMemcpy(d_target, target, target_length * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_pattern, pattern, pattern_length * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_func, func, target_length * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_answer, answer, target_length * sizeof(int), hipMemcpyHostToDevice);
KMP<<<(target_length / pattern_length + M)/M, M>>>(d_pattern, d_target ,d_func, d_answer, pattern_length, target_length);
hipMemcpy(answer, d_answer, target_length * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
hipEventElapsedTime( &elapsedTime, start, stop );
hipEventDestroy(start);
hipEventDestroy(stop);
printf("When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n", target_length, pattern_length, elapsedTime);
for(int i = 0; i < target_length; i++) {
if (answer[i] != -1) {
printf("Find a matching substring starting at: %d.\n", i);
}
}
hipFree(d_target);
hipFree(d_pattern);
hipFree(d_func);
hipFree(d_answer);
free(target);
free(pattern);
return 0;
} | .text
.file "kmp-cuda.hip"
.globl _Z6preKMPPcPi # -- Begin function _Z6preKMPPcPi
.p2align 4, 0x90
.type _Z6preKMPPcPi,@function
_Z6preKMPPcPi: # @_Z6preKMPPcPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
callq strlen
movl $-1, (%rbx)
cmpl $2, %eax
jl .LBB0_6
# %bb.1: # %.lr.ph.preheader
movl %eax, %eax
movl $1, %ecx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
incl %edx
movl %edx, (%rbx,%rcx,4)
incq %rcx
cmpq %rax, %rcx
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
leaq -1(%rcx), %rsi
movq %rsi, %rdx
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rdx,4), %edx
testl %edx, %edx
js .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=2
movzbl (%r14,%rdx), %edi
cmpb (%r14,%rsi), %dil
jne .LBB0_3
jmp .LBB0_5
.LBB0_6: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6preKMPPcPi, .Lfunc_end0-_Z6preKMPPcPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__KMPPcS_PiS0_ii # -- Begin function _Z18__device_stub__KMPPcS_PiS0_ii
.p2align 4, 0x90
.type _Z18__device_stub__KMPPcS_PiS0_ii,@function
_Z18__device_stub__KMPPcS_PiS0_ii: # @_Z18__device_stub__KMPPcS_PiS0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3KMPPcS_PiS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z18__device_stub__KMPPcS_PiS0_ii, .Lfunc_end1-_Z18__device_stub__KMPPcS_PiS0_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100000, %edi # imm = 0x186A0
callq malloc
movq %rax, %rbx
movl $3, %edi
callq malloc
movq %rax, %r14
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
movl $1, %ebp
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
movq %r14, %rdi
movl $4, %esi
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movq %r15, %rdx
callq fgets
decl %ebp
jne .LBB2_5
.LBB2_1: # =>This Inner Loop Header: Depth=1
cmpl $1, %ebp
jne .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq %rbx, %rdi
movl $100001, %esi # imm = 0x186A1
jmp .LBB2_4
.LBB2_5:
movq %rbx, %rdi
callq strlen
movq %rax, %rbp
movq %r14, %rdi
callq strlen
movq %rax, 72(%rsp) # 8-byte Spill
movq %r15, %rdi
callq fclose
movslq %ebp, %r13
movq %r13, %rax
shrq $62, %rax
leaq (,%r13,4), %rcx
xorl %r12d, %r12d
negq %rax
sbbq %r12, %r12
movq %rcx, 80(%rsp) # 8-byte Spill
orq %rcx, %r12
movq %r12, %rdi
callq _Znam
movq %rax, %r15
movq %r12, %rdi
callq _Znam
movq %rax, %r12
testl %r13d, %r13d
jle .LBB2_7
# %bb.6: # %.lr.ph.preheader
movl %ebp, %edx
shlq $2, %rdx
movq %r12, %rdi
movl $255, %esi
callq memset@PLT
.LBB2_7: # %._crit_edge
movq %rbx, 64(%rsp) # 8-byte Spill
movq %rbp, 88(%rsp) # 8-byte Spill
movq %r14, %rdi
callq strlen
movl $-1, (%r15)
cmpl $2, %eax
jl .LBB2_13
# %bb.8: # %.lr.ph.preheader.i
movl %eax, %eax
movl $1, %ecx
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_9 Depth=1
incl %edx
movl %edx, (%r15,%rcx,4)
incq %rcx
cmpq %rax, %rcx
je .LBB2_13
.LBB2_9: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
leaq -1(%rcx), %rsi
movq %rsi, %rdx
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rdx,4), %edx
testl %edx, %edx
js .LBB2_12
# %bb.11: # in Loop: Header=BB2_10 Depth=2
movzbl (%r14,%rdx), %edi
cmpb (%r14,%rsi), %dil
jne .LBB2_10
jmp .LBB2_12
.LBB2_13: # %_Z6preKMPPcPi.exit
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq 72(%rsp), %rbx # 4-byte Folded Reload
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq 80(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
movq 72(%rsp), %r13 # 8-byte Reload
cltd
idivl %r13d
# kill: def $eax killed $eax def $rax
leal 4(%rax), %ecx
leal 7(%rax), %edi
testl %ecx, %ecx
cmovnsl %ecx, %edi
sarl $2, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $4, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 88(%rsp), %r15 # 8-byte Reload
jne .LBB2_15
# %bb.14:
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movl %r13d, 60(%rsp)
movl %r15d, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 60(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z3KMPPcS_PiS0_ii, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %r15d, %esi
movl %r13d, %edx
movb $1, %al
callq printf
testl %r15d, %r15d
movq 64(%rsp), %rbx # 8-byte Reload
jle .LBB2_20
# %bb.16: # %.lr.ph68.preheader
movl %r15d, %r13d
xorl %r15d, %r15d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
incq %r15
cmpq %r15, %r13
je .LBB2_20
.LBB2_17: # %.lr.ph68
# =>This Inner Loop Header: Depth=1
cmpl $-1, (%r12,%r15,4)
je .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
jmp .LBB2_19
.LBB2_20: # %._crit_edge69
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3KMPPcS_PiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3KMPPcS_PiS0_ii,@object # @_Z3KMPPcS_PiS0_ii
.section .rodata,"a",@progbits
.globl _Z3KMPPcS_PiS0_ii
.p2align 3, 0x0
_Z3KMPPcS_PiS0_ii:
.quad _Z18__device_stub__KMPPcS_PiS0_ii
.size _Z3KMPPcS_PiS0_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "data.txt"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n"
.size .L.str.3, 83
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Find a matching substring starting at: %d.\n"
.size .L.str.4, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3KMPPcS_PiS0_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "----- This is parallel results using KMP Algo on CUDA. -----"
.size .Lstr, 61
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__KMPPcS_PiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3KMPPcS_PiS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3KMPPcS_PiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD R2, R3, 0x2, R0 ; /* 0x0000000203027824 */
/* 0x000fca00078e0200 */
/*0090*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ IMNMX R7, R2, c[0x0][0x184], PT ; /* 0x0000610002077a17 */
/* 0x000fc80003800200 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x020fe20003f05270 */
/*0100*/ BSSY B0, 0x2d0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*0110*/ @!P0 BRA 0x2a0 ; /* 0x0000018000008947 */
/* 0x001fea0003800000 */
/*0120*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe40007f1e0ff */
/*0130*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fe40000011406 */
/*0140*/ IADD3 R2, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fe40007f3e0ff */
/*0150*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fe400000f0eff */
/*0160*/ IADD3.X R3, R9, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590009037a10 */
/* 0x000fc80000ffe4ff */
/*0170*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1100 */
/*0180*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0190*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*01a0*/ @!P0 BRA 0x1f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01b0*/ LEA R2, P0, R6, c[0x0][0x170], 0x2 ; /* 0x00005c0006027a11 */
/* 0x000fc800078010ff */
/*01c0*/ LEA.HI.X R3, R6, c[0x0][0x174], R9, 0x2, P0 ; /* 0x00005d0006037a11 */
/* 0x000fca00000f1409 */
/*01d0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*01e0*/ BRA 0x2c0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0200*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 BRA 0x2c0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R5, R0, -c[0x0][0x180], RZ ; /* 0x8000600000057a10 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*0260*/ IADD3 R0, R5.reuse, 0x1, RZ ; /* 0x0000000105007810 */
/* 0x040fe20007ffe0ff */
/*0270*/ IMAD.WIDE R2, R5, R2, c[0x0][0x178] ; /* 0x00005e0005027625 */
/* 0x000fca00078e0202 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0290*/ BRA 0x2c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*02a0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06270 */
/*02e0*/ @!P0 BRA 0xf0 ; /* 0xfffffe0000008947 */
/* 0x000fea000383ffff */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3KMPPcS_PiS0_ii
.globl _Z3KMPPcS_PiS0_ii
.p2align 8
.type _Z3KMPPcS_PiS0_ii,@function
_Z3KMPPcS_PiS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_mul_lo_u32 v3, v1, s8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s9, v3
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v2, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s8, -1
v_min_i32_e32 v2, s9, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s9, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v2
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_14
.LBB0_4:
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 -1, v0
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_12
v_ashrrev_i32_e32 v5, 31, v3
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
global_load_u8 v4, v[4:5], off
global_load_u8 v5, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v4, v5
s_and_saveexec_b32 s11, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off
.LBB0_7:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v0
v_add_nc_u32_e32 v1, 1, v3
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_eq_u32_e64 s8, v4
s_cbranch_execz .LBB0_10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s8, v1
v_sub_nc_u32_e32 v0, v3, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, 1, v0
v_lshlrev_b64 v[6:7], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v3, v1
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, v4
.LBB0_12:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, 1, v3
s_branch .LBB0_3
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3KMPPcS_PiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3KMPPcS_PiS0_ii, .Lfunc_end0-_Z3KMPPcS_PiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3KMPPcS_PiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3KMPPcS_PiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00189291_00000000-6_kmp-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6preKMPPcPi
.type _Z6preKMPPcPi, @function
_Z6preKMPPcPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rsi, %rbx
call strlen@PLT
movl $-1, (%rbx)
cmpl $1, %eax
jle .L3
leal -2(%rax), %edi
movl $0, %esi
jmp .L7
.L5:
addl $1, %eax
movl %eax, 4(%rbx,%rsi,4)
leaq 1(%rsi), %rax
cmpq %rdi, %rsi
je .L3
movq %rax, %rsi
.L7:
movl (%rbx,%rsi,4), %eax
testl %eax, %eax
js .L5
movzbl 0(%rbp,%rsi), %ecx
.L6:
movslq %eax, %rdx
cmpb %cl, 0(%rbp,%rdx)
je .L5
movl (%rbx,%rdx,4), %eax
testl %eax, %eax
jns .L6
jmp .L5
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6preKMPPcPi, .-_Z6preKMPPcPi
.globl _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
.type _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii, @function
_Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3KMPPcS_PiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii, .-_Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
.globl _Z3KMPPcS_PiS0_ii
.type _Z3KMPPcS_PiS0_ii, @function
_Z3KMPPcS_PiS0_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3KMPPcS_PiS0_ii, .-_Z3KMPPcS_PiS0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "----- This is parallel results using KMP Algo on CUDA. -----\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "data.txt"
.section .rodata.str1.8
.align 8
.LC3:
.string "When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n"
.align 8
.LC4:
.string "Find a matching substring starting at: %d.\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $100000, %edi
call malloc@PLT
movq %rax, %r14
movl $3, %edi
call malloc@PLT
movq %rax, %r12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rcx
movl $100001, %edx
movl $100000, %esi
movq %r14, %rdi
call __fgets_chk@PLT
movq %rbx, %rcx
movl $4, %edx
movl $3, %esi
movq %r12, %rdi
call __fgets_chk@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rbp
movl %eax, (%rsp)
movq %r12, %rdi
call strlen@PLT
movq %rax, 16(%rsp)
movl %eax, 4(%rsp)
movq %rbx, %rdi
call fclose@PLT
movslq %ebp, %r15
movabsq $2305843009213693950, %rax
cmpq %r15, %rax
jb .L20
leaq 0(,%r15,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbx
testl %ebp, %ebp
jle .L22
leal -1(%rbp), %edx
leaq 4(%rax,%rdx,4), %rdx
.L24:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
.L22:
movq 8(%rsp), %rsi
movq %r12, %rdi
call _Z6preKMPPcPi
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movslq 16(%rsp), %rax
leaq 40(%rsp), %rdi
movq %rax, 24(%rsp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 24(%rsp), %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl (%rsp), %eax
cltd
idivl 4(%rsp)
leal 7(%rax), %edx
addl $4, %eax
cmovns %eax, %edx
sarl $2, %edx
movl %edx, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
movl $2, %ecx
movq %r13, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L26
leal -1(%rbp), %r13d
movl $0, %ebp
leaq .LC4(%rip), %r15
jmp .L28
.L20:
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L33:
movl %ebp, %r9d
movl 16(%rsp), %r8d
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z31__device_stub__Z3KMPPcS_PiS0_iiPcS_PiS0_ii
jmp .L25
.L27:
leaq 1(%rbp), %rax
cmpq %r13, %rbp
je .L26
movq %rax, %rbp
.L28:
cmpl $-1, (%rbx,%rbp,4)
je .L27
movl %ebp, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L26:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z3KMPPcS_PiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3KMPPcS_PiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kmp-cuda.hip"
.globl _Z6preKMPPcPi # -- Begin function _Z6preKMPPcPi
.p2align 4, 0x90
.type _Z6preKMPPcPi,@function
_Z6preKMPPcPi: # @_Z6preKMPPcPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
callq strlen
movl $-1, (%rbx)
cmpl $2, %eax
jl .LBB0_6
# %bb.1: # %.lr.ph.preheader
movl %eax, %eax
movl $1, %ecx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
incl %edx
movl %edx, (%rbx,%rcx,4)
incq %rcx
cmpq %rax, %rcx
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
leaq -1(%rcx), %rsi
movq %rsi, %rdx
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rdx,4), %edx
testl %edx, %edx
js .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=2
movzbl (%r14,%rdx), %edi
cmpb (%r14,%rsi), %dil
jne .LBB0_3
jmp .LBB0_5
.LBB0_6: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6preKMPPcPi, .Lfunc_end0-_Z6preKMPPcPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__KMPPcS_PiS0_ii # -- Begin function _Z18__device_stub__KMPPcS_PiS0_ii
.p2align 4, 0x90
.type _Z18__device_stub__KMPPcS_PiS0_ii,@function
_Z18__device_stub__KMPPcS_PiS0_ii: # @_Z18__device_stub__KMPPcS_PiS0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3KMPPcS_PiS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z18__device_stub__KMPPcS_PiS0_ii, .Lfunc_end1-_Z18__device_stub__KMPPcS_PiS0_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100000, %edi # imm = 0x186A0
callq malloc
movq %rax, %rbx
movl $3, %edi
callq malloc
movq %rax, %r14
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
movl $1, %ebp
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
movq %r14, %rdi
movl $4, %esi
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movq %r15, %rdx
callq fgets
decl %ebp
jne .LBB2_5
.LBB2_1: # =>This Inner Loop Header: Depth=1
cmpl $1, %ebp
jne .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq %rbx, %rdi
movl $100001, %esi # imm = 0x186A1
jmp .LBB2_4
.LBB2_5:
movq %rbx, %rdi
callq strlen
movq %rax, %rbp
movq %r14, %rdi
callq strlen
movq %rax, 72(%rsp) # 8-byte Spill
movq %r15, %rdi
callq fclose
movslq %ebp, %r13
movq %r13, %rax
shrq $62, %rax
leaq (,%r13,4), %rcx
xorl %r12d, %r12d
negq %rax
sbbq %r12, %r12
movq %rcx, 80(%rsp) # 8-byte Spill
orq %rcx, %r12
movq %r12, %rdi
callq _Znam
movq %rax, %r15
movq %r12, %rdi
callq _Znam
movq %rax, %r12
testl %r13d, %r13d
jle .LBB2_7
# %bb.6: # %.lr.ph.preheader
movl %ebp, %edx
shlq $2, %rdx
movq %r12, %rdi
movl $255, %esi
callq memset@PLT
.LBB2_7: # %._crit_edge
movq %rbx, 64(%rsp) # 8-byte Spill
movq %rbp, 88(%rsp) # 8-byte Spill
movq %r14, %rdi
callq strlen
movl $-1, (%r15)
cmpl $2, %eax
jl .LBB2_13
# %bb.8: # %.lr.ph.preheader.i
movl %eax, %eax
movl $1, %ecx
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_9 Depth=1
incl %edx
movl %edx, (%r15,%rcx,4)
incq %rcx
cmpq %rax, %rcx
je .LBB2_13
.LBB2_9: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
leaq -1(%rcx), %rsi
movq %rsi, %rdx
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rdx,4), %edx
testl %edx, %edx
js .LBB2_12
# %bb.11: # in Loop: Header=BB2_10 Depth=2
movzbl (%r14,%rdx), %edi
cmpb (%r14,%rsi), %dil
jne .LBB2_10
jmp .LBB2_12
.LBB2_13: # %_Z6preKMPPcPi.exit
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq 72(%rsp), %rbx # 4-byte Folded Reload
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq 80(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
movq 72(%rsp), %r13 # 8-byte Reload
cltd
idivl %r13d
# kill: def $eax killed $eax def $rax
leal 4(%rax), %ecx
leal 7(%rax), %edi
testl %ecx, %ecx
cmovnsl %ecx, %edi
sarl $2, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $4, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 88(%rsp), %r15 # 8-byte Reload
jne .LBB2_15
# %bb.14:
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movl %r13d, 60(%rsp)
movl %r15d, 56(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 60(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z3KMPPcS_PiS0_ii, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %r15d, %esi
movl %r13d, %edx
movb $1, %al
callq printf
testl %r15d, %r15d
movq 64(%rsp), %rbx # 8-byte Reload
jle .LBB2_20
# %bb.16: # %.lr.ph68.preheader
movl %r15d, %r13d
xorl %r15d, %r15d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
incq %r15
cmpq %r15, %r13
je .LBB2_20
.LBB2_17: # %.lr.ph68
# =>This Inner Loop Header: Depth=1
cmpl $-1, (%r12,%r15,4)
je .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movl $.L.str.4, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
jmp .LBB2_19
.LBB2_20: # %._crit_edge69
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3KMPPcS_PiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3KMPPcS_PiS0_ii,@object # @_Z3KMPPcS_PiS0_ii
.section .rodata,"a",@progbits
.globl _Z3KMPPcS_PiS0_ii
.p2align 3, 0x0
_Z3KMPPcS_PiS0_ii:
.quad _Z18__device_stub__KMPPcS_PiS0_ii
.size _Z3KMPPcS_PiS0_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "data.txt"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "When the target length is %d, pattern length is %d, the elapsed time is %0.3f ms.\n"
.size .L.str.3, 83
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Find a matching substring starting at: %d.\n"
.size .L.str.4, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3KMPPcS_PiS0_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "----- This is parallel results using KMP Algo on CUDA. -----"
.size .Lstr, 61
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__KMPPcS_PiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3KMPPcS_PiS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//=============================================================================
// FILE: mytoy.cu
// AUTHORS: Raul Segura & Manuel Ujaldon (copyright 2014)
// Look for the string "MU" whenever Manuel suggests you to introduce changes
// Feel free to change some other parts of the code too (at your own risk)
//=============================================================================
//=============================================================================
// CUDA functions.
//=============================================================================
//Error handler for CUDA functions.
__global__ void kernelAdd(float *dvalues, int numOperations, int firstInd, int nextColInd)
{
int vi = firstInd + blockIdx.x * blockDim.x + threadIdx.x;
// "numOperations" is the 2nd input parameter to our executable
if (vi < nextColInd) {
for (int j=0; j<numOperations; ++j) {
// The operation performed on each nonzero of our sparse matrix:
dvalues[vi] *=dvalues[vi]+dvalues[vi]*dvalues[vi]; // POINT 3: Choices you may try here:
} // *= (for multiply), /= (for division),
} // or you may investigate some other :-)
} | code for sm_80
Function : _Z9kernelAddPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], !P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0004706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*00c0*/ IADD3 R0, R4, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*00e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*00f0*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fd600078ec0ff */
/*0100*/ @!P0 BRA 0x5c0 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x001fc80007ffe1ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x510 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x3b0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x020fe20000000005 */
/*0190*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ FMUL R4, R4, R5 ; /* 0x0000000504047220 */
/* 0x000fe20000400000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*01c0*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*01d0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*01e0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*01f0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0200*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0210*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0220*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0230*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0250*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0260*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0270*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0280*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0290*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*02a0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*02b0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*02c0*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*02d0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*02e0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*02f0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0300*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0310*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0320*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0330*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0340*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0350*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0360*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0370*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0380*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0390*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe20000400000 */
/*03a0*/ @P1 BRA 0x180 ; /* 0xfffffdd000001947 */
/* 0x000fea000383ffff */
/*03b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*03c0*/ @!P1 BRA 0x4f0 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*03d0*/ FFMA R4, R5.reuse, R5, R5 ; /* 0x0000000505047223 */
/* 0x060fe20000000005 */
/*03e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03f0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0400*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0410*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0420*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0430*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0440*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0450*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0460*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0470*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0480*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0490*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*04a0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*04b0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*04c0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*04d0*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*04e0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe40000400000 */
/*04f0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0500*/ @!P0 BRA 0x5c0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0510*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x020fe20000000005 */
/*0520*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*0530*/ FMUL R4, R4, R5 ; /* 0x0000000504047220 */
/* 0x000fe20000400000 */
/*0540*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0550*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0560*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0570*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0580*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0590*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*05a0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe20000400000 */
/*05b0*/ @P0 BRA 0x510 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*05c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*05d0*/ @!P0 BRA 0x630 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x020fc60000000005 */
/*0600*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0610*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fd80000400000 */
/*0620*/ @P0 BRA 0x5e0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0630*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BRA 0x650; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//=============================================================================
// FILE: mytoy.cu
// AUTHORS: Raul Segura & Manuel Ujaldon (copyright 2014)
// Look for the string "MU" whenever Manuel suggests you to introduce changes
// Feel free to change some other parts of the code too (at your own risk)
//=============================================================================
//=============================================================================
// CUDA functions.
//=============================================================================
//Error handler for CUDA functions.
__global__ void kernelAdd(float *dvalues, int numOperations, int firstInd, int nextColInd)
{
int vi = firstInd + blockIdx.x * blockDim.x + threadIdx.x;
// "numOperations" is the 2nd input parameter to our executable
if (vi < nextColInd) {
for (int j=0; j<numOperations; ++j) {
// The operation performed on each nonzero of our sparse matrix:
dvalues[vi] *=dvalues[vi]+dvalues[vi]*dvalues[vi]; // POINT 3: Choices you may try here:
} // *= (for multiply), /= (for division),
} // or you may investigate some other :-)
} | .file "tmpxft_00149f04_00000000-6_kernelAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9kernelAddPfiiiPfiii
.type _Z31__device_stub__Z9kernelAddPfiiiPfiii, @function
_Z31__device_stub__Z9kernelAddPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9kernelAddPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9kernelAddPfiiiPfiii, .-_Z31__device_stub__Z9kernelAddPfiiiPfiii
.globl _Z9kernelAddPfiii
.type _Z9kernelAddPfiii, @function
_Z9kernelAddPfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9kernelAddPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9kernelAddPfiii, .-_Z9kernelAddPfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9kernelAddPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kernelAddPfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//=============================================================================
// FILE: mytoy.cu
// AUTHORS: Raul Segura & Manuel Ujaldon (copyright 2014)
// Look for the string "MU" whenever Manuel suggests you to introduce changes
// Feel free to change some other parts of the code too (at your own risk)
//=============================================================================
//=============================================================================
// CUDA functions.
//=============================================================================
//Error handler for CUDA functions.
__global__ void kernelAdd(float *dvalues, int numOperations, int firstInd, int nextColInd)
{
int vi = firstInd + blockIdx.x * blockDim.x + threadIdx.x;
// "numOperations" is the 2nd input parameter to our executable
if (vi < nextColInd) {
for (int j=0; j<numOperations; ++j) {
// The operation performed on each nonzero of our sparse matrix:
dvalues[vi] *=dvalues[vi]+dvalues[vi]*dvalues[vi]; // POINT 3: Choices you may try here:
} // *= (for multiply), /= (for division),
} // or you may investigate some other :-)
} | #include <hip/hip_runtime.h>
#include "includes.h"
//=============================================================================
// FILE: mytoy.cu
// AUTHORS: Raul Segura & Manuel Ujaldon (copyright 2014)
// Look for the string "MU" whenever Manuel suggests you to introduce changes
// Feel free to change some other parts of the code too (at your own risk)
//=============================================================================
//=============================================================================
// CUDA functions.
//=============================================================================
//Error handler for CUDA functions.
__global__ void kernelAdd(float *dvalues, int numOperations, int firstInd, int nextColInd)
{
int vi = firstInd + blockIdx.x * blockDim.x + threadIdx.x;
// "numOperations" is the 2nd input parameter to our executable
if (vi < nextColInd) {
for (int j=0; j<numOperations; ++j) {
// The operation performed on each nonzero of our sparse matrix:
dvalues[vi] *=dvalues[vi]+dvalues[vi]*dvalues[vi]; // POINT 3: Choices you may try here:
} // *= (for multiply), /= (for division),
} // or you may investigate some other :-)
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//=============================================================================
// FILE: mytoy.cu
// AUTHORS: Raul Segura & Manuel Ujaldon (copyright 2014)
// Look for the string "MU" whenever Manuel suggests you to introduce changes
// Feel free to change some other parts of the code too (at your own risk)
//=============================================================================
//=============================================================================
// CUDA functions.
//=============================================================================
//Error handler for CUDA functions.
__global__ void kernelAdd(float *dvalues, int numOperations, int firstInd, int nextColInd)
{
int vi = firstInd + blockIdx.x * blockDim.x + threadIdx.x;
// "numOperations" is the 2nd input parameter to our executable
if (vi < nextColInd) {
for (int j=0; j<numOperations; ++j) {
// The operation performed on each nonzero of our sparse matrix:
dvalues[vi] *=dvalues[vi]+dvalues[vi]*dvalues[vi]; // POINT 3: Choices you may try here:
} // *= (for multiply), /= (for division),
} // or you may investigate some other :-)
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9kernelAddPfiii
.globl _Z9kernelAddPfiii
.p2align 8
.type _Z9kernelAddPfiii,@function
_Z9kernelAddPfiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s2, 0
s_mul_i32 s15, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
s_cselect_b32 s3, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
.LBB0_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_fma_f32 v3, v2, v2, v2
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
s_cbranch_scc1 .LBB0_2
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kernelAddPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9kernelAddPfiii, .Lfunc_end0-_Z9kernelAddPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kernelAddPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kernelAddPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//=============================================================================
// FILE: mytoy.cu
// AUTHORS: Raul Segura & Manuel Ujaldon (copyright 2014)
// Look for the string "MU" whenever Manuel suggests you to introduce changes
// Feel free to change some other parts of the code too (at your own risk)
//=============================================================================
//=============================================================================
// CUDA functions.
//=============================================================================
//Error handler for CUDA functions.
__global__ void kernelAdd(float *dvalues, int numOperations, int firstInd, int nextColInd)
{
int vi = firstInd + blockIdx.x * blockDim.x + threadIdx.x;
// "numOperations" is the 2nd input parameter to our executable
if (vi < nextColInd) {
for (int j=0; j<numOperations; ++j) {
// The operation performed on each nonzero of our sparse matrix:
dvalues[vi] *=dvalues[vi]+dvalues[vi]*dvalues[vi]; // POINT 3: Choices you may try here:
} // *= (for multiply), /= (for division),
} // or you may investigate some other :-)
} | .text
.file "kernelAdd.hip"
.globl _Z24__device_stub__kernelAddPfiii # -- Begin function _Z24__device_stub__kernelAddPfiii
.p2align 4, 0x90
.type _Z24__device_stub__kernelAddPfiii,@function
_Z24__device_stub__kernelAddPfiii: # @_Z24__device_stub__kernelAddPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9kernelAddPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__kernelAddPfiii, .Lfunc_end0-_Z24__device_stub__kernelAddPfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kernelAddPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9kernelAddPfiii,@object # @_Z9kernelAddPfiii
.section .rodata,"a",@progbits
.globl _Z9kernelAddPfiii
.p2align 3, 0x0
_Z9kernelAddPfiii:
.quad _Z24__device_stub__kernelAddPfiii
.size _Z9kernelAddPfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9kernelAddPfiii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kernelAddPfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kernelAddPfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9kernelAddPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], !P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0004706670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*00c0*/ IADD3 R0, R4, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*00e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*00f0*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fd600078ec0ff */
/*0100*/ @!P0 BRA 0x5c0 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x001fc80007ffe1ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x510 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x3b0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x020fe20000000005 */
/*0190*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ FMUL R4, R4, R5 ; /* 0x0000000504047220 */
/* 0x000fe20000400000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*01c0*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*01d0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*01e0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*01f0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0200*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0210*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0220*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0230*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0250*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0260*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0270*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0280*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0290*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*02a0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*02b0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*02c0*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*02d0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*02e0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*02f0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0300*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0310*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0320*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0330*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0340*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0350*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0360*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0370*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0380*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0390*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe20000400000 */
/*03a0*/ @P1 BRA 0x180 ; /* 0xfffffdd000001947 */
/* 0x000fea000383ffff */
/*03b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*03c0*/ @!P1 BRA 0x4f0 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*03d0*/ FFMA R4, R5.reuse, R5, R5 ; /* 0x0000000505047223 */
/* 0x060fe20000000005 */
/*03e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*03f0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0400*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0410*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0420*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0430*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0440*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0450*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0460*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0470*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0480*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0490*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*04a0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*04b0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*04c0*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*04d0*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*04e0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe40000400000 */
/*04f0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0500*/ @!P0 BRA 0x5c0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0510*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x020fe20000000005 */
/*0520*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*0530*/ FMUL R4, R4, R5 ; /* 0x0000000504047220 */
/* 0x000fe20000400000 */
/*0540*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0550*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*0560*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fc80000400000 */
/*0570*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x000fc80000000005 */
/*0580*/ FMUL R4, R5, R4 ; /* 0x0000000405047220 */
/* 0x000fc80000400000 */
/*0590*/ FFMA R5, R4, R4, R4 ; /* 0x0000000404057223 */
/* 0x000fc80000000004 */
/*05a0*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fe20000400000 */
/*05b0*/ @P0 BRA 0x510 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*05c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*05d0*/ @!P0 BRA 0x630 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*05e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ FFMA R4, R5, R5, R5 ; /* 0x0000000505047223 */
/* 0x020fc60000000005 */
/*0600*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0610*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x000fd80000400000 */
/*0620*/ @P0 BRA 0x5e0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0630*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BRA 0x650; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9kernelAddPfiii
.globl _Z9kernelAddPfiii
.p2align 8
.type _Z9kernelAddPfiii,@function
_Z9kernelAddPfiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s2, 0
s_mul_i32 s15, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
s_cselect_b32 s3, -1, 0
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_and_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
.LBB0_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_fma_f32 v3, v2, v2, v2
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v3
s_cbranch_scc1 .LBB0_2
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kernelAddPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9kernelAddPfiii, .Lfunc_end0-_Z9kernelAddPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kernelAddPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kernelAddPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00149f04_00000000-6_kernelAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9kernelAddPfiiiPfiii
.type _Z31__device_stub__Z9kernelAddPfiiiPfiii, @function
_Z31__device_stub__Z9kernelAddPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9kernelAddPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9kernelAddPfiiiPfiii, .-_Z31__device_stub__Z9kernelAddPfiiiPfiii
.globl _Z9kernelAddPfiii
.type _Z9kernelAddPfiii, @function
_Z9kernelAddPfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9kernelAddPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9kernelAddPfiii, .-_Z9kernelAddPfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9kernelAddPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kernelAddPfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelAdd.hip"
.globl _Z24__device_stub__kernelAddPfiii # -- Begin function _Z24__device_stub__kernelAddPfiii
.p2align 4, 0x90
.type _Z24__device_stub__kernelAddPfiii,@function
_Z24__device_stub__kernelAddPfiii: # @_Z24__device_stub__kernelAddPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9kernelAddPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__kernelAddPfiii, .Lfunc_end0-_Z24__device_stub__kernelAddPfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kernelAddPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9kernelAddPfiii,@object # @_Z9kernelAddPfiii
.section .rodata,"a",@progbits
.globl _Z9kernelAddPfiii
.p2align 3, 0x0
_Z9kernelAddPfiii:
.quad _Z24__device_stub__kernelAddPfiii
.size _Z9kernelAddPfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9kernelAddPfiii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kernelAddPfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kernelAddPfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include"finitedifference.cuh"
#define field(a,b) field[ (a)*Zm + (b) ]
#define diffield(a,b) diffield[ (a)*Zm + (b) ]
#define coef(a,b) coef[ (a)*Zm + (b) ]
#define difffield(a,b) difffield[ (a)*Zm + (b)]
__global__ void compute_spatial_X_derivative(float* difffield, float* field, int Xm, int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
while(tx < Xm-2)
{
while(ty < Zm-2)
{
difffield(tx+1,ty+1) = 0.5*( field( tx + 2, ty + 1 )-field( tx ,ty + 1 ));
//printf("%d: %d => %f, %f, %f, %d, %d\n",tx,ty,difffield(tx+1,ty+1),field( tx + 2, ty + 1 ), field( tx ,ty + 1 ),Xm,Ym);
//printf("%d: %d=> %f\n",tx,ty,field(tx,ty));
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x * gridDim.x;
}
}
__global__ void compute_spatial_Z_derivative(float* difffield, float* field, int Xm, int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
while(tx < Xm - 2)
{
while(ty < Zm - 2)
{
difffield( tx + 1,ty + 1 ) = 0.5*(field( tx + 1 , ty + 2 )-field( tx + 1 ,ty ));
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x*gridDim.x;
}
}
__global__ void update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float *dev_xx_x,
float *dev_zz_z,
float *dev_xz_x,
float *dev_xz_z,
float *dev_ux_x,
float *dev_ux_z,
float *dev_uz_x,
float *dev_uz_z,
float *lambda,
float *mu,
float *rho,
float dt,
int Xm,
int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
int thread = tx*Zm + ty;
while(tx < Xm )
{
while(ty < Zm )
{
stress_xx[thread] += dt*(dev_ux_x[thread]*(lambda[thread]+2.0*mu[thread]) + dev_uz_z[thread]*lambda[thread]);
stress_zz[thread] += dt*(dev_uz_z[thread]*(lambda[thread]+2.0*mu[thread]) + dev_ux_x[thread]*lambda[thread]);
stress_xz[thread] += dt*mu[thread]*(dev_uz_x[thread] + dev_ux_z[thread]);
dev_veloc_u[thread] += dt*(1./rho[thread])*(dev_xx_x[thread] + dev_xz_z[thread]);
dev_veloc_w[thread] += dt*(1./rho[thread])*(dev_zz_z[thread] + dev_xz_x[thread]);
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x*gridDim.x;
}
}
void compute_derivative(int direction, float *inputfield, float *derivative, int Xm, int Zm, dim3 num_blocks, dim3 thread_per_block, cudaStream_t custream)
{
if(direction == XDERIVATIVE)
{
//printf("compute X derivative!\n");
compute_spatial_X_derivative<<<num_blocks, thread_per_block, 0, custream>>>(derivative, inputfield, Xm, Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
}
if(direction == ZDERIVATIVE)
{
compute_spatial_Z_derivative<<<num_blocks, thread_per_block,0, custream>>>(derivative, inputfield, Xm, Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
}
}
void call_update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float* dev_xx_x,
float* dev_zz_z,
float* dev_xz_x,
float* dev_xz_z,
float* dev_ux_x,
float* dev_ux_z,
float* dev_uz_x,
float* dev_uz_z,
float* lambda,
float* mu,
float* rho,
float dt,
int Xm,
int Zm,
dim3 num_blocks,
dim3 thread_per_block,
cudaStream_t custream)
{
update_field<<<num_blocks, thread_per_block, 0, custream>>>( dev_veloc_u,
dev_veloc_w,
stress_xx,
stress_zz,
stress_xz,
dev_xx_x,
dev_zz_z,
dev_xz_x,
dev_xz_z,
dev_ux_x,
dev_ux_z,
dev_uz_x,
dev_uz_z,
lambda,
mu,
rho,
dt,
Xm,
Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
} | code for sm_80
Function : _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R44, SR_CTAID.X ; /* 0x00000000002c7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R45, SR_CTAID.Y ; /* 0x00000000002d7919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R44, R44, c[0x0][0x0], R3 ; /* 0x000000002c2c7a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R44, c[0x0][0x1e4], PT ; /* 0x000079002c007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R45, R45, c[0x0][0x4], R0 ; /* 0x000001002d2d7a24 */
/* 0x002fd800078e0200 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ F2F.F64.F32 R2, c[0x0][0x1e0] ; /* 0x0000780000027b10 */
/* 0x000e220000201800 */
/*00a0*/ HFMA2.MMA R35, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff237435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R34, R44, c[0x0][0x1e8], R45 ; /* 0x00007a002c227a24 */
/* 0x000fe200078e022d */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R34, R35, c[0x0][0x1a8] ; /* 0x00006a0022047625 */
/* 0x000fc800078e0223 */
/*00e0*/ IMAD.WIDE R6, R34, R35, c[0x0][0x1c8] ; /* 0x0000720022067625 */
/* 0x000fc800078e0223 */
/*00f0*/ IMAD.WIDE R8, R34, R35, c[0x0][0x1d0] ; /* 0x0000740022087625 */
/* 0x000fc800078e0223 */
/*0100*/ IMAD.WIDE R10, R34, R35, c[0x0][0x1c0] ; /* 0x00007000220a7625 */
/* 0x000fc800078e0223 */
/*0110*/ IMAD.WIDE R12, R34, R35, c[0x0][0x170] ; /* 0x00005c00220c7625 */
/* 0x000fc800078e0223 */
/*0120*/ IMAD.WIDE R14, R34, R35, c[0x0][0x178] ; /* 0x00005e00220e7625 */
/* 0x000fc800078e0223 */
/*0130*/ IMAD.WIDE R16, R34, R35, c[0x0][0x1b8] ; /* 0x00006e0022107625 */
/* 0x000fc800078e0223 */
/*0140*/ IMAD.WIDE R18, R34, R35, c[0x0][0x1b0] ; /* 0x00006c0022127625 */
/* 0x000fc800078e0223 */
/*0150*/ IMAD.WIDE R20, R34, R35, c[0x0][0x180] ; /* 0x0000600022147625 */
/* 0x000fc800078e0223 */
/*0160*/ IMAD.WIDE R22, R34, R35, c[0x0][0x1d8] ; /* 0x0000760022167625 */
/* 0x000fc800078e0223 */
/*0170*/ IMAD.WIDE R24, R34, R35, c[0x0][0x188] ; /* 0x0000620022187625 */
/* 0x000fc800078e0223 */
/*0180*/ IMAD.WIDE R26, R34, R35, c[0x0][0x1a0] ; /* 0x00006800221a7625 */
/* 0x000fc800078e0223 */
/*0190*/ IMAD.WIDE R28, R34, R35, c[0x0][0x160] ; /* 0x00005800221c7625 */
/* 0x000fc800078e0223 */
/*01a0*/ IMAD.WIDE R30, R34, R35, c[0x0][0x190] ; /* 0x00006400221e7625 */
/* 0x000fc800078e0223 */
/*01b0*/ IMAD.WIDE R32, R34, R35, c[0x0][0x198] ; /* 0x0000660022207625 */
/* 0x000fc800078e0223 */
/*01c0*/ IMAD.WIDE R34, R34, R35, c[0x0][0x168] ; /* 0x00005a0022227625 */
/* 0x001fc800078e0223 */
/*01d0*/ ISETP.GE.AND P1, PT, R45, c[0x0][0x1e8], PT ; /* 0x00007a002d007a0c */
/* 0x000fe20003f26270 */
/*01e0*/ IMAD.MOV.U32 R37, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff257624 */
/* 0x001fe200078e00ff */
/*01f0*/ BSSY B0, 0x8a0 ; /* 0x000006a000007945 */
/* 0x000fe60003800000 */
/*0200*/ IMAD R44, R37, c[0x0][0xc], R44 ; /* 0x00000300252c7a24 */
/* 0x000fca00078e022c */
/*0210*/ ISETP.GE.AND P0, PT, R44, c[0x0][0x1e4], PT ; /* 0x000079002c007a0c */
/* 0x000fc60003f06270 */
/*0220*/ @P1 BRA 0x890 ; /* 0x0000066000001947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R42, [R8.64] ; /* 0x00000004082a7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R40, [R6.64] ; /* 0x0000000406287981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R41, [R10.64] ; /* 0x000000040a297981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R43, [R12.64] ; /* 0x000000040c2b7981 */
/* 0x000f22000c1e1900 */
/*0280*/ F2F.F64.F32 R36, R42 ; /* 0x0000002a00247310 */
/* 0x005ff00000201800 */
/*0290*/ F2F.F64.F32 R38, R40 ; /* 0x0000002800267310 */
/* 0x008e240000201800 */
/*02a0*/ DFMA R36, R36, 2, R38 ; /* 0x400000002424782b */
/* 0x0018040000000026 */
/*02b0*/ FMUL R38, R40, R41 ; /* 0x0000002928267220 */
/* 0x010fc80000400000 */
/*02c0*/ F2F.F64.F32 R40, R0 ; /* 0x0000000000287310 */
/* 0x020ff00000201800 */
/*02d0*/ F2F.F64.F32 R38, R38 ; /* 0x0000002600267310 */
/* 0x000e240000201800 */
/*02e0*/ DFMA R36, R40, R36, R38 ; /* 0x000000242824722b */
/* 0x00104c0000000026 */
/*02f0*/ F2F.F64.F32 R38, R43 ; /* 0x0000002b00267310 */
/* 0x001e640000201800 */
/*0300*/ DFMA R38, R2, R36, R38 ; /* 0x000000240226722b */
/* 0x002e140000000026 */
/*0310*/ F2F.F32.F64 R39, R38 ; /* 0x0000002600277310 */
/* 0x001e240000301000 */
/*0320*/ STG.E [R12.64], R39 ; /* 0x000000270c007986 */
/* 0x0011e8000c101904 */
/*0330*/ LDG.E R43, [R8.64] ; /* 0x00000004082b7981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R41, [R6.64] ; /* 0x0000000406297981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R42, [R4.64] ; /* 0x00000004042a7981 */
/* 0x000ee8000c1e1900 */
/*0360*/ LDG.E R40, [R10.64] ; /* 0x000000040a287981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R0, [R14.64] ; /* 0x000000040e007981 */
/* 0x000f62000c1e1900 */
/*0380*/ F2F.F64.F32 R36, R43 ; /* 0x0000002b00247310 */
/* 0x004ff00000201800 */
/*0390*/ F2F.F64.F32 R38, R41 ; /* 0x0000002900267310 */
/* 0x0016240000201800 */
/*03a0*/ FMUL R41, R41, R42 ; /* 0x0000002a29297220 */
/* 0x008fcc0000400000 */
/*03b0*/ F2F.F64.F32 R42, R40 ; /* 0x00000028002a7310 */
/* 0x010fe20000201800 */
/*03c0*/ DFMA R36, R36, 2, R38 ; /* 0x400000002424782b */
/* 0x00104e0000000026 */
/*03d0*/ F2F.F64.F32 R38, R41 ; /* 0x0000002900267310 */
/* 0x001e640000201800 */
/*03e0*/ DFMA R36, R42, R36, R38 ; /* 0x000000242a24722b */
/* 0x002a0c0000000026 */
/*03f0*/ F2F.F64.F32 R38, R0 ; /* 0x0000000000267310 */
/* 0x020e240000201800 */
/*0400*/ DFMA R36, R2, R36, R38 ; /* 0x000000240224722b */
/* 0x001e140000000026 */
/*0410*/ F2F.F32.F64 R37, R36 ; /* 0x0000002400257310 */
/* 0x001e240000301000 */
/*0420*/ STG.E [R14.64], R37 ; /* 0x000000250e007986 */
/* 0x0011e8000c101904 */
/*0430*/ LDG.E R39, [R18.64] ; /* 0x0000000412277981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R42, [R16.64] ; /* 0x00000004102a7981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R38, [R8.64] ; /* 0x0000000408267981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R43, [R20.64] ; /* 0x00000004142b7981 */
/* 0x000f22000c1e1900 */
/*0470*/ FADD R39, R39, R42 ; /* 0x0000002a27277221 */
/* 0x004fc40000000000 */
/*0480*/ FMUL R38, R38, c[0x0][0x1e0] ; /* 0x0000780026267a20 */
/* 0x008fc80000400000 */
/*0490*/ FFMA R43, R38, R39, R43 ; /* 0x00000027262b7223 */
/* 0x010fca000000002b */
/*04a0*/ STG.E [R20.64], R43 ; /* 0x0000002b14007986 */
/* 0x0003e8000c101904 */
/*04b0*/ LDG.E R38, [R22.64] ; /* 0x0000000416267981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ BSSY B1, 0x5e0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*04d0*/ F2F.F64.F32 R38, R38 ; /* 0x0000002600267310 */
/* 0x004e300000201800 */
/*04e0*/ MUFU.RCP64H R37, R39 ; /* 0x0000002700257308 */
/* 0x001e220000001800 */
/*04f0*/ IADD3 R36, R39, 0x300402, RZ ; /* 0x0030040227247810 */
/* 0x000fc80007ffe0ff */
/*0500*/ FSETP.GEU.AND P1, PT, |R36|, 5.8789094863358348022e-39, PT ; /* 0x004004022400780b */
/* 0x000fe40003f2e200 */
/*0510*/ DFMA R40, -R38, R36, 1 ; /* 0x3ff000002628742b */
/* 0x001e0c0000000124 */
/*0520*/ DFMA R40, R40, R40, R40 ; /* 0x000000282828722b */
/* 0x001e0c0000000028 */
/*0530*/ DFMA R36, R36, R40, R36 ; /* 0x000000282424722b */
/* 0x001e0c0000000024 */
/*0540*/ DFMA R40, -R38, R36, 1 ; /* 0x3ff000002628742b */
/* 0x001e0c0000000124 */
/*0550*/ DFMA R36, R36, R40, R36 ; /* 0x000000282424722b */
/* 0x0012220000000024 */
/*0560*/ @P1 BRA 0x5d0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT R40, R39, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff27287812 */
/* 0x002fe400078ec0ff */
/*0580*/ MOV R0, 0x5b0 ; /* 0x000005b000007802 */
/* 0x000fe40000000f00 */
/*0590*/ IADD3 R40, R40, -0x100000, RZ ; /* 0xfff0000028287810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000031000007944 */
/* 0x001fea0003c00000 */
/*05b0*/ MOV R36, R38 ; /* 0x0000002600247202 */
/* 0x002fe40000000f00 */
/*05c0*/ MOV R37, R39 ; /* 0x0000002700257202 */
/* 0x000fe40000000f00 */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R39, [R24.64] ; /* 0x0000000418277981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R42, [R28.64] ; /* 0x000000041c2a7981 */
/* 0x000ee2000c1e1900 */
/*0610*/ DMUL R36, R2, R36 ; /* 0x0000002402247228 */
/* 0x001e220000000000 */
/*0620*/ FADD R0, R0, R39 ; /* 0x0000002700007221 */
/* 0x004fe20000000000 */
/*0630*/ F2F.F64.F32 R40, R42 ; /* 0x0000002a00287310 */
/* 0x00aff00000201800 */
/*0640*/ F2F.F64.F32 R38, R0 ; /* 0x0000000000267310 */
/* 0x000e240000201800 */
/*0650*/ DFMA R40, R36, R38, R40 ; /* 0x000000262428722b */
/* 0x001e140000000028 */
/*0660*/ F2F.F32.F64 R41, R40 ; /* 0x0000002800297310 */
/* 0x001e240000301000 */
/*0670*/ STG.E [R28.64], R41 ; /* 0x000000291c007986 */
/* 0x0011e8000c101904 */
/*0680*/ LDG.E R38, [R22.64] ; /* 0x0000000416267981 */
/* 0x000ea2000c1e1900 */
/*0690*/ BSSY B1, 0x7b0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*06a0*/ F2F.F64.F32 R38, R38 ; /* 0x0000002600267310 */
/* 0x004e700000201800 */
/*06b0*/ MUFU.RCP64H R37, R39 ; /* 0x0000002700257308 */
/* 0x002e620000001800 */
/*06c0*/ IADD3 R36, R39, 0x300402, RZ ; /* 0x0030040227247810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ FSETP.GEU.AND P1, PT, |R36|, 5.8789094863358348022e-39, PT ; /* 0x004004022400780b */
/* 0x000fe40003f2e200 */
/*06e0*/ DFMA R42, -R38, R36, 1 ; /* 0x3ff00000262a742b */
/* 0x002e4c0000000124 */
/*06f0*/ DFMA R42, R42, R42, R42 ; /* 0x0000002a2a2a722b */
/* 0x002e4c000000002a */
/*0700*/ DFMA R36, R36, R42, R36 ; /* 0x0000002a2424722b */
/* 0x002e4c0000000024 */
/*0710*/ DFMA R42, -R38, R36, 1 ; /* 0x3ff00000262a742b */
/* 0x002e4c0000000124 */
/*0720*/ DFMA R36, R36, R42, R36 ; /* 0x0000002a2424722b */
/* 0x0020620000000024 */
/*0730*/ @P1 BRA 0x7a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R40, R39, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff27287812 */
/* 0x000fe400078ec0ff */
/*0750*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe40000000f00 */
/*0760*/ IADD3 R40, R40, -0x100000, RZ ; /* 0xfff0000028287810 */
/* 0x000fe40007ffe0ff */
/*0770*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000014000007944 */
/* 0x003fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R36, RZ, RZ, R38 ; /* 0x000000ffff247224 */
/* 0x002fe200078e0026 */
/*0790*/ MOV R37, R39 ; /* 0x0000002700257202 */
/* 0x000fe40000000f00 */
/*07a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E R0, [R32.64] ; /* 0x0000000420007981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R39, [R30.64] ; /* 0x000000041e277981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R40, [R34.64] ; /* 0x0000000422287981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ DMUL R36, R2, R36 ; /* 0x0000002402247228 */
/* 0x002e620000000000 */
/*07f0*/ FADD R39, R0, R39 ; /* 0x0000002700277221 */
/* 0x004fe20000000000 */
/*0800*/ F2F.F64.F32 R40, R40 ; /* 0x0000002800287310 */
/* 0x009ff00000201800 */
/*0810*/ F2F.F64.F32 R38, R39 ; /* 0x0000002700267310 */
/* 0x000e640000201800 */
/*0820*/ DFMA R36, R36, R38, R40 ; /* 0x000000262424722b */
/* 0x002e140000000028 */
/*0830*/ F2F.F32.F64 R37, R36 ; /* 0x0000002400257310 */
/* 0x001e220000301000 */
/*0840*/ MOV R0, c[0x0][0x4] ; /* 0x0000010000007a02 */
/* 0x000fca0000000f00 */
/*0850*/ IMAD R45, R0, c[0x0][0x10], R45 ; /* 0x00000400002d7a24 */
/* 0x000fca00078e022d */
/*0860*/ ISETP.GE.AND P1, PT, R45, c[0x0][0x1e8], PT ; /* 0x00007a002d007a0c */
/* 0x000fe20003f26270 */
/*0870*/ STG.E [R34.64], R37 ; /* 0x0000002522007986 */
/* 0x0011d8000c101904 */
/*0880*/ @!P1 BRA 0x230 ; /* 0xfffff9a000009947 */
/* 0x000fea000383ffff */
/*0890*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08a0*/ @!P0 BRA 0x1d0 ; /* 0xfffff92000008947 */
/* 0x000fea000383ffff */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R36, RZ, RZ, R38 ; /* 0x000000ffff247224 */
/* 0x000fe200078e0026 */
/*08d0*/ MOV R37, R39 ; /* 0x0000002700257202 */
/* 0x000fe20000000f00 */
/*08e0*/ BSSY B2, 0xb20 ; /* 0x0000023000027945 */
/* 0x000fea0003800000 */
/*08f0*/ DSETP.GTU.AND P1, PT, |R36|, +INF , PT ; /* 0x7ff000002400742a */
/* 0x000e1c0003f2c200 */
/*0900*/ @P1 BRA 0xaf0 ; /* 0x000001e000001947 */
/* 0x001fea0003800000 */
/*0910*/ LOP3.LUT R41, R39, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff27297812 */
/* 0x000fc800078ec0ff */
/*0920*/ IADD3 R38, R41, -0x1, RZ ; /* 0xffffffff29267810 */
/* 0x000fc80007ffe0ff */
/*0930*/ ISETP.GE.U32.AND P1, PT, R38, 0x7fefffff, PT ; /* 0x7fefffff2600780c */
/* 0x000fda0003f26070 */
/*0940*/ @P1 LOP3.LUT R39, R37, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000025271812 */
/* 0x000fe400078e3cff */
/*0950*/ @P1 MOV R38, RZ ; /* 0x000000ff00261202 */
/* 0x000fe20000000f00 */
/*0960*/ @P1 BRA 0xb10 ; /* 0x000001a000001947 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.GE.U32.AND P1, PT, R41, 0x1000001, PT ; /* 0x010000012900780c */
/* 0x000fda0003f26070 */
/*0980*/ @!P1 BRA 0xa60 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0990*/ IADD3 R39, R37, -0x3fe00000, RZ ; /* 0xc020000025277810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ IMAD.MOV.U32 R38, RZ, RZ, R36 ; /* 0x000000ffff267224 */
/* 0x000fc600078e0024 */
/*09b0*/ MUFU.RCP64H R41, R39 ; /* 0x0000002700297308 */
/* 0x000e260000001800 */
/*09c0*/ DFMA R42, -R38, R40, 1 ; /* 0x3ff00000262a742b */
/* 0x001e0c0000000128 */
/*09d0*/ DFMA R42, R42, R42, R42 ; /* 0x0000002a2a2a722b */
/* 0x001e0c000000002a */
/*09e0*/ DFMA R42, R40, R42, R40 ; /* 0x0000002a282a722b */
/* 0x001e0c0000000028 */
/*09f0*/ DFMA R40, -R38, R42, 1 ; /* 0x3ff000002628742b */
/* 0x001e0c000000012a */
/*0a00*/ DFMA R40, R42, R40, R42 ; /* 0x000000282a28722b */
/* 0x001e0c000000002a */
/*0a10*/ DMUL R40, R40, 2.2250738585072013831e-308 ; /* 0x0010000028287828 */
/* 0x001e0c0000000000 */
/*0a20*/ DFMA R36, -R36, R40, 1 ; /* 0x3ff000002424742b */
/* 0x001e0c0000000128 */
/*0a30*/ DFMA R36, R36, R36, R36 ; /* 0x000000242424722b */
/* 0x001e0c0000000024 */
/*0a40*/ DFMA R38, R40, R36, R40 ; /* 0x000000242826722b */
/* 0x0010620000000028 */
/*0a50*/ BRA 0xb10 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0a60*/ DMUL R36, R36, 8.11296384146066816958e+31 ; /* 0x4690000024247828 */
/* 0x000e0c0000000000 */
/*0a70*/ MUFU.RCP64H R41, R37 ; /* 0x0000002500297308 */
/* 0x001e240000001800 */
/*0a80*/ DFMA R38, -R36, R40, 1 ; /* 0x3ff000002426742b */
/* 0x001e0c0000000128 */
/*0a90*/ DFMA R38, R38, R38, R38 ; /* 0x000000262626722b */
/* 0x001e0c0000000026 */
/*0aa0*/ DFMA R38, R40, R38, R40 ; /* 0x000000262826722b */
/* 0x001e0c0000000028 */
/*0ab0*/ DFMA R40, -R36, R38, 1 ; /* 0x3ff000002428742b */
/* 0x001e0c0000000126 */
/*0ac0*/ DFMA R38, R38, R40, R38 ; /* 0x000000282626722b */
/* 0x001e0c0000000026 */
/*0ad0*/ DMUL R38, R38, 8.11296384146066816958e+31 ; /* 0x4690000026267828 */
/* 0x001e220000000000 */
/*0ae0*/ BRA 0xb10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0af0*/ LOP3.LUT R39, R37, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000025277812 */
/* 0x000fe400078efcff */
/*0b00*/ MOV R38, R36 ; /* 0x0000002400267202 */
/* 0x000fe40000000f00 */
/*0b10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R37, -RZ, RZ, 0, 0 ; /* 0x00000000ff257435 */
/* 0x001fe200000001ff */
/*0b30*/ MOV R36, R0 ; /* 0x0000000000247202 */
/* 0x000fca0000000f00 */
/*0b40*/ RET.REL.NODEC R36 0x0 ; /* 0xfffff4b024007950 */
/* 0x000fea0003c3ffff */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z28compute_spatial_Z_derivativePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0090*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIADD3 UR5, UR5, -0x2, URZ ; /* 0xfffffffe05057890 */
/* 0x000fe2000fffe03f */
/*00b0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R6, R3, c[0x0][0x4], R6 ; /* 0x0000010003067a24 */
/* 0x001fca00078e0206 */
/*00e0*/ ISETP.GE.AND P0, PT, R6, UR5, PT ; /* 0x0000000506007c0c */
/* 0x000fe2000bf06270 */
/*00f0*/ BSSY B0, 0x220 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0100*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fd60000000f00 */
/*0110*/ @P0 BRA 0x210 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0120*/ IADD3 R13, R0, 0x1, RZ ; /* 0x00000001000d7810 */
/* 0x000fc80007ffe0ff */
/*0130*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R4, R13, c[0x0][0x174], R6 ; /* 0x00005d000d047a24 */
/* 0x000fd200078e0206 */
/*0150*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0207 */
/*0160*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080602087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R9, c[0x0][0x4] ; /* 0x0000010000097a02 */
/* 0x000fca0000000f00 */
/*01a0*/ IMAD R6, R9, c[0x0][0x10], R6 ; /* 0x0000040009067a24 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GE.AND P0, PT, R6, UR5, PT ; /* 0x0000000506007c0c */
/* 0x000fe2000bf06270 */
/*01c0*/ FADD R8, -R5, R8 ; /* 0x0000000805087221 */
/* 0x004fe40000000100 */
/*01d0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*01e0*/ FMUL R7, R8, 0.5 ; /* 0x3f00000008077820 */
/* 0x000fca0000400000 */
/*01f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101906 */
/*0200*/ @!P0 BRA 0x130 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0240*/ @!P0 BRA 0xe0 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z28compute_spatial_X_derivativePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002200 */
/*0090*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIADD3 UR5, UR5, -0x2, URZ ; /* 0xfffffffe05057890 */
/* 0x000fe2000fffe03f */
/*00b0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R8, R3, c[0x0][0x4], R8 ; /* 0x0000010003087a24 */
/* 0x001fca00078e0208 */
/*00e0*/ ISETP.GE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe2000bf06270 */
/*00f0*/ BSSY B0, 0x250 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0100*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fd60000000f00 */
/*0110*/ @P0 BRA 0x240 ; /* 0x0000012000000947 */
/* 0x001fea0003800000 */
/*0120*/ IADD3 R10, R0, 0x2, RZ ; /* 0x00000002000a7810 */
/* 0x000fe40007ffe0ff */
/*0130*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R3, R8, 0x1, RZ ; /* 0x0000000108037810 */
/* 0x000fca0007ffe0ff */
/*0150*/ IMAD R2, R10, c[0x0][0x174], R3.reuse ; /* 0x00005d000a027a24 */
/* 0x100fe400078e0203 */
/*0160*/ IMAD R6, R0, c[0x0][0x174], R3 ; /* 0x00005d0000067a24 */
/* 0x000fe400078e0203 */
/*0170*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.WIDE R4, R6.reuse, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x040fe400078e0207 */
/*0190*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R6, R6, c[0x0][0x174], RZ ; /* 0x00005d0006067a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R11, c[0x0][0x4] ; /* 0x00000100000b7a02 */
/* 0x000fc60000000f00 */
/*01d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*01e0*/ IMAD R8, R11, c[0x0][0x10], R8 ; /* 0x000004000b087a24 */
/* 0x000fca00078e0208 */
/*01f0*/ ISETP.GE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe2000bf06270 */
/*0200*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fc80000000100 */
/*0210*/ FMUL R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fca0000400000 */
/*0220*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e6000c101906 */
/*0230*/ @!P0 BRA 0x130 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */
/* 0x000fca00078e0200 */
/*0260*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0270*/ @!P0 BRA 0xe0 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include"finitedifference.cuh"
#define field(a,b) field[ (a)*Zm + (b) ]
#define diffield(a,b) diffield[ (a)*Zm + (b) ]
#define coef(a,b) coef[ (a)*Zm + (b) ]
#define difffield(a,b) difffield[ (a)*Zm + (b)]
__global__ void compute_spatial_X_derivative(float* difffield, float* field, int Xm, int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
while(tx < Xm-2)
{
while(ty < Zm-2)
{
difffield(tx+1,ty+1) = 0.5*( field( tx + 2, ty + 1 )-field( tx ,ty + 1 ));
//printf("%d: %d => %f, %f, %f, %d, %d\n",tx,ty,difffield(tx+1,ty+1),field( tx + 2, ty + 1 ), field( tx ,ty + 1 ),Xm,Ym);
//printf("%d: %d=> %f\n",tx,ty,field(tx,ty));
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x * gridDim.x;
}
}
__global__ void compute_spatial_Z_derivative(float* difffield, float* field, int Xm, int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
while(tx < Xm - 2)
{
while(ty < Zm - 2)
{
difffield( tx + 1,ty + 1 ) = 0.5*(field( tx + 1 , ty + 2 )-field( tx + 1 ,ty ));
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x*gridDim.x;
}
}
__global__ void update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float *dev_xx_x,
float *dev_zz_z,
float *dev_xz_x,
float *dev_xz_z,
float *dev_ux_x,
float *dev_ux_z,
float *dev_uz_x,
float *dev_uz_z,
float *lambda,
float *mu,
float *rho,
float dt,
int Xm,
int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
int thread = tx*Zm + ty;
while(tx < Xm )
{
while(ty < Zm )
{
stress_xx[thread] += dt*(dev_ux_x[thread]*(lambda[thread]+2.0*mu[thread]) + dev_uz_z[thread]*lambda[thread]);
stress_zz[thread] += dt*(dev_uz_z[thread]*(lambda[thread]+2.0*mu[thread]) + dev_ux_x[thread]*lambda[thread]);
stress_xz[thread] += dt*mu[thread]*(dev_uz_x[thread] + dev_ux_z[thread]);
dev_veloc_u[thread] += dt*(1./rho[thread])*(dev_xx_x[thread] + dev_xz_z[thread]);
dev_veloc_w[thread] += dt*(1./rho[thread])*(dev_zz_z[thread] + dev_xz_x[thread]);
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x*gridDim.x;
}
}
void compute_derivative(int direction, float *inputfield, float *derivative, int Xm, int Zm, dim3 num_blocks, dim3 thread_per_block, cudaStream_t custream)
{
if(direction == XDERIVATIVE)
{
//printf("compute X derivative!\n");
compute_spatial_X_derivative<<<num_blocks, thread_per_block, 0, custream>>>(derivative, inputfield, Xm, Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
}
if(direction == ZDERIVATIVE)
{
compute_spatial_Z_derivative<<<num_blocks, thread_per_block,0, custream>>>(derivative, inputfield, Xm, Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
}
}
void call_update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float* dev_xx_x,
float* dev_zz_z,
float* dev_xz_x,
float* dev_xz_z,
float* dev_ux_x,
float* dev_ux_z,
float* dev_uz_x,
float* dev_uz_z,
float* lambda,
float* mu,
float* rho,
float dt,
int Xm,
int Zm,
dim3 num_blocks,
dim3 thread_per_block,
cudaStream_t custream)
{
update_field<<<num_blocks, thread_per_block, 0, custream>>>( dev_veloc_u,
dev_veloc_w,
stress_xx,
stress_zz,
stress_xz,
dev_xx_x,
dev_zz_z,
dev_xz_x,
dev_xz_z,
dev_ux_x,
dev_ux_z,
dev_uz_x,
dev_uz_z,
lambda,
mu,
rho,
dt,
Xm,
Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
} | .file "tmpxft_00012d57_00000000-6_finitedifference.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
.type _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii, @function
_Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28compute_spatial_X_derivativePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii, .-_Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
.globl _Z28compute_spatial_X_derivativePfS_ii
.type _Z28compute_spatial_X_derivativePfS_ii, @function
_Z28compute_spatial_X_derivativePfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z28compute_spatial_X_derivativePfS_ii, .-_Z28compute_spatial_X_derivativePfS_ii
.globl _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
.type _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii, @function
_Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28compute_spatial_Z_derivativePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii, .-_Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
.globl _Z28compute_spatial_Z_derivativePfS_ii
.type _Z28compute_spatial_Z_derivativePfS_ii, @function
_Z28compute_spatial_Z_derivativePfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z28compute_spatial_Z_derivativePfS_ii, .-_Z28compute_spatial_Z_derivativePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: %s\n"
.text
.globl _Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st
.type _Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st, @function
_Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
movq %rdx, %rbx
movl %ecx, %r12d
movl %r8d, %r13d
cmpl $1, %edi
je .L25
cmpl $2, %edi
je .L26
.L19:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl 72(%rsp), %ecx
movl $0, %r8d
movq 64(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
je .L19
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
movl %r13d, %ecx
movl %r12d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
jmp .L21
.L26:
movl 72(%rsp), %ecx
movl $0, %r8d
movq 64(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L23:
call cudaGetLastError@PLT
testl %eax, %eax
je .L19
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %r13d, %ecx
movl %r12d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
jmp .L23
.cfi_endproc
.LFE2057:
.size _Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st, .-_Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st
.globl _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.type _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, @function
_Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii:
.LFB2087:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rcx, 112(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movss %xmm0, 12(%rsp)
movq 384(%rsp), %rax
movq %rax, 88(%rsp)
movq 392(%rsp), %rax
movq %rax, 80(%rsp)
movq 400(%rsp), %rax
movq %rax, 72(%rsp)
movq 408(%rsp), %rax
movq %rax, 64(%rsp)
movq 416(%rsp), %rax
movq %rax, 56(%rsp)
movq 424(%rsp), %rax
movq %rax, 48(%rsp)
movq 432(%rsp), %rax
movq %rax, 40(%rsp)
movq 440(%rsp), %rax
movq %rax, 32(%rsp)
movq 448(%rsp), %rax
movq %rax, 24(%rsp)
movq 456(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 112(%rsp), %rax
movq %rax, 232(%rsp)
leaq 104(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rax
movq %rax, 264(%rsp)
leaq 72(%rsp), %rax
movq %rax, 272(%rsp)
leaq 64(%rsp), %rax
movq %rax, 280(%rsp)
leaq 56(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 32(%rsp), %rax
movq %rax, 312(%rsp)
leaq 24(%rsp), %rax
movq %rax, 320(%rsp)
leaq 16(%rsp), %rax
movq %rax, 328(%rsp)
leaq 12(%rsp), %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
leaq 472(%rsp), %rax
movq %rax, 352(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
leaq 152(%rsp), %rcx
leaq 144(%rsp), %rdx
leaq 172(%rsp), %rsi
leaq 160(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 152(%rsp)
.cfi_def_cfa_offset 392
pushq 152(%rsp)
.cfi_def_cfa_offset 400
leaq 224(%rsp), %r9
movq 188(%rsp), %rcx
movl 196(%rsp), %r8d
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
leaq _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, .-_Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.globl _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.type _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, @function
_Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 104(%rsp)
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
pushq 104(%rsp)
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, .-_Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.globl _Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st
.type _Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st, @function
_Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movss %xmm0, 12(%rsp)
movl 200(%rsp), %ecx
movq 208(%rsp), %r9
movl $0, %r8d
movq 192(%rsp), %rdx
movq 176(%rsp), %rdi
movl 184(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L38:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
pushq 168(%rsp)
.cfi_def_cfa_offset 104
pushq 168(%rsp)
.cfi_def_cfa_offset 112
pushq 168(%rsp)
.cfi_def_cfa_offset 120
pushq 168(%rsp)
.cfi_def_cfa_offset 128
pushq 168(%rsp)
.cfi_def_cfa_offset 136
pushq 168(%rsp)
.cfi_def_cfa_offset 144
pushq 168(%rsp)
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
movss 108(%rsp), %xmm0
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
addq $96, %rsp
.cfi_def_cfa_offset 80
jmp .L38
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st, .-_Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii"
.align 8
.LC2:
.string "_Z28compute_spatial_Z_derivativePfS_ii"
.align 8
.LC3:
.string "_Z28compute_spatial_X_derivativePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28compute_spatial_Z_derivativePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z28compute_spatial_X_derivativePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<cuda_runtime.h>
#include<stdio.h>
#include"finitedifference.cuh"
#define field(a,b) field[ (a)*Zm + (b) ]
#define diffield(a,b) diffield[ (a)*Zm + (b) ]
#define coef(a,b) coef[ (a)*Zm + (b) ]
#define difffield(a,b) difffield[ (a)*Zm + (b)]
__global__ void compute_spatial_X_derivative(float* difffield, float* field, int Xm, int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
while(tx < Xm-2)
{
while(ty < Zm-2)
{
difffield(tx+1,ty+1) = 0.5*( field( tx + 2, ty + 1 )-field( tx ,ty + 1 ));
//printf("%d: %d => %f, %f, %f, %d, %d\n",tx,ty,difffield(tx+1,ty+1),field( tx + 2, ty + 1 ), field( tx ,ty + 1 ),Xm,Ym);
//printf("%d: %d=> %f\n",tx,ty,field(tx,ty));
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x * gridDim.x;
}
}
__global__ void compute_spatial_Z_derivative(float* difffield, float* field, int Xm, int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
while(tx < Xm - 2)
{
while(ty < Zm - 2)
{
difffield( tx + 1,ty + 1 ) = 0.5*(field( tx + 1 , ty + 2 )-field( tx + 1 ,ty ));
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x*gridDim.x;
}
}
__global__ void update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float *dev_xx_x,
float *dev_zz_z,
float *dev_xz_x,
float *dev_xz_z,
float *dev_ux_x,
float *dev_ux_z,
float *dev_uz_x,
float *dev_uz_z,
float *lambda,
float *mu,
float *rho,
float dt,
int Xm,
int Zm)
{
int tx = blockDim.x * blockIdx.x + threadIdx.x;
int ty = blockDim.y * blockIdx.y + threadIdx.y;
int thread = tx*Zm + ty;
while(tx < Xm )
{
while(ty < Zm )
{
stress_xx[thread] += dt*(dev_ux_x[thread]*(lambda[thread]+2.0*mu[thread]) + dev_uz_z[thread]*lambda[thread]);
stress_zz[thread] += dt*(dev_uz_z[thread]*(lambda[thread]+2.0*mu[thread]) + dev_ux_x[thread]*lambda[thread]);
stress_xz[thread] += dt*mu[thread]*(dev_uz_x[thread] + dev_ux_z[thread]);
dev_veloc_u[thread] += dt*(1./rho[thread])*(dev_xx_x[thread] + dev_xz_z[thread]);
dev_veloc_w[thread] += dt*(1./rho[thread])*(dev_zz_z[thread] + dev_xz_x[thread]);
ty += blockDim.y * gridDim.y;
}
tx += blockDim.x*gridDim.x;
}
}
void compute_derivative(int direction, float *inputfield, float *derivative, int Xm, int Zm, dim3 num_blocks, dim3 thread_per_block, cudaStream_t custream)
{
if(direction == XDERIVATIVE)
{
//printf("compute X derivative!\n");
compute_spatial_X_derivative<<<num_blocks, thread_per_block, 0, custream>>>(derivative, inputfield, Xm, Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
}
if(direction == ZDERIVATIVE)
{
compute_spatial_Z_derivative<<<num_blocks, thread_per_block,0, custream>>>(derivative, inputfield, Xm, Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
}
}
void call_update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float* dev_xx_x,
float* dev_zz_z,
float* dev_xz_x,
float* dev_xz_z,
float* dev_ux_x,
float* dev_ux_z,
float* dev_uz_x,
float* dev_uz_z,
float* lambda,
float* mu,
float* rho,
float dt,
int Xm,
int Zm,
dim3 num_blocks,
dim3 thread_per_block,
cudaStream_t custream)
{
update_field<<<num_blocks, thread_per_block, 0, custream>>>( dev_veloc_u,
dev_veloc_w,
stress_xx,
stress_zz,
stress_xz,
dev_xx_x,
dev_zz_z,
dev_xz_x,
dev_xz_z,
dev_ux_x,
dev_ux_z,
dev_uz_x,
dev_uz_z,
lambda,
mu,
rho,
dt,
Xm,
Zm);
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess)
{
// print the CUDA error message and exit
printf("CUDA error: %s\n", cudaGetErrorString(error));
exit(-1);
}
} | #include <hip/hip_runtime.h>
#define XDERIVATIVE 1
#define ZDERIVATIVE 2
void compute_derivative(int direction, float *inputfield, float *derivative, int Xm, int Zm, dim3 num_blocks, dim3 thread_per_block, hipStream_t custream);
void call_update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float* dev_xx_x,
float* dev_zz_z,
float* dev_xz_x,
float* dev_xz_z,
float* dev_ux_x,
float* dev_ux_z,
float* dev_uz_x,
float* uz_z,
float* lambda,
float* mu,
float* rho,
float dt,
int Xm,
int Zm,
dim3 num_blocks,
dim3 thread_per_block,
hipStream_t custream); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define XDERIVATIVE 1
#define ZDERIVATIVE 2
void compute_derivative(int direction, float *inputfield, float *derivative, int Xm, int Zm, dim3 num_blocks, dim3 thread_per_block, hipStream_t custream);
void call_update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float* dev_xx_x,
float* dev_zz_z,
float* dev_xz_x,
float* dev_xz_z,
float* dev_ux_x,
float* dev_ux_z,
float* dev_uz_x,
float* uz_z,
float* lambda,
float* mu,
float* rho,
float dt,
int Xm,
int Zm,
dim3 num_blocks,
dim3 thread_per_block,
hipStream_t custream); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define XDERIVATIVE 1
#define ZDERIVATIVE 2
void compute_derivative(int direction, float *inputfield, float *derivative, int Xm, int Zm, dim3 num_blocks, dim3 thread_per_block, hipStream_t custream);
void call_update_field(float* dev_veloc_u,
float* dev_veloc_w,
float *stress_xx,
float *stress_zz,
float *stress_xz,
float* dev_xx_x,
float* dev_zz_z,
float* dev_xz_x,
float* dev_xz_z,
float* dev_ux_x,
float* dev_ux_z,
float* dev_uz_x,
float* uz_z,
float* lambda,
float* mu,
float* rho,
float dt,
int Xm,
int Zm,
dim3 num_blocks,
dim3 thread_per_block,
hipStream_t custream); | .text
.file "finitedifference.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R44, SR_CTAID.X ; /* 0x00000000002c7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R45, SR_CTAID.Y ; /* 0x00000000002d7919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R44, R44, c[0x0][0x0], R3 ; /* 0x000000002c2c7a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R44, c[0x0][0x1e4], PT ; /* 0x000079002c007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R45, R45, c[0x0][0x4], R0 ; /* 0x000001002d2d7a24 */
/* 0x002fd800078e0200 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ F2F.F64.F32 R2, c[0x0][0x1e0] ; /* 0x0000780000027b10 */
/* 0x000e220000201800 */
/*00a0*/ HFMA2.MMA R35, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff237435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R34, R44, c[0x0][0x1e8], R45 ; /* 0x00007a002c227a24 */
/* 0x000fe200078e022d */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R34, R35, c[0x0][0x1a8] ; /* 0x00006a0022047625 */
/* 0x000fc800078e0223 */
/*00e0*/ IMAD.WIDE R6, R34, R35, c[0x0][0x1c8] ; /* 0x0000720022067625 */
/* 0x000fc800078e0223 */
/*00f0*/ IMAD.WIDE R8, R34, R35, c[0x0][0x1d0] ; /* 0x0000740022087625 */
/* 0x000fc800078e0223 */
/*0100*/ IMAD.WIDE R10, R34, R35, c[0x0][0x1c0] ; /* 0x00007000220a7625 */
/* 0x000fc800078e0223 */
/*0110*/ IMAD.WIDE R12, R34, R35, c[0x0][0x170] ; /* 0x00005c00220c7625 */
/* 0x000fc800078e0223 */
/*0120*/ IMAD.WIDE R14, R34, R35, c[0x0][0x178] ; /* 0x00005e00220e7625 */
/* 0x000fc800078e0223 */
/*0130*/ IMAD.WIDE R16, R34, R35, c[0x0][0x1b8] ; /* 0x00006e0022107625 */
/* 0x000fc800078e0223 */
/*0140*/ IMAD.WIDE R18, R34, R35, c[0x0][0x1b0] ; /* 0x00006c0022127625 */
/* 0x000fc800078e0223 */
/*0150*/ IMAD.WIDE R20, R34, R35, c[0x0][0x180] ; /* 0x0000600022147625 */
/* 0x000fc800078e0223 */
/*0160*/ IMAD.WIDE R22, R34, R35, c[0x0][0x1d8] ; /* 0x0000760022167625 */
/* 0x000fc800078e0223 */
/*0170*/ IMAD.WIDE R24, R34, R35, c[0x0][0x188] ; /* 0x0000620022187625 */
/* 0x000fc800078e0223 */
/*0180*/ IMAD.WIDE R26, R34, R35, c[0x0][0x1a0] ; /* 0x00006800221a7625 */
/* 0x000fc800078e0223 */
/*0190*/ IMAD.WIDE R28, R34, R35, c[0x0][0x160] ; /* 0x00005800221c7625 */
/* 0x000fc800078e0223 */
/*01a0*/ IMAD.WIDE R30, R34, R35, c[0x0][0x190] ; /* 0x00006400221e7625 */
/* 0x000fc800078e0223 */
/*01b0*/ IMAD.WIDE R32, R34, R35, c[0x0][0x198] ; /* 0x0000660022207625 */
/* 0x000fc800078e0223 */
/*01c0*/ IMAD.WIDE R34, R34, R35, c[0x0][0x168] ; /* 0x00005a0022227625 */
/* 0x001fc800078e0223 */
/*01d0*/ ISETP.GE.AND P1, PT, R45, c[0x0][0x1e8], PT ; /* 0x00007a002d007a0c */
/* 0x000fe20003f26270 */
/*01e0*/ IMAD.MOV.U32 R37, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff257624 */
/* 0x001fe200078e00ff */
/*01f0*/ BSSY B0, 0x8a0 ; /* 0x000006a000007945 */
/* 0x000fe60003800000 */
/*0200*/ IMAD R44, R37, c[0x0][0xc], R44 ; /* 0x00000300252c7a24 */
/* 0x000fca00078e022c */
/*0210*/ ISETP.GE.AND P0, PT, R44, c[0x0][0x1e4], PT ; /* 0x000079002c007a0c */
/* 0x000fc60003f06270 */
/*0220*/ @P1 BRA 0x890 ; /* 0x0000066000001947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R42, [R8.64] ; /* 0x00000004082a7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R40, [R6.64] ; /* 0x0000000406287981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R41, [R10.64] ; /* 0x000000040a297981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R43, [R12.64] ; /* 0x000000040c2b7981 */
/* 0x000f22000c1e1900 */
/*0280*/ F2F.F64.F32 R36, R42 ; /* 0x0000002a00247310 */
/* 0x005ff00000201800 */
/*0290*/ F2F.F64.F32 R38, R40 ; /* 0x0000002800267310 */
/* 0x008e240000201800 */
/*02a0*/ DFMA R36, R36, 2, R38 ; /* 0x400000002424782b */
/* 0x0018040000000026 */
/*02b0*/ FMUL R38, R40, R41 ; /* 0x0000002928267220 */
/* 0x010fc80000400000 */
/*02c0*/ F2F.F64.F32 R40, R0 ; /* 0x0000000000287310 */
/* 0x020ff00000201800 */
/*02d0*/ F2F.F64.F32 R38, R38 ; /* 0x0000002600267310 */
/* 0x000e240000201800 */
/*02e0*/ DFMA R36, R40, R36, R38 ; /* 0x000000242824722b */
/* 0x00104c0000000026 */
/*02f0*/ F2F.F64.F32 R38, R43 ; /* 0x0000002b00267310 */
/* 0x001e640000201800 */
/*0300*/ DFMA R38, R2, R36, R38 ; /* 0x000000240226722b */
/* 0x002e140000000026 */
/*0310*/ F2F.F32.F64 R39, R38 ; /* 0x0000002600277310 */
/* 0x001e240000301000 */
/*0320*/ STG.E [R12.64], R39 ; /* 0x000000270c007986 */
/* 0x0011e8000c101904 */
/*0330*/ LDG.E R43, [R8.64] ; /* 0x00000004082b7981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R41, [R6.64] ; /* 0x0000000406297981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R42, [R4.64] ; /* 0x00000004042a7981 */
/* 0x000ee8000c1e1900 */
/*0360*/ LDG.E R40, [R10.64] ; /* 0x000000040a287981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R0, [R14.64] ; /* 0x000000040e007981 */
/* 0x000f62000c1e1900 */
/*0380*/ F2F.F64.F32 R36, R43 ; /* 0x0000002b00247310 */
/* 0x004ff00000201800 */
/*0390*/ F2F.F64.F32 R38, R41 ; /* 0x0000002900267310 */
/* 0x0016240000201800 */
/*03a0*/ FMUL R41, R41, R42 ; /* 0x0000002a29297220 */
/* 0x008fcc0000400000 */
/*03b0*/ F2F.F64.F32 R42, R40 ; /* 0x00000028002a7310 */
/* 0x010fe20000201800 */
/*03c0*/ DFMA R36, R36, 2, R38 ; /* 0x400000002424782b */
/* 0x00104e0000000026 */
/*03d0*/ F2F.F64.F32 R38, R41 ; /* 0x0000002900267310 */
/* 0x001e640000201800 */
/*03e0*/ DFMA R36, R42, R36, R38 ; /* 0x000000242a24722b */
/* 0x002a0c0000000026 */
/*03f0*/ F2F.F64.F32 R38, R0 ; /* 0x0000000000267310 */
/* 0x020e240000201800 */
/*0400*/ DFMA R36, R2, R36, R38 ; /* 0x000000240224722b */
/* 0x001e140000000026 */
/*0410*/ F2F.F32.F64 R37, R36 ; /* 0x0000002400257310 */
/* 0x001e240000301000 */
/*0420*/ STG.E [R14.64], R37 ; /* 0x000000250e007986 */
/* 0x0011e8000c101904 */
/*0430*/ LDG.E R39, [R18.64] ; /* 0x0000000412277981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R42, [R16.64] ; /* 0x00000004102a7981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R38, [R8.64] ; /* 0x0000000408267981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R43, [R20.64] ; /* 0x00000004142b7981 */
/* 0x000f22000c1e1900 */
/*0470*/ FADD R39, R39, R42 ; /* 0x0000002a27277221 */
/* 0x004fc40000000000 */
/*0480*/ FMUL R38, R38, c[0x0][0x1e0] ; /* 0x0000780026267a20 */
/* 0x008fc80000400000 */
/*0490*/ FFMA R43, R38, R39, R43 ; /* 0x00000027262b7223 */
/* 0x010fca000000002b */
/*04a0*/ STG.E [R20.64], R43 ; /* 0x0000002b14007986 */
/* 0x0003e8000c101904 */
/*04b0*/ LDG.E R38, [R22.64] ; /* 0x0000000416267981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ BSSY B1, 0x5e0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*04d0*/ F2F.F64.F32 R38, R38 ; /* 0x0000002600267310 */
/* 0x004e300000201800 */
/*04e0*/ MUFU.RCP64H R37, R39 ; /* 0x0000002700257308 */
/* 0x001e220000001800 */
/*04f0*/ IADD3 R36, R39, 0x300402, RZ ; /* 0x0030040227247810 */
/* 0x000fc80007ffe0ff */
/*0500*/ FSETP.GEU.AND P1, PT, |R36|, 5.8789094863358348022e-39, PT ; /* 0x004004022400780b */
/* 0x000fe40003f2e200 */
/*0510*/ DFMA R40, -R38, R36, 1 ; /* 0x3ff000002628742b */
/* 0x001e0c0000000124 */
/*0520*/ DFMA R40, R40, R40, R40 ; /* 0x000000282828722b */
/* 0x001e0c0000000028 */
/*0530*/ DFMA R36, R36, R40, R36 ; /* 0x000000282424722b */
/* 0x001e0c0000000024 */
/*0540*/ DFMA R40, -R38, R36, 1 ; /* 0x3ff000002628742b */
/* 0x001e0c0000000124 */
/*0550*/ DFMA R36, R36, R40, R36 ; /* 0x000000282424722b */
/* 0x0012220000000024 */
/*0560*/ @P1 BRA 0x5d0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT R40, R39, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff27287812 */
/* 0x002fe400078ec0ff */
/*0580*/ MOV R0, 0x5b0 ; /* 0x000005b000007802 */
/* 0x000fe40000000f00 */
/*0590*/ IADD3 R40, R40, -0x100000, RZ ; /* 0xfff0000028287810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000031000007944 */
/* 0x001fea0003c00000 */
/*05b0*/ MOV R36, R38 ; /* 0x0000002600247202 */
/* 0x002fe40000000f00 */
/*05c0*/ MOV R37, R39 ; /* 0x0000002700257202 */
/* 0x000fe40000000f00 */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ LDG.E R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R39, [R24.64] ; /* 0x0000000418277981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R42, [R28.64] ; /* 0x000000041c2a7981 */
/* 0x000ee2000c1e1900 */
/*0610*/ DMUL R36, R2, R36 ; /* 0x0000002402247228 */
/* 0x001e220000000000 */
/*0620*/ FADD R0, R0, R39 ; /* 0x0000002700007221 */
/* 0x004fe20000000000 */
/*0630*/ F2F.F64.F32 R40, R42 ; /* 0x0000002a00287310 */
/* 0x00aff00000201800 */
/*0640*/ F2F.F64.F32 R38, R0 ; /* 0x0000000000267310 */
/* 0x000e240000201800 */
/*0650*/ DFMA R40, R36, R38, R40 ; /* 0x000000262428722b */
/* 0x001e140000000028 */
/*0660*/ F2F.F32.F64 R41, R40 ; /* 0x0000002800297310 */
/* 0x001e240000301000 */
/*0670*/ STG.E [R28.64], R41 ; /* 0x000000291c007986 */
/* 0x0011e8000c101904 */
/*0680*/ LDG.E R38, [R22.64] ; /* 0x0000000416267981 */
/* 0x000ea2000c1e1900 */
/*0690*/ BSSY B1, 0x7b0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*06a0*/ F2F.F64.F32 R38, R38 ; /* 0x0000002600267310 */
/* 0x004e700000201800 */
/*06b0*/ MUFU.RCP64H R37, R39 ; /* 0x0000002700257308 */
/* 0x002e620000001800 */
/*06c0*/ IADD3 R36, R39, 0x300402, RZ ; /* 0x0030040227247810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ FSETP.GEU.AND P1, PT, |R36|, 5.8789094863358348022e-39, PT ; /* 0x004004022400780b */
/* 0x000fe40003f2e200 */
/*06e0*/ DFMA R42, -R38, R36, 1 ; /* 0x3ff00000262a742b */
/* 0x002e4c0000000124 */
/*06f0*/ DFMA R42, R42, R42, R42 ; /* 0x0000002a2a2a722b */
/* 0x002e4c000000002a */
/*0700*/ DFMA R36, R36, R42, R36 ; /* 0x0000002a2424722b */
/* 0x002e4c0000000024 */
/*0710*/ DFMA R42, -R38, R36, 1 ; /* 0x3ff00000262a742b */
/* 0x002e4c0000000124 */
/*0720*/ DFMA R36, R36, R42, R36 ; /* 0x0000002a2424722b */
/* 0x0020620000000024 */
/*0730*/ @P1 BRA 0x7a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R40, R39, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff27287812 */
/* 0x000fe400078ec0ff */
/*0750*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe40000000f00 */
/*0760*/ IADD3 R40, R40, -0x100000, RZ ; /* 0xfff0000028287810 */
/* 0x000fe40007ffe0ff */
/*0770*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000014000007944 */
/* 0x003fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R36, RZ, RZ, R38 ; /* 0x000000ffff247224 */
/* 0x002fe200078e0026 */
/*0790*/ MOV R37, R39 ; /* 0x0000002700257202 */
/* 0x000fe40000000f00 */
/*07a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E R0, [R32.64] ; /* 0x0000000420007981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R39, [R30.64] ; /* 0x000000041e277981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R40, [R34.64] ; /* 0x0000000422287981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ DMUL R36, R2, R36 ; /* 0x0000002402247228 */
/* 0x002e620000000000 */
/*07f0*/ FADD R39, R0, R39 ; /* 0x0000002700277221 */
/* 0x004fe20000000000 */
/*0800*/ F2F.F64.F32 R40, R40 ; /* 0x0000002800287310 */
/* 0x009ff00000201800 */
/*0810*/ F2F.F64.F32 R38, R39 ; /* 0x0000002700267310 */
/* 0x000e640000201800 */
/*0820*/ DFMA R36, R36, R38, R40 ; /* 0x000000262424722b */
/* 0x002e140000000028 */
/*0830*/ F2F.F32.F64 R37, R36 ; /* 0x0000002400257310 */
/* 0x001e220000301000 */
/*0840*/ MOV R0, c[0x0][0x4] ; /* 0x0000010000007a02 */
/* 0x000fca0000000f00 */
/*0850*/ IMAD R45, R0, c[0x0][0x10], R45 ; /* 0x00000400002d7a24 */
/* 0x000fca00078e022d */
/*0860*/ ISETP.GE.AND P1, PT, R45, c[0x0][0x1e8], PT ; /* 0x00007a002d007a0c */
/* 0x000fe20003f26270 */
/*0870*/ STG.E [R34.64], R37 ; /* 0x0000002522007986 */
/* 0x0011d8000c101904 */
/*0880*/ @!P1 BRA 0x230 ; /* 0xfffff9a000009947 */
/* 0x000fea000383ffff */
/*0890*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08a0*/ @!P0 BRA 0x1d0 ; /* 0xfffff92000008947 */
/* 0x000fea000383ffff */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R36, RZ, RZ, R38 ; /* 0x000000ffff247224 */
/* 0x000fe200078e0026 */
/*08d0*/ MOV R37, R39 ; /* 0x0000002700257202 */
/* 0x000fe20000000f00 */
/*08e0*/ BSSY B2, 0xb20 ; /* 0x0000023000027945 */
/* 0x000fea0003800000 */
/*08f0*/ DSETP.GTU.AND P1, PT, |R36|, +INF , PT ; /* 0x7ff000002400742a */
/* 0x000e1c0003f2c200 */
/*0900*/ @P1 BRA 0xaf0 ; /* 0x000001e000001947 */
/* 0x001fea0003800000 */
/*0910*/ LOP3.LUT R41, R39, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff27297812 */
/* 0x000fc800078ec0ff */
/*0920*/ IADD3 R38, R41, -0x1, RZ ; /* 0xffffffff29267810 */
/* 0x000fc80007ffe0ff */
/*0930*/ ISETP.GE.U32.AND P1, PT, R38, 0x7fefffff, PT ; /* 0x7fefffff2600780c */
/* 0x000fda0003f26070 */
/*0940*/ @P1 LOP3.LUT R39, R37, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000025271812 */
/* 0x000fe400078e3cff */
/*0950*/ @P1 MOV R38, RZ ; /* 0x000000ff00261202 */
/* 0x000fe20000000f00 */
/*0960*/ @P1 BRA 0xb10 ; /* 0x000001a000001947 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.GE.U32.AND P1, PT, R41, 0x1000001, PT ; /* 0x010000012900780c */
/* 0x000fda0003f26070 */
/*0980*/ @!P1 BRA 0xa60 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0990*/ IADD3 R39, R37, -0x3fe00000, RZ ; /* 0xc020000025277810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ IMAD.MOV.U32 R38, RZ, RZ, R36 ; /* 0x000000ffff267224 */
/* 0x000fc600078e0024 */
/*09b0*/ MUFU.RCP64H R41, R39 ; /* 0x0000002700297308 */
/* 0x000e260000001800 */
/*09c0*/ DFMA R42, -R38, R40, 1 ; /* 0x3ff00000262a742b */
/* 0x001e0c0000000128 */
/*09d0*/ DFMA R42, R42, R42, R42 ; /* 0x0000002a2a2a722b */
/* 0x001e0c000000002a */
/*09e0*/ DFMA R42, R40, R42, R40 ; /* 0x0000002a282a722b */
/* 0x001e0c0000000028 */
/*09f0*/ DFMA R40, -R38, R42, 1 ; /* 0x3ff000002628742b */
/* 0x001e0c000000012a */
/*0a00*/ DFMA R40, R42, R40, R42 ; /* 0x000000282a28722b */
/* 0x001e0c000000002a */
/*0a10*/ DMUL R40, R40, 2.2250738585072013831e-308 ; /* 0x0010000028287828 */
/* 0x001e0c0000000000 */
/*0a20*/ DFMA R36, -R36, R40, 1 ; /* 0x3ff000002424742b */
/* 0x001e0c0000000128 */
/*0a30*/ DFMA R36, R36, R36, R36 ; /* 0x000000242424722b */
/* 0x001e0c0000000024 */
/*0a40*/ DFMA R38, R40, R36, R40 ; /* 0x000000242826722b */
/* 0x0010620000000028 */
/*0a50*/ BRA 0xb10 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0a60*/ DMUL R36, R36, 8.11296384146066816958e+31 ; /* 0x4690000024247828 */
/* 0x000e0c0000000000 */
/*0a70*/ MUFU.RCP64H R41, R37 ; /* 0x0000002500297308 */
/* 0x001e240000001800 */
/*0a80*/ DFMA R38, -R36, R40, 1 ; /* 0x3ff000002426742b */
/* 0x001e0c0000000128 */
/*0a90*/ DFMA R38, R38, R38, R38 ; /* 0x000000262626722b */
/* 0x001e0c0000000026 */
/*0aa0*/ DFMA R38, R40, R38, R40 ; /* 0x000000262826722b */
/* 0x001e0c0000000028 */
/*0ab0*/ DFMA R40, -R36, R38, 1 ; /* 0x3ff000002428742b */
/* 0x001e0c0000000126 */
/*0ac0*/ DFMA R38, R38, R40, R38 ; /* 0x000000282626722b */
/* 0x001e0c0000000026 */
/*0ad0*/ DMUL R38, R38, 8.11296384146066816958e+31 ; /* 0x4690000026267828 */
/* 0x001e220000000000 */
/*0ae0*/ BRA 0xb10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0af0*/ LOP3.LUT R39, R37, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000025277812 */
/* 0x000fe400078efcff */
/*0b00*/ MOV R38, R36 ; /* 0x0000002400267202 */
/* 0x000fe40000000f00 */
/*0b10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R37, -RZ, RZ, 0, 0 ; /* 0x00000000ff257435 */
/* 0x001fe200000001ff */
/*0b30*/ MOV R36, R0 ; /* 0x0000000000247202 */
/* 0x000fca0000000f00 */
/*0b40*/ RET.REL.NODEC R36 0x0 ; /* 0xfffff4b024007950 */
/* 0x000fea0003c3ffff */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z28compute_spatial_Z_derivativePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0090*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIADD3 UR5, UR5, -0x2, URZ ; /* 0xfffffffe05057890 */
/* 0x000fe2000fffe03f */
/*00b0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R6, R3, c[0x0][0x4], R6 ; /* 0x0000010003067a24 */
/* 0x001fca00078e0206 */
/*00e0*/ ISETP.GE.AND P0, PT, R6, UR5, PT ; /* 0x0000000506007c0c */
/* 0x000fe2000bf06270 */
/*00f0*/ BSSY B0, 0x220 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0100*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fd60000000f00 */
/*0110*/ @P0 BRA 0x210 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0120*/ IADD3 R13, R0, 0x1, RZ ; /* 0x00000001000d7810 */
/* 0x000fc80007ffe0ff */
/*0130*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R4, R13, c[0x0][0x174], R6 ; /* 0x00005d000d047a24 */
/* 0x000fd200078e0206 */
/*0150*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0207 */
/*0160*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080602087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0190*/ MOV R9, c[0x0][0x4] ; /* 0x0000010000097a02 */
/* 0x000fca0000000f00 */
/*01a0*/ IMAD R6, R9, c[0x0][0x10], R6 ; /* 0x0000040009067a24 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GE.AND P0, PT, R6, UR5, PT ; /* 0x0000000506007c0c */
/* 0x000fe2000bf06270 */
/*01c0*/ FADD R8, -R5, R8 ; /* 0x0000000805087221 */
/* 0x004fe40000000100 */
/*01d0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*01e0*/ FMUL R7, R8, 0.5 ; /* 0x3f00000008077820 */
/* 0x000fca0000400000 */
/*01f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101906 */
/*0200*/ @!P0 BRA 0x130 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0240*/ @!P0 BRA 0xe0 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z28compute_spatial_X_derivativePfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e220000002200 */
/*0090*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIADD3 UR5, UR5, -0x2, URZ ; /* 0xfffffffe05057890 */
/* 0x000fe2000fffe03f */
/*00b0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R8, R3, c[0x0][0x4], R8 ; /* 0x0000010003087a24 */
/* 0x001fca00078e0208 */
/*00e0*/ ISETP.GE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe2000bf06270 */
/*00f0*/ BSSY B0, 0x250 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0100*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fd60000000f00 */
/*0110*/ @P0 BRA 0x240 ; /* 0x0000012000000947 */
/* 0x001fea0003800000 */
/*0120*/ IADD3 R10, R0, 0x2, RZ ; /* 0x00000002000a7810 */
/* 0x000fe40007ffe0ff */
/*0130*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R3, R8, 0x1, RZ ; /* 0x0000000108037810 */
/* 0x000fca0007ffe0ff */
/*0150*/ IMAD R2, R10, c[0x0][0x174], R3.reuse ; /* 0x00005d000a027a24 */
/* 0x100fe400078e0203 */
/*0160*/ IMAD R6, R0, c[0x0][0x174], R3 ; /* 0x00005d0000067a24 */
/* 0x000fe400078e0203 */
/*0170*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.WIDE R4, R6.reuse, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x040fe400078e0207 */
/*0190*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IADD3 R6, R6, c[0x0][0x174], RZ ; /* 0x00005d0006067a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ MOV R11, c[0x0][0x4] ; /* 0x00000100000b7a02 */
/* 0x000fc60000000f00 */
/*01d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*01e0*/ IMAD R8, R11, c[0x0][0x10], R8 ; /* 0x000004000b087a24 */
/* 0x000fca00078e0208 */
/*01f0*/ ISETP.GE.AND P0, PT, R8, UR5, PT ; /* 0x0000000508007c0c */
/* 0x000fe2000bf06270 */
/*0200*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fc80000000100 */
/*0210*/ FMUL R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fca0000400000 */
/*0220*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e6000c101906 */
/*0230*/ @!P0 BRA 0x130 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */
/* 0x000fca00078e0200 */
/*0260*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0270*/ @!P0 BRA 0xe0 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00012d57_00000000-6_finitedifference.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
.type _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii, @function
_Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28compute_spatial_X_derivativePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii, .-_Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
.globl _Z28compute_spatial_X_derivativePfS_ii
.type _Z28compute_spatial_X_derivativePfS_ii, @function
_Z28compute_spatial_X_derivativePfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z28compute_spatial_X_derivativePfS_ii, .-_Z28compute_spatial_X_derivativePfS_ii
.globl _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
.type _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii, @function
_Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28compute_spatial_Z_derivativePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii, .-_Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
.globl _Z28compute_spatial_Z_derivativePfS_ii
.type _Z28compute_spatial_Z_derivativePfS_ii, @function
_Z28compute_spatial_Z_derivativePfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z28compute_spatial_Z_derivativePfS_ii, .-_Z28compute_spatial_Z_derivativePfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: %s\n"
.text
.globl _Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st
.type _Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st, @function
_Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
movq %rdx, %rbx
movl %ecx, %r12d
movl %r8d, %r13d
cmpl $1, %edi
je .L25
cmpl $2, %edi
je .L26
.L19:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl 72(%rsp), %ecx
movl $0, %r8d
movq 64(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
call cudaGetLastError@PLT
testl %eax, %eax
je .L19
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
movl %r13d, %ecx
movl %r12d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z28compute_spatial_X_derivativePfS_iiPfS_ii
jmp .L21
.L26:
movl 72(%rsp), %ecx
movl $0, %r8d
movq 64(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L23:
call cudaGetLastError@PLT
testl %eax, %eax
je .L19
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %r13d, %ecx
movl %r12d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z52__device_stub__Z28compute_spatial_Z_derivativePfS_iiPfS_ii
jmp .L23
.cfi_endproc
.LFE2057:
.size _Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st, .-_Z18compute_derivativeiPfS_ii4dim3S0_P11CUstream_st
.globl _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.type _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, @function
_Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii:
.LFB2087:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rcx, 112(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movss %xmm0, 12(%rsp)
movq 384(%rsp), %rax
movq %rax, 88(%rsp)
movq 392(%rsp), %rax
movq %rax, 80(%rsp)
movq 400(%rsp), %rax
movq %rax, 72(%rsp)
movq 408(%rsp), %rax
movq %rax, 64(%rsp)
movq 416(%rsp), %rax
movq %rax, 56(%rsp)
movq 424(%rsp), %rax
movq %rax, 48(%rsp)
movq 432(%rsp), %rax
movq %rax, 40(%rsp)
movq 440(%rsp), %rax
movq %rax, 32(%rsp)
movq 448(%rsp), %rax
movq %rax, 24(%rsp)
movq 456(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 112(%rsp), %rax
movq %rax, 232(%rsp)
leaq 104(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rax
movq %rax, 264(%rsp)
leaq 72(%rsp), %rax
movq %rax, 272(%rsp)
leaq 64(%rsp), %rax
movq %rax, 280(%rsp)
leaq 56(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 32(%rsp), %rax
movq %rax, 312(%rsp)
leaq 24(%rsp), %rax
movq %rax, 320(%rsp)
leaq 16(%rsp), %rax
movq %rax, 328(%rsp)
leaq 12(%rsp), %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
leaq 472(%rsp), %rax
movq %rax, 352(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
leaq 152(%rsp), %rcx
leaq 144(%rsp), %rdx
leaq 172(%rsp), %rsi
leaq 160(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 152(%rsp)
.cfi_def_cfa_offset 392
pushq 152(%rsp)
.cfi_def_cfa_offset 400
leaq 224(%rsp), %r9
movq 188(%rsp), %rcx
movl 196(%rsp), %r8d
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
leaq _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, .-_Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.globl _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.type _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, @function
_Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 104(%rsp)
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
pushq 104(%rsp)
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii, .-_Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
.globl _Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st
.type _Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st, @function
_Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movss %xmm0, 12(%rsp)
movl 200(%rsp), %ecx
movq 208(%rsp), %r9
movl $0, %r8d
movq 192(%rsp), %rdx
movq 176(%rsp), %rdi
movl 184(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L38:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 168(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
pushq 168(%rsp)
.cfi_def_cfa_offset 104
pushq 168(%rsp)
.cfi_def_cfa_offset 112
pushq 168(%rsp)
.cfi_def_cfa_offset 120
pushq 168(%rsp)
.cfi_def_cfa_offset 128
pushq 168(%rsp)
.cfi_def_cfa_offset 136
pushq 168(%rsp)
.cfi_def_cfa_offset 144
pushq 168(%rsp)
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
movss 108(%rsp), %xmm0
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z65__device_stub__Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fiiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii
addq $96, %rsp
.cfi_def_cfa_offset 80
jmp .L38
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st, .-_Z17call_update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii4dim3S0_P11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii"
.align 8
.LC2:
.string "_Z28compute_spatial_Z_derivativePfS_ii"
.align 8
.LC3:
.string "_Z28compute_spatial_X_derivativePfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12update_fieldPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z28compute_spatial_Z_derivativePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z28compute_spatial_X_derivativePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "finitedifference.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void scalarDiv_wfcNorm(double2* in, double dr, double* pSum, double2* out){
unsigned int gid = getGid3d3d();
double2 result;
double norm = sqrt((pSum[0])*dr);
result.x = (in[gid].x/norm);
result.y = (in[gid].y/norm);
out[gid] = result;
} | code for sm_80
Function : _Z17scalarDiv_wfcNormP7double2dPdS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fcc00078e00ff */
/*0040*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0080*/ S2R R15, SR_CTAID.Z ; /* 0x00000000000f7919 */
/* 0x000e280000002700 */
/*0090*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e680000002500 */
/*00a0*/ S2R R17, SR_TID.Z ; /* 0x0000000000117919 */
/* 0x000ee80000002300 */
/*00b0*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000f220000002100 */
/*00c0*/ IMAD R0, R15, c[0x0][0x10], R0 ; /* 0x000004000f007a24 */
/* 0x001fc800078e0200 */
/*00d0*/ IMAD R0, R0, c[0x0][0xc], R13 ; /* 0x0000030000007a24 */
/* 0x002fc800078e020d */
/*00e0*/ IMAD R0, R0, c[0x0][0x8], R17 ; /* 0x0000020000007a24 */
/* 0x008fe200078e0211 */
/*00f0*/ DMUL R4, R2, c[0x0][0x168] ; /* 0x00005a0002047a28 */
/* 0x0040640000000000 */
/*0100*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x001e280000002200 */
/*0110*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e680000001c00 */
/*0120*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe40003f06070 */
/*0140*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x002e620000000000 */
/*0150*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0160*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x002e220000000808 */
/*0170*/ IMAD R12, R0, c[0x0][0x0], R19 ; /* 0x00000000000c7a24 */
/* 0x010fca00078e0213 */
/*0180*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*0190*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*01a0*/ DFMA R10, R10, R8, R6 ; /* 0x000000080a0a722b */
/* 0x001e0c0000000006 */
/*01b0*/ DMUL R8, R4, R10 ; /* 0x0000000a04087228 */
/* 0x001e080000000000 */
/*01c0*/ IADD3 R17, R11, -0x100000, RZ ; /* 0xfff000000b117810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*01e0*/ DFMA R14, R8, -R8, R4 ; /* 0x80000008080e722b */
/* 0x001e0c0000000004 */
/*01f0*/ DFMA R2, R14, R16, R8 ; /* 0x000000100e02722b */
/* 0x0010620000000008 */
/*0200*/ @!P0 BRA 0x250 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0210*/ MOV R0, 0x230 ; /* 0x0000023000007802 */
/* 0x000fca0000000f00 */
/*0220*/ CALL.REL.NOINC 0xb70 ; /* 0x0000094000007944 */
/* 0x003fea0003c00000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, 0x10 ; /* 0x00000010ff0d7424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE.U32 R8, R12, R13, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x001fcc00078e000d */
/*0270*/ LDG.E.128 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1d00 */
/*0280*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x002e220000001800 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*02a0*/ BSSY B0, 0x410 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*02b0*/ IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fc800078e000d */
/*02c0*/ DFMA R6, R4, -R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000802 */
/*02d0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*02e0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*02f0*/ DFMA R4, R6, -R2, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000802 */
/*0300*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e8c0000000006 */
/*0310*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x004e220000000000 */
/*0320*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fca0003f2e200 */
/*0330*/ DFMA R14, R6, -R2, R10 ; /* 0x80000002060e722b */
/* 0x001e0c000000000a */
/*0340*/ DFMA R6, R4, R14, R6 ; /* 0x0000000e0406722b */
/* 0x001e140000000006 */
/*0350*/ FFMA R0, RZ, R3, R7 ; /* 0x00000003ff007223 */
/* 0x001fca0000000007 */
/*0360*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0370*/ @P0 BRA P1, 0x400 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0380*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*0390*/ MOV R24, 0x3e0 ; /* 0x000003e000187802 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*03c0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*03d0*/ CALL.REL.NOINC 0x590 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*03f0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x000e220000001800 */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0430*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe20003f2e200 */
/*0440*/ BSSY B0, 0x570 ; /* 0x0000012000007945 */
/* 0x000fe80003800000 */
/*0450*/ DFMA R10, R4, -R2, 1 ; /* 0x3ff00000040a742b */
/* 0x001e0c0000000802 */
/*0460*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0470*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x001e0c0000000004 */
/*0480*/ DFMA R4, R10, -R2, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c0000000802 */
/*0490*/ DFMA R14, R10, R4, R10 ; /* 0x000000040a0e722b */
/* 0x001e0c000000000a */
/*04a0*/ DMUL R4, R8, R14 ; /* 0x0000000e08047228 */
/* 0x001e0c0000000000 */
/*04b0*/ DFMA R10, R4, -R2, R8 ; /* 0x80000002040a722b */
/* 0x001e0c0000000008 */
/*04c0*/ DFMA R4, R14, R10, R4 ; /* 0x0000000a0e04722b */
/* 0x001e140000000004 */
/*04d0*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x001fca0000000005 */
/*04e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*04f0*/ @P0 BRA P1, 0x560 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0500*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0510*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0530*/ MOV R24, 0x560 ; /* 0x0000056000187802 */
/* 0x000fe20000000f00 */
/*0540*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0550*/ CALL.REL.NOINC 0x590 ; /* 0x0000003000007944 */
/* 0x002fea0003c00000 */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ STG.E.128 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x000fe2000c101d04 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*05a0*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff1a7424 */
/* 0x000fe200078e00ff */
/*05b0*/ LOP3.LUT R14, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b0e7812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; /* 0x00000001ff1c7424 */
/* 0x000fe200078e00ff */
/*05d0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*05e0*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0004 */
/*05f0*/ LOP3.LUT R15, R14, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000e0f7812 */
/* 0x000fe200078efcff */
/*0600*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000a */
/*0610*/ LOP3.LUT R25, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005197812 */
/* 0x000fe200078ec0ff */
/*0620*/ BSSY B1, 0xb30 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0630*/ LOP3.LUT R22, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b167812 */
/* 0x000fc600078ec0ff */
/*0640*/ @!P0 DMUL R14, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a0e8828 */
/* 0x000e220000000000 */
/*0650*/ ISETP.GE.U32.AND P1, PT, R25, R22, PT ; /* 0x000000161900720c */
/* 0x000fe20003f26070 */
/*0660*/ IMAD.MOV.U32 R27, RZ, RZ, R22 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0016 */
/*0670*/ @!P2 LOP3.LUT R0, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b00a812 */
/* 0x000fe200078ec0ff */
/*0680*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0690*/ MUFU.RCP64H R29, R15 ; /* 0x0000000f001d7308 */
/* 0x001e220000001800 */
/*06a0*/ SEL R17, R26, 0x63400000, !P1 ; /* 0x634000001a117807 */
/* 0x000fe40004800000 */
/*06b0*/ @!P2 ISETP.GE.U32.AND P3, PT, R25, R0, PT ; /* 0x000000001900a20c */
/* 0x000fe20003f66070 */
/*06c0*/ IMAD.MOV.U32 R0, RZ, RZ, R25 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0019 */
/*06d0*/ LOP3.LUT R17, R17, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff11117812 */
/* 0x000fc400078ef805 */
/*06e0*/ @!P2 SEL R21, R26, 0x63400000, !P3 ; /* 0x634000001a15a807 */
/* 0x000fe40005800000 */
/*06f0*/ @!P0 LOP3.LUT R27, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f1b8812 */
/* 0x000fe400078ec0ff */
/*0700*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R5, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef805 */
/*0710*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0720*/ DFMA R18, R28, -R14, 1 ; /* 0x3ff000001c12742b */
/* 0x001e0a000000080e */
/*0730*/ @!P2 DFMA R16, R16, 2, -R20 ; /* 0x400000001010a82b */
/* 0x000fc80000000814 */
/*0740*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0750*/ DFMA R18, R28, R18, R28 ; /* 0x000000121c12722b */
/* 0x001062000000001c */
/*0760*/ @!P2 LOP3.LUT R0, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001100a812 */
/* 0x000fe400078ec0ff */
/*0770*/ IADD3 R28, R27, -0x1, RZ ; /* 0xffffffff1b1c7810 */
/* 0x001fe40007ffe0ff */
/*0780*/ IADD3 R22, R0, -0x1, RZ ; /* 0xffffffff00167810 */
/* 0x000fe20007ffe0ff */
/*0790*/ DFMA R20, R18, -R14, 1 ; /* 0x3ff000001214742b */
/* 0x002e06000000080e */
/*07a0*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc60003f04070 */
/*07b0*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x001e220000000012 */
/*07c0*/ ISETP.GT.U32.OR P0, PT, R28, 0x7feffffe, P0 ; /* 0x7feffffe1c00780c */
/* 0x000fca0000704470 */
/*07d0*/ DMUL R20, R18, R16 ; /* 0x0000001012147228 */
/* 0x001e0c0000000000 */
/*07e0*/ DFMA R22, R20, -R14, R16 ; /* 0x8000000e1416722b */
/* 0x001e0c0000000010 */
/*07f0*/ DFMA R22, R18, R22, R20 ; /* 0x000000161216722b */
/* 0x0010620000000014 */
/*0800*/ @P0 BRA 0x9d0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R4, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b047812 */
/* 0x000fc800078ec0ff */
/*0820*/ ISETP.GE.U32.AND P0, PT, R25.reuse, R4, PT ; /* 0x000000041900720c */
/* 0x040fe20003f06070 */
/*0830*/ IMAD.IADD R0, R25, 0x1, -R4 ; /* 0x0000000119007824 */
/* 0x000fe400078e0a04 */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0850*/ SEL R5, R26, 0x63400000, !P0 ; /* 0x634000001a057807 */
/* 0x000fe40004000000 */
/*0860*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fc80007800200 */
/*0870*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*0880*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a05 */
/*0890*/ IADD3 R5, R0, 0x7fe00000, RZ ; /* 0x7fe0000000057810 */
/* 0x000fcc0007ffe0ff */
/*08a0*/ DMUL R18, R22, R4 ; /* 0x0000000416127228 */
/* 0x003e140000000000 */
/*08b0*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*08c0*/ @P0 BRA 0xb20 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*08d0*/ DFMA R14, R22, -R14, R16 ; /* 0x8000000e160e722b */
/* 0x000e220000000010 */
/*08e0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*08f0*/ FSETP.NEU.AND P0, PT, R15.reuse, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x041fe40003f0d000 */
/*0900*/ LOP3.LUT R17, R15, 0x80000000, R11, 0x48, !PT ; /* 0x800000000f117812 */
/* 0x000fc800078e480b */
/*0910*/ LOP3.LUT R5, R17, R5, RZ, 0xfc, !PT ; /* 0x0000000511057212 */
/* 0x000fce00078efcff */
/*0920*/ @!P0 BRA 0xb20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*0940*/ DMUL.RP R4, R22, R4 ; /* 0x0000000416047228 */
/* 0x000e220000008000 */
/*0950*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fcc00078e00ff */
/*0960*/ DFMA R10, R18, -R10, R22 ; /* 0x8000000a120a722b */
/* 0x000e460000000016 */
/*0970*/ LOP3.LUT R17, R5, R17, RZ, 0x3c, !PT ; /* 0x0000001105117212 */
/* 0x001fc600078e3cff */
/*0980*/ IADD3 R10, -R0, -0x43300000, RZ ; /* 0xbcd00000000a7810 */
/* 0x002fc80007ffe1ff */
/*0990*/ FSETP.NEU.AND P0, PT, |R11|, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fc80003f0d200 */
/*09a0*/ FSEL R18, R4, R18, !P0 ; /* 0x0000001204127208 */
/* 0x000fe40004000000 */
/*09b0*/ FSEL R19, R17, R19, !P0 ; /* 0x0000001311137208 */
/* 0x000fe20004000000 */
/*09c0*/ BRA 0xb20 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*09d0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*09e0*/ @P0 BRA 0xb00 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*09f0*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*0a00*/ @P0 BRA 0xad0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0a10*/ ISETP.NE.AND P0, PT, R0, R27, PT ; /* 0x0000001b0000720c */
/* 0x000fe20003f05270 */
/*0a20*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0a30*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0a40*/ @!P0 BRA 0xb20 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*0a60*/ LOP3.LUT R19, R5, 0x80000000, R11, 0x48, !PT ; /* 0x8000000005137812 */
/* 0x000fe400078e480b */
/*0a70*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*0a80*/ @P0 LOP3.LUT R0, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013000812 */
/* 0x000fe200078efcff */
/*0a90*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0aa0*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0ab0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R0 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0000 */
/*0ac0*/ BRA 0xb20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ad0*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x001fe200078efcff */
/*0ae0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000a */
/*0af0*/ BRA 0xb20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT R19, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005137812 */
/* 0x001fe200078efcff */
/*0b10*/ IMAD.MOV.U32 R18, RZ, RZ, R4 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0004 */
/*0b20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b30*/ IMAD.MOV.U32 R25, RZ, RZ, 0x0 ; /* 0x00000000ff197424 */
/* 0x000fe400078e00ff */
/*0b40*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0012 */
/*0b50*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*0b60*/ RET.REL.NODEC R24 0x0 ; /* 0xfffff49018007950 */
/* 0x000fec0003c3ffff */
/*0b70*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe40003f06070 */
/*0b80*/ MOV R11, R17 ; /* 0x00000011000b7202 */
/* 0x000fd60000000f00 */
/*0b90*/ @!P0 BRA 0xc20 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ DFMA.RM R8, R14, R10, R8 ; /* 0x0000000a0e08722b */
/* 0x000e140000004008 */
/*0bb0*/ IADD3 R2, P0, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x001fca0007f1e0ff */
/*0bc0*/ IMAD.X R3, RZ, RZ, R9, P0 ; /* 0x000000ffff037224 */
/* 0x000fcc00000e0609 */
/*0bd0*/ DFMA.RP R4, -R8, R2, R4 ; /* 0x000000020804722b */
/* 0x000e0c0000008104 */
/*0be0*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x001e0c0003f04000 */
/*0bf0*/ FSEL R2, R2, R8, P0 ; /* 0x0000000802027208 */
/* 0x001fe40000000000 */
/*0c00*/ FSEL R3, R3, R9, P0 ; /* 0x0000000903037208 */
/* 0x000fe20000000000 */
/*0c10*/ BRA 0xdb0 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0c20*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e1c0003f05000 */
/*0c30*/ @!P0 BRA 0xda0 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*0c40*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0c50*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff028424 */
/* 0x000fe400078e00ff */
/*0c60*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, -0x80000 ; /* 0xfff80000ff038424 */
/* 0x000fe200078e00ff */
/*0c70*/ @!P0 BRA 0xdb0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f04270 */
/*0c90*/ @P0 BRA 0xda0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0ca0*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0cb0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0cc0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0cd0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff097424 */
/* 0x000fe200078e00ff */
/*0ce0*/ MUFU.RSQ64H R3, R5 ; /* 0x0000000500037308 */
/* 0x001e240000001c00 */
/*0cf0*/ DMUL R6, R2, R2 ; /* 0x0000000202067228 */
/* 0x001e0c0000000000 */
/*0d00*/ DFMA R6, R4, -R6, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000806 */
/*0d10*/ DFMA R8, R6, R8, 0.5 ; /* 0x3fe000000608742b */
/* 0x001fc80000000008 */
/*0d20*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x000e0c0000000000 */
/*0d30*/ DFMA R6, R8, R6, R2 ; /* 0x000000060806722b */
/* 0x001e0c0000000002 */
/*0d40*/ DMUL R2, R4, R6 ; /* 0x0000000604027228 */
/* 0x0010480000000000 */
/*0d50*/ IADD3 R7, R7, -0x100000, RZ ; /* 0xfff0000007077810 */
/* 0x001fe40007ffe0ff */
/*0d60*/ DFMA R8, R2, -R2, R4 ; /* 0x800000020208722b */
/* 0x002e0c0000000004 */
/*0d70*/ DFMA R2, R6, R8, R2 ; /* 0x000000080602722b */
/* 0x001e140000000002 */
/*0d80*/ IADD3 R3, R3, -0x3500000, RZ ; /* 0xfcb0000003037810 */
/* 0x001fe20007ffe0ff */
/*0d90*/ BRA 0xdb0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0da0*/ DADD R2, R4, R4 ; /* 0x0000000004027229 */
/* 0x0000540000000004 */
/*0db0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x003fe400078e0002 */
/*0dc0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*0dd0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0de0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0df0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff20002007950 */
/* 0x000fea0003c3ffff */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void scalarDiv_wfcNorm(double2* in, double dr, double* pSum, double2* out){
unsigned int gid = getGid3d3d();
double2 result;
double norm = sqrt((pSum[0])*dr);
result.x = (in[gid].x/norm);
result.y = (in[gid].y/norm);
out[gid] = result;
} | .file "tmpxft_0004334b_00000000-6_scalarDiv_wfcNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_
.type _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_, @function
_Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17scalarDiv_wfcNormP7double2dPdS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_, .-_Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_
.globl _Z17scalarDiv_wfcNormP7double2dPdS0_
.type _Z17scalarDiv_wfcNormP7double2dPdS0_, @function
_Z17scalarDiv_wfcNormP7double2dPdS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17scalarDiv_wfcNormP7double2dPdS0_, .-_Z17scalarDiv_wfcNormP7double2dPdS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17scalarDiv_wfcNormP7double2dPdS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17scalarDiv_wfcNormP7double2dPdS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void scalarDiv_wfcNorm(double2* in, double dr, double* pSum, double2* out){
unsigned int gid = getGid3d3d();
double2 result;
double norm = sqrt((pSum[0])*dr);
result.x = (in[gid].x/norm);
result.y = (in[gid].y/norm);
out[gid] = result;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void scalarDiv_wfcNorm(double2* in, double dr, double* pSum, double2* out){
unsigned int gid = getGid3d3d();
double2 result;
double norm = sqrt((pSum[0])*dr);
result.x = (in[gid].x/norm);
result.y = (in[gid].y/norm);
out[gid] = result;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void scalarDiv_wfcNorm(double2* in, double dr, double* pSum, double2* out){
unsigned int gid = getGid3d3d();
double2 result;
double norm = sqrt((pSum[0])*dr);
result.x = (in[gid].x/norm);
result.y = (in[gid].y/norm);
out[gid] = result;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.globl _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.p2align 8
.type _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_,@function
_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_:
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_load_b64 s[8:9], s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s3, s13
s_cmp_lt_u32 s13, s2
s_cselect_b32 s2, 12, 18
v_mov_b32_e32 v1, s2
global_load_u16 v10, v1, s[4:5]
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f64 v[1:2], s[4:5], s[2:3]
s_and_b32 s2, s9, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[1:2], v3
v_bfe_u32 v1, v0, 20, 10
v_mad_u64_u32 v[2:3], null, s10, s2, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s2, s8, 16
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v2, s2, v[1:2]
v_rsq_f64_e32 v[6:7], v[4:5]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v8, v10, v[0:1]
v_mov_b32_e32 v2, 0
s_waitcnt_depctr 0xfff
v_mul_f64 v[10:11], v[4:5], v[6:7]
v_mul_f64 v[6:7], v[6:7], 0.5
v_lshlrev_b64 v[8:9], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v8
v_add_co_ci_u32_e64 v1, s0, s1, v9, s0
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s0, 0xffffff80, 0
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x260
global_load_b128 v[0:3], v[0:1], off
v_fma_f64 v[12:13], -v[6:7], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
v_fma_f64 v[12:13], -v[10:11], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[6:7], v[10:11]
v_fma_f64 v[12:13], -v[10:11], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[12:13], v[6:7], v[10:11]
v_ldexp_f64 v[6:7], v[6:7], s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[0:1]
v_div_scale_f64 v[10:11], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[12:13], v[6:7]
v_rcp_f64_e32 v[14:15], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[6:7], v[12:13], 1.0
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], -v[6:7], v[12:13], 1.0
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_div_scale_f64 v[16:17], s0, v[2:3], v[4:5], v[2:3]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[18:19], v[20:21], v[12:13]
v_mul_f64 v[22:23], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], -v[6:7], v[18:19], v[20:21]
v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[18:19]
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[0:1], v[6:7], v[4:5], v[0:1]
v_div_fixup_f64 v[2:3], v[10:11], v[4:5], v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, .Lfunc_end0-_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void scalarDiv_wfcNorm(double2* in, double dr, double* pSum, double2* out){
unsigned int gid = getGid3d3d();
double2 result;
double norm = sqrt((pSum[0])*dr);
result.x = (in[gid].x/norm);
result.y = (in[gid].y/norm);
out[gid] = result;
} | .text
.file "scalarDiv_wfcNorm.hip"
.globl _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_ # -- Begin function _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.p2align 4, 0x90
.type _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_,@function
_Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_: # @_Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
movq %rdx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, .Lfunc_end0-_Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_,@object # @_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.section .rodata,"a",@progbits
.globl _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.p2align 3, 0x0
_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_:
.quad _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.size _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17scalarDiv_wfcNormP7double2dPdS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fcc00078e00ff */
/*0040*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0080*/ S2R R15, SR_CTAID.Z ; /* 0x00000000000f7919 */
/* 0x000e280000002700 */
/*0090*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e680000002500 */
/*00a0*/ S2R R17, SR_TID.Z ; /* 0x0000000000117919 */
/* 0x000ee80000002300 */
/*00b0*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000f220000002100 */
/*00c0*/ IMAD R0, R15, c[0x0][0x10], R0 ; /* 0x000004000f007a24 */
/* 0x001fc800078e0200 */
/*00d0*/ IMAD R0, R0, c[0x0][0xc], R13 ; /* 0x0000030000007a24 */
/* 0x002fc800078e020d */
/*00e0*/ IMAD R0, R0, c[0x0][0x8], R17 ; /* 0x0000020000007a24 */
/* 0x008fe200078e0211 */
/*00f0*/ DMUL R4, R2, c[0x0][0x168] ; /* 0x00005a0002047a28 */
/* 0x0040640000000000 */
/*0100*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x001e280000002200 */
/*0110*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e680000001c00 */
/*0120*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */
/* 0x000fc80007ffe0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe40003f06070 */
/*0140*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x002e620000000000 */
/*0150*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0160*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x002e220000000808 */
/*0170*/ IMAD R12, R0, c[0x0][0x0], R19 ; /* 0x00000000000c7a24 */
/* 0x010fca00078e0213 */
/*0180*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*0190*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*01a0*/ DFMA R10, R10, R8, R6 ; /* 0x000000080a0a722b */
/* 0x001e0c0000000006 */
/*01b0*/ DMUL R8, R4, R10 ; /* 0x0000000a04087228 */
/* 0x001e080000000000 */
/*01c0*/ IADD3 R17, R11, -0x100000, RZ ; /* 0xfff000000b117810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*01e0*/ DFMA R14, R8, -R8, R4 ; /* 0x80000008080e722b */
/* 0x001e0c0000000004 */
/*01f0*/ DFMA R2, R14, R16, R8 ; /* 0x000000100e02722b */
/* 0x0010620000000008 */
/*0200*/ @!P0 BRA 0x250 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0210*/ MOV R0, 0x230 ; /* 0x0000023000007802 */
/* 0x000fca0000000f00 */
/*0220*/ CALL.REL.NOINC 0xb70 ; /* 0x0000094000007944 */
/* 0x003fea0003c00000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, 0x10 ; /* 0x00000010ff0d7424 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD.WIDE.U32 R8, R12, R13, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x001fcc00078e000d */
/*0270*/ LDG.E.128 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1d00 */
/*0280*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x002e220000001800 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*02a0*/ BSSY B0, 0x410 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*02b0*/ IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fc800078e000d */
/*02c0*/ DFMA R6, R4, -R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000802 */
/*02d0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*02e0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*02f0*/ DFMA R4, R6, -R2, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000802 */
/*0300*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e8c0000000006 */
/*0310*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x004e220000000000 */
/*0320*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fca0003f2e200 */
/*0330*/ DFMA R14, R6, -R2, R10 ; /* 0x80000002060e722b */
/* 0x001e0c000000000a */
/*0340*/ DFMA R6, R4, R14, R6 ; /* 0x0000000e0406722b */
/* 0x001e140000000006 */
/*0350*/ FFMA R0, RZ, R3, R7 ; /* 0x00000003ff007223 */
/* 0x001fca0000000007 */
/*0360*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0370*/ @P0 BRA P1, 0x400 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0380*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*0390*/ MOV R24, 0x3e0 ; /* 0x000003e000187802 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*03c0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*03d0*/ CALL.REL.NOINC 0x590 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*03f0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x000e220000001800 */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0430*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe20003f2e200 */
/*0440*/ BSSY B0, 0x570 ; /* 0x0000012000007945 */
/* 0x000fe80003800000 */
/*0450*/ DFMA R10, R4, -R2, 1 ; /* 0x3ff00000040a742b */
/* 0x001e0c0000000802 */
/*0460*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0470*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x001e0c0000000004 */
/*0480*/ DFMA R4, R10, -R2, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c0000000802 */
/*0490*/ DFMA R14, R10, R4, R10 ; /* 0x000000040a0e722b */
/* 0x001e0c000000000a */
/*04a0*/ DMUL R4, R8, R14 ; /* 0x0000000e08047228 */
/* 0x001e0c0000000000 */
/*04b0*/ DFMA R10, R4, -R2, R8 ; /* 0x80000002040a722b */
/* 0x001e0c0000000008 */
/*04c0*/ DFMA R4, R14, R10, R4 ; /* 0x0000000a0e04722b */
/* 0x001e140000000004 */
/*04d0*/ FFMA R0, RZ, R3, R5 ; /* 0x00000003ff007223 */
/* 0x001fca0000000005 */
/*04e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*04f0*/ @P0 BRA P1, 0x560 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0500*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0510*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0530*/ MOV R24, 0x560 ; /* 0x0000056000187802 */
/* 0x000fe20000000f00 */
/*0540*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0550*/ CALL.REL.NOINC 0x590 ; /* 0x0000003000007944 */
/* 0x002fea0003c00000 */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ STG.E.128 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x000fe2000c101d04 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*05a0*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff1a7424 */
/* 0x000fe200078e00ff */
/*05b0*/ LOP3.LUT R14, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b0e7812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; /* 0x00000001ff1c7424 */
/* 0x000fe200078e00ff */
/*05d0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*05e0*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0004 */
/*05f0*/ LOP3.LUT R15, R14, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000e0f7812 */
/* 0x000fe200078efcff */
/*0600*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000a */
/*0610*/ LOP3.LUT R25, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005197812 */
/* 0x000fe200078ec0ff */
/*0620*/ BSSY B1, 0xb30 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0630*/ LOP3.LUT R22, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b167812 */
/* 0x000fc600078ec0ff */
/*0640*/ @!P0 DMUL R14, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a0e8828 */
/* 0x000e220000000000 */
/*0650*/ ISETP.GE.U32.AND P1, PT, R25, R22, PT ; /* 0x000000161900720c */
/* 0x000fe20003f26070 */
/*0660*/ IMAD.MOV.U32 R27, RZ, RZ, R22 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0016 */
/*0670*/ @!P2 LOP3.LUT R0, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b00a812 */
/* 0x000fe200078ec0ff */
/*0680*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0690*/ MUFU.RCP64H R29, R15 ; /* 0x0000000f001d7308 */
/* 0x001e220000001800 */
/*06a0*/ SEL R17, R26, 0x63400000, !P1 ; /* 0x634000001a117807 */
/* 0x000fe40004800000 */
/*06b0*/ @!P2 ISETP.GE.U32.AND P3, PT, R25, R0, PT ; /* 0x000000001900a20c */
/* 0x000fe20003f66070 */
/*06c0*/ IMAD.MOV.U32 R0, RZ, RZ, R25 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0019 */
/*06d0*/ LOP3.LUT R17, R17, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff11117812 */
/* 0x000fc400078ef805 */
/*06e0*/ @!P2 SEL R21, R26, 0x63400000, !P3 ; /* 0x634000001a15a807 */
/* 0x000fe40005800000 */
/*06f0*/ @!P0 LOP3.LUT R27, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f1b8812 */
/* 0x000fe400078ec0ff */
/*0700*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R5, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef805 */
/*0710*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0720*/ DFMA R18, R28, -R14, 1 ; /* 0x3ff000001c12742b */
/* 0x001e0a000000080e */
/*0730*/ @!P2 DFMA R16, R16, 2, -R20 ; /* 0x400000001010a82b */
/* 0x000fc80000000814 */
/*0740*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0750*/ DFMA R18, R28, R18, R28 ; /* 0x000000121c12722b */
/* 0x001062000000001c */
/*0760*/ @!P2 LOP3.LUT R0, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001100a812 */
/* 0x000fe400078ec0ff */
/*0770*/ IADD3 R28, R27, -0x1, RZ ; /* 0xffffffff1b1c7810 */
/* 0x001fe40007ffe0ff */
/*0780*/ IADD3 R22, R0, -0x1, RZ ; /* 0xffffffff00167810 */
/* 0x000fe20007ffe0ff */
/*0790*/ DFMA R20, R18, -R14, 1 ; /* 0x3ff000001214742b */
/* 0x002e06000000080e */
/*07a0*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc60003f04070 */
/*07b0*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x001e220000000012 */
/*07c0*/ ISETP.GT.U32.OR P0, PT, R28, 0x7feffffe, P0 ; /* 0x7feffffe1c00780c */
/* 0x000fca0000704470 */
/*07d0*/ DMUL R20, R18, R16 ; /* 0x0000001012147228 */
/* 0x001e0c0000000000 */
/*07e0*/ DFMA R22, R20, -R14, R16 ; /* 0x8000000e1416722b */
/* 0x001e0c0000000010 */
/*07f0*/ DFMA R22, R18, R22, R20 ; /* 0x000000161216722b */
/* 0x0010620000000014 */
/*0800*/ @P0 BRA 0x9d0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R4, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b047812 */
/* 0x000fc800078ec0ff */
/*0820*/ ISETP.GE.U32.AND P0, PT, R25.reuse, R4, PT ; /* 0x000000041900720c */
/* 0x040fe20003f06070 */
/*0830*/ IMAD.IADD R0, R25, 0x1, -R4 ; /* 0x0000000119007824 */
/* 0x000fe400078e0a04 */
/*0840*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0850*/ SEL R5, R26, 0x63400000, !P0 ; /* 0x634000001a057807 */
/* 0x000fe40004000000 */
/*0860*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fc80007800200 */
/*0870*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*0880*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a05 */
/*0890*/ IADD3 R5, R0, 0x7fe00000, RZ ; /* 0x7fe0000000057810 */
/* 0x000fcc0007ffe0ff */
/*08a0*/ DMUL R18, R22, R4 ; /* 0x0000000416127228 */
/* 0x003e140000000000 */
/*08b0*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*08c0*/ @P0 BRA 0xb20 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*08d0*/ DFMA R14, R22, -R14, R16 ; /* 0x8000000e160e722b */
/* 0x000e220000000010 */
/*08e0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*08f0*/ FSETP.NEU.AND P0, PT, R15.reuse, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x041fe40003f0d000 */
/*0900*/ LOP3.LUT R17, R15, 0x80000000, R11, 0x48, !PT ; /* 0x800000000f117812 */
/* 0x000fc800078e480b */
/*0910*/ LOP3.LUT R5, R17, R5, RZ, 0xfc, !PT ; /* 0x0000000511057212 */
/* 0x000fce00078efcff */
/*0920*/ @!P0 BRA 0xb20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0930*/ IMAD.MOV R11, RZ, RZ, -R0 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a00 */
/*0940*/ DMUL.RP R4, R22, R4 ; /* 0x0000000416047228 */
/* 0x000e220000008000 */
/*0950*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fcc00078e00ff */
/*0960*/ DFMA R10, R18, -R10, R22 ; /* 0x8000000a120a722b */
/* 0x000e460000000016 */
/*0970*/ LOP3.LUT R17, R5, R17, RZ, 0x3c, !PT ; /* 0x0000001105117212 */
/* 0x001fc600078e3cff */
/*0980*/ IADD3 R10, -R0, -0x43300000, RZ ; /* 0xbcd00000000a7810 */
/* 0x002fc80007ffe1ff */
/*0990*/ FSETP.NEU.AND P0, PT, |R11|, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fc80003f0d200 */
/*09a0*/ FSEL R18, R4, R18, !P0 ; /* 0x0000001204127208 */
/* 0x000fe40004000000 */
/*09b0*/ FSEL R19, R17, R19, !P0 ; /* 0x0000001311137208 */
/* 0x000fe20004000000 */
/*09c0*/ BRA 0xb20 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*09d0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*09e0*/ @P0 BRA 0xb00 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*09f0*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*0a00*/ @P0 BRA 0xad0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0a10*/ ISETP.NE.AND P0, PT, R0, R27, PT ; /* 0x0000001b0000720c */
/* 0x000fe20003f05270 */
/*0a20*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0a30*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0a40*/ @!P0 BRA 0xb20 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*0a60*/ LOP3.LUT R19, R5, 0x80000000, R11, 0x48, !PT ; /* 0x8000000005137812 */
/* 0x000fe400078e480b */
/*0a70*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*0a80*/ @P0 LOP3.LUT R0, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013000812 */
/* 0x000fe200078efcff */
/*0a90*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0aa0*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0ab0*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R0 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0000 */
/*0ac0*/ BRA 0xb20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ad0*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x001fe200078efcff */
/*0ae0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000a */
/*0af0*/ BRA 0xb20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT R19, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005137812 */
/* 0x001fe200078efcff */
/*0b10*/ IMAD.MOV.U32 R18, RZ, RZ, R4 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0004 */
/*0b20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b30*/ IMAD.MOV.U32 R25, RZ, RZ, 0x0 ; /* 0x00000000ff197424 */
/* 0x000fe400078e00ff */
/*0b40*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0012 */
/*0b50*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*0b60*/ RET.REL.NODEC R24 0x0 ; /* 0xfffff49018007950 */
/* 0x000fec0003c3ffff */
/*0b70*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe40003f06070 */
/*0b80*/ MOV R11, R17 ; /* 0x00000011000b7202 */
/* 0x000fd60000000f00 */
/*0b90*/ @!P0 BRA 0xc20 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ DFMA.RM R8, R14, R10, R8 ; /* 0x0000000a0e08722b */
/* 0x000e140000004008 */
/*0bb0*/ IADD3 R2, P0, R8, 0x1, RZ ; /* 0x0000000108027810 */
/* 0x001fca0007f1e0ff */
/*0bc0*/ IMAD.X R3, RZ, RZ, R9, P0 ; /* 0x000000ffff037224 */
/* 0x000fcc00000e0609 */
/*0bd0*/ DFMA.RP R4, -R8, R2, R4 ; /* 0x000000020804722b */
/* 0x000e0c0000008104 */
/*0be0*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x001e0c0003f04000 */
/*0bf0*/ FSEL R2, R2, R8, P0 ; /* 0x0000000802027208 */
/* 0x001fe40000000000 */
/*0c00*/ FSEL R3, R3, R9, P0 ; /* 0x0000000903037208 */
/* 0x000fe20000000000 */
/*0c10*/ BRA 0xdb0 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0c20*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e1c0003f05000 */
/*0c30*/ @!P0 BRA 0xda0 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*0c40*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0c50*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff028424 */
/* 0x000fe400078e00ff */
/*0c60*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, -0x80000 ; /* 0xfff80000ff038424 */
/* 0x000fe200078e00ff */
/*0c70*/ @!P0 BRA 0xdb0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f04270 */
/*0c90*/ @P0 BRA 0xda0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0ca0*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0cb0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0cc0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0cd0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff097424 */
/* 0x000fe200078e00ff */
/*0ce0*/ MUFU.RSQ64H R3, R5 ; /* 0x0000000500037308 */
/* 0x001e240000001c00 */
/*0cf0*/ DMUL R6, R2, R2 ; /* 0x0000000202067228 */
/* 0x001e0c0000000000 */
/*0d00*/ DFMA R6, R4, -R6, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000806 */
/*0d10*/ DFMA R8, R6, R8, 0.5 ; /* 0x3fe000000608742b */
/* 0x001fc80000000008 */
/*0d20*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x000e0c0000000000 */
/*0d30*/ DFMA R6, R8, R6, R2 ; /* 0x000000060806722b */
/* 0x001e0c0000000002 */
/*0d40*/ DMUL R2, R4, R6 ; /* 0x0000000604027228 */
/* 0x0010480000000000 */
/*0d50*/ IADD3 R7, R7, -0x100000, RZ ; /* 0xfff0000007077810 */
/* 0x001fe40007ffe0ff */
/*0d60*/ DFMA R8, R2, -R2, R4 ; /* 0x800000020208722b */
/* 0x002e0c0000000004 */
/*0d70*/ DFMA R2, R6, R8, R2 ; /* 0x000000080602722b */
/* 0x001e140000000002 */
/*0d80*/ IADD3 R3, R3, -0x3500000, RZ ; /* 0xfcb0000003037810 */
/* 0x001fe20007ffe0ff */
/*0d90*/ BRA 0xdb0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0da0*/ DADD R2, R4, R4 ; /* 0x0000000004027229 */
/* 0x0000540000000004 */
/*0db0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x003fe400078e0002 */
/*0dc0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*0dd0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0de0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0df0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff20002007950 */
/* 0x000fea0003c3ffff */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.globl _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.p2align 8
.type _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_,@function
_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_:
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_load_b64 s[8:9], s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s10, s3, s13
s_cmp_lt_u32 s13, s2
s_cselect_b32 s2, 12, 18
v_mov_b32_e32 v1, s2
global_load_u16 v10, v1, s[4:5]
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f64 v[1:2], s[4:5], s[2:3]
s_and_b32 s2, s9, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[1:2], v3
v_bfe_u32 v1, v0, 20, 10
v_mad_u64_u32 v[2:3], null, s10, s2, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s2, s8, 16
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v2, s2, v[1:2]
v_rsq_f64_e32 v[6:7], v[4:5]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[1:2], null, v8, v10, v[0:1]
v_mov_b32_e32 v2, 0
s_waitcnt_depctr 0xfff
v_mul_f64 v[10:11], v[4:5], v[6:7]
v_mul_f64 v[6:7], v[6:7], 0.5
v_lshlrev_b64 v[8:9], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v8
v_add_co_ci_u32_e64 v1, s0, s1, v9, s0
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s0, 0xffffff80, 0
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x260
global_load_b128 v[0:3], v[0:1], off
v_fma_f64 v[12:13], -v[6:7], v[10:11], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
v_fma_f64 v[12:13], -v[10:11], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[6:7], v[10:11]
v_fma_f64 v[12:13], -v[10:11], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[12:13], v[6:7], v[10:11]
v_ldexp_f64 v[6:7], v[6:7], s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[0:1]
v_div_scale_f64 v[10:11], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[12:13], v[6:7]
v_rcp_f64_e32 v[14:15], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[6:7], v[12:13], 1.0
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], -v[6:7], v[12:13], 1.0
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
v_div_scale_f64 v[16:17], s0, v[2:3], v[4:5], v[2:3]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[18:19], v[20:21], v[12:13]
v_mul_f64 v[22:23], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], -v[6:7], v[18:19], v[20:21]
v_fma_f64 v[10:11], -v[10:11], v[22:23], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[18:19]
s_mov_b32 vcc_lo, s0
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[0:1], v[6:7], v[4:5], v[0:1]
v_div_fixup_f64 v[2:3], v[10:11], v[4:5], v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, .Lfunc_end0-_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004334b_00000000-6_scalarDiv_wfcNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_
.type _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_, @function
_Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17scalarDiv_wfcNormP7double2dPdS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_, .-_Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_
.globl _Z17scalarDiv_wfcNormP7double2dPdS0_
.type _Z17scalarDiv_wfcNormP7double2dPdS0_, @function
_Z17scalarDiv_wfcNormP7double2dPdS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z17scalarDiv_wfcNormP7double2dPdS0_P7double2dPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17scalarDiv_wfcNormP7double2dPdS0_, .-_Z17scalarDiv_wfcNormP7double2dPdS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17scalarDiv_wfcNormP7double2dPdS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17scalarDiv_wfcNormP7double2dPdS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scalarDiv_wfcNorm.hip"
.globl _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_ # -- Begin function _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.p2align 4, 0x90
.type _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_,@function
_Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_: # @_Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movq %rsi, 56(%rsp)
movq %rdx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, .Lfunc_end0-_Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_,@object # @_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.section .rodata,"a",@progbits
.globl _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.p2align 3, 0x0
_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_:
.quad _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.size _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17scalarDiv_wfcNormP15HIP_vector_typeIdLj2EEdPdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void profilePhaseSolve_kernel() {} | code for sm_80
Function : _Z24profilePhaseSolve_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void profilePhaseSolve_kernel() {} | .file "tmpxft_0015d78c_00000000-6_profilePhaseSolve_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z24profilePhaseSolve_kernelvv
.type _Z43__device_stub__Z24profilePhaseSolve_kernelvv, @function
_Z43__device_stub__Z24profilePhaseSolve_kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z24profilePhaseSolve_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z24profilePhaseSolve_kernelvv, .-_Z43__device_stub__Z24profilePhaseSolve_kernelvv
.globl _Z24profilePhaseSolve_kernelv
.type _Z24profilePhaseSolve_kernelv, @function
_Z24profilePhaseSolve_kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24profilePhaseSolve_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24profilePhaseSolve_kernelv, .-_Z24profilePhaseSolve_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z24profilePhaseSolve_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24profilePhaseSolve_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void profilePhaseSolve_kernel() {} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void profilePhaseSolve_kernel() {} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void profilePhaseSolve_kernel() {} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24profilePhaseSolve_kernelv
.globl _Z24profilePhaseSolve_kernelv
.p2align 8
.type _Z24profilePhaseSolve_kernelv,@function
_Z24profilePhaseSolve_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24profilePhaseSolve_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24profilePhaseSolve_kernelv, .Lfunc_end0-_Z24profilePhaseSolve_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24profilePhaseSolve_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z24profilePhaseSolve_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void profilePhaseSolve_kernel() {} | .text
.file "profilePhaseSolve_kernel.hip"
.globl _Z39__device_stub__profilePhaseSolve_kernelv # -- Begin function _Z39__device_stub__profilePhaseSolve_kernelv
.p2align 4, 0x90
.type _Z39__device_stub__profilePhaseSolve_kernelv,@function
_Z39__device_stub__profilePhaseSolve_kernelv: # @_Z39__device_stub__profilePhaseSolve_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24profilePhaseSolve_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z39__device_stub__profilePhaseSolve_kernelv, .Lfunc_end0-_Z39__device_stub__profilePhaseSolve_kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24profilePhaseSolve_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24profilePhaseSolve_kernelv,@object # @_Z24profilePhaseSolve_kernelv
.section .rodata,"a",@progbits
.globl _Z24profilePhaseSolve_kernelv
.p2align 3, 0x0
_Z24profilePhaseSolve_kernelv:
.quad _Z39__device_stub__profilePhaseSolve_kernelv
.size _Z24profilePhaseSolve_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24profilePhaseSolve_kernelv"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__profilePhaseSolve_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24profilePhaseSolve_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24profilePhaseSolve_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24profilePhaseSolve_kernelv
.globl _Z24profilePhaseSolve_kernelv
.p2align 8
.type _Z24profilePhaseSolve_kernelv,@function
_Z24profilePhaseSolve_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24profilePhaseSolve_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24profilePhaseSolve_kernelv, .Lfunc_end0-_Z24profilePhaseSolve_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24profilePhaseSolve_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z24profilePhaseSolve_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015d78c_00000000-6_profilePhaseSolve_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z24profilePhaseSolve_kernelvv
.type _Z43__device_stub__Z24profilePhaseSolve_kernelvv, @function
_Z43__device_stub__Z24profilePhaseSolve_kernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z24profilePhaseSolve_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z24profilePhaseSolve_kernelvv, .-_Z43__device_stub__Z24profilePhaseSolve_kernelvv
.globl _Z24profilePhaseSolve_kernelv
.type _Z24profilePhaseSolve_kernelv, @function
_Z24profilePhaseSolve_kernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24profilePhaseSolve_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24profilePhaseSolve_kernelv, .-_Z24profilePhaseSolve_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z24profilePhaseSolve_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24profilePhaseSolve_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "profilePhaseSolve_kernel.hip"
.globl _Z39__device_stub__profilePhaseSolve_kernelv # -- Begin function _Z39__device_stub__profilePhaseSolve_kernelv
.p2align 4, 0x90
.type _Z39__device_stub__profilePhaseSolve_kernelv,@function
_Z39__device_stub__profilePhaseSolve_kernelv: # @_Z39__device_stub__profilePhaseSolve_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24profilePhaseSolve_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z39__device_stub__profilePhaseSolve_kernelv, .Lfunc_end0-_Z39__device_stub__profilePhaseSolve_kernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24profilePhaseSolve_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24profilePhaseSolve_kernelv,@object # @_Z24profilePhaseSolve_kernelv
.section .rodata,"a",@progbits
.globl _Z24profilePhaseSolve_kernelv
.p2align 3, 0x0
_Z24profilePhaseSolve_kernelv:
.quad _Z39__device_stub__profilePhaseSolve_kernelv
.size _Z24profilePhaseSolve_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24profilePhaseSolve_kernelv"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__profilePhaseSolve_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24profilePhaseSolve_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime_api.h>
#include <errno.h>
/*
To compile:
nvcc -o NishantLinear NishantLinear.cu
./NishantLinear
*/
typedef struct point_t {
double x;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000;
point_t data[] = {
{74.32,120.84},{65.26,121.98},{77.84,134.32},{69.57,135.09},
{83.26,119.06},{83.05,140.32},{65.65,115.63},{76.75,151.06},
{84.45,150.47},{69.40,138.40},{82.03,147.61},{27.33,61.48},
{25.60,51.97},{38.04,88.45},{77.76,145.24},{28.43,81.89},
{31.71,78.13},{27.36,73.40},{54.04,109.85},{43.06,91.41},
{36.52,83.97},{43.11,96.10},{ 6.18,29.10},{92.31,165.55},
{67.81,143.99},{25.45,55.32},{54.02,90.03},{28.22,64.80},
{62.75,111.23},{36.57,71.48},{94.73,155.45},{79.13,153.33},
{27.86,72.36},{20.11,65.43},{59.94,114.35},{85.52,155.16},
{85.37,140.60},{65.97,118.83},{88.21,169.64},{35.79,83.69},
{21.90,73.79},{56.63,128.76},{91.98,165.94},{ 1.36,37.69},
{81.26,139.19},{71.64,107.32},{85.98,163.26},{93.96,162.49},
{79.91,145.04},{ 6.11,39.39},{44.73,73.84},{68.92,139.47},
{77.18,141.98},{72.13,129.30},{50.28,108.96},{61.16,111.38},
{66.14,140.93},{44.08,97.81},{16.77,40.34},{16.70,50.86},
{59.13,112.08},{15.15,59.60},{93.81,143.23},{49.23,92.65},
{32.74,67.49},{68.25,126.33},{ 9.56,36.93},{31.83,75.94},
{40.71,87.30},{11.10,40.29},{58.04,126.23},{95.12,134.62},
{ 0.68,28.04},{19.12,60.55},{84.81,155.16},{38.99,88.37},
{66.88,123.61},{ 6.86,42.43},{93.37,137.53},{15.58,59.18},
{ 0.30,31.59},{88.57,143.82},{87.95,165.66},{40.17,87.81},
{13.46,58.73},{44.00,76.35},{25.69,68.91},{62.71,112.10},
{91.10,153.90},{73.52,130.98},{16.42,41.91},{ 5.87,36.39},
{90.12,161.07},{84.88,138.05},{53.95,106.06},{87.79,154.60},
{77.27,143.05},{13.49,74.97},{13.14,47.77},{ 9.30,41.92},
{ 0.71,21.96},{26.81,66.82},{42.23,80.13},{ 6.66,27.61},
{67.69,110.99},{72.84,127.78},{86.78,144.62},{95.84,164.17},
{67.52,129.59},{48.65,112.08},{18.89,43.44},{51.07,96.06},
{88.19,173.36},{65.55,130.34},{39.75,62.84},{55.27,106.13},
{71.83,135.84},{34.28,88.20},{ 8.81,52.14},{93.18,142.03},
{47.54,73.37},{97.50,166.12},{11.10,42.77},{68.67,127.02},
{85.34,145.07},{93.61,167.18},{ 1.89,44.21},{86.51,149.85},
{15.29,40.05},{ 4.21,30.16},{14.52,46.99},{16.92,69.83},
{ 8.20,43.81},{96.34,172.12},{50.00,93.94},{88.14,147.53},
{85.91,163.13},{26.42,56.73},{97.38,154.94},{ 2.65,16.28},
{ 6.81,39.91},{21.70,75.92},{94.83,168.82},{50.81,102.41},
{12.90,40.37},{29.38,83.34},{57.93,120.19},{40.92,70.33},
{38.56,69.62},{77.29,133.60},{33.13,73.56},{99.41,177.31},
{86.41,148.28},{74.31,131.53},{61.05,103.73},{23.24,59.15},
{63.39,123.16},{70.53,115.20},{67.13,136.04},{31.30,73.20},
{95.79,164.82},{58.68,118.67},{71.03,109.72},{93.72,154.28},
{67.05,132.54},{70.35,124.09},{29.84,71.01},{20.24,59.78},
{ 0.97,41.22},{93.39,149.87},{ 6.22,36.20},{85.37,149.42},
{94.99,179.85},{ 2.49,36.99},{16.85,74.31},{63.26,109.26},
{43.93,96.97},{63.80,118.28},{65.35,128.19},{75.85,140.19},
{78.66,131.83},{31.72,85.87},{36.43,102.70},{57.29,127.00},
{29.47,67.71},{37.65,66.89},{69.97,119.91},{81.83,148.86},
{16.01,55.54},{39.07,96.46},{82.40,145.82},{ 3.48,21.48},
{24.46,49.97},{65.16,120.89},{40.30,61.66},{48.65,100.57},
{17.35,61.49},{78.57,129.88},{82.11,158.20},{78.76,150.95},
{40.42,95.94},{15.98,89.37},{58.24,114.69},{30.77,77.66},
{30.12,66.37},{23.12,59.60},{ 3.97,26.67},{70.79,152.61},
{31.55,58.79},{71.76,141.49},{65.38,125.36},{ 0.09,40.37},
{48.35,99.59},{28.35,71.36},{77.63,134.21},{80.16,155.93},
{57.03,104.57},{73.94,122.89},{69.52,126.04},{69.12,128.15},
{49.23,92.20},{29.51,75.73},{12.42,35.78},{23.99,68.83},
{87.57,150.45},{85.75,153.99},{65.77,116.91},{62.66,89.46},
{94.36,169.09},{71.34,130.37},{26.77,66.00},{84.96,152.25},
{99.36,171.00},{25.27,65.15},{40.90,83.09},{41.88,87.31},
{50.28,95.14},{34.46,72.83},{72.08,110.45},{28.18,92.23},
{55.72,96.12},{24.05,64.82},{11.10,45.74},{33.01,67.92},
{56.14,89.96},{51.34,92.68},{75.68,124.52},{86.01,138.68},
{15.52,36.84},{78.84,139.72},{50.60,99.34},{84.86,143.68},
{33.44,89.45},{95.15,159.16},{98.66,174.63},{98.89,177.31},
{ 0.22,32.76},{65.77,135.07},{62.00,120.58},{45.87,97.80},
{ 4.91,20.11},{67.67,122.38},{42.67,87.39},{97.96,167.90},
{ 7.06,30.63},{83.70,154.09},{86.63,144.36},{32.89,65.96},
{ 5.21,22.98},{ 5.98,26.51},{66.30,137.16},{39.17,77.89},
{ 2.73,28.32},{ 5.91,25.71},{32.78,68.70},{ 5.73,35.92},
{92.45,166.73},{26.56,69.02},{33.36,67.78},{ 7.42,35.05},
{31.91,73.37},{57.78,103.77},{18.36,46.33},{ 7.04,40.37},
{15.50,37.36},{92.22,143.66},{ 0.24,19.94},{72.72,125.55},
{85.87,150.62},{78.44,122.55},{18.35,46.92},{99.34,162.19},
{94.40,158.10},{99.60,183.60},{60.63,133.23},{58.63,108.60},
{81.73,135.89},{78.93,133.47},{34.54,70.76},{93.71,169.14},
{34.14,70.68},{25.99,70.68},{67.14,96.65},{79.89,137.52},
{21.90,64.34},{61.94,122.48},{11.52,36.18},{41.74,66.51},
{18.88,57.27},{35.65,81.68},{16.33,51.15},{93.05,167.55},
{54.26,83.98},{53.83,102.20},{28.78,82.46},{64.35,110.83},
{53.51,116.26},{ 2.82,32.22},{53.36,92.03},{71.24,111.89},
{87.15,163.87},{18.73,64.74},{83.52,153.50},{84.01,154.92},
{36.49,77.57},{62.86,119.17},{32.24,81.11},{56.85,123.39},
{75.97,136.19},{58.48,129.23},{44.89,80.77},{91.11,155.67},
{19.70,56.69},{44.00,88.89},{75.66,138.43},{46.95,91.04},
{44.01,88.91},{67.16,109.81},{54.44,102.18},{28.62,72.39},
{43.76,84.11},{84.32,139.89},{31.99,75.00},{20.26,73.70},
{16.35,51.26},{59.89,111.55},{11.70,49.09},{83.08,159.45},
{99.58,184.11},{15.73,37.30},{89.59,146.56},{14.12,48.10},
{27.15,42.01},{28.96,60.06},{ 7.82,31.16},{93.89,160.81},
{72.27,120.85},{87.42,151.10},{29.47,72.81},{57.93,117.23},
{ 1.70,29.60},{38.55,82.96},{81.79,157.78},{15.70,47.43},
{ 7.32,56.93},{70.99,140.63},{25.80,73.71},{45.59,93.13},
{24.08,68.93},{14.22,58.86},{90.03,165.33},{47.91,101.52},
{48.27,93.92},{86.80,142.92},{20.46,53.98},{66.31,115.18},
{99.92,184.57},{19.87,61.97},{ 9.73,42.02},{45.59,78.71},
{ 8.35,22.65},{91.29,183.42},{38.82,77.83},{14.30,36.17},
{28.80,68.88},{59.77,111.10},{83.90,149.05},{50.79,110.46},
{49.95,80.42},{85.09,143.31},{51.53,103.90},{63.44,122.52},
{72.61,149.96},{65.26,124.07},{31.63,79.17},{14.05,53.27},
{36.71,83.60},{19.73,63.11},{14.95,45.66},{54.11,100.24},
{10.18,30.76},{41.49,77.74},{24.38,72.10},{84.09,131.94},
{ 3.57,39.81},{ 2.78,27.64},{24.93,61.37},{95.99,168.54},
{42.30,92.71},{18.98,59.48},{76.28,121.80},{79.30,151.37},
{ 7.00,37.39},{80.79,135.72},{69.44,120.73},{42.77,92.25},
{32.20,88.33},{73.59,142.65},{17.59,54.86},{95.83,160.03},
{11.02,48.32},{ 9.93,42.93},{33.89,76.38},{12.13,40.50},
{75.94,147.26},{ 9.23,48.75},{ 7.60,37.19},{28.25,74.34},
{61.68,125.95},{94.42,153.15},{57.66,109.37},{80.98,147.79},
{56.09,125.36},{84.58,134.57},{10.71,50.68},{65.78,109.09},
{ 5.53,29.65},{21.76,66.76},{29.72,68.32},{30.95,65.11},
{33.28,76.75},{32.27,76.25},{66.89,125.02},{61.77,130.69},
{21.02,62.13},{32.91,82.69},{70.89,135.40},{ 8.94,16.91},
{29.94,65.56},{65.69,123.48},{14.80,33.48},{ 9.57,41.51},
{89.72,152.22},{64.24,122.87},{91.64,149.30},{46.82,102.14},
{50.99,110.36},{17.79,38.14},{ 7.90,51.68},{12.78,47.33},
{27.85,85.08},{67.02,121.10},{62.72,116.87},{61.31,121.87},
{72.12,124.47},{28.11,76.38},{63.64,123.50},{66.97,107.79},
{ 6.35,42.15},{89.92,165.27},{62.12,113.19},{17.84,45.99},
{33.67,66.11},{26.25,57.52},{44.71,110.28},{93.14,158.82},
{54.20,127.63},{46.93,95.42},{67.46,143.27},{79.18,141.36},
{54.55,110.88},{ 4.95,27.55},{31.70,64.97},{30.73,48.94},
{27.91,61.66},{75.79,140.06},{38.66,77.44},{90.18,169.84},
{42.99,97.27},{68.93,124.92},{55.59,117.87},{39.67,81.86},
{89.35,159.60},{52.51,109.72},{ 8.49,42.26},{21.53,59.50},
{51.38,83.29},{90.07,151.22},{11.97,49.68},{82.04,152.58},
{47.71,87.95},{97.42,165.81},{66.17,118.73},{28.23,67.72},
{70.68,134.71},{15.39,73.56},{43.41,85.49},{71.98,135.77},
{91.54,166.17},{78.44,131.82},{75.21,140.69},{64.99,121.77},
{55.80,120.61},{28.26,54.50},{64.89,117.80},{56.68,86.63},
{95.42,167.13},{97.62,165.29},{37.77,91.08},{33.34,84.16},
{ 4.98,32.59},{28.97,68.62},{58.70,122.63},{79.84,137.92},
{32.96,71.35},{70.15,116.32},{72.12,134.93},{87.84,145.90},
{37.58,74.91},{63.70,125.43},{51.04,96.37},{32.89,82.41},
{31.47,72.95},{65.71,123.19},{96.25,157.46},{33.41,88.58},
{73.69,124.34},{57.08,124.45},{58.55,107.26},{86.84,161.96},
{ 9.62,28.89},{70.74,132.77},{68.89,129.50},{30.79,66.63},
{84.18,156.88},{94.64,171.65},{52.65,86.94},{10.52,33.08},
{38.17,75.30},{98.23,166.00},{ 7.75,35.38},{64.33,121.67},
{20.65,58.43},{62.53,113.41},{46.49,97.40},{14.85,35.92},
{74.12,143.61},{ 1.02,15.85},{12.87,42.28},{48.12,91.79},
{61.07,112.44},{77.01,139.88},{79.93,144.04},{36.84,84.94},
{33.85,60.73},{83.60,159.64},{12.23,47.55},{45.34,103.84},
{66.93,117.43},{21.56,69.56},{54.89,108.03},{57.71,116.51},
{76.57,133.11},{41.43,98.74},{88.17,151.47},{16.57,55.41},
{ 1.30,33.67},{46.81,103.18},{ 0.19,26.49},{17.91,68.60},
{41.37,97.56},{46.12,92.01},{71.36,145.82},{ 8.14,38.29},
{39.45,73.01},{20.97,65.88},{49.34,100.46},{21.48,59.98},
{38.58,90.56},{69.89,149.19},{25.62,63.62},{59.26,126.66},
{54.69,120.65},{98.54,172.69},{72.37,131.63},{50.46,105.66},
{10.51,47.47},{86.15,125.82},{29.42,64.20},{71.03,127.79},
{21.88,63.20},{38.56,73.82},{23.67,63.21},{66.31,123.16},
{79.91,150.99},{ 1.26,19.88},{34.65,84.60},{ 2.93,36.05},
{53.99,126.60},{85.32,144.81},{45.63,107.71},{84.45,141.47},
{19.25,56.39},{ 0.52,31.56},{33.02,67.43},{ 7.00,37.20},
{82.26,143.53},{ 4.45,15.35},{22.45,75.67},{76.26,137.05},
{20.22,56.74},{35.92,74.35},{ 0.04,28.10},{83.36,150.05},
{64.10,121.94},{ 7.78,29.86},{83.17,125.35},{10.58,35.47},
{65.62,119.24},{72.56,127.30},{37.73,84.99},{93.05,153.36},
{35.86,81.75},{85.52,131.55},{81.75,143.62},{62.45,109.58},
{94.79,157.53},{77.74,134.35},{19.22,57.07},{70.78,121.14},
{99.37,161.95},{ 7.02,27.35},{82.54,124.89},{92.82,162.19},
{49.32,90.72},{95.46,153.94},{ 4.44,44.30},{52.79,112.48},
{ 0.45,27.60},{59.99,105.48},{61.27,113.11},{36.60,91.98},
{39.19,62.24},{23.68,74.57},{43.64,101.62},{48.14,109.21},
{33.56,66.36},{12.16,51.62},{84.84,133.20},{36.73,87.83},
{77.97,148.53},{25.78,61.35},{ 6.88,19.81},{84.02,150.62},
{74.04,129.53},{36.17,77.70},{10.10,55.22},{82.12,133.04},
{65.12,114.23},{26.15,61.14},{55.79,119.04},{ 5.13,26.96},
{ 9.71,39.05},{47.23,86.33},{88.17,140.47},{72.00,136.55},
{50.19,89.91},{99.03,166.27},{21.80,57.90},{15.84,62.55},
{97.93,169.82},{74.70,150.72},{62.10,117.73},{88.59,177.33},
{10.67,32.20},{86.19,139.54},{ 0.86,38.95},{43.94,85.59},
{65.26,125.30},{ 5.12,36.78},{27.90,70.23},{48.49,95.07},
{26.33,50.10},{74.26,130.64},{28.17,65.67},{85.53,154.38},
{ 8.81,33.59},{59.30,110.24},{ 8.41,45.21},{86.78,117.81},
{71.55,108.99},{73.00,128.87},{ 7.57,46.42},{ 2.67,16.23},
{89.76,160.13},{73.35,128.80},{13.22,47.10},{57.21,117.30},
{21.69,58.75},{ 1.84,10.87},{74.03,126.89},{32.43,65.31},
{18.91,36.75},{79.01,137.13},{88.99,130.99},{16.45,59.89},
{ 4.14,34.35},{36.84,83.81},{98.42,154.48},{ 1.50,52.05},
{92.91,175.37},{89.54,149.20},{65.71,118.76},{83.84,149.47},
{20.52,73.44},{70.11,128.04},{32.45,74.00},{72.44,123.91},
{93.91,149.22},{34.12,88.83},{50.65,113.43},{33.81,79.51},
{12.18,52.09},{30.27,61.00},{69.99,118.16},{56.61,112.51},
{36.00,90.54},{ 8.47,27.15},{29.54,47.31},{14.50,58.68},
{79.92,143.07},{78.10,143.79},{98.15,174.48},{30.29,72.34},
{57.69,101.31},{ 2.09,33.80},{ 5.90,46.20},{58.34,104.23},
{66.17,141.37},{55.53,110.07},{96.92,167.10},{ 1.50,33.93},
{26.19,65.67},{23.48,72.74},{90.92,160.50},{91.19,139.91},
{ 3.88,44.28},{62.88,106.53},{56.04,116.06},{10.11,30.51},
{71.35,138.82},{88.37,157.42},{73.00,147.11},{64.14,111.08},
{49.26,114.19},{49.88,112.10},{49.18,101.53},{48.13,96.06},
{33.33,76.01},{94.52,162.99},{78.18,136.67},{51.02,104.82},
{44.69,108.02},{47.99,106.22},{16.25,49.11},{16.16,50.10},
{39.00,88.35},{15.85,50.41},{46.26,100.51},{25.21,46.36},
{45.35,95.33},{39.77,92.25},{28.30,80.66},{75.07,127.22},
{74.78,129.95},{20.69,64.27},{37.14,93.13},{57.61,107.97},
{ 2.63,45.27},{81.08,152.29},{56.31,107.93},{50.35,94.40},
{55.35,101.37},{55.53,115.00},{29.57,58.12},{ 1.66,24.24},
{87.56,147.66},{62.13,117.35},{46.82,104.00},{86.97,147.44},
{41.02,89.98},{17.06,62.61},{82.41,136.36},{23.22,42.70},
{18.75,67.28},{71.33,131.04},{69.52,129.33},{82.63,147.12},
{47.24,90.92},{22.65,65.96},{73.05,139.46},{70.24,128.58},
{29.19,69.72},{40.67,72.89},{69.21,114.59},{ 4.61,26.99},
{ 8.77,53.62},{93.77,153.76},{90.60,155.79},{87.58,173.84},
{91.49,158.66},{45.29,110.83},{94.97,166.03},{53.88,102.45},
{48.87,94.11},{ 0.63,26.45},{67.53,115.30},{58.60,117.09},
{65.46,130.14},{69.45,139.73},{ 6.01,36.67},{70.72,123.43},
{39.03,97.08},{24.29,65.89},{ 7.03,35.23},{56.64,114.54},
{52.23,105.48},{66.33,125.88},{51.49,100.16},{14.78,62.37},
{23.72,54.24},{90.24,161.83},{66.28,110.00},{ 5.60,45.74},
{12.64,54.09},{ 7.18,25.05},{56.95,117.69},{69.10,117.20},
{36.09,91.50},{ 4.58,30.30},{33.13,58.84},{65.16,109.84},
{31.16,63.92},{57.47,106.93},{32.84,75.74},{26.60,71.48},
{ 9.90,43.94},{94.26,159.14},{90.71,150.67},{19.62,65.93},
{65.93,136.01},{51.32,105.70},{37.18,78.73},{50.31,88.51},
{93.10,151.38},{39.46,81.33},{21.54,75.04},{97.69,166.07},
{79.40,142.16},{14.70,39.74},{94.09,171.81},{43.79,93.80},
{62.05,110.89},{79.22,134.78},{97.36,168.21},{90.50,166.31},
{83.33,146.74},{95.86,167.96},{ 0.16,34.61},{42.31,90.83},
{92.62,151.94},{35.59,82.69},{74.19,135.22},{63.46,128.10},
{44.86,107.00},{57.32,125.09},{45.04,91.50},{84.27,165.01},
{57.91,128.78},{85.40,140.95},{48.96,93.90},{74.52,132.30},
{57.24,116.84},{58.48,102.05},{69.03,126.67},{ 4.38,39.47},
{51.33,92.33},{19.61,62.98},{59.83,112.01},{70.57,118.57},
{ 5.45,35.48},{28.72,54.61},{22.55,49.25},{69.93,124.02},
{63.43,117.73},{72.72,133.87},{77.01,140.12},{34.51,71.52},
{14.37,31.51},{ 3.24,31.74},{ 6.99,46.12},{ 0.44,-4.78},
{12.34,45.71},{71.62,135.47},{81.04,137.69},{30.62,64.26},
{23.27,63.97},{95.44,177.74},{19.31,60.92},{67.51,120.81},
{68.89,136.62},{65.18,128.79},{43.58,103.31},{76.18,152.18},
{78.16,142.12},{13.17,55.95},{83.40,139.03},{ 0.57,27.11},
{99.35,162.87},{64.00,102.77},{50.54,107.18},{56.45,117.60},
{26.03,51.83},{63.38,110.88},{73.76,137.72},{ 1.76,30.03},
{71.03,131.12},{ 0.53,33.73},{32.10,90.32},{22.91,60.97},
{61.07,116.18},{11.66,52.86},{22.94,46.74},{38.12,88.13},
{84.17,142.08},{39.19,72.19},{46.30,81.32},{58.31,100.03},
{15.84,34.20},{ 8.05,33.07},{46.34,99.75},{66.27,119.29},
{14.38,37.29},{94.29,165.90},{ 2.14,29.37},{84.18,154.89},
{24.02,58.82},{89.02,140.67},{78.31,132.86},{14.09,63.99},
{58.63,137.58},{83.66,156.76},{82.29,129.03},{ 6.96,39.48},
{ 2.73,24.93},{71.83,133.05},{75.65,136.18},{82.53,154.15},
{ 8.62,61.15},{32.22,88.34},{11.56,35.27},{44.96,97.85},
{99.65,165.85},{60.11,113.71},{ 3.62,24.97},{88.03,138.06},
{90.15,163.07},{90.64,149.29},{ 5.75,27.35},{51.11,100.58},
{20.92,43.65},{59.70,109.50},{69.38,138.45},{27.90,78.59},
{26.52,68.55},{22.67,54.08},{48.17,96.37},{ 0.19,33.79},
{40.42,80.04},{65.17,120.38},{95.98,162.88},{50.44,99.58},
{31.94,89.91},{27.18,63.57},{74.36,129.34},{ 5.46,28.48},
{35.21,81.14},{37.94,70.78},{16.22,53.52},{52.52,115.72}
};
double residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].x, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 )
{
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
__device__ double d_residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
error_sum_arr[i] = d_residual_error(d_data[i].x, d_data[i].y, *m, *c);
}
int main() {
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cudaError_t error;
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be = rms_error(bm, bc);
error = cudaMalloc(&d_dm, (sizeof(double) * 8));
if(error){
fprintf(stderr, "cudaMalloc on d_dm returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaMalloc(&d_dc, (sizeof(double) * 8));
if(error){
fprintf(stderr, "cudaMalloc on d_dc returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaMalloc(&d_error_sum_arr, (sizeof(double) * 1000));
if(error){
fprintf(stderr, "cudaMalloc on d_error_sum_arr returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaMalloc(&d_data, sizeof(data));
if(error){
fprintf(stderr, "cudaMalloc on d_data returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i] = bc + (oc[i] * step);
}
error = cudaMemcpy(d_dm, dm, (sizeof(double) * 8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_dm returned %d %s\n", error,
cudaGetErrorString(error));
}
error = cudaMemcpy(d_dc, dc, (sizeof(double) * 8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_dc returned %d %s\n", error,
cudaGetErrorString(error));
}
error = cudaMemcpy(d_data, data, sizeof(data), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_data returned %d %s\n", error,
cudaGetErrorString(error));
}
for(i=0;i<8;i++) {
double h_error_sum_arr[1000];
double error_sum_total;
double error_sum_mean;
d_rms_error <<<100,10>>>(&d_dm[i], &d_dc[i], d_error_sum_arr, d_data);
cudaDeviceSynchronize();
error = cudaMemcpy(&h_error_sum_arr, d_error_sum_arr, (sizeof(double) * 1000), cudaMemcpyDeviceToHost);
if(error){
fprintf(stderr, "cudaMemcpy to error_sum returned %d %s\n", error,
cudaGetErrorString(error));
}
for(int j=0; j<n_data; j++) {
//Add each error sum to the error sum total.
error_sum_total += h_error_sum_arr[j];
}
error_sum_mean = error_sum_total / n_data;
e[i] = sqrt(error_sum_mean);
if(e[i] < best_error) {
best_error = e[i];
best_error_i = i;
}
//Reset the error sum total.
error_sum_total = 0;
}
printf("best m,c is %lf,%lf with error %lf in direction %d\n",
dm[best_error_i], dc[best_error_i], best_error, best_error_i);
if(best_error < be) {
be = best_error;
bm = dm[best_error_i];
bc = dc[best_error_i];
} else {
minimum_found = 1;
}
}
//Free memory for d_dm
error = cudaFree(d_dm);
if(error){
fprintf(stderr, "cudaFree on d_dm returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Free memory for d_dc
error = cudaFree(d_dc);
if(error){
fprintf(stderr, "cudaFree on d_dc returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_data);
if(error){
fprintf(stderr, "cudaFree on d_data returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_error_sum_arr);
if(error){
fprintf(stderr, "cudaFree on d_error_sum_arr returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime_api.h>
#include <errno.h>
/*
To compile:
nvcc -o NishantLinear NishantLinear.cu
./NishantLinear
*/
typedef struct point_t {
double x;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000;
point_t data[] = {
{74.32,120.84},{65.26,121.98},{77.84,134.32},{69.57,135.09},
{83.26,119.06},{83.05,140.32},{65.65,115.63},{76.75,151.06},
{84.45,150.47},{69.40,138.40},{82.03,147.61},{27.33,61.48},
{25.60,51.97},{38.04,88.45},{77.76,145.24},{28.43,81.89},
{31.71,78.13},{27.36,73.40},{54.04,109.85},{43.06,91.41},
{36.52,83.97},{43.11,96.10},{ 6.18,29.10},{92.31,165.55},
{67.81,143.99},{25.45,55.32},{54.02,90.03},{28.22,64.80},
{62.75,111.23},{36.57,71.48},{94.73,155.45},{79.13,153.33},
{27.86,72.36},{20.11,65.43},{59.94,114.35},{85.52,155.16},
{85.37,140.60},{65.97,118.83},{88.21,169.64},{35.79,83.69},
{21.90,73.79},{56.63,128.76},{91.98,165.94},{ 1.36,37.69},
{81.26,139.19},{71.64,107.32},{85.98,163.26},{93.96,162.49},
{79.91,145.04},{ 6.11,39.39},{44.73,73.84},{68.92,139.47},
{77.18,141.98},{72.13,129.30},{50.28,108.96},{61.16,111.38},
{66.14,140.93},{44.08,97.81},{16.77,40.34},{16.70,50.86},
{59.13,112.08},{15.15,59.60},{93.81,143.23},{49.23,92.65},
{32.74,67.49},{68.25,126.33},{ 9.56,36.93},{31.83,75.94},
{40.71,87.30},{11.10,40.29},{58.04,126.23},{95.12,134.62},
{ 0.68,28.04},{19.12,60.55},{84.81,155.16},{38.99,88.37},
{66.88,123.61},{ 6.86,42.43},{93.37,137.53},{15.58,59.18},
{ 0.30,31.59},{88.57,143.82},{87.95,165.66},{40.17,87.81},
{13.46,58.73},{44.00,76.35},{25.69,68.91},{62.71,112.10},
{91.10,153.90},{73.52,130.98},{16.42,41.91},{ 5.87,36.39},
{90.12,161.07},{84.88,138.05},{53.95,106.06},{87.79,154.60},
{77.27,143.05},{13.49,74.97},{13.14,47.77},{ 9.30,41.92},
{ 0.71,21.96},{26.81,66.82},{42.23,80.13},{ 6.66,27.61},
{67.69,110.99},{72.84,127.78},{86.78,144.62},{95.84,164.17},
{67.52,129.59},{48.65,112.08},{18.89,43.44},{51.07,96.06},
{88.19,173.36},{65.55,130.34},{39.75,62.84},{55.27,106.13},
{71.83,135.84},{34.28,88.20},{ 8.81,52.14},{93.18,142.03},
{47.54,73.37},{97.50,166.12},{11.10,42.77},{68.67,127.02},
{85.34,145.07},{93.61,167.18},{ 1.89,44.21},{86.51,149.85},
{15.29,40.05},{ 4.21,30.16},{14.52,46.99},{16.92,69.83},
{ 8.20,43.81},{96.34,172.12},{50.00,93.94},{88.14,147.53},
{85.91,163.13},{26.42,56.73},{97.38,154.94},{ 2.65,16.28},
{ 6.81,39.91},{21.70,75.92},{94.83,168.82},{50.81,102.41},
{12.90,40.37},{29.38,83.34},{57.93,120.19},{40.92,70.33},
{38.56,69.62},{77.29,133.60},{33.13,73.56},{99.41,177.31},
{86.41,148.28},{74.31,131.53},{61.05,103.73},{23.24,59.15},
{63.39,123.16},{70.53,115.20},{67.13,136.04},{31.30,73.20},
{95.79,164.82},{58.68,118.67},{71.03,109.72},{93.72,154.28},
{67.05,132.54},{70.35,124.09},{29.84,71.01},{20.24,59.78},
{ 0.97,41.22},{93.39,149.87},{ 6.22,36.20},{85.37,149.42},
{94.99,179.85},{ 2.49,36.99},{16.85,74.31},{63.26,109.26},
{43.93,96.97},{63.80,118.28},{65.35,128.19},{75.85,140.19},
{78.66,131.83},{31.72,85.87},{36.43,102.70},{57.29,127.00},
{29.47,67.71},{37.65,66.89},{69.97,119.91},{81.83,148.86},
{16.01,55.54},{39.07,96.46},{82.40,145.82},{ 3.48,21.48},
{24.46,49.97},{65.16,120.89},{40.30,61.66},{48.65,100.57},
{17.35,61.49},{78.57,129.88},{82.11,158.20},{78.76,150.95},
{40.42,95.94},{15.98,89.37},{58.24,114.69},{30.77,77.66},
{30.12,66.37},{23.12,59.60},{ 3.97,26.67},{70.79,152.61},
{31.55,58.79},{71.76,141.49},{65.38,125.36},{ 0.09,40.37},
{48.35,99.59},{28.35,71.36},{77.63,134.21},{80.16,155.93},
{57.03,104.57},{73.94,122.89},{69.52,126.04},{69.12,128.15},
{49.23,92.20},{29.51,75.73},{12.42,35.78},{23.99,68.83},
{87.57,150.45},{85.75,153.99},{65.77,116.91},{62.66,89.46},
{94.36,169.09},{71.34,130.37},{26.77,66.00},{84.96,152.25},
{99.36,171.00},{25.27,65.15},{40.90,83.09},{41.88,87.31},
{50.28,95.14},{34.46,72.83},{72.08,110.45},{28.18,92.23},
{55.72,96.12},{24.05,64.82},{11.10,45.74},{33.01,67.92},
{56.14,89.96},{51.34,92.68},{75.68,124.52},{86.01,138.68},
{15.52,36.84},{78.84,139.72},{50.60,99.34},{84.86,143.68},
{33.44,89.45},{95.15,159.16},{98.66,174.63},{98.89,177.31},
{ 0.22,32.76},{65.77,135.07},{62.00,120.58},{45.87,97.80},
{ 4.91,20.11},{67.67,122.38},{42.67,87.39},{97.96,167.90},
{ 7.06,30.63},{83.70,154.09},{86.63,144.36},{32.89,65.96},
{ 5.21,22.98},{ 5.98,26.51},{66.30,137.16},{39.17,77.89},
{ 2.73,28.32},{ 5.91,25.71},{32.78,68.70},{ 5.73,35.92},
{92.45,166.73},{26.56,69.02},{33.36,67.78},{ 7.42,35.05},
{31.91,73.37},{57.78,103.77},{18.36,46.33},{ 7.04,40.37},
{15.50,37.36},{92.22,143.66},{ 0.24,19.94},{72.72,125.55},
{85.87,150.62},{78.44,122.55},{18.35,46.92},{99.34,162.19},
{94.40,158.10},{99.60,183.60},{60.63,133.23},{58.63,108.60},
{81.73,135.89},{78.93,133.47},{34.54,70.76},{93.71,169.14},
{34.14,70.68},{25.99,70.68},{67.14,96.65},{79.89,137.52},
{21.90,64.34},{61.94,122.48},{11.52,36.18},{41.74,66.51},
{18.88,57.27},{35.65,81.68},{16.33,51.15},{93.05,167.55},
{54.26,83.98},{53.83,102.20},{28.78,82.46},{64.35,110.83},
{53.51,116.26},{ 2.82,32.22},{53.36,92.03},{71.24,111.89},
{87.15,163.87},{18.73,64.74},{83.52,153.50},{84.01,154.92},
{36.49,77.57},{62.86,119.17},{32.24,81.11},{56.85,123.39},
{75.97,136.19},{58.48,129.23},{44.89,80.77},{91.11,155.67},
{19.70,56.69},{44.00,88.89},{75.66,138.43},{46.95,91.04},
{44.01,88.91},{67.16,109.81},{54.44,102.18},{28.62,72.39},
{43.76,84.11},{84.32,139.89},{31.99,75.00},{20.26,73.70},
{16.35,51.26},{59.89,111.55},{11.70,49.09},{83.08,159.45},
{99.58,184.11},{15.73,37.30},{89.59,146.56},{14.12,48.10},
{27.15,42.01},{28.96,60.06},{ 7.82,31.16},{93.89,160.81},
{72.27,120.85},{87.42,151.10},{29.47,72.81},{57.93,117.23},
{ 1.70,29.60},{38.55,82.96},{81.79,157.78},{15.70,47.43},
{ 7.32,56.93},{70.99,140.63},{25.80,73.71},{45.59,93.13},
{24.08,68.93},{14.22,58.86},{90.03,165.33},{47.91,101.52},
{48.27,93.92},{86.80,142.92},{20.46,53.98},{66.31,115.18},
{99.92,184.57},{19.87,61.97},{ 9.73,42.02},{45.59,78.71},
{ 8.35,22.65},{91.29,183.42},{38.82,77.83},{14.30,36.17},
{28.80,68.88},{59.77,111.10},{83.90,149.05},{50.79,110.46},
{49.95,80.42},{85.09,143.31},{51.53,103.90},{63.44,122.52},
{72.61,149.96},{65.26,124.07},{31.63,79.17},{14.05,53.27},
{36.71,83.60},{19.73,63.11},{14.95,45.66},{54.11,100.24},
{10.18,30.76},{41.49,77.74},{24.38,72.10},{84.09,131.94},
{ 3.57,39.81},{ 2.78,27.64},{24.93,61.37},{95.99,168.54},
{42.30,92.71},{18.98,59.48},{76.28,121.80},{79.30,151.37},
{ 7.00,37.39},{80.79,135.72},{69.44,120.73},{42.77,92.25},
{32.20,88.33},{73.59,142.65},{17.59,54.86},{95.83,160.03},
{11.02,48.32},{ 9.93,42.93},{33.89,76.38},{12.13,40.50},
{75.94,147.26},{ 9.23,48.75},{ 7.60,37.19},{28.25,74.34},
{61.68,125.95},{94.42,153.15},{57.66,109.37},{80.98,147.79},
{56.09,125.36},{84.58,134.57},{10.71,50.68},{65.78,109.09},
{ 5.53,29.65},{21.76,66.76},{29.72,68.32},{30.95,65.11},
{33.28,76.75},{32.27,76.25},{66.89,125.02},{61.77,130.69},
{21.02,62.13},{32.91,82.69},{70.89,135.40},{ 8.94,16.91},
{29.94,65.56},{65.69,123.48},{14.80,33.48},{ 9.57,41.51},
{89.72,152.22},{64.24,122.87},{91.64,149.30},{46.82,102.14},
{50.99,110.36},{17.79,38.14},{ 7.90,51.68},{12.78,47.33},
{27.85,85.08},{67.02,121.10},{62.72,116.87},{61.31,121.87},
{72.12,124.47},{28.11,76.38},{63.64,123.50},{66.97,107.79},
{ 6.35,42.15},{89.92,165.27},{62.12,113.19},{17.84,45.99},
{33.67,66.11},{26.25,57.52},{44.71,110.28},{93.14,158.82},
{54.20,127.63},{46.93,95.42},{67.46,143.27},{79.18,141.36},
{54.55,110.88},{ 4.95,27.55},{31.70,64.97},{30.73,48.94},
{27.91,61.66},{75.79,140.06},{38.66,77.44},{90.18,169.84},
{42.99,97.27},{68.93,124.92},{55.59,117.87},{39.67,81.86},
{89.35,159.60},{52.51,109.72},{ 8.49,42.26},{21.53,59.50},
{51.38,83.29},{90.07,151.22},{11.97,49.68},{82.04,152.58},
{47.71,87.95},{97.42,165.81},{66.17,118.73},{28.23,67.72},
{70.68,134.71},{15.39,73.56},{43.41,85.49},{71.98,135.77},
{91.54,166.17},{78.44,131.82},{75.21,140.69},{64.99,121.77},
{55.80,120.61},{28.26,54.50},{64.89,117.80},{56.68,86.63},
{95.42,167.13},{97.62,165.29},{37.77,91.08},{33.34,84.16},
{ 4.98,32.59},{28.97,68.62},{58.70,122.63},{79.84,137.92},
{32.96,71.35},{70.15,116.32},{72.12,134.93},{87.84,145.90},
{37.58,74.91},{63.70,125.43},{51.04,96.37},{32.89,82.41},
{31.47,72.95},{65.71,123.19},{96.25,157.46},{33.41,88.58},
{73.69,124.34},{57.08,124.45},{58.55,107.26},{86.84,161.96},
{ 9.62,28.89},{70.74,132.77},{68.89,129.50},{30.79,66.63},
{84.18,156.88},{94.64,171.65},{52.65,86.94},{10.52,33.08},
{38.17,75.30},{98.23,166.00},{ 7.75,35.38},{64.33,121.67},
{20.65,58.43},{62.53,113.41},{46.49,97.40},{14.85,35.92},
{74.12,143.61},{ 1.02,15.85},{12.87,42.28},{48.12,91.79},
{61.07,112.44},{77.01,139.88},{79.93,144.04},{36.84,84.94},
{33.85,60.73},{83.60,159.64},{12.23,47.55},{45.34,103.84},
{66.93,117.43},{21.56,69.56},{54.89,108.03},{57.71,116.51},
{76.57,133.11},{41.43,98.74},{88.17,151.47},{16.57,55.41},
{ 1.30,33.67},{46.81,103.18},{ 0.19,26.49},{17.91,68.60},
{41.37,97.56},{46.12,92.01},{71.36,145.82},{ 8.14,38.29},
{39.45,73.01},{20.97,65.88},{49.34,100.46},{21.48,59.98},
{38.58,90.56},{69.89,149.19},{25.62,63.62},{59.26,126.66},
{54.69,120.65},{98.54,172.69},{72.37,131.63},{50.46,105.66},
{10.51,47.47},{86.15,125.82},{29.42,64.20},{71.03,127.79},
{21.88,63.20},{38.56,73.82},{23.67,63.21},{66.31,123.16},
{79.91,150.99},{ 1.26,19.88},{34.65,84.60},{ 2.93,36.05},
{53.99,126.60},{85.32,144.81},{45.63,107.71},{84.45,141.47},
{19.25,56.39},{ 0.52,31.56},{33.02,67.43},{ 7.00,37.20},
{82.26,143.53},{ 4.45,15.35},{22.45,75.67},{76.26,137.05},
{20.22,56.74},{35.92,74.35},{ 0.04,28.10},{83.36,150.05},
{64.10,121.94},{ 7.78,29.86},{83.17,125.35},{10.58,35.47},
{65.62,119.24},{72.56,127.30},{37.73,84.99},{93.05,153.36},
{35.86,81.75},{85.52,131.55},{81.75,143.62},{62.45,109.58},
{94.79,157.53},{77.74,134.35},{19.22,57.07},{70.78,121.14},
{99.37,161.95},{ 7.02,27.35},{82.54,124.89},{92.82,162.19},
{49.32,90.72},{95.46,153.94},{ 4.44,44.30},{52.79,112.48},
{ 0.45,27.60},{59.99,105.48},{61.27,113.11},{36.60,91.98},
{39.19,62.24},{23.68,74.57},{43.64,101.62},{48.14,109.21},
{33.56,66.36},{12.16,51.62},{84.84,133.20},{36.73,87.83},
{77.97,148.53},{25.78,61.35},{ 6.88,19.81},{84.02,150.62},
{74.04,129.53},{36.17,77.70},{10.10,55.22},{82.12,133.04},
{65.12,114.23},{26.15,61.14},{55.79,119.04},{ 5.13,26.96},
{ 9.71,39.05},{47.23,86.33},{88.17,140.47},{72.00,136.55},
{50.19,89.91},{99.03,166.27},{21.80,57.90},{15.84,62.55},
{97.93,169.82},{74.70,150.72},{62.10,117.73},{88.59,177.33},
{10.67,32.20},{86.19,139.54},{ 0.86,38.95},{43.94,85.59},
{65.26,125.30},{ 5.12,36.78},{27.90,70.23},{48.49,95.07},
{26.33,50.10},{74.26,130.64},{28.17,65.67},{85.53,154.38},
{ 8.81,33.59},{59.30,110.24},{ 8.41,45.21},{86.78,117.81},
{71.55,108.99},{73.00,128.87},{ 7.57,46.42},{ 2.67,16.23},
{89.76,160.13},{73.35,128.80},{13.22,47.10},{57.21,117.30},
{21.69,58.75},{ 1.84,10.87},{74.03,126.89},{32.43,65.31},
{18.91,36.75},{79.01,137.13},{88.99,130.99},{16.45,59.89},
{ 4.14,34.35},{36.84,83.81},{98.42,154.48},{ 1.50,52.05},
{92.91,175.37},{89.54,149.20},{65.71,118.76},{83.84,149.47},
{20.52,73.44},{70.11,128.04},{32.45,74.00},{72.44,123.91},
{93.91,149.22},{34.12,88.83},{50.65,113.43},{33.81,79.51},
{12.18,52.09},{30.27,61.00},{69.99,118.16},{56.61,112.51},
{36.00,90.54},{ 8.47,27.15},{29.54,47.31},{14.50,58.68},
{79.92,143.07},{78.10,143.79},{98.15,174.48},{30.29,72.34},
{57.69,101.31},{ 2.09,33.80},{ 5.90,46.20},{58.34,104.23},
{66.17,141.37},{55.53,110.07},{96.92,167.10},{ 1.50,33.93},
{26.19,65.67},{23.48,72.74},{90.92,160.50},{91.19,139.91},
{ 3.88,44.28},{62.88,106.53},{56.04,116.06},{10.11,30.51},
{71.35,138.82},{88.37,157.42},{73.00,147.11},{64.14,111.08},
{49.26,114.19},{49.88,112.10},{49.18,101.53},{48.13,96.06},
{33.33,76.01},{94.52,162.99},{78.18,136.67},{51.02,104.82},
{44.69,108.02},{47.99,106.22},{16.25,49.11},{16.16,50.10},
{39.00,88.35},{15.85,50.41},{46.26,100.51},{25.21,46.36},
{45.35,95.33},{39.77,92.25},{28.30,80.66},{75.07,127.22},
{74.78,129.95},{20.69,64.27},{37.14,93.13},{57.61,107.97},
{ 2.63,45.27},{81.08,152.29},{56.31,107.93},{50.35,94.40},
{55.35,101.37},{55.53,115.00},{29.57,58.12},{ 1.66,24.24},
{87.56,147.66},{62.13,117.35},{46.82,104.00},{86.97,147.44},
{41.02,89.98},{17.06,62.61},{82.41,136.36},{23.22,42.70},
{18.75,67.28},{71.33,131.04},{69.52,129.33},{82.63,147.12},
{47.24,90.92},{22.65,65.96},{73.05,139.46},{70.24,128.58},
{29.19,69.72},{40.67,72.89},{69.21,114.59},{ 4.61,26.99},
{ 8.77,53.62},{93.77,153.76},{90.60,155.79},{87.58,173.84},
{91.49,158.66},{45.29,110.83},{94.97,166.03},{53.88,102.45},
{48.87,94.11},{ 0.63,26.45},{67.53,115.30},{58.60,117.09},
{65.46,130.14},{69.45,139.73},{ 6.01,36.67},{70.72,123.43},
{39.03,97.08},{24.29,65.89},{ 7.03,35.23},{56.64,114.54},
{52.23,105.48},{66.33,125.88},{51.49,100.16},{14.78,62.37},
{23.72,54.24},{90.24,161.83},{66.28,110.00},{ 5.60,45.74},
{12.64,54.09},{ 7.18,25.05},{56.95,117.69},{69.10,117.20},
{36.09,91.50},{ 4.58,30.30},{33.13,58.84},{65.16,109.84},
{31.16,63.92},{57.47,106.93},{32.84,75.74},{26.60,71.48},
{ 9.90,43.94},{94.26,159.14},{90.71,150.67},{19.62,65.93},
{65.93,136.01},{51.32,105.70},{37.18,78.73},{50.31,88.51},
{93.10,151.38},{39.46,81.33},{21.54,75.04},{97.69,166.07},
{79.40,142.16},{14.70,39.74},{94.09,171.81},{43.79,93.80},
{62.05,110.89},{79.22,134.78},{97.36,168.21},{90.50,166.31},
{83.33,146.74},{95.86,167.96},{ 0.16,34.61},{42.31,90.83},
{92.62,151.94},{35.59,82.69},{74.19,135.22},{63.46,128.10},
{44.86,107.00},{57.32,125.09},{45.04,91.50},{84.27,165.01},
{57.91,128.78},{85.40,140.95},{48.96,93.90},{74.52,132.30},
{57.24,116.84},{58.48,102.05},{69.03,126.67},{ 4.38,39.47},
{51.33,92.33},{19.61,62.98},{59.83,112.01},{70.57,118.57},
{ 5.45,35.48},{28.72,54.61},{22.55,49.25},{69.93,124.02},
{63.43,117.73},{72.72,133.87},{77.01,140.12},{34.51,71.52},
{14.37,31.51},{ 3.24,31.74},{ 6.99,46.12},{ 0.44,-4.78},
{12.34,45.71},{71.62,135.47},{81.04,137.69},{30.62,64.26},
{23.27,63.97},{95.44,177.74},{19.31,60.92},{67.51,120.81},
{68.89,136.62},{65.18,128.79},{43.58,103.31},{76.18,152.18},
{78.16,142.12},{13.17,55.95},{83.40,139.03},{ 0.57,27.11},
{99.35,162.87},{64.00,102.77},{50.54,107.18},{56.45,117.60},
{26.03,51.83},{63.38,110.88},{73.76,137.72},{ 1.76,30.03},
{71.03,131.12},{ 0.53,33.73},{32.10,90.32},{22.91,60.97},
{61.07,116.18},{11.66,52.86},{22.94,46.74},{38.12,88.13},
{84.17,142.08},{39.19,72.19},{46.30,81.32},{58.31,100.03},
{15.84,34.20},{ 8.05,33.07},{46.34,99.75},{66.27,119.29},
{14.38,37.29},{94.29,165.90},{ 2.14,29.37},{84.18,154.89},
{24.02,58.82},{89.02,140.67},{78.31,132.86},{14.09,63.99},
{58.63,137.58},{83.66,156.76},{82.29,129.03},{ 6.96,39.48},
{ 2.73,24.93},{71.83,133.05},{75.65,136.18},{82.53,154.15},
{ 8.62,61.15},{32.22,88.34},{11.56,35.27},{44.96,97.85},
{99.65,165.85},{60.11,113.71},{ 3.62,24.97},{88.03,138.06},
{90.15,163.07},{90.64,149.29},{ 5.75,27.35},{51.11,100.58},
{20.92,43.65},{59.70,109.50},{69.38,138.45},{27.90,78.59},
{26.52,68.55},{22.67,54.08},{48.17,96.37},{ 0.19,33.79},
{40.42,80.04},{65.17,120.38},{95.98,162.88},{50.44,99.58},
{31.94,89.91},{27.18,63.57},{74.36,129.34},{ 5.46,28.48},
{35.21,81.14},{37.94,70.78},{16.22,53.52},{52.52,115.72}
};
double residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].x, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
int time_difference(struct timespec *start, struct timespec *finish, long long int *difference)
{
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 )
{
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
__device__ double d_residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
error_sum_arr[i] = d_residual_error(d_data[i].x, d_data[i].y, *m, *c);
}
int main() {
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
hipError_t error;
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be = rms_error(bm, bc);
error = hipMalloc(&d_dm, (sizeof(double) * 8));
if(error){
fprintf(stderr, "hipMalloc on d_dm returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipMalloc(&d_dc, (sizeof(double) * 8));
if(error){
fprintf(stderr, "hipMalloc on d_dc returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipMalloc(&d_error_sum_arr, (sizeof(double) * 1000));
if(error){
fprintf(stderr, "hipMalloc on d_error_sum_arr returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipMalloc(&d_data, sizeof(data));
if(error){
fprintf(stderr, "hipMalloc on d_data returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i] = bc + (oc[i] * step);
}
error = hipMemcpy(d_dm, dm, (sizeof(double) * 8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_dm returned %d %s\n", error,
hipGetErrorString(error));
}
error = hipMemcpy(d_dc, dc, (sizeof(double) * 8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_dc returned %d %s\n", error,
hipGetErrorString(error));
}
error = hipMemcpy(d_data, data, sizeof(data), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_data returned %d %s\n", error,
hipGetErrorString(error));
}
for(i=0;i<8;i++) {
double h_error_sum_arr[1000];
double error_sum_total;
double error_sum_mean;
d_rms_error <<<100,10>>>(&d_dm[i], &d_dc[i], d_error_sum_arr, d_data);
hipDeviceSynchronize();
error = hipMemcpy(&h_error_sum_arr, d_error_sum_arr, (sizeof(double) * 1000), hipMemcpyDeviceToHost);
if(error){
fprintf(stderr, "hipMemcpy to error_sum returned %d %s\n", error,
hipGetErrorString(error));
}
for(int j=0; j<n_data; j++) {
//Add each error sum to the error sum total.
error_sum_total += h_error_sum_arr[j];
}
error_sum_mean = error_sum_total / n_data;
e[i] = sqrt(error_sum_mean);
if(e[i] < best_error) {
best_error = e[i];
best_error_i = i;
}
//Reset the error sum total.
error_sum_total = 0;
}
printf("best m,c is %lf,%lf with error %lf in direction %d\n",
dm[best_error_i], dc[best_error_i], best_error, best_error_i);
if(best_error < be) {
be = best_error;
bm = dm[best_error_i];
bc = dc[best_error_i];
} else {
minimum_found = 1;
}
}
//Free memory for d_dm
error = hipFree(d_dm);
if(error){
fprintf(stderr, "hipFree on d_dm returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Free memory for d_dc
error = hipFree(d_dc);
if(error){
fprintf(stderr, "hipFree on d_dc returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_data);
if(error){
fprintf(stderr, "hipFree on d_data returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_error_sum_arr);
if(error){
fprintf(stderr, "hipFree on d_error_sum_arr returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void func (char* stringInput, int stringSize, int* integerInput, char* dummySpace) {
int counter = 0;
for (int i=0;i<stringSize;i++)
dummySpace[counter++] = stringInput[i];
for (int i=0;i<sizeof(int);i++)
dummySpace[counter++] = ((char*)integerInput)[i];
} | code for sm_80
Function : _Z4funcPciPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 BRA 0x8d0 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*00a0*/ @!P0 BRA 0x760 ; /* 0x000006b000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe20007ffe1ff */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fd000078e00ff */
/*0120*/ @!P0 BRA 0x620 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x430 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1100 */
/*0180*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c10110c */
/*0190*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*01a0*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0043e8000c10110c */
/*01b0*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea8000c1e1100 */
/*01c0*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x0045e8000c10110c */
/*01d0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x000ee8000c1e1100 */
/*01e0*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x0087e8000c10110c */
/*01f0*/ LDG.E.U8 R15, [R2.64+0x4] ; /* 0x0000040c020f7981 */
/* 0x000f28000c1e1100 */
/*0200*/ STG.E.U8 [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0109e8000c10110c */
/*0210*/ LDG.E.U8 R17, [R2.64+0x5] ; /* 0x0000050c02117981 */
/* 0x000f68000c1e1100 */
/*0220*/ STG.E.U8 [R4.64+0x5], R17 ; /* 0x0000051104007986 */
/* 0x020be8000c10110c */
/*0230*/ LDG.E.U8 R7, [R2.64+0x6] ; /* 0x0000060c02077981 */
/* 0x001ea8000c1e1100 */
/*0240*/ STG.E.U8 [R4.64+0x6], R7 ; /* 0x0000060704007986 */
/* 0x0041e8000c10110c */
/*0250*/ LDG.E.U8 R9, [R2.64+0x7] ; /* 0x0000070c02097981 */
/* 0x002ea8000c1e1100 */
/*0260*/ STG.E.U8 [R4.64+0x7], R9 ; /* 0x0000070904007986 */
/* 0x0043e8000c10110c */
/*0270*/ LDG.E.U8 R11, [R2.64+0x8] ; /* 0x0000080c020b7981 */
/* 0x000ea8000c1e1100 */
/*0280*/ STG.E.U8 [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0045e8000c10110c */
/*0290*/ LDG.E.U8 R13, [R2.64+0x9] ; /* 0x0000090c020d7981 */
/* 0x008ee8000c1e1100 */
/*02a0*/ STG.E.U8 [R4.64+0x9], R13 ; /* 0x0000090d04007986 */
/* 0x0087e8000c10110c */
/*02b0*/ LDG.E.U8 R15, [R2.64+0xa] ; /* 0x00000a0c020f7981 */
/* 0x010f28000c1e1100 */
/*02c0*/ STG.E.U8 [R4.64+0xa], R15 ; /* 0x00000a0f04007986 */
/* 0x010fe8000c10110c */
/*02d0*/ LDG.E.U8 R17, [R2.64+0xb] ; /* 0x00000b0c02117981 */
/* 0x020f28000c1e1100 */
/*02e0*/ STG.E.U8 [R4.64+0xb], R17 ; /* 0x00000b1104007986 */
/* 0x010fe8000c10110c */
/*02f0*/ LDG.E.U8 R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x001f28000c1e1100 */
/*0300*/ STG.E.U8 [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x0101e8000c10110c */
/*0310*/ LDG.E.U8 R9, [R2.64+0xd] ; /* 0x00000d0c02097981 */
/* 0x002f28000c1e1100 */
/*0320*/ STG.E.U8 [R4.64+0xd], R9 ; /* 0x00000d0904007986 */
/* 0x0103e8000c10110c */
/*0330*/ LDG.E.U8 R11, [R2.64+0xe] ; /* 0x00000e0c020b7981 */
/* 0x004ea2000c1e1100 */
/*0340*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0360*/ STG.E.U8 [R4.64+0xe], R11 ; /* 0x00000e0b04007986 */
/* 0x004fe8000c10110c */
/*0370*/ LDG.E.U8 R13, [R2.64+0xf] ; /* 0x00000f0c020d7981 */
/* 0x0084e2000c1e1100 */
/*0380*/ IADD3 R8, P3, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fe20007f7e0ff */
/*0390*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*03a0*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc60007f5e0ff */
/*03b0*/ IMAD.X R7, RZ, RZ, R3, P3 ; /* 0x000000ffff077224 */
/* 0x001fe400018e0603 */
/*03c0*/ IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff097224 */
/* 0x002fe200010e0605 */
/*03d0*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x004fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*03f0*/ STG.E.U8 [R4.64+0xf], R13 ; /* 0x00000f0d04007986 */
/* 0x0081e4000c10110c */
/*0400*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000a */
/*0410*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0420*/ @P1 BRA 0x170 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*0430*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x600 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1100 */
/*0460*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c10110c */
/*0470*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*0480*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0043e8000c10110c */
/*0490*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea8000c1e1100 */
/*04a0*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x0045e8000c10110c */
/*04b0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x000ee8000c1e1100 */
/*04c0*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x0087e8000c10110c */
/*04d0*/ LDG.E.U8 R15, [R2.64+0x4] ; /* 0x0000040c020f7981 */
/* 0x000f28000c1e1100 */
/*04e0*/ STG.E.U8 [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x010fe8000c10110c */
/*04f0*/ LDG.E.U8 R17, [R2.64+0x5] ; /* 0x0000050c02117981 */
/* 0x000f28000c1e1100 */
/*0500*/ STG.E.U8 [R4.64+0x5], R17 ; /* 0x0000051104007986 */
/* 0x010fe8000c10110c */
/*0510*/ LDG.E.U8 R7, [R2.64+0x6] ; /* 0x0000060c02077981 */
/* 0x001f22000c1e1100 */
/*0520*/ IADD3 R8, P2, R2, 0x8, RZ ; /* 0x0000000802087810 */
/* 0x000fc40007f5e0ff */
/*0530*/ IADD3 R10, P1, R4, 0x8, RZ ; /* 0x00000008040a7810 */
/* 0x000fe20007f3e0ff */
/*0540*/ STG.E.U8 [R4.64+0x6], R7 ; /* 0x0000060704007986 */
/* 0x010fe8000c10110c */
/*0550*/ LDG.E.U8 R9, [R2.64+0x7] ; /* 0x0000070c02097981 */
/* 0x002122000c1e1100 */
/*0560*/ IMAD.X R11, RZ, RZ, R3, P2 ; /* 0x000000ffff0b7224 */
/* 0x004fe200010e0603 */
/*0570*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0580*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x008fe200008e0605 */
/*0590*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0008 */
/*05c0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*05d0*/ STG.E.U8 [R4.64+0x7], R9 ; /* 0x0000070904007986 */
/* 0x0101e4000c10110c */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fc400078e000a */
/*05f0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0600*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0610*/ @!P0 BRA 0x760 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1100 */
/*0630*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c10110c */
/*0640*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*0650*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0043e8000c10110c */
/*0660*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea2000c1e1100 */
/*0670*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0680*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0690*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x004fe8000c10110c */
/*06a0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x0004e2000c1e1100 */
/*06b0*/ IADD3 R8, P2, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fe20007f5e0ff */
/*06c0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*06d0*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fc60007f3e0ff */
/*06e0*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0603 */
/*06f0*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x002fe400008e0605 */
/*0700*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x004fe200078e0008 */
/*0710*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe20000000f00 */
/*0720*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x0081e4000c10110c */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000a */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0750*/ @P0 BRA 0x620 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0760*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0770*/ @!P0 BRA 0x8d0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0780*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0790*/ ULDC.64 UR10, c[0x0][0x178] ; /* 0x00005e00000a7ab9 */
/* 0x000fe40000000a00 */
/*07a0*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*07b0*/ UIADD3 UR7, UP0, UR4, UR8, URZ ; /* 0x0000000804077290 */
/* 0x000fe4000ff1e03f */
/*07c0*/ UIADD3 UR6, UP1, UR4, UR10, URZ ; /* 0x0000000a04067290 */
/* 0x000fe4000ff3e03f */
/*07d0*/ UIADD3.X UR8, UR5, UR9, URZ, UP0, !UPT ; /* 0x0000000905087290 */
/* 0x000fc400087fe43f */
/*07e0*/ UIADD3.X UR5, UR5, UR11, URZ, UP1, !UPT ; /* 0x0000000b05057290 */
/* 0x000fc80008ffe43f */
/*07f0*/ IMAD.U32 R3, RZ, RZ, UR8 ; /* 0x00000008ff037e24 */
/* 0x001fe4000f8e00ff */
/*0800*/ IMAD.U32 R2, RZ, RZ, UR7 ; /* 0x00000007ff027e24 */
/* 0x000fca000f8e00ff */
/*0810*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000c02037981 */
/* 0x000ea2000c1e1100 */
/*0820*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0840*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0850*/ UIADD3 UR7, UP0, UR7, 0x1, URZ ; /* 0x0000000107077890 */
/* 0x000fe2000ff1e03f */
/*0860*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0870*/ UIADD3 UR6, UP1, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe4000ff3e03f */
/*0880*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0890*/ UIADD3.X UR8, URZ, UR8, URZ, UP0, !UPT ; /* 0x000000083f087290 */
/* 0x000fc400087fe43f */
/*08a0*/ UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; /* 0x000000053f057290 */
/* 0x000fe20008ffe43f */
/*08b0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041ea000c10110c */
/*08c0*/ @P0 BRA 0x7f0 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*08e0*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe20000000a00 */
/*08f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x001fca00078e00ff */
/*0900*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea2000c1e1100 */
/*0910*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000ff1e03f */
/*0920*/ ULEA.HI.X.SX32 UR4, UR4, UR7, 0x1, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f0e3f */
/*0930*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x000fc8000f8e00ff */
/*0940*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fca000f8e00ff */
/*0950*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c10110c */
/*0960*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*0970*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x004fe8000c10110c */
/*0980*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea8000c1e1100 */
/*0990*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x004fe8000c10110c */
/*09a0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x000ea8000c1e1100 */
/*09b0*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x004fe2000c10110c */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void func (char* stringInput, int stringSize, int* integerInput, char* dummySpace) {
int counter = 0;
for (int i=0;i<stringSize;i++)
dummySpace[counter++] = stringInput[i];
for (int i=0;i<sizeof(int);i++)
dummySpace[counter++] = ((char*)integerInput)[i];
} | .file "tmpxft_000cf127_00000000-6_func.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4funcPciPiS_PciPiS_
.type _Z28__device_stub__Z4funcPciPiS_PciPiS_, @function
_Z28__device_stub__Z4funcPciPiS_PciPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4funcPciPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4funcPciPiS_PciPiS_, .-_Z28__device_stub__Z4funcPciPiS_PciPiS_
.globl _Z4funcPciPiS_
.type _Z4funcPciPiS_, @function
_Z4funcPciPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4funcPciPiS_PciPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4funcPciPiS_, .-_Z4funcPciPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcPciPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPciPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void func (char* stringInput, int stringSize, int* integerInput, char* dummySpace) {
int counter = 0;
for (int i=0;i<stringSize;i++)
dummySpace[counter++] = stringInput[i];
for (int i=0;i<sizeof(int);i++)
dummySpace[counter++] = ((char*)integerInput)[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void func (char* stringInput, int stringSize, int* integerInput, char* dummySpace) {
int counter = 0;
for (int i=0;i<stringSize;i++)
dummySpace[counter++] = stringInput[i];
for (int i=0;i<sizeof(int);i++)
dummySpace[counter++] = ((char*)integerInput)[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void func (char* stringInput, int stringSize, int* integerInput, char* dummySpace) {
int counter = 0;
for (int i=0;i<stringSize;i++)
dummySpace[counter++] = stringInput[i];
for (int i=0;i<sizeof(int);i++)
dummySpace[counter++] = ((char*)integerInput)[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPciPiS_
.globl _Z4funcPciPiS_
.p2align 8
.type _Z4funcPciPiS_,@function
_Z4funcPciPiS_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s9, s8
s_mov_b64 s[6:7], s[2:3]
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
global_store_b8 v0, v1, s[6:7]
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_add_i32 s9, s9, -1
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s9, 0
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
s_mov_b32 s8, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_add_u32 s4, s2, s8
s_addc_u32 s5, s3, 0
s_mov_b64 s[2:3], 0
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s2
s_addc_u32 s7, s1, s3
global_load_u8 v1, v0, s[6:7]
s_add_u32 s6, s4, s2
s_addc_u32 s7, s5, s3
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
s_waitcnt vmcnt(0)
global_store_b8 v0, v1, s[6:7]
s_cbranch_scc0 .LBB0_5
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPciPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPciPiS_, .Lfunc_end0-_Z4funcPciPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPciPiS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z4funcPciPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void func (char* stringInput, int stringSize, int* integerInput, char* dummySpace) {
int counter = 0;
for (int i=0;i<stringSize;i++)
dummySpace[counter++] = stringInput[i];
for (int i=0;i<sizeof(int);i++)
dummySpace[counter++] = ((char*)integerInput)[i];
} | .text
.file "func.hip"
.globl _Z19__device_stub__funcPciPiS_ # -- Begin function _Z19__device_stub__funcPciPiS_
.p2align 4, 0x90
.type _Z19__device_stub__funcPciPiS_,@function
_Z19__device_stub__funcPciPiS_: # @_Z19__device_stub__funcPciPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4funcPciPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPciPiS_, .Lfunc_end0-_Z19__device_stub__funcPciPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPciPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPciPiS_,@object # @_Z4funcPciPiS_
.section .rodata,"a",@progbits
.globl _Z4funcPciPiS_
.p2align 3, 0x0
_Z4funcPciPiS_:
.quad _Z19__device_stub__funcPciPiS_
.size _Z4funcPciPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcPciPiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPciPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPciPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4funcPciPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 BRA 0x8d0 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*00a0*/ @!P0 BRA 0x760 ; /* 0x000006b000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe20007ffe1ff */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fd000078e00ff */
/*0120*/ @!P0 BRA 0x620 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x430 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1100 */
/*0180*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c10110c */
/*0190*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*01a0*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0043e8000c10110c */
/*01b0*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea8000c1e1100 */
/*01c0*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x0045e8000c10110c */
/*01d0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x000ee8000c1e1100 */
/*01e0*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x0087e8000c10110c */
/*01f0*/ LDG.E.U8 R15, [R2.64+0x4] ; /* 0x0000040c020f7981 */
/* 0x000f28000c1e1100 */
/*0200*/ STG.E.U8 [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0109e8000c10110c */
/*0210*/ LDG.E.U8 R17, [R2.64+0x5] ; /* 0x0000050c02117981 */
/* 0x000f68000c1e1100 */
/*0220*/ STG.E.U8 [R4.64+0x5], R17 ; /* 0x0000051104007986 */
/* 0x020be8000c10110c */
/*0230*/ LDG.E.U8 R7, [R2.64+0x6] ; /* 0x0000060c02077981 */
/* 0x001ea8000c1e1100 */
/*0240*/ STG.E.U8 [R4.64+0x6], R7 ; /* 0x0000060704007986 */
/* 0x0041e8000c10110c */
/*0250*/ LDG.E.U8 R9, [R2.64+0x7] ; /* 0x0000070c02097981 */
/* 0x002ea8000c1e1100 */
/*0260*/ STG.E.U8 [R4.64+0x7], R9 ; /* 0x0000070904007986 */
/* 0x0043e8000c10110c */
/*0270*/ LDG.E.U8 R11, [R2.64+0x8] ; /* 0x0000080c020b7981 */
/* 0x000ea8000c1e1100 */
/*0280*/ STG.E.U8 [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0045e8000c10110c */
/*0290*/ LDG.E.U8 R13, [R2.64+0x9] ; /* 0x0000090c020d7981 */
/* 0x008ee8000c1e1100 */
/*02a0*/ STG.E.U8 [R4.64+0x9], R13 ; /* 0x0000090d04007986 */
/* 0x0087e8000c10110c */
/*02b0*/ LDG.E.U8 R15, [R2.64+0xa] ; /* 0x00000a0c020f7981 */
/* 0x010f28000c1e1100 */
/*02c0*/ STG.E.U8 [R4.64+0xa], R15 ; /* 0x00000a0f04007986 */
/* 0x010fe8000c10110c */
/*02d0*/ LDG.E.U8 R17, [R2.64+0xb] ; /* 0x00000b0c02117981 */
/* 0x020f28000c1e1100 */
/*02e0*/ STG.E.U8 [R4.64+0xb], R17 ; /* 0x00000b1104007986 */
/* 0x010fe8000c10110c */
/*02f0*/ LDG.E.U8 R7, [R2.64+0xc] ; /* 0x00000c0c02077981 */
/* 0x001f28000c1e1100 */
/*0300*/ STG.E.U8 [R4.64+0xc], R7 ; /* 0x00000c0704007986 */
/* 0x0101e8000c10110c */
/*0310*/ LDG.E.U8 R9, [R2.64+0xd] ; /* 0x00000d0c02097981 */
/* 0x002f28000c1e1100 */
/*0320*/ STG.E.U8 [R4.64+0xd], R9 ; /* 0x00000d0904007986 */
/* 0x0103e8000c10110c */
/*0330*/ LDG.E.U8 R11, [R2.64+0xe] ; /* 0x00000e0c020b7981 */
/* 0x004ea2000c1e1100 */
/*0340*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0360*/ STG.E.U8 [R4.64+0xe], R11 ; /* 0x00000e0b04007986 */
/* 0x004fe8000c10110c */
/*0370*/ LDG.E.U8 R13, [R2.64+0xf] ; /* 0x00000f0c020d7981 */
/* 0x0084e2000c1e1100 */
/*0380*/ IADD3 R8, P3, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fe20007f7e0ff */
/*0390*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*03a0*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc60007f5e0ff */
/*03b0*/ IMAD.X R7, RZ, RZ, R3, P3 ; /* 0x000000ffff077224 */
/* 0x001fe400018e0603 */
/*03c0*/ IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff097224 */
/* 0x002fe200010e0605 */
/*03d0*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x004fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*03f0*/ STG.E.U8 [R4.64+0xf], R13 ; /* 0x00000f0d04007986 */
/* 0x0081e4000c10110c */
/*0400*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000a */
/*0410*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0420*/ @P1 BRA 0x170 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*0430*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x600 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1100 */
/*0460*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c10110c */
/*0470*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*0480*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0043e8000c10110c */
/*0490*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea8000c1e1100 */
/*04a0*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x0045e8000c10110c */
/*04b0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x000ee8000c1e1100 */
/*04c0*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x0087e8000c10110c */
/*04d0*/ LDG.E.U8 R15, [R2.64+0x4] ; /* 0x0000040c020f7981 */
/* 0x000f28000c1e1100 */
/*04e0*/ STG.E.U8 [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x010fe8000c10110c */
/*04f0*/ LDG.E.U8 R17, [R2.64+0x5] ; /* 0x0000050c02117981 */
/* 0x000f28000c1e1100 */
/*0500*/ STG.E.U8 [R4.64+0x5], R17 ; /* 0x0000051104007986 */
/* 0x010fe8000c10110c */
/*0510*/ LDG.E.U8 R7, [R2.64+0x6] ; /* 0x0000060c02077981 */
/* 0x001f22000c1e1100 */
/*0520*/ IADD3 R8, P2, R2, 0x8, RZ ; /* 0x0000000802087810 */
/* 0x000fc40007f5e0ff */
/*0530*/ IADD3 R10, P1, R4, 0x8, RZ ; /* 0x00000008040a7810 */
/* 0x000fe20007f3e0ff */
/*0540*/ STG.E.U8 [R4.64+0x6], R7 ; /* 0x0000060704007986 */
/* 0x010fe8000c10110c */
/*0550*/ LDG.E.U8 R9, [R2.64+0x7] ; /* 0x0000070c02097981 */
/* 0x002122000c1e1100 */
/*0560*/ IMAD.X R11, RZ, RZ, R3, P2 ; /* 0x000000ffff0b7224 */
/* 0x004fe200010e0603 */
/*0570*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0580*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x008fe200008e0605 */
/*0590*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0008 */
/*05c0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*05d0*/ STG.E.U8 [R4.64+0x7], R9 ; /* 0x0000070904007986 */
/* 0x0101e4000c10110c */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fc400078e000a */
/*05f0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0600*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0610*/ @!P0 BRA 0x760 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea8000c1e1100 */
/*0630*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041e8000c10110c */
/*0640*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*0650*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0043e8000c10110c */
/*0660*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea2000c1e1100 */
/*0670*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0680*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0690*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x004fe8000c10110c */
/*06a0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x0004e2000c1e1100 */
/*06b0*/ IADD3 R8, P2, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fe20007f5e0ff */
/*06c0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*06d0*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fc60007f3e0ff */
/*06e0*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0603 */
/*06f0*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x002fe400008e0605 */
/*0700*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x004fe200078e0008 */
/*0710*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe20000000f00 */
/*0720*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x0081e4000c10110c */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000a */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0750*/ @P0 BRA 0x620 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0760*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0770*/ @!P0 BRA 0x8d0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0780*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0790*/ ULDC.64 UR10, c[0x0][0x178] ; /* 0x00005e00000a7ab9 */
/* 0x000fe40000000a00 */
/*07a0*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*07b0*/ UIADD3 UR7, UP0, UR4, UR8, URZ ; /* 0x0000000804077290 */
/* 0x000fe4000ff1e03f */
/*07c0*/ UIADD3 UR6, UP1, UR4, UR10, URZ ; /* 0x0000000a04067290 */
/* 0x000fe4000ff3e03f */
/*07d0*/ UIADD3.X UR8, UR5, UR9, URZ, UP0, !UPT ; /* 0x0000000905087290 */
/* 0x000fc400087fe43f */
/*07e0*/ UIADD3.X UR5, UR5, UR11, URZ, UP1, !UPT ; /* 0x0000000b05057290 */
/* 0x000fc80008ffe43f */
/*07f0*/ IMAD.U32 R3, RZ, RZ, UR8 ; /* 0x00000008ff037e24 */
/* 0x001fe4000f8e00ff */
/*0800*/ IMAD.U32 R2, RZ, RZ, UR7 ; /* 0x00000007ff027e24 */
/* 0x000fca000f8e00ff */
/*0810*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000c02037981 */
/* 0x000ea2000c1e1100 */
/*0820*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0840*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0850*/ UIADD3 UR7, UP0, UR7, 0x1, URZ ; /* 0x0000000107077890 */
/* 0x000fe2000ff1e03f */
/*0860*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0870*/ UIADD3 UR6, UP1, UR6, 0x1, URZ ; /* 0x0000000106067890 */
/* 0x000fe4000ff3e03f */
/*0880*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0890*/ UIADD3.X UR8, URZ, UR8, URZ, UP0, !UPT ; /* 0x000000083f087290 */
/* 0x000fc400087fe43f */
/*08a0*/ UIADD3.X UR5, URZ, UR5, URZ, UP1, !UPT ; /* 0x000000053f057290 */
/* 0x000fe20008ffe43f */
/*08b0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041ea000c10110c */
/*08c0*/ @P0 BRA 0x7f0 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*08e0*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe20000000a00 */
/*08f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x001fca00078e00ff */
/*0900*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000c02077981 */
/* 0x000ea2000c1e1100 */
/*0910*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000ff1e03f */
/*0920*/ ULEA.HI.X.SX32 UR4, UR4, UR7, 0x1, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f0e3f */
/*0930*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x000fc8000f8e00ff */
/*0940*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fca000f8e00ff */
/*0950*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c10110c */
/*0960*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010c02097981 */
/* 0x000ea8000c1e1100 */
/*0970*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x004fe8000c10110c */
/*0980*/ LDG.E.U8 R11, [R2.64+0x2] ; /* 0x0000020c020b7981 */
/* 0x000ea8000c1e1100 */
/*0990*/ STG.E.U8 [R4.64+0x2], R11 ; /* 0x0000020b04007986 */
/* 0x004fe8000c10110c */
/*09a0*/ LDG.E.U8 R13, [R2.64+0x3] ; /* 0x0000030c020d7981 */
/* 0x000ea8000c1e1100 */
/*09b0*/ STG.E.U8 [R4.64+0x3], R13 ; /* 0x0000030d04007986 */
/* 0x004fe2000c10110c */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPciPiS_
.globl _Z4funcPciPiS_
.p2align 8
.type _Z4funcPciPiS_,@function
_Z4funcPciPiS_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s9, s8
s_mov_b64 s[6:7], s[2:3]
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
global_store_b8 v0, v1, s[6:7]
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_add_i32 s9, s9, -1
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s9, 0
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
s_mov_b32 s8, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_add_u32 s4, s2, s8
s_addc_u32 s5, s3, 0
s_mov_b64 s[2:3], 0
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s2
s_addc_u32 s7, s1, s3
global_load_u8 v1, v0, s[6:7]
s_add_u32 s6, s4, s2
s_addc_u32 s7, s5, s3
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
s_waitcnt vmcnt(0)
global_store_b8 v0, v1, s[6:7]
s_cbranch_scc0 .LBB0_5
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPciPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPciPiS_, .Lfunc_end0-_Z4funcPciPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPciPiS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z4funcPciPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cf127_00000000-6_func.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4funcPciPiS_PciPiS_
.type _Z28__device_stub__Z4funcPciPiS_PciPiS_, @function
_Z28__device_stub__Z4funcPciPiS_PciPiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4funcPciPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4funcPciPiS_PciPiS_, .-_Z28__device_stub__Z4funcPciPiS_PciPiS_
.globl _Z4funcPciPiS_
.type _Z4funcPciPiS_, @function
_Z4funcPciPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4funcPciPiS_PciPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4funcPciPiS_, .-_Z4funcPciPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcPciPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPciPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "func.hip"
.globl _Z19__device_stub__funcPciPiS_ # -- Begin function _Z19__device_stub__funcPciPiS_
.p2align 4, 0x90
.type _Z19__device_stub__funcPciPiS_,@function
_Z19__device_stub__funcPciPiS_: # @_Z19__device_stub__funcPciPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4funcPciPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPciPiS_, .Lfunc_end0-_Z19__device_stub__funcPciPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPciPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPciPiS_,@object # @_Z4funcPciPiS_
.section .rodata,"a",@progbits
.globl _Z4funcPciPiS_
.p2align 3, 0x0
_Z4funcPciPiS_:
.quad _Z19__device_stub__funcPciPiS_
.size _Z4funcPciPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcPciPiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPciPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPciPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cufft.h>
#include <iostream>
const int NX = 2048;
const int NY = 2048;
const int DEFAULT_FFT_TRIALS = 10000;
const int DEFAULT_META_TRIALS = 10;
const int BATCH_SIZE = 1;
int main(int argc, char **argv) {
int fft_trials = DEFAULT_FFT_TRIALS;
int meta_trials = DEFAULT_META_TRIALS;
printf("[INFO] META trials: %d\n", meta_trials);
printf("[INFO] FFT trials: %d\n", fft_trials);
long nx = NX;
long ny = NX;
printf("[INFO] NX Length: %ld\n", nx);
printf("[INFO] NY Length: %ld\n", ny);
cufftComplex *h_original_signal, *h_applied_fft_signal;
cudaMallocHost((void **) &h_original_signal, sizeof(cufftComplex) * NX * NY);
cudaMallocHost((void **) &h_applied_fft_signal, sizeof(cufftComplex) * NX * NY);
cufftComplex *d_original_signal, *d_applied_fft_signal;
cudaMalloc((void **) &d_original_signal, sizeof(cufftComplex) * NX * NY);
cudaMalloc((void **) &d_applied_fft_signal, sizeof(cufftComplex) * NX * NY);
/*
* generate random signal as original signal
*/
srand(0); // initialize random seed
for (int i = 0; i < NX*NY; i++) {
h_original_signal[i].x = (float)((int)rand() % 10);
h_original_signal[i].y = 0.0;
}
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_original_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
cudaMemcpy(d_original_signal, h_original_signal, sizeof(cufftComplex) * NX * NY, cudaMemcpyHostToDevice);
cufftHandle fft_plan;
//cufftPlan1d(&fft_plan, NX, CUFFT_C2C, BATCH_SIZE);
cufftPlan2d(&fft_plan, NX, NY, CUFFT_C2C);
// int *n = new int[2];
// n[0] = nx;
// n[1] = ny;
//
// int *inembed = new int[2];
// inembed[0] = nx;
// inembed[1] = ny;
//
// int istride = 1;
// int idist = nx*ny;
//
// cufftPlanMany(&fft_plan, 2, n, inembed, istride, idist, inembed, istride, idist, CUFFT_C2C, 1);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float sum_of_elapsed_times = 0.0;
printf("[INFO] Run benchmark...\n");
for (int i = 0; i < meta_trials; i++) {
cudaEventRecord(start, 0);
for (int j = 0; j < fft_trials; j++) {
cufftExecC2C(fft_plan, d_original_signal, d_applied_fft_signal, CUFFT_FORWARD);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsed_time_ms;
cudaEventElapsedTime(&elapsed_time_ms, start, stop);
float elapsed_time_sec = elapsed_time_ms / 1000.0;
sum_of_elapsed_times += elapsed_time_sec;
printf("%f sec\n", elapsed_time_sec);
}
cudaMemcpy(h_applied_fft_signal, d_applied_fft_signal, sizeof(cufftComplex) * NX * NY, cudaMemcpyDeviceToHost);
// printf("[INFO] computing sum...\n");
//
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_applied_fft_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
//
// float red = 0;
// for (int i = 0; i < NX*NY; i++) {
// red += h_applied_fft_signal[i].x;
// red -= h_applied_fft_signal[i].y;
// }
//
// printf("SUM : %f\n", red);
printf("[INFO] Finished!\n");
printf("[INFO] Average: %lf sec\n", sum_of_elapsed_times / meta_trials);
cudaEventDestroy(start);
cudaEventDestroy(stop);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cufft.h>
#include <iostream>
const int NX = 2048;
const int NY = 2048;
const int DEFAULT_FFT_TRIALS = 10000;
const int DEFAULT_META_TRIALS = 10;
const int BATCH_SIZE = 1;
int main(int argc, char **argv) {
int fft_trials = DEFAULT_FFT_TRIALS;
int meta_trials = DEFAULT_META_TRIALS;
printf("[INFO] META trials: %d\n", meta_trials);
printf("[INFO] FFT trials: %d\n", fft_trials);
long nx = NX;
long ny = NX;
printf("[INFO] NX Length: %ld\n", nx);
printf("[INFO] NY Length: %ld\n", ny);
cufftComplex *h_original_signal, *h_applied_fft_signal;
cudaMallocHost((void **) &h_original_signal, sizeof(cufftComplex) * NX * NY);
cudaMallocHost((void **) &h_applied_fft_signal, sizeof(cufftComplex) * NX * NY);
cufftComplex *d_original_signal, *d_applied_fft_signal;
cudaMalloc((void **) &d_original_signal, sizeof(cufftComplex) * NX * NY);
cudaMalloc((void **) &d_applied_fft_signal, sizeof(cufftComplex) * NX * NY);
/*
* generate random signal as original signal
*/
srand(0); // initialize random seed
for (int i = 0; i < NX*NY; i++) {
h_original_signal[i].x = (float)((int)rand() % 10);
h_original_signal[i].y = 0.0;
}
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_original_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
cudaMemcpy(d_original_signal, h_original_signal, sizeof(cufftComplex) * NX * NY, cudaMemcpyHostToDevice);
cufftHandle fft_plan;
//cufftPlan1d(&fft_plan, NX, CUFFT_C2C, BATCH_SIZE);
cufftPlan2d(&fft_plan, NX, NY, CUFFT_C2C);
// int *n = new int[2];
// n[0] = nx;
// n[1] = ny;
//
// int *inembed = new int[2];
// inembed[0] = nx;
// inembed[1] = ny;
//
// int istride = 1;
// int idist = nx*ny;
//
// cufftPlanMany(&fft_plan, 2, n, inembed, istride, idist, inembed, istride, idist, CUFFT_C2C, 1);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float sum_of_elapsed_times = 0.0;
printf("[INFO] Run benchmark...\n");
for (int i = 0; i < meta_trials; i++) {
cudaEventRecord(start, 0);
for (int j = 0; j < fft_trials; j++) {
cufftExecC2C(fft_plan, d_original_signal, d_applied_fft_signal, CUFFT_FORWARD);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsed_time_ms;
cudaEventElapsedTime(&elapsed_time_ms, start, stop);
float elapsed_time_sec = elapsed_time_ms / 1000.0;
sum_of_elapsed_times += elapsed_time_sec;
printf("%f sec\n", elapsed_time_sec);
}
cudaMemcpy(h_applied_fft_signal, d_applied_fft_signal, sizeof(cufftComplex) * NX * NY, cudaMemcpyDeviceToHost);
// printf("[INFO] computing sum...\n");
//
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_applied_fft_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
//
// float red = 0;
// for (int i = 0; i < NX*NY; i++) {
// red += h_applied_fft_signal[i].x;
// red -= h_applied_fft_signal[i].y;
// }
//
// printf("SUM : %f\n", red);
printf("[INFO] Finished!\n");
printf("[INFO] Average: %lf sec\n", sum_of_elapsed_times / meta_trials);
cudaEventDestroy(start);
cudaEventDestroy(stop);
} | .file "tmpxft_001200f9_00000000-6_sfft2D.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "[INFO] META trials: %d\n"
.LC2:
.string "[INFO] FFT trials: %d\n"
.LC3:
.string "[INFO] NX Length: %ld\n"
.LC4:
.string "[INFO] NY Length: %ld\n"
.LC5:
.string "[INFO] Run benchmark...\n"
.LC7:
.string "%f sec\n"
.LC8:
.string "[INFO] Finished!\n"
.LC10:
.string "[INFO] Average: %lf sec\n"
.text
.globl main
.type main, @function
main:
.LFB3692:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $10, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $10000, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2048, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2048, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $33554432, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $33554432, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $33554432, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $33554432, %esi
call cudaMalloc@PLT
movl $0, %edi
call srand@PLT
movl $0, %ebx
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx)
movq 8(%rsp), %rax
movl $0x00000000, 4(%rax,%rbx)
addq $8, %rbx
cmpq $33554432, %rbx
jne .L4
movl $1, %ecx
movl $33554432, %edx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rdi
movl $41, %ecx
movl $2048, %edx
movl $2048, %esi
call cufftPlan2d@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %ebp
movl $0x00000000, %r14d
leaq 4(%rsp), %r13
leaq .LC7(%rip), %r12
.L6:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $10000, %ebx
.L5:
movl $-1, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl (%rsp), %edi
call cufftExecC2C@PLT
subl $1, %ebx
jne .L5
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC6(%rip), %xmm0
movd %r14d, %xmm1
addss %xmm0, %xmm1
movd %xmm1, %r14d
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebp
jne .L6
movl $2, %ecx
movl $33554432, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movd %r14d, %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3692:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3718:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3718:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.align 4
.LC9:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cufft.h>
#include <iostream>
const int NX = 2048;
const int NY = 2048;
const int DEFAULT_FFT_TRIALS = 10000;
const int DEFAULT_META_TRIALS = 10;
const int BATCH_SIZE = 1;
int main(int argc, char **argv) {
int fft_trials = DEFAULT_FFT_TRIALS;
int meta_trials = DEFAULT_META_TRIALS;
printf("[INFO] META trials: %d\n", meta_trials);
printf("[INFO] FFT trials: %d\n", fft_trials);
long nx = NX;
long ny = NX;
printf("[INFO] NX Length: %ld\n", nx);
printf("[INFO] NY Length: %ld\n", ny);
cufftComplex *h_original_signal, *h_applied_fft_signal;
cudaMallocHost((void **) &h_original_signal, sizeof(cufftComplex) * NX * NY);
cudaMallocHost((void **) &h_applied_fft_signal, sizeof(cufftComplex) * NX * NY);
cufftComplex *d_original_signal, *d_applied_fft_signal;
cudaMalloc((void **) &d_original_signal, sizeof(cufftComplex) * NX * NY);
cudaMalloc((void **) &d_applied_fft_signal, sizeof(cufftComplex) * NX * NY);
/*
* generate random signal as original signal
*/
srand(0); // initialize random seed
for (int i = 0; i < NX*NY; i++) {
h_original_signal[i].x = (float)((int)rand() % 10);
h_original_signal[i].y = 0.0;
}
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_original_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
cudaMemcpy(d_original_signal, h_original_signal, sizeof(cufftComplex) * NX * NY, cudaMemcpyHostToDevice);
cufftHandle fft_plan;
//cufftPlan1d(&fft_plan, NX, CUFFT_C2C, BATCH_SIZE);
cufftPlan2d(&fft_plan, NX, NY, CUFFT_C2C);
// int *n = new int[2];
// n[0] = nx;
// n[1] = ny;
//
// int *inembed = new int[2];
// inembed[0] = nx;
// inembed[1] = ny;
//
// int istride = 1;
// int idist = nx*ny;
//
// cufftPlanMany(&fft_plan, 2, n, inembed, istride, idist, inembed, istride, idist, CUFFT_C2C, 1);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float sum_of_elapsed_times = 0.0;
printf("[INFO] Run benchmark...\n");
for (int i = 0; i < meta_trials; i++) {
cudaEventRecord(start, 0);
for (int j = 0; j < fft_trials; j++) {
cufftExecC2C(fft_plan, d_original_signal, d_applied_fft_signal, CUFFT_FORWARD);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsed_time_ms;
cudaEventElapsedTime(&elapsed_time_ms, start, stop);
float elapsed_time_sec = elapsed_time_ms / 1000.0;
sum_of_elapsed_times += elapsed_time_sec;
printf("%f sec\n", elapsed_time_sec);
}
cudaMemcpy(h_applied_fft_signal, d_applied_fft_signal, sizeof(cufftComplex) * NX * NY, cudaMemcpyDeviceToHost);
// printf("[INFO] computing sum...\n");
//
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_applied_fft_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
//
// float red = 0;
// for (int i = 0; i < NX*NY; i++) {
// red += h_applied_fft_signal[i].x;
// red -= h_applied_fft_signal[i].y;
// }
//
// printf("SUM : %f\n", red);
printf("[INFO] Finished!\n");
printf("[INFO] Average: %lf sec\n", sum_of_elapsed_times / meta_trials);
cudaEventDestroy(start);
cudaEventDestroy(stop);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hipfft/hipfft.h>
#include <iostream>
const int NX = 2048;
const int NY = 2048;
const int DEFAULT_FFT_TRIALS = 10000;
const int DEFAULT_META_TRIALS = 10;
const int BATCH_SIZE = 1;
int main(int argc, char **argv) {
int fft_trials = DEFAULT_FFT_TRIALS;
int meta_trials = DEFAULT_META_TRIALS;
printf("[INFO] META trials: %d\n", meta_trials);
printf("[INFO] FFT trials: %d\n", fft_trials);
long nx = NX;
long ny = NX;
printf("[INFO] NX Length: %ld\n", nx);
printf("[INFO] NY Length: %ld\n", ny);
hipfftComplex *h_original_signal, *h_applied_fft_signal;
hipHostMalloc((void **) &h_original_signal, sizeof(hipfftComplex) * NX * NY, hipHostMallocDefault);
hipHostMalloc((void **) &h_applied_fft_signal, sizeof(hipfftComplex) * NX * NY, hipHostMallocDefault);
hipfftComplex *d_original_signal, *d_applied_fft_signal;
hipMalloc((void **) &d_original_signal, sizeof(hipfftComplex) * NX * NY);
hipMalloc((void **) &d_applied_fft_signal, sizeof(hipfftComplex) * NX * NY);
/*
* generate random signal as original signal
*/
srand(0); // initialize random seed
for (int i = 0; i < NX*NY; i++) {
h_original_signal[i].x = (float)((int)rand() % 10);
h_original_signal[i].y = 0.0;
}
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_original_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
hipMemcpy(d_original_signal, h_original_signal, sizeof(hipfftComplex) * NX * NY, hipMemcpyHostToDevice);
hipfftHandle fft_plan;
//cufftPlan1d(&fft_plan, NX, CUFFT_C2C, BATCH_SIZE);
hipfftPlan2d(&fft_plan, NX, NY, HIPFFT_C2C);
// int *n = new int[2];
// n[0] = nx;
// n[1] = ny;
//
// int *inembed = new int[2];
// inembed[0] = nx;
// inembed[1] = ny;
//
// int istride = 1;
// int idist = nx*ny;
//
// cufftPlanMany(&fft_plan, 2, n, inembed, istride, idist, inembed, istride, idist, CUFFT_C2C, 1);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float sum_of_elapsed_times = 0.0;
printf("[INFO] Run benchmark...\n");
for (int i = 0; i < meta_trials; i++) {
hipEventRecord(start, 0);
for (int j = 0; j < fft_trials; j++) {
hipfftExecC2C(fft_plan, d_original_signal, d_applied_fft_signal, HIPFFT_FORWARD);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsed_time_ms;
hipEventElapsedTime(&elapsed_time_ms, start, stop);
float elapsed_time_sec = elapsed_time_ms / 1000.0;
sum_of_elapsed_times += elapsed_time_sec;
printf("%f sec\n", elapsed_time_sec);
}
hipMemcpy(h_applied_fft_signal, d_applied_fft_signal, sizeof(hipfftComplex) * NX * NY, hipMemcpyDeviceToHost);
// printf("[INFO] computing sum...\n");
//
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_applied_fft_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
//
// float red = 0;
// for (int i = 0; i < NX*NY; i++) {
// red += h_applied_fft_signal[i].x;
// red -= h_applied_fft_signal[i].y;
// }
//
// printf("SUM : %f\n", red);
printf("[INFO] Finished!\n");
printf("[INFO] Average: %lf sec\n", sum_of_elapsed_times / meta_trials);
hipEventDestroy(start);
hipEventDestroy(stop);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hipfft/hipfft.h>
#include <iostream>
const int NX = 2048;
const int NY = 2048;
const int DEFAULT_FFT_TRIALS = 10000;
const int DEFAULT_META_TRIALS = 10;
const int BATCH_SIZE = 1;
int main(int argc, char **argv) {
int fft_trials = DEFAULT_FFT_TRIALS;
int meta_trials = DEFAULT_META_TRIALS;
printf("[INFO] META trials: %d\n", meta_trials);
printf("[INFO] FFT trials: %d\n", fft_trials);
long nx = NX;
long ny = NX;
printf("[INFO] NX Length: %ld\n", nx);
printf("[INFO] NY Length: %ld\n", ny);
hipfftComplex *h_original_signal, *h_applied_fft_signal;
hipHostMalloc((void **) &h_original_signal, sizeof(hipfftComplex) * NX * NY, hipHostMallocDefault);
hipHostMalloc((void **) &h_applied_fft_signal, sizeof(hipfftComplex) * NX * NY, hipHostMallocDefault);
hipfftComplex *d_original_signal, *d_applied_fft_signal;
hipMalloc((void **) &d_original_signal, sizeof(hipfftComplex) * NX * NY);
hipMalloc((void **) &d_applied_fft_signal, sizeof(hipfftComplex) * NX * NY);
/*
* generate random signal as original signal
*/
srand(0); // initialize random seed
for (int i = 0; i < NX*NY; i++) {
h_original_signal[i].x = (float)((int)rand() % 10);
h_original_signal[i].y = 0.0;
}
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_original_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
hipMemcpy(d_original_signal, h_original_signal, sizeof(hipfftComplex) * NX * NY, hipMemcpyHostToDevice);
hipfftHandle fft_plan;
//cufftPlan1d(&fft_plan, NX, CUFFT_C2C, BATCH_SIZE);
hipfftPlan2d(&fft_plan, NX, NY, HIPFFT_C2C);
// int *n = new int[2];
// n[0] = nx;
// n[1] = ny;
//
// int *inembed = new int[2];
// inembed[0] = nx;
// inembed[1] = ny;
//
// int istride = 1;
// int idist = nx*ny;
//
// cufftPlanMany(&fft_plan, 2, n, inembed, istride, idist, inembed, istride, idist, CUFFT_C2C, 1);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float sum_of_elapsed_times = 0.0;
printf("[INFO] Run benchmark...\n");
for (int i = 0; i < meta_trials; i++) {
hipEventRecord(start, 0);
for (int j = 0; j < fft_trials; j++) {
hipfftExecC2C(fft_plan, d_original_signal, d_applied_fft_signal, HIPFFT_FORWARD);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsed_time_ms;
hipEventElapsedTime(&elapsed_time_ms, start, stop);
float elapsed_time_sec = elapsed_time_ms / 1000.0;
sum_of_elapsed_times += elapsed_time_sec;
printf("%f sec\n", elapsed_time_sec);
}
hipMemcpy(h_applied_fft_signal, d_applied_fft_signal, sizeof(hipfftComplex) * NX * NY, hipMemcpyDeviceToHost);
// printf("[INFO] computing sum...\n");
//
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_applied_fft_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
//
// float red = 0;
// for (int i = 0; i < NX*NY; i++) {
// red += h_applied_fft_signal[i].x;
// red -= h_applied_fft_signal[i].y;
// }
//
// printf("SUM : %f\n", red);
printf("[INFO] Finished!\n");
printf("[INFO] Average: %lf sec\n", sum_of_elapsed_times / meta_trials);
hipEventDestroy(start);
hipEventDestroy(stop);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hipfft/hipfft.h>
#include <iostream>
const int NX = 2048;
const int NY = 2048;
const int DEFAULT_FFT_TRIALS = 10000;
const int DEFAULT_META_TRIALS = 10;
const int BATCH_SIZE = 1;
int main(int argc, char **argv) {
int fft_trials = DEFAULT_FFT_TRIALS;
int meta_trials = DEFAULT_META_TRIALS;
printf("[INFO] META trials: %d\n", meta_trials);
printf("[INFO] FFT trials: %d\n", fft_trials);
long nx = NX;
long ny = NX;
printf("[INFO] NX Length: %ld\n", nx);
printf("[INFO] NY Length: %ld\n", ny);
hipfftComplex *h_original_signal, *h_applied_fft_signal;
hipHostMalloc((void **) &h_original_signal, sizeof(hipfftComplex) * NX * NY, hipHostMallocDefault);
hipHostMalloc((void **) &h_applied_fft_signal, sizeof(hipfftComplex) * NX * NY, hipHostMallocDefault);
hipfftComplex *d_original_signal, *d_applied_fft_signal;
hipMalloc((void **) &d_original_signal, sizeof(hipfftComplex) * NX * NY);
hipMalloc((void **) &d_applied_fft_signal, sizeof(hipfftComplex) * NX * NY);
/*
* generate random signal as original signal
*/
srand(0); // initialize random seed
for (int i = 0; i < NX*NY; i++) {
h_original_signal[i].x = (float)((int)rand() % 10);
h_original_signal[i].y = 0.0;
}
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_original_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
hipMemcpy(d_original_signal, h_original_signal, sizeof(hipfftComplex) * NX * NY, hipMemcpyHostToDevice);
hipfftHandle fft_plan;
//cufftPlan1d(&fft_plan, NX, CUFFT_C2C, BATCH_SIZE);
hipfftPlan2d(&fft_plan, NX, NY, HIPFFT_C2C);
// int *n = new int[2];
// n[0] = nx;
// n[1] = ny;
//
// int *inembed = new int[2];
// inembed[0] = nx;
// inembed[1] = ny;
//
// int istride = 1;
// int idist = nx*ny;
//
// cufftPlanMany(&fft_plan, 2, n, inembed, istride, idist, inembed, istride, idist, CUFFT_C2C, 1);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float sum_of_elapsed_times = 0.0;
printf("[INFO] Run benchmark...\n");
for (int i = 0; i < meta_trials; i++) {
hipEventRecord(start, 0);
for (int j = 0; j < fft_trials; j++) {
hipfftExecC2C(fft_plan, d_original_signal, d_applied_fft_signal, HIPFFT_FORWARD);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsed_time_ms;
hipEventElapsedTime(&elapsed_time_ms, start, stop);
float elapsed_time_sec = elapsed_time_ms / 1000.0;
sum_of_elapsed_times += elapsed_time_sec;
printf("%f sec\n", elapsed_time_sec);
}
hipMemcpy(h_applied_fft_signal, d_applied_fft_signal, sizeof(hipfftComplex) * NX * NY, hipMemcpyDeviceToHost);
// printf("[INFO] computing sum...\n");
//
// for (int i = 0; i < NX; ++i){
// for (int j = 0; j < NY; ++j){
// std::cout << h_applied_fft_signal[i*NX + j].x << " ";
// }
// std::cout << std::endl;
// }
//
// float red = 0;
// for (int i = 0; i < NX*NY; i++) {
// red += h_applied_fft_signal[i].x;
// red -= h_applied_fft_signal[i].y;
// }
//
// printf("SUM : %f\n", red);
printf("[INFO] Finished!\n");
printf("[INFO] Average: %lf sec\n", sum_of_elapsed_times / meta_trials);
hipEventDestroy(start);
hipEventDestroy(stop);
} | .text
.file "sfft2D.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $10, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $10000, %esi # imm = 0x2710
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $2048, %esi # imm = 0x800
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $2048, %esi # imm = 0x800
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
xorl %edx, %edx
callq hipHostMalloc
leaq 72(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
xorl %edx, %edx
callq hipHostMalloc
leaq 56(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
callq hipMalloc
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 32(%rsp), %rax
movss %xmm0, (%rax,%rbx,8)
movq 32(%rsp), %rax
movl $0, 4(%rax,%rbx,8)
incq %rbx
cmpq $4194304, %rbx # imm = 0x400000
jne .LBB0_1
# %bb.2:
movq 56(%rsp), %rdi
movq 32(%rsp), %rsi
movl $33554432, %edx # imm = 0x2000000
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
movl $41, %ecx
callq hipfftPlan2d
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
xorps %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %r14d, %r14d
leaq 44(%rsp), %rbx
.p2align 4, 0x90
.LBB0_3: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10000, %ebp # imm = 0x2710
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movq 64(%rsp), %rdi
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
movl $-1, %ecx
callq hipfftExecC2C
decl %ebp
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incl %r14d
cmpl $10, %r14d
jne .LBB0_3
# %bb.6:
movq 72(%rsp), %rdi
movq 48(%rsp), %rsi
movl $33554432, %edx # imm = 0x2000000
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[INFO] META trials: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "[INFO] FFT trials: %d\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "[INFO] NX Length: %ld\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[INFO] NY Length: %ld\n"
.size .L.str.3, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f sec\n"
.size .L.str.5, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "[INFO] Average: %lf sec\n"
.size .L.str.7, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[INFO] Run benchmark..."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "[INFO] Finished!"
.size .Lstr.1, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001200f9_00000000-6_sfft2D.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "[INFO] META trials: %d\n"
.LC2:
.string "[INFO] FFT trials: %d\n"
.LC3:
.string "[INFO] NX Length: %ld\n"
.LC4:
.string "[INFO] NY Length: %ld\n"
.LC5:
.string "[INFO] Run benchmark...\n"
.LC7:
.string "%f sec\n"
.LC8:
.string "[INFO] Finished!\n"
.LC10:
.string "[INFO] Average: %lf sec\n"
.text
.globl main
.type main, @function
main:
.LFB3692:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $10, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $10000, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2048, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2048, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $33554432, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $33554432, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $33554432, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $33554432, %esi
call cudaMalloc@PLT
movl $0, %edi
call srand@PLT
movl $0, %ebx
.L4:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx)
movq 8(%rsp), %rax
movl $0x00000000, 4(%rax,%rbx)
addq $8, %rbx
cmpq $33554432, %rbx
jne .L4
movl $1, %ecx
movl $33554432, %edx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rdi
movl $41, %ecx
movl $2048, %edx
movl $2048, %esi
call cufftPlan2d@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %ebp
movl $0x00000000, %r14d
leaq 4(%rsp), %r13
leaq .LC7(%rip), %r12
.L6:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $10000, %ebx
.L5:
movl $-1, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl (%rsp), %edi
call cufftExecC2C@PLT
subl $1, %ebx
jne .L5
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
divss .LC6(%rip), %xmm0
movd %r14d, %xmm1
addss %xmm0, %xmm1
movd %xmm1, %r14d
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebp
jne .L6
movl $2, %ecx
movl $33554432, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movd %r14d, %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3692:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3718:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3718:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.align 4
.LC9:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sfft2D.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $10, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $10000, %esi # imm = 0x2710
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $2048, %esi # imm = 0x800
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $2048, %esi # imm = 0x800
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
xorl %edx, %edx
callq hipHostMalloc
leaq 72(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
xorl %edx, %edx
callq hipHostMalloc
leaq 56(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $33554432, %esi # imm = 0x2000000
callq hipMalloc
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 32(%rsp), %rax
movss %xmm0, (%rax,%rbx,8)
movq 32(%rsp), %rax
movl $0, 4(%rax,%rbx,8)
incq %rbx
cmpq $4194304, %rbx # imm = 0x400000
jne .LBB0_1
# %bb.2:
movq 56(%rsp), %rdi
movq 32(%rsp), %rsi
movl $33554432, %edx # imm = 0x2000000
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
movl $41, %ecx
callq hipfftPlan2d
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
xorps %xmm0, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
xorl %r14d, %r14d
leaq 44(%rsp), %rbx
.p2align 4, 0x90
.LBB0_3: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10000, %ebp # imm = 0x2710
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movq 64(%rsp), %rdi
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
movl $-1, %ecx
callq hipfftExecC2C
decl %ebp
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 12(%rsp) # 4-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incl %r14d
cmpl $10, %r14d
jne .LBB0_3
# %bb.6:
movq 72(%rsp), %rdi
movq 48(%rsp), %rsi
movl $33554432, %edx # imm = 0x2000000
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[INFO] META trials: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "[INFO] FFT trials: %d\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "[INFO] NX Length: %ld\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[INFO] NY Length: %ld\n"
.size .L.str.3, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f sec\n"
.size .L.str.5, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "[INFO] Average: %lf sec\n"
.size .L.str.7, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[INFO] Run benchmark..."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "[INFO] Finished!"
.size .Lstr.1, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// __device__ - GPU
// __global__ - GPU
// __host__ - CPU
__global__ void add( int a, int b, int *c)
{
*c = a + b;
}
int main()
{
int c;
int *dev_c;
cudaMalloc( (void**)&dev_c, sizeof(int));
add<<<1,1>>> (1, 2, dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("%i\n", c);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// __device__ - GPU
// __global__ - GPU
// __host__ - CPU
__global__ void add( int a, int b, int *c)
{
*c = a + b;
}
int main()
{
int c;
int *dev_c;
cudaMalloc( (void**)&dev_c, sizeof(int));
add<<<1,1>>> (1, 2, dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("%i\n", c);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_0010bcfd_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $2, %esi
movl $1, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
// __device__ - GPU
// __global__ - GPU
// __host__ - CPU
__global__ void add( int a, int b, int *c)
{
*c = a + b;
}
int main()
{
int c;
int *dev_c;
cudaMalloc( (void**)&dev_c, sizeof(int));
add<<<1,1>>> (1, 2, dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("%i\n", c);
cudaFree(dev_c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
// __device__ - GPU
// __global__ - GPU
// __host__ - CPU
__global__ void add( int a, int b, int *c)
{
*c = a + b;
}
int main()
{
int c;
int *dev_c;
hipMalloc( (void**)&dev_c, sizeof(int));
add<<<1,1>>> (1, 2, dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("%i\n", c);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
// __device__ - GPU
// __global__ - GPU
// __host__ - CPU
__global__ void add( int a, int b, int *c)
{
*c = a + b;
}
int main()
{
int c;
int *dev_c;
hipMalloc( (void**)&dev_c, sizeof(int));
add<<<1,1>>> (1, 2, dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("%i\n", c);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
// __device__ - GPU
// __global__ - GPU
// __host__ - CPU
__global__ void add( int a, int b, int *c)
{
*c = a + b;
}
int main()
{
int c;
int *dev_c;
hipMalloc( (void**)&dev_c, sizeof(int));
add<<<1,1>>> (1, 2, dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("%i\n", c);
hipFree(dev_c);
return 0;
} | .text
.file "kernel.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $1, 12(%rsp)
movl $2, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010bcfd_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $2, %esi
movl $1, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $1, 12(%rsp)
movl $2, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight, float r, float g, float b)
{
int column = threadIdx.x + blockDim.x * blockIdx.z;
if (column >= inputWidth)
return;
int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel
+ column;
int imagePixels = inputWidth * inputHeight;
if (id < 3*imagePixels) // 3 for RGB
{
float color = 0.0f;
switch (blockIdx.y)
{
case 0:
color = r;
break;
case 1:
color = g;
break;
case 2:
color = b;
break;
}
target[id] = color;
}
} | code for sm_80
Function : _Z23DrawRgbBackgroundKernelPfiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0080*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*00a0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e260000002500 */
/*00b0*/ UIMAD UR4, UR4, 0x3, URZ ; /* 0x00000003040478a4 */
/* 0x000fe2000f8e023f */
/*00c0*/ IMAD R3, R4, c[0x0][0xc], R3 ; /* 0x0000030004037a24 */
/* 0x001fc800078e0203 */
/*00d0*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0130*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe400078e0202 */
/*0140*/ @!P0 BRA 0x1b0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f05270 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fd800078e00ff */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f05270 */
/*0190*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fd60000000f00 */
/*01a0*/ @P0 MOV R5, RZ ; /* 0x000000ff00050202 */
/* 0x000fca0000000f00 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight, float r, float g, float b)
{
int column = threadIdx.x + blockDim.x * blockIdx.z;
if (column >= inputWidth)
return;
int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel
+ column;
int imagePixels = inputWidth * inputHeight;
if (id < 3*imagePixels) // 3 for RGB
{
float color = 0.0f;
switch (blockIdx.y)
{
case 0:
color = r;
break;
case 1:
color = g;
break;
case 2:
color = b;
break;
}
target[id] = color;
}
} | .file "tmpxft_001b0ad4_00000000-6_DrawRgbBackgroundKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
.type _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff, @function
_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23DrawRgbBackgroundKernelPfiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff, .-_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
.globl _Z23DrawRgbBackgroundKernelPfiifff
.type _Z23DrawRgbBackgroundKernelPfiifff, @function
_Z23DrawRgbBackgroundKernelPfiifff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23DrawRgbBackgroundKernelPfiifff, .-_Z23DrawRgbBackgroundKernelPfiifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23DrawRgbBackgroundKernelPfiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23DrawRgbBackgroundKernelPfiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight, float r, float g, float b)
{
int column = threadIdx.x + blockDim.x * blockIdx.z;
if (column >= inputWidth)
return;
int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel
+ column;
int imagePixels = inputWidth * inputHeight;
if (id < 3*imagePixels) // 3 for RGB
{
float color = 0.0f;
switch (blockIdx.y)
{
case 0:
color = r;
break;
case 1:
color = g;
break;
case 2:
color = b;
break;
}
target[id] = color;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight, float r, float g, float b)
{
int column = threadIdx.x + blockDim.x * blockIdx.z;
if (column >= inputWidth)
return;
int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel
+ column;
int imagePixels = inputWidth * inputHeight;
if (id < 3*imagePixels) // 3 for RGB
{
float color = 0.0f;
switch (blockIdx.y)
{
case 0:
color = r;
break;
case 1:
color = g;
break;
case 2:
color = b;
break;
}
target[id] = color;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight, float r, float g, float b)
{
int column = threadIdx.x + blockDim.x * blockIdx.z;
if (column >= inputWidth)
return;
int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel
+ column;
int imagePixels = inputWidth * inputHeight;
if (id < 3*imagePixels) // 3 for RGB
{
float color = 0.0f;
switch (blockIdx.y)
{
case 0:
color = r;
break;
case 1:
color = g;
break;
case 2:
color = b;
break;
}
target[id] = color;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23DrawRgbBackgroundKernelPfiifff
.globl _Z23DrawRgbBackgroundKernelPfiifff
.p2align 8
.type _Z23DrawRgbBackgroundKernelPfiifff,@function
_Z23DrawRgbBackgroundKernelPfiifff:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[0:1]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_14
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s13
v_mad_u64_u32 v[0:1], null, s2, s4, v[2:3]
s_mul_i32 s2, s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s2, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_6
s_cmp_lt_i32 s14, 2
s_cbranch_scc1 .LBB0_7
s_mov_b32 s3, 0
s_cmp_eq_u32 s14, 2
s_mov_b32 s2, 0
s_cbranch_scc0 .LBB0_8
s_load_b32 s2, s[0:1], 0x18
s_branch .LBB0_8
.LBB0_6:
s_branch .LBB0_11
.LBB0_7:
s_mov_b32 s3, -1
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x14
.LBB0_10:
s_cbranch_execnz .LBB0_13
.LBB0_11:
s_cmp_lg_u32 s14, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, 0
s_cbranch_scc1 .LBB0_13
s_load_b32 s2, s[0:1], 0x10
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23DrawRgbBackgroundKernelPfiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23DrawRgbBackgroundKernelPfiifff, .Lfunc_end0-_Z23DrawRgbBackgroundKernelPfiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23DrawRgbBackgroundKernelPfiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23DrawRgbBackgroundKernelPfiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawRgbBackgroundKernel(float *target, int inputWidth, int inputHeight, float r, float g, float b)
{
int column = threadIdx.x + blockDim.x * blockIdx.z;
if (column >= inputWidth)
return;
int id = inputWidth * ( blockIdx.y * gridDim.x + blockIdx.x) // blockIdx.x == row, blockIdx.y == color channel
+ column;
int imagePixels = inputWidth * inputHeight;
if (id < 3*imagePixels) // 3 for RGB
{
float color = 0.0f;
switch (blockIdx.y)
{
case 0:
color = r;
break;
case 1:
color = g;
break;
case 2:
color = b;
break;
}
target[id] = color;
}
} | .text
.file "DrawRgbBackgroundKernel.hip"
.globl _Z38__device_stub__DrawRgbBackgroundKernelPfiifff # -- Begin function _Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.p2align 4, 0x90
.type _Z38__device_stub__DrawRgbBackgroundKernelPfiifff,@function
_Z38__device_stub__DrawRgbBackgroundKernelPfiifff: # @_Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23DrawRgbBackgroundKernelPfiifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z38__device_stub__DrawRgbBackgroundKernelPfiifff, .Lfunc_end0-_Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23DrawRgbBackgroundKernelPfiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23DrawRgbBackgroundKernelPfiifff,@object # @_Z23DrawRgbBackgroundKernelPfiifff
.section .rodata,"a",@progbits
.globl _Z23DrawRgbBackgroundKernelPfiifff
.p2align 3, 0x0
_Z23DrawRgbBackgroundKernelPfiifff:
.quad _Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.size _Z23DrawRgbBackgroundKernelPfiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23DrawRgbBackgroundKernelPfiifff"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23DrawRgbBackgroundKernelPfiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23DrawRgbBackgroundKernelPfiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e220000002700 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0080*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*00a0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e260000002500 */
/*00b0*/ UIMAD UR4, UR4, 0x3, URZ ; /* 0x00000003040478a4 */
/* 0x000fe2000f8e023f */
/*00c0*/ IMAD R3, R4, c[0x0][0xc], R3 ; /* 0x0000030004037a24 */
/* 0x001fc800078e0203 */
/*00d0*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0130*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe400078e0202 */
/*0140*/ @!P0 BRA 0x1b0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f05270 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fd800078e00ff */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f05270 */
/*0190*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fd60000000f00 */
/*01a0*/ @P0 MOV R5, RZ ; /* 0x000000ff00050202 */
/* 0x000fca0000000f00 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23DrawRgbBackgroundKernelPfiifff
.globl _Z23DrawRgbBackgroundKernelPfiifff
.p2align 8
.type _Z23DrawRgbBackgroundKernelPfiifff,@function
_Z23DrawRgbBackgroundKernelPfiifff:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[0:1]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_14
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s13
v_mad_u64_u32 v[0:1], null, s2, s4, v[2:3]
s_mul_i32 s2, s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s2, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_6
s_cmp_lt_i32 s14, 2
s_cbranch_scc1 .LBB0_7
s_mov_b32 s3, 0
s_cmp_eq_u32 s14, 2
s_mov_b32 s2, 0
s_cbranch_scc0 .LBB0_8
s_load_b32 s2, s[0:1], 0x18
s_branch .LBB0_8
.LBB0_6:
s_branch .LBB0_11
.LBB0_7:
s_mov_b32 s3, -1
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x14
.LBB0_10:
s_cbranch_execnz .LBB0_13
.LBB0_11:
s_cmp_lg_u32 s14, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s2, 0
s_cbranch_scc1 .LBB0_13
s_load_b32 s2, s[0:1], 0x10
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23DrawRgbBackgroundKernelPfiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23DrawRgbBackgroundKernelPfiifff, .Lfunc_end0-_Z23DrawRgbBackgroundKernelPfiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23DrawRgbBackgroundKernelPfiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23DrawRgbBackgroundKernelPfiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0ad4_00000000-6_DrawRgbBackgroundKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
.type _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff, @function
_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23DrawRgbBackgroundKernelPfiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff, .-_Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
.globl _Z23DrawRgbBackgroundKernelPfiifff
.type _Z23DrawRgbBackgroundKernelPfiifff, @function
_Z23DrawRgbBackgroundKernelPfiifff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z23DrawRgbBackgroundKernelPfiifffPfiifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23DrawRgbBackgroundKernelPfiifff, .-_Z23DrawRgbBackgroundKernelPfiifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23DrawRgbBackgroundKernelPfiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23DrawRgbBackgroundKernelPfiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DrawRgbBackgroundKernel.hip"
.globl _Z38__device_stub__DrawRgbBackgroundKernelPfiifff # -- Begin function _Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.p2align 4, 0x90
.type _Z38__device_stub__DrawRgbBackgroundKernelPfiifff,@function
_Z38__device_stub__DrawRgbBackgroundKernelPfiifff: # @_Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23DrawRgbBackgroundKernelPfiifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z38__device_stub__DrawRgbBackgroundKernelPfiifff, .Lfunc_end0-_Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23DrawRgbBackgroundKernelPfiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23DrawRgbBackgroundKernelPfiifff,@object # @_Z23DrawRgbBackgroundKernelPfiifff
.section .rodata,"a",@progbits
.globl _Z23DrawRgbBackgroundKernelPfiifff
.p2align 3, 0x0
_Z23DrawRgbBackgroundKernelPfiifff:
.quad _Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.size _Z23DrawRgbBackgroundKernelPfiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23DrawRgbBackgroundKernelPfiifff"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__DrawRgbBackgroundKernelPfiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23DrawRgbBackgroundKernelPfiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <sstream>
#include <fstream>
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include "changeDatatype.cuh"
using namespace std;
__global__ void changeType(float* srcData, float* dstData, int n, int c, int h, int w, int filtersPerThread_x, int filtersPerThread_y) {
const int idxCol = threadIdx.y + blockDim.y*blockIdx.y;
const int idxRow = threadIdx.x + blockDim.x*blockIdx.x;
int maxBlock = (n * c) / (filtersPerThread_x * filtersPerThread_y);
int idxBlock = (int)fminf((float)(blockIdx.y * gridDim.x + blockIdx.x), (float)(maxBlock));
const int idxfilterW = threadIdx.x % w;
const int idxfilterH = threadIdx.y % h;
int threadChannelX = threadIdx.x / w;
int threadChannelY = threadIdx.y / h;
int idxChannel_a =idxBlock * filtersPerThread_x * filtersPerThread_y + threadChannelY *filtersPerThread_x + threadChannelX;
int idxChannel = idxChannel_a % c;
int idxN = (int)fminf((float)(idxChannel_a / c), (float)(n-1));
dstData[idxN * (c * w* h) + idxChannel * (w*h) + idxfilterH * w + idxfilterW] = srcData[idxfilterH * (n * c * w) + idxfilterW * (c * n) + idxChannel * n + idxN];
}
void changeDataType(float* srcData, float* dstData, int n, int c, int h, int w) {
int filtersPerThread_x = 30 / w;
int filtersPerThread_y = 30 / h;
int totalBlocks = (c * n) / (filtersPerThread_x * filtersPerThread_y) + 1;
int numBlock_y = totalBlocks / 255 + 1;
dim3 numOfBlocks(255, numBlock_y, 1);
dim3 threadsPerBlock(30, 30, 1);
changeType <<< numOfBlocks, threadsPerBlock >> > (srcData, dstData, n, c, h, w, filtersPerThread_x, filtersPerThread_y);
} | code for sm_80
Function : _Z10changeTypePfS_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ I2F.U32.RP R9, c[0x0][0x178] ; /* 0x00005e0000097b06 */
/* 0x000e220000209000 */
/*0030*/ MOV R0, c[0x0][0x174] ; /* 0x00005d0000007a02 */
/* 0x000fe20000000f00 */
/*0040*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e620000002600 */
/*0050*/ IMAD R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a24 */
/* 0x000fe200078e02ff */
/*0060*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0070*/ ISETP.NE.U32.AND P5, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003fa5070 */
/*0080*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe400078e02ff */
/*0090*/ IABS R2, R3.reuse ; /* 0x0000000300027213 */
/* 0x080fe20000000000 */
/*00a0*/ I2F.U32.RP R7, c[0x0][0x17c] ; /* 0x00005f0000077b06 */
/* 0x000fe20000209000 */
/*00b0*/ IABS R10, R3 ; /* 0x00000003000a7213 */
/* 0x000fe20000000000 */
/*00c0*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*00d0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f25270 */
/*00e0*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000eb00000209400 */
/*00f0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x001e300000001000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x004ea20000001000 */
/*0110*/ UIMAD UR4, UR4, UR6, UR5 ; /* 0x00000006040472a4 */
/* 0x002fce000f8e0205 */
/*0120*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e620000001000 */
/*0130*/ IADD3 R9, R9, 0xffffffe, RZ ; /* 0x0ffffffe09097810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x004fca0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000021f000 */
/*0160*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fe40000000000 */
/*0170*/ IADD3 R8, R8, 0xffffffe, RZ ; /* 0x0ffffffe08087810 */
/* 0x002fca0007ffe0ff */
/*0180*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0002a2000021f000 */
/*0190*/ IADD3 R15, RZ, -R9, RZ ; /* 0x80000009ff0f7210 */
/* 0x001fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x002fc800078e00ff */
/*01b0*/ IMAD R15, R15, c[0x0][0x178], RZ ; /* 0x00005e000f0f7a24 */
/* 0x000fe400078e02ff */
/*01c0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x004fc800078e0a05 */
/*01d0*/ IMAD R11, R11, R2, RZ ; /* 0x000000020b0b7224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R4, R5, R11, R4 ; /* 0x0000000b05047227 */
/* 0x000fe200078e0004 */
/*01f0*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R11, R8 ; /* 0x00000008000b7305 */
/* 0x0001e4000021f000 */
/*0210*/ IMAD.MOV R6, RZ, RZ, -R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a0a */
/*0220*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0230*/ IMAD.HI.U32 R12, R4, R5, RZ ; /* 0x00000005040c7227 */
/* 0x000fe400078e00ff */
/*0240*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e640000002100 */
/*0250*/ IMAD R7, R12, R6, R5 ; /* 0x000000060c077224 */
/* 0x000fe200078e0205 */
/*0260*/ IABS R6, c[0x0][0x174] ; /* 0x00005d0000067a13 */
/* 0x000fe20000000000 */
/*0270*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc400078e00ff */
/*0290*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe20003f44070 */
/*02a0*/ I2F.RP R13, R6 ; /* 0x00000006000d7306 */
/* 0x000e220000209400 */
/*02b0*/ IMAD.HI.U32 R8, R9, R15, R8 ; /* 0x0000000f09087227 */
/* 0x000fd600078e0008 */
/*02c0*/ @!P2 IMAD.IADD R7, R7, 0x1, -R2 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a02 */
/*02d0*/ @!P2 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0ca810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f45070 */
/*02f0*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x001e220000001000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe20003f06070 */
/*0310*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*0320*/ LOP3.LUT R2, R0, R3, RZ, 0x3c, !PT ; /* 0x0000000300027212 */
/* 0x000fc600078e3cff */
/*0330*/ IMAD R7, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007077a24 */
/* 0x000fe200078e02ff */
/*0340*/ ISETP.GE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f66270 */
/*0350*/ I2F.U32 R2, UR4 ; /* 0x0000000400027d06 */
/* 0x000fe20008201000 */
/*0360*/ IMAD.HI.U32 R11, R11, R7, R10 ; /* 0x000000070b0b7227 */
/* 0x000fe200078e000a */
/*0370*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0380*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0390*/ IMAD.HI.U32 R7, R8, R5, RZ ; /* 0x0000000508077227 */
/* 0x004fe200078e00ff */
/*03a0*/ @P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c0810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ IMAD.HI.U32 R8, R11, R4, RZ ; /* 0x000000040b087227 */
/* 0x002fe400078e00ff */
/*03c0*/ @!P3 IADD3 R12, -R12, RZ, RZ ; /* 0x000000ff0c0cb210 */
/* 0x000fe40007ffe1ff */
/*03d0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a07 */
/*03e0*/ @!P1 LOP3.LUT R12, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0c9212 */
/* 0x000fe200078e33ff */
/*03f0*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a08 */
/*0400*/ IADD3 R3, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d037810 */
/* 0x001fe20007ffe0ff */
/*0410*/ IMAD R11, R10, c[0x0][0x178], R5 ; /* 0x00005e000a0b7a24 */
/* 0x000fe400078e0205 */
/*0420*/ IMAD R10, R9, c[0x0][0x17c], R4 ; /* 0x00005f00090a7a24 */
/* 0x000fc400078e0204 */
/*0430*/ I2F R9, R12 ; /* 0x0000000c00097306 */
/* 0x000e220000201400 */
/*0440*/ ISETP.GE.U32.AND P3, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f66070 */
/*0450*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fca0003f06070 */
/*0460*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e6c000021f000 */
/*0470*/ @P3 IADD3 R11, R11, -c[0x0][0x178], RZ ; /* 0x80005e000b0b3a10 */
/* 0x000fe40007ffe0ff */
/*0480*/ FMNMX R2, R2, R9, PT ; /* 0x0000000902027209 */
/* 0x001fe40003800000 */
/*0490*/ @P0 IADD3 R10, R10, -c[0x0][0x17c], RZ ; /* 0x80005f000a0a0a10 */
/* 0x000fc40007ffe0ff */
/*04a0*/ ISETP.GE.U32.AND P4, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f86070 */
/*04b0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e22000020f100 */
/*04c0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fe20003f26070 */
/*04d0*/ IMAD.MOV R11, RZ, RZ, -R3 ; /* 0x000000ffff0b7224 */
/* 0x002fe200078e0a03 */
/*04e0*/ @P3 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107073810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe20007ffe0ff */
/*0500*/ IMAD R11, R11, R6, RZ ; /* 0x000000060b0b7224 */
/* 0x000fca00078e02ff */
/*0510*/ @P4 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107074810 */
/* 0x000fe40007ffe0ff */
/*0520*/ @!P5 LOP3.LUT R7, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff07da12 */
/* 0x000fe400078e33ff */
/*0530*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0540*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff08aa12 */
/* 0x000fe200078e33ff */
/*0550*/ IMAD R9, R2, c[0x0][0x184], R7 ; /* 0x0000610002097a24 */
/* 0x001fe400078e0207 */
/*0560*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD R9, R9, c[0x0][0x180], R8 ; /* 0x0000600009097a24 */
/* 0x000fc400078e0208 */
/*0580*/ IMAD.HI.U32 R2, R3, R11, R2 ; /* 0x0000000b03027227 */
/* 0x000fc600078e0002 */
/*0590*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fc80000000000 */
/*05a0*/ MOV R3, R10 ; /* 0x0000000a00037202 */
/* 0x000fca0000000f00 */
/*05b0*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fc800078e00ff */
/*05c0*/ IMAD.MOV R10, RZ, RZ, -R2 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a02 */
/*05d0*/ IMAD R3, R6.reuse, R10, R3 ; /* 0x0000000a06037224 */
/* 0x040fe400078e0203 */
/*05e0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0a07 */
/*05f0*/ IMAD.MOV R7, RZ, RZ, -R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a08 */
/*0600*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f24070 */
/*0610*/ IMAD R5, R10, c[0x0][0x178], R5 ; /* 0x00005e000a057a24 */
/* 0x000fe400078e0205 */
/*0620*/ IMAD R4, R7, c[0x0][0x17c], R4 ; /* 0x00005f0007047a24 */
/* 0x000fd400078e0204 */
/*0630*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0640*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*0650*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25270 */
/*0660*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0670*/ LOP3.LUT R3, R9, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0009037a12 */
/* 0x000fe200078e3cff */
/*0680*/ I2F R6, UR4 ; /* 0x0000000400067d06 */
/* 0x000fe20008201400 */
/*0690*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*06a0*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*06b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*06c0*/ @!P2 IADD3 R2, -R2, RZ, RZ ; /* 0x000000ff0202a210 */
/* 0x000fe40007ffe1ff */
/*06d0*/ @!P1 LOP3.LUT R2, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff029a12 */
/* 0x000fc800078e33ff */
/*06e0*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x000e220000201400 */
/*06f0*/ IADD3 R8, -R2, RZ, RZ ; /* 0x000000ff02087210 */
/* 0x000fca0007ffe1ff */
/*0700*/ IMAD R9, R8, c[0x0][0x174], R9 ; /* 0x00005d0008097a24 */
/* 0x000fe200078e0209 */
/*0710*/ FMNMX R6, R3, R6, PT ; /* 0x0000000603067209 */
/* 0x001fe20003800000 */
/*0720*/ IMAD R3, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005037a24 */
/* 0x000fc800078e0204 */
/*0730*/ IMAD R0, R0, R3, RZ ; /* 0x0000000300007224 */
/* 0x000fe200078e02ff */
/*0740*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e26000020f100 */
/*0750*/ IMAD R3, R9, c[0x0][0x170], R0 ; /* 0x00005c0009037a24 */
/* 0x000fe400078e0200 */
/*0760*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc600078e00ff */
/*0770*/ IADD3 R3, R6, R3, RZ ; /* 0x0000000306037210 */
/* 0x001fca0007ffe0ff */
/*0780*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0200 */
/*0790*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ IMAD R6, R6, c[0x0][0x174], R9 ; /* 0x00005d0006067a24 */
/* 0x000fc800078e0209 */
/*07b0*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*07c0*/ IMAD R5, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005057a24 */
/* 0x000fc800078e0204 */
/*07d0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*07e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <sstream>
#include <fstream>
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include "changeDatatype.cuh"
using namespace std;
__global__ void changeType(float* srcData, float* dstData, int n, int c, int h, int w, int filtersPerThread_x, int filtersPerThread_y) {
const int idxCol = threadIdx.y + blockDim.y*blockIdx.y;
const int idxRow = threadIdx.x + blockDim.x*blockIdx.x;
int maxBlock = (n * c) / (filtersPerThread_x * filtersPerThread_y);
int idxBlock = (int)fminf((float)(blockIdx.y * gridDim.x + blockIdx.x), (float)(maxBlock));
const int idxfilterW = threadIdx.x % w;
const int idxfilterH = threadIdx.y % h;
int threadChannelX = threadIdx.x / w;
int threadChannelY = threadIdx.y / h;
int idxChannel_a =idxBlock * filtersPerThread_x * filtersPerThread_y + threadChannelY *filtersPerThread_x + threadChannelX;
int idxChannel = idxChannel_a % c;
int idxN = (int)fminf((float)(idxChannel_a / c), (float)(n-1));
dstData[idxN * (c * w* h) + idxChannel * (w*h) + idxfilterH * w + idxfilterW] = srcData[idxfilterH * (n * c * w) + idxfilterW * (c * n) + idxChannel * n + idxN];
}
void changeDataType(float* srcData, float* dstData, int n, int c, int h, int w) {
int filtersPerThread_x = 30 / w;
int filtersPerThread_y = 30 / h;
int totalBlocks = (c * n) / (filtersPerThread_x * filtersPerThread_y) + 1;
int numBlock_y = totalBlocks / 255 + 1;
dim3 numOfBlocks(255, numBlock_y, 1);
dim3 threadsPerBlock(30, 30, 1);
changeType <<< numOfBlocks, threadsPerBlock >> > (srcData, dstData, n, c, h, w, filtersPerThread_x, filtersPerThread_y);
} | .file "tmpxft_001483a8_00000000-6_changeDatatype.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3860:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
.type _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii, @function
_Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii:
.LFB3882:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10changeTypePfS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3882:
.size _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii, .-_Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
.globl _Z10changeTypePfS_iiiiii
.type _Z10changeTypePfS_iiiiii, @function
_Z10changeTypePfS_iiiiii:
.LFB3883:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3883:
.size _Z10changeTypePfS_iiiiii, .-_Z10changeTypePfS_iiiiii
.globl _Z14changeDataTypePfS_iiii
.type _Z14changeDataTypePfS_iiii, @function
_Z14changeDataTypePfS_iiii:
.LFB3857:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %ebp
movl %r9d, %r12d
movl $30, %ebx
movl %ebx, %eax
cltd
idivl %r9d
movl %eax, %r15d
movl %ebx, %eax
cltd
idivl %r8d
movl %eax, %ebx
movl $255, 24(%rsp)
movl %ecx, %eax
imull %r13d, %eax
movl %r15d, %ecx
imull %ebx, %ecx
cltd
idivl %ecx
leal 1(%rax), %edx
movslq %edx, %rax
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
sarl $31, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 28(%rsp)
movl $30, 36(%rsp)
movl $30, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq %rbx
.cfi_def_cfa_offset 120
pushq %r15
.cfi_def_cfa_offset 128
movl %r12d, %r9d
movl %ebp, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE3857:
.size _Z14changeDataTypePfS_iiii, .-_Z14changeDataTypePfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10changeTypePfS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10changeTypePfS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3885:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <device_functions.h>
#include <sstream>
#include <fstream>
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include "changeDatatype.cuh"
using namespace std;
__global__ void changeType(float* srcData, float* dstData, int n, int c, int h, int w, int filtersPerThread_x, int filtersPerThread_y) {
const int idxCol = threadIdx.y + blockDim.y*blockIdx.y;
const int idxRow = threadIdx.x + blockDim.x*blockIdx.x;
int maxBlock = (n * c) / (filtersPerThread_x * filtersPerThread_y);
int idxBlock = (int)fminf((float)(blockIdx.y * gridDim.x + blockIdx.x), (float)(maxBlock));
const int idxfilterW = threadIdx.x % w;
const int idxfilterH = threadIdx.y % h;
int threadChannelX = threadIdx.x / w;
int threadChannelY = threadIdx.y / h;
int idxChannel_a =idxBlock * filtersPerThread_x * filtersPerThread_y + threadChannelY *filtersPerThread_x + threadChannelX;
int idxChannel = idxChannel_a % c;
int idxN = (int)fminf((float)(idxChannel_a / c), (float)(n-1));
dstData[idxN * (c * w* h) + idxChannel * (w*h) + idxfilterH * w + idxfilterW] = srcData[idxfilterH * (n * c * w) + idxfilterW * (c * n) + idxChannel * n + idxN];
}
void changeDataType(float* srcData, float* dstData, int n, int c, int h, int w) {
int filtersPerThread_x = 30 / w;
int filtersPerThread_y = 30 / h;
int totalBlocks = (c * n) / (filtersPerThread_x * filtersPerThread_y) + 1;
int numBlock_y = totalBlocks / 255 + 1;
dim3 numOfBlocks(255, numBlock_y, 1);
dim3 threadsPerBlock(30, 30, 1);
changeType <<< numOfBlocks, threadsPerBlock >> > (srcData, dstData, n, c, h, w, filtersPerThread_x, filtersPerThread_y);
} | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <sstream>
#include <fstream>
#include <iostream>
#include <stdlib.h>
#include <math.h>
void changeDataType(float* srcData, float* dstData, int n, int c, int h, int w); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <sstream>
#include <fstream>
#include <iostream>
#include <stdlib.h>
#include <math.h>
void changeDataType(float* srcData, float* dstData, int n, int c, int h, int w); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <sstream>
#include <fstream>
#include <iostream>
#include <stdlib.h>
#include <math.h>
void changeDataType(float* srcData, float* dstData, int n, int c, int h, int w); | .text
.file "changeDatatype.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10changeTypePfS_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ I2F.U32.RP R9, c[0x0][0x178] ; /* 0x00005e0000097b06 */
/* 0x000e220000209000 */
/*0030*/ MOV R0, c[0x0][0x174] ; /* 0x00005d0000007a02 */
/* 0x000fe20000000f00 */
/*0040*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e620000002600 */
/*0050*/ IMAD R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a24 */
/* 0x000fe200078e02ff */
/*0060*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0070*/ ISETP.NE.U32.AND P5, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003fa5070 */
/*0080*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe400078e02ff */
/*0090*/ IABS R2, R3.reuse ; /* 0x0000000300027213 */
/* 0x080fe20000000000 */
/*00a0*/ I2F.U32.RP R7, c[0x0][0x17c] ; /* 0x00005f0000077b06 */
/* 0x000fe20000209000 */
/*00b0*/ IABS R10, R3 ; /* 0x00000003000a7213 */
/* 0x000fe20000000000 */
/*00c0*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*00d0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f25270 */
/*00e0*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000eb00000209400 */
/*00f0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x001e300000001000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x004ea20000001000 */
/*0110*/ UIMAD UR4, UR4, UR6, UR5 ; /* 0x00000006040472a4 */
/* 0x002fce000f8e0205 */
/*0120*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e620000001000 */
/*0130*/ IADD3 R9, R9, 0xffffffe, RZ ; /* 0x0ffffffe09097810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x004fca0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000021f000 */
/*0160*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fe40000000000 */
/*0170*/ IADD3 R8, R8, 0xffffffe, RZ ; /* 0x0ffffffe08087810 */
/* 0x002fca0007ffe0ff */
/*0180*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0002a2000021f000 */
/*0190*/ IADD3 R15, RZ, -R9, RZ ; /* 0x80000009ff0f7210 */
/* 0x001fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x002fc800078e00ff */
/*01b0*/ IMAD R15, R15, c[0x0][0x178], RZ ; /* 0x00005e000f0f7a24 */
/* 0x000fe400078e02ff */
/*01c0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x004fc800078e0a05 */
/*01d0*/ IMAD R11, R11, R2, RZ ; /* 0x000000020b0b7224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R4, R5, R11, R4 ; /* 0x0000000b05047227 */
/* 0x000fe200078e0004 */
/*01f0*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R11, R8 ; /* 0x00000008000b7305 */
/* 0x0001e4000021f000 */
/*0210*/ IMAD.MOV R6, RZ, RZ, -R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a0a */
/*0220*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0230*/ IMAD.HI.U32 R12, R4, R5, RZ ; /* 0x00000005040c7227 */
/* 0x000fe400078e00ff */
/*0240*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e640000002100 */
/*0250*/ IMAD R7, R12, R6, R5 ; /* 0x000000060c077224 */
/* 0x000fe200078e0205 */
/*0260*/ IABS R6, c[0x0][0x174] ; /* 0x00005d0000067a13 */
/* 0x000fe20000000000 */
/*0270*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc400078e00ff */
/*0290*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe20003f44070 */
/*02a0*/ I2F.RP R13, R6 ; /* 0x00000006000d7306 */
/* 0x000e220000209400 */
/*02b0*/ IMAD.HI.U32 R8, R9, R15, R8 ; /* 0x0000000f09087227 */
/* 0x000fd600078e0008 */
/*02c0*/ @!P2 IMAD.IADD R7, R7, 0x1, -R2 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a02 */
/*02d0*/ @!P2 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0ca810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f45070 */
/*02f0*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x001e220000001000 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe20003f06070 */
/*0310*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*0320*/ LOP3.LUT R2, R0, R3, RZ, 0x3c, !PT ; /* 0x0000000300027212 */
/* 0x000fc600078e3cff */
/*0330*/ IMAD R7, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007077a24 */
/* 0x000fe200078e02ff */
/*0340*/ ISETP.GE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f66270 */
/*0350*/ I2F.U32 R2, UR4 ; /* 0x0000000400027d06 */
/* 0x000fe20008201000 */
/*0360*/ IMAD.HI.U32 R11, R11, R7, R10 ; /* 0x000000070b0b7227 */
/* 0x000fe200078e000a */
/*0370*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0380*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0390*/ IMAD.HI.U32 R7, R8, R5, RZ ; /* 0x0000000508077227 */
/* 0x004fe200078e00ff */
/*03a0*/ @P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c0810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ IMAD.HI.U32 R8, R11, R4, RZ ; /* 0x000000040b087227 */
/* 0x002fe400078e00ff */
/*03c0*/ @!P3 IADD3 R12, -R12, RZ, RZ ; /* 0x000000ff0c0cb210 */
/* 0x000fe40007ffe1ff */
/*03d0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a07 */
/*03e0*/ @!P1 LOP3.LUT R12, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0c9212 */
/* 0x000fe200078e33ff */
/*03f0*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a08 */
/*0400*/ IADD3 R3, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d037810 */
/* 0x001fe20007ffe0ff */
/*0410*/ IMAD R11, R10, c[0x0][0x178], R5 ; /* 0x00005e000a0b7a24 */
/* 0x000fe400078e0205 */
/*0420*/ IMAD R10, R9, c[0x0][0x17c], R4 ; /* 0x00005f00090a7a24 */
/* 0x000fc400078e0204 */
/*0430*/ I2F R9, R12 ; /* 0x0000000c00097306 */
/* 0x000e220000201400 */
/*0440*/ ISETP.GE.U32.AND P3, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f66070 */
/*0450*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fca0003f06070 */
/*0460*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e6c000021f000 */
/*0470*/ @P3 IADD3 R11, R11, -c[0x0][0x178], RZ ; /* 0x80005e000b0b3a10 */
/* 0x000fe40007ffe0ff */
/*0480*/ FMNMX R2, R2, R9, PT ; /* 0x0000000902027209 */
/* 0x001fe40003800000 */
/*0490*/ @P0 IADD3 R10, R10, -c[0x0][0x17c], RZ ; /* 0x80005f000a0a0a10 */
/* 0x000fc40007ffe0ff */
/*04a0*/ ISETP.GE.U32.AND P4, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fe40003f86070 */
/*04b0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e22000020f100 */
/*04c0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x17c], PT ; /* 0x00005f000a007a0c */
/* 0x000fe20003f26070 */
/*04d0*/ IMAD.MOV R11, RZ, RZ, -R3 ; /* 0x000000ffff0b7224 */
/* 0x002fe200078e0a03 */
/*04e0*/ @P3 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107073810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe20007ffe0ff */
/*0500*/ IMAD R11, R11, R6, RZ ; /* 0x000000060b0b7224 */
/* 0x000fca00078e02ff */
/*0510*/ @P4 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107074810 */
/* 0x000fe40007ffe0ff */
/*0520*/ @!P5 LOP3.LUT R7, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff07da12 */
/* 0x000fe400078e33ff */
/*0530*/ @P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108081810 */
/* 0x000fe40007ffe0ff */
/*0540*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff08aa12 */
/* 0x000fe200078e33ff */
/*0550*/ IMAD R9, R2, c[0x0][0x184], R7 ; /* 0x0000610002097a24 */
/* 0x001fe400078e0207 */
/*0560*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD R9, R9, c[0x0][0x180], R8 ; /* 0x0000600009097a24 */
/* 0x000fc400078e0208 */
/*0580*/ IMAD.HI.U32 R2, R3, R11, R2 ; /* 0x0000000b03027227 */
/* 0x000fc600078e0002 */
/*0590*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fc80000000000 */
/*05a0*/ MOV R3, R10 ; /* 0x0000000a00037202 */
/* 0x000fca0000000f00 */
/*05b0*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fc800078e00ff */
/*05c0*/ IMAD.MOV R10, RZ, RZ, -R2 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0a02 */
/*05d0*/ IMAD R3, R6.reuse, R10, R3 ; /* 0x0000000a06037224 */
/* 0x040fe400078e0203 */
/*05e0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0a07 */
/*05f0*/ IMAD.MOV R7, RZ, RZ, -R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a08 */
/*0600*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f24070 */
/*0610*/ IMAD R5, R10, c[0x0][0x178], R5 ; /* 0x00005e000a057a24 */
/* 0x000fe400078e0205 */
/*0620*/ IMAD R4, R7, c[0x0][0x17c], R4 ; /* 0x00005f0007047a24 */
/* 0x000fd400078e0204 */
/*0630*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0640*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*0650*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25270 */
/*0660*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*0670*/ LOP3.LUT R3, R9, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0009037a12 */
/* 0x000fe200078e3cff */
/*0680*/ I2F R6, UR4 ; /* 0x0000000400067d06 */
/* 0x000fe20008201400 */
/*0690*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*06a0*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*06b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*06c0*/ @!P2 IADD3 R2, -R2, RZ, RZ ; /* 0x000000ff0202a210 */
/* 0x000fe40007ffe1ff */
/*06d0*/ @!P1 LOP3.LUT R2, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff029a12 */
/* 0x000fc800078e33ff */
/*06e0*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x000e220000201400 */
/*06f0*/ IADD3 R8, -R2, RZ, RZ ; /* 0x000000ff02087210 */
/* 0x000fca0007ffe1ff */
/*0700*/ IMAD R9, R8, c[0x0][0x174], R9 ; /* 0x00005d0008097a24 */
/* 0x000fe200078e0209 */
/*0710*/ FMNMX R6, R3, R6, PT ; /* 0x0000000603067209 */
/* 0x001fe20003800000 */
/*0720*/ IMAD R3, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005037a24 */
/* 0x000fc800078e0204 */
/*0730*/ IMAD R0, R0, R3, RZ ; /* 0x0000000300007224 */
/* 0x000fe200078e02ff */
/*0740*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e26000020f100 */
/*0750*/ IMAD R3, R9, c[0x0][0x170], R0 ; /* 0x00005c0009037a24 */
/* 0x000fe400078e0200 */
/*0760*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc600078e00ff */
/*0770*/ IADD3 R3, R6, R3, RZ ; /* 0x0000000306037210 */
/* 0x001fca0007ffe0ff */
/*0780*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0200 */
/*0790*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*07a0*/ IMAD R6, R6, c[0x0][0x174], R9 ; /* 0x00005d0006067a24 */
/* 0x000fc800078e0209 */
/*07b0*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*07c0*/ IMAD R5, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005057a24 */
/* 0x000fc800078e0204 */
/*07d0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*07e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001483a8_00000000-6_changeDatatype.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3860:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
.type _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii, @function
_Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii:
.LFB3882:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10changeTypePfS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3882:
.size _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii, .-_Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
.globl _Z10changeTypePfS_iiiiii
.type _Z10changeTypePfS_iiiiii, @function
_Z10changeTypePfS_iiiiii:
.LFB3883:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3883:
.size _Z10changeTypePfS_iiiiii, .-_Z10changeTypePfS_iiiiii
.globl _Z14changeDataTypePfS_iiii
.type _Z14changeDataTypePfS_iiii, @function
_Z14changeDataTypePfS_iiii:
.LFB3857:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %r13d
movl %ecx, %r14d
movl %r8d, %ebp
movl %r9d, %r12d
movl $30, %ebx
movl %ebx, %eax
cltd
idivl %r9d
movl %eax, %r15d
movl %ebx, %eax
cltd
idivl %r8d
movl %eax, %ebx
movl $255, 24(%rsp)
movl %ecx, %eax
imull %r13d, %eax
movl %r15d, %ecx
imull %ebx, %ecx
cltd
idivl %ecx
leal 1(%rax), %edx
movslq %edx, %rax
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
sarl $31, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, 28(%rsp)
movl $30, 36(%rsp)
movl $30, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq %rbx
.cfi_def_cfa_offset 120
pushq %r15
.cfi_def_cfa_offset 128
movl %r12d, %r9d
movl %ebp, %r8d
movl %r14d, %ecx
movl %r13d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z10changeTypePfS_iiiiiiPfS_iiiiii
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE3857:
.size _Z14changeDataTypePfS_iiii, .-_Z14changeDataTypePfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10changeTypePfS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10changeTypePfS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3885:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "changeDatatype.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* UpdaterHy1D.cpp
*
* Created on: 25 янв. 2016 г.
* Author: aleksandr
*/
#include "UpdaterHy1D.h"
__device__
void UpdaterHy1D::operator() (const int indx) {
Hy[indx] = Chyh[indx]*Hy[indx] + Chye[indx]*(Ez[indx+1] - Ez[indx]);
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* UpdaterHy1D.cpp
*
* Created on: 25 янв. 2016 г.
* Author: aleksandr
*/
#include "UpdaterHy1D.h"
__device__
void UpdaterHy1D::operator() (const int indx) {
Hy[indx] = Chyh[indx]*Hy[indx] + Chye[indx]*(Ez[indx+1] - Ez[indx]);
} | /*
* UpdaterHy1D.cpp
*
* Created on: 25 янв. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "UpdaterHy1D.h"
__device__
void UpdaterHy1D::operator() (const int indx) {
Hy[indx] = Chyh[indx]*Hy[indx] + Chye[indx]*(Ez[indx+1] - Ez[indx]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* UpdaterHy1D.cpp
*
* Created on: 25 янв. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "UpdaterHy1D.h"
__device__
void UpdaterHy1D::operator() (const int indx) {
Hy[indx] = Chyh[indx]*Hy[indx] + Chye[indx]*(Ez[indx+1] - Ez[indx]);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* UpdaterHy1D.cpp
*
* Created on: 25 янв. 2016 г.
* Author: aleksandr
*/
#include <hip/hip_runtime.h>
#include "UpdaterHy1D.h"
__device__
void UpdaterHy1D::operator() (const int indx) {
Hy[indx] = Chyh[indx]*Hy[indx] + Chye[indx]*(Ez[indx+1] - Ez[indx]);
} | .text
.file "UpdaterHy1D.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <time.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code:%d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__global__ void array_mult_kernel(double *A, double *B, double *C)
{
C[blockIdx.x * blockDim.x + threadIdx.x] = A[blockIdx.x * blockDim.x + threadIdx.x] *
B[blockIdx.x * blockDim.x + threadIdx.x];
}
void array_mult_dev(double *d_A, double *d_B, double *d_C, int N)
{
int bSize;
int tSize = 32;
bSize = (N >> 5) + 1;
//while (res > 128)
{
//bSize = res >> 5; // 32 = 2 ^ 5
array_mult_kernel<<<bSize, tSize>>>(d_A, d_B, d_C);
}
cudaDeviceSynchronize();
}
void array_mult_host_naive(double *A, double *B, double *C, const int N)
{
for (int idx = 0; idx < N; idx++)
{
C[idx] = A[idx] * B[idx];
}
}
void array_mult_host_test_2(double *d_A, double *d_B, double *d_C, const int N)
{
double *buffA;
double *buffB;
double *buffC;
buffA = (double*)malloc(sizeof(double) * N);
buffB = (double*)malloc(sizeof(double) * N);
buffC = (double*)malloc(sizeof(double) * N);
cudaMemcpy(buffA, d_A, sizeof(double) * N, cudaMemcpyDeviceToHost);
cudaMemcpy(buffB, d_B, sizeof(double) * N, cudaMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
buffC[j] = buffA[j] * buffB[j];
}
cudaMemcpy(d_C, buffC, sizeof(double) * N, cudaMemcpyHostToDevice);
free(buffA);
free(buffB);
free(buffC);
}
void array_mult_host_test_3(double *h_A, double *h_B, double *h_C,
double *d_A, double *d_B, double *d_C,
const int N)
{
cudaMemcpy(h_A, d_A, sizeof(double) * N, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, sizeof(double) * N, cudaMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
h_C[j] = h_A[j] * h_B[j];
}
cudaMemcpy(d_C, h_C, sizeof(double) * N, cudaMemcpyHostToDevice);
}
void array_mult_host_hybr(double *d_A, double *d_B, double *d_C, int N)
{
int off = 0;
if (N >= 1024)
{
int bSize = N / 1024;
off = bSize * 1024;
N -= off;
array_mult_kernel<<<bSize, 32>>>(d_A, d_B, d_C);
}
array_mult_host_test_2(&d_A[off], &d_B[off], &d_C[off], N);
cudaDeviceSynchronize();
}
void initialData(double *ip,int size)
{
// generate different seed for random number
time_t t;
srand((unsigned int) time(&t));
for (int i=0; i<size; i++)
{
ip[i] = (double)( rand() & 0xFF )/10.0;
}
}
bool checkResult(double *h_res, double *d_res, int n)
{
double buff;
for (int i = 0; i < n; ++i)
{
cudaMemcpy(&buff, &d_res[i], sizeof(double), cudaMemcpyDeviceToHost);
if (abs(buff - h_res[i]) >= 1.E-12)
{
printf("Test failed on i=%d, host: %lf, dev: %lf\n", i, h_res[i], buff);
return false;
}
//printf("%lf, %lf\n", h_res[i], buff);
}
printf("Test pass\n");
return true;
}
void launchTest(int N, int repeat)
{
double tStart, tEnd, sum;
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *)malloc(sizeof(double) * N);
h_B = (double *)malloc(sizeof(double) * N);
h_C = (double *)malloc(sizeof(double) * N);
cudaMalloc((void **)&d_A, sizeof(double) * N);
cudaMalloc((void **)&d_B, sizeof(double) * N);
cudaMalloc((void **)&d_C, sizeof(double) * N);
printf("\nInitializing data (size=%d)\n", N);
initialData(h_A, N);
initialData(h_B, N);
cudaMemcpy(d_A, h_A, sizeof(double) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizeof(double) * N, cudaMemcpyHostToDevice);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_naive(h_A, h_B, h_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_naive", (sum / repeat * 1000));
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_test_3(h_A, h_B, h_C, d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_test_3", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_test_2(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_test_2", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_hybr(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_hybr", (sum / repeat * 1000));
array_mult_host_hybr(d_A, d_B, d_C, N);
array_mult_host_naive(h_A, h_B, h_C, N);
checkResult(h_C, d_C, N);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_dev(d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_dev", (sum / repeat * 1000));
// array_mult_host_naive(h_A, h_B, h_C, N);
// checkResult(h_C, d_C, N);
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main(int argc, char **argv)
{
for (int i = atoi(argv[1]); i < atoi(argv[2]); i *= 2)
{
launchTest(i, 10);
}
return(0);
} | code for sm_80
Function : _Z17array_mult_kernelPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0009 */
/*0070*/ IMAD.WIDE.U32 R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0009 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0009 */
/*00b0*/ DMUL R6, R2, R4 ; /* 0x0000000402067228 */
/* 0x004e0e0000000000 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <time.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code:%d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__global__ void array_mult_kernel(double *A, double *B, double *C)
{
C[blockIdx.x * blockDim.x + threadIdx.x] = A[blockIdx.x * blockDim.x + threadIdx.x] *
B[blockIdx.x * blockDim.x + threadIdx.x];
}
void array_mult_dev(double *d_A, double *d_B, double *d_C, int N)
{
int bSize;
int tSize = 32;
bSize = (N >> 5) + 1;
//while (res > 128)
{
//bSize = res >> 5; // 32 = 2 ^ 5
array_mult_kernel<<<bSize, tSize>>>(d_A, d_B, d_C);
}
cudaDeviceSynchronize();
}
void array_mult_host_naive(double *A, double *B, double *C, const int N)
{
for (int idx = 0; idx < N; idx++)
{
C[idx] = A[idx] * B[idx];
}
}
void array_mult_host_test_2(double *d_A, double *d_B, double *d_C, const int N)
{
double *buffA;
double *buffB;
double *buffC;
buffA = (double*)malloc(sizeof(double) * N);
buffB = (double*)malloc(sizeof(double) * N);
buffC = (double*)malloc(sizeof(double) * N);
cudaMemcpy(buffA, d_A, sizeof(double) * N, cudaMemcpyDeviceToHost);
cudaMemcpy(buffB, d_B, sizeof(double) * N, cudaMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
buffC[j] = buffA[j] * buffB[j];
}
cudaMemcpy(d_C, buffC, sizeof(double) * N, cudaMemcpyHostToDevice);
free(buffA);
free(buffB);
free(buffC);
}
void array_mult_host_test_3(double *h_A, double *h_B, double *h_C,
double *d_A, double *d_B, double *d_C,
const int N)
{
cudaMemcpy(h_A, d_A, sizeof(double) * N, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, sizeof(double) * N, cudaMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
h_C[j] = h_A[j] * h_B[j];
}
cudaMemcpy(d_C, h_C, sizeof(double) * N, cudaMemcpyHostToDevice);
}
void array_mult_host_hybr(double *d_A, double *d_B, double *d_C, int N)
{
int off = 0;
if (N >= 1024)
{
int bSize = N / 1024;
off = bSize * 1024;
N -= off;
array_mult_kernel<<<bSize, 32>>>(d_A, d_B, d_C);
}
array_mult_host_test_2(&d_A[off], &d_B[off], &d_C[off], N);
cudaDeviceSynchronize();
}
void initialData(double *ip,int size)
{
// generate different seed for random number
time_t t;
srand((unsigned int) time(&t));
for (int i=0; i<size; i++)
{
ip[i] = (double)( rand() & 0xFF )/10.0;
}
}
bool checkResult(double *h_res, double *d_res, int n)
{
double buff;
for (int i = 0; i < n; ++i)
{
cudaMemcpy(&buff, &d_res[i], sizeof(double), cudaMemcpyDeviceToHost);
if (abs(buff - h_res[i]) >= 1.E-12)
{
printf("Test failed on i=%d, host: %lf, dev: %lf\n", i, h_res[i], buff);
return false;
}
//printf("%lf, %lf\n", h_res[i], buff);
}
printf("Test pass\n");
return true;
}
void launchTest(int N, int repeat)
{
double tStart, tEnd, sum;
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *)malloc(sizeof(double) * N);
h_B = (double *)malloc(sizeof(double) * N);
h_C = (double *)malloc(sizeof(double) * N);
cudaMalloc((void **)&d_A, sizeof(double) * N);
cudaMalloc((void **)&d_B, sizeof(double) * N);
cudaMalloc((void **)&d_C, sizeof(double) * N);
printf("\nInitializing data (size=%d)\n", N);
initialData(h_A, N);
initialData(h_B, N);
cudaMemcpy(d_A, h_A, sizeof(double) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizeof(double) * N, cudaMemcpyHostToDevice);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_naive(h_A, h_B, h_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_naive", (sum / repeat * 1000));
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_test_3(h_A, h_B, h_C, d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_test_3", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_test_2(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_test_2", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_hybr(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_hybr", (sum / repeat * 1000));
array_mult_host_hybr(d_A, d_B, d_C, N);
array_mult_host_naive(h_A, h_B, h_C, N);
checkResult(h_C, d_C, N);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_dev(d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_dev", (sum / repeat * 1000));
// array_mult_host_naive(h_A, h_B, h_C, N);
// checkResult(h_C, d_C, N);
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main(int argc, char **argv)
{
for (int i = atoi(argv[1]); i < atoi(argv[2]); i *= 2)
{
launchTest(i, 10);
}
return(0);
} | .file "tmpxft_0002b742_00000000-6_sypha_solver_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3681:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z21array_mult_host_naivePdS_S_i
.type _Z21array_mult_host_naivePdS_S_i, @function
_Z21array_mult_host_naivePdS_S_i:
.LFB3671:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L7
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L9:
movsd (%rdi,%rax), %xmm0
mulsd (%rsi,%rax), %xmm0
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE3671:
.size _Z21array_mult_host_naivePdS_S_i, .-_Z21array_mult_host_naivePdS_S_i
.globl _Z22array_mult_host_test_2PdS_S_i
.type _Z22array_mult_host_test_2PdS_S_i, @function
_Z22array_mult_host_test_2PdS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movl %ecx, %r14d
movslq %ecx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L12
movl $0, %eax
.L13:
movsd 0(%r13,%rax), %xmm0
mulsd (%r12,%rax), %xmm0
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L13
.L12:
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z22array_mult_host_test_2PdS_S_i, .-_Z22array_mult_host_test_2PdS_S_i
.globl _Z22array_mult_host_test_3PdS_S_S_S_S_i
.type _Z22array_mult_host_test_3PdS_S_S_S_S_i, @function
_Z22array_mult_host_test_3PdS_S_S_S_S_i:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %rbp
movq %rcx, %rsi
movq %r8, %r14
movq %r9, 8(%rsp)
movl 80(%rsp), %r15d
movslq %r15d, %rbx
salq $3, %rbx
movl $2, %ecx
movq %rbx, %rdx
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L17
movl $0, %eax
.L18:
movsd (%r12,%rax), %xmm0
mulsd 0(%r13,%rax), %xmm0
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L18
.L17:
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z22array_mult_host_test_3PdS_S_S_S_S_i, .-_Z22array_mult_host_test_3PdS_S_S_S_S_i
.globl _Z11initialDataPdi
.type _Z11initialDataPdi, @function
_Z11initialDataPdi:
.LFB3675:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L21
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,8), %rbp
.L23:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L23
.L21:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3675:
.size _Z11initialDataPdi, .-_Z11initialDataPdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Test failed on i=%d, host: %lf, dev: %lf\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Test pass\n"
.text
.globl _Z11checkResultPdS_i
.type _Z11checkResultPdS_i, @function
_Z11checkResultPdS_i:
.LFB3676:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
testl %edx, %edx
jle .L29
movq %rdi, %r13
movq %rsi, %rbp
movslq %edx, %r12
movl $0, %ebx
movq %rsp, %r14
.L33:
movl $2, %ecx
movl $8, %edx
movq %rbp, %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movsd (%rsp), %xmm1
movsd 0(%r13,%rbx,8), %xmm2
movapd %xmm1, %xmm0
subsd %xmm2, %xmm0
andpd .LC2(%rip), %xmm0
comisd .LC3(%rip), %xmm0
jnb .L39
addq $1, %rbx
addq $8, %rbp
cmpq %r12, %rbx
jne .L33
.L29:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L28:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L40
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movapd %xmm2, %xmm0
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L28
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3676:
.size _Z11checkResultPdS_i, .-_Z11checkResultPdS_i
.globl _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
.type _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_, @function
_Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_:
.LFB3703:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17array_mult_kernelPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_, .-_Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
.globl _Z17array_mult_kernelPdS_S_
.type _Z17array_mult_kernelPdS_S_, @function
_Z17array_mult_kernelPdS_S_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z17array_mult_kernelPdS_S_, .-_Z17array_mult_kernelPdS_S_
.globl _Z20array_mult_host_hybrPdS_S_i
.type _Z20array_mult_host_hybrPdS_S_i, @function
_Z20array_mult_host_hybrPdS_S_i:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movl $0, %ebx
cmpl $1023, %ecx
jg .L54
.L50:
movslq %ebx, %rax
salq $3, %rax
leaq (%r14,%rax), %rdx
leaq 0(%r13,%rax), %rsi
leaq (%r12,%rax), %rdi
movl %ebp, %ecx
call _Z22array_mult_host_test_2PdS_S_i
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
leal 1023(%rcx), %ebx
testl %ecx, %ecx
cmovns %ecx, %ebx
movl %ebx, %edx
sarl $10, %edx
andl $-1024, %ebx
movl %ecx, %eax
sarl $31, %eax
shrl $22, %eax
addl %eax, %ebp
andl $1023, %ebp
subl %eax, %ebp
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl %edx, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
jmp .L50
.cfi_endproc
.LFE3674:
.size _Z20array_mult_host_hybrPdS_S_i, .-_Z20array_mult_host_hybrPdS_S_i
.section .rodata.str1.1
.LC7:
.string "\nInitializing data (size=%d)\n"
.LC9:
.string "array_mult_host_test_2"
.LC10:
.string "%30s - %12.9lf ms\n"
.LC11:
.string "array_mult_host_hybr"
.text
.globl _Z10launchTestii
.type _Z10launchTestii, @function
_Z10launchTestii:
.LFB3677:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r14, %rdi
call _Z11initialDataPdi
movl %ebp, %esi
movq %r15, %rdi
call _Z11initialDataPdi
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L56
movl $0, %ebx
movq $0x000000000, (%rsp)
.L57:
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z22array_mult_host_test_2PdS_S_i
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movl %ebx, %r12d
addl $1, %ebx
cmpl %ebx, %r13d
jne .L57
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movsd %xmm5, 24(%rsp)
divsd %xmm5, %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
movq $0x000000000, (%rsp)
.L58:
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z20array_mult_host_hybrPdS_S_i
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movl %ebx, %eax
addl $1, %ebx
cmpl %eax, %r12d
jne .L58
.L59:
movsd (%rsp), %xmm0
divsd 24(%rsp), %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC11(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z20array_mult_host_hybrPdS_S_i
movl %ebp, %ecx
movq 16(%rsp), %rbx
movq %rbx, %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z21array_mult_host_naivePdS_S_i
movl %ebp, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call _Z11checkResultPdS_i
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pxor %xmm7, %xmm7
cvtsi2sdl %r13d, %xmm7
movsd %xmm7, 24(%rsp)
pxor %xmm0, %xmm0
divsd %xmm7, %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq $0x000000000, (%rsp)
jmp .L59
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3677:
.size _Z10launchTestii, .-_Z10launchTestii
.globl main
.type main, @function
main:
.LFB3678:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L67
.L68:
movl $10, %esi
movl %ebx, %edi
call _Z10launchTestii
addl %ebx, %ebx
.L67:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl %eax, %ebx
jl .L68
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size main, .-main
.globl _Z14array_mult_devPdS_S_i
.type _Z14array_mult_devPdS_S_i, @function
_Z14array_mult_devPdS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $32, 20(%rsp)
movl $1, 24(%rsp)
sarl $5, %ecx
addl $1, %ecx
movl %ecx, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L71:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
jmp .L71
.cfi_endproc
.LFE3670:
.size _Z14array_mult_devPdS_S_i, .-_Z14array_mult_devPdS_S_i
.section .rodata.str1.1
.LC12:
.string "_Z17array_mult_kernelPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z17array_mult_kernelPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1076101120
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -2127697391
.long 1030854553
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <time.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code:%d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__global__ void array_mult_kernel(double *A, double *B, double *C)
{
C[blockIdx.x * blockDim.x + threadIdx.x] = A[blockIdx.x * blockDim.x + threadIdx.x] *
B[blockIdx.x * blockDim.x + threadIdx.x];
}
void array_mult_dev(double *d_A, double *d_B, double *d_C, int N)
{
int bSize;
int tSize = 32;
bSize = (N >> 5) + 1;
//while (res > 128)
{
//bSize = res >> 5; // 32 = 2 ^ 5
array_mult_kernel<<<bSize, tSize>>>(d_A, d_B, d_C);
}
cudaDeviceSynchronize();
}
void array_mult_host_naive(double *A, double *B, double *C, const int N)
{
for (int idx = 0; idx < N; idx++)
{
C[idx] = A[idx] * B[idx];
}
}
void array_mult_host_test_2(double *d_A, double *d_B, double *d_C, const int N)
{
double *buffA;
double *buffB;
double *buffC;
buffA = (double*)malloc(sizeof(double) * N);
buffB = (double*)malloc(sizeof(double) * N);
buffC = (double*)malloc(sizeof(double) * N);
cudaMemcpy(buffA, d_A, sizeof(double) * N, cudaMemcpyDeviceToHost);
cudaMemcpy(buffB, d_B, sizeof(double) * N, cudaMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
buffC[j] = buffA[j] * buffB[j];
}
cudaMemcpy(d_C, buffC, sizeof(double) * N, cudaMemcpyHostToDevice);
free(buffA);
free(buffB);
free(buffC);
}
void array_mult_host_test_3(double *h_A, double *h_B, double *h_C,
double *d_A, double *d_B, double *d_C,
const int N)
{
cudaMemcpy(h_A, d_A, sizeof(double) * N, cudaMemcpyDeviceToHost);
cudaMemcpy(h_B, d_B, sizeof(double) * N, cudaMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
h_C[j] = h_A[j] * h_B[j];
}
cudaMemcpy(d_C, h_C, sizeof(double) * N, cudaMemcpyHostToDevice);
}
void array_mult_host_hybr(double *d_A, double *d_B, double *d_C, int N)
{
int off = 0;
if (N >= 1024)
{
int bSize = N / 1024;
off = bSize * 1024;
N -= off;
array_mult_kernel<<<bSize, 32>>>(d_A, d_B, d_C);
}
array_mult_host_test_2(&d_A[off], &d_B[off], &d_C[off], N);
cudaDeviceSynchronize();
}
void initialData(double *ip,int size)
{
// generate different seed for random number
time_t t;
srand((unsigned int) time(&t));
for (int i=0; i<size; i++)
{
ip[i] = (double)( rand() & 0xFF )/10.0;
}
}
bool checkResult(double *h_res, double *d_res, int n)
{
double buff;
for (int i = 0; i < n; ++i)
{
cudaMemcpy(&buff, &d_res[i], sizeof(double), cudaMemcpyDeviceToHost);
if (abs(buff - h_res[i]) >= 1.E-12)
{
printf("Test failed on i=%d, host: %lf, dev: %lf\n", i, h_res[i], buff);
return false;
}
//printf("%lf, %lf\n", h_res[i], buff);
}
printf("Test pass\n");
return true;
}
void launchTest(int N, int repeat)
{
double tStart, tEnd, sum;
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *)malloc(sizeof(double) * N);
h_B = (double *)malloc(sizeof(double) * N);
h_C = (double *)malloc(sizeof(double) * N);
cudaMalloc((void **)&d_A, sizeof(double) * N);
cudaMalloc((void **)&d_B, sizeof(double) * N);
cudaMalloc((void **)&d_C, sizeof(double) * N);
printf("\nInitializing data (size=%d)\n", N);
initialData(h_A, N);
initialData(h_B, N);
cudaMemcpy(d_A, h_A, sizeof(double) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, sizeof(double) * N, cudaMemcpyHostToDevice);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_naive(h_A, h_B, h_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_naive", (sum / repeat * 1000));
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_test_3(h_A, h_B, h_C, d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_test_3", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_test_2(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_test_2", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_hybr(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_hybr", (sum / repeat * 1000));
array_mult_host_hybr(d_A, d_B, d_C, N);
array_mult_host_naive(h_A, h_B, h_C, N);
checkResult(h_C, d_C, N);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_dev(d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_dev", (sum / repeat * 1000));
// array_mult_host_naive(h_A, h_B, h_C, N);
// checkResult(h_C, d_C, N);
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main(int argc, char **argv)
{
for (int i = atoi(argv[1]); i < atoi(argv[2]); i *= 2)
{
launchTest(i, 10);
}
return(0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <time.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code:%d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__global__ void array_mult_kernel(double *A, double *B, double *C)
{
C[blockIdx.x * blockDim.x + threadIdx.x] = A[blockIdx.x * blockDim.x + threadIdx.x] *
B[blockIdx.x * blockDim.x + threadIdx.x];
}
void array_mult_dev(double *d_A, double *d_B, double *d_C, int N)
{
int bSize;
int tSize = 32;
bSize = (N >> 5) + 1;
//while (res > 128)
{
//bSize = res >> 5; // 32 = 2 ^ 5
array_mult_kernel<<<bSize, tSize>>>(d_A, d_B, d_C);
}
hipDeviceSynchronize();
}
void array_mult_host_naive(double *A, double *B, double *C, const int N)
{
for (int idx = 0; idx < N; idx++)
{
C[idx] = A[idx] * B[idx];
}
}
void array_mult_host_test_2(double *d_A, double *d_B, double *d_C, const int N)
{
double *buffA;
double *buffB;
double *buffC;
buffA = (double*)malloc(sizeof(double) * N);
buffB = (double*)malloc(sizeof(double) * N);
buffC = (double*)malloc(sizeof(double) * N);
hipMemcpy(buffA, d_A, sizeof(double) * N, hipMemcpyDeviceToHost);
hipMemcpy(buffB, d_B, sizeof(double) * N, hipMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
buffC[j] = buffA[j] * buffB[j];
}
hipMemcpy(d_C, buffC, sizeof(double) * N, hipMemcpyHostToDevice);
free(buffA);
free(buffB);
free(buffC);
}
void array_mult_host_test_3(double *h_A, double *h_B, double *h_C,
double *d_A, double *d_B, double *d_C,
const int N)
{
hipMemcpy(h_A, d_A, sizeof(double) * N, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, sizeof(double) * N, hipMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
h_C[j] = h_A[j] * h_B[j];
}
hipMemcpy(d_C, h_C, sizeof(double) * N, hipMemcpyHostToDevice);
}
void array_mult_host_hybr(double *d_A, double *d_B, double *d_C, int N)
{
int off = 0;
if (N >= 1024)
{
int bSize = N / 1024;
off = bSize * 1024;
N -= off;
array_mult_kernel<<<bSize, 32>>>(d_A, d_B, d_C);
}
array_mult_host_test_2(&d_A[off], &d_B[off], &d_C[off], N);
hipDeviceSynchronize();
}
void initialData(double *ip,int size)
{
// generate different seed for random number
time_t t;
srand((unsigned int) time(&t));
for (int i=0; i<size; i++)
{
ip[i] = (double)( rand() & 0xFF )/10.0;
}
}
bool checkResult(double *h_res, double *d_res, int n)
{
double buff;
for (int i = 0; i < n; ++i)
{
hipMemcpy(&buff, &d_res[i], sizeof(double), hipMemcpyDeviceToHost);
if (abs(buff - h_res[i]) >= 1.E-12)
{
printf("Test failed on i=%d, host: %lf, dev: %lf\n", i, h_res[i], buff);
return false;
}
//printf("%lf, %lf\n", h_res[i], buff);
}
printf("Test pass\n");
return true;
}
void launchTest(int N, int repeat)
{
double tStart, tEnd, sum;
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *)malloc(sizeof(double) * N);
h_B = (double *)malloc(sizeof(double) * N);
h_C = (double *)malloc(sizeof(double) * N);
hipMalloc((void **)&d_A, sizeof(double) * N);
hipMalloc((void **)&d_B, sizeof(double) * N);
hipMalloc((void **)&d_C, sizeof(double) * N);
printf("\nInitializing data (size=%d)\n", N);
initialData(h_A, N);
initialData(h_B, N);
hipMemcpy(d_A, h_A, sizeof(double) * N, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizeof(double) * N, hipMemcpyHostToDevice);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_naive(h_A, h_B, h_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_naive", (sum / repeat * 1000));
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_test_3(h_A, h_B, h_C, d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_test_3", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_test_2(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_test_2", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_hybr(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_hybr", (sum / repeat * 1000));
array_mult_host_hybr(d_A, d_B, d_C, N);
array_mult_host_naive(h_A, h_B, h_C, N);
checkResult(h_C, d_C, N);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_dev(d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_dev", (sum / repeat * 1000));
// array_mult_host_naive(h_A, h_B, h_C, N);
// checkResult(h_C, d_C, N);
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main(int argc, char **argv)
{
for (int i = atoi(argv[1]); i < atoi(argv[2]); i *= 2)
{
launchTest(i, 10);
}
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <time.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code:%d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__global__ void array_mult_kernel(double *A, double *B, double *C)
{
C[blockIdx.x * blockDim.x + threadIdx.x] = A[blockIdx.x * blockDim.x + threadIdx.x] *
B[blockIdx.x * blockDim.x + threadIdx.x];
}
void array_mult_dev(double *d_A, double *d_B, double *d_C, int N)
{
int bSize;
int tSize = 32;
bSize = (N >> 5) + 1;
//while (res > 128)
{
//bSize = res >> 5; // 32 = 2 ^ 5
array_mult_kernel<<<bSize, tSize>>>(d_A, d_B, d_C);
}
hipDeviceSynchronize();
}
void array_mult_host_naive(double *A, double *B, double *C, const int N)
{
for (int idx = 0; idx < N; idx++)
{
C[idx] = A[idx] * B[idx];
}
}
void array_mult_host_test_2(double *d_A, double *d_B, double *d_C, const int N)
{
double *buffA;
double *buffB;
double *buffC;
buffA = (double*)malloc(sizeof(double) * N);
buffB = (double*)malloc(sizeof(double) * N);
buffC = (double*)malloc(sizeof(double) * N);
hipMemcpy(buffA, d_A, sizeof(double) * N, hipMemcpyDeviceToHost);
hipMemcpy(buffB, d_B, sizeof(double) * N, hipMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
buffC[j] = buffA[j] * buffB[j];
}
hipMemcpy(d_C, buffC, sizeof(double) * N, hipMemcpyHostToDevice);
free(buffA);
free(buffB);
free(buffC);
}
void array_mult_host_test_3(double *h_A, double *h_B, double *h_C,
double *d_A, double *d_B, double *d_C,
const int N)
{
hipMemcpy(h_A, d_A, sizeof(double) * N, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, sizeof(double) * N, hipMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
h_C[j] = h_A[j] * h_B[j];
}
hipMemcpy(d_C, h_C, sizeof(double) * N, hipMemcpyHostToDevice);
}
void array_mult_host_hybr(double *d_A, double *d_B, double *d_C, int N)
{
int off = 0;
if (N >= 1024)
{
int bSize = N / 1024;
off = bSize * 1024;
N -= off;
array_mult_kernel<<<bSize, 32>>>(d_A, d_B, d_C);
}
array_mult_host_test_2(&d_A[off], &d_B[off], &d_C[off], N);
hipDeviceSynchronize();
}
void initialData(double *ip,int size)
{
// generate different seed for random number
time_t t;
srand((unsigned int) time(&t));
for (int i=0; i<size; i++)
{
ip[i] = (double)( rand() & 0xFF )/10.0;
}
}
bool checkResult(double *h_res, double *d_res, int n)
{
double buff;
for (int i = 0; i < n; ++i)
{
hipMemcpy(&buff, &d_res[i], sizeof(double), hipMemcpyDeviceToHost);
if (abs(buff - h_res[i]) >= 1.E-12)
{
printf("Test failed on i=%d, host: %lf, dev: %lf\n", i, h_res[i], buff);
return false;
}
//printf("%lf, %lf\n", h_res[i], buff);
}
printf("Test pass\n");
return true;
}
void launchTest(int N, int repeat)
{
double tStart, tEnd, sum;
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *)malloc(sizeof(double) * N);
h_B = (double *)malloc(sizeof(double) * N);
h_C = (double *)malloc(sizeof(double) * N);
hipMalloc((void **)&d_A, sizeof(double) * N);
hipMalloc((void **)&d_B, sizeof(double) * N);
hipMalloc((void **)&d_C, sizeof(double) * N);
printf("\nInitializing data (size=%d)\n", N);
initialData(h_A, N);
initialData(h_B, N);
hipMemcpy(d_A, h_A, sizeof(double) * N, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizeof(double) * N, hipMemcpyHostToDevice);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_naive(h_A, h_B, h_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_naive", (sum / repeat * 1000));
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_test_3(h_A, h_B, h_C, d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_test_3", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_test_2(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_test_2", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_hybr(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_hybr", (sum / repeat * 1000));
array_mult_host_hybr(d_A, d_B, d_C, N);
array_mult_host_naive(h_A, h_B, h_C, N);
checkResult(h_C, d_C, N);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_dev(d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_dev", (sum / repeat * 1000));
// array_mult_host_naive(h_A, h_B, h_C, N);
// checkResult(h_C, d_C, N);
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main(int argc, char **argv)
{
for (int i = atoi(argv[1]); i < atoi(argv[2]); i *= 2)
{
launchTest(i, 10);
}
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17array_mult_kernelPdS_S_
.globl _Z17array_mult_kernelPdS_S_
.p2align 8
.type _Z17array_mult_kernelPdS_S_,@function
_Z17array_mult_kernelPdS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17array_mult_kernelPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17array_mult_kernelPdS_S_, .Lfunc_end0-_Z17array_mult_kernelPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17array_mult_kernelPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17array_mult_kernelPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
#include <time.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code:%d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
__global__ void array_mult_kernel(double *A, double *B, double *C)
{
C[blockIdx.x * blockDim.x + threadIdx.x] = A[blockIdx.x * blockDim.x + threadIdx.x] *
B[blockIdx.x * blockDim.x + threadIdx.x];
}
void array_mult_dev(double *d_A, double *d_B, double *d_C, int N)
{
int bSize;
int tSize = 32;
bSize = (N >> 5) + 1;
//while (res > 128)
{
//bSize = res >> 5; // 32 = 2 ^ 5
array_mult_kernel<<<bSize, tSize>>>(d_A, d_B, d_C);
}
hipDeviceSynchronize();
}
void array_mult_host_naive(double *A, double *B, double *C, const int N)
{
for (int idx = 0; idx < N; idx++)
{
C[idx] = A[idx] * B[idx];
}
}
void array_mult_host_test_2(double *d_A, double *d_B, double *d_C, const int N)
{
double *buffA;
double *buffB;
double *buffC;
buffA = (double*)malloc(sizeof(double) * N);
buffB = (double*)malloc(sizeof(double) * N);
buffC = (double*)malloc(sizeof(double) * N);
hipMemcpy(buffA, d_A, sizeof(double) * N, hipMemcpyDeviceToHost);
hipMemcpy(buffB, d_B, sizeof(double) * N, hipMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
buffC[j] = buffA[j] * buffB[j];
}
hipMemcpy(d_C, buffC, sizeof(double) * N, hipMemcpyHostToDevice);
free(buffA);
free(buffB);
free(buffC);
}
void array_mult_host_test_3(double *h_A, double *h_B, double *h_C,
double *d_A, double *d_B, double *d_C,
const int N)
{
hipMemcpy(h_A, d_A, sizeof(double) * N, hipMemcpyDeviceToHost);
hipMemcpy(h_B, d_B, sizeof(double) * N, hipMemcpyDeviceToHost);
for (int j = 0; j < N; ++j)
{
h_C[j] = h_A[j] * h_B[j];
}
hipMemcpy(d_C, h_C, sizeof(double) * N, hipMemcpyHostToDevice);
}
void array_mult_host_hybr(double *d_A, double *d_B, double *d_C, int N)
{
int off = 0;
if (N >= 1024)
{
int bSize = N / 1024;
off = bSize * 1024;
N -= off;
array_mult_kernel<<<bSize, 32>>>(d_A, d_B, d_C);
}
array_mult_host_test_2(&d_A[off], &d_B[off], &d_C[off], N);
hipDeviceSynchronize();
}
void initialData(double *ip,int size)
{
// generate different seed for random number
time_t t;
srand((unsigned int) time(&t));
for (int i=0; i<size; i++)
{
ip[i] = (double)( rand() & 0xFF )/10.0;
}
}
bool checkResult(double *h_res, double *d_res, int n)
{
double buff;
for (int i = 0; i < n; ++i)
{
hipMemcpy(&buff, &d_res[i], sizeof(double), hipMemcpyDeviceToHost);
if (abs(buff - h_res[i]) >= 1.E-12)
{
printf("Test failed on i=%d, host: %lf, dev: %lf\n", i, h_res[i], buff);
return false;
}
//printf("%lf, %lf\n", h_res[i], buff);
}
printf("Test pass\n");
return true;
}
void launchTest(int N, int repeat)
{
double tStart, tEnd, sum;
double *h_A, *h_B, *h_C;
double *d_A, *d_B, *d_C;
h_A = (double *)malloc(sizeof(double) * N);
h_B = (double *)malloc(sizeof(double) * N);
h_C = (double *)malloc(sizeof(double) * N);
hipMalloc((void **)&d_A, sizeof(double) * N);
hipMalloc((void **)&d_B, sizeof(double) * N);
hipMalloc((void **)&d_C, sizeof(double) * N);
printf("\nInitializing data (size=%d)\n", N);
initialData(h_A, N);
initialData(h_B, N);
hipMemcpy(d_A, h_A, sizeof(double) * N, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, sizeof(double) * N, hipMemcpyHostToDevice);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_naive(h_A, h_B, h_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_naive", (sum / repeat * 1000));
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_host_test_3(h_A, h_B, h_C, d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_host_test_3", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_test_2(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_test_2", (sum / repeat * 1000));
sum = 0;
for (int i = 0; i < repeat; ++i)
{
tStart = cpuSecond();
array_mult_host_hybr(d_A, d_B, d_C, N);
tEnd = cpuSecond();
sum += (tEnd - tStart);
}
printf("%30s - %12.9lf ms\n", "array_mult_host_hybr", (sum / repeat * 1000));
array_mult_host_hybr(d_A, d_B, d_C, N);
array_mult_host_naive(h_A, h_B, h_C, N);
checkResult(h_C, d_C, N);
// sum = 0;
// for (int i = 0; i < repeat; ++i)
// {
// tStart = cpuSecond();
// array_mult_dev(d_A, d_B, d_C, N);
// tEnd = cpuSecond();
// sum += (tEnd - tStart);
// }
// printf("%30s - %12.9lf ms\n", "array_mult_dev", (sum / repeat * 1000));
// array_mult_host_naive(h_A, h_B, h_C, N);
// checkResult(h_C, d_C, N);
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main(int argc, char **argv)
{
for (int i = atoi(argv[1]); i < atoi(argv[2]); i *= 2)
{
launchTest(i, 10);
}
return(0);
} | .text
.file "sypha_solver_test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z32__device_stub__array_mult_kernelPdS_S_ # -- Begin function _Z32__device_stub__array_mult_kernelPdS_S_
.p2align 4, 0x90
.type _Z32__device_stub__array_mult_kernelPdS_S_,@function
_Z32__device_stub__array_mult_kernelPdS_S_: # @_Z32__device_stub__array_mult_kernelPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17array_mult_kernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z32__device_stub__array_mult_kernelPdS_S_, .Lfunc_end1-_Z32__device_stub__array_mult_kernelPdS_S_
.cfi_endproc
# -- End function
.globl _Z14array_mult_devPdS_S_i # -- Begin function _Z14array_mult_devPdS_S_i
.p2align 4, 0x90
.type _Z14array_mult_devPdS_S_i,@function
_Z14array_mult_devPdS_S_i: # @_Z14array_mult_devPdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $ecx killed $ecx def $rcx
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
sarl $5, %ecx
leal 1(%rcx), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17array_mult_kernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z14array_mult_devPdS_S_i, .Lfunc_end2-_Z14array_mult_devPdS_S_i
.cfi_endproc
# -- End function
.globl _Z21array_mult_host_naivePdS_S_i # -- Begin function _Z21array_mult_host_naivePdS_S_i
.p2align 4, 0x90
.type _Z21array_mult_host_naivePdS_S_i,@function
_Z21array_mult_host_naivePdS_S_i: # @_Z21array_mult_host_naivePdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%rsi,%rcx,8), %xmm0
movsd %xmm0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z21array_mult_host_naivePdS_S_i, .Lfunc_end3-_Z21array_mult_host_naivePdS_S_i
.cfi_endproc
# -- End function
.globl _Z22array_mult_host_test_2PdS_S_i # -- Begin function _Z22array_mult_host_test_2PdS_S_i
.p2align 4, 0x90
.type _Z22array_mult_host_test_2PdS_S_i,@function
_Z22array_mult_host_test_2PdS_S_i: # @_Z22array_mult_host_test_2PdS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl %ecx, 4(%rsp) # 4-byte Spill
movslq %ecx, %rbp
leaq (,%rbp,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebp, %ebp
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl 4(%rsp), %eax # 4-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r15,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r12,%rcx,8), %xmm0
movsd %xmm0, (%r13,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq 16(%rsp), %rdi # 8-byte Reload
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end4:
.size _Z22array_mult_host_test_2PdS_S_i, .Lfunc_end4-_Z22array_mult_host_test_2PdS_S_i
.cfi_endproc
# -- End function
.globl _Z22array_mult_host_test_3PdS_S_S_S_S_i # -- Begin function _Z22array_mult_host_test_3PdS_S_S_S_S_i
.p2align 4, 0x90
.type _Z22array_mult_host_test_3PdS_S_S_S_S_i,@function
_Z22array_mult_host_test_3PdS_S_S_S_S_i: # @_Z22array_mult_host_test_3PdS_S_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, (%rsp) # 8-byte Spill
movq %r8, %rbp
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r13
movslq 64(%rsp), %rbx
leaq (,%rbx,8), %r15
movq %rcx, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testq %rbx, %rbx
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r13,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r12,%rcx,8), %xmm0
movsd %xmm0, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq (%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end5:
.size _Z22array_mult_host_test_3PdS_S_S_S_S_i, .Lfunc_end5-_Z22array_mult_host_test_3PdS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20array_mult_host_hybrPdS_S_i # -- Begin function _Z20array_mult_host_hybrPdS_S_i
.p2align 4, 0x90
.type _Z20array_mult_host_hybrPdS_S_i,@function
_Z20array_mult_host_hybrPdS_S_i: # @_Z20array_mult_host_hybrPdS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cmpl $1024, %ecx # imm = 0x400
jl .LBB6_1
# %bb.2:
movl %ecx, %edi
shrl $10, %edi
movl %ecx, %r12d
movl %ecx, %ebp
andl $2147482624, %ebp # imm = 0x7FFFFC00
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17array_mult_kernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
movl %r12d, %ecx
andl $1023, %ecx # imm = 0x3FF
movl %ebp, %eax
jmp .LBB6_5
.LBB6_1:
xorl %eax, %eax
.LBB6_5:
leaq (%r15,%rax,8), %rdi
leaq (%r14,%rax,8), %rsi
leaq (%rbx,%rax,8), %rdx
callq _Z22array_mult_host_test_2PdS_S_i
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z20array_mult_host_hybrPdS_S_i, .Lfunc_end6-_Z20array_mult_host_hybrPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11initialDataPdi
.LCPI7_0:
.quad 0x4024000000000000 # double 10
.text
.globl _Z11initialDataPdi
.p2align 4, 0x90
.type _Z11initialDataPdi,@function
_Z11initialDataPdi: # @_Z11initialDataPdi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB7_2
.LBB7_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z11initialDataPdi, .Lfunc_end7-_Z11initialDataPdi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPdS_i
.LCPI8_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI8_1:
.quad 0x3d719799812dea11 # double 9.9999999999999998E-13
.text
.globl _Z11checkResultPdS_i
.p2align 4, 0x90
.type _Z11checkResultPdS_i,@function
_Z11checkResultPdS_i: # @_Z11checkResultPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
setle %bpl
jle .LBB8_8
# %bb.1: # %.lr.ph.preheader
movl %edx, %r12d
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movsd (%rsp), %xmm1 # xmm1 = mem[0],zero
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, %xmm2
subsd %xmm0, %xmm2
andpd .LCPI8_0(%rip), %xmm2
xorl %r15d, %r15d
ucomisd .LCPI8_1(%rip), %xmm2
jae .LBB8_6
# %bb.2: # %.lr.ph33.preheader
movl %r12d, %r13d
addq $8, %rbx
leaq -1(%r13), %rbp
xorl %r15d, %r15d
movq %rsp, %r12
.p2align 4, 0x90
.LBB8_3: # %.lr.ph33
# =>This Inner Loop Header: Depth=1
cmpq %r15, %rbp
je .LBB8_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB8_3 Depth=1
movl $8, %edx
movq %r12, %rdi
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
movsd (%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 8(%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, %xmm2
subsd %xmm0, %xmm2
andpd .LCPI8_0(%rip), %xmm2
addq $8, %rbx
incq %r15
ucomisd .LCPI8_1(%rip), %xmm2
jb .LBB8_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %r13, %r15
setae %bpl
.LBB8_6:
movl $.L.str, %edi
movl %r15d, %esi
movb $2, %al
callq printf
jmp .LBB8_9
.LBB8_7: # %.critedge.loopexit
incq %r15
cmpq %r13, %r15
setae %bpl
.LBB8_8: # %.critedge
movl $.Lstr, %edi
callq puts@PLT
.LBB8_9:
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z11checkResultPdS_i, .Lfunc_end8-_Z11checkResultPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10launchTestii
.LCPI9_0:
.quad 0x4024000000000000 # double 10
.LCPI9_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI9_2:
.quad 0x408f400000000000 # double 1000
.LCPI9_4:
.quad 0x3d719799812dea11 # double 9.9999999999999998E-13
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI9_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z10launchTestii
.p2align 4, 0x90
.type _Z10launchTestii,@function
_Z10launchTestii: # @_Z10launchTestii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
movslq %edi, %r12
leaq (,%r12,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r15, 8(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
movl %ebp, %r15d
testl %r12d, %r12d
jle .LBB9_6
# %bb.1: # %.lr.ph.preheader.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB9_2
# %bb.3: # %_Z11initialDataPdi.exit
leaq 16(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
movq 56(%rsp), %r13 # 8-byte Reload
jle .LBB9_7
# %bb.4: # %.lr.ph.preheader.i45
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_5: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movsd %xmm0, (%r13,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB9_5
jmp .LBB9_7
.LBB9_6: # %_Z11initialDataPdi.exit51.critedge
leaq 16(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
movq 56(%rsp), %r13 # 8-byte Reload
.LBB9_7: # %_Z11initialDataPdi.exit51
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq 8(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
testl %r14d, %r14d
jle .LBB9_10
# %bb.8: # %.lr.ph
leaq 16(%rsp), %r13
movl %r14d, %r12d
.p2align 4, 0x90
.LBB9_9: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 24(%rsp), %xmm2
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 72(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebp, %ecx
callq _Z22array_mult_host_test_2PdS_S_i
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI9_1(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 72(%rsp), %xmm1 # 8-byte Folded Reload
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
decl %r12d
jne .LBB9_9
.LBB9_10: # %._crit_edge
xorps %xmm1, %xmm1
cvtsi2sd %r14d, %xmm1
movsd %xmm1, 80(%rsp) # 8-byte Spill
divsd %xmm1, %xmm0
mulsd .LCPI9_2(%rip), %xmm0
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movb $1, %al
callq printf
testl %r14d, %r14d
xorpd %xmm0, %xmm0
jle .LBB9_13
# %bb.11: # %.lr.ph72
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB9_12: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 24(%rsp), %xmm2
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 72(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebp, %ecx
callq _Z20array_mult_host_hybrPdS_S_i
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI9_1(%rip), %xmm1
addsd %xmm0, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 72(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm1, %xmm0
decl %r14d
jne .LBB9_12
.LBB9_13: # %._crit_edge73
divsd 80(%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI9_2(%rip), %xmm0
movl $.L.str.3, %edi
movl $.L.str.5, %esi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebp, %ecx
callq _Z20array_mult_host_hybrPdS_S_i
testl %ebp, %ebp
movq 56(%rsp), %r14 # 8-byte Reload
movq 64(%rsp), %rcx # 8-byte Reload
jle .LBB9_16
# %bb.14: # %.lr.ph.preheader.i52
xorl %eax, %eax
.p2align 4, 0x90
.LBB9_15: # %.lr.ph.i54
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%rcx,%rax,8)
incq %rax
cmpq %rax, %r15
jne .LBB9_15
.LBB9_16: # %_Z21array_mult_host_naivePdS_S_i.exit
testl %ebp, %ebp
jle .LBB9_21
# %bb.17: # %.lr.ph.preheader.i58
movq 32(%rsp), %r13
xorl %r12d, %r12d
leaq 16(%rsp), %rbp
.p2align 4, 0x90
.LBB9_18: # %.lr.ph.i60
# =>This Inner Loop Header: Depth=1
movl $8, %edx
movq %rbp, %rdi
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
movsd 16(%rsp), %xmm1 # xmm1 = mem[0],zero
movq 64(%rsp), %rax # 8-byte Reload
movsd (%rax,%r12,8), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, %xmm2
subsd %xmm0, %xmm2
andpd .LCPI9_3(%rip), %xmm2
ucomisd .LCPI9_4(%rip), %xmm2
jae .LBB9_19
# %bb.20: # in Loop: Header=BB9_18 Depth=1
incq %r12
addq $8, %r13
cmpq %r12, %r15
jne .LBB9_18
.LBB9_21: # %.critedge.i
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB9_22
.LBB9_19:
movl $.L.str, %edi
movl %r12d, %esi
movb $2, %al
callq printf
.LBB9_22: # %_Z11checkResultPdS_i.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z10launchTestii, .Lfunc_end9-_Z10launchTestii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.p2align 4, 0x90
.LBB10_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl %eax, %r14d
jge .LBB10_3
# %bb.1: # %.lr.ph
# in Loop: Header=BB10_2 Depth=1
movl %r14d, %edi
movl $10, %esi
callq _Z10launchTestii
addl %r14d, %r14d
jmp .LBB10_2
.LBB10_3: # %._crit_edge
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17array_mult_kernelPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17array_mult_kernelPdS_S_,@object # @_Z17array_mult_kernelPdS_S_
.section .rodata,"a",@progbits
.globl _Z17array_mult_kernelPdS_S_
.p2align 3, 0x0
_Z17array_mult_kernelPdS_S_:
.quad _Z32__device_stub__array_mult_kernelPdS_S_
.size _Z17array_mult_kernelPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Test failed on i=%d, host: %lf, dev: %lf\n"
.size .L.str, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nInitializing data (size=%d)\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%30s - %12.9lf ms\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "array_mult_host_test_2"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "array_mult_host_hybr"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17array_mult_kernelPdS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test pass"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__array_mult_kernelPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17array_mult_kernelPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17array_mult_kernelPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0009 */
/*0070*/ IMAD.WIDE.U32 R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0009 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0009 */
/*00b0*/ DMUL R6, R2, R4 ; /* 0x0000000402067228 */
/* 0x004e0e0000000000 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17array_mult_kernelPdS_S_
.globl _Z17array_mult_kernelPdS_S_
.p2align 8
.type _Z17array_mult_kernelPdS_S_,@function
_Z17array_mult_kernelPdS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17array_mult_kernelPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17array_mult_kernelPdS_S_, .Lfunc_end0-_Z17array_mult_kernelPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17array_mult_kernelPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17array_mult_kernelPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b742_00000000-6_sypha_solver_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3681:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z21array_mult_host_naivePdS_S_i
.type _Z21array_mult_host_naivePdS_S_i, @function
_Z21array_mult_host_naivePdS_S_i:
.LFB3671:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L7
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L9:
movsd (%rdi,%rax), %xmm0
mulsd (%rsi,%rax), %xmm0
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE3671:
.size _Z21array_mult_host_naivePdS_S_i, .-_Z21array_mult_host_naivePdS_S_i
.globl _Z22array_mult_host_test_2PdS_S_i
.type _Z22array_mult_host_test_2PdS_S_i, @function
_Z22array_mult_host_test_2PdS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movl %ecx, %r14d
movslq %ecx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %r14d, %r14d
jle .L12
movl $0, %eax
.L13:
movsd 0(%r13,%rax), %xmm0
mulsd (%r12,%rax), %xmm0
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L13
.L12:
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z22array_mult_host_test_2PdS_S_i, .-_Z22array_mult_host_test_2PdS_S_i
.globl _Z22array_mult_host_test_3PdS_S_S_S_S_i
.type _Z22array_mult_host_test_3PdS_S_S_S_S_i, @function
_Z22array_mult_host_test_3PdS_S_S_S_S_i:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %rbp
movq %rcx, %rsi
movq %r8, %r14
movq %r9, 8(%rsp)
movl 80(%rsp), %r15d
movslq %r15d, %rbx
salq $3, %rbx
movl $2, %ecx
movq %rbx, %rdx
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L17
movl $0, %eax
.L18:
movsd (%r12,%rax), %xmm0
mulsd 0(%r13,%rax), %xmm0
movsd %xmm0, 0(%rbp,%rax)
addq $8, %rax
cmpq %rax, %rbx
jne .L18
.L17:
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _Z22array_mult_host_test_3PdS_S_S_S_S_i, .-_Z22array_mult_host_test_3PdS_S_S_S_S_i
.globl _Z11initialDataPdi
.type _Z11initialDataPdi, @function
_Z11initialDataPdi:
.LFB3675:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L21
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,8), %rbp
.L23:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L23
.L21:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3675:
.size _Z11initialDataPdi, .-_Z11initialDataPdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Test failed on i=%d, host: %lf, dev: %lf\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Test pass\n"
.text
.globl _Z11checkResultPdS_i
.type _Z11checkResultPdS_i, @function
_Z11checkResultPdS_i:
.LFB3676:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
testl %edx, %edx
jle .L29
movq %rdi, %r13
movq %rsi, %rbp
movslq %edx, %r12
movl $0, %ebx
movq %rsp, %r14
.L33:
movl $2, %ecx
movl $8, %edx
movq %rbp, %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movsd (%rsp), %xmm1
movsd 0(%r13,%rbx,8), %xmm2
movapd %xmm1, %xmm0
subsd %xmm2, %xmm0
andpd .LC2(%rip), %xmm0
comisd .LC3(%rip), %xmm0
jnb .L39
addq $1, %rbx
addq $8, %rbp
cmpq %r12, %rbx
jne .L33
.L29:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L28:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L40
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movapd %xmm2, %xmm0
movl %ebx, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L28
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3676:
.size _Z11checkResultPdS_i, .-_Z11checkResultPdS_i
.globl _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
.type _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_, @function
_Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_:
.LFB3703:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17array_mult_kernelPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_, .-_Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
.globl _Z17array_mult_kernelPdS_S_
.type _Z17array_mult_kernelPdS_S_, @function
_Z17array_mult_kernelPdS_S_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z17array_mult_kernelPdS_S_, .-_Z17array_mult_kernelPdS_S_
.globl _Z20array_mult_host_hybrPdS_S_i
.type _Z20array_mult_host_hybrPdS_S_i, @function
_Z20array_mult_host_hybrPdS_S_i:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movl $0, %ebx
cmpl $1023, %ecx
jg .L54
.L50:
movslq %ebx, %rax
salq $3, %rax
leaq (%r14,%rax), %rdx
leaq 0(%r13,%rax), %rsi
leaq (%r12,%rax), %rdi
movl %ebp, %ecx
call _Z22array_mult_host_test_2PdS_S_i
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
leal 1023(%rcx), %ebx
testl %ecx, %ecx
cmovns %ecx, %ebx
movl %ebx, %edx
sarl $10, %edx
andl $-1024, %ebx
movl %ecx, %eax
sarl $31, %eax
shrl $22, %eax
addl %eax, %ebp
andl $1023, %ebp
subl %eax, %ebp
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl %edx, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
jmp .L50
.cfi_endproc
.LFE3674:
.size _Z20array_mult_host_hybrPdS_S_i, .-_Z20array_mult_host_hybrPdS_S_i
.section .rodata.str1.1
.LC7:
.string "\nInitializing data (size=%d)\n"
.LC9:
.string "array_mult_host_test_2"
.LC10:
.string "%30s - %12.9lf ms\n"
.LC11:
.string "array_mult_host_hybr"
.text
.globl _Z10launchTestii
.type _Z10launchTestii, @function
_Z10launchTestii:
.LFB3677:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r14, %rdi
call _Z11initialDataPdi
movl %ebp, %esi
movq %r15, %rdi
call _Z11initialDataPdi
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L56
movl $0, %ebx
movq $0x000000000, (%rsp)
.L57:
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z22array_mult_host_test_2PdS_S_i
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movl %ebx, %r12d
addl $1, %ebx
cmpl %ebx, %r13d
jne .L57
pxor %xmm5, %xmm5
cvtsi2sdl %ebx, %xmm5
movsd %xmm5, 24(%rsp)
divsd %xmm5, %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
movq $0x000000000, (%rsp)
.L58:
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z20array_mult_host_hybrPdS_S_i
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movl %ebx, %eax
addl $1, %ebx
cmpl %eax, %r12d
jne .L58
.L59:
movsd (%rsp), %xmm0
divsd 24(%rsp), %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC11(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z20array_mult_host_hybrPdS_S_i
movl %ebp, %ecx
movq 16(%rsp), %rbx
movq %rbx, %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z21array_mult_host_naivePdS_S_i
movl %ebp, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call _Z11checkResultPdS_i
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pxor %xmm7, %xmm7
cvtsi2sdl %r13d, %xmm7
movsd %xmm7, 24(%rsp)
pxor %xmm0, %xmm0
divsd %xmm7, %xmm0
mulsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq $0x000000000, (%rsp)
jmp .L59
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3677:
.size _Z10launchTestii, .-_Z10launchTestii
.globl main
.type main, @function
main:
.LFB3678:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L67
.L68:
movl $10, %esi
movl %ebx, %edi
call _Z10launchTestii
addl %ebx, %ebx
.L67:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl %eax, %ebx
jl .L68
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size main, .-main
.globl _Z14array_mult_devPdS_S_i
.type _Z14array_mult_devPdS_S_i, @function
_Z14array_mult_devPdS_S_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $32, 20(%rsp)
movl $1, 24(%rsp)
sarl $5, %ecx
addl $1, %ecx
movl %ecx, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L71:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z41__device_stub__Z17array_mult_kernelPdS_S_PdS_S_
jmp .L71
.cfi_endproc
.LFE3670:
.size _Z14array_mult_devPdS_S_i, .-_Z14array_mult_devPdS_S_i
.section .rodata.str1.1
.LC12:
.string "_Z17array_mult_kernelPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z17array_mult_kernelPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1076101120
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -2127697391
.long 1030854553
.align 8
.LC8:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sypha_solver_test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z32__device_stub__array_mult_kernelPdS_S_ # -- Begin function _Z32__device_stub__array_mult_kernelPdS_S_
.p2align 4, 0x90
.type _Z32__device_stub__array_mult_kernelPdS_S_,@function
_Z32__device_stub__array_mult_kernelPdS_S_: # @_Z32__device_stub__array_mult_kernelPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17array_mult_kernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z32__device_stub__array_mult_kernelPdS_S_, .Lfunc_end1-_Z32__device_stub__array_mult_kernelPdS_S_
.cfi_endproc
# -- End function
.globl _Z14array_mult_devPdS_S_i # -- Begin function _Z14array_mult_devPdS_S_i
.p2align 4, 0x90
.type _Z14array_mult_devPdS_S_i,@function
_Z14array_mult_devPdS_S_i: # @_Z14array_mult_devPdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $ecx killed $ecx def $rcx
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
sarl $5, %ecx
leal 1(%rcx), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17array_mult_kernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z14array_mult_devPdS_S_i, .Lfunc_end2-_Z14array_mult_devPdS_S_i
.cfi_endproc
# -- End function
.globl _Z21array_mult_host_naivePdS_S_i # -- Begin function _Z21array_mult_host_naivePdS_S_i
.p2align 4, 0x90
.type _Z21array_mult_host_naivePdS_S_i,@function
_Z21array_mult_host_naivePdS_S_i: # @_Z21array_mult_host_naivePdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%rsi,%rcx,8), %xmm0
movsd %xmm0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z21array_mult_host_naivePdS_S_i, .Lfunc_end3-_Z21array_mult_host_naivePdS_S_i
.cfi_endproc
# -- End function
.globl _Z22array_mult_host_test_2PdS_S_i # -- Begin function _Z22array_mult_host_test_2PdS_S_i
.p2align 4, 0x90
.type _Z22array_mult_host_test_2PdS_S_i,@function
_Z22array_mult_host_test_2PdS_S_i: # @_Z22array_mult_host_test_2PdS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl %ecx, 4(%rsp) # 4-byte Spill
movslq %ecx, %rbp
leaq (,%rbp,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebp, %ebp
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl 4(%rsp), %eax # 4-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r15,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r12,%rcx,8), %xmm0
movsd %xmm0, (%r13,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq 16(%rsp), %rdi # 8-byte Reload
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end4:
.size _Z22array_mult_host_test_2PdS_S_i, .Lfunc_end4-_Z22array_mult_host_test_2PdS_S_i
.cfi_endproc
# -- End function
.globl _Z22array_mult_host_test_3PdS_S_S_S_S_i # -- Begin function _Z22array_mult_host_test_3PdS_S_S_S_S_i
.p2align 4, 0x90
.type _Z22array_mult_host_test_3PdS_S_S_S_S_i,@function
_Z22array_mult_host_test_3PdS_S_S_S_S_i: # @_Z22array_mult_host_test_3PdS_S_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, (%rsp) # 8-byte Spill
movq %r8, %rbp
movq %rdx, %r14
movq %rsi, %r12
movq %rdi, %r13
movslq 64(%rsp), %rbx
leaq (,%rbx,8), %r15
movq %rcx, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testq %rbx, %rbx
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%r13,%rcx,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r12,%rcx,8), %xmm0
movsd %xmm0, (%r14,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq (%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end5:
.size _Z22array_mult_host_test_3PdS_S_S_S_S_i, .Lfunc_end5-_Z22array_mult_host_test_3PdS_S_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z20array_mult_host_hybrPdS_S_i # -- Begin function _Z20array_mult_host_hybrPdS_S_i
.p2align 4, 0x90
.type _Z20array_mult_host_hybrPdS_S_i,@function
_Z20array_mult_host_hybrPdS_S_i: # @_Z20array_mult_host_hybrPdS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cmpl $1024, %ecx # imm = 0x400
jl .LBB6_1
# %bb.2:
movl %ecx, %edi
shrl $10, %edi
movl %ecx, %r12d
movl %ecx, %ebp
andl $2147482624, %ebp # imm = 0x7FFFFC00
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17array_mult_kernelPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
movl %r12d, %ecx
andl $1023, %ecx # imm = 0x3FF
movl %ebp, %eax
jmp .LBB6_5
.LBB6_1:
xorl %eax, %eax
.LBB6_5:
leaq (%r15,%rax,8), %rdi
leaq (%r14,%rax,8), %rsi
leaq (%rbx,%rax,8), %rdx
callq _Z22array_mult_host_test_2PdS_S_i
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z20array_mult_host_hybrPdS_S_i, .Lfunc_end6-_Z20array_mult_host_hybrPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11initialDataPdi
.LCPI7_0:
.quad 0x4024000000000000 # double 10
.text
.globl _Z11initialDataPdi
.p2align 4, 0x90
.type _Z11initialDataPdi,@function
_Z11initialDataPdi: # @_Z11initialDataPdi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB7_2
.LBB7_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z11initialDataPdi, .Lfunc_end7-_Z11initialDataPdi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPdS_i
.LCPI8_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI8_1:
.quad 0x3d719799812dea11 # double 9.9999999999999998E-13
.text
.globl _Z11checkResultPdS_i
.p2align 4, 0x90
.type _Z11checkResultPdS_i,@function
_Z11checkResultPdS_i: # @_Z11checkResultPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
setle %bpl
jle .LBB8_8
# %bb.1: # %.lr.ph.preheader
movl %edx, %r12d
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movsd (%rsp), %xmm1 # xmm1 = mem[0],zero
movsd (%r14), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, %xmm2
subsd %xmm0, %xmm2
andpd .LCPI8_0(%rip), %xmm2
xorl %r15d, %r15d
ucomisd .LCPI8_1(%rip), %xmm2
jae .LBB8_6
# %bb.2: # %.lr.ph33.preheader
movl %r12d, %r13d
addq $8, %rbx
leaq -1(%r13), %rbp
xorl %r15d, %r15d
movq %rsp, %r12
.p2align 4, 0x90
.LBB8_3: # %.lr.ph33
# =>This Inner Loop Header: Depth=1
cmpq %r15, %rbp
je .LBB8_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB8_3 Depth=1
movl $8, %edx
movq %r12, %rdi
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
movsd (%rsp), %xmm1 # xmm1 = mem[0],zero
movsd 8(%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, %xmm2
subsd %xmm0, %xmm2
andpd .LCPI8_0(%rip), %xmm2
addq $8, %rbx
incq %r15
ucomisd .LCPI8_1(%rip), %xmm2
jb .LBB8_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %r13, %r15
setae %bpl
.LBB8_6:
movl $.L.str, %edi
movl %r15d, %esi
movb $2, %al
callq printf
jmp .LBB8_9
.LBB8_7: # %.critedge.loopexit
incq %r15
cmpq %r13, %r15
setae %bpl
.LBB8_8: # %.critedge
movl $.Lstr, %edi
callq puts@PLT
.LBB8_9:
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z11checkResultPdS_i, .Lfunc_end8-_Z11checkResultPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10launchTestii
.LCPI9_0:
.quad 0x4024000000000000 # double 10
.LCPI9_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI9_2:
.quad 0x408f400000000000 # double 1000
.LCPI9_4:
.quad 0x3d719799812dea11 # double 9.9999999999999998E-13
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI9_3:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z10launchTestii
.p2align 4, 0x90
.type _Z10launchTestii,@function
_Z10launchTestii: # @_Z10launchTestii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
movslq %edi, %r12
leaq (,%r12,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r15, 8(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
movl %ebp, %r15d
testl %r12d, %r12d
jle .LBB9_6
# %bb.1: # %.lr.ph.preheader.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB9_2
# %bb.3: # %_Z11initialDataPdi.exit
leaq 16(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
movq 56(%rsp), %r13 # 8-byte Reload
jle .LBB9_7
# %bb.4: # %.lr.ph.preheader.i45
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB9_5: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movsd %xmm0, (%r13,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB9_5
jmp .LBB9_7
.LBB9_6: # %_Z11initialDataPdi.exit51.critedge
leaq 16(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
movq 56(%rsp), %r13 # 8-byte Reload
.LBB9_7: # %_Z11initialDataPdi.exit51
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq 8(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
testl %r14d, %r14d
jle .LBB9_10
# %bb.8: # %.lr.ph
leaq 16(%rsp), %r13
movl %r14d, %r12d
.p2align 4, 0x90
.LBB9_9: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 24(%rsp), %xmm2
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 72(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebp, %ecx
callq _Z22array_mult_host_test_2PdS_S_i
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI9_1(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 72(%rsp), %xmm1 # 8-byte Folded Reload
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
decl %r12d
jne .LBB9_9
.LBB9_10: # %._crit_edge
xorps %xmm1, %xmm1
cvtsi2sd %r14d, %xmm1
movsd %xmm1, 80(%rsp) # 8-byte Spill
divsd %xmm1, %xmm0
mulsd .LCPI9_2(%rip), %xmm0
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movb $1, %al
callq printf
testl %r14d, %r14d
xorpd %xmm0, %xmm0
jle .LBB9_13
# %bb.11: # %.lr.ph72
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB9_12: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 24(%rsp), %xmm2
movsd .LCPI9_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 72(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebp, %ecx
callq _Z20array_mult_host_hybrPdS_S_i
movq %r13, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI9_1(%rip), %xmm1
addsd %xmm0, %xmm1
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 72(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm1, %xmm0
decl %r14d
jne .LBB9_12
.LBB9_13: # %._crit_edge73
divsd 80(%rsp), %xmm0 # 8-byte Folded Reload
mulsd .LCPI9_2(%rip), %xmm0
movl $.L.str.3, %edi
movl $.L.str.5, %esi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movl %ebp, %ecx
callq _Z20array_mult_host_hybrPdS_S_i
testl %ebp, %ebp
movq 56(%rsp), %r14 # 8-byte Reload
movq 64(%rsp), %rcx # 8-byte Reload
jle .LBB9_16
# %bb.14: # %.lr.ph.preheader.i52
xorl %eax, %eax
.p2align 4, 0x90
.LBB9_15: # %.lr.ph.i54
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
mulsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%rcx,%rax,8)
incq %rax
cmpq %rax, %r15
jne .LBB9_15
.LBB9_16: # %_Z21array_mult_host_naivePdS_S_i.exit
testl %ebp, %ebp
jle .LBB9_21
# %bb.17: # %.lr.ph.preheader.i58
movq 32(%rsp), %r13
xorl %r12d, %r12d
leaq 16(%rsp), %rbp
.p2align 4, 0x90
.LBB9_18: # %.lr.ph.i60
# =>This Inner Loop Header: Depth=1
movl $8, %edx
movq %rbp, %rdi
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
movsd 16(%rsp), %xmm1 # xmm1 = mem[0],zero
movq 64(%rsp), %rax # 8-byte Reload
movsd (%rax,%r12,8), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, %xmm2
subsd %xmm0, %xmm2
andpd .LCPI9_3(%rip), %xmm2
ucomisd .LCPI9_4(%rip), %xmm2
jae .LBB9_19
# %bb.20: # in Loop: Header=BB9_18 Depth=1
incq %r12
addq $8, %r13
cmpq %r12, %r15
jne .LBB9_18
.LBB9_21: # %.critedge.i
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB9_22
.LBB9_19:
movl $.L.str, %edi
movl %r12d, %esi
movb $2, %al
callq printf
.LBB9_22: # %_Z11checkResultPdS_i.exit
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z10launchTestii, .Lfunc_end9-_Z10launchTestii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.p2align 4, 0x90
.LBB10_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl %eax, %r14d
jge .LBB10_3
# %bb.1: # %.lr.ph
# in Loop: Header=BB10_2 Depth=1
movl %r14d, %edi
movl $10, %esi
callq _Z10launchTestii
addl %r14d, %r14d
jmp .LBB10_2
.LBB10_3: # %._crit_edge
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17array_mult_kernelPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17array_mult_kernelPdS_S_,@object # @_Z17array_mult_kernelPdS_S_
.section .rodata,"a",@progbits
.globl _Z17array_mult_kernelPdS_S_
.p2align 3, 0x0
_Z17array_mult_kernelPdS_S_:
.quad _Z32__device_stub__array_mult_kernelPdS_S_
.size _Z17array_mult_kernelPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Test failed on i=%d, host: %lf, dev: %lf\n"
.size .L.str, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nInitializing data (size=%d)\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%30s - %12.9lf ms\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "array_mult_host_test_2"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "array_mult_host_hybr"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17array_mult_kernelPdS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test pass"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__array_mult_kernelPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17array_mult_kernelPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
int i;
for( i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void _saxpy_cuda(int n, float a, float *x, float *y){
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
if(Idx < N)
y[Idx]=a*x[Idx]+y[Idx];
return;
}
void saxpy_gpu(int n, float a, float *x, float *y){
int size = sizeof(float)*N;
//TODO
float *x_dev;
float *y_dev;
cudaMalloc((void**)&x_dev, size);
cudaMalloc((void**)&y_dev,size);
cudaMemset(x_dev, 0.0, size);
cudaMemset(y_dev, 0.0, size);
cudaMemcpy(x_dev, x, size, cudaMemcpyHostToDevice );
cudaMemcpy(y_dev, y, size, cudaMemcpyHostToDevice);
//TODO
//function
dim3 bs (4096,1,1);
dim3 ts(1024,1,1);
_saxpy_cuda <<< bs,ts >>> (n, a, x_dev, y_dev);
//cudaMemcpy(x, x_dev, size, cudaMemcpyDeviceToHost);
cudaMemcpy(y, y_dev, size, cudaMemcpyDeviceToHost);
cudaFree(x_dev);
cudaFree(y_dev);
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
x = (float *) malloc( size);
y = (float *) malloc( size);
a=3;
int i;
// initialize for
for( i=0; i<N; i++){
x[i]=i*0.001;
y[i]=0;
}
printf(" data\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
//saxpy(N, a, x, y);
saxpy_gpu(N,a,x,y);
printf(" result\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
free(x);
free(y);
return 0;
} | code for sm_80
Function : _Z11_saxpy_cudaifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3fffff, PT ; /* 0x003fffff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
int i;
for( i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void _saxpy_cuda(int n, float a, float *x, float *y){
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
if(Idx < N)
y[Idx]=a*x[Idx]+y[Idx];
return;
}
void saxpy_gpu(int n, float a, float *x, float *y){
int size = sizeof(float)*N;
//TODO
float *x_dev;
float *y_dev;
cudaMalloc((void**)&x_dev, size);
cudaMalloc((void**)&y_dev,size);
cudaMemset(x_dev, 0.0, size);
cudaMemset(y_dev, 0.0, size);
cudaMemcpy(x_dev, x, size, cudaMemcpyHostToDevice );
cudaMemcpy(y_dev, y, size, cudaMemcpyHostToDevice);
//TODO
//function
dim3 bs (4096,1,1);
dim3 ts(1024,1,1);
_saxpy_cuda <<< bs,ts >>> (n, a, x_dev, y_dev);
//cudaMemcpy(x, x_dev, size, cudaMemcpyDeviceToHost);
cudaMemcpy(y, y_dev, size, cudaMemcpyDeviceToHost);
cudaFree(x_dev);
cudaFree(y_dev);
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
x = (float *) malloc( size);
y = (float *) malloc( size);
a=3;
int i;
// initialize for
for( i=0; i<N; i++){
x[i]=i*0.001;
y[i]=0;
}
printf(" data\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
//saxpy(N, a, x, y);
saxpy_gpu(N,a,x,y);
printf(" result\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
free(x);
free(y);
return 0;
} | .file "tmpxft_0000645e_00000000-6_saxpy_1.5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdx,%rax), %xmm1
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.globl _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
.type _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_, @function
_Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11_saxpy_cudaifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_, .-_Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
.globl _Z11_saxpy_cudaifPfS_
.type _Z11_saxpy_cudaifPfS_, @function
_Z11_saxpy_cudaifPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11_saxpy_cudaifPfS_, .-_Z11_saxpy_cudaifPfS_
.globl _Z9saxpy_gpuifPfS_
.type _Z9saxpy_gpuifPfS_, @function
_Z9saxpy_gpuifPfS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movss %xmm0, 12(%rsp)
movq %rsi, %r12
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $16777216, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movss 12(%rsp), %xmm0
movl %ebp, %edi
call _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9saxpy_gpuifPfS_, .-_Z9saxpy_gpuifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " data\n"
.LC3:
.string "y[%d] = %f, "
.LC4:
.string "\n"
.LC6:
.string " result\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movsd .LC0(%rip), %xmm1
.L22:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC3(%rip), %r13
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq $5, %r12
jne .L23
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
movq %rbp, %rsi
movss .LC5(%rip), %xmm0
movl $4194304, %edi
call _Z9saxpy_gpuifPfS_
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC3(%rip), %r13
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq $5, %r12
jne .L24
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z11_saxpy_cudaifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11_saxpy_cudaifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
int i;
for( i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void _saxpy_cuda(int n, float a, float *x, float *y){
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
if(Idx < N)
y[Idx]=a*x[Idx]+y[Idx];
return;
}
void saxpy_gpu(int n, float a, float *x, float *y){
int size = sizeof(float)*N;
//TODO
float *x_dev;
float *y_dev;
cudaMalloc((void**)&x_dev, size);
cudaMalloc((void**)&y_dev,size);
cudaMemset(x_dev, 0.0, size);
cudaMemset(y_dev, 0.0, size);
cudaMemcpy(x_dev, x, size, cudaMemcpyHostToDevice );
cudaMemcpy(y_dev, y, size, cudaMemcpyHostToDevice);
//TODO
//function
dim3 bs (4096,1,1);
dim3 ts(1024,1,1);
_saxpy_cuda <<< bs,ts >>> (n, a, x_dev, y_dev);
//cudaMemcpy(x, x_dev, size, cudaMemcpyDeviceToHost);
cudaMemcpy(y, y_dev, size, cudaMemcpyDeviceToHost);
cudaFree(x_dev);
cudaFree(y_dev);
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
x = (float *) malloc( size);
y = (float *) malloc( size);
a=3;
int i;
// initialize for
for( i=0; i<N; i++){
x[i]=i*0.001;
y[i]=0;
}
printf(" data\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
//saxpy(N, a, x, y);
saxpy_gpu(N,a,x,y);
printf(" result\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
free(x);
free(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
int i;
for( i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void _saxpy_cuda(int n, float a, float *x, float *y){
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
if(Idx < N)
y[Idx]=a*x[Idx]+y[Idx];
return;
}
void saxpy_gpu(int n, float a, float *x, float *y){
int size = sizeof(float)*N;
//TODO
float *x_dev;
float *y_dev;
hipMalloc((void**)&x_dev, size);
hipMalloc((void**)&y_dev,size);
hipMemset(x_dev, 0.0, size);
hipMemset(y_dev, 0.0, size);
hipMemcpy(x_dev, x, size, hipMemcpyHostToDevice );
hipMemcpy(y_dev, y, size, hipMemcpyHostToDevice);
//TODO
//function
dim3 bs (4096,1,1);
dim3 ts(1024,1,1);
_saxpy_cuda <<< bs,ts >>> (n, a, x_dev, y_dev);
//cudaMemcpy(x, x_dev, size, cudaMemcpyDeviceToHost);
hipMemcpy(y, y_dev, size, hipMemcpyDeviceToHost);
hipFree(x_dev);
hipFree(y_dev);
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
x = (float *) malloc( size);
y = (float *) malloc( size);
a=3;
int i;
// initialize for
for( i=0; i<N; i++){
x[i]=i*0.001;
y[i]=0;
}
printf(" data\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
//saxpy(N, a, x, y);
saxpy_gpu(N,a,x,y);
printf(" result\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
free(x);
free(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
int i;
for( i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void _saxpy_cuda(int n, float a, float *x, float *y){
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
if(Idx < N)
y[Idx]=a*x[Idx]+y[Idx];
return;
}
void saxpy_gpu(int n, float a, float *x, float *y){
int size = sizeof(float)*N;
//TODO
float *x_dev;
float *y_dev;
hipMalloc((void**)&x_dev, size);
hipMalloc((void**)&y_dev,size);
hipMemset(x_dev, 0.0, size);
hipMemset(y_dev, 0.0, size);
hipMemcpy(x_dev, x, size, hipMemcpyHostToDevice );
hipMemcpy(y_dev, y, size, hipMemcpyHostToDevice);
//TODO
//function
dim3 bs (4096,1,1);
dim3 ts(1024,1,1);
_saxpy_cuda <<< bs,ts >>> (n, a, x_dev, y_dev);
//cudaMemcpy(x, x_dev, size, cudaMemcpyDeviceToHost);
hipMemcpy(y, y_dev, size, hipMemcpyDeviceToHost);
hipFree(x_dev);
hipFree(y_dev);
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
x = (float *) malloc( size);
y = (float *) malloc( size);
a=3;
int i;
// initialize for
for( i=0; i<N; i++){
x[i]=i*0.001;
y[i]=0;
}
printf(" data\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
//saxpy(N, a, x, y);
saxpy_gpu(N,a,x,y);
printf(" result\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
free(x);
free(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11_saxpy_cudaifPfS_
.globl _Z11_saxpy_cudaifPfS_
.p2align 8
.type _Z11_saxpy_cudaifPfS_,@function
_Z11_saxpy_cudaifPfS_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11_saxpy_cudaifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11_saxpy_cudaifPfS_, .Lfunc_end0-_Z11_saxpy_cudaifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11_saxpy_cudaifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11_saxpy_cudaifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
int i;
for( i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void _saxpy_cuda(int n, float a, float *x, float *y){
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
if(Idx < N)
y[Idx]=a*x[Idx]+y[Idx];
return;
}
void saxpy_gpu(int n, float a, float *x, float *y){
int size = sizeof(float)*N;
//TODO
float *x_dev;
float *y_dev;
hipMalloc((void**)&x_dev, size);
hipMalloc((void**)&y_dev,size);
hipMemset(x_dev, 0.0, size);
hipMemset(y_dev, 0.0, size);
hipMemcpy(x_dev, x, size, hipMemcpyHostToDevice );
hipMemcpy(y_dev, y, size, hipMemcpyHostToDevice);
//TODO
//function
dim3 bs (4096,1,1);
dim3 ts(1024,1,1);
_saxpy_cuda <<< bs,ts >>> (n, a, x_dev, y_dev);
//cudaMemcpy(x, x_dev, size, cudaMemcpyDeviceToHost);
hipMemcpy(y, y_dev, size, hipMemcpyDeviceToHost);
hipFree(x_dev);
hipFree(y_dev);
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
x = (float *) malloc( size);
y = (float *) malloc( size);
a=3;
int i;
// initialize for
for( i=0; i<N; i++){
x[i]=i*0.001;
y[i]=0;
}
printf(" data\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
//saxpy(N, a, x, y);
saxpy_gpu(N,a,x,y);
printf(" result\n");
for( i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
free(x);
free(y);
return 0;
} | .text
.file "saxpy_1.5.hip"
.globl _Z5saxpyifPfS_ # -- Begin function _Z5saxpyifPfS_
.p2align 4, 0x90
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_: # @_Z5saxpyifPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdx,%rcx,4), %xmm1
movss %xmm1, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub___saxpy_cudaifPfS_ # -- Begin function _Z26__device_stub___saxpy_cudaifPfS_
.p2align 4, 0x90
.type _Z26__device_stub___saxpy_cudaifPfS_,@function
_Z26__device_stub___saxpy_cudaifPfS_: # @_Z26__device_stub___saxpy_cudaifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11_saxpy_cudaifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub___saxpy_cudaifPfS_, .Lfunc_end1-_Z26__device_stub___saxpy_cudaifPfS_
.cfi_endproc
# -- End function
.globl _Z9saxpy_gpuifPfS_ # -- Begin function _Z9saxpy_gpuifPfS_
.p2align 4, 0x90
.type _Z9saxpy_gpuifPfS_,@function
_Z9saxpy_gpuifPfS_: # @_Z9saxpy_gpuifPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movss %xmm0, 20(%rsp) # 4-byte Spill
movl %edi, %ebp
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl %ebp, 28(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11_saxpy_cudaifPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9saxpy_gpuifPfS_, .Lfunc_end2-_Z9saxpy_gpuifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movl $16777216, %edx # imm = 0x1000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %r15d, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rbx,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB3_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $5, %r15
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $4194304, %edi # imm = 0x400000
movq %rbx, %rsi
movq %r14, %rdx
callq _Z9saxpy_gpuifPfS_
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $5, %r15
jne .LBB3_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11_saxpy_cudaifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11_saxpy_cudaifPfS_,@object # @_Z11_saxpy_cudaifPfS_
.section .rodata,"a",@progbits
.globl _Z11_saxpy_cudaifPfS_
.p2align 3, 0x0
_Z11_saxpy_cudaifPfS_:
.quad _Z26__device_stub___saxpy_cudaifPfS_
.size _Z11_saxpy_cudaifPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "y[%d] = %f, "
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11_saxpy_cudaifPfS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " data"
.size .Lstr, 6
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " result"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub___saxpy_cudaifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11_saxpy_cudaifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11_saxpy_cudaifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3fffff, PT ; /* 0x003fffff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11_saxpy_cudaifPfS_
.globl _Z11_saxpy_cudaifPfS_
.p2align 8
.type _Z11_saxpy_cudaifPfS_,@function
_Z11_saxpy_cudaifPfS_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11_saxpy_cudaifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11_saxpy_cudaifPfS_, .Lfunc_end0-_Z11_saxpy_cudaifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11_saxpy_cudaifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11_saxpy_cudaifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000645e_00000000-6_saxpy_1.5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdx,%rax), %xmm1
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.globl _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
.type _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_, @function
_Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11_saxpy_cudaifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_, .-_Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
.globl _Z11_saxpy_cudaifPfS_
.type _Z11_saxpy_cudaifPfS_, @function
_Z11_saxpy_cudaifPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11_saxpy_cudaifPfS_, .-_Z11_saxpy_cudaifPfS_
.globl _Z9saxpy_gpuifPfS_
.type _Z9saxpy_gpuifPfS_, @function
_Z9saxpy_gpuifPfS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movss %xmm0, 12(%rsp)
movq %rsi, %r12
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaMemset@PLT
movl $16777216, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movss 12(%rsp), %xmm0
movl %ebp, %edi
call _Z35__device_stub__Z11_saxpy_cudaifPfS_ifPfS_
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9saxpy_gpuifPfS_, .-_Z9saxpy_gpuifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " data\n"
.LC3:
.string "y[%d] = %f, "
.LC4:
.string "\n"
.LC6:
.string " result\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movsd .LC0(%rip), %xmm1
.L22:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC3(%rip), %r13
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq $5, %r12
jne .L23
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
movq %rbp, %rsi
movss .LC5(%rip), %xmm0
movl $4194304, %edi
call _Z9saxpy_gpuifPfS_
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC3(%rip), %r13
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq $5, %r12
jne .L24
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z11_saxpy_cudaifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11_saxpy_cudaifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_1.5.hip"
.globl _Z5saxpyifPfS_ # -- Begin function _Z5saxpyifPfS_
.p2align 4, 0x90
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_: # @_Z5saxpyifPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdx,%rcx,4), %xmm1
movss %xmm1, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub___saxpy_cudaifPfS_ # -- Begin function _Z26__device_stub___saxpy_cudaifPfS_
.p2align 4, 0x90
.type _Z26__device_stub___saxpy_cudaifPfS_,@function
_Z26__device_stub___saxpy_cudaifPfS_: # @_Z26__device_stub___saxpy_cudaifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11_saxpy_cudaifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z26__device_stub___saxpy_cudaifPfS_, .Lfunc_end1-_Z26__device_stub___saxpy_cudaifPfS_
.cfi_endproc
# -- End function
.globl _Z9saxpy_gpuifPfS_ # -- Begin function _Z9saxpy_gpuifPfS_
.p2align 4, 0x90
.type _Z9saxpy_gpuifPfS_,@function
_Z9saxpy_gpuifPfS_: # @_Z9saxpy_gpuifPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movss %xmm0, 20(%rsp) # 4-byte Spill
movl %edi, %ebp
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl %ebp, 28(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11_saxpy_cudaifPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9saxpy_gpuifPfS_, .Lfunc_end2-_Z9saxpy_gpuifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movl $16777216, %edx # imm = 0x1000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %r15d, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rbx,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB3_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $5, %r15
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $4194304, %edi # imm = 0x400000
movq %rbx, %rsi
movq %r14, %rdx
callq _Z9saxpy_gpuifPfS_
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $5, %r15
jne .LBB3_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11_saxpy_cudaifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11_saxpy_cudaifPfS_,@object # @_Z11_saxpy_cudaifPfS_
.section .rodata,"a",@progbits
.globl _Z11_saxpy_cudaifPfS_
.p2align 3, 0x0
_Z11_saxpy_cudaifPfS_:
.quad _Z26__device_stub___saxpy_cudaifPfS_
.size _Z11_saxpy_cudaifPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "y[%d] = %f, "
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11_saxpy_cudaifPfS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " data"
.size .Lstr, 6
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " result"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub___saxpy_cudaifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11_saxpy_cudaifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void devFillAffectedIndex(int nRemove, int maxTriPerVert, int *pTriangleAffectedIndex)
{
int n = blockIdx.x*blockDim.x + threadIdx.x;
while (n < nRemove) {
for (int i = 0; i < maxTriPerVert; i++) {
pTriangleAffectedIndex[i + n*maxTriPerVert] = n;
pTriangleAffectedIndex[i + n*maxTriPerVert + nRemove*maxTriPerVert] = n;
}
n += blockDim.x*gridDim.x;
}
} | code for sm_80
Function : _Z20devFillAffectedIndexiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fda0003f01270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD R7, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000077a24 */
/* 0x040fe200078e02ff */
/*00b0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00e0*/ SHF.R.S32.HI R2, RZ, 0x1f, R7 ; /* 0x0000001fff027819 */
/* 0x000fe40000011407 */
/*00f0*/ IADD3 R6, -R0, c[0x0][0x164], RZ ; /* 0x0000590000067a10 */
/* 0x000fe40007ffe1ff */
/*0100*/ SHF.L.U64.HI R9, R7, 0x2, R2 ; /* 0x0000000207097819 */
/* 0x000fc80000010202 */
/*0110*/ IMAD R21, R8, c[0x0][0x164], RZ ; /* 0x0000590008157a24 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0130*/ @!P1 BRA 0x790 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0150*/ IMAD.WIDE R2, R21, 0x4, RZ ; /* 0x0000000415027825 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff117624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff137624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R15, RZ, RZ, R6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0006 */
/*01a0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*01b0*/ @!P0 BRA 0x670 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P2, PT, R15, 0xc, PT ; /* 0x0000000c0f00780c */
/* 0x000fe40003f44270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P2 BRA 0x4a0 ; /* 0x000002b00000a947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ IADD3 R10, P2, R2, R17.reuse, RZ ; /* 0x00000011020a7210 */
/* 0x081fe40007f5e0ff */
/*0210*/ IADD3 R12, P3, R4, R17, RZ ; /* 0x00000011040c7210 */
/* 0x000fe40007f7e0ff */
/*0220*/ IADD3 R15, R15, -0x10, RZ ; /* 0xfffffff00f0f7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.X R11, R3, 0x1, R19.reuse, P2 ; /* 0x00000001030b7824 */
/* 0x100fe200010e0613 */
/*0240*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.X R13, R5, 0x1, R19, P3 ; /* 0x00000001050d7824 */
/* 0x000fe200018e0613 */
/*0260*/ ISETP.GT.AND P2, PT, R15, 0xc, PT ; /* 0x0000000c0f00780c */
/* 0x000fe40003f44270 */
/*0270*/ STG.E [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001e2000c101904 */
/*0280*/ IADD3 R17, P3, R17, 0x40, RZ ; /* 0x0000004011117810 */
/* 0x000fc60007f7e0ff */
/*0290*/ STG.E [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0001e4000c101904 */
/*02a0*/ IMAD.X R19, RZ, RZ, R19, P3 ; /* 0x000000ffff137224 */
/* 0x000fe400018e0613 */
/*02b0*/ STG.E [R10.64+0x4], R8 ; /* 0x000004080a007986 */
/* 0x0001e8000c101904 */
/*02c0*/ STG.E [R12.64+0x4], R8 ; /* 0x000004080c007986 */
/* 0x0001e8000c101904 */
/*02d0*/ STG.E [R10.64+0x8], R8 ; /* 0x000008080a007986 */
/* 0x0001e8000c101904 */
/*02e0*/ STG.E [R12.64+0x8], R8 ; /* 0x000008080c007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R10.64+0xc], R8 ; /* 0x00000c080a007986 */
/* 0x0001e8000c101904 */
/*0300*/ STG.E [R12.64+0xc], R8 ; /* 0x00000c080c007986 */
/* 0x0001e8000c101904 */
/*0310*/ STG.E [R10.64+0x10], R8 ; /* 0x000010080a007986 */
/* 0x0001e8000c101904 */
/*0320*/ STG.E [R12.64+0x10], R8 ; /* 0x000010080c007986 */
/* 0x0001e8000c101904 */
/*0330*/ STG.E [R10.64+0x14], R8 ; /* 0x000014080a007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R12.64+0x14], R8 ; /* 0x000014080c007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R10.64+0x18], R8 ; /* 0x000018080a007986 */
/* 0x0001e8000c101904 */
/*0360*/ STG.E [R12.64+0x18], R8 ; /* 0x000018080c007986 */
/* 0x0001e8000c101904 */
/*0370*/ STG.E [R10.64+0x1c], R8 ; /* 0x00001c080a007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R12.64+0x1c], R8 ; /* 0x00001c080c007986 */
/* 0x0001e8000c101904 */
/*0390*/ STG.E [R10.64+0x20], R8 ; /* 0x000020080a007986 */
/* 0x0001e8000c101904 */
/*03a0*/ STG.E [R12.64+0x20], R8 ; /* 0x000020080c007986 */
/* 0x0001e8000c101904 */
/*03b0*/ STG.E [R10.64+0x24], R8 ; /* 0x000024080a007986 */
/* 0x0001e8000c101904 */
/*03c0*/ STG.E [R12.64+0x24], R8 ; /* 0x000024080c007986 */
/* 0x0001e8000c101904 */
/*03d0*/ STG.E [R10.64+0x28], R8 ; /* 0x000028080a007986 */
/* 0x0001e8000c101904 */
/*03e0*/ STG.E [R12.64+0x28], R8 ; /* 0x000028080c007986 */
/* 0x0001e8000c101904 */
/*03f0*/ STG.E [R10.64+0x2c], R8 ; /* 0x00002c080a007986 */
/* 0x0001e8000c101904 */
/*0400*/ STG.E [R12.64+0x2c], R8 ; /* 0x00002c080c007986 */
/* 0x0001e8000c101904 */
/*0410*/ STG.E [R10.64+0x30], R8 ; /* 0x000030080a007986 */
/* 0x0001e8000c101904 */
/*0420*/ STG.E [R12.64+0x30], R8 ; /* 0x000030080c007986 */
/* 0x0001e8000c101904 */
/*0430*/ STG.E [R10.64+0x34], R8 ; /* 0x000034080a007986 */
/* 0x0001e8000c101904 */
/*0440*/ STG.E [R12.64+0x34], R8 ; /* 0x000034080c007986 */
/* 0x0001e8000c101904 */
/*0450*/ STG.E [R10.64+0x38], R8 ; /* 0x000038080a007986 */
/* 0x0001e8000c101904 */
/*0460*/ STG.E [R12.64+0x38], R8 ; /* 0x000038080c007986 */
/* 0x0001e8000c101904 */
/*0470*/ STG.E [R10.64+0x3c], R8 ; /* 0x00003c080a007986 */
/* 0x0001e8000c101904 */
/*0480*/ STG.E [R12.64+0x3c], R8 ; /* 0x00003c080c007986 */
/* 0x0001e2000c101904 */
/*0490*/ @P2 BRA 0x200 ; /* 0xfffffd6000002947 */
/* 0x000fea000383ffff */
/*04a0*/ ISETP.GT.AND P2, PT, R15, 0x4, PT ; /* 0x000000040f00780c */
/* 0x000fda0003f44270 */
/*04b0*/ @!P2 BRA 0x650 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R10, P0, R2, R17.reuse, RZ ; /* 0x00000011020a7210 */
/* 0x081fe40007f1e0ff */
/*04d0*/ IADD3 R12, P2, R4, R17, RZ ; /* 0x00000011040c7210 */
/* 0x000fe40007f5e0ff */
/*04e0*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe20007ffe0ff */
/*04f0*/ IMAD.X R11, R3, 0x1, R19.reuse, P0 ; /* 0x00000001030b7824 */
/* 0x100fe200000e0613 */
/*0500*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0510*/ IMAD.X R13, R5, 0x1, R19, P2 ; /* 0x00000001050d7824 */
/* 0x000fe200010e0613 */
/*0520*/ IADD3 R17, P2, R17, 0x20, RZ ; /* 0x0000002011117810 */
/* 0x000fe40007f5e0ff */
/*0530*/ STG.E [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001e2000c101904 */
/*0540*/ IADD3 R15, R15, -0x8, RZ ; /* 0xfffffff80f0f7810 */
/* 0x000fc40007ffe0ff */
/*0550*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0613 */
/*0560*/ STG.E [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0001e8000c101904 */
/*0570*/ STG.E [R10.64+0x4], R8 ; /* 0x000004080a007986 */
/* 0x0001e8000c101904 */
/*0580*/ STG.E [R12.64+0x4], R8 ; /* 0x000004080c007986 */
/* 0x0001e8000c101904 */
/*0590*/ STG.E [R10.64+0x8], R8 ; /* 0x000008080a007986 */
/* 0x0001e8000c101904 */
/*05a0*/ STG.E [R12.64+0x8], R8 ; /* 0x000008080c007986 */
/* 0x0001e8000c101904 */
/*05b0*/ STG.E [R10.64+0xc], R8 ; /* 0x00000c080a007986 */
/* 0x0001e8000c101904 */
/*05c0*/ STG.E [R12.64+0xc], R8 ; /* 0x00000c080c007986 */
/* 0x0001e8000c101904 */
/*05d0*/ STG.E [R10.64+0x10], R8 ; /* 0x000010080a007986 */
/* 0x0001e8000c101904 */
/*05e0*/ STG.E [R12.64+0x10], R8 ; /* 0x000010080c007986 */
/* 0x0001e8000c101904 */
/*05f0*/ STG.E [R10.64+0x14], R8 ; /* 0x000014080a007986 */
/* 0x0001e8000c101904 */
/*0600*/ STG.E [R12.64+0x14], R8 ; /* 0x000014080c007986 */
/* 0x0001e8000c101904 */
/*0610*/ STG.E [R10.64+0x18], R8 ; /* 0x000018080a007986 */
/* 0x0001e8000c101904 */
/*0620*/ STG.E [R12.64+0x18], R8 ; /* 0x000018080c007986 */
/* 0x0001e8000c101904 */
/*0630*/ STG.E [R10.64+0x1c], R8 ; /* 0x00001c080a007986 */
/* 0x0001e8000c101904 */
/*0640*/ STG.E [R12.64+0x1c], R8 ; /* 0x00001c080c007986 */
/* 0x0001e4000c101904 */
/*0650*/ ISETP.NE.OR P0, PT, R15, RZ, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0000705670 */
/*0660*/ @!P0 BRA 0x790 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0670*/ IADD3 R10, P0, R2, R17.reuse, RZ ; /* 0x00000011020a7210 */
/* 0x081fe40007f1e0ff */
/*0680*/ IADD3 R12, P2, R4, R17, RZ ; /* 0x00000011040c7210 */
/* 0x000fe40007f5e0ff */
/*0690*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ IMAD.X R11, R3, 0x1, R19.reuse, P0 ; /* 0x00000001030b7824 */
/* 0x100fe200000e0613 */
/*06b0*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.X R13, R5, 0x1, R19, P2 ; /* 0x00000001050d7824 */
/* 0x000fe200010e0613 */
/*06d0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f05270 */
/*06e0*/ STG.E [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001e2000c101904 */
/*06f0*/ IADD3 R17, P2, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fc60007f5e0ff */
/*0700*/ STG.E [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0001e4000c101904 */
/*0710*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe400010e0613 */
/*0720*/ STG.E [R10.64+0x4], R8 ; /* 0x000004080a007986 */
/* 0x0001e8000c101904 */
/*0730*/ STG.E [R12.64+0x4], R8 ; /* 0x000004080c007986 */
/* 0x0001e8000c101904 */
/*0740*/ STG.E [R10.64+0x8], R8 ; /* 0x000008080a007986 */
/* 0x0001e8000c101904 */
/*0750*/ STG.E [R12.64+0x8], R8 ; /* 0x000008080c007986 */
/* 0x0001e8000c101904 */
/*0760*/ STG.E [R10.64+0xc], R8 ; /* 0x00000c080a007986 */
/* 0x0001e8000c101904 */
/*0770*/ STG.E [R12.64+0xc], R8 ; /* 0x00000c080c007986 */
/* 0x0001e4000c101904 */
/*0780*/ @P0 BRA 0x670 ; /* 0xfffffee000000947 */
/* 0x001fea000383ffff */
/*0790*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07a0*/ @!P0 BRA 0x890 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.IADD R2, R21, 0x1, R14 ; /* 0x0000000115027824 */
/* 0x000fe400078e020e */
/*07c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*07e0*/ LEA R4, P0, R7, R2, 0x2 ; /* 0x0000000207047211 */
/* 0x000fe200078010ff */
/*07f0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0003e8000c101904 */
/*0800*/ IMAD.X R5, R3, 0x1, R9, P0 ; /* 0x0000000103057824 */
/* 0x000fe200000e0609 */
/*0810*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05270 */
/*0820*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003f2000c101904 */
/*0830*/ @!P0 BRA 0x890 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*0850*/ STG.E [R2.64+0x4], R8 ; /* 0x0000040802007986 */
/* 0x0005e8000c101904 */
/*0860*/ STG.E [R4.64+0x4], R8 ; /* 0x0000040804007986 */
/* 0x0005f0000c101904 */
/*0870*/ @P0 STG.E [R2.64+0x8], R8 ; /* 0x0000080802000986 */
/* 0x0005e8000c101904 */
/*0880*/ @P0 STG.E [R4.64+0x8], R8 ; /* 0x0000080804000986 */
/* 0x0005e4000c101904 */
/*0890*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x006fc800078e00ff */
/*08a0*/ IMAD R8, R3, c[0x0][0xc], R8 ; /* 0x0000030003087a24 */
/* 0x001fca00078e0208 */
/*08b0*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*08c0*/ @!P0 BRA 0x110 ; /* 0xfffff84000008947 */
/* 0x000fea000383ffff */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void devFillAffectedIndex(int nRemove, int maxTriPerVert, int *pTriangleAffectedIndex)
{
int n = blockIdx.x*blockDim.x + threadIdx.x;
while (n < nRemove) {
for (int i = 0; i < maxTriPerVert; i++) {
pTriangleAffectedIndex[i + n*maxTriPerVert] = n;
pTriangleAffectedIndex[i + n*maxTriPerVert + nRemove*maxTriPerVert] = n;
}
n += blockDim.x*gridDim.x;
}
} | .file "tmpxft_0014b68c_00000000-6_devFillAffectedIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi
.type _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi, @function
_Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20devFillAffectedIndexiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi, .-_Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi
.globl _Z20devFillAffectedIndexiiPi
.type _Z20devFillAffectedIndexiiPi, @function
_Z20devFillAffectedIndexiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20devFillAffectedIndexiiPi, .-_Z20devFillAffectedIndexiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20devFillAffectedIndexiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20devFillAffectedIndexiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void devFillAffectedIndex(int nRemove, int maxTriPerVert, int *pTriangleAffectedIndex)
{
int n = blockIdx.x*blockDim.x + threadIdx.x;
while (n < nRemove) {
for (int i = 0; i < maxTriPerVert; i++) {
pTriangleAffectedIndex[i + n*maxTriPerVert] = n;
pTriangleAffectedIndex[i + n*maxTriPerVert + nRemove*maxTriPerVert] = n;
}
n += blockDim.x*gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void devFillAffectedIndex(int nRemove, int maxTriPerVert, int *pTriangleAffectedIndex)
{
int n = blockIdx.x*blockDim.x + threadIdx.x;
while (n < nRemove) {
for (int i = 0; i < maxTriPerVert; i++) {
pTriangleAffectedIndex[i + n*maxTriPerVert] = n;
pTriangleAffectedIndex[i + n*maxTriPerVert + nRemove*maxTriPerVert] = n;
}
n += blockDim.x*gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void devFillAffectedIndex(int nRemove, int maxTriPerVert, int *pTriangleAffectedIndex)
{
int n = blockIdx.x*blockDim.x + threadIdx.x;
while (n < nRemove) {
for (int i = 0; i < maxTriPerVert; i++) {
pTriangleAffectedIndex[i + n*maxTriPerVert] = n;
pTriangleAffectedIndex[i + n*maxTriPerVert + nRemove*maxTriPerVert] = n;
}
n += blockDim.x*gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20devFillAffectedIndexiiPi
.globl _Z20devFillAffectedIndexiiPi
.p2align 8
.type _Z20devFillAffectedIndexiiPi,@function
_Z20devFillAffectedIndexiiPi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
s_mul_i32 s15, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s15, v0
v_cmpx_gt_i32_e64 s4, v7
s_cbranch_execz .LBB0_6
s_load_b32 s5, s[0:1], 0x4
s_load_b32 s3, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_add3_u32 v0, s15, s4, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v0, s5, v0
v_mul_lo_u32 v2, s5, v7
s_cmp_gt_i32 s5, 0
s_mul_i32 s3, s3, s6
s_cselect_b32 s2, -1, 0
s_mov_b32 s6, 0
s_mul_i32 s7, s3, s5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v7, s3, v7
v_add_nc_u32_e32 v0, s7, v0
v_add_nc_u32_e32 v2, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v7
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s8, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v9, vcc_lo
.LBB0_5:
global_store_b32 v[5:6], v7, off
global_store_b32 v[3:4], v7, off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20devFillAffectedIndexiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20devFillAffectedIndexiiPi, .Lfunc_end0-_Z20devFillAffectedIndexiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20devFillAffectedIndexiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20devFillAffectedIndexiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void devFillAffectedIndex(int nRemove, int maxTriPerVert, int *pTriangleAffectedIndex)
{
int n = blockIdx.x*blockDim.x + threadIdx.x;
while (n < nRemove) {
for (int i = 0; i < maxTriPerVert; i++) {
pTriangleAffectedIndex[i + n*maxTriPerVert] = n;
pTriangleAffectedIndex[i + n*maxTriPerVert + nRemove*maxTriPerVert] = n;
}
n += blockDim.x*gridDim.x;
}
} | .text
.file "devFillAffectedIndex.hip"
.globl _Z35__device_stub__devFillAffectedIndexiiPi # -- Begin function _Z35__device_stub__devFillAffectedIndexiiPi
.p2align 4, 0x90
.type _Z35__device_stub__devFillAffectedIndexiiPi,@function
_Z35__device_stub__devFillAffectedIndexiiPi: # @_Z35__device_stub__devFillAffectedIndexiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20devFillAffectedIndexiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__devFillAffectedIndexiiPi, .Lfunc_end0-_Z35__device_stub__devFillAffectedIndexiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20devFillAffectedIndexiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20devFillAffectedIndexiiPi,@object # @_Z20devFillAffectedIndexiiPi
.section .rodata,"a",@progbits
.globl _Z20devFillAffectedIndexiiPi
.p2align 3, 0x0
_Z20devFillAffectedIndexiiPi:
.quad _Z35__device_stub__devFillAffectedIndexiiPi
.size _Z20devFillAffectedIndexiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20devFillAffectedIndexiiPi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__devFillAffectedIndexiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20devFillAffectedIndexiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20devFillAffectedIndexiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fda0003f01270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD R7, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000077a24 */
/* 0x040fe200078e02ff */
/*00b0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00e0*/ SHF.R.S32.HI R2, RZ, 0x1f, R7 ; /* 0x0000001fff027819 */
/* 0x000fe40000011407 */
/*00f0*/ IADD3 R6, -R0, c[0x0][0x164], RZ ; /* 0x0000590000067a10 */
/* 0x000fe40007ffe1ff */
/*0100*/ SHF.L.U64.HI R9, R7, 0x2, R2 ; /* 0x0000000207097819 */
/* 0x000fc80000010202 */
/*0110*/ IMAD R21, R8, c[0x0][0x164], RZ ; /* 0x0000590008157a24 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0130*/ @!P1 BRA 0x790 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0150*/ IMAD.WIDE R2, R21, 0x4, RZ ; /* 0x0000000415027825 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff117624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff137624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R15, RZ, RZ, R6 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0006 */
/*01a0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*01b0*/ @!P0 BRA 0x670 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P2, PT, R15, 0xc, PT ; /* 0x0000000c0f00780c */
/* 0x000fe40003f44270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P2 BRA 0x4a0 ; /* 0x000002b00000a947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ IADD3 R10, P2, R2, R17.reuse, RZ ; /* 0x00000011020a7210 */
/* 0x081fe40007f5e0ff */
/*0210*/ IADD3 R12, P3, R4, R17, RZ ; /* 0x00000011040c7210 */
/* 0x000fe40007f7e0ff */
/*0220*/ IADD3 R15, R15, -0x10, RZ ; /* 0xfffffff00f0f7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.X R11, R3, 0x1, R19.reuse, P2 ; /* 0x00000001030b7824 */
/* 0x100fe200010e0613 */
/*0240*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.X R13, R5, 0x1, R19, P3 ; /* 0x00000001050d7824 */
/* 0x000fe200018e0613 */
/*0260*/ ISETP.GT.AND P2, PT, R15, 0xc, PT ; /* 0x0000000c0f00780c */
/* 0x000fe40003f44270 */
/*0270*/ STG.E [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001e2000c101904 */
/*0280*/ IADD3 R17, P3, R17, 0x40, RZ ; /* 0x0000004011117810 */
/* 0x000fc60007f7e0ff */
/*0290*/ STG.E [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0001e4000c101904 */
/*02a0*/ IMAD.X R19, RZ, RZ, R19, P3 ; /* 0x000000ffff137224 */
/* 0x000fe400018e0613 */
/*02b0*/ STG.E [R10.64+0x4], R8 ; /* 0x000004080a007986 */
/* 0x0001e8000c101904 */
/*02c0*/ STG.E [R12.64+0x4], R8 ; /* 0x000004080c007986 */
/* 0x0001e8000c101904 */
/*02d0*/ STG.E [R10.64+0x8], R8 ; /* 0x000008080a007986 */
/* 0x0001e8000c101904 */
/*02e0*/ STG.E [R12.64+0x8], R8 ; /* 0x000008080c007986 */
/* 0x0001e8000c101904 */
/*02f0*/ STG.E [R10.64+0xc], R8 ; /* 0x00000c080a007986 */
/* 0x0001e8000c101904 */
/*0300*/ STG.E [R12.64+0xc], R8 ; /* 0x00000c080c007986 */
/* 0x0001e8000c101904 */
/*0310*/ STG.E [R10.64+0x10], R8 ; /* 0x000010080a007986 */
/* 0x0001e8000c101904 */
/*0320*/ STG.E [R12.64+0x10], R8 ; /* 0x000010080c007986 */
/* 0x0001e8000c101904 */
/*0330*/ STG.E [R10.64+0x14], R8 ; /* 0x000014080a007986 */
/* 0x0001e8000c101904 */
/*0340*/ STG.E [R12.64+0x14], R8 ; /* 0x000014080c007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R10.64+0x18], R8 ; /* 0x000018080a007986 */
/* 0x0001e8000c101904 */
/*0360*/ STG.E [R12.64+0x18], R8 ; /* 0x000018080c007986 */
/* 0x0001e8000c101904 */
/*0370*/ STG.E [R10.64+0x1c], R8 ; /* 0x00001c080a007986 */
/* 0x0001e8000c101904 */
/*0380*/ STG.E [R12.64+0x1c], R8 ; /* 0x00001c080c007986 */
/* 0x0001e8000c101904 */
/*0390*/ STG.E [R10.64+0x20], R8 ; /* 0x000020080a007986 */
/* 0x0001e8000c101904 */
/*03a0*/ STG.E [R12.64+0x20], R8 ; /* 0x000020080c007986 */
/* 0x0001e8000c101904 */
/*03b0*/ STG.E [R10.64+0x24], R8 ; /* 0x000024080a007986 */
/* 0x0001e8000c101904 */
/*03c0*/ STG.E [R12.64+0x24], R8 ; /* 0x000024080c007986 */
/* 0x0001e8000c101904 */
/*03d0*/ STG.E [R10.64+0x28], R8 ; /* 0x000028080a007986 */
/* 0x0001e8000c101904 */
/*03e0*/ STG.E [R12.64+0x28], R8 ; /* 0x000028080c007986 */
/* 0x0001e8000c101904 */
/*03f0*/ STG.E [R10.64+0x2c], R8 ; /* 0x00002c080a007986 */
/* 0x0001e8000c101904 */
/*0400*/ STG.E [R12.64+0x2c], R8 ; /* 0x00002c080c007986 */
/* 0x0001e8000c101904 */
/*0410*/ STG.E [R10.64+0x30], R8 ; /* 0x000030080a007986 */
/* 0x0001e8000c101904 */
/*0420*/ STG.E [R12.64+0x30], R8 ; /* 0x000030080c007986 */
/* 0x0001e8000c101904 */
/*0430*/ STG.E [R10.64+0x34], R8 ; /* 0x000034080a007986 */
/* 0x0001e8000c101904 */
/*0440*/ STG.E [R12.64+0x34], R8 ; /* 0x000034080c007986 */
/* 0x0001e8000c101904 */
/*0450*/ STG.E [R10.64+0x38], R8 ; /* 0x000038080a007986 */
/* 0x0001e8000c101904 */
/*0460*/ STG.E [R12.64+0x38], R8 ; /* 0x000038080c007986 */
/* 0x0001e8000c101904 */
/*0470*/ STG.E [R10.64+0x3c], R8 ; /* 0x00003c080a007986 */
/* 0x0001e8000c101904 */
/*0480*/ STG.E [R12.64+0x3c], R8 ; /* 0x00003c080c007986 */
/* 0x0001e2000c101904 */
/*0490*/ @P2 BRA 0x200 ; /* 0xfffffd6000002947 */
/* 0x000fea000383ffff */
/*04a0*/ ISETP.GT.AND P2, PT, R15, 0x4, PT ; /* 0x000000040f00780c */
/* 0x000fda0003f44270 */
/*04b0*/ @!P2 BRA 0x650 ; /* 0x000001900000a947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R10, P0, R2, R17.reuse, RZ ; /* 0x00000011020a7210 */
/* 0x081fe40007f1e0ff */
/*04d0*/ IADD3 R12, P2, R4, R17, RZ ; /* 0x00000011040c7210 */
/* 0x000fe40007f5e0ff */
/*04e0*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe20007ffe0ff */
/*04f0*/ IMAD.X R11, R3, 0x1, R19.reuse, P0 ; /* 0x00000001030b7824 */
/* 0x100fe200000e0613 */
/*0500*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0510*/ IMAD.X R13, R5, 0x1, R19, P2 ; /* 0x00000001050d7824 */
/* 0x000fe200010e0613 */
/*0520*/ IADD3 R17, P2, R17, 0x20, RZ ; /* 0x0000002011117810 */
/* 0x000fe40007f5e0ff */
/*0530*/ STG.E [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001e2000c101904 */
/*0540*/ IADD3 R15, R15, -0x8, RZ ; /* 0xfffffff80f0f7810 */
/* 0x000fc40007ffe0ff */
/*0550*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0613 */
/*0560*/ STG.E [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0001e8000c101904 */
/*0570*/ STG.E [R10.64+0x4], R8 ; /* 0x000004080a007986 */
/* 0x0001e8000c101904 */
/*0580*/ STG.E [R12.64+0x4], R8 ; /* 0x000004080c007986 */
/* 0x0001e8000c101904 */
/*0590*/ STG.E [R10.64+0x8], R8 ; /* 0x000008080a007986 */
/* 0x0001e8000c101904 */
/*05a0*/ STG.E [R12.64+0x8], R8 ; /* 0x000008080c007986 */
/* 0x0001e8000c101904 */
/*05b0*/ STG.E [R10.64+0xc], R8 ; /* 0x00000c080a007986 */
/* 0x0001e8000c101904 */
/*05c0*/ STG.E [R12.64+0xc], R8 ; /* 0x00000c080c007986 */
/* 0x0001e8000c101904 */
/*05d0*/ STG.E [R10.64+0x10], R8 ; /* 0x000010080a007986 */
/* 0x0001e8000c101904 */
/*05e0*/ STG.E [R12.64+0x10], R8 ; /* 0x000010080c007986 */
/* 0x0001e8000c101904 */
/*05f0*/ STG.E [R10.64+0x14], R8 ; /* 0x000014080a007986 */
/* 0x0001e8000c101904 */
/*0600*/ STG.E [R12.64+0x14], R8 ; /* 0x000014080c007986 */
/* 0x0001e8000c101904 */
/*0610*/ STG.E [R10.64+0x18], R8 ; /* 0x000018080a007986 */
/* 0x0001e8000c101904 */
/*0620*/ STG.E [R12.64+0x18], R8 ; /* 0x000018080c007986 */
/* 0x0001e8000c101904 */
/*0630*/ STG.E [R10.64+0x1c], R8 ; /* 0x00001c080a007986 */
/* 0x0001e8000c101904 */
/*0640*/ STG.E [R12.64+0x1c], R8 ; /* 0x00001c080c007986 */
/* 0x0001e4000c101904 */
/*0650*/ ISETP.NE.OR P0, PT, R15, RZ, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0000705670 */
/*0660*/ @!P0 BRA 0x790 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0670*/ IADD3 R10, P0, R2, R17.reuse, RZ ; /* 0x00000011020a7210 */
/* 0x081fe40007f1e0ff */
/*0680*/ IADD3 R12, P2, R4, R17, RZ ; /* 0x00000011040c7210 */
/* 0x000fe40007f5e0ff */
/*0690*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ IMAD.X R11, R3, 0x1, R19.reuse, P0 ; /* 0x00000001030b7824 */
/* 0x100fe200000e0613 */
/*06b0*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.X R13, R5, 0x1, R19, P2 ; /* 0x00000001050d7824 */
/* 0x000fe200010e0613 */
/*06d0*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f05270 */
/*06e0*/ STG.E [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001e2000c101904 */
/*06f0*/ IADD3 R17, P2, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fc60007f5e0ff */
/*0700*/ STG.E [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x0001e4000c101904 */
/*0710*/ IMAD.X R19, RZ, RZ, R19, P2 ; /* 0x000000ffff137224 */
/* 0x000fe400010e0613 */
/*0720*/ STG.E [R10.64+0x4], R8 ; /* 0x000004080a007986 */
/* 0x0001e8000c101904 */
/*0730*/ STG.E [R12.64+0x4], R8 ; /* 0x000004080c007986 */
/* 0x0001e8000c101904 */
/*0740*/ STG.E [R10.64+0x8], R8 ; /* 0x000008080a007986 */
/* 0x0001e8000c101904 */
/*0750*/ STG.E [R12.64+0x8], R8 ; /* 0x000008080c007986 */
/* 0x0001e8000c101904 */
/*0760*/ STG.E [R10.64+0xc], R8 ; /* 0x00000c080a007986 */
/* 0x0001e8000c101904 */
/*0770*/ STG.E [R12.64+0xc], R8 ; /* 0x00000c080c007986 */
/* 0x0001e4000c101904 */
/*0780*/ @P0 BRA 0x670 ; /* 0xfffffee000000947 */
/* 0x001fea000383ffff */
/*0790*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07a0*/ @!P0 BRA 0x890 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.IADD R2, R21, 0x1, R14 ; /* 0x0000000115027824 */
/* 0x000fe400078e020e */
/*07c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*07d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*07e0*/ LEA R4, P0, R7, R2, 0x2 ; /* 0x0000000207047211 */
/* 0x000fe200078010ff */
/*07f0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0003e8000c101904 */
/*0800*/ IMAD.X R5, R3, 0x1, R9, P0 ; /* 0x0000000103057824 */
/* 0x000fe200000e0609 */
/*0810*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05270 */
/*0820*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003f2000c101904 */
/*0830*/ @!P0 BRA 0x890 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*0850*/ STG.E [R2.64+0x4], R8 ; /* 0x0000040802007986 */
/* 0x0005e8000c101904 */
/*0860*/ STG.E [R4.64+0x4], R8 ; /* 0x0000040804007986 */
/* 0x0005f0000c101904 */
/*0870*/ @P0 STG.E [R2.64+0x8], R8 ; /* 0x0000080802000986 */
/* 0x0005e8000c101904 */
/*0880*/ @P0 STG.E [R4.64+0x8], R8 ; /* 0x0000080804000986 */
/* 0x0005e4000c101904 */
/*0890*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x006fc800078e00ff */
/*08a0*/ IMAD R8, R3, c[0x0][0xc], R8 ; /* 0x0000030003087a24 */
/* 0x001fca00078e0208 */
/*08b0*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*08c0*/ @!P0 BRA 0x110 ; /* 0xfffff84000008947 */
/* 0x000fea000383ffff */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20devFillAffectedIndexiiPi
.globl _Z20devFillAffectedIndexiiPi
.p2align 8
.type _Z20devFillAffectedIndexiiPi,@function
_Z20devFillAffectedIndexiiPi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
s_mul_i32 s15, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s15, v0
v_cmpx_gt_i32_e64 s4, v7
s_cbranch_execz .LBB0_6
s_load_b32 s5, s[0:1], 0x4
s_load_b32 s3, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_add3_u32 v0, s15, s4, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v0, s5, v0
v_mul_lo_u32 v2, s5, v7
s_cmp_gt_i32 s5, 0
s_mul_i32 s3, s3, s6
s_cselect_b32 s2, -1, 0
s_mov_b32 s6, 0
s_mul_i32 s7, s3, s5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v7, s3, v7
v_add_nc_u32_e32 v0, s7, v0
v_add_nc_u32_e32 v2, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v7
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_6
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s8, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v9, vcc_lo
.LBB0_5:
global_store_b32 v[5:6], v7, off
global_store_b32 v[3:4], v7, off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20devFillAffectedIndexiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20devFillAffectedIndexiiPi, .Lfunc_end0-_Z20devFillAffectedIndexiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20devFillAffectedIndexiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20devFillAffectedIndexiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b68c_00000000-6_devFillAffectedIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi
.type _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi, @function
_Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20devFillAffectedIndexiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi, .-_Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi
.globl _Z20devFillAffectedIndexiiPi
.type _Z20devFillAffectedIndexiiPi, @function
_Z20devFillAffectedIndexiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20devFillAffectedIndexiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20devFillAffectedIndexiiPi, .-_Z20devFillAffectedIndexiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20devFillAffectedIndexiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20devFillAffectedIndexiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "devFillAffectedIndex.hip"
.globl _Z35__device_stub__devFillAffectedIndexiiPi # -- Begin function _Z35__device_stub__devFillAffectedIndexiiPi
.p2align 4, 0x90
.type _Z35__device_stub__devFillAffectedIndexiiPi,@function
_Z35__device_stub__devFillAffectedIndexiiPi: # @_Z35__device_stub__devFillAffectedIndexiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20devFillAffectedIndexiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__devFillAffectedIndexiiPi, .Lfunc_end0-_Z35__device_stub__devFillAffectedIndexiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20devFillAffectedIndexiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20devFillAffectedIndexiiPi,@object # @_Z20devFillAffectedIndexiiPi
.section .rodata,"a",@progbits
.globl _Z20devFillAffectedIndexiiPi
.p2align 3, 0x0
_Z20devFillAffectedIndexiiPi:
.quad _Z35__device_stub__devFillAffectedIndexiiPi
.size _Z20devFillAffectedIndexiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20devFillAffectedIndexiiPi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__devFillAffectedIndexiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20devFillAffectedIndexiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void getSortedDegree(int numNodes, int *offset, int *workspace1, int *workspace2, int *workspace3)
{
for(int i=blockDim.x*blockIdx.x+threadIdx.x; i<numNodes; i++)
{
// initiate all workspace to 0
workspace1[i] = 0;
workspace2[i] = 0;
workspace3[i] = 0;
// compute each neighlist's length
int neighlistLen=offset[i+1]-offset[i];
// group the nodes by their degree
if(neighlistLen >= 512) workspace1[i] = 1;
else if(neighlistLen > 32) workspace2[i] = 1;
else if(neighlistLen >0 && neighlistLen <= 32) workspace3[i] = 1;
}
}
__global__ void filter(int *predicateArray, int* scanArray, int *newPlace, int sizeScan)
{
for(int i=blockDim.x*blockIdx.x+threadIdx.x; i<sizeScan; i++)
{
if(predicateArray[i] ==1)
newPlace[scanArray[i]-1] = i;
}
} | code for sm_80
Function : _Z6filterPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fc800078e02ff */
/*0040*/ IMAD.IADD R2, R0, 0x1, R5 ; /* 0x0000000100027824 */
/* 0x002fca00078e0205 */
/*0050*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe200078e33ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R0, -R5.reuse, c[0x0][0x178], -R0 ; /* 0x00005e0005007a10 */
/* 0x040fe20007ffe900 */
/*00a0*/ BSSY B0, 0x2b0 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IADD3 R3, -R5, c[0x0][0x178], R3 ; /* 0x00005e0005037a10 */
/* 0x000fe40007ffe103 */
/*00c0*/ LOP3.LUT P1, R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe2000782c0ff */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0002 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fd60003f06070 */
/*00f0*/ @!P1 BRA 0x2a0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0120*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*0140*/ MOV R8, R5 ; /* 0x0000000500087202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0003 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0004 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0008 */
/*0190*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ ISETP.NE.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f25270 */
/*01b0*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff049224 */
/* 0x000fe400078e0009 */
/*01c0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff059224 */
/* 0x000fca00078e000a */
/*01d0*/ @!P1 LDG.E R2, [R4.64] ; /* 0x0000000404029981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R7, P2, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f5e0ff */
/*0210*/ ISETP.NE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f65270 */
/*0220*/ IADD3.X R8, RZ, R8, RZ, P2, !PT ; /* 0x00000008ff087210 */
/* 0x000fe400017fe4ff */
/*0230*/ @!P1 IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02029810 */
/* 0x004fca0007ffe0ff */
/*0240*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002029625 */
/* 0x000fca00078e0203 */
/*0250*/ @!P1 STG.E [R2.64], R0 ; /* 0x0000000002009986 */
/* 0x0001e2000c101904 */
/*0260*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fca0007f3e0ff */
/*0270*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0280*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x001fe20007ffe0ff */
/*0290*/ @P3 BRA 0x170 ; /* 0xfffffed000003947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*02e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*02f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0300*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0310*/ @!P0 LDG.E R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ea2000c1e1900 */
/*0320*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff078424 */
/* 0x000fe200078e00ff */
/*0330*/ @!P0 IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06068810 */
/* 0x004fca0007ffe0ff */
/*0340*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006068625 */
/* 0x000fca00078e0207 */
/*0350*/ @!P0 STG.E [R6.64], R0 ; /* 0x0000000006008986 */
/* 0x0001e8000c101904 */
/*0360*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea4000c1e1900 */
/*0370*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fda0003f05270 */
/*0380*/ @!P0 LDG.E R8, [R2.64+0x4] ; /* 0x0000040402088981 */
/* 0x000ea2000c1e1900 */
/*0390*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff098424 */
/* 0x000fe200078e00ff */
/*03a0*/ @!P0 IADD3 R11, R0, 0x1, RZ ; /* 0x00000001000b8810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ @!P0 IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08088810 */
/* 0x004fca0007ffe0ff */
/*03c0*/ @!P0 IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008088625 */
/* 0x000fca00078e0209 */
/*03d0*/ @!P0 STG.E [R8.64], R11 ; /* 0x0000000b08008986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x004fda0003f05270 */
/*0400*/ @!P0 LDG.E R6, [R2.64+0x8] ; /* 0x0000080402068981 */
/* 0x001ea2000c1e1900 */
/*0410*/ @!P0 MOV R7, 0x4 ; /* 0x0000000400078802 */
/* 0x000fe40000000f00 */
/*0420*/ @!P0 IADD3 R13, R0, 0x2, RZ ; /* 0x00000002000d8810 */
/* 0x000fe40007ffe0ff */
/*0430*/ @!P0 IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06068810 */
/* 0x004fca0007ffe0ff */
/*0440*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006068625 */
/* 0x000fca00078e0207 */
/*0450*/ @!P0 STG.E [R6.64], R13 ; /* 0x0000000d06008986 */
/* 0x0001e8000c101904 */
/*0460*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x004fda0003f05270 */
/*0480*/ @!P0 LDG.E R8, [R2.64+0xc] ; /* 0x00000c0402088981 */
/* 0x0022a2000c1e1900 */
/*0490*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff098424 */
/* 0x000fe200078e00ff */
/*04a0*/ @!P0 IADD3 R11, R0.reuse, 0x3, RZ ; /* 0x00000003000b8810 */
/* 0x040fe40007ffe0ff */
/*04b0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f3e0ff */
/*04d0*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x002fc60007f5e0ff */
/*04e0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*04f0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0500*/ @!P0 IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08088810 */
/* 0x004fca0007ffe0ff */
/*0510*/ @!P0 IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008088625 */
/* 0x000fca00078e0209 */
/*0520*/ @!P0 STG.E [R8.64], R11 ; /* 0x0000000b08008986 */
/* 0x0001e2000c101904 */
/*0530*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0540*/ @!P0 BRA 0x2f0 ; /* 0xfffffda000008947 */
/* 0x001fea000383ffff */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15getSortedDegreeiPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fc800078e02ff */
/*0040*/ IMAD.IADD R2, R0, 0x1, R7 ; /* 0x0000000100027824 */
/* 0x002fca00078e0207 */
/*0050*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, -R7, c[0x0][0x160], -R0 ; /* 0x0000580007037a10 */
/* 0x000fe20007ffe900 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*00a0*/ BSSY B0, 0x3e0 ; /* 0x0000033000007945 */
/* 0x000fe20003800000 */
/*00b0*/ LOP3.LUT P0, R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fe2000780c0ff */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0002 */
/*00d0*/ IADD3 R4, -R7, c[0x0][0x160], R4 ; /* 0x0000580007047a10 */
/* 0x000fd60007ffe104 */
/*00e0*/ @!P0 BRA 0x3d0 ; /* 0x000002e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e020b */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0003 */
/*0130*/ MOV R12, R2 ; /* 0x00000002000c7202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R2, R0, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020b */
/*0150*/ IMAD.WIDE R6, R0, R11, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fc800078e020b */
/*0160*/ IMAD.WIDE R8, R0, R11, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e020b */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e0003 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000c */
/*01a0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fe20000000f00 */
/*01b0*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0001e8000c101904 */
/*01c0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0001e8000c101904 */
/*01d0*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e8000c101904 */
/*01e0*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0210*/ BSSY B1, 0x340 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0220*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc40007ffe0ff */
/*0230*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0240*/ IMAD.IADD R12, R13, 0x1, -R12 ; /* 0x000000010d0c7824 */
/* 0x004fca00078e0a0c */
/*0250*/ ISETP.GT.AND P1, PT, R12, 0x1ff, PT ; /* 0x000001ff0c00780c */
/* 0x000fda0003f24270 */
/*0260*/ @P1 BRA 0x310 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0270*/ ISETP.GT.AND P1, PT, R12, 0x20, PT ; /* 0x000000200c00780c */
/* 0x001fda0003f24270 */
/*0280*/ @P1 BRA 0x2e0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f26270 */
/*02a0*/ @!P1 BRA 0x330 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fca00078e00ff */
/*02c0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e2000c101904 */
/*02d0*/ BRA 0x330 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fca00078e00ff */
/*02f0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e2000c101904 */
/*0300*/ BRA 0x330 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x001fca00078e00ff */
/*0320*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e4000c101904 */
/*0330*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe40007f5e0ff */
/*0350*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f7e0ff */
/*0360*/ IADD3 R10, P4, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007f9e0ff */
/*0370*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0380*/ IADD3 R12, P1, R2, 0x4, RZ ; /* 0x00000004020c7810 */
/* 0x000fe20007f3e0ff */
/*0390*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe400018e0609 */
/*03a0*/ IMAD.X R11, RZ, RZ, R11, P4 ; /* 0x000000ffff0b7224 */
/* 0x000fe200020e060b */
/*03b0*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe20000ffe4ff */
/*03c0*/ @P0 BRA 0x190 ; /* 0xfffffdc000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fda0003f06070 */
/*03f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0400*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0410*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fd20007ffe0ff */
/*0420*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*0430*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0440*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0450*/ IMAD.WIDE R2, R0, R9, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fc800078e0209 */
/*0460*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0209 */
/*0470*/ IMAD.WIDE R6, R0, R9, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0209 */
/*0480*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc60000000f00 */
/*0490*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*04b0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101904 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fc600078e000b */
/*04d0*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e8000c101904 */
/*04e0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0001e8000c101904 */
/*04f0*/ LDG.E R10, [R2.64+-0x4] ; /* 0xfffffc04020a7981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0510*/ BSSY B0, 0x620 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.IADD R10, R11, 0x1, -R10 ; /* 0x000000010b0a7824 */
/* 0x004fca00078e0a0a */
/*0530*/ ISETP.GT.AND P0, PT, R10, 0x1ff, PT ; /* 0x000001ff0a00780c */
/* 0x000fda0003f04270 */
/*0540*/ @P0 BRA 0x5f0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GT.AND P0, PT, R10, 0x20, PT ; /* 0x000000200a00780c */
/* 0x001fda0003f04270 */
/*0560*/ @P0 BRA 0x5c0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0580*/ @!P0 BRA 0x610 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0590*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0b7435 */
/* 0x000fce00000001ff */
/*05a0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e2000c101904 */
/*05b0*/ BRA 0x610 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*05c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fca00078e00ff */
/*05d0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e2000c101904 */
/*05e0*/ BRA 0x610 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x001fca00078e00ff */
/*0600*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ STG.E [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x0003e8000c101904 */
/*0630*/ STG.E [R6.64+0x4], RZ ; /* 0x000004ff06007986 */
/* 0x0003e8000c101904 */
/*0640*/ STG.E [R8.64+0x4], RZ ; /* 0x000004ff08007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x001ea2000c1e1900 */
/*0670*/ BSSY B0, 0x780 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0680*/ IMAD.IADD R10, R11, 0x1, -R10 ; /* 0x000000010b0a7824 */
/* 0x004fca00078e0a0a */
/*0690*/ ISETP.GT.AND P0, PT, R10, 0x1ff, PT ; /* 0x000001ff0a00780c */
/* 0x000fda0003f04270 */
/*06a0*/ @P0 BRA 0x750 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GT.AND P0, PT, R10, 0x20, PT ; /* 0x000000200a00780c */
/* 0x002fda0003f04270 */
/*06c0*/ @P0 BRA 0x720 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*06e0*/ @!P0 BRA 0x770 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*06f0*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fca0000000f00 */
/*0700*/ STG.E [R8.64+0x4], R11 ; /* 0x0000040b08007986 */
/* 0x0001e2000c101904 */
/*0710*/ BRA 0x770 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fca00078e00ff */
/*0730*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x0001e2000c101904 */
/*0740*/ BRA 0x770 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x002fca00078e00ff */
/*0760*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e4000c101904 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x0003e8000c101904 */
/*0790*/ STG.E [R6.64+0x8], RZ ; /* 0x000008ff06007986 */
/* 0x0003e8000c101904 */
/*07a0*/ STG.E [R8.64+0x8], RZ ; /* 0x000008ff08007986 */
/* 0x0003e8000c101904 */
/*07b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x001ea2000c1e1900 */
/*07d0*/ BSSY B0, 0x8e0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*07e0*/ IMAD.IADD R10, R11, 0x1, -R10 ; /* 0x000000010b0a7824 */
/* 0x004fca00078e0a0a */
/*07f0*/ ISETP.GT.AND P0, PT, R10, 0x1ff, PT ; /* 0x000001ff0a00780c */
/* 0x000fda0003f04270 */
/*0800*/ @P0 BRA 0x8b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GT.AND P0, PT, R10, 0x20, PT ; /* 0x000000200a00780c */
/* 0x002fda0003f04270 */
/*0820*/ @P0 BRA 0x880 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0840*/ @!P0 BRA 0x8d0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0850*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0b7435 */
/* 0x000fce00000001ff */
/*0860*/ STG.E [R8.64+0x8], R11 ; /* 0x0000080b08007986 */
/* 0x0001e2000c101904 */
/*0870*/ BRA 0x8d0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fca00078e00ff */
/*0890*/ STG.E [R6.64+0x8], R11 ; /* 0x0000080b06007986 */
/* 0x0001e2000c101904 */
/*08a0*/ BRA 0x8d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x002fca00078e00ff */
/*08c0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0001e4000c101904 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ STG.E [R4.64+0xc], RZ ; /* 0x00000cff04007986 */
/* 0x0003e8000c101904 */
/*08f0*/ STG.E [R6.64+0xc], RZ ; /* 0x00000cff06007986 */
/* 0x0003e8000c101904 */
/*0900*/ STG.E [R8.64+0xc], RZ ; /* 0x00000cff08007986 */
/* 0x0003e8000c101904 */
/*0910*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x001ea2000c1e1900 */
/*0930*/ BSSY B0, 0xa50 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0940*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0950*/ IMAD.IADD R10, R11, 0x1, -R10 ; /* 0x000000010b0a7824 */
/* 0x004fca00078e0a0a */
/*0960*/ ISETP.GT.AND P0, PT, R10, 0x1ff, PT ; /* 0x000001ff0a00780c */
/* 0x000fda0003f04270 */
/*0970*/ @P0 BRA 0xa20 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0980*/ ISETP.GT.AND P0, PT, R10, 0x20, PT ; /* 0x000000200a00780c */
/* 0x002fda0003f04270 */
/*0990*/ @P0 BRA 0x9f0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*09a0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*09b0*/ @!P0 BRA 0xa40 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*09c0*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fca0000000f00 */
/*09d0*/ STG.E [R8.64+0xc], R11 ; /* 0x00000c0b08007986 */
/* 0x0001e2000c101904 */
/*09e0*/ BRA 0xa40 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fca00078e00ff */
/*0a00*/ STG.E [R6.64+0xc], R11 ; /* 0x00000c0b06007986 */
/* 0x0001e2000c101904 */
/*0a10*/ BRA 0xa40 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a20*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x002fca00078e00ff */
/*0a30*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0001e4000c101904 */
/*0a40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06270 */
/*0a60*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fe40007f3e0ff */
/*0a70*/ IADD3 R6, P3, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x001fe40007f7e0ff */
/*0a80*/ IADD3 R4, P4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007f9e0ff */
/*0a90*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e0603 */
/*0aa0*/ IADD3 R8, P2, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007f5e0ff */
/*0ab0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe400018e0607 */
/*0ac0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*0ad0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200017fe4ff */
/*0ae0*/ @!P0 BRA 0x4a0 ; /* 0xfffff9b000008947 */
/* 0x000fea000383ffff */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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