system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cc_labelling.cuh"
constexpr int connectivity = 4;
__global__ void initialization_step(const int* nn_list, int* residual_list, int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
int label = i;
for (int j = i * connectivity; (j - i * connectivity) < connectivity; ++j)
{
int nn = nn_list[j];
if (nn == -1)
continue;
if (nn < label)
label = nn;
}
int pos = i * connectivity;
for (int j = i * connectivity; (j - i * connectivity) < connectivity; ++j)
{
int nn = nn_list[j];
if (nn == -1)
continue;
if (nn < i && nn != label)
residual_list[pos++] = nn;
}
// Assign label
labels[i] = label;
}
__global__ void analysis_step(int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
int last_label;
do
{
last_label = labels[i];
labels[i] = labels[labels[i]];
} while (labels[i] != last_label);
}
__global__ void reduction_step(const int* residual_list, int* labels, int height, int width)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
if (x >= width || y >= height)
return;
int i = x + y * width;
for (int j = i * connectivity; (j - i * connectivity) < connectivity && residual_list[j] != -1; ++j)
{
int label_1 = labels[i];
while (label_1 != labels[label_1])
label_1 = labels[label_1];
int residual_element = residual_list[j];
int label_2 = labels[residual_element];
while (label_2 != labels[label_2])
label_2 = labels[label_2];
bool flag = label_1 == label_2;
if (label_1 < label_2)
{
int tmp = label_1;
label_1 = label_2;
label_2 = tmp;
}
while (!flag)
{
int label_3 = atomicMin(&labels[label_1], label_2);
if (label_3 == label_2)
flag = true;
else if (label_3 > label_2)
label_1 = label_3;
else if (label_3 < label_2)
{
label_1 = label_2;
label_2 = label_3;
}
}
}
} | #pragma once
#include <hip/hip_runtime.h>
__global__ void initialization_step(const int* nn_list, int* residual_list, int* labels, int height, int width);
__global__ void analysis_step(int* labels, int height, int width);
__global__ void reduction_step(const int* residual_list, int* labels, int height, int width); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
__global__ void initialization_step(const int* nn_list, int* residual_list, int* labels, int height, int width);
__global__ void analysis_step(int* labels, int height, int width);
__global__ void reduction_step(const int* residual_list, int* labels, int height, int width); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
__global__ void initialization_step(const int* nn_list, int* residual_list, int* labels, int height, int width);
__global__ void analysis_step(int* labels, int height, int width);
__global__ void reduction_step(const int* residual_list, int* labels, int height, int width); | .text
.file "cc_labelling.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14reduction_stepPKiPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R5, R3, c[0x0][0x174], R0 ; /* 0x00005d0003057a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.SHL.U32 R3, R5, 0x4, RZ ; /* 0x0000000405037824 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0200 */
/*00f0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1900 */
/*0100*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0200 */
/*0130*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000162000c1e1900 */
/*0140*/ BSSY B0, 0x1d0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0150*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011408 */
/*0160*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x020fcc00078e0200 */
/*0170*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*0190*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*01b0*/ @P0 BRA 0x160 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ LEA R6, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008067a11 */
/* 0x000fc800078010ff */
/*01e0*/ LEA.HI.X R7, R8, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0008077a11 */
/* 0x000fca00000f140b */
/*01f0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000362000c1e1900 */
/*0200*/ BSSY B0, 0x280 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*0210*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x022fcc00078e0200 */
/*0220*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*0240*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*0260*/ @P0 BRA 0x210 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe20003f05270 */
/*0290*/ BSSY B0, 0x390 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*02a0*/ @!P0 BRA 0x380 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMNMX R9, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b097217 */
/* 0x0c0fe20003800200 */
/*02c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*02d0*/ IMNMX R8, R11, R10, !PT ; /* 0x0000000a0b087217 */
/* 0x000fca0007800200 */
/*02e0*/ IMAD.WIDE R6, R8, R0, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0200 */
/*02f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0300*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R6, [R6.64], R9 ; /* 0x00000009060679a8 */
/* 0x000ea400089ee3c4 */
/*0310*/ ISETP.NE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f25270 */
/*0320*/ @P1 ISETP.GE.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600120c */
/* 0x0c0fe40003f46270 */
/*0330*/ @P1 ISETP.GT.AND P0, PT, R6.reuse, R9, PT ; /* 0x000000090600120c */
/* 0x040fe40003f04270 */
/*0340*/ @P1 SEL R10, R9.reuse, R8, !P2 ; /* 0x00000008090a1207 */
/* 0x040fe40005000000 */
/*0350*/ @P1 IMNMX R9, R9, R6, PT ; /* 0x0000000609091217 */
/* 0x000fe40003800200 */
/*0360*/ @P1 SEL R8, R6, R10, P0 ; /* 0x0000000a06081207 */
/* 0x000fe20000000000 */
/*0370*/ @P1 BRA 0x2e0 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*03b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03c0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000362000c1e1900 */
/*03d0*/ BSSY B0, 0x460 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*03e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011408 */
/*03f0*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x020fcc00078e0200 */
/*0400*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*0420*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*0440*/ @P0 BRA 0x3f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ LEA R6, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008067a11 */
/* 0x000fc800078010ff */
/*0470*/ LEA.HI.X R7, R8, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0008077a11 */
/* 0x000fca00000f140b */
/*0480*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000562000c1e1900 */
/*0490*/ BSSY B0, 0x510 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*04a0*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x024fcc00078e0200 */
/*04b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*04d0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x004fe20003f05270 */
/*04e0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*04f0*/ @P0 BRA 0x4a0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.NE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe20003f05270 */
/*0520*/ BSSY B0, 0x620 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*0530*/ @!P0 BRA 0x610 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0540*/ IMNMX R9, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b097217 */
/* 0x0c0fe20003800200 */
/*0550*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0560*/ IMNMX R8, R11, R10, !PT ; /* 0x0000000a0b087217 */
/* 0x000fca0007800200 */
/*0570*/ IMAD.WIDE R6, R8, R0, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0200 */
/*0580*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0590*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R6, [R6.64], R9 ; /* 0x00000009060679a8 */
/* 0x000ea400089ee3c4 */
/*05a0*/ ISETP.NE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f25270 */
/*05b0*/ @P1 ISETP.GE.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600120c */
/* 0x0c0fe40003f46270 */
/*05c0*/ @P1 ISETP.GT.AND P0, PT, R6.reuse, R9, PT ; /* 0x000000090600120c */
/* 0x040fe40003f04270 */
/*05d0*/ @P1 SEL R10, R9.reuse, R8, !P2 ; /* 0x00000008090a1207 */
/* 0x040fe40005000000 */
/*05e0*/ @P1 IMNMX R9, R9, R6, PT ; /* 0x0000000609091217 */
/* 0x000fe40003800200 */
/*05f0*/ @P1 SEL R8, R6, R10, P0 ; /* 0x0000000a06081207 */
/* 0x000fe20000000000 */
/*0600*/ @P1 BRA 0x570 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000ea4000c1e1900 */
/*0630*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x004fda0003f05270 */
/*0640*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0650*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000562000c1e1900 */
/*0660*/ BSSY B0, 0x6f0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0670*/ SHF.R.S32.HI R11, RZ, 0x1f, R8 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011408 */
/*0680*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x020fcc00078e0200 */
/*0690*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0009 */
/*06b0*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x008fe20003f05270 */
/*06c0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*06d0*/ @P0 BRA 0x680 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ LEA R6, P0, R8, c[0x0][0x168], 0x2 ; /* 0x00005a0008067a11 */
/* 0x000fc800078010ff */
/*0700*/ LEA.HI.X R7, R8, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0008077a11 */
/* 0x000fca00000f140b */
/*0710*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000762000c1e1900 */
/*0720*/ BSSY B0, 0x7a0 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*0730*/ IMAD.WIDE R6, R9, R0, c[0x0][0x168] ; /* 0x00005a0009067625 */
/* 0x028fcc00078e0200 */
/*0740*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*0760*/ ISETP.NE.AND P0, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x008fe20003f05270 */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0006 */
/*0780*/ @P0 BRA 0x730 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.NE.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe20003f05270 */
/*07b0*/ BSSY B0, 0x8b0 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*07c0*/ @!P0 BRA 0x8a0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*07d0*/ IMNMX R9, R11.reuse, R10.reuse, PT ; /* 0x0000000a0b097217 */
/* 0x0c0fe20003800200 */
/*07e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*07f0*/ IMNMX R8, R11, R10, !PT ; /* 0x0000000a0b087217 */
/* 0x000fca0007800200 */
/*0800*/ IMAD.WIDE R6, R8, R0, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0200 */
/*0810*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0820*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R6, [R6.64], R9 ; /* 0x00000009060679a8 */
/* 0x000ee400089ee3c4 */
/*0830*/ ISETP.NE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x008fda0003f25270 */
/*0840*/ @P1 ISETP.GE.AND P2, PT, R6.reuse, R9.reuse, PT ; /* 0x000000090600120c */
/* 0x0c0fe40003f46270 */
/*0850*/ @P1 ISETP.GT.AND P0, PT, R6.reuse, R9, PT ; /* 0x000000090600120c */
/* 0x040fe40003f04270 */
/*0860*/ @P1 SEL R10, R9.reuse, R8, !P2 ; /* 0x00000008090a1207 */
/* 0x040fe40005000000 */
/*0870*/ @P1 IMNMX R9, R9, R6, PT ; /* 0x0000000609091217 */
/* 0x000fe40003800200 */
/*0880*/ @P1 SEL R8, R6, R10, P0 ; /* 0x0000000a06081207 */
/* 0x000fe20000000000 */
/*0890*/ @P1 BRA 0x800 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0402067981 */
/* 0x000ee4000c1e1900 */
/*08c0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x008fda0003f05270 */
/*08d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x007162000c1e1900 */
/*08f0*/ BSSY B0, 0x980 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0900*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*0910*/ IMAD.WIDE R2, R5, R0, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x020fcc00078e0200 */
/*0920*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0005 */
/*0940*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fe20003f05270 */
/*0950*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0002 */
/*0960*/ @P0 BRA 0x910 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0980*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0990*/ LEA.HI.X R3, R6, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fca00000f1407 */
/*09a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*09b0*/ BSSY B0, 0xa30 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*09c0*/ IMAD.WIDE R2, R5, R0, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x021fcc00078e0200 */
/*09d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*09f0*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fe20003f05270 */
/*0a00*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fd800078e0002 */
/*0a10*/ @P0 BRA 0x9c0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.NE.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f05270 */
/*0a40*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a50*/ IMNMX R5, R7.reuse, R4.reuse, PT ; /* 0x0000000407057217 */
/* 0x0c0fe40003800200 */
/*0a60*/ IMNMX R0, R7, R4, !PT ; /* 0x0000000407007217 */
/* 0x000fe20007800200 */
/*0a70*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0a80*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0207 */
/*0a90*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fea0003800000 */
/*0aa0*/ ATOMG.E.MIN.S32.STRONG.GPU PT, R2, [R2.64], R5 ; /* 0x00000005020279a8 */
/* 0x000ea400089ee3c4 */
/*0ab0*/ ISETP.NE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fda0003f25270 */
/*0ac0*/ @P1 ISETP.GE.AND P2, PT, R2.reuse, R5.reuse, PT ; /* 0x000000050200120c */
/* 0x0c0fe40003f46270 */
/*0ad0*/ @P1 ISETP.GT.AND P0, PT, R2.reuse, R5, PT ; /* 0x000000050200120c */
/* 0x040fe40003f04270 */
/*0ae0*/ @P1 SEL R4, R5.reuse, R0, !P2 ; /* 0x0000000005041207 */
/* 0x040fe40005000000 */
/*0af0*/ @P1 IMNMX R5, R5, R2, PT ; /* 0x0000000205051217 */
/* 0x000fe40003800200 */
/*0b00*/ @P1 SEL R0, R2, R4, P0 ; /* 0x0000000402001207 */
/* 0x000fe20000000000 */
/*0b10*/ @P1 BRA 0xa80 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0b20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13analysis_stepPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0206 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000164000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R0, R6, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x020fcc00078e0206 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0043e2000c101904 */
/*0120*/ ISETP.NE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f05270 */
/*0130*/ MOV R0, R5 ; /* 0x0000000500007202 */
/* 0x000fd60000000f00 */
/*0140*/ @P0 BRA 0xf0 ; /* 0xffffffa000000947 */
/* 0x002fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19initialization_stepPKiPiS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.SHL.U32 R5, R0, 0x4, RZ ; /* 0x0000000400057824 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.WIDE R2, R5, R19, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0213 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0120*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f62000c1e1900 */
/*0130*/ BSSY B0, 0x2c0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0005 */
/*0150*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fc80003f05270 */
/*0160*/ ISETP.LT.AND P0, PT, R7, R0.reuse, P0 ; /* 0x000000000700720c */
/* 0x080fe40000701270 */
/*0170*/ ISETP.NE.AND P1, PT, R13, -0x1, PT ; /* 0xffffffff0d00780c */
/* 0x008fe40003f25270 */
/*0180*/ SEL R4, R7, R0, P0 ; /* 0x0000000007047207 */
/* 0x000fe40000000000 */
/*0190*/ ISETP.NE.AND P0, PT, R9, -0x1, PT ; /* 0xffffffff0900780c */
/* 0x010fe40003f05270 */
/*01a0*/ ISETP.LT.AND P1, PT, R13, R4, P1 ; /* 0x000000040d00720c */
/* 0x000fc80000f21270 */
/*01b0*/ SEL R4, R13, R4, P1 ; /* 0x000000040d047207 */
/* 0x000fe40000800000 */
/*01c0*/ ISETP.NE.AND P1, PT, R11, -0x1, PT ; /* 0xffffffff0b00780c */
/* 0x020fe40003f25270 */
/*01d0*/ ISETP.LT.AND P0, PT, R9, R4, P0 ; /* 0x000000040900720c */
/* 0x000fc80000701270 */
/*01e0*/ SEL R4, R9, R4, P0 ; /* 0x0000000409047207 */
/* 0x000fe40000000000 */
/*01f0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f06270 */
/*0200*/ ISETP.LT.AND P1, PT, R11, R4, P1 ; /* 0x000000040b00720c */
/* 0x000fc80000f21270 */
/*0210*/ SEL R11, R11, R4, P1 ; /* 0x000000040b0b7207 */
/* 0x000fc80000800000 */
/*0220*/ ISETP.NE.AND P0, PT, R7, R11, !P0 ; /* 0x0000000b0700720c */
/* 0x000fc80004705270 */
/*0230*/ ISETP.NE.AND P0, PT, R7, -0x1, P0 ; /* 0xffffffff0700780c */
/* 0x000fda0000705270 */
/*0240*/ @!P0 BRA 0x2b0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0250*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe40000011405 */
/*0260*/ LEA R4, P0, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x000fc800078010ff */
/*0270*/ LEA.HI.X R5, R5, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0005057a11 */
/* 0x000fca00000f1408 */
/*0280*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000162000c1e1900 */
/*02a0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R13, R11, PT ; /* 0x0000000b0d00720c */
/* 0x020fc80003f05270 */
/*02d0*/ ISETP.GE.OR P0, PT, R13, R0, !P0 ; /* 0x000000000d00720c */
/* 0x000fc80004706670 */
/*02e0*/ ISETP.EQ.OR P0, PT, R13, -0x1, P0 ; /* 0xffffffff0d00780c */
/* 0x000fda0000702670 */
/*02f0*/ @!P0 IMAD.WIDE R4, R6, R19, c[0x0][0x168] ; /* 0x00005a0006048625 */
/* 0x001fca00078e0213 */
/*0300*/ @!P0 STG.E [R4.64], R13 ; /* 0x0000000d04008986 */
/* 0x0001e8000c101904 */
/*0310*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ @!P0 IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106078810 */
/* 0x000fca0007ffe0ff */
/*0330*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0007 */
/*0340*/ ISETP.NE.AND P1, PT, R15, R11, PT ; /* 0x0000000b0f00720c */
/* 0x004fc80003f25270 */
/*0350*/ ISETP.GE.OR P1, PT, R15, R0, !P1 ; /* 0x000000000f00720c */
/* 0x000fc80004f26670 */
/*0360*/ ISETP.EQ.OR P1, PT, R15, -0x1, P1 ; /* 0xffffffff0f00780c */
/* 0x000fda0000f22670 */
/*0370*/ @!P1 IMAD.WIDE R8, R6, R19, c[0x0][0x168] ; /* 0x00005a0006089625 */
/* 0x000fca00078e0213 */
/*0380*/ @!P1 STG.E [R8.64], R15 ; /* 0x0000000f08009986 */
/* 0x000fe8000c101904 */
/*0390*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ @!P1 IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106049810 */
/* 0x001fca0007ffe0ff */
/*03b0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0004 */
/*03c0*/ ISETP.NE.AND P0, PT, R17, R11, PT ; /* 0x0000000b1100720c */
/* 0x004fc80003f05270 */
/*03d0*/ ISETP.GE.OR P0, PT, R17, R0, !P0 ; /* 0x000000001100720c */
/* 0x000fc80004706670 */
/*03e0*/ ISETP.EQ.OR P0, PT, R17, -0x1, P0 ; /* 0xffffffff1100780c */
/* 0x000fda0000702670 */
/*03f0*/ @!P0 IMAD.WIDE R4, R6, R19, c[0x0][0x168] ; /* 0x00005a0006048625 */
/* 0x000fc800078e0213 */
/*0400*/ IMAD.WIDE R6, R0, R19, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0213 */
/*0410*/ @!P0 STG.E [R4.64], R17 ; /* 0x0000001104008986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c851_00000000-6_cc_labelling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii
.type _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii, @function
_Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19initialization_stepPKiPiS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii, .-_Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii
.globl _Z19initialization_stepPKiPiS1_ii
.type _Z19initialization_stepPKiPiS1_ii, @function
_Z19initialization_stepPKiPiS1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z19initialization_stepPKiPiS1_iiPKiPiS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19initialization_stepPKiPiS1_ii, .-_Z19initialization_stepPKiPiS1_ii
.globl _Z35__device_stub__Z13analysis_stepPiiiPiii
.type _Z35__device_stub__Z13analysis_stepPiiiPiii, @function
_Z35__device_stub__Z13analysis_stepPiiiPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13analysis_stepPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z13analysis_stepPiiiPiii, .-_Z35__device_stub__Z13analysis_stepPiiiPiii
.globl _Z13analysis_stepPiii
.type _Z13analysis_stepPiii, @function
_Z13analysis_stepPiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13analysis_stepPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13analysis_stepPiii, .-_Z13analysis_stepPiii
.globl _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii
.type _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii, @function
_Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14reduction_stepPKiPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii, .-_Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii
.globl _Z14reduction_stepPKiPiii
.type _Z14reduction_stepPKiPiii, @function
_Z14reduction_stepPKiPiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14reduction_stepPKiPiiiPKiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z14reduction_stepPKiPiii, .-_Z14reduction_stepPKiPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14reduction_stepPKiPiii"
.LC1:
.string "_Z13analysis_stepPiii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z19initialization_stepPKiPiS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14reduction_stepPKiPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13analysis_stepPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z19initialization_stepPKiPiS1_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cc_labelling.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KGaborFilter1(double* filter, double* Vr, int width, int height, double ss , double r0, double sr0, double stheta0 )
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
double x = i;
double y = j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
#define Eps 1E-6;
double r = sqrt(x*x+ y*y)+Eps;
double theta;
if (x>0) theta= atan2( y, x); else theta = PI/2;
//double ff = exp( cos(2*theta)/stheta0 )
// *
// exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*ss*r;
// Correction Jonathan 7-12-16
double ff = exp( cos(2*theta)/(4*pow(stheta0,2) ) )
*
exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*4*pow(ss*r,3);
filter[i+j*width] = ff;
if (i>0 || j>0) Vr[i+j*width] = ff/(4*pow(ss*r,3)); else Vr[i+j*width] = 0;
} | .file "tmpxft_000f1019_00000000-6_KGaborFilter1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd
.type _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd, @function
_Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13KGaborFilter1PdS_iidddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd, .-_Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd
.globl _Z13KGaborFilter1PdS_iidddd
.type _Z13KGaborFilter1PdS_iidddd, @function
_Z13KGaborFilter1PdS_iidddd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13KGaborFilter1PdS_iidddd, .-_Z13KGaborFilter1PdS_iidddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13KGaborFilter1PdS_iidddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13KGaborFilter1PdS_iidddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MaxThreadsY
.bss
.align 4
.type MaxThreadsY, @object
.size MaxThreadsY, 4
MaxThreadsY:
.zero 4
.globl MaxThreadsX
.align 4
.type MaxThreadsX, @object
.size MaxThreadsX, 4
MaxThreadsX:
.zero 4
.globl MaxThreadsPerBlock
.align 4
.type MaxThreadsPerBlock, @object
.size MaxThreadsPerBlock, 4
MaxThreadsPerBlock:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KGaborFilter1(double* filter, double* Vr, int width, int height, double ss , double r0, double sr0, double stheta0 )
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
double x = i;
double y = j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
#define Eps 1E-6;
double r = sqrt(x*x+ y*y)+Eps;
double theta;
if (x>0) theta= atan2( y, x); else theta = PI/2;
//double ff = exp( cos(2*theta)/stheta0 )
// *
// exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*ss*r;
// Correction Jonathan 7-12-16
double ff = exp( cos(2*theta)/(4*pow(stheta0,2) ) )
*
exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*4*pow(ss*r,3);
filter[i+j*width] = ff;
if (i>0 || j>0) Vr[i+j*width] = ff/(4*pow(ss*r,3)); else Vr[i+j*width] = 0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KGaborFilter1(double* filter, double* Vr, int width, int height, double ss , double r0, double sr0, double stheta0 )
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
double x = i;
double y = j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
#define Eps 1E-6;
double r = sqrt(x*x+ y*y)+Eps;
double theta;
if (x>0) theta= atan2( y, x); else theta = PI/2;
//double ff = exp( cos(2*theta)/stheta0 )
// *
// exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*ss*r;
// Correction Jonathan 7-12-16
double ff = exp( cos(2*theta)/(4*pow(stheta0,2) ) )
*
exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*4*pow(ss*r,3);
filter[i+j*width] = ff;
if (i>0 || j>0) Vr[i+j*width] = ff/(4*pow(ss*r,3)); else Vr[i+j*width] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KGaborFilter1(double* filter, double* Vr, int width, int height, double ss , double r0, double sr0, double stheta0 )
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
if (i >= width || j >= height) return;
double x = i;
double y = j;
if (i> width/2) x = width-i;
if (j> height/2) y = height-j;
#define Eps 1E-6;
double r = sqrt(x*x+ y*y)+Eps;
double theta;
if (x>0) theta= atan2( y, x); else theta = PI/2;
//double ff = exp( cos(2*theta)/stheta0 )
// *
// exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*ss*r;
// Correction Jonathan 7-12-16
double ff = exp( cos(2*theta)/(4*pow(stheta0,2) ) )
*
exp(-0.5*pow(log(r/r0),2)/log(1+pow(sr0,2))) * pow(r0/r,3)*4*pow(ss*r,3);
filter[i+j*width] = ff;
if (i>0 || j>0) Vr[i+j*width] = ff/(4*pow(ss*r,3)); else Vr[i+j*width] = 0;
} | .text
.file "KGaborFilter1.hip"
.globl _Z28__device_stub__KGaborFilter1PdS_iidddd # -- Begin function _Z28__device_stub__KGaborFilter1PdS_iidddd
.p2align 4, 0x90
.type _Z28__device_stub__KGaborFilter1PdS_iidddd,@function
_Z28__device_stub__KGaborFilter1PdS_iidddd: # @_Z28__device_stub__KGaborFilter1PdS_iidddd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movsd %xmm3, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13KGaborFilter1PdS_iidddd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z28__device_stub__KGaborFilter1PdS_iidddd, .Lfunc_end0-_Z28__device_stub__KGaborFilter1PdS_iidddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13KGaborFilter1PdS_iidddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type MaxThreadsPerBlock,@object # @MaxThreadsPerBlock
.bss
.globl MaxThreadsPerBlock
.p2align 2, 0x0
MaxThreadsPerBlock:
.long 0 # 0x0
.size MaxThreadsPerBlock, 4
.type MaxThreadsX,@object # @MaxThreadsX
.globl MaxThreadsX
.p2align 2, 0x0
MaxThreadsX:
.long 0 # 0x0
.size MaxThreadsX, 4
.type MaxThreadsY,@object # @MaxThreadsY
.globl MaxThreadsY
.p2align 2, 0x0
MaxThreadsY:
.long 0 # 0x0
.size MaxThreadsY, 4
.type _Z13KGaborFilter1PdS_iidddd,@object # @_Z13KGaborFilter1PdS_iidddd
.section .rodata,"a",@progbits
.globl _Z13KGaborFilter1PdS_iidddd
.p2align 3, 0x0
_Z13KGaborFilter1PdS_iidddd:
.quad _Z28__device_stub__KGaborFilter1PdS_iidddd
.size _Z13KGaborFilter1PdS_iidddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13KGaborFilter1PdS_iidddd"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__KGaborFilter1PdS_iidddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13KGaborFilter1PdS_iidddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f1019_00000000-6_KGaborFilter1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd
.type _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd, @function
_Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13KGaborFilter1PdS_iidddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd, .-_Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd
.globl _Z13KGaborFilter1PdS_iidddd
.type _Z13KGaborFilter1PdS_iidddd, @function
_Z13KGaborFilter1PdS_iidddd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13KGaborFilter1PdS_iiddddPdS_iidddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13KGaborFilter1PdS_iidddd, .-_Z13KGaborFilter1PdS_iidddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13KGaborFilter1PdS_iidddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13KGaborFilter1PdS_iidddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MaxThreadsY
.bss
.align 4
.type MaxThreadsY, @object
.size MaxThreadsY, 4
MaxThreadsY:
.zero 4
.globl MaxThreadsX
.align 4
.type MaxThreadsX, @object
.size MaxThreadsX, 4
MaxThreadsX:
.zero 4
.globl MaxThreadsPerBlock
.align 4
.type MaxThreadsPerBlock, @object
.size MaxThreadsPerBlock, 4
MaxThreadsPerBlock:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KGaborFilter1.hip"
.globl _Z28__device_stub__KGaborFilter1PdS_iidddd # -- Begin function _Z28__device_stub__KGaborFilter1PdS_iidddd
.p2align 4, 0x90
.type _Z28__device_stub__KGaborFilter1PdS_iidddd,@function
_Z28__device_stub__KGaborFilter1PdS_iidddd: # @_Z28__device_stub__KGaborFilter1PdS_iidddd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movsd %xmm3, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13KGaborFilter1PdS_iidddd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z28__device_stub__KGaborFilter1PdS_iidddd, .Lfunc_end0-_Z28__device_stub__KGaborFilter1PdS_iidddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13KGaborFilter1PdS_iidddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type MaxThreadsPerBlock,@object # @MaxThreadsPerBlock
.bss
.globl MaxThreadsPerBlock
.p2align 2, 0x0
MaxThreadsPerBlock:
.long 0 # 0x0
.size MaxThreadsPerBlock, 4
.type MaxThreadsX,@object # @MaxThreadsX
.globl MaxThreadsX
.p2align 2, 0x0
MaxThreadsX:
.long 0 # 0x0
.size MaxThreadsX, 4
.type MaxThreadsY,@object # @MaxThreadsY
.globl MaxThreadsY
.p2align 2, 0x0
MaxThreadsY:
.long 0 # 0x0
.size MaxThreadsY, 4
.type _Z13KGaborFilter1PdS_iidddd,@object # @_Z13KGaborFilter1PdS_iidddd
.section .rodata,"a",@progbits
.globl _Z13KGaborFilter1PdS_iidddd
.p2align 3, 0x0
_Z13KGaborFilter1PdS_iidddd:
.quad _Z28__device_stub__KGaborFilter1PdS_iidddd
.size _Z13KGaborFilter1PdS_iidddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13KGaborFilter1PdS_iidddd"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__KGaborFilter1PdS_iidddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13KGaborFilter1PdS_iidddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Projection(float2 *__restrict__ newVel, float2 *__restrict__ gradPressure, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
newVel[y*simWidth+x].x -= gradPressure[y*simWidth+x].x;
newVel[y*simWidth+x].y -= gradPressure[y*simWidth+x].y;
} | code for sm_80
Function : _Z10ProjectionP6float2S0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0005 */
/*00c0*/ LDG.E.64.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e9b00 */
/*00d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00e0*/ FADD R7, -R3, R7 ; /* 0x0000000703077221 */
/* 0x004fe40000000100 */
/*00f0*/ FADD R6, -R2, R6 ; /* 0x0000000602067221 */
/* 0x000fca0000000100 */
/*0100*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101b04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Projection(float2 *__restrict__ newVel, float2 *__restrict__ gradPressure, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
newVel[y*simWidth+x].x -= gradPressure[y*simWidth+x].x;
newVel[y*simWidth+x].y -= gradPressure[y*simWidth+x].y;
} | .file "tmpxft_000f8edc_00000000-6_Projection.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j
.type _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j, @function
_Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10ProjectionP6float2S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j, .-_Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j
.globl _Z10ProjectionP6float2S0_j
.type _Z10ProjectionP6float2S0_j, @function
_Z10ProjectionP6float2S0_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10ProjectionP6float2S0_j, .-_Z10ProjectionP6float2S0_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10ProjectionP6float2S0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ProjectionP6float2S0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Projection(float2 *__restrict__ newVel, float2 *__restrict__ gradPressure, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
newVel[y*simWidth+x].x -= gradPressure[y*simWidth+x].x;
newVel[y*simWidth+x].y -= gradPressure[y*simWidth+x].y;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Projection(float2 *__restrict__ newVel, float2 *__restrict__ gradPressure, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
newVel[y*simWidth+x].x -= gradPressure[y*simWidth+x].x;
newVel[y*simWidth+x].y -= gradPressure[y*simWidth+x].y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Projection(float2 *__restrict__ newVel, float2 *__restrict__ gradPressure, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
newVel[y*simWidth+x].x -= gradPressure[y*simWidth+x].x;
newVel[y*simWidth+x].y -= gradPressure[y*simWidth+x].y;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.globl _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.p2align 8
.type _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j,@function
_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mov_b32_e32 v1, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v2, v4, v2 :: v_dual_sub_f32 v3, v5, v3
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Projection(float2 *__restrict__ newVel, float2 *__restrict__ gradPressure, unsigned int simWidth)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
newVel[y*simWidth+x].x -= gradPressure[y*simWidth+x].x;
newVel[y*simWidth+x].y -= gradPressure[y*simWidth+x].y;
} | .text
.file "Projection.hip"
.globl _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j # -- Begin function _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.p2align 4, 0x90
.type _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j,@function
_Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j: # @_Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j,@object # @_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.section .rodata,"a",@progbits
.globl _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.p2align 3, 0x0
_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j:
.quad _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.size _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10ProjectionP6float2S0_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe400078e0005 */
/*00c0*/ LDG.E.64.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e9b00 */
/*00d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00e0*/ FADD R7, -R3, R7 ; /* 0x0000000703077221 */
/* 0x004fe40000000100 */
/*00f0*/ FADD R6, -R2, R6 ; /* 0x0000000602067221 */
/* 0x000fca0000000100 */
/*0100*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101b04 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.globl _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.p2align 8
.type _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j,@function
_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mov_b32_e32 v1, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v2, v4, v2 :: v_dual_sub_f32 v3, v5, v3
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f8edc_00000000-6_Projection.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j
.type _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j, @function
_Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10ProjectionP6float2S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j, .-_Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j
.globl _Z10ProjectionP6float2S0_j
.type _Z10ProjectionP6float2S0_j, @function
_Z10ProjectionP6float2S0_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z10ProjectionP6float2S0_jP6float2S0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10ProjectionP6float2S0_j, .-_Z10ProjectionP6float2S0_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10ProjectionP6float2S0_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ProjectionP6float2S0_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Projection.hip"
.globl _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j # -- Begin function _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.p2align 4, 0x90
.type _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j,@function
_Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j: # @_Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j, .Lfunc_end0-_Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j,@object # @_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.section .rodata,"a",@progbits
.globl _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.p2align 3, 0x0
_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j:
.quad _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.size _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10ProjectionP15HIP_vector_typeIfLj2EES1_j"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ProjectionP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ProjectionP15HIP_vector_typeIfLj2EES1_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
using namespace std;
// ----------------------------------------------------------------------------
#define checkLastError() { \
cudaError_t error = cudaGetLastError(); \
int id; \
cudaGetDevice(&id); \
if(error != cudaSuccess) { \
printf("Cuda failure error in file '%s' in line %i: '%s' at device %d \n", \
__FILE__,__LINE__, cudaGetErrorString(error), id); \
exit(EXIT_FAILURE); \
} \
}
// ----------------------------------------------------------------------------
__global__
void __convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
__shared__ float sharedMem[14][14][14];
int shared_index_1d, global_index_1d, index_1d;
// int2 shared_index_2d, global_index_2d, index_2d;
int3 shared_index_3d, global_index_3d, index_3d;
// Multi batch loading
int trial;
for(trial=0; trial <6; trial++)
{
shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
threadIdx.y * blockDim.x +
threadIdx.x +
blockDim.x * blockDim.y * blockDim.z * trial; // Next number of loading
shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
(shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
(shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
blockIdx.y * blockDim.y + shared_index_3d.y - 3,
blockIdx.z * blockDim.z + shared_index_3d.z - 3);
global_index_1d = global_index_3d.z * dimy * dimx +
global_index_3d.y * dimx +
global_index_3d.x;
if (shared_index_3d.z < (blockDim.z + 2*3))
{
if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
global_index_3d.y >= 0 && global_index_3d.y < dimy &&
global_index_3d.x >= 0 && global_index_3d.x < dimx )
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
else
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
}
__syncthreads();
}
// // First batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x;
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// __syncthreads();
// // Second batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x +
// blockDim.x * blockDim.y * blockDim.z; // Next number of loading
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (shared_index_3d.z < (blockDim.z + 2*3))
// {
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// }
// __syncthreads();
index_3d = make_int3(blockIdx.x * blockDim.x + threadIdx.x,
blockIdx.y * blockDim.y + threadIdx.y,
blockIdx.z * blockDim.z + threadIdx.z);
index_1d = index_3d.z * dimy * dimx +
index_3d.y * dimx +
index_3d.x;
// Store back
if (index_3d.z < dimz &&
index_3d.y < dimy &&
index_3d.x < dimx)
dst[index_1d] = sharedMem[threadIdx.z+3][threadIdx.y+3][threadIdx.x+3];
}
void convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
dim3 numBlocks((dimx/8 + ((dimx%8)?1:0)),
(dimy/8 + ((dimy%8)?1:0)),
(dimz/8 + ((dimz%8)?1:0)));
dim3 numThreads(8, 8, 8);
__convolution<<<numBlocks, numThreads>>>(src, dst, dimx, dimy, dimz);
}
// ----------------------------------------------------------------------------
int main(int argc, char** argv)
{
srand(time(NULL)); // for random number generator
// Specify dimensions
const int dimx = 100;
const int dimy = 100;
const int dimz = 100;
const int total = dimx*dimy*dimz;
// Allocate host memory
float *h_src = new float[total];
float *h_dst = new float[total];
// Allocate device memory
float *d_src;
float *d_dst;
cudaMalloc((void**)&d_src, total*sizeof(float)); checkLastError();
cudaMalloc((void**)&d_dst, total*sizeof(float)); checkLastError();
// Initialize the image source
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
h_src[z*dimy*dimx+y*dimx+x] = (float)rand();
}
}
}
// Transferring to the device memory
cudaMemcpy(d_src, h_src, total*sizeof(float), cudaMemcpyHostToDevice); checkLastError();
convolution(d_src, d_dst, dimx, dimy, dimz);
cudaMemcpy(h_dst, d_dst, total*sizeof(float), cudaMemcpyDeviceToHost); checkLastError();
// Verify the result
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
if(h_src[z*dimy*dimx+y*dimx+x] != h_dst[z*dimy*dimx+y*dimx+x])
{
printf("Solution doesnot match at x: %d, y: %d, z: %d\n", x, y, z);
goto cleanup;
}
// else
// printf("Solution match at x: %d, y: %d, z: %d\n", x, y, z);
}
}
}
printf("Solution is correct.\n");
cleanup:
cudaFree(d_src);
cudaFree(d_dst);
free(h_src);
free(h_dst);
return 0;
} | .file "tmpxft_000ce67e_00000000-6_cuda-convolution.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
.type _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii, @function
_Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13__convolutionPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii, .-_Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
.globl _Z13__convolutionPfS_iii
.type _Z13__convolutionPfS_iii, @function
_Z13__convolutionPfS_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z13__convolutionPfS_iii, .-_Z13__convolutionPfS_iii
.globl _Z11convolutionPfS_iii
.type _Z11convolutionPfS_iii, @function
_Z11convolutionPfS_iii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r14
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
testb $7, %dl
setne %dl
movzbl %dl, %edx
leal 7(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $3, %eax
addl %edx, %eax
movl %eax, 8(%rsp)
testb $7, %cl
setne %dl
movzbl %dl, %edx
leal 7(%rcx), %eax
testl %ecx, %ecx
cmovns %ecx, %eax
sarl $3, %eax
addl %edx, %eax
movl %eax, 12(%rsp)
testb $7, %r8b
setne %sil
movzbl %sil, %esi
leal 7(%r8), %eax
testl %r8d, %r8d
cmovns %r8d, %eax
sarl $3, %eax
addl %eax, %esi
movl $8, 20(%rsp)
movl $8, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $8, %ecx
movq 8(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
jmp .L11
.cfi_endproc
.LFE3669:
.size _Z11convolutionPfS_iii, .-_Z11convolutionPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/tmquan/hetero/master/samples/cuda/convolution/cuda-convolution.cu"
.align 8
.LC1:
.string "Cuda failure error in file '%s' in line %i: '%s' at device %d \n"
.align 8
.LC2:
.string "Solution doesnot match at x: %d, y: %d, z: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Solution is correct.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r13
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 16(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L38
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L39
leaq 400(%r13), %r12
leaq 4000400(%r13), %r15
jmp .L18
.L38:
movl 16(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $143, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl 4(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $144, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
addq $400, %rbp
cmpq %r12, %rbp
je .L20
.L22:
leaq -400(%rbp), %rbx
.L19:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
jmp .L40
.L20:
cmpq %r12, %r15
je .L21
.L18:
movq %r12, %rbp
addq $40000, %r12
jmp .L22
.L21:
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L41
movl $100, %r8d
movl $100, %ecx
movl $100, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z11convolutionPfS_iii
movl $2, %ecx
movl $4000000, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L42
movl $0, %esi
movl $0, %r8d
.L25:
movq %rsi, %rdx
movl $0, %ecx
.L32:
movl $0, %eax
leaq 0(%r13,%rdx), %r9
leaq (%r14,%rdx), %rdi
.L29:
movss (%r9,%rax,4), %xmm0
ucomiss (%rdi,%rax,4), %xmm0
jp .L34
jne .L34
addq $1, %rax
cmpq $100, %rax
jne .L29
addl $1, %ecx
addq $400, %rdx
cmpl $100, %ecx
jne .L32
addl $1, %r8d
addq $40000, %rsi
cmpl $100, %r8d
jne .L25
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L41:
movl 4(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $158, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl 4(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $162, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13__convolutionPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13__convolutionPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <time.h>
using namespace std;
// ----------------------------------------------------------------------------
#define checkLastError() { \
cudaError_t error = cudaGetLastError(); \
int id; \
cudaGetDevice(&id); \
if(error != cudaSuccess) { \
printf("Cuda failure error in file '%s' in line %i: '%s' at device %d \n", \
__FILE__,__LINE__, cudaGetErrorString(error), id); \
exit(EXIT_FAILURE); \
} \
}
// ----------------------------------------------------------------------------
__global__
void __convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
__shared__ float sharedMem[14][14][14];
int shared_index_1d, global_index_1d, index_1d;
// int2 shared_index_2d, global_index_2d, index_2d;
int3 shared_index_3d, global_index_3d, index_3d;
// Multi batch loading
int trial;
for(trial=0; trial <6; trial++)
{
shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
threadIdx.y * blockDim.x +
threadIdx.x +
blockDim.x * blockDim.y * blockDim.z * trial; // Next number of loading
shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
(shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
(shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
blockIdx.y * blockDim.y + shared_index_3d.y - 3,
blockIdx.z * blockDim.z + shared_index_3d.z - 3);
global_index_1d = global_index_3d.z * dimy * dimx +
global_index_3d.y * dimx +
global_index_3d.x;
if (shared_index_3d.z < (blockDim.z + 2*3))
{
if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
global_index_3d.y >= 0 && global_index_3d.y < dimy &&
global_index_3d.x >= 0 && global_index_3d.x < dimx )
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
else
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
}
__syncthreads();
}
// // First batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x;
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// __syncthreads();
// // Second batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x +
// blockDim.x * blockDim.y * blockDim.z; // Next number of loading
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (shared_index_3d.z < (blockDim.z + 2*3))
// {
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// }
// __syncthreads();
index_3d = make_int3(blockIdx.x * blockDim.x + threadIdx.x,
blockIdx.y * blockDim.y + threadIdx.y,
blockIdx.z * blockDim.z + threadIdx.z);
index_1d = index_3d.z * dimy * dimx +
index_3d.y * dimx +
index_3d.x;
// Store back
if (index_3d.z < dimz &&
index_3d.y < dimy &&
index_3d.x < dimx)
dst[index_1d] = sharedMem[threadIdx.z+3][threadIdx.y+3][threadIdx.x+3];
}
void convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
dim3 numBlocks((dimx/8 + ((dimx%8)?1:0)),
(dimy/8 + ((dimy%8)?1:0)),
(dimz/8 + ((dimz%8)?1:0)));
dim3 numThreads(8, 8, 8);
__convolution<<<numBlocks, numThreads>>>(src, dst, dimx, dimy, dimz);
}
// ----------------------------------------------------------------------------
int main(int argc, char** argv)
{
srand(time(NULL)); // for random number generator
// Specify dimensions
const int dimx = 100;
const int dimy = 100;
const int dimz = 100;
const int total = dimx*dimy*dimz;
// Allocate host memory
float *h_src = new float[total];
float *h_dst = new float[total];
// Allocate device memory
float *d_src;
float *d_dst;
cudaMalloc((void**)&d_src, total*sizeof(float)); checkLastError();
cudaMalloc((void**)&d_dst, total*sizeof(float)); checkLastError();
// Initialize the image source
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
h_src[z*dimy*dimx+y*dimx+x] = (float)rand();
}
}
}
// Transferring to the device memory
cudaMemcpy(d_src, h_src, total*sizeof(float), cudaMemcpyHostToDevice); checkLastError();
convolution(d_src, d_dst, dimx, dimy, dimz);
cudaMemcpy(h_dst, d_dst, total*sizeof(float), cudaMemcpyDeviceToHost); checkLastError();
// Verify the result
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
if(h_src[z*dimy*dimx+y*dimx+x] != h_dst[z*dimy*dimx+y*dimx+x])
{
printf("Solution doesnot match at x: %d, y: %d, z: %d\n", x, y, z);
goto cleanup;
}
// else
// printf("Solution match at x: %d, y: %d, z: %d\n", x, y, z);
}
}
}
printf("Solution is correct.\n");
cleanup:
cudaFree(d_src);
cudaFree(d_dst);
free(h_src);
free(h_dst);
return 0;
} | #include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
using namespace std;
// ----------------------------------------------------------------------------
#define checkLastError() { \
hipError_t error = hipGetLastError(); \
int id; \
hipGetDevice(&id); \
if(error != hipSuccess) { \
printf("Cuda failure error in file '%s' in line %i: '%s' at device %d \n", \
__FILE__,__LINE__, hipGetErrorString(error), id); \
exit(EXIT_FAILURE); \
} \
}
// ----------------------------------------------------------------------------
__global__
void __convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
__shared__ float sharedMem[14][14][14];
int shared_index_1d, global_index_1d, index_1d;
// int2 shared_index_2d, global_index_2d, index_2d;
int3 shared_index_3d, global_index_3d, index_3d;
// Multi batch loading
int trial;
for(trial=0; trial <6; trial++)
{
shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
threadIdx.y * blockDim.x +
threadIdx.x +
blockDim.x * blockDim.y * blockDim.z * trial; // Next number of loading
shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
(shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
(shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
blockIdx.y * blockDim.y + shared_index_3d.y - 3,
blockIdx.z * blockDim.z + shared_index_3d.z - 3);
global_index_1d = global_index_3d.z * dimy * dimx +
global_index_3d.y * dimx +
global_index_3d.x;
if (shared_index_3d.z < (blockDim.z + 2*3))
{
if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
global_index_3d.y >= 0 && global_index_3d.y < dimy &&
global_index_3d.x >= 0 && global_index_3d.x < dimx )
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
else
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
}
__syncthreads();
}
// // First batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x;
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// __syncthreads();
// // Second batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x +
// blockDim.x * blockDim.y * blockDim.z; // Next number of loading
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (shared_index_3d.z < (blockDim.z + 2*3))
// {
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// }
// __syncthreads();
index_3d = make_int3(blockIdx.x * blockDim.x + threadIdx.x,
blockIdx.y * blockDim.y + threadIdx.y,
blockIdx.z * blockDim.z + threadIdx.z);
index_1d = index_3d.z * dimy * dimx +
index_3d.y * dimx +
index_3d.x;
// Store back
if (index_3d.z < dimz &&
index_3d.y < dimy &&
index_3d.x < dimx)
dst[index_1d] = sharedMem[threadIdx.z+3][threadIdx.y+3][threadIdx.x+3];
}
void convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
dim3 numBlocks((dimx/8 + ((dimx%8)?1:0)),
(dimy/8 + ((dimy%8)?1:0)),
(dimz/8 + ((dimz%8)?1:0)));
dim3 numThreads(8, 8, 8);
__convolution<<<numBlocks, numThreads>>>(src, dst, dimx, dimy, dimz);
}
// ----------------------------------------------------------------------------
int main(int argc, char** argv)
{
srand(time(NULL)); // for random number generator
// Specify dimensions
const int dimx = 100;
const int dimy = 100;
const int dimz = 100;
const int total = dimx*dimy*dimz;
// Allocate host memory
float *h_src = new float[total];
float *h_dst = new float[total];
// Allocate device memory
float *d_src;
float *d_dst;
hipMalloc((void**)&d_src, total*sizeof(float)); checkLastError();
hipMalloc((void**)&d_dst, total*sizeof(float)); checkLastError();
// Initialize the image source
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
h_src[z*dimy*dimx+y*dimx+x] = (float)rand();
}
}
}
// Transferring to the device memory
hipMemcpy(d_src, h_src, total*sizeof(float), hipMemcpyHostToDevice); checkLastError();
convolution(d_src, d_dst, dimx, dimy, dimz);
hipMemcpy(h_dst, d_dst, total*sizeof(float), hipMemcpyDeviceToHost); checkLastError();
// Verify the result
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
if(h_src[z*dimy*dimx+y*dimx+x] != h_dst[z*dimy*dimx+y*dimx+x])
{
printf("Solution doesnot match at x: %d, y: %d, z: %d\n", x, y, z);
goto cleanup;
}
// else
// printf("Solution match at x: %d, y: %d, z: %d\n", x, y, z);
}
}
}
printf("Solution is correct.\n");
cleanup:
hipFree(d_src);
hipFree(d_dst);
free(h_src);
free(h_dst);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
using namespace std;
// ----------------------------------------------------------------------------
#define checkLastError() { \
hipError_t error = hipGetLastError(); \
int id; \
hipGetDevice(&id); \
if(error != hipSuccess) { \
printf("Cuda failure error in file '%s' in line %i: '%s' at device %d \n", \
__FILE__,__LINE__, hipGetErrorString(error), id); \
exit(EXIT_FAILURE); \
} \
}
// ----------------------------------------------------------------------------
__global__
void __convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
__shared__ float sharedMem[14][14][14];
int shared_index_1d, global_index_1d, index_1d;
// int2 shared_index_2d, global_index_2d, index_2d;
int3 shared_index_3d, global_index_3d, index_3d;
// Multi batch loading
int trial;
for(trial=0; trial <6; trial++)
{
shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
threadIdx.y * blockDim.x +
threadIdx.x +
blockDim.x * blockDim.y * blockDim.z * trial; // Next number of loading
shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
(shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
(shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
blockIdx.y * blockDim.y + shared_index_3d.y - 3,
blockIdx.z * blockDim.z + shared_index_3d.z - 3);
global_index_1d = global_index_3d.z * dimy * dimx +
global_index_3d.y * dimx +
global_index_3d.x;
if (shared_index_3d.z < (blockDim.z + 2*3))
{
if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
global_index_3d.y >= 0 && global_index_3d.y < dimy &&
global_index_3d.x >= 0 && global_index_3d.x < dimx )
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
else
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
}
__syncthreads();
}
// // First batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x;
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// __syncthreads();
// // Second batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x +
// blockDim.x * blockDim.y * blockDim.z; // Next number of loading
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (shared_index_3d.z < (blockDim.z + 2*3))
// {
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// }
// __syncthreads();
index_3d = make_int3(blockIdx.x * blockDim.x + threadIdx.x,
blockIdx.y * blockDim.y + threadIdx.y,
blockIdx.z * blockDim.z + threadIdx.z);
index_1d = index_3d.z * dimy * dimx +
index_3d.y * dimx +
index_3d.x;
// Store back
if (index_3d.z < dimz &&
index_3d.y < dimy &&
index_3d.x < dimx)
dst[index_1d] = sharedMem[threadIdx.z+3][threadIdx.y+3][threadIdx.x+3];
}
void convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
dim3 numBlocks((dimx/8 + ((dimx%8)?1:0)),
(dimy/8 + ((dimy%8)?1:0)),
(dimz/8 + ((dimz%8)?1:0)));
dim3 numThreads(8, 8, 8);
__convolution<<<numBlocks, numThreads>>>(src, dst, dimx, dimy, dimz);
}
// ----------------------------------------------------------------------------
int main(int argc, char** argv)
{
srand(time(NULL)); // for random number generator
// Specify dimensions
const int dimx = 100;
const int dimy = 100;
const int dimz = 100;
const int total = dimx*dimy*dimz;
// Allocate host memory
float *h_src = new float[total];
float *h_dst = new float[total];
// Allocate device memory
float *d_src;
float *d_dst;
hipMalloc((void**)&d_src, total*sizeof(float)); checkLastError();
hipMalloc((void**)&d_dst, total*sizeof(float)); checkLastError();
// Initialize the image source
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
h_src[z*dimy*dimx+y*dimx+x] = (float)rand();
}
}
}
// Transferring to the device memory
hipMemcpy(d_src, h_src, total*sizeof(float), hipMemcpyHostToDevice); checkLastError();
convolution(d_src, d_dst, dimx, dimy, dimz);
hipMemcpy(h_dst, d_dst, total*sizeof(float), hipMemcpyDeviceToHost); checkLastError();
// Verify the result
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
if(h_src[z*dimy*dimx+y*dimx+x] != h_dst[z*dimy*dimx+y*dimx+x])
{
printf("Solution doesnot match at x: %d, y: %d, z: %d\n", x, y, z);
goto cleanup;
}
// else
// printf("Solution match at x: %d, y: %d, z: %d\n", x, y, z);
}
}
}
printf("Solution is correct.\n");
cleanup:
hipFree(d_src);
hipFree(d_dst);
free(h_src);
free(h_dst);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13__convolutionPfS_iii
.globl _Z13__convolutionPfS_iii
.p2align 8
.type _Z13__convolutionPfS_iii,@function
_Z13__convolutionPfS_iii:
s_load_b64 s[2:3], s[0:1], 0x2c
v_and_b32_e32 v5, 0x3ff, v0
s_mov_b32 s11, 6
s_waitcnt lgkmcnt(0)
s_lshr_b32 s18, s2, 16
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s18, 6
s_add_i32 s8, s2, 6
s_and_b32 s3, s3, 0xffff
s_mul_i32 s9, s8, s4
v_cvt_f32_u32_e32 v1, s8
v_cvt_f32_u32_e32 v2, s9
s_sub_i32 s12, 0, s9
s_sub_i32 s16, 0, s8
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x18
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_mul_i32 s17, s15, s3
s_mul_i32 s19, s3, s18
s_add_i32 s17, s17, -3
s_mul_i32 s19, s19, s2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v7, v1
v_cvt_u32_f32_e32 v6, v2
v_bfe_u32 v1, v0, 10, 10
v_bfe_u32 v2, v0, 20, 10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_lo_u32 v4, s16, v7
v_mul_lo_u32 v3, s12, v6
s_mul_i32 s12, s13, s2
s_delay_alu instid0(VALU_DEP_3)
v_mad_u32_u24 v8, v2, s18, v1
s_mul_i32 s16, s14, s18
s_add_i32 s12, s12, -3
s_add_i32 s16, s16, -3
s_add_i32 s18, s3, 6
v_mul_hi_u32 v10, v7, v4
v_mul_hi_u32 v9, v6, v3
v_mad_u64_u32 v[3:4], null, v8, s2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, v7, v10
v_add_nc_u32_e32 v6, v6, v9
s_branch .LBB0_5
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s22
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s21
v_mul_lo_u32 v4, v9, 56
v_mul_lo_u32 v5, v8, 0x310
v_lshlrev_b32_e32 v8, 2, v10
v_add3_u32 v4, v5, v4, v8
s_waitcnt vmcnt(0)
ds_store_b32 v4, v11
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v3, s19, v3
s_add_i32 s11, s11, -1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s11, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v6
s_mov_b32 s20, exec_lo
v_mul_lo_u32 v5, v4, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v3, v5
v_subrev_nc_u32_e32 v9, s9, v5
v_cmp_le_u32_e32 vcc_lo, s9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v9 :: v_dual_add_nc_u32 v8, 1, v4
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s9, v5
v_add_nc_u32_e32 v8, 1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v4, v8, vcc_lo
v_cmpx_gt_u32_e64 s18, v8
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v4, v8, s9
s_mov_b32 s21, exec_lo
v_add_nc_u32_e32 v12, s17, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v3, v4
v_mad_u64_u32 v[4:5], null, v10, v7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v5, s8
v_sub_nc_u32_e32 v4, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s8, v4
v_cmp_le_u32_e32 vcc_lo, s8, v4
v_dual_cndmask_b32 v4, v4, v11 :: v_dual_add_nc_u32 v9, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v9, vcc_lo
v_mov_b32_e32 v11, -1.0
v_cmp_le_u32_e32 vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, 1, v5
v_cndmask_b32_e32 v9, v5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v9, s8
v_sub_nc_u32_e32 v10, v10, v4
v_cmpx_lt_i32_e32 -1, v12
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v11, -1.0 :: v_dual_add_nc_u32 v4, s16, v9
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s2, -1, v4
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s22, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, s12, v10
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_mov_b32_e32 v11, -1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s4, v5
v_cmp_lt_i32_e64 s3, -1, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_1
v_mad_u64_u32 v[13:14], null, v12, s5, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, s4, v[5:6]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[11:12]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v11, v[4:5], off
s_branch .LBB0_1
.LBB0_10:
s_load_b64 s[2:3], s[0:1], 0x2c
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[5:6], null, s15, s3, v[2:3]
v_mad_u64_u32 v[6:7], null, s14, s2, v[1:2]
v_mad_u64_u32 v[3:4], null, s13, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s10, v5
v_cmp_gt_i32_e64 s2, s5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s3, s4, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[7:8], null, v5, s5, v[6:7]
v_mul_u32_u24_e32 v4, 56, v1
v_mul_u32_u24_e32 v2, 0x310, v2
v_lshlrev_b32_e32 v5, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v7, s4, v[3:4]
v_add3_u32 v1, v2, v4, v5
ds_load_b32 v2, v1 offset:2532
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13__convolutionPfS_iii
.amdhsa_group_segment_fixed_size 10976
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13__convolutionPfS_iii, .Lfunc_end0-_Z13__convolutionPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 10976
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13__convolutionPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z13__convolutionPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
using namespace std;
// ----------------------------------------------------------------------------
#define checkLastError() { \
hipError_t error = hipGetLastError(); \
int id; \
hipGetDevice(&id); \
if(error != hipSuccess) { \
printf("Cuda failure error in file '%s' in line %i: '%s' at device %d \n", \
__FILE__,__LINE__, hipGetErrorString(error), id); \
exit(EXIT_FAILURE); \
} \
}
// ----------------------------------------------------------------------------
__global__
void __convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
__shared__ float sharedMem[14][14][14];
int shared_index_1d, global_index_1d, index_1d;
// int2 shared_index_2d, global_index_2d, index_2d;
int3 shared_index_3d, global_index_3d, index_3d;
// Multi batch loading
int trial;
for(trial=0; trial <6; trial++)
{
shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
threadIdx.y * blockDim.x +
threadIdx.x +
blockDim.x * blockDim.y * blockDim.z * trial; // Next number of loading
shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
(shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
(shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
blockIdx.y * blockDim.y + shared_index_3d.y - 3,
blockIdx.z * blockDim.z + shared_index_3d.z - 3);
global_index_1d = global_index_3d.z * dimy * dimx +
global_index_3d.y * dimx +
global_index_3d.x;
if (shared_index_3d.z < (blockDim.z + 2*3))
{
if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
global_index_3d.y >= 0 && global_index_3d.y < dimy &&
global_index_3d.x >= 0 && global_index_3d.x < dimx )
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
else
sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
}
__syncthreads();
}
// // First batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x;
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// __syncthreads();
// // Second batch loading
// shared_index_1d = threadIdx.z * blockDim.y * blockDim.x +
// threadIdx.y * blockDim.x +
// threadIdx.x +
// blockDim.x * blockDim.y * blockDim.z; // Next number of loading
// shared_index_3d = make_int3((shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) % (blockDim.x+2*3),
// (shared_index_1d % ((blockDim.y+2*3) * (blockDim.x+2*3))) / (blockDim.x+2*3),
// (shared_index_1d / ((blockDim.y+2*3) * (blockDim.x+2*3))) );
// global_index_3d = make_int3(blockIdx.x * blockDim.x + shared_index_3d.x - 3,
// blockIdx.y * blockDim.y + shared_index_3d.y - 3,
// blockIdx.z * blockDim.z + shared_index_3d.z - 3);
// global_index_1d = global_index_3d.z * dimy * dimx +
// global_index_3d.y * dimx +
// global_index_3d.x;
// if (shared_index_3d.z < (blockDim.z + 2*3))
// {
// if (global_index_3d.z >= 0 && global_index_3d.z < dimz &&
// global_index_3d.y >= 0 && global_index_3d.y < dimy &&
// global_index_3d.x >= 0 && global_index_3d.x < dimx )
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = src[global_index_1d];
// else
// sharedMem[shared_index_3d.z][shared_index_3d.y][shared_index_3d.x] = -1;
// }
// __syncthreads();
index_3d = make_int3(blockIdx.x * blockDim.x + threadIdx.x,
blockIdx.y * blockDim.y + threadIdx.y,
blockIdx.z * blockDim.z + threadIdx.z);
index_1d = index_3d.z * dimy * dimx +
index_3d.y * dimx +
index_3d.x;
// Store back
if (index_3d.z < dimz &&
index_3d.y < dimy &&
index_3d.x < dimx)
dst[index_1d] = sharedMem[threadIdx.z+3][threadIdx.y+3][threadIdx.x+3];
}
void convolution(float *src, float *dst, int dimx, int dimy, int dimz)
{
dim3 numBlocks((dimx/8 + ((dimx%8)?1:0)),
(dimy/8 + ((dimy%8)?1:0)),
(dimz/8 + ((dimz%8)?1:0)));
dim3 numThreads(8, 8, 8);
__convolution<<<numBlocks, numThreads>>>(src, dst, dimx, dimy, dimz);
}
// ----------------------------------------------------------------------------
int main(int argc, char** argv)
{
srand(time(NULL)); // for random number generator
// Specify dimensions
const int dimx = 100;
const int dimy = 100;
const int dimz = 100;
const int total = dimx*dimy*dimz;
// Allocate host memory
float *h_src = new float[total];
float *h_dst = new float[total];
// Allocate device memory
float *d_src;
float *d_dst;
hipMalloc((void**)&d_src, total*sizeof(float)); checkLastError();
hipMalloc((void**)&d_dst, total*sizeof(float)); checkLastError();
// Initialize the image source
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
h_src[z*dimy*dimx+y*dimx+x] = (float)rand();
}
}
}
// Transferring to the device memory
hipMemcpy(d_src, h_src, total*sizeof(float), hipMemcpyHostToDevice); checkLastError();
convolution(d_src, d_dst, dimx, dimy, dimz);
hipMemcpy(h_dst, d_dst, total*sizeof(float), hipMemcpyDeviceToHost); checkLastError();
// Verify the result
for(int z=0; z<dimz; z++)
{
for(int y=0; y<dimy; y++)
{
for(int x=0; x<dimx; x++)
{
if(h_src[z*dimy*dimx+y*dimx+x] != h_dst[z*dimy*dimx+y*dimx+x])
{
printf("Solution doesnot match at x: %d, y: %d, z: %d\n", x, y, z);
goto cleanup;
}
// else
// printf("Solution match at x: %d, y: %d, z: %d\n", x, y, z);
}
}
}
printf("Solution is correct.\n");
cleanup:
hipFree(d_src);
hipFree(d_dst);
free(h_src);
free(h_dst);
return 0;
} | .text
.file "cuda-convolution.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub____convolutionPfS_iii # -- Begin function _Z28__device_stub____convolutionPfS_iii
.p2align 4, 0x90
.type _Z28__device_stub____convolutionPfS_iii,@function
_Z28__device_stub____convolutionPfS_iii: # @_Z28__device_stub____convolutionPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13__convolutionPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub____convolutionPfS_iii, .Lfunc_end0-_Z28__device_stub____convolutionPfS_iii
.cfi_endproc
# -- End function
.globl _Z11convolutionPfS_iii # -- Begin function _Z11convolutionPfS_iii
.p2align 4, 0x90
.type _Z11convolutionPfS_iii,@function
_Z11convolutionPfS_iii: # @_Z11convolutionPfS_iii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %r8d, %ebx
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 7(%r15), %eax
testl %edx, %edx
cmovnsl %edx, %eax
sarl $3, %eax
movl %edx, %ecx
andl $7, %ecx
cmpl $1, %ecx
sbbl $-1, %eax
leal 7(%r14), %edi
testl %r14d, %r14d
cmovnsl %r14d, %edi
sarl $3, %edi
movl %r14d, %ecx
andl $7, %ecx
cmpl $1, %ecx
sbbl $-1, %edi
leal 7(%rbx), %esi
testl %r8d, %r8d
cmovnsl %r8d, %esi
sarl $3, %esi
movl %r8d, %ecx
andl $7, %ecx
cmpl $1, %ecx
sbbl $-1, %esi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13__convolutionPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11convolutionPfS_iii, .Lfunc_end1-_Z11convolutionPfS_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, 8(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, 24(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
movl %eax, %ebp
leaq 16(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_1
# %bb.3:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
movl %eax, %ebp
leaq 4(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_4
# %bb.5:
xorl %r14d, %r14d
movq 8(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB2_6: # %.preheader59
# =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
# Child Loop BB2_8 Depth 3
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_7: # %.preheader58
# Parent Loop BB2_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_8 Depth 3
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_6 Depth=1
# Parent Loop BB2_7 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
incq %rbx
cmpq $100, %rbx
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=2
incq %r13
addq $400, %r12 # imm = 0x190
cmpq $100, %r13
jne .LBB2_7
# %bb.10: # in Loop: Header=BB2_6 Depth=1
incq %r14
addq $40000, %r15 # imm = 0x9C40
cmpq $100, %r14
jne .LBB2_6
# %bb.11:
movq 32(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
leaq 4(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_12
# %bb.13:
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movl $100, %edx
movl $100, %ecx
movl $100, %r8d
callq _Z11convolutionPfS_iii
movq 16(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
leaq 4(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_14
# %bb.17:
movq %rbx, %r14
addq $4, %r14
movq 8(%rsp), %rbp # 8-byte Reload
addq $4, %rbp
xorl %r15d, %r15d
movq %rbx, %rdx
.p2align 4, 0x90
.LBB2_18: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB2_19 Depth 2
# Child Loop BB2_27 Depth 3
imulq $10000, %r15, %r13 # imm = 0x2710
movq %rbp, 40(%rsp) # 8-byte Spill
movq %r14, 48(%rsp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_19: # %.preheader
# Parent Loop BB2_18 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_27 Depth 3
imulq $100, %r12, %rax
addq %r13, %rax
movq 8(%rsp), %rcx # 8-byte Reload
movss (%rcx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rdx,%rax,4), %xmm0
jne .LBB2_20
jnp .LBB2_26
.LBB2_20: # in Loop: Header=BB2_19 Depth=2
xorl %esi, %esi
xorl %ebx, %ebx
jmp .LBB2_25
.p2align 4, 0x90
.LBB2_26: # %.lr.ph.preheader
# in Loop: Header=BB2_19 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_27: # %.lr.ph
# Parent Loop BB2_18 Depth=1
# Parent Loop BB2_19 Depth=2
# => This Inner Loop Header: Depth=3
cmpq $99, %rax
je .LBB2_28
# %bb.23: # in Loop: Header=BB2_27 Depth=3
movss (%rbp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%rax), %rsi
ucomiss (%r14,%rax,4), %xmm0
movq %rsi, %rax
jne .LBB2_24
jnp .LBB2_27
.LBB2_24: # %._crit_edge.loopexit
# in Loop: Header=BB2_19 Depth=2
leaq -1(%rsi), %rax
cmpq $99, %rax
setae %bl
.LBB2_25: # %._crit_edge
# in Loop: Header=BB2_19 Depth=2
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
movl %r12d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $20, %eax
movq 24(%rsp), %rdx # 8-byte Reload
testb %bl, %bl
je .LBB2_30
.LBB2_21: # in Loop: Header=BB2_19 Depth=2
incq %r12
addq $400, %r14 # imm = 0x190
addq $400, %rbp # imm = 0x190
cmpq $100, %r12
jne .LBB2_19
jmp .LBB2_22
.LBB2_28: # %.loopexit.loopexit
# in Loop: Header=BB2_19 Depth=2
setae %bl
movl $17, %eax
testb %bl, %bl
jne .LBB2_21
jmp .LBB2_30
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_18 Depth=1
movl $14, %eax
.LBB2_30: # in Loop: Header=BB2_18 Depth=1
cmpl $14, %eax
jne .LBB2_31
# %bb.15: # in Loop: Header=BB2_18 Depth=1
incq %r15
movq 48(%rsp), %r14 # 8-byte Reload
addq $40000, %r14 # imm = 0x9C40
movq 40(%rsp), %rbp # 8-byte Reload
addq $40000, %rbp # imm = 0x9C40
cmpq $100, %r15
jne .LBB2_18
# %bb.16:
movl $11, %eax
.LBB2_31:
cmpl $20, %eax
je .LBB2_34
# %bb.32:
cmpl $11, %eax
jne .LBB2_35
# %bb.33:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_34:
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
.LBB2_35:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 112
movl %ebp, %edi
callq hipGetErrorString
movl 16(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $143, %edx
jmp .LBB2_2
.LBB2_4:
movl %ebp, %edi
callq hipGetErrorString
movl 4(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $144, %edx
jmp .LBB2_2
.LBB2_12:
movl %ebp, %edi
callq hipGetErrorString
movl 4(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $158, %edx
jmp .LBB2_2
.LBB2_14:
movl %ebp, %edi
callq hipGetErrorString
movl 4(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $162, %edx
.LBB2_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13__convolutionPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13__convolutionPfS_iii,@object # @_Z13__convolutionPfS_iii
.section .rodata,"a",@progbits
.globl _Z13__convolutionPfS_iii
.p2align 3, 0x0
_Z13__convolutionPfS_iii:
.quad _Z28__device_stub____convolutionPfS_iii
.size _Z13__convolutionPfS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda failure error in file '%s' in line %i: '%s' at device %d \n"
.size .L.str, 64
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/tmquan/hetero/master/samples/cuda/convolution/cuda-convolution.hip"
.size .L.str.1, 124
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Solution doesnot match at x: %d, y: %d, z: %d\n"
.size .L.str.2, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13__convolutionPfS_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Solution is correct."
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub____convolutionPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13__convolutionPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce67e_00000000-6_cuda-convolution.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
.type _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii, @function
_Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13__convolutionPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii, .-_Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
.globl _Z13__convolutionPfS_iii
.type _Z13__convolutionPfS_iii, @function
_Z13__convolutionPfS_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z13__convolutionPfS_iii, .-_Z13__convolutionPfS_iii
.globl _Z11convolutionPfS_iii
.type _Z11convolutionPfS_iii, @function
_Z11convolutionPfS_iii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r14
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
testb $7, %dl
setne %dl
movzbl %dl, %edx
leal 7(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $3, %eax
addl %edx, %eax
movl %eax, 8(%rsp)
testb $7, %cl
setne %dl
movzbl %dl, %edx
leal 7(%rcx), %eax
testl %ecx, %ecx
cmovns %ecx, %eax
sarl $3, %eax
addl %edx, %eax
movl %eax, 12(%rsp)
testb $7, %r8b
setne %sil
movzbl %sil, %esi
leal 7(%r8), %eax
testl %r8d, %r8d
cmovns %r8d, %eax
sarl $3, %eax
addl %eax, %esi
movl $8, 20(%rsp)
movl $8, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $8, %ecx
movq 8(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z38__device_stub__Z13__convolutionPfS_iiiPfS_iii
jmp .L11
.cfi_endproc
.LFE3669:
.size _Z11convolutionPfS_iii, .-_Z11convolutionPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/tmquan/hetero/master/samples/cuda/convolution/cuda-convolution.cu"
.align 8
.LC1:
.string "Cuda failure error in file '%s' in line %i: '%s' at device %d \n"
.align 8
.LC2:
.string "Solution doesnot match at x: %d, y: %d, z: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Solution is correct.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r13
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 16(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L38
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L39
leaq 400(%r13), %r12
leaq 4000400(%r13), %r15
jmp .L18
.L38:
movl 16(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $143, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl 4(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $144, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
addq $400, %rbp
cmpq %r12, %rbp
je .L20
.L22:
leaq -400(%rbp), %rbx
.L19:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
jmp .L40
.L20:
cmpq %r12, %r15
je .L21
.L18:
movq %r12, %rbp
addq $40000, %r12
jmp .L22
.L21:
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L41
movl $100, %r8d
movl $100, %ecx
movl $100, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z11convolutionPfS_iii
movl $2, %ecx
movl $4000000, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
testl %ebx, %ebx
jne .L42
movl $0, %esi
movl $0, %r8d
.L25:
movq %rsi, %rdx
movl $0, %ecx
.L32:
movl $0, %eax
leaq 0(%r13,%rdx), %r9
leaq (%r14,%rdx), %rdi
.L29:
movss (%r9,%rax,4), %xmm0
ucomiss (%rdi,%rax,4), %xmm0
jp .L34
jne .L34
addq $1, %rax
cmpq $100, %rax
jne .L29
addl $1, %ecx
addq $400, %rdx
cmpl $100, %ecx
jne .L32
addl $1, %r8d
addq $40000, %rsi
cmpl $100, %r8d
jne .L25
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L41:
movl 4(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $158, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl 4(%rsp), %ebp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %r9d
movl $162, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13__convolutionPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13__convolutionPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-convolution.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub____convolutionPfS_iii # -- Begin function _Z28__device_stub____convolutionPfS_iii
.p2align 4, 0x90
.type _Z28__device_stub____convolutionPfS_iii,@function
_Z28__device_stub____convolutionPfS_iii: # @_Z28__device_stub____convolutionPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13__convolutionPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub____convolutionPfS_iii, .Lfunc_end0-_Z28__device_stub____convolutionPfS_iii
.cfi_endproc
# -- End function
.globl _Z11convolutionPfS_iii # -- Begin function _Z11convolutionPfS_iii
.p2align 4, 0x90
.type _Z11convolutionPfS_iii,@function
_Z11convolutionPfS_iii: # @_Z11convolutionPfS_iii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %r8d, %ebx
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
leal 7(%r15), %eax
testl %edx, %edx
cmovnsl %edx, %eax
sarl $3, %eax
movl %edx, %ecx
andl $7, %ecx
cmpl $1, %ecx
sbbl $-1, %eax
leal 7(%r14), %edi
testl %r14d, %r14d
cmovnsl %r14d, %edi
sarl $3, %edi
movl %r14d, %ecx
andl $7, %ecx
cmpl $1, %ecx
sbbl $-1, %edi
leal 7(%rbx), %esi
testl %r8d, %r8d
cmovnsl %r8d, %esi
sarl $3, %esi
movl %r8d, %ecx
andl $7, %ecx
cmpl $1, %ecx
sbbl $-1, %esi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13__convolutionPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11convolutionPfS_iii, .Lfunc_end1-_Z11convolutionPfS_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, 8(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, 24(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
movl %eax, %ebp
leaq 16(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_1
# %bb.3:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
movl %eax, %ebp
leaq 4(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_4
# %bb.5:
xorl %r14d, %r14d
movq 8(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB2_6: # %.preheader59
# =>This Loop Header: Depth=1
# Child Loop BB2_7 Depth 2
# Child Loop BB2_8 Depth 3
movq %r15, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_7: # %.preheader58
# Parent Loop BB2_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_8 Depth 3
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_6 Depth=1
# Parent Loop BB2_7 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbx,4)
incq %rbx
cmpq $100, %rbx
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=2
incq %r13
addq $400, %r12 # imm = 0x190
cmpq $100, %r13
jne .LBB2_7
# %bb.10: # in Loop: Header=BB2_6 Depth=1
incq %r14
addq $40000, %r15 # imm = 0x9C40
cmpq $100, %r14
jne .LBB2_6
# %bb.11:
movq 32(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
leaq 4(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_12
# %bb.13:
movq 32(%rsp), %rdi
movq 16(%rsp), %rsi
movl $100, %edx
movl $100, %ecx
movl $100, %r8d
callq _Z11convolutionPfS_iii
movq 16(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
movl %eax, %ebp
leaq 4(%rsp), %rdi
callq hipGetDevice
testl %ebp, %ebp
jne .LBB2_14
# %bb.17:
movq %rbx, %r14
addq $4, %r14
movq 8(%rsp), %rbp # 8-byte Reload
addq $4, %rbp
xorl %r15d, %r15d
movq %rbx, %rdx
.p2align 4, 0x90
.LBB2_18: # %.preheader57
# =>This Loop Header: Depth=1
# Child Loop BB2_19 Depth 2
# Child Loop BB2_27 Depth 3
imulq $10000, %r15, %r13 # imm = 0x2710
movq %rbp, 40(%rsp) # 8-byte Spill
movq %r14, 48(%rsp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_19: # %.preheader
# Parent Loop BB2_18 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_27 Depth 3
imulq $100, %r12, %rax
addq %r13, %rax
movq 8(%rsp), %rcx # 8-byte Reload
movss (%rcx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rdx,%rax,4), %xmm0
jne .LBB2_20
jnp .LBB2_26
.LBB2_20: # in Loop: Header=BB2_19 Depth=2
xorl %esi, %esi
xorl %ebx, %ebx
jmp .LBB2_25
.p2align 4, 0x90
.LBB2_26: # %.lr.ph.preheader
# in Loop: Header=BB2_19 Depth=2
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_27: # %.lr.ph
# Parent Loop BB2_18 Depth=1
# Parent Loop BB2_19 Depth=2
# => This Inner Loop Header: Depth=3
cmpq $99, %rax
je .LBB2_28
# %bb.23: # in Loop: Header=BB2_27 Depth=3
movss (%rbp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%rax), %rsi
ucomiss (%r14,%rax,4), %xmm0
movq %rsi, %rax
jne .LBB2_24
jnp .LBB2_27
.LBB2_24: # %._crit_edge.loopexit
# in Loop: Header=BB2_19 Depth=2
leaq -1(%rsi), %rax
cmpq $99, %rax
setae %bl
.LBB2_25: # %._crit_edge
# in Loop: Header=BB2_19 Depth=2
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
movl %r12d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $20, %eax
movq 24(%rsp), %rdx # 8-byte Reload
testb %bl, %bl
je .LBB2_30
.LBB2_21: # in Loop: Header=BB2_19 Depth=2
incq %r12
addq $400, %r14 # imm = 0x190
addq $400, %rbp # imm = 0x190
cmpq $100, %r12
jne .LBB2_19
jmp .LBB2_22
.LBB2_28: # %.loopexit.loopexit
# in Loop: Header=BB2_19 Depth=2
setae %bl
movl $17, %eax
testb %bl, %bl
jne .LBB2_21
jmp .LBB2_30
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_18 Depth=1
movl $14, %eax
.LBB2_30: # in Loop: Header=BB2_18 Depth=1
cmpl $14, %eax
jne .LBB2_31
# %bb.15: # in Loop: Header=BB2_18 Depth=1
incq %r15
movq 48(%rsp), %r14 # 8-byte Reload
addq $40000, %r14 # imm = 0x9C40
movq 40(%rsp), %rbp # 8-byte Reload
addq $40000, %rbp # imm = 0x9C40
cmpq $100, %r15
jne .LBB2_18
# %bb.16:
movl $11, %eax
.LBB2_31:
cmpl $20, %eax
je .LBB2_34
# %bb.32:
cmpl $11, %eax
jne .LBB2_35
# %bb.33:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_34:
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
.LBB2_35:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 112
movl %ebp, %edi
callq hipGetErrorString
movl 16(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $143, %edx
jmp .LBB2_2
.LBB2_4:
movl %ebp, %edi
callq hipGetErrorString
movl 4(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $144, %edx
jmp .LBB2_2
.LBB2_12:
movl %ebp, %edi
callq hipGetErrorString
movl 4(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $158, %edx
jmp .LBB2_2
.LBB2_14:
movl %ebp, %edi
callq hipGetErrorString
movl 4(%rsp), %r8d
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $162, %edx
.LBB2_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13__convolutionPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13__convolutionPfS_iii,@object # @_Z13__convolutionPfS_iii
.section .rodata,"a",@progbits
.globl _Z13__convolutionPfS_iii
.p2align 3, 0x0
_Z13__convolutionPfS_iii:
.quad _Z28__device_stub____convolutionPfS_iii
.size _Z13__convolutionPfS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda failure error in file '%s' in line %i: '%s' at device %d \n"
.size .L.str, 64
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/tmquan/hetero/master/samples/cuda/convolution/cuda-convolution.hip"
.size .L.str.1, 124
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Solution doesnot match at x: %d, y: %d, z: %d\n"
.size .L.str.2, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13__convolutionPfS_iii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Solution is correct."
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub____convolutionPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13__convolutionPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
__host__ cudaEvent_t get_time(void) {
cudaEvent_t time;
cudaEventCreate(&time);
cudaEventRecord(time);
return time;
}
// Pulled from module 6 assignment
__host__ void generate_rand_data(int * host_data_ptr, const int num_elem)
{
// Generate random values from 0-19
for(unsigned int i=0; i < num_elem; i++)
host_data_ptr[i] = (int) (rand()%20);
}
__global__ void gpuKernel(int *A, int *B, int *C, const int num_elem) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx < (num_elem)) {
// Load data from global memory into registers
int a = A[idx];
int b = B[idx];
int c = 0;
// Perform some math on the array values
c = (a*b) + a + b;
c = c*c;
C[idx] = c;
}
}
__host__ float execute_concurrent_streamed_kernel(int arraySize, int N, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
const int d_byteSize = N*sizeof(int);
cudaDeviceProp prop;
int whichDevice;
// Following taken from the book "CUDA by Example"
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
// "A GPU supporting device overlap possesses the capacity to simultaneously
// execute a CUDA C kernel while performing a copy between device and host memory."
if(!prop.deviceOverlap) {
printf("Device will not handle overlaps, so no speedup from streams\n");
return 0;
}
cudaStream_t stream0, stream1;
cudaStreamCreate(&stream0);
cudaStreamCreate(&stream1);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a0, *d_b0, *d_c0; // Buffers used in stream0
int *d_a1, *d_b1, *d_c1; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
cudaHostAlloc((void **)&h_a, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_b, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_c, h_byteSize, cudaHostAllocDefault);
// Used in stream0
cudaMalloc((void**) &d_a0, d_byteSize);
cudaMalloc((void**) &d_b0, d_byteSize);
cudaMalloc((void**) &d_c0, d_byteSize);
// Used in stream1
cudaMalloc((void**) &d_a1, d_byteSize);
cudaMalloc((void**) &d_b1, d_byteSize);
cudaMalloc((void**) &d_c1, d_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
cudaEvent_t startT, stopT;
float deltaT;
startT = get_time();
/* =================================================================================
* We are only copying part of full data each time. Queueing in a ping-pong fashion
* like shown below optimizes the execution timeline. Trying to queue all stream0
* operations and then queue all stream1 operations will cause the copy back to host
* memory in stream0 to block the copy to device for stream1. Now copies can start
* in stream1 while stream0's kernel is executing.
* =================================================================================
*/
for(int i=0; i<arraySize; i+=N*2) {
// Queue up copy of data for a array in both streams
cudaMemcpyAsync(d_a0, h_a+i, d_byteSize, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(d_a1, h_a+i+N, d_byteSize, cudaMemcpyHostToDevice, stream1);
// Queue up copy of data for b array in both streams
cudaMemcpyAsync(d_b0, h_b+i, d_byteSize, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(d_b1, h_b+i+N, d_byteSize, cudaMemcpyHostToDevice, stream1);
// Queue up running of gpu kernel
gpuKernel<<<N/tpb, tpb, 0, stream0>>>(d_a0, d_b0, d_c0, N);
gpuKernel<<<N/tpb, tpb, 0, stream1>>>(d_a1, d_b1, d_c1, N);
// Queue up copy of data from device to pinned memory
cudaMemcpyAsync(h_c+i, d_c0, d_byteSize, cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(h_c+i+N, d_c1, d_byteSize, cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
stopT = get_time();
cudaEventSynchronize(stopT);
cudaEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFree(d_a0);
cudaFree(d_b0);
cudaFree(d_c0);
cudaFree(d_a1);
cudaFree(d_b1);
cudaFree(d_c1);
cudaEventDestroy(startT);
cudaEventDestroy(stopT);
cudaStreamDestroy(stream0);
cudaStreamDestroy(stream1);
return deltaT;
}
__host__ float execute_kernel(int arraySize, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a, *d_b, *d_c; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
cudaHostAlloc((void **)&h_a, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_b, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_c, h_byteSize, cudaHostAllocDefault);
cudaMalloc((void**) &d_a, h_byteSize);
cudaMalloc((void**) &d_b, h_byteSize);
cudaMalloc((void**) &d_c, h_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
cudaEvent_t startT, stopT;
float deltaT;
startT = get_time();
// Copy data to device
cudaMemcpy(d_a, h_a, h_byteSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, h_byteSize, cudaMemcpyHostToDevice);
gpuKernel<<<arraySize/tpb, tpb>>>(d_a, d_b, d_c, arraySize);
cudaMemcpy(h_c, d_c, h_byteSize, cudaMemcpyDeviceToHost);
stopT = get_time();
cudaEventSynchronize(stopT);
cudaEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaEventDestroy(startT);
cudaEventDestroy(stopT);
return deltaT;
}
int main(int argc, char **argv) {
int arraySize = 4096; // Total number of elements to process.
int N = 256; // Number of elements to pass to GPU at one time.
int tpb = 128;
if(argc >= 2)
arraySize = atoi(argv[1]);
if(argc >= 3)
N = atoi(argv[2]);
if(argc >= 4)
tpb = atoi(argv[3]);
if(arraySize % N !=0 || N%tpb!=0) {
printf("Number of total threads is not divisible by number of elements to process in each stream iteration.\n");
return 0;
}
float delta_concurrent = execute_concurrent_streamed_kernel(arraySize, N, tpb);
float delta_normal = execute_kernel(arraySize, tpb);
printf("========================\n");
printf("Summary\n");
printf("Total Threads: %d\n", arraySize);
printf("Number of concurrent kernel instances: %d\n", N);
printf("Thread Size: %d\n", tpb);
printf("========================\n");
printf("Time to copy memory and execute kernel with two streams running concurrently.\n");
printf("duration: %fms\n",delta_concurrent);
printf("========================\n");
printf("Time to copy memory and execute kernel running using a normal kernel execution.\n");
printf("duration: %fms\n\n\n",delta_normal);
} | code for sm_80
Function : _Z9gpuKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R0, R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ IMAD R0, R4, R3, R0 ; /* 0x0000000304007224 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD R9, R0, R0, RZ ; /* 0x0000000000097224 */
/* 0x000fca00078e02ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
__host__ cudaEvent_t get_time(void) {
cudaEvent_t time;
cudaEventCreate(&time);
cudaEventRecord(time);
return time;
}
// Pulled from module 6 assignment
__host__ void generate_rand_data(int * host_data_ptr, const int num_elem)
{
// Generate random values from 0-19
for(unsigned int i=0; i < num_elem; i++)
host_data_ptr[i] = (int) (rand()%20);
}
__global__ void gpuKernel(int *A, int *B, int *C, const int num_elem) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx < (num_elem)) {
// Load data from global memory into registers
int a = A[idx];
int b = B[idx];
int c = 0;
// Perform some math on the array values
c = (a*b) + a + b;
c = c*c;
C[idx] = c;
}
}
__host__ float execute_concurrent_streamed_kernel(int arraySize, int N, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
const int d_byteSize = N*sizeof(int);
cudaDeviceProp prop;
int whichDevice;
// Following taken from the book "CUDA by Example"
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
// "A GPU supporting device overlap possesses the capacity to simultaneously
// execute a CUDA C kernel while performing a copy between device and host memory."
if(!prop.deviceOverlap) {
printf("Device will not handle overlaps, so no speedup from streams\n");
return 0;
}
cudaStream_t stream0, stream1;
cudaStreamCreate(&stream0);
cudaStreamCreate(&stream1);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a0, *d_b0, *d_c0; // Buffers used in stream0
int *d_a1, *d_b1, *d_c1; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
cudaHostAlloc((void **)&h_a, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_b, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_c, h_byteSize, cudaHostAllocDefault);
// Used in stream0
cudaMalloc((void**) &d_a0, d_byteSize);
cudaMalloc((void**) &d_b0, d_byteSize);
cudaMalloc((void**) &d_c0, d_byteSize);
// Used in stream1
cudaMalloc((void**) &d_a1, d_byteSize);
cudaMalloc((void**) &d_b1, d_byteSize);
cudaMalloc((void**) &d_c1, d_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
cudaEvent_t startT, stopT;
float deltaT;
startT = get_time();
/* =================================================================================
* We are only copying part of full data each time. Queueing in a ping-pong fashion
* like shown below optimizes the execution timeline. Trying to queue all stream0
* operations and then queue all stream1 operations will cause the copy back to host
* memory in stream0 to block the copy to device for stream1. Now copies can start
* in stream1 while stream0's kernel is executing.
* =================================================================================
*/
for(int i=0; i<arraySize; i+=N*2) {
// Queue up copy of data for a array in both streams
cudaMemcpyAsync(d_a0, h_a+i, d_byteSize, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(d_a1, h_a+i+N, d_byteSize, cudaMemcpyHostToDevice, stream1);
// Queue up copy of data for b array in both streams
cudaMemcpyAsync(d_b0, h_b+i, d_byteSize, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(d_b1, h_b+i+N, d_byteSize, cudaMemcpyHostToDevice, stream1);
// Queue up running of gpu kernel
gpuKernel<<<N/tpb, tpb, 0, stream0>>>(d_a0, d_b0, d_c0, N);
gpuKernel<<<N/tpb, tpb, 0, stream1>>>(d_a1, d_b1, d_c1, N);
// Queue up copy of data from device to pinned memory
cudaMemcpyAsync(h_c+i, d_c0, d_byteSize, cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(h_c+i+N, d_c1, d_byteSize, cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
stopT = get_time();
cudaEventSynchronize(stopT);
cudaEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFree(d_a0);
cudaFree(d_b0);
cudaFree(d_c0);
cudaFree(d_a1);
cudaFree(d_b1);
cudaFree(d_c1);
cudaEventDestroy(startT);
cudaEventDestroy(stopT);
cudaStreamDestroy(stream0);
cudaStreamDestroy(stream1);
return deltaT;
}
__host__ float execute_kernel(int arraySize, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a, *d_b, *d_c; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
cudaHostAlloc((void **)&h_a, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_b, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_c, h_byteSize, cudaHostAllocDefault);
cudaMalloc((void**) &d_a, h_byteSize);
cudaMalloc((void**) &d_b, h_byteSize);
cudaMalloc((void**) &d_c, h_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
cudaEvent_t startT, stopT;
float deltaT;
startT = get_time();
// Copy data to device
cudaMemcpy(d_a, h_a, h_byteSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, h_byteSize, cudaMemcpyHostToDevice);
gpuKernel<<<arraySize/tpb, tpb>>>(d_a, d_b, d_c, arraySize);
cudaMemcpy(h_c, d_c, h_byteSize, cudaMemcpyDeviceToHost);
stopT = get_time();
cudaEventSynchronize(stopT);
cudaEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaEventDestroy(startT);
cudaEventDestroy(stopT);
return deltaT;
}
int main(int argc, char **argv) {
int arraySize = 4096; // Total number of elements to process.
int N = 256; // Number of elements to pass to GPU at one time.
int tpb = 128;
if(argc >= 2)
arraySize = atoi(argv[1]);
if(argc >= 3)
N = atoi(argv[2]);
if(argc >= 4)
tpb = atoi(argv[3]);
if(arraySize % N !=0 || N%tpb!=0) {
printf("Number of total threads is not divisible by number of elements to process in each stream iteration.\n");
return 0;
}
float delta_concurrent = execute_concurrent_streamed_kernel(arraySize, N, tpb);
float delta_normal = execute_kernel(arraySize, tpb);
printf("========================\n");
printf("Summary\n");
printf("Total Threads: %d\n", arraySize);
printf("Number of concurrent kernel instances: %d\n", N);
printf("Thread Size: %d\n", tpb);
printf("========================\n");
printf("Time to copy memory and execute kernel with two streams running concurrently.\n");
printf("duration: %fms\n",delta_concurrent);
printf("========================\n");
printf("Time to copy memory and execute kernel running using a normal kernel execution.\n");
printf("duration: %fms\n\n\n",delta_normal);
} | .file "tmpxft_000978e3_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z18generate_rand_dataPii
.type _Z18generate_rand_dataPii, @function
_Z18generate_rand_dataPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
je .L12
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leal -1(%rsi), %eax
leaq 4(%rdi,%rax,4), %rbp
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z18generate_rand_dataPii, .-_Z18generate_rand_dataPii
.globl _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9gpuKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
.globl _Z9gpuKernelPiS_S_i
.type _Z9gpuKernelPiS_S_i, @function
_Z9gpuKernelPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9gpuKernelPiS_S_i, .-_Z9gpuKernelPiS_S_i
.globl _Z14execute_kernelii
.type _Z14execute_kernelii, @function
_Z14execute_kernelii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 0(,%rdi,4), %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 8(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, %esi
movq (%rsp), %rdi
call _Z18generate_rand_dataPii
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z18generate_rand_dataPii
call _Z8get_timev
movq %rax, %r13
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, %eax
cltd
idivl %r12d
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, %rbx
movq %rax, %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq %rbx, %rdx
movq %r13, %rsi
call cudaEventElapsedTime@PLT
movq (%rsp), %rdi
call cudaFreeHost@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaEventDestroy@PLT
movq %rbx, %rdi
call cudaEventDestroy@PLT
movss 60(%rsp), %xmm0
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z14execute_kernelii, .-_Z14execute_kernelii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Device will not handle overlaps, so no speedup from streams\n"
.text
.globl _Z34execute_concurrent_streamed_kerneliii
.type _Z34execute_concurrent_streamed_kerneliii, @function
_Z34execute_concurrent_streamed_kerneliii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1224, %rsp
.cfi_def_cfa_offset 1280
movl %edi, 32(%rsp)
movl %esi, 12(%rsp)
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 1208(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rdi
call cudaGetDevice@PLT
leaq 176(%rsp), %rdi
movl 60(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 560(%rsp)
je .L39
movl 12(%rsp), %r12d
movslq %r12d, %rbp
leaq 64(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 72(%rsp), %rdi
call cudaStreamCreate@PLT
movl 32(%rsp), %r14d
leal 0(,%r14,4), %ebx
movslq %ebx, %rbx
leaq 80(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 88(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 96(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leal 0(,%r12,4), %ebx
movslq %ebx, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %r14d, %esi
movq 80(%rsp), %rdi
call _Z18generate_rand_dataPii
movl %r14d, %esi
movq 88(%rsp), %rdi
call _Z18generate_rand_dataPii
call _Z8get_timev
movq %rax, %r15
testl %r14d, %r14d
jle .L32
leal (%r12,%r12), %ecx
movslq %ecx, %rax
salq $2, %rax
movq %rax, 16(%rsp)
leaq 0(,%rbp,4), %rax
movq %rax, 24(%rsp)
movl $0, %ebp
movl $0, %r14d
movl %ecx, 36(%rsp)
movq %r15, 40(%rsp)
jmp .L35
.L39:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
jmp .L29
.L33:
movl %r13d, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl %r15d, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 72(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L34:
movq %rbp, %rdi
addq 96(%rsp), %rdi
movq 64(%rsp), %r8
movl $2, %ecx
movq %rbx, %rdx
movq 120(%rsp), %rsi
call cudaMemcpyAsync@PLT
movq %r12, %rdi
addq 96(%rsp), %rdi
movq 72(%rsp), %r8
movl $2, %ecx
movq %rbx, %rdx
movq 144(%rsp), %rsi
call cudaMemcpyAsync@PLT
movl 36(%rsp), %eax
addl %eax, %r14d
movq 16(%rsp), %rax
addq %rax, %rbp
cmpl %r14d, 32(%rsp)
jle .L41
.L35:
movq %rbp, %rsi
addq 80(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 104(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 24(%rsp), %rax
leaq 0(%rbp,%rax), %r12
movq %r12, %rsi
addq 80(%rsp), %rsi
movq 72(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 128(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbp, %rsi
addq 88(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %r12, %rsi
addq 88(%rsp), %rsi
movq 72(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 136(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl %r13d, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl 12(%rsp), %eax
cltd
idivl %r13d
movl %eax, %r15d
movl %eax, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 64(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl 12(%rsp), %ecx
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
jmp .L33
.L40:
movl 12(%rsp), %ecx
movq 144(%rsp), %rdx
movq 136(%rsp), %rsi
movq 128(%rsp), %rdi
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
jmp .L34
.L41:
movq 40(%rsp), %r15
.L32:
movq 64(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 72(%rsp), %rdi
call cudaStreamSynchronize@PLT
call _Z8get_timev
movq %rax, %rbx
movq %rax, %rdi
call cudaEventSynchronize@PLT
leaq 164(%rsp), %rdi
movq %rbx, %rdx
movq %r15, %rsi
call cudaEventElapsedTime@PLT
movq 80(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rdi
call cudaFreeHost@PLT
movq 96(%rsp), %rdi
call cudaFreeHost@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call cudaEventDestroy@PLT
movq %rbx, %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 72(%rsp), %rdi
call cudaStreamDestroy@PLT
movss 164(%rsp), %xmm0
.L29:
movq 1208(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $1224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z34execute_concurrent_streamed_kerneliii, .-_Z34execute_concurrent_streamed_kerneliii
.section .rodata.str1.8
.align 8
.LC2:
.string "Number of total threads is not divisible by number of elements to process in each stream iteration.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "========================\n"
.LC4:
.string "Summary\n"
.LC5:
.string "Total Threads: %d\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Number of concurrent kernel instances: %d\n"
.section .rodata.str1.1
.LC7:
.string "Thread Size: %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Time to copy memory and execute kernel with two streams running concurrently.\n"
.section .rodata.str1.1
.LC9:
.string "duration: %fms\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Time to copy memory and execute kernel running using a normal kernel execution.\n"
.section .rodata.str1.1
.LC11:
.string "duration: %fms\n\n\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
cmpl $1, %edi
jg .L54
movl $256, %ebx
movl $4096, %r12d
movl $128, %ebp
.L44:
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
je .L48
.L47:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L52:
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
cmpl $2, %ebx
jg .L55
testb %al, %al
jne .L47
movl $256, %ebx
movl $128, %ebp
.L48:
movl %ebp, %edx
movl %ebx, %esi
movl %r12d, %edi
call _Z34execute_concurrent_streamed_kerneliii
movss %xmm0, 8(%rsp)
movl %ebp, %esi
movl %r12d, %edi
call _Z14execute_kernelii
movss %xmm0, 12(%rsp)
leaq .LC3(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L52
.L55:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
cmpl $3, %ebx
jle .L51
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
.L46:
movl %r13d, %ebx
movl %r12d, %eax
cltd
idivl %r13d
testl %edx, %edx
jne .L47
jmp .L44
.L51:
movl $128, %ebp
jmp .L46
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9gpuKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpuKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
__host__ cudaEvent_t get_time(void) {
cudaEvent_t time;
cudaEventCreate(&time);
cudaEventRecord(time);
return time;
}
// Pulled from module 6 assignment
__host__ void generate_rand_data(int * host_data_ptr, const int num_elem)
{
// Generate random values from 0-19
for(unsigned int i=0; i < num_elem; i++)
host_data_ptr[i] = (int) (rand()%20);
}
__global__ void gpuKernel(int *A, int *B, int *C, const int num_elem) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx < (num_elem)) {
// Load data from global memory into registers
int a = A[idx];
int b = B[idx];
int c = 0;
// Perform some math on the array values
c = (a*b) + a + b;
c = c*c;
C[idx] = c;
}
}
__host__ float execute_concurrent_streamed_kernel(int arraySize, int N, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
const int d_byteSize = N*sizeof(int);
cudaDeviceProp prop;
int whichDevice;
// Following taken from the book "CUDA by Example"
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
// "A GPU supporting device overlap possesses the capacity to simultaneously
// execute a CUDA C kernel while performing a copy between device and host memory."
if(!prop.deviceOverlap) {
printf("Device will not handle overlaps, so no speedup from streams\n");
return 0;
}
cudaStream_t stream0, stream1;
cudaStreamCreate(&stream0);
cudaStreamCreate(&stream1);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a0, *d_b0, *d_c0; // Buffers used in stream0
int *d_a1, *d_b1, *d_c1; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
cudaHostAlloc((void **)&h_a, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_b, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_c, h_byteSize, cudaHostAllocDefault);
// Used in stream0
cudaMalloc((void**) &d_a0, d_byteSize);
cudaMalloc((void**) &d_b0, d_byteSize);
cudaMalloc((void**) &d_c0, d_byteSize);
// Used in stream1
cudaMalloc((void**) &d_a1, d_byteSize);
cudaMalloc((void**) &d_b1, d_byteSize);
cudaMalloc((void**) &d_c1, d_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
cudaEvent_t startT, stopT;
float deltaT;
startT = get_time();
/* =================================================================================
* We are only copying part of full data each time. Queueing in a ping-pong fashion
* like shown below optimizes the execution timeline. Trying to queue all stream0
* operations and then queue all stream1 operations will cause the copy back to host
* memory in stream0 to block the copy to device for stream1. Now copies can start
* in stream1 while stream0's kernel is executing.
* =================================================================================
*/
for(int i=0; i<arraySize; i+=N*2) {
// Queue up copy of data for a array in both streams
cudaMemcpyAsync(d_a0, h_a+i, d_byteSize, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(d_a1, h_a+i+N, d_byteSize, cudaMemcpyHostToDevice, stream1);
// Queue up copy of data for b array in both streams
cudaMemcpyAsync(d_b0, h_b+i, d_byteSize, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(d_b1, h_b+i+N, d_byteSize, cudaMemcpyHostToDevice, stream1);
// Queue up running of gpu kernel
gpuKernel<<<N/tpb, tpb, 0, stream0>>>(d_a0, d_b0, d_c0, N);
gpuKernel<<<N/tpb, tpb, 0, stream1>>>(d_a1, d_b1, d_c1, N);
// Queue up copy of data from device to pinned memory
cudaMemcpyAsync(h_c+i, d_c0, d_byteSize, cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(h_c+i+N, d_c1, d_byteSize, cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
stopT = get_time();
cudaEventSynchronize(stopT);
cudaEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFree(d_a0);
cudaFree(d_b0);
cudaFree(d_c0);
cudaFree(d_a1);
cudaFree(d_b1);
cudaFree(d_c1);
cudaEventDestroy(startT);
cudaEventDestroy(stopT);
cudaStreamDestroy(stream0);
cudaStreamDestroy(stream1);
return deltaT;
}
__host__ float execute_kernel(int arraySize, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a, *d_b, *d_c; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
cudaHostAlloc((void **)&h_a, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_b, h_byteSize, cudaHostAllocDefault);
cudaHostAlloc((void **)&h_c, h_byteSize, cudaHostAllocDefault);
cudaMalloc((void**) &d_a, h_byteSize);
cudaMalloc((void**) &d_b, h_byteSize);
cudaMalloc((void**) &d_c, h_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
cudaEvent_t startT, stopT;
float deltaT;
startT = get_time();
// Copy data to device
cudaMemcpy(d_a, h_a, h_byteSize, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, h_byteSize, cudaMemcpyHostToDevice);
gpuKernel<<<arraySize/tpb, tpb>>>(d_a, d_b, d_c, arraySize);
cudaMemcpy(h_c, d_c, h_byteSize, cudaMemcpyDeviceToHost);
stopT = get_time();
cudaEventSynchronize(stopT);
cudaEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaEventDestroy(startT);
cudaEventDestroy(stopT);
return deltaT;
}
int main(int argc, char **argv) {
int arraySize = 4096; // Total number of elements to process.
int N = 256; // Number of elements to pass to GPU at one time.
int tpb = 128;
if(argc >= 2)
arraySize = atoi(argv[1]);
if(argc >= 3)
N = atoi(argv[2]);
if(argc >= 4)
tpb = atoi(argv[3]);
if(arraySize % N !=0 || N%tpb!=0) {
printf("Number of total threads is not divisible by number of elements to process in each stream iteration.\n");
return 0;
}
float delta_concurrent = execute_concurrent_streamed_kernel(arraySize, N, tpb);
float delta_normal = execute_kernel(arraySize, tpb);
printf("========================\n");
printf("Summary\n");
printf("Total Threads: %d\n", arraySize);
printf("Number of concurrent kernel instances: %d\n", N);
printf("Thread Size: %d\n", tpb);
printf("========================\n");
printf("Time to copy memory and execute kernel with two streams running concurrently.\n");
printf("duration: %fms\n",delta_concurrent);
printf("========================\n");
printf("Time to copy memory and execute kernel running using a normal kernel execution.\n");
printf("duration: %fms\n\n\n",delta_normal);
} | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
__host__ hipEvent_t get_time(void) {
hipEvent_t time;
hipEventCreate(&time);
hipEventRecord(time);
return time;
}
// Pulled from module 6 assignment
__host__ void generate_rand_data(int * host_data_ptr, const int num_elem)
{
// Generate random values from 0-19
for(unsigned int i=0; i < num_elem; i++)
host_data_ptr[i] = (int) (rand()%20);
}
__global__ void gpuKernel(int *A, int *B, int *C, const int num_elem) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx < (num_elem)) {
// Load data from global memory into registers
int a = A[idx];
int b = B[idx];
int c = 0;
// Perform some math on the array values
c = (a*b) + a + b;
c = c*c;
C[idx] = c;
}
}
__host__ float execute_concurrent_streamed_kernel(int arraySize, int N, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
const int d_byteSize = N*sizeof(int);
hipDeviceProp_t prop;
int whichDevice;
// Following taken from the book "CUDA by Example"
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
// "A GPU supporting device overlap possesses the capacity to simultaneously
// execute a CUDA C kernel while performing a copy between device and host memory."
if(!prop.deviceOverlap) {
printf("Device will not handle overlaps, so no speedup from streams\n");
return 0;
}
hipStream_t stream0, stream1;
hipStreamCreate(&stream0);
hipStreamCreate(&stream1);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a0, *d_b0, *d_c0; // Buffers used in stream0
int *d_a1, *d_b1, *d_c1; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
hipHostAlloc((void **)&h_a, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_b, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_c, h_byteSize, hipHostMallocDefault);
// Used in stream0
hipMalloc((void**) &d_a0, d_byteSize);
hipMalloc((void**) &d_b0, d_byteSize);
hipMalloc((void**) &d_c0, d_byteSize);
// Used in stream1
hipMalloc((void**) &d_a1, d_byteSize);
hipMalloc((void**) &d_b1, d_byteSize);
hipMalloc((void**) &d_c1, d_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
hipEvent_t startT, stopT;
float deltaT;
startT = get_time();
/* =================================================================================
* We are only copying part of full data each time. Queueing in a ping-pong fashion
* like shown below optimizes the execution timeline. Trying to queue all stream0
* operations and then queue all stream1 operations will cause the copy back to host
* memory in stream0 to block the copy to device for stream1. Now copies can start
* in stream1 while stream0's kernel is executing.
* =================================================================================
*/
for(int i=0; i<arraySize; i+=N*2) {
// Queue up copy of data for a array in both streams
hipMemcpyAsync(d_a0, h_a+i, d_byteSize, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(d_a1, h_a+i+N, d_byteSize, hipMemcpyHostToDevice, stream1);
// Queue up copy of data for b array in both streams
hipMemcpyAsync(d_b0, h_b+i, d_byteSize, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(d_b1, h_b+i+N, d_byteSize, hipMemcpyHostToDevice, stream1);
// Queue up running of gpu kernel
gpuKernel<<<N/tpb, tpb, 0, stream0>>>(d_a0, d_b0, d_c0, N);
gpuKernel<<<N/tpb, tpb, 0, stream1>>>(d_a1, d_b1, d_c1, N);
// Queue up copy of data from device to pinned memory
hipMemcpyAsync(h_c+i, d_c0, d_byteSize, hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(h_c+i+N, d_c1, d_byteSize, hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
stopT = get_time();
hipEventSynchronize(stopT);
hipEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipFree(d_a0);
hipFree(d_b0);
hipFree(d_c0);
hipFree(d_a1);
hipFree(d_b1);
hipFree(d_c1);
hipEventDestroy(startT);
hipEventDestroy(stopT);
hipStreamDestroy(stream0);
hipStreamDestroy(stream1);
return deltaT;
}
__host__ float execute_kernel(int arraySize, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a, *d_b, *d_c; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
hipHostAlloc((void **)&h_a, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_b, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_c, h_byteSize, hipHostMallocDefault);
hipMalloc((void**) &d_a, h_byteSize);
hipMalloc((void**) &d_b, h_byteSize);
hipMalloc((void**) &d_c, h_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
hipEvent_t startT, stopT;
float deltaT;
startT = get_time();
// Copy data to device
hipMemcpy(d_a, h_a, h_byteSize, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, h_byteSize, hipMemcpyHostToDevice);
gpuKernel<<<arraySize/tpb, tpb>>>(d_a, d_b, d_c, arraySize);
hipMemcpy(h_c, d_c, h_byteSize, hipMemcpyDeviceToHost);
stopT = get_time();
hipEventSynchronize(stopT);
hipEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipEventDestroy(startT);
hipEventDestroy(stopT);
return deltaT;
}
int main(int argc, char **argv) {
int arraySize = 4096; // Total number of elements to process.
int N = 256; // Number of elements to pass to GPU at one time.
int tpb = 128;
if(argc >= 2)
arraySize = atoi(argv[1]);
if(argc >= 3)
N = atoi(argv[2]);
if(argc >= 4)
tpb = atoi(argv[3]);
if(arraySize % N !=0 || N%tpb!=0) {
printf("Number of total threads is not divisible by number of elements to process in each stream iteration.\n");
return 0;
}
float delta_concurrent = execute_concurrent_streamed_kernel(arraySize, N, tpb);
float delta_normal = execute_kernel(arraySize, tpb);
printf("========================\n");
printf("Summary\n");
printf("Total Threads: %d\n", arraySize);
printf("Number of concurrent kernel instances: %d\n", N);
printf("Thread Size: %d\n", tpb);
printf("========================\n");
printf("Time to copy memory and execute kernel with two streams running concurrently.\n");
printf("duration: %fms\n",delta_concurrent);
printf("========================\n");
printf("Time to copy memory and execute kernel running using a normal kernel execution.\n");
printf("duration: %fms\n\n\n",delta_normal);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
__host__ hipEvent_t get_time(void) {
hipEvent_t time;
hipEventCreate(&time);
hipEventRecord(time);
return time;
}
// Pulled from module 6 assignment
__host__ void generate_rand_data(int * host_data_ptr, const int num_elem)
{
// Generate random values from 0-19
for(unsigned int i=0; i < num_elem; i++)
host_data_ptr[i] = (int) (rand()%20);
}
__global__ void gpuKernel(int *A, int *B, int *C, const int num_elem) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx < (num_elem)) {
// Load data from global memory into registers
int a = A[idx];
int b = B[idx];
int c = 0;
// Perform some math on the array values
c = (a*b) + a + b;
c = c*c;
C[idx] = c;
}
}
__host__ float execute_concurrent_streamed_kernel(int arraySize, int N, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
const int d_byteSize = N*sizeof(int);
hipDeviceProp_t prop;
int whichDevice;
// Following taken from the book "CUDA by Example"
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
// "A GPU supporting device overlap possesses the capacity to simultaneously
// execute a CUDA C kernel while performing a copy between device and host memory."
if(!prop.deviceOverlap) {
printf("Device will not handle overlaps, so no speedup from streams\n");
return 0;
}
hipStream_t stream0, stream1;
hipStreamCreate(&stream0);
hipStreamCreate(&stream1);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a0, *d_b0, *d_c0; // Buffers used in stream0
int *d_a1, *d_b1, *d_c1; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
hipHostAlloc((void **)&h_a, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_b, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_c, h_byteSize, hipHostMallocDefault);
// Used in stream0
hipMalloc((void**) &d_a0, d_byteSize);
hipMalloc((void**) &d_b0, d_byteSize);
hipMalloc((void**) &d_c0, d_byteSize);
// Used in stream1
hipMalloc((void**) &d_a1, d_byteSize);
hipMalloc((void**) &d_b1, d_byteSize);
hipMalloc((void**) &d_c1, d_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
hipEvent_t startT, stopT;
float deltaT;
startT = get_time();
/* =================================================================================
* We are only copying part of full data each time. Queueing in a ping-pong fashion
* like shown below optimizes the execution timeline. Trying to queue all stream0
* operations and then queue all stream1 operations will cause the copy back to host
* memory in stream0 to block the copy to device for stream1. Now copies can start
* in stream1 while stream0's kernel is executing.
* =================================================================================
*/
for(int i=0; i<arraySize; i+=N*2) {
// Queue up copy of data for a array in both streams
hipMemcpyAsync(d_a0, h_a+i, d_byteSize, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(d_a1, h_a+i+N, d_byteSize, hipMemcpyHostToDevice, stream1);
// Queue up copy of data for b array in both streams
hipMemcpyAsync(d_b0, h_b+i, d_byteSize, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(d_b1, h_b+i+N, d_byteSize, hipMemcpyHostToDevice, stream1);
// Queue up running of gpu kernel
gpuKernel<<<N/tpb, tpb, 0, stream0>>>(d_a0, d_b0, d_c0, N);
gpuKernel<<<N/tpb, tpb, 0, stream1>>>(d_a1, d_b1, d_c1, N);
// Queue up copy of data from device to pinned memory
hipMemcpyAsync(h_c+i, d_c0, d_byteSize, hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(h_c+i+N, d_c1, d_byteSize, hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
stopT = get_time();
hipEventSynchronize(stopT);
hipEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipFree(d_a0);
hipFree(d_b0);
hipFree(d_c0);
hipFree(d_a1);
hipFree(d_b1);
hipFree(d_c1);
hipEventDestroy(startT);
hipEventDestroy(stopT);
hipStreamDestroy(stream0);
hipStreamDestroy(stream1);
return deltaT;
}
__host__ float execute_kernel(int arraySize, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a, *d_b, *d_c; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
hipHostAlloc((void **)&h_a, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_b, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_c, h_byteSize, hipHostMallocDefault);
hipMalloc((void**) &d_a, h_byteSize);
hipMalloc((void**) &d_b, h_byteSize);
hipMalloc((void**) &d_c, h_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
hipEvent_t startT, stopT;
float deltaT;
startT = get_time();
// Copy data to device
hipMemcpy(d_a, h_a, h_byteSize, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, h_byteSize, hipMemcpyHostToDevice);
gpuKernel<<<arraySize/tpb, tpb>>>(d_a, d_b, d_c, arraySize);
hipMemcpy(h_c, d_c, h_byteSize, hipMemcpyDeviceToHost);
stopT = get_time();
hipEventSynchronize(stopT);
hipEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipEventDestroy(startT);
hipEventDestroy(stopT);
return deltaT;
}
int main(int argc, char **argv) {
int arraySize = 4096; // Total number of elements to process.
int N = 256; // Number of elements to pass to GPU at one time.
int tpb = 128;
if(argc >= 2)
arraySize = atoi(argv[1]);
if(argc >= 3)
N = atoi(argv[2]);
if(argc >= 4)
tpb = atoi(argv[3]);
if(arraySize % N !=0 || N%tpb!=0) {
printf("Number of total threads is not divisible by number of elements to process in each stream iteration.\n");
return 0;
}
float delta_concurrent = execute_concurrent_streamed_kernel(arraySize, N, tpb);
float delta_normal = execute_kernel(arraySize, tpb);
printf("========================\n");
printf("Summary\n");
printf("Total Threads: %d\n", arraySize);
printf("Number of concurrent kernel instances: %d\n", N);
printf("Thread Size: %d\n", tpb);
printf("========================\n");
printf("Time to copy memory and execute kernel with two streams running concurrently.\n");
printf("duration: %fms\n",delta_concurrent);
printf("========================\n");
printf("Time to copy memory and execute kernel running using a normal kernel execution.\n");
printf("duration: %fms\n\n\n",delta_normal);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpuKernelPiS_S_i
.globl _Z9gpuKernelPiS_S_i
.p2align 8
.type _Z9gpuKernelPiS_S_i,@function
_Z9gpuKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v3
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpuKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpuKernelPiS_S_i, .Lfunc_end0-_Z9gpuKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpuKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9gpuKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
__host__ hipEvent_t get_time(void) {
hipEvent_t time;
hipEventCreate(&time);
hipEventRecord(time);
return time;
}
// Pulled from module 6 assignment
__host__ void generate_rand_data(int * host_data_ptr, const int num_elem)
{
// Generate random values from 0-19
for(unsigned int i=0; i < num_elem; i++)
host_data_ptr[i] = (int) (rand()%20);
}
__global__ void gpuKernel(int *A, int *B, int *C, const int num_elem) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx < (num_elem)) {
// Load data from global memory into registers
int a = A[idx];
int b = B[idx];
int c = 0;
// Perform some math on the array values
c = (a*b) + a + b;
c = c*c;
C[idx] = c;
}
}
__host__ float execute_concurrent_streamed_kernel(int arraySize, int N, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
const int d_byteSize = N*sizeof(int);
hipDeviceProp_t prop;
int whichDevice;
// Following taken from the book "CUDA by Example"
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
// "A GPU supporting device overlap possesses the capacity to simultaneously
// execute a CUDA C kernel while performing a copy between device and host memory."
if(!prop.deviceOverlap) {
printf("Device will not handle overlaps, so no speedup from streams\n");
return 0;
}
hipStream_t stream0, stream1;
hipStreamCreate(&stream0);
hipStreamCreate(&stream1);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a0, *d_b0, *d_c0; // Buffers used in stream0
int *d_a1, *d_b1, *d_c1; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
hipHostAlloc((void **)&h_a, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_b, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_c, h_byteSize, hipHostMallocDefault);
// Used in stream0
hipMalloc((void**) &d_a0, d_byteSize);
hipMalloc((void**) &d_b0, d_byteSize);
hipMalloc((void**) &d_c0, d_byteSize);
// Used in stream1
hipMalloc((void**) &d_a1, d_byteSize);
hipMalloc((void**) &d_b1, d_byteSize);
hipMalloc((void**) &d_c1, d_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
hipEvent_t startT, stopT;
float deltaT;
startT = get_time();
/* =================================================================================
* We are only copying part of full data each time. Queueing in a ping-pong fashion
* like shown below optimizes the execution timeline. Trying to queue all stream0
* operations and then queue all stream1 operations will cause the copy back to host
* memory in stream0 to block the copy to device for stream1. Now copies can start
* in stream1 while stream0's kernel is executing.
* =================================================================================
*/
for(int i=0; i<arraySize; i+=N*2) {
// Queue up copy of data for a array in both streams
hipMemcpyAsync(d_a0, h_a+i, d_byteSize, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(d_a1, h_a+i+N, d_byteSize, hipMemcpyHostToDevice, stream1);
// Queue up copy of data for b array in both streams
hipMemcpyAsync(d_b0, h_b+i, d_byteSize, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(d_b1, h_b+i+N, d_byteSize, hipMemcpyHostToDevice, stream1);
// Queue up running of gpu kernel
gpuKernel<<<N/tpb, tpb, 0, stream0>>>(d_a0, d_b0, d_c0, N);
gpuKernel<<<N/tpb, tpb, 0, stream1>>>(d_a1, d_b1, d_c1, N);
// Queue up copy of data from device to pinned memory
hipMemcpyAsync(h_c+i, d_c0, d_byteSize, hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(h_c+i+N, d_c1, d_byteSize, hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
stopT = get_time();
hipEventSynchronize(stopT);
hipEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipFree(d_a0);
hipFree(d_b0);
hipFree(d_c0);
hipFree(d_a1);
hipFree(d_b1);
hipFree(d_c1);
hipEventDestroy(startT);
hipEventDestroy(stopT);
hipStreamDestroy(stream0);
hipStreamDestroy(stream1);
return deltaT;
}
__host__ float execute_kernel(int arraySize, int tpb) {
const int h_byteSize = arraySize*sizeof(int);
int *h_a, *h_b, *h_c;
// Create two sets of GPU buffers
int *d_a, *d_b, *d_c; // Buffers used in stream1
// Allocate pinned memory, cudaMemcpyAsync requires host memory be page-locked
hipHostAlloc((void **)&h_a, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_b, h_byteSize, hipHostMallocDefault);
hipHostAlloc((void **)&h_c, h_byteSize, hipHostMallocDefault);
hipMalloc((void**) &d_a, h_byteSize);
hipMalloc((void**) &d_b, h_byteSize);
hipMalloc((void**) &d_c, h_byteSize);
// Fill host arrays with random data
generate_rand_data(h_a, arraySize);
generate_rand_data(h_b, arraySize);
// Timers
hipEvent_t startT, stopT;
float deltaT;
startT = get_time();
// Copy data to device
hipMemcpy(d_a, h_a, h_byteSize, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, h_byteSize, hipMemcpyHostToDevice);
gpuKernel<<<arraySize/tpb, tpb>>>(d_a, d_b, d_c, arraySize);
hipMemcpy(h_c, d_c, h_byteSize, hipMemcpyDeviceToHost);
stopT = get_time();
hipEventSynchronize(stopT);
hipEventElapsedTime(&deltaT, startT, stopT);
// Cleanup memory
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipEventDestroy(startT);
hipEventDestroy(stopT);
return deltaT;
}
int main(int argc, char **argv) {
int arraySize = 4096; // Total number of elements to process.
int N = 256; // Number of elements to pass to GPU at one time.
int tpb = 128;
if(argc >= 2)
arraySize = atoi(argv[1]);
if(argc >= 3)
N = atoi(argv[2]);
if(argc >= 4)
tpb = atoi(argv[3]);
if(arraySize % N !=0 || N%tpb!=0) {
printf("Number of total threads is not divisible by number of elements to process in each stream iteration.\n");
return 0;
}
float delta_concurrent = execute_concurrent_streamed_kernel(arraySize, N, tpb);
float delta_normal = execute_kernel(arraySize, tpb);
printf("========================\n");
printf("Summary\n");
printf("Total Threads: %d\n", arraySize);
printf("Number of concurrent kernel instances: %d\n", N);
printf("Thread Size: %d\n", tpb);
printf("========================\n");
printf("Time to copy memory and execute kernel with two streams running concurrently.\n");
printf("duration: %fms\n",delta_concurrent);
printf("========================\n");
printf("Time to copy memory and execute kernel running using a normal kernel execution.\n");
printf("duration: %fms\n\n\n",delta_normal);
} | .text
.file "assignment.hip"
.globl _Z8get_timev # -- Begin function _Z8get_timev
.p2align 4, 0x90
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8get_timev, .Lfunc_end0-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z18generate_rand_dataPii # -- Begin function _Z18generate_rand_dataPii
.p2align 4, 0x90
.type _Z18generate_rand_dataPii,@function
_Z18generate_rand_dataPii: # @_Z18generate_rand_dataPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z18generate_rand_dataPii, .Lfunc_end1-_Z18generate_rand_dataPii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpuKernelPiS_S_i # -- Begin function _Z24__device_stub__gpuKernelPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__gpuKernelPiS_S_i,@function
_Z24__device_stub__gpuKernelPiS_S_i: # @_Z24__device_stub__gpuKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpuKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__gpuKernelPiS_S_i, .Lfunc_end2-_Z24__device_stub__gpuKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z34execute_concurrent_streamed_kerneliii # -- Begin function _Z34execute_concurrent_streamed_kerneliii
.p2align 4, 0x90
.type _Z34execute_concurrent_streamed_kerneliii,@function
_Z34execute_concurrent_streamed_kerneliii: # @_Z34execute_concurrent_streamed_kerneliii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 1792
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 28(%rsp) # 4-byte Spill
movl %esi, %ebx
movl %edi, %r12d
leaq 220(%rsp), %rdi
callq hipGetDevice
movl 220(%rsp), %esi
leaq 264(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 648(%rsp)
je .LBB3_1
# %bb.2:
movq %rbx, 80(%rsp) # 8-byte Spill
leal (,%rbx,4), %ebx
leal (,%r12,4), %ebp
leaq 16(%rsp), %rdi
callq hipStreamCreate
leaq 8(%rsp), %rdi
callq hipStreamCreate
movslq %ebp, %r15
leaq 40(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 136(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
movslq %ebx, %r15
leaq 128(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 120(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 112(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 104(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 96(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %r12d, %ebp
testl %r12d, %r12d
je .LBB3_5
# %bb.3: # %.lr.ph.preheader.i
movq 40(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB3_4
.LBB3_5: # %_Z18generate_rand_dataPii.exit
testl %r12d, %r12d
je .LBB3_8
# %bb.6: # %.lr.ph.preheader.i55
movq 32(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i57
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB3_7
.LBB3_8: # %_Z18generate_rand_dataPii.exit61
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rax
movq %rax, 224(%rsp) # 8-byte Spill
testl %r12d, %r12d
movq 80(%rsp), %r12 # 8-byte Reload
jle .LBB3_15
# %bb.9: # %.lr.ph
movslq %r12d, %rbx
movabsq $4294967296, %rax # imm = 0x100000000
movl 28(%rsp), %ecx # 4-byte Reload
orq %rax, %rcx
movq %rcx, 256(%rsp) # 8-byte Spill
leal (%r12,%r12), %eax
cltq
movq %rax, 240(%rsp) # 8-byte Spill
leaq (,%rax,4), %rax
movq %rax, 232(%rsp) # 8-byte Spill
shlq $2, %rbx
xorl %r14d, %r14d
xorl %r13d, %r13d
movq %rbp, 248(%rsp) # 8-byte Spill
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_14: # in Loop: Header=BB3_10 Depth=1
movq 136(%rsp), %rdi
addq %r14, %rdi
movq 112(%rsp), %rsi
movq 16(%rsp), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 136(%rsp), %rdi
addq %rbx, %rdi
addq %r14, %rdi
movq 88(%rsp), %rsi
movq 8(%rsp), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
addq 240(%rsp), %r13 # 8-byte Folded Reload
addq 232(%rsp), %r14 # 8-byte Folded Reload
movq 248(%rsp), %rbp # 8-byte Reload
cmpq %rbp, %r13
jge .LBB3_15
.LBB3_10: # =>This Inner Loop Header: Depth=1
movq 128(%rsp), %rdi
movq 40(%rsp), %rsi
addq %r14, %rsi
movq 16(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 104(%rsp), %rdi
movq 40(%rsp), %rsi
addq %rbx, %rsi
addq %r14, %rsi
movq 8(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 120(%rsp), %rdi
movq 32(%rsp), %rsi
addq %r14, %rsi
movq 16(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 96(%rsp), %rdi
movq 32(%rsp), %rsi
addq %rbx, %rsi
addq %r14, %rsi
movq 8(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movl %r12d, %eax
cltd
idivl 28(%rsp) # 4-byte Folded Reload
movl %eax, %r12d
movq 16(%rsp), %r9
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movq %r12, %rdi
movl $1, %esi
movq 256(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11: # in Loop: Header=BB3_10 Depth=1
movq 128(%rsp), %rax
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movq %rdx, 192(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, 4(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 200(%rsp), %rax
movq %rax, 56(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z9gpuKernelPiS_S_i, %edi
leaq 48(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_12: # in Loop: Header=BB3_10 Depth=1
movq 8(%rsp), %r9
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 80(%rsp), %r12 # 8-byte Reload
jne .LBB3_14
# %bb.13: # in Loop: Header=BB3_10 Depth=1
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movq %rdx, 192(%rsp)
movl %r12d, 4(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 200(%rsp), %rax
movq %rax, 56(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z9gpuKernelPiS_S_i, %edi
leaq 48(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_14
.LBB3_15: # %._crit_edge
movq 16(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
callq hipStreamSynchronize
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rbx
movq %rbx, %rdi
callq hipEventSynchronize
leaq 48(%rsp), %rdi
movq 224(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %rbx, %rdx
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 136(%rsp), %rdi
callq hipHostFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipStreamDestroy
movq 8(%rsp), %rdi
callq hipStreamDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB3_16
.LBB3_1:
movl $.Lstr, %edi
callq puts@PLT
xorps %xmm0, %xmm0
.LBB3_16:
addq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z34execute_concurrent_streamed_kerneliii, .Lfunc_end3-_Z34execute_concurrent_streamed_kerneliii
.cfi_endproc
# -- End function
.globl _Z14execute_kernelii # -- Begin function _Z14execute_kernelii
.p2align 4, 0x90
.type _Z14execute_kernelii,@function
_Z14execute_kernelii: # @_Z14execute_kernelii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
leal (,%r14,4), %eax
movslq %eax, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 88(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r14d, %r15d
testl %r14d, %r14d
je .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
movq 32(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB4_2
.LBB4_3: # %_Z18generate_rand_dataPii.exit
testl %r14d, %r14d
je .LBB4_6
# %bb.4: # %.lr.ph.preheader.i23
movq 24(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i25
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB4_5
.LBB4_6: # %_Z18generate_rand_dataPii.exit29
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %r15
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r14d, %eax
cltd
idivl %ebp
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
leaq (%rax,%rcx), %rdi
movl %ebp, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %r14d, 44(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9gpuKernelPiS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movq 88(%rsp), %rdi
movq (%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rbx
movq %rbx, %rdi
callq hipEventSynchronize
leaq 48(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 88(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq hipEventDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14execute_kernelii, .Lfunc_end4-_Z14execute_kernelii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movl %edi, %ebp
movl $4096, %ebx # imm = 0x1000
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl $256, %r14d # imm = 0x100
cmpl $3, %ebp
jl .LBB5_4
# %bb.3:
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.LBB5_4:
movl $128, %r15d
cmpl $4, %ebp
jl .LBB5_6
# %bb.5:
movq 24(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB5_6:
movl %ebx, %eax
cltd
idivl %r14d
testl %edx, %edx
jne .LBB5_8
# %bb.7:
movl %r14d, %eax
cltd
idivl %r15d
testl %edx, %edx
je .LBB5_9
.LBB5_8:
movl $.Lstr.7, %edi
callq puts@PLT
.LBB5_10:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_9:
.cfi_def_cfa_offset 64
movl %ebx, %edi
movl %r14d, %esi
movl %r15d, %edx
callq _Z34execute_concurrent_streamed_kerneliii
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %ebx, %edi
movl %r15d, %esi
callq _Z14execute_kernelii
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
jmp .LBB5_10
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpuKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpuKernelPiS_S_i,@object # @_Z9gpuKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9gpuKernelPiS_S_i
.p2align 3, 0x0
_Z9gpuKernelPiS_S_i:
.quad _Z24__device_stub__gpuKernelPiS_S_i
.size _Z9gpuKernelPiS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Total Threads: %d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Number of concurrent kernel instances: %d\n"
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Thread Size: %d\n"
.size .L.str.6, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "duration: %fms\n"
.size .L.str.8, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "duration: %fms\n\n\n"
.size .L.str.10, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpuKernelPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device will not handle overlaps, so no speedup from streams"
.size .Lstr, 60
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Summary"
.size .Lstr.2, 8
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Time to copy memory and execute kernel with two streams running concurrently."
.size .Lstr.4, 78
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "========================"
.size .Lstr.5, 25
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Time to copy memory and execute kernel running using a normal kernel execution."
.size .Lstr.6, 80
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Number of total threads is not divisible by number of elements to process in each stream iteration."
.size .Lstr.7, 100
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpuKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpuKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9gpuKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R0, R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ IMAD R0, R4, R3, R0 ; /* 0x0000000304007224 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD R9, R0, R0, RZ ; /* 0x0000000000097224 */
/* 0x000fca00078e02ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpuKernelPiS_S_i
.globl _Z9gpuKernelPiS_S_i
.p2align 8
.type _Z9gpuKernelPiS_S_i,@function
_Z9gpuKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v3
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpuKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpuKernelPiS_S_i, .Lfunc_end0-_Z9gpuKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpuKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9gpuKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000978e3_00000000-6_assignment.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z18generate_rand_dataPii
.type _Z18generate_rand_dataPii, @function
_Z18generate_rand_dataPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
je .L12
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leal -1(%rsi), %eax
leaq 4(%rdi,%rax,4), %rbp
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z18generate_rand_dataPii, .-_Z18generate_rand_dataPii
.globl _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9gpuKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
.globl _Z9gpuKernelPiS_S_i
.type _Z9gpuKernelPiS_S_i, @function
_Z9gpuKernelPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9gpuKernelPiS_S_i, .-_Z9gpuKernelPiS_S_i
.globl _Z14execute_kernelii
.type _Z14execute_kernelii, @function
_Z14execute_kernelii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 0(,%rdi,4), %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 8(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, %esi
movq (%rsp), %rdi
call _Z18generate_rand_dataPii
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z18generate_rand_dataPii
call _Z8get_timev
movq %rax, %r13
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, %eax
cltd
idivl %r12d
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, %rbx
movq %rax, %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq %rbx, %rdx
movq %r13, %rsi
call cudaEventElapsedTime@PLT
movq (%rsp), %rdi
call cudaFreeHost@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call cudaEventDestroy@PLT
movq %rbx, %rdi
call cudaEventDestroy@PLT
movss 60(%rsp), %xmm0
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z14execute_kernelii, .-_Z14execute_kernelii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Device will not handle overlaps, so no speedup from streams\n"
.text
.globl _Z34execute_concurrent_streamed_kerneliii
.type _Z34execute_concurrent_streamed_kerneliii, @function
_Z34execute_concurrent_streamed_kerneliii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1224, %rsp
.cfi_def_cfa_offset 1280
movl %edi, 32(%rsp)
movl %esi, 12(%rsp)
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 1208(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rdi
call cudaGetDevice@PLT
leaq 176(%rsp), %rdi
movl 60(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 560(%rsp)
je .L39
movl 12(%rsp), %r12d
movslq %r12d, %rbp
leaq 64(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 72(%rsp), %rdi
call cudaStreamCreate@PLT
movl 32(%rsp), %r14d
leal 0(,%r14,4), %ebx
movslq %ebx, %rbx
leaq 80(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 88(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leaq 96(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
leal 0(,%r12,4), %ebx
movslq %ebx, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %r14d, %esi
movq 80(%rsp), %rdi
call _Z18generate_rand_dataPii
movl %r14d, %esi
movq 88(%rsp), %rdi
call _Z18generate_rand_dataPii
call _Z8get_timev
movq %rax, %r15
testl %r14d, %r14d
jle .L32
leal (%r12,%r12), %ecx
movslq %ecx, %rax
salq $2, %rax
movq %rax, 16(%rsp)
leaq 0(,%rbp,4), %rax
movq %rax, 24(%rsp)
movl $0, %ebp
movl $0, %r14d
movl %ecx, 36(%rsp)
movq %r15, 40(%rsp)
jmp .L35
.L39:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
jmp .L29
.L33:
movl %r13d, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl %r15d, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 72(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L34:
movq %rbp, %rdi
addq 96(%rsp), %rdi
movq 64(%rsp), %r8
movl $2, %ecx
movq %rbx, %rdx
movq 120(%rsp), %rsi
call cudaMemcpyAsync@PLT
movq %r12, %rdi
addq 96(%rsp), %rdi
movq 72(%rsp), %r8
movl $2, %ecx
movq %rbx, %rdx
movq 144(%rsp), %rsi
call cudaMemcpyAsync@PLT
movl 36(%rsp), %eax
addl %eax, %r14d
movq 16(%rsp), %rax
addq %rax, %rbp
cmpl %r14d, 32(%rsp)
jle .L41
.L35:
movq %rbp, %rsi
addq 80(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 104(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 24(%rsp), %rax
leaq 0(%rbp,%rax), %r12
movq %r12, %rsi
addq 80(%rsp), %rsi
movq 72(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 128(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbp, %rsi
addq 88(%rsp), %rsi
movq 64(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %r12, %rsi
addq 88(%rsp), %rsi
movq 72(%rsp), %r8
movl $1, %ecx
movq %rbx, %rdx
movq 136(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl %r13d, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl 12(%rsp), %eax
cltd
idivl %r13d
movl %eax, %r15d
movl %eax, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 64(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl 12(%rsp), %ecx
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
jmp .L33
.L40:
movl 12(%rsp), %ecx
movq 144(%rsp), %rdx
movq 136(%rsp), %rsi
movq 128(%rsp), %rdi
call _Z33__device_stub__Z9gpuKernelPiS_S_iPiS_S_i
jmp .L34
.L41:
movq 40(%rsp), %r15
.L32:
movq 64(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 72(%rsp), %rdi
call cudaStreamSynchronize@PLT
call _Z8get_timev
movq %rax, %rbx
movq %rax, %rdi
call cudaEventSynchronize@PLT
leaq 164(%rsp), %rdi
movq %rbx, %rdx
movq %r15, %rsi
call cudaEventElapsedTime@PLT
movq 80(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rdi
call cudaFreeHost@PLT
movq 96(%rsp), %rdi
call cudaFreeHost@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call cudaEventDestroy@PLT
movq %rbx, %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 72(%rsp), %rdi
call cudaStreamDestroy@PLT
movss 164(%rsp), %xmm0
.L29:
movq 1208(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $1224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z34execute_concurrent_streamed_kerneliii, .-_Z34execute_concurrent_streamed_kerneliii
.section .rodata.str1.8
.align 8
.LC2:
.string "Number of total threads is not divisible by number of elements to process in each stream iteration.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "========================\n"
.LC4:
.string "Summary\n"
.LC5:
.string "Total Threads: %d\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Number of concurrent kernel instances: %d\n"
.section .rodata.str1.1
.LC7:
.string "Thread Size: %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Time to copy memory and execute kernel with two streams running concurrently.\n"
.section .rodata.str1.1
.LC9:
.string "duration: %fms\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Time to copy memory and execute kernel running using a normal kernel execution.\n"
.section .rodata.str1.1
.LC11:
.string "duration: %fms\n\n\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
cmpl $1, %edi
jg .L54
movl $256, %ebx
movl $4096, %r12d
movl $128, %ebp
.L44:
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
je .L48
.L47:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L52:
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %edi, %ebx
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
cmpl $2, %ebx
jg .L55
testb %al, %al
jne .L47
movl $256, %ebx
movl $128, %ebp
.L48:
movl %ebp, %edx
movl %ebx, %esi
movl %r12d, %edi
call _Z34execute_concurrent_streamed_kerneliii
movss %xmm0, 8(%rsp)
movl %ebp, %esi
movl %r12d, %edi
call _Z14execute_kernelii
movss %xmm0, 12(%rsp)
leaq .LC3(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L52
.L55:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
cmpl $3, %ebx
jle .L51
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
.L46:
movl %r13d, %ebx
movl %r12d, %eax
cltd
idivl %r13d
testl %edx, %edx
jne .L47
jmp .L44
.L51:
movl $128, %ebp
jmp .L46
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z9gpuKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpuKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "assignment.hip"
.globl _Z8get_timev # -- Begin function _Z8get_timev
.p2align 4, 0x90
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8get_timev, .Lfunc_end0-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z18generate_rand_dataPii # -- Begin function _Z18generate_rand_dataPii
.p2align 4, 0x90
.type _Z18generate_rand_dataPii,@function
_Z18generate_rand_dataPii: # @_Z18generate_rand_dataPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z18generate_rand_dataPii, .Lfunc_end1-_Z18generate_rand_dataPii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpuKernelPiS_S_i # -- Begin function _Z24__device_stub__gpuKernelPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__gpuKernelPiS_S_i,@function
_Z24__device_stub__gpuKernelPiS_S_i: # @_Z24__device_stub__gpuKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpuKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__gpuKernelPiS_S_i, .Lfunc_end2-_Z24__device_stub__gpuKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z34execute_concurrent_streamed_kerneliii # -- Begin function _Z34execute_concurrent_streamed_kerneliii
.p2align 4, 0x90
.type _Z34execute_concurrent_streamed_kerneliii,@function
_Z34execute_concurrent_streamed_kerneliii: # @_Z34execute_concurrent_streamed_kerneliii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 1792
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 28(%rsp) # 4-byte Spill
movl %esi, %ebx
movl %edi, %r12d
leaq 220(%rsp), %rdi
callq hipGetDevice
movl 220(%rsp), %esi
leaq 264(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 648(%rsp)
je .LBB3_1
# %bb.2:
movq %rbx, 80(%rsp) # 8-byte Spill
leal (,%rbx,4), %ebx
leal (,%r12,4), %ebp
leaq 16(%rsp), %rdi
callq hipStreamCreate
leaq 8(%rsp), %rdi
callq hipStreamCreate
movslq %ebp, %r15
leaq 40(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 136(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
movslq %ebx, %r15
leaq 128(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 120(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 112(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 104(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 96(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl %r12d, %ebp
testl %r12d, %r12d
je .LBB3_5
# %bb.3: # %.lr.ph.preheader.i
movq 40(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB3_4
.LBB3_5: # %_Z18generate_rand_dataPii.exit
testl %r12d, %r12d
je .LBB3_8
# %bb.6: # %.lr.ph.preheader.i55
movq 32(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i57
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB3_7
.LBB3_8: # %_Z18generate_rand_dataPii.exit61
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rax
movq %rax, 224(%rsp) # 8-byte Spill
testl %r12d, %r12d
movq 80(%rsp), %r12 # 8-byte Reload
jle .LBB3_15
# %bb.9: # %.lr.ph
movslq %r12d, %rbx
movabsq $4294967296, %rax # imm = 0x100000000
movl 28(%rsp), %ecx # 4-byte Reload
orq %rax, %rcx
movq %rcx, 256(%rsp) # 8-byte Spill
leal (%r12,%r12), %eax
cltq
movq %rax, 240(%rsp) # 8-byte Spill
leaq (,%rax,4), %rax
movq %rax, 232(%rsp) # 8-byte Spill
shlq $2, %rbx
xorl %r14d, %r14d
xorl %r13d, %r13d
movq %rbp, 248(%rsp) # 8-byte Spill
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_14: # in Loop: Header=BB3_10 Depth=1
movq 136(%rsp), %rdi
addq %r14, %rdi
movq 112(%rsp), %rsi
movq 16(%rsp), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 136(%rsp), %rdi
addq %rbx, %rdi
addq %r14, %rdi
movq 88(%rsp), %rsi
movq 8(%rsp), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
addq 240(%rsp), %r13 # 8-byte Folded Reload
addq 232(%rsp), %r14 # 8-byte Folded Reload
movq 248(%rsp), %rbp # 8-byte Reload
cmpq %rbp, %r13
jge .LBB3_15
.LBB3_10: # =>This Inner Loop Header: Depth=1
movq 128(%rsp), %rdi
movq 40(%rsp), %rsi
addq %r14, %rsi
movq 16(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 104(%rsp), %rdi
movq 40(%rsp), %rsi
addq %rbx, %rsi
addq %r14, %rsi
movq 8(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 120(%rsp), %rdi
movq 32(%rsp), %rsi
addq %r14, %rsi
movq 16(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 96(%rsp), %rdi
movq 32(%rsp), %rsi
addq %rbx, %rsi
addq %r14, %rsi
movq 8(%rsp), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movl %r12d, %eax
cltd
idivl 28(%rsp) # 4-byte Folded Reload
movl %eax, %r12d
movq 16(%rsp), %r9
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movq %r12, %rdi
movl $1, %esi
movq 256(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11: # in Loop: Header=BB3_10 Depth=1
movq 128(%rsp), %rax
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movq %rdx, 192(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, 4(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 200(%rsp), %rax
movq %rax, 56(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z9gpuKernelPiS_S_i, %edi
leaq 48(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_12: # in Loop: Header=BB3_10 Depth=1
movq 8(%rsp), %r9
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 80(%rsp), %r12 # 8-byte Reload
jne .LBB3_14
# %bb.13: # in Loop: Header=BB3_10 Depth=1
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 208(%rsp)
movq %rcx, 200(%rsp)
movq %rdx, 192(%rsp)
movl %r12d, 4(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 200(%rsp), %rax
movq %rax, 56(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z9gpuKernelPiS_S_i, %edi
leaq 48(%rsp), %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_14
.LBB3_15: # %._crit_edge
movq 16(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
callq hipStreamSynchronize
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rbx
movq %rbx, %rdi
callq hipEventSynchronize
leaq 48(%rsp), %rdi
movq 224(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %rbx, %rdx
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 136(%rsp), %rdi
callq hipHostFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipStreamDestroy
movq 8(%rsp), %rdi
callq hipStreamDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB3_16
.LBB3_1:
movl $.Lstr, %edi
callq puts@PLT
xorps %xmm0, %xmm0
.LBB3_16:
addq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z34execute_concurrent_streamed_kerneliii, .Lfunc_end3-_Z34execute_concurrent_streamed_kerneliii
.cfi_endproc
# -- End function
.globl _Z14execute_kernelii # -- Begin function _Z14execute_kernelii
.p2align 4, 0x90
.type _Z14execute_kernelii,@function
_Z14execute_kernelii: # @_Z14execute_kernelii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
leal (,%r14,4), %eax
movslq %eax, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 88(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r14d, %r15d
testl %r14d, %r14d
je .LBB4_3
# %bb.1: # %.lr.ph.preheader.i
movq 32(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB4_2
.LBB4_3: # %_Z18generate_rand_dataPii.exit
testl %r14d, %r14d
je .LBB4_6
# %bb.4: # %.lr.ph.preheader.i23
movq 24(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i25
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq %r13, %r15
jne .LBB4_5
.LBB4_6: # %_Z18generate_rand_dataPii.exit29
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %r15
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r14d, %eax
cltd
idivl %ebp
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rcx # imm = 0x100000000
leaq (%rax,%rcx), %rdi
movl %ebp, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %r14d, 44(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9gpuKernelPiS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
movq 88(%rsp), %rdi
movq (%rsp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rbx
movq %rbx, %rdi
callq hipEventSynchronize
leaq 48(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 88(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq hipEventDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14execute_kernelii, .Lfunc_end4-_Z14execute_kernelii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movl %edi, %ebp
movl $4096, %ebx # imm = 0x1000
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
movl $256, %r14d # imm = 0x100
cmpl $3, %ebp
jl .LBB5_4
# %bb.3:
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
.LBB5_4:
movl $128, %r15d
cmpl $4, %ebp
jl .LBB5_6
# %bb.5:
movq 24(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB5_6:
movl %ebx, %eax
cltd
idivl %r14d
testl %edx, %edx
jne .LBB5_8
# %bb.7:
movl %r14d, %eax
cltd
idivl %r15d
testl %edx, %edx
je .LBB5_9
.LBB5_8:
movl $.Lstr.7, %edi
callq puts@PLT
.LBB5_10:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_9:
.cfi_def_cfa_offset 64
movl %ebx, %edi
movl %r14d, %esi
movl %r15d, %edx
callq _Z34execute_concurrent_streamed_kerneliii
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %ebx, %edi
movl %r15d, %esi
callq _Z14execute_kernelii
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
jmp .LBB5_10
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpuKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpuKernelPiS_S_i,@object # @_Z9gpuKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9gpuKernelPiS_S_i
.p2align 3, 0x0
_Z9gpuKernelPiS_S_i:
.quad _Z24__device_stub__gpuKernelPiS_S_i
.size _Z9gpuKernelPiS_S_i, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Total Threads: %d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Number of concurrent kernel instances: %d\n"
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Thread Size: %d\n"
.size .L.str.6, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "duration: %fms\n"
.size .L.str.8, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "duration: %fms\n\n\n"
.size .L.str.10, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpuKernelPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device will not handle overlaps, so no speedup from streams"
.size .Lstr, 60
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Summary"
.size .Lstr.2, 8
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Time to copy memory and execute kernel with two streams running concurrently."
.size .Lstr.4, 78
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "========================"
.size .Lstr.5, 25
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Time to copy memory and execute kernel running using a normal kernel execution."
.size .Lstr.6, 80
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Number of total threads is not divisible by number of elements to process in each stream iteration."
.size .Lstr.7, 100
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpuKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpuKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void pnpolyGPU(const float *vertex, float testx, float testy, int* results)
{
int id = blockIdx.x;
int indexOriginX = (blockIdx.x + 1) * 3;
int indexOriginY = (blockIdx.x + 1) * 3 + 1;
int indexDestinoX = blockIdx.x * 3;
int indexDestinoY = blockIdx.x * 3 + 1;
if ( ((vertex[indexOriginY]>testy) != (vertex[indexDestinoY]>testy)) && (testx < (vertex[indexDestinoX]-vertex[indexOriginX]) * (testy-vertex[indexOriginY]) / (vertex[indexDestinoY]-vertex[indexOriginY]) + vertex[indexOriginX]) )
results[id] = 1;
else
results[id] = 0;
} | code for sm_80
Function : _Z9pnpolyGPUPKfffPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD R4, R0, 0x3, RZ ; /* 0x0000000300047824 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0060*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R3, [R4.64+0x10] ; /* 0x0000100404037981 */
/* 0x000ee2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0090*/ FSETP.GT.AND P0, PT, R6, c[0x0][0x16c], PT ; /* 0x00005b0006007a0b */
/* 0x004fc80003f04000 */
/*00a0*/ FSETP.GT.XOR P0, PT, R3, c[0x0][0x16c], P0 ; /* 0x00005b0003007a0b */
/* 0x008fda0000704800 */
/*00b0*/ @!P0 BRA 0x1f0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R2, [R4.64+0xc] ; /* 0x00000c0404027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ FADD R9, -R3.reuse, R6 ; /* 0x0000000603097221 */
/* 0x040fe40000000100 */
/*00f0*/ FADD R6, -R3, c[0x0][0x16c] ; /* 0x00005b0003067621 */
/* 0x000fe40000000100 */
/*0100*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e240000001000 */
/*0110*/ FFMA R3, -R9, R8, 1 ; /* 0x3f80000009037423 */
/* 0x001fc80000000108 */
/*0120*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fe40000000008 */
/*0130*/ FADD R7, R7, -R2 ; /* 0x8000000207077221 */
/* 0x004fc80000000000 */
/*0140*/ FMUL R6, R7, R6 ; /* 0x0000000607067220 */
/* 0x000fc80000400000 */
/*0150*/ FCHK P0, R6, R9 ; /* 0x0000000906007302 */
/* 0x000e220000000000 */
/*0160*/ FFMA R8, R6, R3, RZ ; /* 0x0000000306087223 */
/* 0x000fc800000000ff */
/*0170*/ FFMA R7, -R9, R8, R6 ; /* 0x0000000809077223 */
/* 0x000fc80000000106 */
/*0180*/ FFMA R3, R3, R7, R8 ; /* 0x0000000703037223 */
/* 0x000fe20000000008 */
/*0190*/ @!P0 BRA 0x1c0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01a0*/ MOV R4, 0x1c0 ; /* 0x000001c000047802 */
/* 0x000fe40000000f00 */
/*01b0*/ CALL.REL.NOINC 0x230 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*01c0*/ FADD R3, R2, R3 ; /* 0x0000000302037221 */
/* 0x001fca0000000000 */
/*01d0*/ FSETP.GT.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0b */
/* 0x000fc80003f04000 */
/*01e0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.U32.HI R5, RZ, 0x17, R9.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011609 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, R6.reuse ; /* 0x000000ffff077224 */
/* 0x100fe200078e0006 */
/*0250*/ SHF.R.U32.HI R3, RZ, 0x17, R6 ; /* 0x00000017ff037819 */
/* 0x000fe20000011606 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0009 */
/*0270*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0280*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0290*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fc40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*0300*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x840 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0340*/ @!P0 BRA 0x820 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x820 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x800 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7d0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R7, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006078823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R8, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009089823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R9, R5, 0xc0800000, 0x17 ; /* 0xc080000005097811 */
/* 0x000fe400078eb8ff */
/*0470*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe400078e0a09 */
/*0490*/ IMAD R7, R6, -0x800000, R7 ; /* 0xff80000006077824 */
/* 0x000fe400078e0207 */
/*04a0*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*04b0*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fc80000010100 */
/*04c0*/ FFMA R3, R8, R12, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000c */
/*04d0*/ FFMA R14, R8, R3, R8 ; /* 0x00000003080e7223 */
/* 0x000fc80000000008 */
/*04e0*/ FFMA R3, R7, R14, RZ ; /* 0x0000000e07037223 */
/* 0x000fc800000000ff */
/*04f0*/ FFMA R8, R12, R3, R7 ; /* 0x000000030c087223 */
/* 0x000fc80000000007 */
/*0500*/ FFMA R11, R14, R8, R3 ; /* 0x000000080e0b7223 */
/* 0x000fc80000000003 */
/*0510*/ FFMA R12, R12, R11, R7 ; /* 0x0000000b0c0c7223 */
/* 0x000fe20000000007 */
/*0520*/ IADD3 R7, R6, 0x7f, -R5 ; /* 0x0000007f06077810 */
/* 0x000fc60007ffe805 */
/*0530*/ FFMA R3, R14, R12, R11 ; /* 0x0000000c0e037223 */
/* 0x000fe4000000000b */
/*0540*/ IMAD.IADD R10, R7, 0x1, R10 ; /* 0x00000001070a7824 */
/* 0x000fc600078e020a */
/*0550*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0560*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0570*/ IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105097824 */
/* 0x000fca00078e020a */
/*0580*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05a0*/ @!P0 BRA 0x7b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05c0*/ @P0 BRA 0x780 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05e0*/ @P0 BRA 0x850 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0600*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0610*/ @!P0 BRA 0x850 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0620*/ FFMA.RZ R5, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e057223 */
/* 0x1c0fe2000000c00b */
/*0630*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe20007ffe0ff */
/*0640*/ FFMA.RM R6, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e067223 */
/* 0x1c0fe2000000400b */
/*0650*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0660*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0670*/ FFMA.RP R5, R14, R12, R11 ; /* 0x0000000c0e057223 */
/* 0x000fe2000000800b */
/*0680*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0690*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06a0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*06b0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*06c0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06d0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06e0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06f0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0710*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0720*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0730*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0740*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0750*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0760*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x850 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0790*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x850 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe200078e0203 */
/*07c0*/ BRA 0x850 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07e0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0810*/ BRA 0x850 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0820*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0830*/ BRA 0x850 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0840*/ FADD.FTZ R3, R6, R9 ; /* 0x0000000906037221 */
/* 0x000fe40000010000 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0860*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff79004007950 */
/* 0x000fea0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void pnpolyGPU(const float *vertex, float testx, float testy, int* results)
{
int id = blockIdx.x;
int indexOriginX = (blockIdx.x + 1) * 3;
int indexOriginY = (blockIdx.x + 1) * 3 + 1;
int indexDestinoX = blockIdx.x * 3;
int indexDestinoY = blockIdx.x * 3 + 1;
if ( ((vertex[indexOriginY]>testy) != (vertex[indexDestinoY]>testy)) && (testx < (vertex[indexDestinoX]-vertex[indexOriginX]) * (testy-vertex[indexOriginY]) / (vertex[indexDestinoY]-vertex[indexOriginY]) + vertex[indexOriginX]) )
results[id] = 1;
else
results[id] = 0;
} | .file "tmpxft_000abc65_00000000-6_pnpolyGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi
.type _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi, @function
_Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9pnpolyGPUPKfffPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi, .-_Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi
.globl _Z9pnpolyGPUPKfffPi
.type _Z9pnpolyGPUPKfffPi, @function
_Z9pnpolyGPUPKfffPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9pnpolyGPUPKfffPi, .-_Z9pnpolyGPUPKfffPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9pnpolyGPUPKfffPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pnpolyGPUPKfffPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void pnpolyGPU(const float *vertex, float testx, float testy, int* results)
{
int id = blockIdx.x;
int indexOriginX = (blockIdx.x + 1) * 3;
int indexOriginY = (blockIdx.x + 1) * 3 + 1;
int indexDestinoX = blockIdx.x * 3;
int indexDestinoY = blockIdx.x * 3 + 1;
if ( ((vertex[indexOriginY]>testy) != (vertex[indexDestinoY]>testy)) && (testx < (vertex[indexDestinoX]-vertex[indexOriginX]) * (testy-vertex[indexOriginY]) / (vertex[indexDestinoY]-vertex[indexOriginY]) + vertex[indexOriginX]) )
results[id] = 1;
else
results[id] = 0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pnpolyGPU(const float *vertex, float testx, float testy, int* results)
{
int id = blockIdx.x;
int indexOriginX = (blockIdx.x + 1) * 3;
int indexOriginY = (blockIdx.x + 1) * 3 + 1;
int indexDestinoX = blockIdx.x * 3;
int indexDestinoY = blockIdx.x * 3 + 1;
if ( ((vertex[indexOriginY]>testy) != (vertex[indexDestinoY]>testy)) && (testx < (vertex[indexDestinoX]-vertex[indexOriginX]) * (testy-vertex[indexOriginY]) / (vertex[indexDestinoY]-vertex[indexOriginY]) + vertex[indexOriginX]) )
results[id] = 1;
else
results[id] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pnpolyGPU(const float *vertex, float testx, float testy, int* results)
{
int id = blockIdx.x;
int indexOriginX = (blockIdx.x + 1) * 3;
int indexOriginY = (blockIdx.x + 1) * 3 + 1;
int indexDestinoX = blockIdx.x * 3;
int indexDestinoY = blockIdx.x * 3 + 1;
if ( ((vertex[indexOriginY]>testy) != (vertex[indexDestinoY]>testy)) && (testx < (vertex[indexDestinoX]-vertex[indexOriginX]) * (testy-vertex[indexOriginY]) / (vertex[indexDestinoY]-vertex[indexOriginY]) + vertex[indexOriginX]) )
results[id] = 1;
else
results[id] = 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9pnpolyGPUPKfffPi
.globl _Z9pnpolyGPUPKfffPi
.p2align 8
.type _Z9pnpolyGPUPKfffPi,@function
_Z9pnpolyGPUPKfffPi:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0xc
s_mul_i32 s6, s15, 3
s_mov_b32 s2, s15
s_add_i32 s8, s6, 4
s_add_i32 s10, s6, 1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[10:11], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_clause 0x1
s_load_b32 s9, s[8:9], 0x0
s_load_b32 s10, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s7, s9, s3
v_cmp_ngt_f32_e64 s8, s10, s3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s7, s7, s8
s_mov_b32 s8, 1
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s7, s6, 31
v_sub_f32_e64 v0, s3, s9
s_lshl_b64 s[12:13], s[6:7], 2
s_add_i32 s6, s6, 3
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_ashr_i32 s7, s6, 31
v_sub_f32_e64 v2, s10, s9
s_lshl_b64 s[6:7], s[6:7], 2
s_load_b32 s3, s[0:1], 0x8
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_clause 0x1
s_load_b32 s6, s[12:13], 0x0
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s6, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v1
v_div_scale_f32 v1, null, v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v1, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v3
v_fma_f32 v6, -v1, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v3
v_fma_f32 v1, -v1, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v3, v5
v_div_fixup_f32 v0, v1, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, s4, v0
v_cmp_nlt_f32_e64 s7, s3, v0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_4
s_mov_b32 s8, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s8
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9pnpolyGPUPKfffPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9pnpolyGPUPKfffPi, .Lfunc_end0-_Z9pnpolyGPUPKfffPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9pnpolyGPUPKfffPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9pnpolyGPUPKfffPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pnpolyGPU(const float *vertex, float testx, float testy, int* results)
{
int id = blockIdx.x;
int indexOriginX = (blockIdx.x + 1) * 3;
int indexOriginY = (blockIdx.x + 1) * 3 + 1;
int indexDestinoX = blockIdx.x * 3;
int indexDestinoY = blockIdx.x * 3 + 1;
if ( ((vertex[indexOriginY]>testy) != (vertex[indexDestinoY]>testy)) && (testx < (vertex[indexDestinoX]-vertex[indexOriginX]) * (testy-vertex[indexOriginY]) / (vertex[indexDestinoY]-vertex[indexOriginY]) + vertex[indexOriginX]) )
results[id] = 1;
else
results[id] = 0;
} | .text
.file "pnpolyGPU.hip"
.globl _Z24__device_stub__pnpolyGPUPKfffPi # -- Begin function _Z24__device_stub__pnpolyGPUPKfffPi
.p2align 4, 0x90
.type _Z24__device_stub__pnpolyGPUPKfffPi,@function
_Z24__device_stub__pnpolyGPUPKfffPi: # @_Z24__device_stub__pnpolyGPUPKfffPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9pnpolyGPUPKfffPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__pnpolyGPUPKfffPi, .Lfunc_end0-_Z24__device_stub__pnpolyGPUPKfffPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9pnpolyGPUPKfffPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9pnpolyGPUPKfffPi,@object # @_Z9pnpolyGPUPKfffPi
.section .rodata,"a",@progbits
.globl _Z9pnpolyGPUPKfffPi
.p2align 3, 0x0
_Z9pnpolyGPUPKfffPi:
.quad _Z24__device_stub__pnpolyGPUPKfffPi
.size _Z9pnpolyGPUPKfffPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9pnpolyGPUPKfffPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__pnpolyGPUPKfffPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9pnpolyGPUPKfffPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9pnpolyGPUPKfffPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD R4, R0, 0x3, RZ ; /* 0x0000000300047824 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0060*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R3, [R4.64+0x10] ; /* 0x0000100404037981 */
/* 0x000ee2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0090*/ FSETP.GT.AND P0, PT, R6, c[0x0][0x16c], PT ; /* 0x00005b0006007a0b */
/* 0x004fc80003f04000 */
/*00a0*/ FSETP.GT.XOR P0, PT, R3, c[0x0][0x16c], P0 ; /* 0x00005b0003007a0b */
/* 0x008fda0000704800 */
/*00b0*/ @!P0 BRA 0x1f0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R2, [R4.64+0xc] ; /* 0x00000c0404027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ FADD R9, -R3.reuse, R6 ; /* 0x0000000603097221 */
/* 0x040fe40000000100 */
/*00f0*/ FADD R6, -R3, c[0x0][0x16c] ; /* 0x00005b0003067621 */
/* 0x000fe40000000100 */
/*0100*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e240000001000 */
/*0110*/ FFMA R3, -R9, R8, 1 ; /* 0x3f80000009037423 */
/* 0x001fc80000000108 */
/*0120*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fe40000000008 */
/*0130*/ FADD R7, R7, -R2 ; /* 0x8000000207077221 */
/* 0x004fc80000000000 */
/*0140*/ FMUL R6, R7, R6 ; /* 0x0000000607067220 */
/* 0x000fc80000400000 */
/*0150*/ FCHK P0, R6, R9 ; /* 0x0000000906007302 */
/* 0x000e220000000000 */
/*0160*/ FFMA R8, R6, R3, RZ ; /* 0x0000000306087223 */
/* 0x000fc800000000ff */
/*0170*/ FFMA R7, -R9, R8, R6 ; /* 0x0000000809077223 */
/* 0x000fc80000000106 */
/*0180*/ FFMA R3, R3, R7, R8 ; /* 0x0000000703037223 */
/* 0x000fe20000000008 */
/*0190*/ @!P0 BRA 0x1c0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01a0*/ MOV R4, 0x1c0 ; /* 0x000001c000047802 */
/* 0x000fe40000000f00 */
/*01b0*/ CALL.REL.NOINC 0x230 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*01c0*/ FADD R3, R2, R3 ; /* 0x0000000302037221 */
/* 0x001fca0000000000 */
/*01d0*/ FSETP.GT.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0b */
/* 0x000fc80003f04000 */
/*01e0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.U32.HI R5, RZ, 0x17, R9.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011609 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, R6.reuse ; /* 0x000000ffff077224 */
/* 0x100fe200078e0006 */
/*0250*/ SHF.R.U32.HI R3, RZ, 0x17, R6 ; /* 0x00000017ff037819 */
/* 0x000fe20000011606 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0009 */
/*0270*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0280*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0290*/ IADD3 R12, R5, -0x1, RZ ; /* 0xffffffff050c7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fc40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*0300*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x840 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0340*/ @!P0 BRA 0x820 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x820 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x800 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7d0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R7, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006078823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R8, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009089823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R9, R5, 0xc0800000, 0x17 ; /* 0xc080000005097811 */
/* 0x000fe400078eb8ff */
/*0470*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD.IADD R9, R8, 0x1, -R9 ; /* 0x0000000108097824 */
/* 0x000fe400078e0a09 */
/*0490*/ IMAD R7, R6, -0x800000, R7 ; /* 0xff80000006077824 */
/* 0x000fe400078e0207 */
/*04a0*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*04b0*/ FADD.FTZ R12, -R9, -RZ ; /* 0x800000ff090c7221 */
/* 0x000fc80000010100 */
/*04c0*/ FFMA R3, R8, R12, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000c */
/*04d0*/ FFMA R14, R8, R3, R8 ; /* 0x00000003080e7223 */
/* 0x000fc80000000008 */
/*04e0*/ FFMA R3, R7, R14, RZ ; /* 0x0000000e07037223 */
/* 0x000fc800000000ff */
/*04f0*/ FFMA R8, R12, R3, R7 ; /* 0x000000030c087223 */
/* 0x000fc80000000007 */
/*0500*/ FFMA R11, R14, R8, R3 ; /* 0x000000080e0b7223 */
/* 0x000fc80000000003 */
/*0510*/ FFMA R12, R12, R11, R7 ; /* 0x0000000b0c0c7223 */
/* 0x000fe20000000007 */
/*0520*/ IADD3 R7, R6, 0x7f, -R5 ; /* 0x0000007f06077810 */
/* 0x000fc60007ffe805 */
/*0530*/ FFMA R3, R14, R12, R11 ; /* 0x0000000c0e037223 */
/* 0x000fe4000000000b */
/*0540*/ IMAD.IADD R10, R7, 0x1, R10 ; /* 0x00000001070a7824 */
/* 0x000fc600078e020a */
/*0550*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0560*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0570*/ IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105097824 */
/* 0x000fca00078e020a */
/*0580*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05a0*/ @!P0 BRA 0x7b0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*05c0*/ @P0 BRA 0x780 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05e0*/ @P0 BRA 0x850 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0600*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0610*/ @!P0 BRA 0x850 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0620*/ FFMA.RZ R5, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e057223 */
/* 0x1c0fe2000000c00b */
/*0630*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe20007ffe0ff */
/*0640*/ FFMA.RM R6, R14.reuse, R12.reuse, R11.reuse ; /* 0x0000000c0e067223 */
/* 0x1c0fe2000000400b */
/*0650*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0660*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0670*/ FFMA.RP R5, R14, R12, R11 ; /* 0x0000000c0e057223 */
/* 0x000fe2000000800b */
/*0680*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0690*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06a0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*06b0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*06c0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*06d0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*06e0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*06f0*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0710*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0720*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0730*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0740*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0750*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0760*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x850 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0790*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x850 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe200078e0203 */
/*07c0*/ BRA 0x850 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07e0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0810*/ BRA 0x850 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0820*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0830*/ BRA 0x850 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0840*/ FADD.FTZ R3, R6, R9 ; /* 0x0000000906037221 */
/* 0x000fe40000010000 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0860*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff79004007950 */
/* 0x000fea0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9pnpolyGPUPKfffPi
.globl _Z9pnpolyGPUPKfffPi
.p2align 8
.type _Z9pnpolyGPUPKfffPi,@function
_Z9pnpolyGPUPKfffPi:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0xc
s_mul_i32 s6, s15, 3
s_mov_b32 s2, s15
s_add_i32 s8, s6, 4
s_add_i32 s10, s6, 1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[10:11], s[10:11], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s4, s10
s_addc_u32 s11, s5, s11
s_clause 0x1
s_load_b32 s9, s[8:9], 0x0
s_load_b32 s10, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s7, s9, s3
v_cmp_ngt_f32_e64 s8, s10, s3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s7, s7, s8
s_mov_b32 s8, 1
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s7, s6, 31
v_sub_f32_e64 v0, s3, s9
s_lshl_b64 s[12:13], s[6:7], 2
s_add_i32 s6, s6, 3
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_ashr_i32 s7, s6, 31
v_sub_f32_e64 v2, s10, s9
s_lshl_b64 s[6:7], s[6:7], 2
s_load_b32 s3, s[0:1], 0x8
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_clause 0x1
s_load_b32 s6, s[12:13], 0x0
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s6, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, v0, v1
v_div_scale_f32 v1, null, v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v1, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
v_div_scale_f32 v4, vcc_lo, v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v3
v_fma_f32 v6, -v1, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v3
v_fma_f32 v1, -v1, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v3, v5
v_div_fixup_f32 v0, v1, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, s4, v0
v_cmp_nlt_f32_e64 s7, s3, v0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_4
s_mov_b32 s8, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s8
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9pnpolyGPUPKfffPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9pnpolyGPUPKfffPi, .Lfunc_end0-_Z9pnpolyGPUPKfffPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9pnpolyGPUPKfffPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9pnpolyGPUPKfffPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000abc65_00000000-6_pnpolyGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi
.type _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi, @function
_Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9pnpolyGPUPKfffPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi, .-_Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi
.globl _Z9pnpolyGPUPKfffPi
.type _Z9pnpolyGPUPKfffPi, @function
_Z9pnpolyGPUPKfffPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9pnpolyGPUPKfffPiPKfffPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9pnpolyGPUPKfffPi, .-_Z9pnpolyGPUPKfffPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9pnpolyGPUPKfffPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pnpolyGPUPKfffPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pnpolyGPU.hip"
.globl _Z24__device_stub__pnpolyGPUPKfffPi # -- Begin function _Z24__device_stub__pnpolyGPUPKfffPi
.p2align 4, 0x90
.type _Z24__device_stub__pnpolyGPUPKfffPi,@function
_Z24__device_stub__pnpolyGPUPKfffPi: # @_Z24__device_stub__pnpolyGPUPKfffPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9pnpolyGPUPKfffPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__pnpolyGPUPKfffPi, .Lfunc_end0-_Z24__device_stub__pnpolyGPUPKfffPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9pnpolyGPUPKfffPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9pnpolyGPUPKfffPi,@object # @_Z9pnpolyGPUPKfffPi
.section .rodata,"a",@progbits
.globl _Z9pnpolyGPUPKfffPi
.p2align 3, 0x0
_Z9pnpolyGPUPKfffPi:
.quad _Z24__device_stub__pnpolyGPUPKfffPi
.size _Z9pnpolyGPUPKfffPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9pnpolyGPUPKfffPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__pnpolyGPUPKfffPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9pnpolyGPUPKfffPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <vector>
#include <random>
#include <time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
using std::vector;
using std::random_device;
using std::mt19937;
using std::uniform_real_distribution;
#define SIZE 100000
int main()
{
clock_t start = clock();
random_device rnd;
mt19937 mt;
mt.seed(rnd());
uniform_real_distribution<double> real_rnd(0.0, 1.0);
vector<double> host_w(SIZE, 10.0);
vector<double> host_input(SIZE);
vector<double> host_output(SIZE);
for(int i = 0; i < SIZE; ++i) host_input[i] = real_rnd(mt);
// allocate device side vector
thrust::device_vector<double> device_w(SIZE);
thrust::device_vector<double> device_input(SIZE);
thrust::device_vector<double> device_output(SIZE);
// copy host to device
thrust::copy(host_w.begin(), host_w.end(), device_w.begin());
thrust::copy(host_input.begin(), host_input.end(), device_input.begin());
// device_output = device_w * device_input
clock_t transform_start = clock();
thrust::transform(device_w.begin(), device_w.end(), device_input.begin(), device_output.begin(), thrust::multiplies<double>());
clock_t transform_end = clock();
// copy device to host
thrust::copy(device_output.begin(), device_output.end(), host_output.begin());
clock_t end = clock();
std::cout << "transform time: " << (double)(transform_end - transform_start) / CLOCKS_PER_SEC << std::endl;
std::cout << "program time: " << (double)(end - start) / CLOCKS_PER_SEC << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIdEEEESF_SF_NS9_14no_stencil_tagENS7_10multipliesIdEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x8, RZ ; /* 0x0000000800027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x3, R5 ; /* 0x0000000300007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*01d0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1b00 */
/*01e0*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x004e0e0000000000 */
/*01f0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0011e8000c101b04 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E.64 R6, [R6.64+0x800] ; /* 0x0008000406067981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ LDG.E.64 R4, [R4.64+0x800] ; /* 0x0008000404047981 */
/* 0x000ea4000c1e1b00 */
/*0240*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x005e0e0000000000 */
/*0250*/ STG.E.64 [R2.64+0x800], R8 ; /* 0x0008000802007986 */
/* 0x001fe2000c101b04 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1b00 */
/*0290*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x004e0e0000000000 */
/*02a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x001fe8000c101b04 */
/*02b0*/ LDG.E.64 R10, [R6.64+0x800] ; /* 0x00080004060a7981 */
/* 0x000ea8000c1e1b00 */
/*02c0*/ LDG.E.64 R12, [R4.64+0x800] ; /* 0x00080004040c7981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ DMUL R10, R10, R12 ; /* 0x0000000c0a0a7228 */
/* 0x004e0e0000000000 */
/*02e0*/ STG.E.64 [R2.64+0x800], R10 ; /* 0x0008000a02007986 */
/* 0x001fe2000c101b04 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIdEEdEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R6, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R7, RZ ; /* 0x0000000702007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R4, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003047a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000027a11 */
/* 0x000fe400078218ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x3, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1c03 */
/*00d0*/ @P0 BRA 0x1c0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0100*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff040624 */
/* 0x000fe400078e00ff */
/*0130*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff050624 */
/* 0x000fca00078e00ff */
/*0140*/ @P0 STG.E.64 [R2.64], R4 ; /* 0x0000000402000986 */
/* 0x0001e2000c101b04 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fc80003f04070 */
/*0160*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04100 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*01a0*/ STG.E.64 [R2.64+0x800], R4 ; /* 0x0008000402007986 */
/* 0x000fe2000c101b04 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*01e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b04 */
/*01f0*/ STG.E.64 [R2.64+0x800], R4 ; /* 0x0008000402007986 */
/* 0x000fe2000c101b04 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
#include <random>
#include <time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
using std::vector;
using std::random_device;
using std::mt19937;
using std::uniform_real_distribution;
#define SIZE 100000
int main()
{
clock_t start = clock();
random_device rnd;
mt19937 mt;
mt.seed(rnd());
uniform_real_distribution<double> real_rnd(0.0, 1.0);
vector<double> host_w(SIZE, 10.0);
vector<double> host_input(SIZE);
vector<double> host_output(SIZE);
for(int i = 0; i < SIZE; ++i) host_input[i] = real_rnd(mt);
// allocate device side vector
thrust::device_vector<double> device_w(SIZE);
thrust::device_vector<double> device_input(SIZE);
thrust::device_vector<double> device_output(SIZE);
// copy host to device
thrust::copy(host_w.begin(), host_w.end(), device_w.begin());
thrust::copy(host_input.begin(), host_input.end(), device_input.begin());
// device_output = device_w * device_input
clock_t transform_start = clock();
thrust::transform(device_w.begin(), device_w.end(), device_input.begin(), device_output.begin(), thrust::multiplies<double>());
clock_t transform_end = clock();
// copy device to host
thrust::copy(device_output.begin(), device_output.end(), host_output.begin());
clock_t end = clock();
std::cout << "transform time: " << (double)(transform_end - transform_start) / CLOCKS_PER_SEC << std::endl;
std::cout << "program time: " << (double)(end - start) / CLOCKS_PER_SEC << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <random>
#include <time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
using std::vector;
using std::random_device;
using std::mt19937;
using std::uniform_real_distribution;
#define SIZE 100000
int main()
{
clock_t start = clock();
random_device rnd;
mt19937 mt;
mt.seed(rnd());
uniform_real_distribution<double> real_rnd(0.0, 1.0);
vector<double> host_w(SIZE, 10.0);
vector<double> host_input(SIZE);
vector<double> host_output(SIZE);
for(int i = 0; i < SIZE; ++i) host_input[i] = real_rnd(mt);
// allocate device side vector
thrust::device_vector<double> device_w(SIZE);
thrust::device_vector<double> device_input(SIZE);
thrust::device_vector<double> device_output(SIZE);
// copy host to device
thrust::copy(host_w.begin(), host_w.end(), device_w.begin());
thrust::copy(host_input.begin(), host_input.end(), device_input.begin());
// device_output = device_w * device_input
clock_t transform_start = clock();
thrust::transform(device_w.begin(), device_w.end(), device_input.begin(), device_output.begin(), thrust::multiplies<double>());
clock_t transform_end = clock();
// copy device to host
thrust::copy(device_output.begin(), device_output.end(), host_output.begin());
clock_t end = clock();
std::cout << "transform time: " << (double)(transform_end - transform_start) / CLOCKS_PER_SEC << std::endl;
std::cout << "program time: " << (double)(end - start) / CLOCKS_PER_SEC << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <random>
#include <time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform.h>
#include <thrust/copy.h>
using std::vector;
using std::random_device;
using std::mt19937;
using std::uniform_real_distribution;
#define SIZE 100000
int main()
{
clock_t start = clock();
random_device rnd;
mt19937 mt;
mt.seed(rnd());
uniform_real_distribution<double> real_rnd(0.0, 1.0);
vector<double> host_w(SIZE, 10.0);
vector<double> host_input(SIZE);
vector<double> host_output(SIZE);
for(int i = 0; i < SIZE; ++i) host_input[i] = real_rnd(mt);
// allocate device side vector
thrust::device_vector<double> device_w(SIZE);
thrust::device_vector<double> device_input(SIZE);
thrust::device_vector<double> device_output(SIZE);
// copy host to device
thrust::copy(host_w.begin(), host_w.end(), device_w.begin());
thrust::copy(host_input.begin(), host_input.end(), device_input.begin());
// device_output = device_w * device_input
clock_t transform_start = clock();
thrust::transform(device_w.begin(), device_w.end(), device_input.begin(), device_output.begin(), thrust::multiplies<double>());
clock_t transform_end = clock();
// copy device to host
thrust::copy(device_output.begin(), device_output.end(), host_output.begin());
clock_t end = clock();
std::cout << "transform time: " << (double)(transform_end - transform_start) / CLOCKS_PER_SEC << std::endl;
std::cout << "program time: " << (double)(end - start) / CLOCKS_PER_SEC << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_lshl_b64 s[0:1], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
flat_store_b64 v[0:1], v[2:3]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b64 v[2:3], v[2:3]
flat_load_b64 v[4:5], v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
flat_store_b64 v[0:1], v[2:3]
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIdEEEESF_SF_NS9_14no_stencil_tagENS7_10multipliesIdEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x8, RZ ; /* 0x0000000800027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x3, R5 ; /* 0x0000000300007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*01d0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1b00 */
/*01e0*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x004e0e0000000000 */
/*01f0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0011e8000c101b04 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E.64 R6, [R6.64+0x800] ; /* 0x0008000406067981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ LDG.E.64 R4, [R4.64+0x800] ; /* 0x0008000404047981 */
/* 0x000ea4000c1e1b00 */
/*0240*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x005e0e0000000000 */
/*0250*/ STG.E.64 [R2.64+0x800], R8 ; /* 0x0008000802007986 */
/* 0x001fe2000c101b04 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea4000c1e1b00 */
/*0290*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x004e0e0000000000 */
/*02a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x001fe8000c101b04 */
/*02b0*/ LDG.E.64 R10, [R6.64+0x800] ; /* 0x00080004060a7981 */
/* 0x000ea8000c1e1b00 */
/*02c0*/ LDG.E.64 R12, [R4.64+0x800] ; /* 0x00080004040c7981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ DMUL R10, R10, R12 ; /* 0x0000000c0a0a7228 */
/* 0x004e0e0000000000 */
/*02e0*/ STG.E.64 [R2.64+0x800], R10 ; /* 0x0008000a02007986 */
/* 0x001fe2000c101b04 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIdEEdEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R6, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R7, RZ ; /* 0x0000000702007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R4, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003047a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000027a11 */
/* 0x000fe400078218ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x3, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1c03 */
/*00d0*/ @P0 BRA 0x1c0 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0100*/ IADD3 R0, R7, 0x100, RZ ; /* 0x0000010007007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff040624 */
/* 0x000fe400078e00ff */
/*0130*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff050624 */
/* 0x000fca00078e00ff */
/*0140*/ @P0 STG.E.64 [R2.64], R4 ; /* 0x0000000402000986 */
/* 0x0001e2000c101b04 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fc80003f04070 */
/*0160*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04100 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*01a0*/ STG.E.64 [R2.64+0x800], R4 ; /* 0x0008000402007986 */
/* 0x000fe2000c101b04 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*01e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe8000c101b04 */
/*01f0*/ STG.E.64 [R2.64+0x800], R4 ; /* 0x0008000402007986 */
/* 0x000fe2000c101b04 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_lshl_b64 s[0:1], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
flat_store_b64 v[0:1], v[2:3]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b64 v[2:3], v[2:3]
flat_load_b64 v[4:5], v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
flat_store_b64 v[0:1], v[2:3]
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIdEEEES9_S9_NS3_14no_stencil_tagENS_10multipliesIdEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Jin Pyo Jeon
// Lab 02
#include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define T 1024 // Shared needs to be known at compile time??
__global__ void calculateDot(int N, int* a, int* b, unsigned long* result){
__shared__ int temp[T];
int lowRange = ceil(N / (T * 1.0)) * threadIdx.x;
int highRange = ceil(N / (T * 1.0)) * (threadIdx.x + 1);
unsigned long sum = 0;
int i = lowRange;
for (; i < highRange; i++) {
sum += a[i] * b[i];
}
temp[threadIdx.x] = sum;
__syncthreads();
if (0 == threadIdx.x) {
unsigned long sum = 0;
for (int i = 0; i < T; i++) {
sum += temp[i];
}
*result = sum;
}
}
void random_ints(int * arr, size_t size){
int i = 0;
for (i = 0; i < size; i++) {
arr[i] = rand() % 2;
}
}
int main(int argc, char**argv) {
unsigned long N;
if (argc >= 2) {
N = strtol(argv[1], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
int *a, *b;
unsigned long *c;
int * d_a, *d_b;
unsigned long *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, sizeof(unsigned long));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (unsigned long *)malloc(sizeof(unsigned long));
random_ints(a, N);
random_ints(b, N);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
calculateDot<<<1, T>>>(N, d_a, d_b, d_c);
cudaMemcpy(c, d_c, sizeof(unsigned long), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("The dot product is %lu with elapsed time of %f s\n", *c, elapsedTime / 1000.0);
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00069755_00000000-6_calculate_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPim
.type _Z11random_intsPim, @function
_Z11random_intsPim:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
.L5:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPim, .-_Z11random_intsPim
.globl _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
.type _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm, @function
_Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calculateDotiPiS_Pm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm, .-_Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
.globl _Z12calculateDotiPiS_Pm
.type _Z12calculateDotiPiS_Pm, @function
_Z12calculateDotiPiS_Pm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12calculateDotiPiS_Pm, .-_Z12calculateDotiPiS_Pm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The dot product is %lu with elapsed time of %f s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L20
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $8, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rsi
movq %r14, %rdi
call _Z11random_intsPim
movq %rbp, %rsi
movq %r13, %rdi
call _Z11random_intsPim
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movq (%r12), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L20:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl %ebp, %edi
call _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z12calculateDotiPiS_Pm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calculateDotiPiS_Pm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Jin Pyo Jeon
// Lab 02
#include <cuda.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define T 1024 // Shared needs to be known at compile time??
__global__ void calculateDot(int N, int* a, int* b, unsigned long* result){
__shared__ int temp[T];
int lowRange = ceil(N / (T * 1.0)) * threadIdx.x;
int highRange = ceil(N / (T * 1.0)) * (threadIdx.x + 1);
unsigned long sum = 0;
int i = lowRange;
for (; i < highRange; i++) {
sum += a[i] * b[i];
}
temp[threadIdx.x] = sum;
__syncthreads();
if (0 == threadIdx.x) {
unsigned long sum = 0;
for (int i = 0; i < T; i++) {
sum += temp[i];
}
*result = sum;
}
}
void random_ints(int * arr, size_t size){
int i = 0;
for (i = 0; i < size; i++) {
arr[i] = rand() % 2;
}
}
int main(int argc, char**argv) {
unsigned long N;
if (argc >= 2) {
N = strtol(argv[1], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
int *a, *b;
unsigned long *c;
int * d_a, *d_b;
unsigned long *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, sizeof(unsigned long));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (unsigned long *)malloc(sizeof(unsigned long));
random_ints(a, N);
random_ints(b, N);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
calculateDot<<<1, T>>>(N, d_a, d_b, d_c);
cudaMemcpy(c, d_c, sizeof(unsigned long), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("The dot product is %lu with elapsed time of %f s\n", *c, elapsedTime / 1000.0);
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | // Jin Pyo Jeon
// Lab 02
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define T 1024 // Shared needs to be known at compile time??
__global__ void calculateDot(int N, int* a, int* b, unsigned long* result){
__shared__ int temp[T];
int lowRange = ceil(N / (T * 1.0)) * threadIdx.x;
int highRange = ceil(N / (T * 1.0)) * (threadIdx.x + 1);
unsigned long sum = 0;
int i = lowRange;
for (; i < highRange; i++) {
sum += a[i] * b[i];
}
temp[threadIdx.x] = sum;
__syncthreads();
if (0 == threadIdx.x) {
unsigned long sum = 0;
for (int i = 0; i < T; i++) {
sum += temp[i];
}
*result = sum;
}
}
void random_ints(int * arr, size_t size){
int i = 0;
for (i = 0; i < size; i++) {
arr[i] = rand() % 2;
}
}
int main(int argc, char**argv) {
unsigned long N;
if (argc >= 2) {
N = strtol(argv[1], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
int *a, *b;
unsigned long *c;
int * d_a, *d_b;
unsigned long *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, sizeof(unsigned long));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (unsigned long *)malloc(sizeof(unsigned long));
random_ints(a, N);
random_ints(b, N);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
calculateDot<<<1, T>>>(N, d_a, d_b, d_c);
hipMemcpy(c, d_c, sizeof(unsigned long), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("The dot product is %lu with elapsed time of %f s\n", *c, elapsedTime / 1000.0);
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Jin Pyo Jeon
// Lab 02
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define T 1024 // Shared needs to be known at compile time??
__global__ void calculateDot(int N, int* a, int* b, unsigned long* result){
__shared__ int temp[T];
int lowRange = ceil(N / (T * 1.0)) * threadIdx.x;
int highRange = ceil(N / (T * 1.0)) * (threadIdx.x + 1);
unsigned long sum = 0;
int i = lowRange;
for (; i < highRange; i++) {
sum += a[i] * b[i];
}
temp[threadIdx.x] = sum;
__syncthreads();
if (0 == threadIdx.x) {
unsigned long sum = 0;
for (int i = 0; i < T; i++) {
sum += temp[i];
}
*result = sum;
}
}
void random_ints(int * arr, size_t size){
int i = 0;
for (i = 0; i < size; i++) {
arr[i] = rand() % 2;
}
}
int main(int argc, char**argv) {
unsigned long N;
if (argc >= 2) {
N = strtol(argv[1], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
int *a, *b;
unsigned long *c;
int * d_a, *d_b;
unsigned long *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, sizeof(unsigned long));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (unsigned long *)malloc(sizeof(unsigned long));
random_ints(a, N);
random_ints(b, N);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
calculateDot<<<1, T>>>(N, d_a, d_b, d_c);
hipMemcpy(c, d_c, sizeof(unsigned long), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("The dot product is %lu with elapsed time of %f s\n", *c, elapsedTime / 1000.0);
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12calculateDotiPiS_Pm
.globl _Z12calculateDotiPiS_Pm
.p2align 8
.type _Z12calculateDotiPiS_Pm,@function
_Z12calculateDotiPiS_Pm:
s_load_b32 s2, s[0:1], 0x0
v_add_nc_u32_e32 v5, 1, v0
v_cvt_f64_u32_e32 v[3:4], v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[5:6], v5
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[1:2], s2
v_ldexp_f64 v[1:2], v[1:2], -10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f64_e32 v[1:2], v[1:2]
v_mul_f64 v[3:4], v[1:2], v[3:4]
v_mul_f64 v[5:6], v[1:2], v[5:6]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f64_e32 v1, v[3:4]
v_cvt_i32_f64_e32 v8, v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v8
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_mov_b32 s4, 0
.p2align 6
.LBB0_2:
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[6:7], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_nc_u32_e32 v1, 1, v1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v8
s_or_b32 s4, vcc_lo, s4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v9, v10, v9
v_add_co_u32 v2, s2, v2, v9
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, 0, v3, s2
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_6:
v_mov_b32_e32 v2, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_cmpk_eq_i32 s2, 0x1000
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_cbranch_scc0 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12calculateDotiPiS_Pm
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12calculateDotiPiS_Pm, .Lfunc_end0-_Z12calculateDotiPiS_Pm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12calculateDotiPiS_Pm
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12calculateDotiPiS_Pm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Jin Pyo Jeon
// Lab 02
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <math.h>
#define T 1024 // Shared needs to be known at compile time??
__global__ void calculateDot(int N, int* a, int* b, unsigned long* result){
__shared__ int temp[T];
int lowRange = ceil(N / (T * 1.0)) * threadIdx.x;
int highRange = ceil(N / (T * 1.0)) * (threadIdx.x + 1);
unsigned long sum = 0;
int i = lowRange;
for (; i < highRange; i++) {
sum += a[i] * b[i];
}
temp[threadIdx.x] = sum;
__syncthreads();
if (0 == threadIdx.x) {
unsigned long sum = 0;
for (int i = 0; i < T; i++) {
sum += temp[i];
}
*result = sum;
}
}
void random_ints(int * arr, size_t size){
int i = 0;
for (i = 0; i < size; i++) {
arr[i] = rand() % 2;
}
}
int main(int argc, char**argv) {
unsigned long N;
if (argc >= 2) {
N = strtol(argv[1], NULL, 10);
} else {
return 0;
}
srand(time(NULL));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
int *a, *b;
unsigned long *c;
int * d_a, *d_b;
unsigned long *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, sizeof(unsigned long));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (unsigned long *)malloc(sizeof(unsigned long));
random_ints(a, N);
random_ints(b, N);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
calculateDot<<<1, T>>>(N, d_a, d_b, d_c);
hipMemcpy(c, d_c, sizeof(unsigned long), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("The dot product is %lu with elapsed time of %f s\n", *c, elapsedTime / 1000.0);
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "calculate_dot.hip"
.globl _Z27__device_stub__calculateDotiPiS_Pm # -- Begin function _Z27__device_stub__calculateDotiPiS_Pm
.p2align 4, 0x90
.type _Z27__device_stub__calculateDotiPiS_Pm,@function
_Z27__device_stub__calculateDotiPiS_Pm: # @_Z27__device_stub__calculateDotiPiS_Pm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12calculateDotiPiS_Pm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__calculateDotiPiS_Pm, .Lfunc_end0-_Z27__device_stub__calculateDotiPiS_Pm
.cfi_endproc
# -- End function
.globl _Z11random_intsPim # -- Begin function _Z11random_intsPim
.p2align 4, 0x90
.type _Z11random_intsPim,@function
_Z11random_intsPim: # @_Z11random_intsPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPim, .Lfunc_end1-_Z11random_intsPim
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
cmpl $2, %edi
jl .LBB2_10
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leal (,%r12,4), %eax
movslq %eax, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movl $8, %edi
callq malloc
movq %rax, %r15
testq %r12, %r12
je .LBB2_7
# %bb.2: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB2_3
# %bb.4: # %_Z11random_intsPim.exit
testq %r12, %r12
je .LBB2_7
# %bb.5: # %.lr.ph.i24.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB2_6
.LBB2_7: # %_Z11random_intsPim.exit28
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r12d, 52(%rsp)
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12calculateDotiPiS_Pm, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 16(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%r15), %rsi
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_10:
xorl %eax, %eax
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12calculateDotiPiS_Pm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12calculateDotiPiS_Pm,@object # @_Z12calculateDotiPiS_Pm
.section .rodata,"a",@progbits
.globl _Z12calculateDotiPiS_Pm
.p2align 3, 0x0
_Z12calculateDotiPiS_Pm:
.quad _Z27__device_stub__calculateDotiPiS_Pm
.size _Z12calculateDotiPiS_Pm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The dot product is %lu with elapsed time of %f s\n"
.size .L.str, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12calculateDotiPiS_Pm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__calculateDotiPiS_Pm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12calculateDotiPiS_Pm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00069755_00000000-6_calculate_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPim
.type _Z11random_intsPim, @function
_Z11random_intsPim:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
.L5:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPim, .-_Z11random_intsPim
.globl _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
.type _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm, @function
_Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calculateDotiPiS_Pm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm, .-_Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
.globl _Z12calculateDotiPiS_Pm
.type _Z12calculateDotiPiS_Pm, @function
_Z12calculateDotiPiS_Pm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12calculateDotiPiS_Pm, .-_Z12calculateDotiPiS_Pm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The dot product is %lu with elapsed time of %f s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L20
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leal 0(,%rbp,4), %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $8, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rsi
movq %r14, %rdi
call _Z11random_intsPim
movq %rbp, %rsi
movq %r13, %rdi
call _Z11random_intsPim
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $8, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movq (%r12), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L20:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl %ebp, %edi
call _Z37__device_stub__Z12calculateDotiPiS_PmiPiS_Pm
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z12calculateDotiPiS_Pm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calculateDotiPiS_Pm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calculate_dot.hip"
.globl _Z27__device_stub__calculateDotiPiS_Pm # -- Begin function _Z27__device_stub__calculateDotiPiS_Pm
.p2align 4, 0x90
.type _Z27__device_stub__calculateDotiPiS_Pm,@function
_Z27__device_stub__calculateDotiPiS_Pm: # @_Z27__device_stub__calculateDotiPiS_Pm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12calculateDotiPiS_Pm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__calculateDotiPiS_Pm, .Lfunc_end0-_Z27__device_stub__calculateDotiPiS_Pm
.cfi_endproc
# -- End function
.globl _Z11random_intsPim # -- Begin function _Z11random_intsPim
.p2align 4, 0x90
.type _Z11random_intsPim,@function
_Z11random_intsPim: # @_Z11random_intsPim
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq %r15, %rbx
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPim, .Lfunc_end1-_Z11random_intsPim
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
cmpl $2, %edi
jl .LBB2_10
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leal (,%r12,4), %eax
movslq %eax, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movl $8, %edi
callq malloc
movq %rax, %r15
testq %r12, %r12
je .LBB2_7
# %bb.2: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB2_3
# %bb.4: # %_Z11random_intsPim.exit
testq %r12, %r12
je .LBB2_7
# %bb.5: # %.lr.ph.i24.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r12
jne .LBB2_6
.LBB2_7: # %_Z11random_intsPim.exit28
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r12d, 52(%rsp)
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12calculateDotiPiS_Pm, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 16(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%r15), %rsi
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_10:
xorl %eax, %eax
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12calculateDotiPiS_Pm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12calculateDotiPiS_Pm,@object # @_Z12calculateDotiPiS_Pm
.section .rodata,"a",@progbits
.globl _Z12calculateDotiPiS_Pm
.p2align 3, 0x0
_Z12calculateDotiPiS_Pm:
.quad _Z27__device_stub__calculateDotiPiS_Pm
.size _Z12calculateDotiPiS_Pm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The dot product is %lu with elapsed time of %f s\n"
.size .L.str, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12calculateDotiPiS_Pm"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__calculateDotiPiS_Pm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12calculateDotiPiS_Pm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void differenceImg(float *d_Octave0,float *d_Octave1,float *d_diffOctave,int pitch,int height){
int x = blockIdx.x*blockDim.x+threadIdx.x;
int y = blockIdx.y*blockDim.y+threadIdx.y;
int index = y * pitch + x;
if(y<height)
d_diffOctave[index] = (d_Octave1[index] - d_Octave0[index]);
} | code for sm_80
Function : _Z13differenceImgPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R3 ; /* 0x0000000002037a24 */
/* 0x001fc800078e0203 */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fc800078e0203 */
/*00c0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0110*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000100 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void differenceImg(float *d_Octave0,float *d_Octave1,float *d_diffOctave,int pitch,int height){
int x = blockIdx.x*blockDim.x+threadIdx.x;
int y = blockIdx.y*blockDim.y+threadIdx.y;
int index = y * pitch + x;
if(y<height)
d_diffOctave[index] = (d_Octave1[index] - d_Octave0[index]);
} | .file "tmpxft_0019d87e_00000000-6_differenceImg.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii
.type _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13differenceImgPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii
.globl _Z13differenceImgPfS_S_ii
.type _Z13differenceImgPfS_S_ii, @function
_Z13differenceImgPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13differenceImgPfS_S_ii, .-_Z13differenceImgPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13differenceImgPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13differenceImgPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void differenceImg(float *d_Octave0,float *d_Octave1,float *d_diffOctave,int pitch,int height){
int x = blockIdx.x*blockDim.x+threadIdx.x;
int y = blockIdx.y*blockDim.y+threadIdx.y;
int index = y * pitch + x;
if(y<height)
d_diffOctave[index] = (d_Octave1[index] - d_Octave0[index]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void differenceImg(float *d_Octave0,float *d_Octave1,float *d_diffOctave,int pitch,int height){
int x = blockIdx.x*blockDim.x+threadIdx.x;
int y = blockIdx.y*blockDim.y+threadIdx.y;
int index = y * pitch + x;
if(y<height)
d_diffOctave[index] = (d_Octave1[index] - d_Octave0[index]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void differenceImg(float *d_Octave0,float *d_Octave1,float *d_diffOctave,int pitch,int height){
int x = blockIdx.x*blockDim.x+threadIdx.x;
int y = blockIdx.y*blockDim.y+threadIdx.y;
int index = y * pitch + x;
if(y<height)
d_diffOctave[index] = (d_Octave1[index] - d_Octave0[index]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13differenceImgPfS_S_ii
.globl _Z13differenceImgPfS_S_ii
.p2align 8
.type _Z13differenceImgPfS_S_ii,@function
_Z13differenceImgPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s2, s[2:3], 0xc
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s4
s_and_b32 s2, s2, 0xffff
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, s14
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13differenceImgPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13differenceImgPfS_S_ii, .Lfunc_end0-_Z13differenceImgPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13differenceImgPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13differenceImgPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void differenceImg(float *d_Octave0,float *d_Octave1,float *d_diffOctave,int pitch,int height){
int x = blockIdx.x*blockDim.x+threadIdx.x;
int y = blockIdx.y*blockDim.y+threadIdx.y;
int index = y * pitch + x;
if(y<height)
d_diffOctave[index] = (d_Octave1[index] - d_Octave0[index]);
} | .text
.file "differenceImg.hip"
.globl _Z28__device_stub__differenceImgPfS_S_ii # -- Begin function _Z28__device_stub__differenceImgPfS_S_ii
.p2align 4, 0x90
.type _Z28__device_stub__differenceImgPfS_S_ii,@function
_Z28__device_stub__differenceImgPfS_S_ii: # @_Z28__device_stub__differenceImgPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13differenceImgPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__differenceImgPfS_S_ii, .Lfunc_end0-_Z28__device_stub__differenceImgPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13differenceImgPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13differenceImgPfS_S_ii,@object # @_Z13differenceImgPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z13differenceImgPfS_S_ii
.p2align 3, 0x0
_Z13differenceImgPfS_S_ii:
.quad _Z28__device_stub__differenceImgPfS_S_ii
.size _Z13differenceImgPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13differenceImgPfS_S_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__differenceImgPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13differenceImgPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13differenceImgPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0030*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*00a0*/ IMAD R3, R2, c[0x0][0x0], R3 ; /* 0x0000000002037a24 */
/* 0x001fc800078e0203 */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fc800078e0203 */
/*00c0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0110*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000100 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13differenceImgPfS_S_ii
.globl _Z13differenceImgPfS_S_ii
.p2align 8
.type _Z13differenceImgPfS_S_ii,@function
_Z13differenceImgPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x1c
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s2, s[2:3], 0xc
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s4
s_and_b32 s2, s2, 0xffff
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s14, s14, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v0, s14
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13differenceImgPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13differenceImgPfS_S_ii, .Lfunc_end0-_Z13differenceImgPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13differenceImgPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13differenceImgPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d87e_00000000-6_differenceImg.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii
.type _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13differenceImgPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii
.globl _Z13differenceImgPfS_S_ii
.type _Z13differenceImgPfS_S_ii, @function
_Z13differenceImgPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13differenceImgPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13differenceImgPfS_S_ii, .-_Z13differenceImgPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13differenceImgPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13differenceImgPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "differenceImg.hip"
.globl _Z28__device_stub__differenceImgPfS_S_ii # -- Begin function _Z28__device_stub__differenceImgPfS_S_ii
.p2align 4, 0x90
.type _Z28__device_stub__differenceImgPfS_S_ii,@function
_Z28__device_stub__differenceImgPfS_S_ii: # @_Z28__device_stub__differenceImgPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13differenceImgPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__differenceImgPfS_S_ii, .Lfunc_end0-_Z28__device_stub__differenceImgPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13differenceImgPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13differenceImgPfS_S_ii,@object # @_Z13differenceImgPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z13differenceImgPfS_S_ii
.p2align 3, 0x0
_Z13differenceImgPfS_S_ii:
.quad _Z28__device_stub__differenceImgPfS_S_ii
.size _Z13differenceImgPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13differenceImgPfS_S_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__differenceImgPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13differenceImgPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <vector>
#include <stdio.h>
#include <iostream>
#include <sstream>
#include <string>
#include <fstream>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#define E_SIZE 100
#define H_SIZE 99
#define BLOCK 1024
//this program will assume a 98x98x98 grid with 2 cells of zero padding for the E fields
//the padded zeros act as PEC boundaries
//The H fields will be 99x99x99 (offset by half cell, inside the PEC boundary)
//This version is a very naive version without matrix versions of the calculations
using namespace std;
__global__ void InitWall(double* ey, double init) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
ey[tid] = init;
}
//calculate ex_{i,j,k} for the next time step
//depends on: ex_{i,j,k} for the current time step, hz of adjacent cells, hy of adj. cells,
//the time step, epsilon, and the cell steps
//ended up using this as the general calculation for all E and H components
__device__ double Calc(double exn, double hzp, double hzn, double hyp, double hyn, double d1, double d2, double perm, double dt) {
double term1, term2;
double t1;
t1 = hzp - hzn;
term1 = t1/d1;
term2 = (hyp - hyn)/d2;
return dt*(term1-term2)/perm+exn;
}
__device__ int E2H(int index) {
int i = index / (E_SIZE*E_SIZE);
index -= (E_SIZE*E_SIZE)*i;
int j = index / E_SIZE;
int k = index - E_SIZE*j;
return i*H_SIZE*H_SIZE+j*H_SIZE+k;
}
__device__ int H2E(int index) {
int i = index / (H_SIZE*H_SIZE);
index -= (H_SIZE*H_SIZE)*i;
int j = index / H_SIZE;
int k = index - H_SIZE*j;
return i*E_SIZE*E_SIZE+j*E_SIZE+k;
}
__global__ void Set_H_X(double* hx, double* ey, double* ez, double mu, int size, double dt) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// don't do anything for any thread ids that are greater
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int y_offset = 100;
old = hx[tid];
int edex = H2E(tid);
t1p = ey[edex+1];
t1n = ey[edex];
t2p = ez[edex+y_offset];
t2n = ez[edex];
hx[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,mu,dt);
}
}
__global__ void Set_H_Y(double* hy, double* ez, double* ex, double mu, int size, double dt) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// don't do anything for any thread ids that are greater
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int x_offset = 10000;
old = hy[tid];
int edex = H2E(tid);
t1p = ez[edex+x_offset];
t1n = ez[edex];
t2p = ex[edex+1];
t2n = ex[edex];
hy[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,mu,dt);
}
}
__global__ void Set_H_Z(double* hz, double* ex, double* ey, double mu, int size, double dt) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// don't do anything for any thread ids that are greater
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int x_offset = 10000;
int y_offset = 100;
old = hz[tid];
int edex = H2E(tid);
t1p = ex[edex+y_offset];
t1n = ex[edex];
t2p = ey[edex+x_offset];
t2n = ey[edex];
hz[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,mu,dt);
}
}
// __global__ void Set_E_X(double* ex, double* hz, double* hy, double eps, int size, double dt) {
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// // respect the border
// int n = 100;
// int n2 = 10000;
// int n3 = 1000000;
// if (tid >= size ||((tid < n2) || (tid > (n3-n2))) || (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))) || ((tid%n == 0) || (tid%n == n-1))){}
// // if ((tid < n2) || (tid > (n3-n2))){}
// // else if (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))){}
// // else if ((tid%n == 0) || (tid%n == n-1)){}
// else {
// // printf("%d\n", tid);
// double old, t1p, t1n, t2p, t2n;
//
// old = ex[tid];
// t1p = hz[tid];
// t1n = hz[tid-H_SIZE];
// t2p = hy[tid];
// t2n = hy[tid-1];
// ex[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
// }
// }
//
// __global__ void Set_E_Y(double* ey, double* hx, double* hz, double eps, int size, double dt) {
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// // respect the border
// // int n = E_SIZE;
// // int n2 = E_SIZE*E_SIZE;
// // int n3 = n2 * E_SIZE;
//
// int n = 100;
// int n2 = 10000;
// int n3 = 1000000;
// if (tid >= size ||((tid < n2) || (tid > (n3-n2))) || (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))) || ((tid%n == 0) || (tid%n == n-1))){}
// //
// // if ((tid < n2) || (tid > (n3-n2))){}
// // else if (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))){}
// // else if ((tid%n == 0) || (tid%n == n-1)){}
// else {
// double old, t1p, t1n, t2p, t2n;
//
// old = ey[tid];
// t1p = hx[tid];
// t1n = hx[tid-1];
// t2p = hz[tid];
// t2n = hz[tid-H_SIZE*H_SIZE];
// ey[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
// }
// }
//
// __global__ void Set_E_Z(double* ez, double* hy, double* hx, double eps, int size, double dt) {
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// // respect the border
// // int n = E_SIZE;
// // int n2 = E_SIZE*E_SIZE;
// // int n3 = n2 * E_SIZE;
//
// int n = 100;
// int n2 = 10000;
// int n3 = 1000000;
// if (tid >= size ||((tid < n2) || (tid > (n3-n2))) || (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))) || ((tid%n == 0) || (tid%n == n-1))){}
// //
// // if ((tid < n2) || (tid > (n3-n2))){}
// // else if (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))){}
// // else if ((tid%n == 0) || (tid%n == n-1)){}
// else {
// double old, t1p, t1n, t2p, t2n;
//
// old = ez[tid];
// t1p = hy[tid];
// t1n = hy[tid-H_SIZE*H_SIZE];
// t2p = hx[tid];
// t2n = hx[tid-H_SIZE];
// ez[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
// }
// }
__global__ void Set_E_X(double* ex, double* hz, double* hy, double eps, int size, double dt, int* inner_indices) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// respect the border
if (tid < size) {
// printf("%d\n", tid);
double old, t1p, t1n, t2p, t2n;
int index = inner_indices[tid];
old = ex[index];
int hdex = E2H(index);
t1p = hz[hdex];
t1n = hz[hdex-99];
t2p = hy[hdex];
t2n = hy[hdex-1];
ex[index] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
}
}
__global__ void Set_E_Y(double* ey, double* hx, double* hz, double eps, int size, double dt, int* inner_indices) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// respect the border
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int index = inner_indices[tid];
int hdex = E2H(index);
old = ey[index];
t1p = hx[hdex];
t1n = hx[hdex-1];
t2p = hz[hdex];
t2n = hz[hdex-99*99];
ey[index] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
}
}
__global__ void Set_E_Z(double* ez, double* hy, double* hx, double eps, int size, double dt, int* inner_indices) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// respect the border
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int index = inner_indices[tid];
int hdex = E2H(index);
old = ez[index];
t1p = hy[hdex];
t1n = hy[hdex-99*99];
t2p = hx[hdex];
t2n = hx[hdex-99];
ez[index] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
}
}
// Used for time keeping independent of the clock
double get_wall_time(){
struct timeval time;
if (gettimeofday(&time,NULL)){
// Handle error
return 0;
}
return (double)time.tv_sec + (double)time.tv_usec * .000001;
}
int nx, ny, nz;
double dx, dy, dz;
double dt;
// double ex[E_SIZE][E_SIZE][E_SIZE] = {0};
// double ey[E_SIZE][E_SIZE][E_SIZE] = {0};
// double ez[E_SIZE][E_SIZE][E_SIZE] = {0};
// double hx[H_SIZE][H_SIZE][H_SIZE] = {0};
// double hy[H_SIZE][H_SIZE][H_SIZE] = {0};
// double hz[H_SIZE][H_SIZE][H_SIZE] = {0};
// enum Field {e_x, e_y, e_z, h_x, h_y, h_z};
// This is source term
// the argument is time value
//
double source(double t) {
double expnum;
expnum = pow(t-5e-7,2.0);
return exp(-1*expnum/1e-15);
};
//use existing procedures for all calculations
//the various calc_enijk procedures are the exact same math, we will just use one
//depends on: desired quantity, Ex array, Ey array, Ez array, Hx array, Hy array,
//Hz array (all of which are pointers), dx, dy, dz, i, j, k
//type values: 0, 1, 2, 3, 4, 5 = ex, ey, ez, hx, hy, hz
// double calc_int(int type, double ex[][ny][nz], double ey[][ny][nz], double ez[][ny][nz],
// double hx[][ny-1][nz-1], double hy[][ny-1][nz-1], double hz[][ny-1][nz-1],
// double dx, double dy, double dz,
// double dt, int i, int j, int k)
//function to calculate the magnitude of a 3-vector
//used to write out results, not part of simulation
double magn(double x, double y, double z) {
// cout << x << ' ' << y << ' ' << z << endl;
double mag;
mag = sqrt(x*x+y*y+z*z);
return mag;
}
// frunction to write out the magnitude of the E-field to a file
int write_to(ofstream& f, double t, int ind, int stride, double* ex, double* ey, double* ez) {
f << t;
int i;
for (i = 0; i < nx; i+=stride) {
int index = ind*100*100+i*100+49; // middle index for 100
f << "\t" << magn(ex[index],ey[index],ez[index]);
}
f << "\t" << ind << "\t" << i << "\t" << 49;
f << endl;
return 0;
}
// primary simulation chunk
int main() {
double eps = 8.85e-12;
double mu = 1.257e-6;
double *ex, *ey, *ez, *hx, *hy, *hz;
int *inner_indices;
int e_size = E_SIZE*E_SIZE*E_SIZE;
int h_size = H_SIZE*H_SIZE*H_SIZE;
int i_size = 98*98*98;
ex = (double *)malloc((e_size)*sizeof(double));
ey = (double *)malloc((e_size)*sizeof(double));
ez = (double *)malloc((e_size)*sizeof(double));
hx = (double *)malloc((h_size)*sizeof(double));
hy = (double *)malloc((h_size)*sizeof(double));
hz = (double *)malloc((h_size)*sizeof(double));
inner_indices = (int *)malloc((i_size)*sizeof(int));
// initialize to zero
for (int i = 0; i < e_size; i++) {
ex[i] = 0.0;
ey[i] = 0.0;
ez[i] = 0.0;
}
for (int i = 0; i < h_size; i++) {
hx[i] = 0.0;
hy[i] = 0.0;
hz[i] = 0.0;
}
// cuda variables
double *d_ex, *d_ey, *d_ez, *d_hx, *d_hy, *d_hz;
int *d_inner;
cudaMalloc((void **)&d_ex, sizeof(double) * (e_size));
cudaMalloc((void **)&d_ey, sizeof(double) * (e_size));
cudaMalloc((void **)&d_ez, sizeof(double) * (e_size));
cudaMalloc((void **)&d_hx, sizeof(double) * (h_size));
cudaMalloc((void **)&d_hy, sizeof(double) * (h_size));
cudaMalloc((void **)&d_hz, sizeof(double) * (h_size));
cudaMalloc((void **)&d_inner, sizeof(int) * (i_size));
cudaMemcpy(d_ex, ex, sizeof(double) * (e_size), cudaMemcpyHostToDevice);
cudaMemcpy(d_ey, ey, sizeof(double) * (e_size), cudaMemcpyHostToDevice);
cudaMemcpy(d_ez, ez, sizeof(double) * (e_size), cudaMemcpyHostToDevice);
cudaMemcpy(d_hx, hx, sizeof(double) * (h_size), cudaMemcpyHostToDevice);
cudaMemcpy(d_hy, hy, sizeof(double) * (h_size), cudaMemcpyHostToDevice);
cudaMemcpy(d_hz, hz, sizeof(double) * (h_size), cudaMemcpyHostToDevice);
nx = E_SIZE;
ny = E_SIZE;
nz = E_SIZE;
dx = 1;
dy = 1;
dz = 1;
dt = 1e-9;
// cout << "middle element is: " << ex[49][49][49] << endl;
//the courant condition for 1 meter is 1.9e-9
//final time be 1e-6 (for 1000 time steps)
double tf = 1e-6;
double t = 0.0;
int a = 0;
ofstream outFiles[11];
stringstream fname;
for (int it = 0; it < 11; it++) {
fname.str("");
fname << "paraOut/output" << it << ".txt";
outFiles[it].open(fname.str());
};
int outind;
ofstream probef;
probef.open("paraOut/test.txt");
ofstream probef2;
probef2.open("paraOut/test_h.txt");
double difference, w_start, w_finish;
w_start = get_wall_time();
int numBlocksH = h_size/BLOCK+1;
int numBlocksI = i_size/BLOCK+1;
dim3 threadsPerBlock(BLOCK, 1); // Max one dimensional block
int count = 0;
for (int i = 1; i < H_SIZE; i++) {
for (int j = 1; j < H_SIZE; j++) {
for (int k = 1; k < H_SIZE; k++) {
inner_indices[count] = i*E_SIZE*E_SIZE+j*E_SIZE+k;
count++;
}
}
}
cudaMemcpy(d_inner, inner_indices, sizeof(int) * (i_size), cudaMemcpyHostToDevice);
while (t<tf) {
cout << "t = " <<t <<endl;
// set the source value for the incoming plane wave at x boundary
double ey_init = source(t);
// InitWall<<<10,1000>>>(d_ey, ey_init);
for (int g = 0; g < ny; g++) {
for (int h = 0; h < nz; h++) {
int index = g*100 + h;
ey[index] = ey_init;
}
}
// Every tenth time step, write out slices of e-field values to a set of files
if (!(a%10)) {
cudaMemcpy(ex, d_ex, sizeof(double) * e_size, cudaMemcpyDeviceToHost);
cudaMemcpy(ez, d_ez, sizeof(double) * e_size, cudaMemcpyDeviceToHost);
cudaMemcpy(hy, d_hy, sizeof(double) * h_size, cudaMemcpyDeviceToHost);
for (int fn = 0; fn < 11; fn++) {
outind = fn*10;
if (outind > 99) {
outind = 99;
}
write_to(outFiles[fn], t, outind, 10, ex, ey, ez);
}
probef << t;
// write to a couple of debug probes placed in the center of the box
for (int y = 45; y < 55; y+=1) {
int ex_index = 49*100*100+49*100+y;
int hy_index = y*99*99+49*99+49;
probef << "\t" << ex[ex_index];
probef2 << "\t" << hy[hy_index];
};
probef << endl;
probef2 << endl;
};
// after wall, might be better to do wall in CUDA
cudaMemcpy(d_ey, ey, sizeof(double) * (e_size), cudaMemcpyHostToDevice);
Set_H_X<<<numBlocksH, threadsPerBlock>>>(d_hx, d_ey, d_ez, mu, h_size, dt);
cudaDeviceSynchronize();
Set_H_Y<<<numBlocksH, threadsPerBlock>>>(d_hy, d_ez, d_ex, mu, h_size, dt);
cudaDeviceSynchronize();
Set_H_Z<<<numBlocksH, threadsPerBlock>>>(d_hz, d_ex, d_ey, mu, h_size, dt);
cudaDeviceSynchronize();
Set_E_X<<<numBlocksI, threadsPerBlock>>>(d_ex, d_hz, d_hy, eps, i_size, dt, d_inner);
cudaDeviceSynchronize();
Set_E_Y<<<numBlocksI, threadsPerBlock>>>(d_ey, d_hx, d_hz, eps, i_size, dt, d_inner);
cudaDeviceSynchronize();
Set_E_Z<<<numBlocksI, threadsPerBlock>>>(d_ez, d_hy, d_hx, eps, i_size, dt, d_inner);
cudaDeviceSynchronize();
// bring back for wall
cudaMemcpy(ey, d_ey, sizeof(double) * e_size, cudaMemcpyDeviceToHost);
t += dt; // time step counter
a += 1; // printing counter
}
w_finish = get_wall_time();
difference = w_finish - w_start;
cout << "Parallel: " << difference << " seconds\n";
probef.flush();
probef.close();
probef2.flush();
probef2.close();
for (int it = 0; it < 11; it++) {
outFiles[it].flush();
outFiles[it].close();
};
return 0;
} | #include <hip/hip_runtime.h>
#include <vector>
#include <stdio.h>
#include <iostream>
#include <sstream>
#include <string>
#include <fstream>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#define E_SIZE 100
#define H_SIZE 99
#define BLOCK 1024
//this program will assume a 98x98x98 grid with 2 cells of zero padding for the E fields
//the padded zeros act as PEC boundaries
//The H fields will be 99x99x99 (offset by half cell, inside the PEC boundary)
//This version is a very naive version without matrix versions of the calculations
using namespace std;
__global__ void InitWall(double* ey, double init) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
ey[tid] = init;
}
//calculate ex_{i,j,k} for the next time step
//depends on: ex_{i,j,k} for the current time step, hz of adjacent cells, hy of adj. cells,
//the time step, epsilon, and the cell steps
//ended up using this as the general calculation for all E and H components
__device__ double Calc(double exn, double hzp, double hzn, double hyp, double hyn, double d1, double d2, double perm, double dt) {
double term1, term2;
double t1;
t1 = hzp - hzn;
term1 = t1/d1;
term2 = (hyp - hyn)/d2;
return dt*(term1-term2)/perm+exn;
}
__device__ int E2H(int index) {
int i = index / (E_SIZE*E_SIZE);
index -= (E_SIZE*E_SIZE)*i;
int j = index / E_SIZE;
int k = index - E_SIZE*j;
return i*H_SIZE*H_SIZE+j*H_SIZE+k;
}
__device__ int H2E(int index) {
int i = index / (H_SIZE*H_SIZE);
index -= (H_SIZE*H_SIZE)*i;
int j = index / H_SIZE;
int k = index - H_SIZE*j;
return i*E_SIZE*E_SIZE+j*E_SIZE+k;
}
__global__ void Set_H_X(double* hx, double* ey, double* ez, double mu, int size, double dt) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// don't do anything for any thread ids that are greater
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int y_offset = 100;
old = hx[tid];
int edex = H2E(tid);
t1p = ey[edex+1];
t1n = ey[edex];
t2p = ez[edex+y_offset];
t2n = ez[edex];
hx[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,mu,dt);
}
}
__global__ void Set_H_Y(double* hy, double* ez, double* ex, double mu, int size, double dt) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// don't do anything for any thread ids that are greater
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int x_offset = 10000;
old = hy[tid];
int edex = H2E(tid);
t1p = ez[edex+x_offset];
t1n = ez[edex];
t2p = ex[edex+1];
t2n = ex[edex];
hy[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,mu,dt);
}
}
__global__ void Set_H_Z(double* hz, double* ex, double* ey, double mu, int size, double dt) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// don't do anything for any thread ids that are greater
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int x_offset = 10000;
int y_offset = 100;
old = hz[tid];
int edex = H2E(tid);
t1p = ex[edex+y_offset];
t1n = ex[edex];
t2p = ey[edex+x_offset];
t2n = ey[edex];
hz[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,mu,dt);
}
}
// __global__ void Set_E_X(double* ex, double* hz, double* hy, double eps, int size, double dt) {
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// // respect the border
// int n = 100;
// int n2 = 10000;
// int n3 = 1000000;
// if (tid >= size ||((tid < n2) || (tid > (n3-n2))) || (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))) || ((tid%n == 0) || (tid%n == n-1))){}
// // if ((tid < n2) || (tid > (n3-n2))){}
// // else if (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))){}
// // else if ((tid%n == 0) || (tid%n == n-1)){}
// else {
// // printf("%d\n", tid);
// double old, t1p, t1n, t2p, t2n;
//
// old = ex[tid];
// t1p = hz[tid];
// t1n = hz[tid-H_SIZE];
// t2p = hy[tid];
// t2n = hy[tid-1];
// ex[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
// }
// }
//
// __global__ void Set_E_Y(double* ey, double* hx, double* hz, double eps, int size, double dt) {
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// // respect the border
// // int n = E_SIZE;
// // int n2 = E_SIZE*E_SIZE;
// // int n3 = n2 * E_SIZE;
//
// int n = 100;
// int n2 = 10000;
// int n3 = 1000000;
// if (tid >= size ||((tid < n2) || (tid > (n3-n2))) || (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))) || ((tid%n == 0) || (tid%n == n-1))){}
// //
// // if ((tid < n2) || (tid > (n3-n2))){}
// // else if (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))){}
// // else if ((tid%n == 0) || (tid%n == n-1)){}
// else {
// double old, t1p, t1n, t2p, t2n;
//
// old = ey[tid];
// t1p = hx[tid];
// t1n = hx[tid-1];
// t2p = hz[tid];
// t2n = hz[tid-H_SIZE*H_SIZE];
// ey[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
// }
// }
//
// __global__ void Set_E_Z(double* ez, double* hy, double* hx, double eps, int size, double dt) {
// int tid = blockIdx.x * blockDim.x + threadIdx.x;
// // respect the border
// // int n = E_SIZE;
// // int n2 = E_SIZE*E_SIZE;
// // int n3 = n2 * E_SIZE;
//
// int n = 100;
// int n2 = 10000;
// int n3 = 1000000;
// if (tid >= size ||((tid < n2) || (tid > (n3-n2))) || (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))) || ((tid%n == 0) || (tid%n == n-1))){}
// //
// // if ((tid < n2) || (tid > (n3-n2))){}
// // else if (((0 < tid%n2) && (tid%n2 < n)) || ((n2-n < tid%n2) && (tid%n2 < n2-1))){}
// // else if ((tid%n == 0) || (tid%n == n-1)){}
// else {
// double old, t1p, t1n, t2p, t2n;
//
// old = ez[tid];
// t1p = hy[tid];
// t1n = hy[tid-H_SIZE*H_SIZE];
// t2p = hx[tid];
// t2n = hx[tid-H_SIZE];
// ez[tid] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
// }
// }
__global__ void Set_E_X(double* ex, double* hz, double* hy, double eps, int size, double dt, int* inner_indices) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// respect the border
if (tid < size) {
// printf("%d\n", tid);
double old, t1p, t1n, t2p, t2n;
int index = inner_indices[tid];
old = ex[index];
int hdex = E2H(index);
t1p = hz[hdex];
t1n = hz[hdex-99];
t2p = hy[hdex];
t2n = hy[hdex-1];
ex[index] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
}
}
__global__ void Set_E_Y(double* ey, double* hx, double* hz, double eps, int size, double dt, int* inner_indices) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// respect the border
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int index = inner_indices[tid];
int hdex = E2H(index);
old = ey[index];
t1p = hx[hdex];
t1n = hx[hdex-1];
t2p = hz[hdex];
t2n = hz[hdex-99*99];
ey[index] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
}
}
__global__ void Set_E_Z(double* ez, double* hy, double* hx, double eps, int size, double dt, int* inner_indices) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// respect the border
if (tid < size) {
double old, t1p, t1n, t2p, t2n;
int index = inner_indices[tid];
int hdex = E2H(index);
old = ez[index];
t1p = hy[hdex];
t1n = hy[hdex-99*99];
t2p = hx[hdex];
t2n = hx[hdex-99];
ez[index] = Calc(old,t1p,t1n,t2p,t2n,1.0,1.0,eps,dt);
}
}
// Used for time keeping independent of the clock
double get_wall_time(){
struct timeval time;
if (gettimeofday(&time,NULL)){
// Handle error
return 0;
}
return (double)time.tv_sec + (double)time.tv_usec * .000001;
}
int nx, ny, nz;
double dx, dy, dz;
double dt;
// double ex[E_SIZE][E_SIZE][E_SIZE] = {0};
// double ey[E_SIZE][E_SIZE][E_SIZE] = {0};
// double ez[E_SIZE][E_SIZE][E_SIZE] = {0};
// double hx[H_SIZE][H_SIZE][H_SIZE] = {0};
// double hy[H_SIZE][H_SIZE][H_SIZE] = {0};
// double hz[H_SIZE][H_SIZE][H_SIZE] = {0};
// enum Field {e_x, e_y, e_z, h_x, h_y, h_z};
// This is source term
// the argument is time value
//
double source(double t) {
double expnum;
expnum = pow(t-5e-7,2.0);
return exp(-1*expnum/1e-15);
};
//use existing procedures for all calculations
//the various calc_enijk procedures are the exact same math, we will just use one
//depends on: desired quantity, Ex array, Ey array, Ez array, Hx array, Hy array,
//Hz array (all of which are pointers), dx, dy, dz, i, j, k
//type values: 0, 1, 2, 3, 4, 5 = ex, ey, ez, hx, hy, hz
// double calc_int(int type, double ex[][ny][nz], double ey[][ny][nz], double ez[][ny][nz],
// double hx[][ny-1][nz-1], double hy[][ny-1][nz-1], double hz[][ny-1][nz-1],
// double dx, double dy, double dz,
// double dt, int i, int j, int k)
//function to calculate the magnitude of a 3-vector
//used to write out results, not part of simulation
double magn(double x, double y, double z) {
// cout << x << ' ' << y << ' ' << z << endl;
double mag;
mag = sqrt(x*x+y*y+z*z);
return mag;
}
// frunction to write out the magnitude of the E-field to a file
int write_to(ofstream& f, double t, int ind, int stride, double* ex, double* ey, double* ez) {
f << t;
int i;
for (i = 0; i < nx; i+=stride) {
int index = ind*100*100+i*100+49; // middle index for 100
f << "\t" << magn(ex[index],ey[index],ez[index]);
}
f << "\t" << ind << "\t" << i << "\t" << 49;
f << endl;
return 0;
}
// primary simulation chunk
int main() {
double eps = 8.85e-12;
double mu = 1.257e-6;
double *ex, *ey, *ez, *hx, *hy, *hz;
int *inner_indices;
int e_size = E_SIZE*E_SIZE*E_SIZE;
int h_size = H_SIZE*H_SIZE*H_SIZE;
int i_size = 98*98*98;
ex = (double *)malloc((e_size)*sizeof(double));
ey = (double *)malloc((e_size)*sizeof(double));
ez = (double *)malloc((e_size)*sizeof(double));
hx = (double *)malloc((h_size)*sizeof(double));
hy = (double *)malloc((h_size)*sizeof(double));
hz = (double *)malloc((h_size)*sizeof(double));
inner_indices = (int *)malloc((i_size)*sizeof(int));
// initialize to zero
for (int i = 0; i < e_size; i++) {
ex[i] = 0.0;
ey[i] = 0.0;
ez[i] = 0.0;
}
for (int i = 0; i < h_size; i++) {
hx[i] = 0.0;
hy[i] = 0.0;
hz[i] = 0.0;
}
// cuda variables
double *d_ex, *d_ey, *d_ez, *d_hx, *d_hy, *d_hz;
int *d_inner;
hipMalloc((void **)&d_ex, sizeof(double) * (e_size));
hipMalloc((void **)&d_ey, sizeof(double) * (e_size));
hipMalloc((void **)&d_ez, sizeof(double) * (e_size));
hipMalloc((void **)&d_hx, sizeof(double) * (h_size));
hipMalloc((void **)&d_hy, sizeof(double) * (h_size));
hipMalloc((void **)&d_hz, sizeof(double) * (h_size));
hipMalloc((void **)&d_inner, sizeof(int) * (i_size));
hipMemcpy(d_ex, ex, sizeof(double) * (e_size), hipMemcpyHostToDevice);
hipMemcpy(d_ey, ey, sizeof(double) * (e_size), hipMemcpyHostToDevice);
hipMemcpy(d_ez, ez, sizeof(double) * (e_size), hipMemcpyHostToDevice);
hipMemcpy(d_hx, hx, sizeof(double) * (h_size), hipMemcpyHostToDevice);
hipMemcpy(d_hy, hy, sizeof(double) * (h_size), hipMemcpyHostToDevice);
hipMemcpy(d_hz, hz, sizeof(double) * (h_size), hipMemcpyHostToDevice);
nx = E_SIZE;
ny = E_SIZE;
nz = E_SIZE;
dx = 1;
dy = 1;
dz = 1;
dt = 1e-9;
// cout << "middle element is: " << ex[49][49][49] << endl;
//the courant condition for 1 meter is 1.9e-9
//final time be 1e-6 (for 1000 time steps)
double tf = 1e-6;
double t = 0.0;
int a = 0;
ofstream outFiles[11];
stringstream fname;
for (int it = 0; it < 11; it++) {
fname.str("");
fname << "paraOut/output" << it << ".txt";
outFiles[it].open(fname.str());
};
int outind;
ofstream probef;
probef.open("paraOut/test.txt");
ofstream probef2;
probef2.open("paraOut/test_h.txt");
double difference, w_start, w_finish;
w_start = get_wall_time();
int numBlocksH = h_size/BLOCK+1;
int numBlocksI = i_size/BLOCK+1;
dim3 threadsPerBlock(BLOCK, 1); // Max one dimensional block
int count = 0;
for (int i = 1; i < H_SIZE; i++) {
for (int j = 1; j < H_SIZE; j++) {
for (int k = 1; k < H_SIZE; k++) {
inner_indices[count] = i*E_SIZE*E_SIZE+j*E_SIZE+k;
count++;
}
}
}
hipMemcpy(d_inner, inner_indices, sizeof(int) * (i_size), hipMemcpyHostToDevice);
while (t<tf) {
cout << "t = " <<t <<endl;
// set the source value for the incoming plane wave at x boundary
double ey_init = source(t);
// InitWall<<<10,1000>>>(d_ey, ey_init);
for (int g = 0; g < ny; g++) {
for (int h = 0; h < nz; h++) {
int index = g*100 + h;
ey[index] = ey_init;
}
}
// Every tenth time step, write out slices of e-field values to a set of files
if (!(a%10)) {
hipMemcpy(ex, d_ex, sizeof(double) * e_size, hipMemcpyDeviceToHost);
hipMemcpy(ez, d_ez, sizeof(double) * e_size, hipMemcpyDeviceToHost);
hipMemcpy(hy, d_hy, sizeof(double) * h_size, hipMemcpyDeviceToHost);
for (int fn = 0; fn < 11; fn++) {
outind = fn*10;
if (outind > 99) {
outind = 99;
}
write_to(outFiles[fn], t, outind, 10, ex, ey, ez);
}
probef << t;
// write to a couple of debug probes placed in the center of the box
for (int y = 45; y < 55; y+=1) {
int ex_index = 49*100*100+49*100+y;
int hy_index = y*99*99+49*99+49;
probef << "\t" << ex[ex_index];
probef2 << "\t" << hy[hy_index];
};
probef << endl;
probef2 << endl;
};
// after wall, might be better to do wall in CUDA
hipMemcpy(d_ey, ey, sizeof(double) * (e_size), hipMemcpyHostToDevice);
Set_H_X<<<numBlocksH, threadsPerBlock>>>(d_hx, d_ey, d_ez, mu, h_size, dt);
hipDeviceSynchronize();
Set_H_Y<<<numBlocksH, threadsPerBlock>>>(d_hy, d_ez, d_ex, mu, h_size, dt);
hipDeviceSynchronize();
Set_H_Z<<<numBlocksH, threadsPerBlock>>>(d_hz, d_ex, d_ey, mu, h_size, dt);
hipDeviceSynchronize();
Set_E_X<<<numBlocksI, threadsPerBlock>>>(d_ex, d_hz, d_hy, eps, i_size, dt, d_inner);
hipDeviceSynchronize();
Set_E_Y<<<numBlocksI, threadsPerBlock>>>(d_ey, d_hx, d_hz, eps, i_size, dt, d_inner);
hipDeviceSynchronize();
Set_E_Z<<<numBlocksI, threadsPerBlock>>>(d_ez, d_hy, d_hx, eps, i_size, dt, d_inner);
hipDeviceSynchronize();
// bring back for wall
hipMemcpy(ey, d_ey, sizeof(double) * e_size, hipMemcpyDeviceToHost);
t += dt; // time step counter
a += 1; // printing counter
}
w_finish = get_wall_time();
difference = w_finish - w_start;
cout << "Parallel: " << difference << " seconds\n";
probef.flush();
probef.close();
probef2.flush();
probef2.close();
for (int it = 0; it < 11; it++) {
outFiles[it].flush();
outFiles[it].close();
};
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c) {
int index = blockIdx.x;
c[index] = a[index] + b[index];
}
#define N 512
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(void) {
int *a, *b, *c; // host copies of a, b, c
int *a_d, *b_d, *c_d; // device copies of a, b, c
int size = N * sizeof(int);
// Alloc space for device copies of a, b, c
cudaMalloc((void **)&a_d, size);
cudaMalloc((void **)&b_d, size);
cudaMalloc((void **)&c_d, size);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
c = (int *)malloc(size);
// Copy inputs to device
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
add<<<N,1>>>(a_d, b_d, c_d);
// Copy result back to host
cudaMemcpy(c, c_d, size, cudaMemcpyDeviceToHost);
// Print results
for(int i=0; i<N; i++)printf("%d) %d + %d = %d\n",i,a[i],b[i],c[i]);
// Cleanup
free(a); free(b); free(c);
cudaFree(a_d); cudaFree(b_d); cudaFree(c_d);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c) {
int index = blockIdx.x;
c[index] = a[index] + b[index];
}
#define N 512
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(void) {
int *a, *b, *c; // host copies of a, b, c
int *a_d, *b_d, *c_d; // device copies of a, b, c
int size = N * sizeof(int);
// Alloc space for device copies of a, b, c
cudaMalloc((void **)&a_d, size);
cudaMalloc((void **)&b_d, size);
cudaMalloc((void **)&c_d, size);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
c = (int *)malloc(size);
// Copy inputs to device
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
add<<<N,1>>>(a_d, b_d, c_d);
// Copy result back to host
cudaMemcpy(c, c_d, size, cudaMemcpyDeviceToHost);
// Print results
for(int i=0; i<N; i++)printf("%d) %d + %d = %d\n",i,a[i],b[i],c[i]);
// Cleanup
free(a); free(b); free(c);
cudaFree(a_d); cudaFree(b_d); cudaFree(c_d);
return 0;
} | .file "tmpxft_001841bc_00000000-6_addvec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d) %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L21:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r9d
movl 0(%rbp,%rbx,4), %r8d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L21
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c) {
int index = blockIdx.x;
c[index] = a[index] + b[index];
}
#define N 512
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(void) {
int *a, *b, *c; // host copies of a, b, c
int *a_d, *b_d, *c_d; // device copies of a, b, c
int size = N * sizeof(int);
// Alloc space for device copies of a, b, c
cudaMalloc((void **)&a_d, size);
cudaMalloc((void **)&b_d, size);
cudaMalloc((void **)&c_d, size);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
c = (int *)malloc(size);
// Copy inputs to device
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
add<<<N,1>>>(a_d, b_d, c_d);
// Copy result back to host
cudaMemcpy(c, c_d, size, cudaMemcpyDeviceToHost);
// Print results
for(int i=0; i<N; i++)printf("%d) %d + %d = %d\n",i,a[i],b[i],c[i]);
// Cleanup
free(a); free(b); free(c);
cudaFree(a_d); cudaFree(b_d); cudaFree(c_d);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c) {
int index = blockIdx.x;
c[index] = a[index] + b[index];
}
#define N 512
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(void) {
int *a, *b, *c; // host copies of a, b, c
int *a_d, *b_d, *c_d; // device copies of a, b, c
int size = N * sizeof(int);
// Alloc space for device copies of a, b, c
hipMalloc((void **)&a_d, size);
hipMalloc((void **)&b_d, size);
hipMalloc((void **)&c_d, size);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
c = (int *)malloc(size);
// Copy inputs to device
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU
add<<<N,1>>>(a_d, b_d, c_d);
// Copy result back to host
hipMemcpy(c, c_d, size, hipMemcpyDeviceToHost);
// Print results
for(int i=0; i<N; i++)printf("%d) %d + %d = %d\n",i,a[i],b[i],c[i]);
// Cleanup
free(a); free(b); free(c);
hipFree(a_d); hipFree(b_d); hipFree(c_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c) {
int index = blockIdx.x;
c[index] = a[index] + b[index];
}
#define N 512
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(void) {
int *a, *b, *c; // host copies of a, b, c
int *a_d, *b_d, *c_d; // device copies of a, b, c
int size = N * sizeof(int);
// Alloc space for device copies of a, b, c
hipMalloc((void **)&a_d, size);
hipMalloc((void **)&b_d, size);
hipMalloc((void **)&c_d, size);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
c = (int *)malloc(size);
// Copy inputs to device
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU
add<<<N,1>>>(a_d, b_d, c_d);
// Copy result back to host
hipMemcpy(c, c_d, size, hipMemcpyDeviceToHost);
// Print results
for(int i=0; i<N; i++)printf("%d) %d + %d = %d\n",i,a[i],b[i],c[i]);
// Cleanup
free(a); free(b); free(c);
hipFree(a_d); hipFree(b_d); hipFree(c_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void add(int *a, int *b, int *c) {
int index = blockIdx.x;
c[index] = a[index] + b[index];
}
#define N 512
void random_ints(int* x, int size)
{
int i;
for (i=0;i<size;i++) {
x[i]=rand()%10;
}
}
int main(void) {
int *a, *b, *c; // host copies of a, b, c
int *a_d, *b_d, *c_d; // device copies of a, b, c
int size = N * sizeof(int);
// Alloc space for device copies of a, b, c
hipMalloc((void **)&a_d, size);
hipMalloc((void **)&b_d, size);
hipMalloc((void **)&c_d, size);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
c = (int *)malloc(size);
// Copy inputs to device
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU
add<<<N,1>>>(a_d, b_d, c_d);
// Copy result back to host
hipMemcpy(c, c_d, size, hipMemcpyDeviceToHost);
// Print results
for(int i=0; i<N; i++)printf("%d) %d + %d = %d\n",i,a[i],b[i],c[i]);
// Cleanup
free(a); free(b); free(c);
hipFree(a_d); hipFree(b_d); hipFree(c_d);
return 0;
} | .text
.file "addvec.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $512, %r14 # imm = 0x200
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit31
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 511(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
movl (%r15,%r12,4), %r8d
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_7
# %bb.8:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d) %d + %d = %d\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001841bc_00000000-6_addvec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d) %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
movl $512, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $2048, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L21:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r9d
movl 0(%rbp,%rbx,4), %r8d
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L21
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addvec.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $512, %r14 # imm = 0x200
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit31
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 511(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %edx
movl (%r14,%r12,4), %ecx
movl (%r15,%r12,4), %r8d
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_7
# %bb.8:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d) %d + %d = %d\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 512
int no_of_nodes;
int edge_list_size;
FILE *fp;
//Structure to hold a node information
struct Node
{
int starting;
int no_of_edges;
};
__global__ void
Kernel3(Node* g_graph_nodes, int* g_graph_edges,int* cd, bool* f1d, bool *f2d,int no_of_nodes,bool *md)
{
int i = blockIdx.x*MAX_THREADS_PER_BLOCK + threadIdx.x;
//int idx, idxi;
//printf("\n Thread id: %d",i);
int ci, cj;
if(f1d[i]==true)
{
f1d[i]=false;
ci=cd[i];
bool cimod=false;
int temp;
for(int j=g_graph_nodes[i].starting;j<(g_graph_nodes[i].starting + g_graph_nodes[i].no_of_edges); j++)
{
temp=g_graph_edges[j];
cj = cd[temp];
if ( ci < cj )
{
atomicMin(&cd[temp],ci);
f2d[temp]=true;
*md=true;
}
else
if (ci>cj)
{
ci=cj;
cimod=true;
}
}
if(cimod==true)
{
atomicMin(&cd[i],ci);
f2d[i]=true;
*md=true;
}
}
// printf("\n End of kernel: %d", cd[i]);
}
long long start_timer();
long long stop_timer(long long start_time, char *name);
void GPLGraph(int argc, char** argv);
////////////////////////////////////////////////////////////////////////////////
// Main Program
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
no_of_nodes=0;
edge_list_size=0;
GPLGraph( argc, argv);
}
void Usage(int argc, char**argv){
fprintf(stderr,"Usage: %s <input_file>\n", argv[0]);
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
void GPLGraph( int argc, char** argv)
{
char *input_f;
if(argc!=2){
Usage(argc, argv);
exit(0);
}
input_f = argv[1];
printf("Reading File\n");
//Read in Graph from a file
fp = fopen(input_f,"r");
if(!fp)
{
printf("Error Reading graph file\n");
return;
}
int source = 0;
fscanf(fp,"%d",&no_of_nodes);
int num_of_blocks = 1;
int num_of_threads_per_block = no_of_nodes;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(no_of_nodes>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(no_of_nodes/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
// allocate host memory
Node* h_graph_nodes = (Node*) malloc(sizeof(Node)*no_of_nodes);
int start, edgeno;
// initalize the memory
for( unsigned int i = 0; i < no_of_nodes; i++)
{
fscanf(fp,"%d %d",&start,&edgeno);
h_graph_nodes[i].starting = start;
h_graph_nodes[i].no_of_edges = edgeno;
}
//read the source node from the file
fscanf(fp,"%d",&source);
source=0;
fscanf(fp,"%d",&edge_list_size);
int id,cost;
int* h_graph_edges = (int*) malloc(sizeof(int)*edge_list_size);
for(unsigned int i=0; i < edge_list_size ; i++)
{
fscanf(fp,"%d",&id);
fscanf(fp,"%d",&cost);
h_graph_edges[i] = id;
}
int* c = (int*) malloc(sizeof(int)*no_of_nodes);
bool* f1 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f2 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f3 = (bool*) malloc(sizeof(bool)*no_of_nodes);
for(unsigned int i=0; i < no_of_nodes ; i++)
{
c[i]=i;
f1[i]=true;
f2[i]=false;
}
if(fp)
fclose(fp);
printf("Read File\n");
//Copy the Node list to device memory
Node* d_graph_nodes;
cudaMalloc( (void**) &d_graph_nodes, sizeof(Node)*no_of_nodes) ;
cudaMemcpy( d_graph_nodes, h_graph_nodes, sizeof(Node)*no_of_nodes, cudaMemcpyHostToDevice) ;
//Copy the Edge List to device Memory
int* d_graph_edges;
cudaMalloc( (void**) &d_graph_edges, sizeof(int)*edge_list_size) ;
cudaMemcpy( d_graph_edges, h_graph_edges, sizeof(int)*edge_list_size, cudaMemcpyHostToDevice) ;
//Allocate Color Array in device Memory
int* cd;
cudaMalloc( (void**) &cd, sizeof(int)*no_of_nodes);
cudaMemcpy( cd, c, sizeof(int)*no_of_nodes,cudaMemcpyHostToDevice);
//Allocate Boolean Array in current Iteration
bool* f1d;
cudaMalloc( (void**) &f1d, sizeof(bool)*no_of_nodes);
cudaMemcpy( f1d, f1, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
//Allocate Boolean Array for next Iteration
bool* f2d;
cudaMalloc( (void**) &f2d, sizeof(bool)*no_of_nodes);
cudaMemcpy( f2d, f2, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
bool* f3d;
cudaMalloc( (void**) &f3d, sizeof(bool)*no_of_nodes);
bool m;
bool *md;
cudaMalloc( (void**) &md, sizeof(bool));
printf("Copied Everything to Kernel");
// setup execution parameters
dim3 grid( num_of_blocks, 1, 1);
dim3 threads( num_of_threads_per_block, 1, 1);
long long timer;
timer = start_timer();
int k=0;
printf("Start traversing the tree\n");
//Call the Kernel untill all the elements of Frontier are not false
do
{
m=false;
//if no thread changes this value then the loop stops
cudaMemcpy( md, &m, sizeof(bool), cudaMemcpyHostToDevice) ;
Kernel3<<< grid, threads, 0 >>>( d_graph_nodes, d_graph_edges,cd,f1d,f2d, no_of_nodes,md);
// check if kernel execution generated and error
cudaMemcpy( f1, f1d, sizeof(bool)*no_of_nodes,cudaMemcpyDeviceToHost);
cudaMemcpy( f2, f2d, sizeof(bool)*no_of_nodes,cudaMemcpyDeviceToHost);
cudaMemcpy( f1d, f2, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
cudaMemcpy( f2d, f1, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
k++;
cudaMemcpy( &m,md , sizeof(bool), cudaMemcpyDeviceToHost) ;
// printf("\n \n Return from kernel: %d",m);
}
while(m);
printf("Kernel Executed %d times\n",k);
// copy result from device to host
cudaMemcpy( c,cd, sizeof(int)*no_of_nodes, cudaMemcpyDeviceToHost) ;
//Store the result into a file
FILE *fpo = fopen("result.txt","w");
for(unsigned int i=0;i<no_of_nodes;i++)
fprintf(fpo,"%d) color:%d\n",i,c[i]);
fclose(fpo);
printf("Result stored in result.txt\n");
// cleanup memory
free( h_graph_nodes);
free( h_graph_edges);
cudaFree(d_graph_nodes);
cudaFree(d_graph_edges);
cudaFree(cd);
cudaFree(f1d);
cudaFree(f2d);
//cudaFree(md);
stop_timer(timer, "Total Processing time");
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *label) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
return end_time - start_time;
} | code for sm_80
Function : _Z7Kernel3P4NodePiS1_PbS2_iS2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R3, R3, 0x200, R0 ; /* 0x0000020003037824 */
/* 0x001fca00078e0200 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fe40000011403 */
/*0060*/ IADD3 R4, P0, R3, c[0x0][0x178], RZ ; /* 0x00005e0003047a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R5, R0, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000057a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1100 */
/*0090*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ LEA R10, P0, R3.reuse, c[0x0][0x160], 0x3 ; /* 0x00005800030a7a11 */
/* 0x040fe200078018ff */
/*00c0*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e6000c101104 */
/*00d0*/ LEA.HI.X R11, R3, c[0x0][0x164], R0, 0x3, P0 ; /* 0x00005900030b7a11 */
/* 0x000fca00000f1c00 */
/*00e0*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004040a0c7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ LEA R8, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003087a11 */
/* 0x000fc800078010ff */
/*0100*/ LEA.HI.X R9, R3, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0003097a11 */
/* 0x000fca00000f1400 */
/*0110*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000162000c1e1900 */
/*0120*/ BSSY B0, 0x3d0 ; /* 0x000002a000007945 */
/* 0x000fe20003800000 */
/*0130*/ PRMT R7, RZ, 0x7610, R7 ; /* 0x00007610ff077816 */
/* 0x000fe40000000007 */
/*0140*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 BRA 0x3c0 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001ea2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0180*/ PRMT R7, RZ, 0x7610, R7 ; /* 0x00007610ff077816 */
/* 0x000fe20000000007 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*01a0*/ IMAD.WIDE R8, R6, R9, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x004fc800078e0209 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0006 */
/*01c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x004fca00078e0205 */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ BSSY B1, 0x350 ; /* 0x0000013000017945 */
/* 0x000fe20003800000 */
/*0220*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.GE.AND P1, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x024fda0003f26270 */
/*0240*/ @P1 ISETP.GT.AND P0, PT, R2.reuse, R11.reuse, PT ; /* 0x0000000b0200120c */
/* 0x0c0fe40003f04270 */
/*0250*/ @P1 IMNMX R2, R2, R11, PT ; /* 0x0000000b02021217 */
/* 0x000fe20003800200 */
/*0260*/ @P1 BRA 0x340 ; /* 0x000000d000001947 */
/* 0x000fea0003800000 */
/*0270*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fe2000001140a */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R10, P2, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a10 */
/* 0x000fe20007f5e0ff */
/*02a0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*02b0*/ RED.E.MIN.S32.STRONG.GPU [R4.64], R2 ; /* 0x000000020400798e */
/* 0x0001e2000c90e384 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fe200078e00ff */
/*02d0*/ IADD3.X R11, R11, c[0x0][0x184], RZ, P2, !PT ; /* 0x000061000b0b7a10 */
/* 0x000fe200017fe4ff */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fc400078e00ff */
/*02f0*/ IMAD.WIDE R14, R3, R14, c[0x0][0x160] ; /* 0x00005800030e7625 */
/* 0x000fe400078e020e */
/*0300*/ STG.E.U8 [R10.64], R18 ; /* 0x000000120a007986 */
/* 0x0001e8000c101104 */
/*0310*/ STG.E.U8 [R12.64], R18 ; /* 0x000000120c007986 */
/* 0x0001e8000c101104 */
/*0320*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R16, [R14.64+0x4] ; /* 0x000004040e107981 */
/* 0x000164000c1e1900 */
/*0340*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0350*/ IMAD.IADD R5, R16, 0x1, R17 ; /* 0x0000000110057824 */
/* 0x021fe200078e0211 */
/*0360*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007f7e0ff */
/*0370*/ @P1 SEL R4, R7, 0x1, !P0 ; /* 0x0000000107041807 */
/* 0x000fe40004000000 */
/*0380*/ ISETP.GE.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fe20003f46270 */
/*0390*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*03a0*/ @P1 PRMT R7, R4, 0x7610, R7 ; /* 0x0000761004071816 */
/* 0x000fd60000000007 */
/*03b0*/ @!P2 BRA 0x1c0 ; /* 0xfffffe000000a947 */
/* 0x000fea000383ffff */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*03d0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc800078ec0ff */
/*03e0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f05270 */
/*03f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0410*/ IADD3 R6, P0, R3.reuse, c[0x0][0x180], RZ ; /* 0x0000600003067a10 */
/* 0x040fe20007f1e0ff */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff087624 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD.WIDE R4, R3, R4, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fe200078e0204 */
/*0440*/ IADD3.X R7, R0, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610000077a10 */
/* 0x000fc600007fe4ff */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0460*/ RED.E.MIN.S32.STRONG.GPU [R4.64], R2 ; /* 0x000000020400798e */
/* 0x020fe2000c90e384 */
/*0470*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff097624 */
/* 0x000fc600078e00ff */
/*0480*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe8000c101104 */
/*0490*/ STG.E.U8 [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101104 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 512
int no_of_nodes;
int edge_list_size;
FILE *fp;
//Structure to hold a node information
struct Node
{
int starting;
int no_of_edges;
};
__global__ void
Kernel3(Node* g_graph_nodes, int* g_graph_edges,int* cd, bool* f1d, bool *f2d,int no_of_nodes,bool *md)
{
int i = blockIdx.x*MAX_THREADS_PER_BLOCK + threadIdx.x;
//int idx, idxi;
//printf("\n Thread id: %d",i);
int ci, cj;
if(f1d[i]==true)
{
f1d[i]=false;
ci=cd[i];
bool cimod=false;
int temp;
for(int j=g_graph_nodes[i].starting;j<(g_graph_nodes[i].starting + g_graph_nodes[i].no_of_edges); j++)
{
temp=g_graph_edges[j];
cj = cd[temp];
if ( ci < cj )
{
atomicMin(&cd[temp],ci);
f2d[temp]=true;
*md=true;
}
else
if (ci>cj)
{
ci=cj;
cimod=true;
}
}
if(cimod==true)
{
atomicMin(&cd[i],ci);
f2d[i]=true;
*md=true;
}
}
// printf("\n End of kernel: %d", cd[i]);
}
long long start_timer();
long long stop_timer(long long start_time, char *name);
void GPLGraph(int argc, char** argv);
////////////////////////////////////////////////////////////////////////////////
// Main Program
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
no_of_nodes=0;
edge_list_size=0;
GPLGraph( argc, argv);
}
void Usage(int argc, char**argv){
fprintf(stderr,"Usage: %s <input_file>\n", argv[0]);
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
void GPLGraph( int argc, char** argv)
{
char *input_f;
if(argc!=2){
Usage(argc, argv);
exit(0);
}
input_f = argv[1];
printf("Reading File\n");
//Read in Graph from a file
fp = fopen(input_f,"r");
if(!fp)
{
printf("Error Reading graph file\n");
return;
}
int source = 0;
fscanf(fp,"%d",&no_of_nodes);
int num_of_blocks = 1;
int num_of_threads_per_block = no_of_nodes;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(no_of_nodes>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(no_of_nodes/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
// allocate host memory
Node* h_graph_nodes = (Node*) malloc(sizeof(Node)*no_of_nodes);
int start, edgeno;
// initalize the memory
for( unsigned int i = 0; i < no_of_nodes; i++)
{
fscanf(fp,"%d %d",&start,&edgeno);
h_graph_nodes[i].starting = start;
h_graph_nodes[i].no_of_edges = edgeno;
}
//read the source node from the file
fscanf(fp,"%d",&source);
source=0;
fscanf(fp,"%d",&edge_list_size);
int id,cost;
int* h_graph_edges = (int*) malloc(sizeof(int)*edge_list_size);
for(unsigned int i=0; i < edge_list_size ; i++)
{
fscanf(fp,"%d",&id);
fscanf(fp,"%d",&cost);
h_graph_edges[i] = id;
}
int* c = (int*) malloc(sizeof(int)*no_of_nodes);
bool* f1 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f2 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f3 = (bool*) malloc(sizeof(bool)*no_of_nodes);
for(unsigned int i=0; i < no_of_nodes ; i++)
{
c[i]=i;
f1[i]=true;
f2[i]=false;
}
if(fp)
fclose(fp);
printf("Read File\n");
//Copy the Node list to device memory
Node* d_graph_nodes;
cudaMalloc( (void**) &d_graph_nodes, sizeof(Node)*no_of_nodes) ;
cudaMemcpy( d_graph_nodes, h_graph_nodes, sizeof(Node)*no_of_nodes, cudaMemcpyHostToDevice) ;
//Copy the Edge List to device Memory
int* d_graph_edges;
cudaMalloc( (void**) &d_graph_edges, sizeof(int)*edge_list_size) ;
cudaMemcpy( d_graph_edges, h_graph_edges, sizeof(int)*edge_list_size, cudaMemcpyHostToDevice) ;
//Allocate Color Array in device Memory
int* cd;
cudaMalloc( (void**) &cd, sizeof(int)*no_of_nodes);
cudaMemcpy( cd, c, sizeof(int)*no_of_nodes,cudaMemcpyHostToDevice);
//Allocate Boolean Array in current Iteration
bool* f1d;
cudaMalloc( (void**) &f1d, sizeof(bool)*no_of_nodes);
cudaMemcpy( f1d, f1, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
//Allocate Boolean Array for next Iteration
bool* f2d;
cudaMalloc( (void**) &f2d, sizeof(bool)*no_of_nodes);
cudaMemcpy( f2d, f2, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
bool* f3d;
cudaMalloc( (void**) &f3d, sizeof(bool)*no_of_nodes);
bool m;
bool *md;
cudaMalloc( (void**) &md, sizeof(bool));
printf("Copied Everything to Kernel");
// setup execution parameters
dim3 grid( num_of_blocks, 1, 1);
dim3 threads( num_of_threads_per_block, 1, 1);
long long timer;
timer = start_timer();
int k=0;
printf("Start traversing the tree\n");
//Call the Kernel untill all the elements of Frontier are not false
do
{
m=false;
//if no thread changes this value then the loop stops
cudaMemcpy( md, &m, sizeof(bool), cudaMemcpyHostToDevice) ;
Kernel3<<< grid, threads, 0 >>>( d_graph_nodes, d_graph_edges,cd,f1d,f2d, no_of_nodes,md);
// check if kernel execution generated and error
cudaMemcpy( f1, f1d, sizeof(bool)*no_of_nodes,cudaMemcpyDeviceToHost);
cudaMemcpy( f2, f2d, sizeof(bool)*no_of_nodes,cudaMemcpyDeviceToHost);
cudaMemcpy( f1d, f2, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
cudaMemcpy( f2d, f1, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
k++;
cudaMemcpy( &m,md , sizeof(bool), cudaMemcpyDeviceToHost) ;
// printf("\n \n Return from kernel: %d",m);
}
while(m);
printf("Kernel Executed %d times\n",k);
// copy result from device to host
cudaMemcpy( c,cd, sizeof(int)*no_of_nodes, cudaMemcpyDeviceToHost) ;
//Store the result into a file
FILE *fpo = fopen("result.txt","w");
for(unsigned int i=0;i<no_of_nodes;i++)
fprintf(fpo,"%d) color:%d\n",i,c[i]);
fclose(fpo);
printf("Result stored in result.txt\n");
// cleanup memory
free( h_graph_nodes);
free( h_graph_edges);
cudaFree(d_graph_nodes);
cudaFree(d_graph_edges);
cudaFree(cd);
cudaFree(f1d);
cudaFree(f2d);
//cudaFree(md);
stop_timer(timer, "Total Processing time");
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *label) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
return end_time - start_time;
} | .file "tmpxft_000811e1_00000000-6_gpl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s <input_file>\n"
.text
.globl _Z5UsageiPPc
.type _Z5UsageiPPc, @function
_Z5UsageiPPc:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5UsageiPPc, .-_Z5UsageiPPc
.globl _Z11start_timerv
.type _Z11start_timerv, @function
_Z11start_timerv:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L8
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z11start_timerv, .-_Z11start_timerv
.section .rodata.str1.1
.LC2:
.string "%s: %.5f sec\n"
.text
.globl _Z10stop_timerxPc
.type _Z10stop_timerxPc, @function
_Z10stop_timerxPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rbx
addq 8(%rsp), %rbx
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
divss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L12
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z10stop_timerxPc, .-_Z10stop_timerxPc
.globl _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
.type _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_, @function
_Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_:
.LFB2086:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7Kernel3P4NodePiS1_PbS2_iS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_, .-_Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
.globl _Z7Kernel3P4NodePiS1_PbS2_iS2_
.type _Z7Kernel3P4NodePiS1_PbS2_iS2_, @function
_Z7Kernel3P4NodePiS1_PbS2_iS2_:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7Kernel3P4NodePiS1_PbS2_iS2_, .-_Z7Kernel3P4NodePiS1_PbS2_iS2_
.section .rodata.str1.1
.LC3:
.string "Reading File\n"
.LC4:
.string "r"
.LC5:
.string "Error Reading graph file\n"
.LC6:
.string "%d"
.LC11:
.string "%d %d"
.LC12:
.string "Read File\n"
.LC13:
.string "Copied Everything to Kernel"
.LC14:
.string "Start traversing the tree\n"
.LC15:
.string "Kernel Executed %d times\n"
.LC16:
.string "w"
.LC17:
.string "result.txt"
.LC18:
.string "%d) color:%d\n"
.LC19:
.string "Result stored in result.txt\n"
.LC20:
.string "Total Processing time"
.text
.globl _Z8GPLGraphiPPc
.type _Z8GPLGraphiPPc, @function
_Z8GPLGraphiPPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L22
call _Z5UsageiPPc
movl $0, %edi
call exit@PLT
.L22:
movq 8(%rsi), %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %rdi
movq %rax, fp(%rip)
testq %rax, %rax
je .L47
movl $0, 20(%rsp)
leaq no_of_nodes(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $0, %eax
call __isoc23_fscanf@PLT
movl no_of_nodes(%rip), %r14d
cmpl $512, %r14d
jle .L25
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC21(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC8(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L26
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC10(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L26:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movslq %r14d, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl $512, %r14d
.L27:
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L29:
leaq 28(%rsp), %rcx
leaq 24(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %eax
movl %eax, (%r12,%rbx,8)
movl 28(%rsp), %eax
movl %eax, 4(%r12,%rbx,8)
addq $1, %rbx
cmpl no_of_nodes(%rip), %ebx
jb .L29
.L28:
leaq 20(%rsp), %rdx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $0, 20(%rsp)
leaq edge_list_size(%rip), %rdx
movq %rbx, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl edge_list_size(%rip), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rsp)
testl %ebx, %ebx
je .L30
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L31:
leaq 32(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 36(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 32(%rsp), %eax
movq (%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
addq $1, %rbx
cmpl edge_list_size(%rip), %ebx
jb .L31
.L30:
movl no_of_nodes(%rip), %r15d
movslq %r15d, %rbx
leaq 0(,%rbx,4), %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
je .L32
movl %r15d, %r15d
movl $0, %eax
.L33:
movl %eax, 0(%r13,%rax,4)
movb $1, 0(%rbp,%rax)
movb $0, (%rbx,%rax)
addq $1, %rax
cmpq %rax, %r15
jne .L33
.L32:
movq fp(%rip), %rdi
testq %rdi, %rdi
je .L34
call fclose@PLT
.L34:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq no_of_nodes(%rip), %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq edge_list_size(%rip), %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movslq edge_list_size(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq (%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %r14d, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
call _Z11start_timerv
movq %rax, 8(%rsp)
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq 19(%rsp), %r15
jmp .L36
.L47:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L25:
movslq %r14d, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl $1, 8(%rsp)
testl %r14d, %r14d
jne .L27
jmp .L28
.L49:
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq 96(%rsp)
.cfi_def_cfa_offset 208
movl no_of_nodes(%rip), %r9d
movq 88(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
addq $16, %rsp
.cfi_def_cfa_offset 192
.L35:
movslq no_of_nodes(%rip), %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rdx
movl $2, %ecx
movq 72(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %r14d
movl $2, %ecx
movl $1, %edx
movq 88(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
cmpb $0, 19(%rsp)
je .L48
.L36:
movb $0, 19(%rsp)
movl $1, %ecx
movl $1, %edx
movq %r15, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
jmp .L49
.L48:
movl %r14d, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq no_of_nodes(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC16(%rip), %rsi
leaq .LC17(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
cmpl $0, no_of_nodes(%rip)
je .L37
movl $0, %ebx
leaq .LC18(%rip), %r14
.L38:
movl 0(%r13,%rbx,4), %r8d
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl no_of_nodes(%rip), %ebx
jb .L38
.L37:
movq %rbp, %rdi
call fclose@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
leaq .LC20(%rip), %rsi
movq 8(%rsp), %rdi
call _Z10stop_timerxPc
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z8GPLGraphiPPc, .-_Z8GPLGraphiPPc
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, no_of_nodes(%rip)
movl $0, edge_list_size(%rip)
call _Z8GPLGraphiPPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC22:
.string "_Z7Kernel3P4NodePiS1_PbS2_iS2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z7Kernel3P4NodePiS1_PbS2_iS2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl fp
.bss
.align 8
.type fp, @object
.size fp, 8
fp:
.zero 8
.globl edge_list_size
.align 4
.type edge_list_size, @object
.size edge_list_size, 4
edge_list_size:
.zero 4
.globl no_of_nodes
.align 4
.type no_of_nodes, @object
.size no_of_nodes, 4
no_of_nodes:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1063256064
.align 8
.LC8:
.long 0
.long 1127219200
.align 8
.LC10:
.long 0
.long 1072693248
.align 8
.LC21:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 512
int no_of_nodes;
int edge_list_size;
FILE *fp;
//Structure to hold a node information
struct Node
{
int starting;
int no_of_edges;
};
__global__ void
Kernel3(Node* g_graph_nodes, int* g_graph_edges,int* cd, bool* f1d, bool *f2d,int no_of_nodes,bool *md)
{
int i = blockIdx.x*MAX_THREADS_PER_BLOCK + threadIdx.x;
//int idx, idxi;
//printf("\n Thread id: %d",i);
int ci, cj;
if(f1d[i]==true)
{
f1d[i]=false;
ci=cd[i];
bool cimod=false;
int temp;
for(int j=g_graph_nodes[i].starting;j<(g_graph_nodes[i].starting + g_graph_nodes[i].no_of_edges); j++)
{
temp=g_graph_edges[j];
cj = cd[temp];
if ( ci < cj )
{
atomicMin(&cd[temp],ci);
f2d[temp]=true;
*md=true;
}
else
if (ci>cj)
{
ci=cj;
cimod=true;
}
}
if(cimod==true)
{
atomicMin(&cd[i],ci);
f2d[i]=true;
*md=true;
}
}
// printf("\n End of kernel: %d", cd[i]);
}
long long start_timer();
long long stop_timer(long long start_time, char *name);
void GPLGraph(int argc, char** argv);
////////////////////////////////////////////////////////////////////////////////
// Main Program
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
no_of_nodes=0;
edge_list_size=0;
GPLGraph( argc, argv);
}
void Usage(int argc, char**argv){
fprintf(stderr,"Usage: %s <input_file>\n", argv[0]);
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
void GPLGraph( int argc, char** argv)
{
char *input_f;
if(argc!=2){
Usage(argc, argv);
exit(0);
}
input_f = argv[1];
printf("Reading File\n");
//Read in Graph from a file
fp = fopen(input_f,"r");
if(!fp)
{
printf("Error Reading graph file\n");
return;
}
int source = 0;
fscanf(fp,"%d",&no_of_nodes);
int num_of_blocks = 1;
int num_of_threads_per_block = no_of_nodes;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(no_of_nodes>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(no_of_nodes/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
// allocate host memory
Node* h_graph_nodes = (Node*) malloc(sizeof(Node)*no_of_nodes);
int start, edgeno;
// initalize the memory
for( unsigned int i = 0; i < no_of_nodes; i++)
{
fscanf(fp,"%d %d",&start,&edgeno);
h_graph_nodes[i].starting = start;
h_graph_nodes[i].no_of_edges = edgeno;
}
//read the source node from the file
fscanf(fp,"%d",&source);
source=0;
fscanf(fp,"%d",&edge_list_size);
int id,cost;
int* h_graph_edges = (int*) malloc(sizeof(int)*edge_list_size);
for(unsigned int i=0; i < edge_list_size ; i++)
{
fscanf(fp,"%d",&id);
fscanf(fp,"%d",&cost);
h_graph_edges[i] = id;
}
int* c = (int*) malloc(sizeof(int)*no_of_nodes);
bool* f1 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f2 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f3 = (bool*) malloc(sizeof(bool)*no_of_nodes);
for(unsigned int i=0; i < no_of_nodes ; i++)
{
c[i]=i;
f1[i]=true;
f2[i]=false;
}
if(fp)
fclose(fp);
printf("Read File\n");
//Copy the Node list to device memory
Node* d_graph_nodes;
cudaMalloc( (void**) &d_graph_nodes, sizeof(Node)*no_of_nodes) ;
cudaMemcpy( d_graph_nodes, h_graph_nodes, sizeof(Node)*no_of_nodes, cudaMemcpyHostToDevice) ;
//Copy the Edge List to device Memory
int* d_graph_edges;
cudaMalloc( (void**) &d_graph_edges, sizeof(int)*edge_list_size) ;
cudaMemcpy( d_graph_edges, h_graph_edges, sizeof(int)*edge_list_size, cudaMemcpyHostToDevice) ;
//Allocate Color Array in device Memory
int* cd;
cudaMalloc( (void**) &cd, sizeof(int)*no_of_nodes);
cudaMemcpy( cd, c, sizeof(int)*no_of_nodes,cudaMemcpyHostToDevice);
//Allocate Boolean Array in current Iteration
bool* f1d;
cudaMalloc( (void**) &f1d, sizeof(bool)*no_of_nodes);
cudaMemcpy( f1d, f1, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
//Allocate Boolean Array for next Iteration
bool* f2d;
cudaMalloc( (void**) &f2d, sizeof(bool)*no_of_nodes);
cudaMemcpy( f2d, f2, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
bool* f3d;
cudaMalloc( (void**) &f3d, sizeof(bool)*no_of_nodes);
bool m;
bool *md;
cudaMalloc( (void**) &md, sizeof(bool));
printf("Copied Everything to Kernel");
// setup execution parameters
dim3 grid( num_of_blocks, 1, 1);
dim3 threads( num_of_threads_per_block, 1, 1);
long long timer;
timer = start_timer();
int k=0;
printf("Start traversing the tree\n");
//Call the Kernel untill all the elements of Frontier are not false
do
{
m=false;
//if no thread changes this value then the loop stops
cudaMemcpy( md, &m, sizeof(bool), cudaMemcpyHostToDevice) ;
Kernel3<<< grid, threads, 0 >>>( d_graph_nodes, d_graph_edges,cd,f1d,f2d, no_of_nodes,md);
// check if kernel execution generated and error
cudaMemcpy( f1, f1d, sizeof(bool)*no_of_nodes,cudaMemcpyDeviceToHost);
cudaMemcpy( f2, f2d, sizeof(bool)*no_of_nodes,cudaMemcpyDeviceToHost);
cudaMemcpy( f1d, f2, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
cudaMemcpy( f2d, f1, sizeof(bool)*no_of_nodes,cudaMemcpyHostToDevice);
k++;
cudaMemcpy( &m,md , sizeof(bool), cudaMemcpyDeviceToHost) ;
// printf("\n \n Return from kernel: %d",m);
}
while(m);
printf("Kernel Executed %d times\n",k);
// copy result from device to host
cudaMemcpy( c,cd, sizeof(int)*no_of_nodes, cudaMemcpyDeviceToHost) ;
//Store the result into a file
FILE *fpo = fopen("result.txt","w");
for(unsigned int i=0;i<no_of_nodes;i++)
fprintf(fpo,"%d) color:%d\n",i,c[i]);
fclose(fpo);
printf("Result stored in result.txt\n");
// cleanup memory
free( h_graph_nodes);
free( h_graph_edges);
cudaFree(d_graph_nodes);
cudaFree(d_graph_edges);
cudaFree(cd);
cudaFree(f1d);
cudaFree(f2d);
//cudaFree(md);
stop_timer(timer, "Total Processing time");
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *label) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
return end_time - start_time;
} | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 512
int no_of_nodes;
int edge_list_size;
FILE *fp;
//Structure to hold a node information
struct Node
{
int starting;
int no_of_edges;
};
__global__ void
Kernel3(Node* g_graph_nodes, int* g_graph_edges,int* cd, bool* f1d, bool *f2d,int no_of_nodes,bool *md)
{
int i = blockIdx.x*MAX_THREADS_PER_BLOCK + threadIdx.x;
//int idx, idxi;
//printf("\n Thread id: %d",i);
int ci, cj;
if(f1d[i]==true)
{
f1d[i]=false;
ci=cd[i];
bool cimod=false;
int temp;
for(int j=g_graph_nodes[i].starting;j<(g_graph_nodes[i].starting + g_graph_nodes[i].no_of_edges); j++)
{
temp=g_graph_edges[j];
cj = cd[temp];
if ( ci < cj )
{
atomicMin(&cd[temp],ci);
f2d[temp]=true;
*md=true;
}
else
if (ci>cj)
{
ci=cj;
cimod=true;
}
}
if(cimod==true)
{
atomicMin(&cd[i],ci);
f2d[i]=true;
*md=true;
}
}
// printf("\n End of kernel: %d", cd[i]);
}
long long start_timer();
long long stop_timer(long long start_time, char *name);
void GPLGraph(int argc, char** argv);
////////////////////////////////////////////////////////////////////////////////
// Main Program
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
no_of_nodes=0;
edge_list_size=0;
GPLGraph( argc, argv);
}
void Usage(int argc, char**argv){
fprintf(stderr,"Usage: %s <input_file>\n", argv[0]);
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
void GPLGraph( int argc, char** argv)
{
char *input_f;
if(argc!=2){
Usage(argc, argv);
exit(0);
}
input_f = argv[1];
printf("Reading File\n");
//Read in Graph from a file
fp = fopen(input_f,"r");
if(!fp)
{
printf("Error Reading graph file\n");
return;
}
int source = 0;
fscanf(fp,"%d",&no_of_nodes);
int num_of_blocks = 1;
int num_of_threads_per_block = no_of_nodes;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(no_of_nodes>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(no_of_nodes/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
// allocate host memory
Node* h_graph_nodes = (Node*) malloc(sizeof(Node)*no_of_nodes);
int start, edgeno;
// initalize the memory
for( unsigned int i = 0; i < no_of_nodes; i++)
{
fscanf(fp,"%d %d",&start,&edgeno);
h_graph_nodes[i].starting = start;
h_graph_nodes[i].no_of_edges = edgeno;
}
//read the source node from the file
fscanf(fp,"%d",&source);
source=0;
fscanf(fp,"%d",&edge_list_size);
int id,cost;
int* h_graph_edges = (int*) malloc(sizeof(int)*edge_list_size);
for(unsigned int i=0; i < edge_list_size ; i++)
{
fscanf(fp,"%d",&id);
fscanf(fp,"%d",&cost);
h_graph_edges[i] = id;
}
int* c = (int*) malloc(sizeof(int)*no_of_nodes);
bool* f1 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f2 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f3 = (bool*) malloc(sizeof(bool)*no_of_nodes);
for(unsigned int i=0; i < no_of_nodes ; i++)
{
c[i]=i;
f1[i]=true;
f2[i]=false;
}
if(fp)
fclose(fp);
printf("Read File\n");
//Copy the Node list to device memory
Node* d_graph_nodes;
hipMalloc( (void**) &d_graph_nodes, sizeof(Node)*no_of_nodes) ;
hipMemcpy( d_graph_nodes, h_graph_nodes, sizeof(Node)*no_of_nodes, hipMemcpyHostToDevice) ;
//Copy the Edge List to device Memory
int* d_graph_edges;
hipMalloc( (void**) &d_graph_edges, sizeof(int)*edge_list_size) ;
hipMemcpy( d_graph_edges, h_graph_edges, sizeof(int)*edge_list_size, hipMemcpyHostToDevice) ;
//Allocate Color Array in device Memory
int* cd;
hipMalloc( (void**) &cd, sizeof(int)*no_of_nodes);
hipMemcpy( cd, c, sizeof(int)*no_of_nodes,hipMemcpyHostToDevice);
//Allocate Boolean Array in current Iteration
bool* f1d;
hipMalloc( (void**) &f1d, sizeof(bool)*no_of_nodes);
hipMemcpy( f1d, f1, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
//Allocate Boolean Array for next Iteration
bool* f2d;
hipMalloc( (void**) &f2d, sizeof(bool)*no_of_nodes);
hipMemcpy( f2d, f2, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
bool* f3d;
hipMalloc( (void**) &f3d, sizeof(bool)*no_of_nodes);
bool m;
bool *md;
hipMalloc( (void**) &md, sizeof(bool));
printf("Copied Everything to Kernel");
// setup execution parameters
dim3 grid( num_of_blocks, 1, 1);
dim3 threads( num_of_threads_per_block, 1, 1);
long long timer;
timer = start_timer();
int k=0;
printf("Start traversing the tree\n");
//Call the Kernel untill all the elements of Frontier are not false
do
{
m=false;
//if no thread changes this value then the loop stops
hipMemcpy( md, &m, sizeof(bool), hipMemcpyHostToDevice) ;
Kernel3<<< grid, threads, 0 >>>( d_graph_nodes, d_graph_edges,cd,f1d,f2d, no_of_nodes,md);
// check if kernel execution generated and error
hipMemcpy( f1, f1d, sizeof(bool)*no_of_nodes,hipMemcpyDeviceToHost);
hipMemcpy( f2, f2d, sizeof(bool)*no_of_nodes,hipMemcpyDeviceToHost);
hipMemcpy( f1d, f2, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
hipMemcpy( f2d, f1, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
k++;
hipMemcpy( &m,md , sizeof(bool), hipMemcpyDeviceToHost) ;
// printf("\n \n Return from kernel: %d",m);
}
while(m);
printf("Kernel Executed %d times\n",k);
// copy result from device to host
hipMemcpy( c,cd, sizeof(int)*no_of_nodes, hipMemcpyDeviceToHost) ;
//Store the result into a file
FILE *fpo = fopen("result.txt","w");
for(unsigned int i=0;i<no_of_nodes;i++)
fprintf(fpo,"%d) color:%d\n",i,c[i]);
fclose(fpo);
printf("Result stored in result.txt\n");
// cleanup memory
free( h_graph_nodes);
free( h_graph_edges);
hipFree(d_graph_nodes);
hipFree(d_graph_edges);
hipFree(cd);
hipFree(f1d);
hipFree(f2d);
//cudaFree(md);
stop_timer(timer, "Total Processing time");
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *label) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
return end_time - start_time;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 512
int no_of_nodes;
int edge_list_size;
FILE *fp;
//Structure to hold a node information
struct Node
{
int starting;
int no_of_edges;
};
__global__ void
Kernel3(Node* g_graph_nodes, int* g_graph_edges,int* cd, bool* f1d, bool *f2d,int no_of_nodes,bool *md)
{
int i = blockIdx.x*MAX_THREADS_PER_BLOCK + threadIdx.x;
//int idx, idxi;
//printf("\n Thread id: %d",i);
int ci, cj;
if(f1d[i]==true)
{
f1d[i]=false;
ci=cd[i];
bool cimod=false;
int temp;
for(int j=g_graph_nodes[i].starting;j<(g_graph_nodes[i].starting + g_graph_nodes[i].no_of_edges); j++)
{
temp=g_graph_edges[j];
cj = cd[temp];
if ( ci < cj )
{
atomicMin(&cd[temp],ci);
f2d[temp]=true;
*md=true;
}
else
if (ci>cj)
{
ci=cj;
cimod=true;
}
}
if(cimod==true)
{
atomicMin(&cd[i],ci);
f2d[i]=true;
*md=true;
}
}
// printf("\n End of kernel: %d", cd[i]);
}
long long start_timer();
long long stop_timer(long long start_time, char *name);
void GPLGraph(int argc, char** argv);
////////////////////////////////////////////////////////////////////////////////
// Main Program
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
no_of_nodes=0;
edge_list_size=0;
GPLGraph( argc, argv);
}
void Usage(int argc, char**argv){
fprintf(stderr,"Usage: %s <input_file>\n", argv[0]);
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
void GPLGraph( int argc, char** argv)
{
char *input_f;
if(argc!=2){
Usage(argc, argv);
exit(0);
}
input_f = argv[1];
printf("Reading File\n");
//Read in Graph from a file
fp = fopen(input_f,"r");
if(!fp)
{
printf("Error Reading graph file\n");
return;
}
int source = 0;
fscanf(fp,"%d",&no_of_nodes);
int num_of_blocks = 1;
int num_of_threads_per_block = no_of_nodes;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(no_of_nodes>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(no_of_nodes/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
// allocate host memory
Node* h_graph_nodes = (Node*) malloc(sizeof(Node)*no_of_nodes);
int start, edgeno;
// initalize the memory
for( unsigned int i = 0; i < no_of_nodes; i++)
{
fscanf(fp,"%d %d",&start,&edgeno);
h_graph_nodes[i].starting = start;
h_graph_nodes[i].no_of_edges = edgeno;
}
//read the source node from the file
fscanf(fp,"%d",&source);
source=0;
fscanf(fp,"%d",&edge_list_size);
int id,cost;
int* h_graph_edges = (int*) malloc(sizeof(int)*edge_list_size);
for(unsigned int i=0; i < edge_list_size ; i++)
{
fscanf(fp,"%d",&id);
fscanf(fp,"%d",&cost);
h_graph_edges[i] = id;
}
int* c = (int*) malloc(sizeof(int)*no_of_nodes);
bool* f1 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f2 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f3 = (bool*) malloc(sizeof(bool)*no_of_nodes);
for(unsigned int i=0; i < no_of_nodes ; i++)
{
c[i]=i;
f1[i]=true;
f2[i]=false;
}
if(fp)
fclose(fp);
printf("Read File\n");
//Copy the Node list to device memory
Node* d_graph_nodes;
hipMalloc( (void**) &d_graph_nodes, sizeof(Node)*no_of_nodes) ;
hipMemcpy( d_graph_nodes, h_graph_nodes, sizeof(Node)*no_of_nodes, hipMemcpyHostToDevice) ;
//Copy the Edge List to device Memory
int* d_graph_edges;
hipMalloc( (void**) &d_graph_edges, sizeof(int)*edge_list_size) ;
hipMemcpy( d_graph_edges, h_graph_edges, sizeof(int)*edge_list_size, hipMemcpyHostToDevice) ;
//Allocate Color Array in device Memory
int* cd;
hipMalloc( (void**) &cd, sizeof(int)*no_of_nodes);
hipMemcpy( cd, c, sizeof(int)*no_of_nodes,hipMemcpyHostToDevice);
//Allocate Boolean Array in current Iteration
bool* f1d;
hipMalloc( (void**) &f1d, sizeof(bool)*no_of_nodes);
hipMemcpy( f1d, f1, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
//Allocate Boolean Array for next Iteration
bool* f2d;
hipMalloc( (void**) &f2d, sizeof(bool)*no_of_nodes);
hipMemcpy( f2d, f2, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
bool* f3d;
hipMalloc( (void**) &f3d, sizeof(bool)*no_of_nodes);
bool m;
bool *md;
hipMalloc( (void**) &md, sizeof(bool));
printf("Copied Everything to Kernel");
// setup execution parameters
dim3 grid( num_of_blocks, 1, 1);
dim3 threads( num_of_threads_per_block, 1, 1);
long long timer;
timer = start_timer();
int k=0;
printf("Start traversing the tree\n");
//Call the Kernel untill all the elements of Frontier are not false
do
{
m=false;
//if no thread changes this value then the loop stops
hipMemcpy( md, &m, sizeof(bool), hipMemcpyHostToDevice) ;
Kernel3<<< grid, threads, 0 >>>( d_graph_nodes, d_graph_edges,cd,f1d,f2d, no_of_nodes,md);
// check if kernel execution generated and error
hipMemcpy( f1, f1d, sizeof(bool)*no_of_nodes,hipMemcpyDeviceToHost);
hipMemcpy( f2, f2d, sizeof(bool)*no_of_nodes,hipMemcpyDeviceToHost);
hipMemcpy( f1d, f2, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
hipMemcpy( f2d, f1, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
k++;
hipMemcpy( &m,md , sizeof(bool), hipMemcpyDeviceToHost) ;
// printf("\n \n Return from kernel: %d",m);
}
while(m);
printf("Kernel Executed %d times\n",k);
// copy result from device to host
hipMemcpy( c,cd, sizeof(int)*no_of_nodes, hipMemcpyDeviceToHost) ;
//Store the result into a file
FILE *fpo = fopen("result.txt","w");
for(unsigned int i=0;i<no_of_nodes;i++)
fprintf(fpo,"%d) color:%d\n",i,c[i]);
fclose(fpo);
printf("Result stored in result.txt\n");
// cleanup memory
free( h_graph_nodes);
free( h_graph_edges);
hipFree(d_graph_nodes);
hipFree(d_graph_edges);
hipFree(cd);
hipFree(f1d);
hipFree(f2d);
//cudaFree(md);
stop_timer(timer, "Total Processing time");
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *label) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
return end_time - start_time;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7Kernel3P4NodePiS1_PbS2_iS2_
.globl _Z7Kernel3P4NodePiS1_PbS2_iS2_
.p2align 8
.type _Z7Kernel3P4NodePiS1_PbS2_iS2_,@function
_Z7Kernel3P4NodePiS1_PbS2_iS2_:
s_load_b64 s[2:3], s[0:1], 0x18
v_lshl_add_u32 v0, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_u8 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v2
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x30
v_mov_b32_e32 v11, 0
s_mov_b32 s11, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v10, v[8:9], off offset:4
global_load_b32 v15, v[2:3], off
global_store_b8 v[4:5], v11, off
s_waitcnt vmcnt(1)
v_cmpx_lt_i32_e32 0, v10
s_cbranch_execz .LBB0_9
v_add_co_u32 v4, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v16, 0
s_mov_b32 s8, 0
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s0, v10
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v11, vcc_lo
s_mov_b32 s0, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_clause 0x1
global_load_b32 v11, v[4:5], off
global_load_b32 v12, v[7:8], off
v_dual_mov_b32 v15, v17 :: v_dual_add_nc_u32 v6, 1, v6
v_add_co_u32 v9, s0, v9, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, v12, v11
v_cmp_ge_i32_e32 vcc_lo, v6, v11
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 s0, s1, exec_lo
s_and_b32 s1, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_mov_b32 s0, s9
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_8
.LBB0_4:
global_load_b32 v11, v[9:10], off
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[11:12]
v_add_co_u32 v13, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v17, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v15, v17
s_xor_b32 s11, exec_lo, s11
v_cmp_gt_i32_e32 vcc_lo, v15, v17
s_or_b32 s9, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s9, s9, exec_lo
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_3
global_atomic_min_i32 v[13:14], v15, off
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_mov_b32_e32 v13, 1
v_mov_b32_e32 v17, v15
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s9, s0
global_store_b8 v[11:12], v13, off
global_store_b8 v16, v13, s[2:3]
s_branch .LBB0_3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v15, v17
s_and_b32 s11, s1, exec_lo
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
global_atomic_min_i32 v[2:3], v15, off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 0
global_store_b8 v[0:1], v2, off
global_store_b8 v3, v2, s[2:3]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7Kernel3P4NodePiS1_PbS2_iS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7Kernel3P4NodePiS1_PbS2_iS2_, .Lfunc_end0-_Z7Kernel3P4NodePiS1_PbS2_iS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7Kernel3P4NodePiS1_PbS2_iS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7Kernel3P4NodePiS1_PbS2_iS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 512
int no_of_nodes;
int edge_list_size;
FILE *fp;
//Structure to hold a node information
struct Node
{
int starting;
int no_of_edges;
};
__global__ void
Kernel3(Node* g_graph_nodes, int* g_graph_edges,int* cd, bool* f1d, bool *f2d,int no_of_nodes,bool *md)
{
int i = blockIdx.x*MAX_THREADS_PER_BLOCK + threadIdx.x;
//int idx, idxi;
//printf("\n Thread id: %d",i);
int ci, cj;
if(f1d[i]==true)
{
f1d[i]=false;
ci=cd[i];
bool cimod=false;
int temp;
for(int j=g_graph_nodes[i].starting;j<(g_graph_nodes[i].starting + g_graph_nodes[i].no_of_edges); j++)
{
temp=g_graph_edges[j];
cj = cd[temp];
if ( ci < cj )
{
atomicMin(&cd[temp],ci);
f2d[temp]=true;
*md=true;
}
else
if (ci>cj)
{
ci=cj;
cimod=true;
}
}
if(cimod==true)
{
atomicMin(&cd[i],ci);
f2d[i]=true;
*md=true;
}
}
// printf("\n End of kernel: %d", cd[i]);
}
long long start_timer();
long long stop_timer(long long start_time, char *name);
void GPLGraph(int argc, char** argv);
////////////////////////////////////////////////////////////////////////////////
// Main Program
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
no_of_nodes=0;
edge_list_size=0;
GPLGraph( argc, argv);
}
void Usage(int argc, char**argv){
fprintf(stderr,"Usage: %s <input_file>\n", argv[0]);
}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
void GPLGraph( int argc, char** argv)
{
char *input_f;
if(argc!=2){
Usage(argc, argv);
exit(0);
}
input_f = argv[1];
printf("Reading File\n");
//Read in Graph from a file
fp = fopen(input_f,"r");
if(!fp)
{
printf("Error Reading graph file\n");
return;
}
int source = 0;
fscanf(fp,"%d",&no_of_nodes);
int num_of_blocks = 1;
int num_of_threads_per_block = no_of_nodes;
//Make execution Parameters according to the number of nodes
//Distribute threads across multiple Blocks if necessary
if(no_of_nodes>MAX_THREADS_PER_BLOCK)
{
num_of_blocks = (int)ceil(no_of_nodes/(double)MAX_THREADS_PER_BLOCK);
num_of_threads_per_block = MAX_THREADS_PER_BLOCK;
}
// allocate host memory
Node* h_graph_nodes = (Node*) malloc(sizeof(Node)*no_of_nodes);
int start, edgeno;
// initalize the memory
for( unsigned int i = 0; i < no_of_nodes; i++)
{
fscanf(fp,"%d %d",&start,&edgeno);
h_graph_nodes[i].starting = start;
h_graph_nodes[i].no_of_edges = edgeno;
}
//read the source node from the file
fscanf(fp,"%d",&source);
source=0;
fscanf(fp,"%d",&edge_list_size);
int id,cost;
int* h_graph_edges = (int*) malloc(sizeof(int)*edge_list_size);
for(unsigned int i=0; i < edge_list_size ; i++)
{
fscanf(fp,"%d",&id);
fscanf(fp,"%d",&cost);
h_graph_edges[i] = id;
}
int* c = (int*) malloc(sizeof(int)*no_of_nodes);
bool* f1 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f2 = (bool*) malloc(sizeof(bool)*no_of_nodes);
bool* f3 = (bool*) malloc(sizeof(bool)*no_of_nodes);
for(unsigned int i=0; i < no_of_nodes ; i++)
{
c[i]=i;
f1[i]=true;
f2[i]=false;
}
if(fp)
fclose(fp);
printf("Read File\n");
//Copy the Node list to device memory
Node* d_graph_nodes;
hipMalloc( (void**) &d_graph_nodes, sizeof(Node)*no_of_nodes) ;
hipMemcpy( d_graph_nodes, h_graph_nodes, sizeof(Node)*no_of_nodes, hipMemcpyHostToDevice) ;
//Copy the Edge List to device Memory
int* d_graph_edges;
hipMalloc( (void**) &d_graph_edges, sizeof(int)*edge_list_size) ;
hipMemcpy( d_graph_edges, h_graph_edges, sizeof(int)*edge_list_size, hipMemcpyHostToDevice) ;
//Allocate Color Array in device Memory
int* cd;
hipMalloc( (void**) &cd, sizeof(int)*no_of_nodes);
hipMemcpy( cd, c, sizeof(int)*no_of_nodes,hipMemcpyHostToDevice);
//Allocate Boolean Array in current Iteration
bool* f1d;
hipMalloc( (void**) &f1d, sizeof(bool)*no_of_nodes);
hipMemcpy( f1d, f1, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
//Allocate Boolean Array for next Iteration
bool* f2d;
hipMalloc( (void**) &f2d, sizeof(bool)*no_of_nodes);
hipMemcpy( f2d, f2, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
bool* f3d;
hipMalloc( (void**) &f3d, sizeof(bool)*no_of_nodes);
bool m;
bool *md;
hipMalloc( (void**) &md, sizeof(bool));
printf("Copied Everything to Kernel");
// setup execution parameters
dim3 grid( num_of_blocks, 1, 1);
dim3 threads( num_of_threads_per_block, 1, 1);
long long timer;
timer = start_timer();
int k=0;
printf("Start traversing the tree\n");
//Call the Kernel untill all the elements of Frontier are not false
do
{
m=false;
//if no thread changes this value then the loop stops
hipMemcpy( md, &m, sizeof(bool), hipMemcpyHostToDevice) ;
Kernel3<<< grid, threads, 0 >>>( d_graph_nodes, d_graph_edges,cd,f1d,f2d, no_of_nodes,md);
// check if kernel execution generated and error
hipMemcpy( f1, f1d, sizeof(bool)*no_of_nodes,hipMemcpyDeviceToHost);
hipMemcpy( f2, f2d, sizeof(bool)*no_of_nodes,hipMemcpyDeviceToHost);
hipMemcpy( f1d, f2, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
hipMemcpy( f2d, f1, sizeof(bool)*no_of_nodes,hipMemcpyHostToDevice);
k++;
hipMemcpy( &m,md , sizeof(bool), hipMemcpyDeviceToHost) ;
// printf("\n \n Return from kernel: %d",m);
}
while(m);
printf("Kernel Executed %d times\n",k);
// copy result from device to host
hipMemcpy( c,cd, sizeof(int)*no_of_nodes, hipMemcpyDeviceToHost) ;
//Store the result into a file
FILE *fpo = fopen("result.txt","w");
for(unsigned int i=0;i<no_of_nodes;i++)
fprintf(fpo,"%d) color:%d\n",i,c[i]);
fclose(fpo);
printf("Result stored in result.txt\n");
// cleanup memory
free( h_graph_nodes);
free( h_graph_edges);
hipFree(d_graph_nodes);
hipFree(d_graph_edges);
hipFree(cd);
hipFree(f1d);
hipFree(f2d);
//cudaFree(md);
stop_timer(timer, "Total Processing time");
}
long long start_timer() {
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec * 1000000 + tv.tv_usec;
}
long long stop_timer(long long start_time, char *label) {
struct timeval tv;
gettimeofday(&tv, NULL);
long long end_time = tv.tv_sec * 1000000 + tv.tv_usec;
printf("%s: %.5f sec\n", label, ((float) (end_time - start_time)) / (1000 * 1000));
return end_time - start_time;
} | .text
.file "gpl.hip"
.globl _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_ # -- Begin function _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.p2align 4, 0x90
.type _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_,@function
_Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_: # @_Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7Kernel3P4NodePiS1_PbS2_iS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_, .Lfunc_end0-_Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, no_of_nodes(%rip)
movl $0, edge_list_size(%rip)
callq _Z8GPLGraphiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8GPLGraphiPPc
.LCPI2_0:
.quad 0x3f60000000000000 # double 0.001953125
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z8GPLGraphiPPc
.p2align 4, 0x90
.type _Z8GPLGraphiPPc,@function
_Z8GPLGraphiPPc: # @_Z8GPLGraphiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_24
# %bb.1:
movq 8(%rsi), %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, fp(%rip)
testq %rax, %rax
je .LBB2_25
# %bb.2:
movabsq $4294967296, %r14 # imm = 0x100000000
movl $0, 28(%rsp)
movl $.L.str.4, %esi
movl $no_of_nodes, %edx
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq no_of_nodes(%rip), %rbx
cmpq $513, %rbx # imm = 0x201
jl .LBB2_3
# %bb.4:
cvtsi2sd %ebx, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
orq %r14, %rax
movq %rax, 104(%rsp) # 8-byte Spill
movl $512, 32(%rsp) # 4-byte Folded Spill
# imm = 0x200
jmp .LBB2_5
.LBB2_25:
movl $.Lstr.1, %edi
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB2_3:
.cfi_def_cfa_offset 352
leaq 1(%r14), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movl %ebx, %eax
movl %ebx, 32(%rsp) # 4-byte Spill
.LBB2_5:
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r12
cmpl $0, no_of_nodes(%rip)
je .LBB2_8
# %bb.6: # %.lr.ph.preheader
leaq 80(%rsp), %rbx
leaq 76(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq fp(%rip), %rdi
movl $.L.str.5, %esi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl 80(%rsp), %eax
movl %eax, (%r12,%r15,8)
movl 76(%rsp), %eax
movl %eax, 4(%r12,%r15,8)
incq %r15
movl no_of_nodes(%rip), %eax
cmpq %rax, %r15
jb .LBB2_7
.LBB2_8: # %._crit_edge
movq %r12, 96(%rsp) # 8-byte Spill
movq fp(%rip), %rdi
leaq 28(%rsp), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq __isoc23_fscanf
movl $0, 28(%rsp)
movq fp(%rip), %rdi
movl $.L.str.4, %esi
movl $edge_list_size, %edx
xorl %eax, %eax
callq __isoc23_fscanf
movslq edge_list_size(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, %r12
testq %rbx, %rbx
je .LBB2_11
# %bb.9: # %.lr.ph77.preheader
leaq 72(%rsp), %rbx
leaq 284(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph77
# =>This Inner Loop Header: Depth=1
movq fp(%rip), %rdi
movl $.L.str.4, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
movl $.L.str.4, %esi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 72(%rsp), %eax
movl %eax, (%r12,%r15,4)
incq %r15
movl edge_list_size(%rip), %eax
cmpq %rax, %r15
jb .LBB2_10
.LBB2_11: # %._crit_edge78
movq %r12, 88(%rsp) # 8-byte Spill
movslq no_of_nodes(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
testq %rbx, %rbx
je .LBB2_14
# %bb.12: # %.lr.ph81.preheader
movl %ebx, %ebx
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
callq memset@PLT
xorl %r14d, %r14d
movq %rbp, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
.p2align 4, 0x90
.LBB2_13: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
movl %r14d, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB2_13
.LBB2_14: # %._crit_edge82
movq fp(%rip), %rdi
testq %rdi, %rdi
je .LBB2_16
# %bb.15:
callq fclose
.LBB2_16:
movl $.Lstr.2, %edi
callq puts@PLT
movslq no_of_nodes(%rip), %rsi
shlq $3, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movq 64(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
shlq $3, %rdx
movq 96(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movslq edge_list_size(%rip), %rsi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movq 56(%rsp), %rdi
movslq edge_list_size(%rip), %rdx
shlq $2, %rdx
movq 88(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movq 40(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
leaq 288(%rsp), %rdi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $1, %esi
callq hipMalloc
xorl %r15d, %r15d
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 32(%rsp), %r14d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 112(%rsp), %rax
movq %rax, 176(%rsp) # 8-byte Spill
movq 120(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl $.Lstr.3, %edi
callq puts@PLT
leaq 7(%rsp), %rbx
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
movq 16(%rsp), %rsi
movslq no_of_nodes(%rip), %rdx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movslq no_of_nodes(%rip), %rdx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
incl %r15d
movq 48(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cmpb $0, 7(%rsp)
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
movb $0, 7(%rsp)
movq 48(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 40(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movl no_of_nodes(%rip), %r8d
movq 48(%rsp), %r9
movq %rax, 272(%rsp)
movq %rcx, 264(%rsp)
movq %rdx, 256(%rsp)
movq %rsi, 248(%rsp)
movq %rdi, 240(%rsp)
movl %r8d, 84(%rsp)
movq %r9, 232(%rsp)
leaq 272(%rsp), %rax
movq %rax, 112(%rsp)
leaq 264(%rsp), %rax
movq %rax, 120(%rsp)
leaq 256(%rsp), %rax
movq %rax, 128(%rsp)
leaq 248(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 152(%rsp)
leaq 232(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rdi
leaq 200(%rsp), %rsi
leaq 192(%rsp), %rdx
leaq 184(%rsp), %rcx
callq __hipPopCallConfiguration
movq 216(%rsp), %rsi
movl 224(%rsp), %edx
movq 200(%rsp), %rcx
movl 208(%rsp), %r8d
movl $_Z7Kernel3P4NodePiS1_PbS2_iS2_, %edi
leaq 112(%rsp), %r9
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_19
.LBB2_20:
movl $.L.str.9, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rsi
movslq no_of_nodes(%rip), %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.10, %edi
movl $.L.str.11, %esi
callq fopen
movq %rax, %rbx
cmpl $0, no_of_nodes(%rip)
je .LBB2_23
# %bb.21: # %.lr.ph85.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_22: # %.lr.ph85
# =>This Inner Loop Header: Depth=1
movl (%r12,%r14,4), %ecx
movl $.L.str.12, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
incq %r14
movl no_of_nodes(%rip), %eax
cmpq %rax, %r14
jb .LBB2_22
.LBB2_23: # %._crit_edge86
movq %rbx, %rdi
callq fclose
movl $.Lstr.4, %edi
callq puts@PLT
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 112(%rsp), %rax
subq 176(%rsp), %rax # 8-byte Folded Reload
movq 120(%rsp), %rcx
subq 32(%rsp), %rcx # 8-byte Folded Reload
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movl $.L.str.14, %esi
movb $1, %al
callq printf
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 352
callq _Z5UsageiPPc
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z8GPLGraphiPPc, .Lfunc_end2-_Z8GPLGraphiPPc
.cfi_endproc
# -- End function
.globl _Z5UsageiPPc # -- Begin function _Z5UsageiPPc
.p2align 4, 0x90
.type _Z5UsageiPPc,@function
_Z5UsageiPPc: # @_Z5UsageiPPc
.cfi_startproc
# %bb.0:
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
jmp fprintf # TAILCALL
.Lfunc_end3:
.size _Z5UsageiPPc, .Lfunc_end3-_Z5UsageiPPc
.cfi_endproc
# -- End function
.globl _Z11start_timerv # -- Begin function _Z11start_timerv
.p2align 4, 0x90
.type _Z11start_timerv,@function
_Z11start_timerv: # @_Z11start_timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 8(%rsp), %rax # imm = 0xF4240
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11start_timerv, .Lfunc_end4-_Z11start_timerv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10stop_timerxPc
.LCPI5_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z10stop_timerxPc
.p2align 4, 0x90
.type _Z10stop_timerxPc,@function
_Z10stop_timerxPc: # @_Z10stop_timerxPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%rsp), %rax # imm = 0xF4240
movq 8(%rsp), %r15
subq %r14, %r15
addq %rax, %r15
cvtsi2ss %r15, %xmm0
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movq %rbx, %rsi
movb $1, %al
callq printf
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z10stop_timerxPc, .Lfunc_end5-_Z10stop_timerxPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7Kernel3P4NodePiS1_PbS2_iS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type no_of_nodes,@object # @no_of_nodes
.bss
.globl no_of_nodes
.p2align 2, 0x0
no_of_nodes:
.long 0 # 0x0
.size no_of_nodes, 4
.type edge_list_size,@object # @edge_list_size
.globl edge_list_size
.p2align 2, 0x0
edge_list_size:
.long 0 # 0x0
.size edge_list_size, 4
.type fp,@object # @fp
.globl fp
.p2align 3, 0x0
fp:
.quad 0
.size fp, 8
.type _Z7Kernel3P4NodePiS1_PbS2_iS2_,@object # @_Z7Kernel3P4NodePiS1_PbS2_iS2_
.section .rodata,"a",@progbits
.globl _Z7Kernel3P4NodePiS1_PbS2_iS2_
.p2align 3, 0x0
_Z7Kernel3P4NodePiS1_PbS2_iS2_:
.quad _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.size _Z7Kernel3P4NodePiS1_PbS2_iS2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s <input_file>\n"
.size .L.str, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d"
.size .L.str.5, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Copied Everything to Kernel"
.size .L.str.7, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Kernel Executed %d times\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "result.txt"
.size .L.str.10, 11
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "w"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d) color:%d\n"
.size .L.str.12, 14
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Total Processing time"
.size .L.str.14, 22
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%s: %.5f sec\n"
.size .L.str.15, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7Kernel3P4NodePiS1_PbS2_iS2_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Reading File"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error Reading graph file"
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Read File"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Start traversing the tree"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Result stored in result.txt"
.size .Lstr.4, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym no_of_nodes
.addrsig_sym edge_list_size
.addrsig_sym _Z7Kernel3P4NodePiS1_PbS2_iS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7Kernel3P4NodePiS1_PbS2_iS2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R3, R3, 0x200, R0 ; /* 0x0000020003037824 */
/* 0x001fca00078e0200 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fe40000011403 */
/*0060*/ IADD3 R4, P0, R3, c[0x0][0x178], RZ ; /* 0x00005e0003047a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R5, R0, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000057a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1100 */
/*0090*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ LEA R10, P0, R3.reuse, c[0x0][0x160], 0x3 ; /* 0x00005800030a7a11 */
/* 0x040fe200078018ff */
/*00c0*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e6000c101104 */
/*00d0*/ LEA.HI.X R11, R3, c[0x0][0x164], R0, 0x3, P0 ; /* 0x00005900030b7a11 */
/* 0x000fca00000f1c00 */
/*00e0*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004040a0c7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ LEA R8, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003087a11 */
/* 0x000fc800078010ff */
/*0100*/ LEA.HI.X R9, R3, c[0x0][0x174], R0, 0x2, P0 ; /* 0x00005d0003097a11 */
/* 0x000fca00000f1400 */
/*0110*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000162000c1e1900 */
/*0120*/ BSSY B0, 0x3d0 ; /* 0x000002a000007945 */
/* 0x000fe20003800000 */
/*0130*/ PRMT R7, RZ, 0x7610, R7 ; /* 0x00007610ff077816 */
/* 0x000fe40000000007 */
/*0140*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 BRA 0x3c0 ; /* 0x0000026000008947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001ea2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0180*/ PRMT R7, RZ, 0x7610, R7 ; /* 0x00007610ff077816 */
/* 0x000fe20000000007 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*01a0*/ IMAD.WIDE R8, R6, R9, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x004fc800078e0209 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0006 */
/*01c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x004fca00078e0205 */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0210*/ BSSY B1, 0x350 ; /* 0x0000013000017945 */
/* 0x000fe20003800000 */
/*0220*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.GE.AND P1, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x024fda0003f26270 */
/*0240*/ @P1 ISETP.GT.AND P0, PT, R2.reuse, R11.reuse, PT ; /* 0x0000000b0200120c */
/* 0x0c0fe40003f04270 */
/*0250*/ @P1 IMNMX R2, R2, R11, PT ; /* 0x0000000b02021217 */
/* 0x000fe20003800200 */
/*0260*/ @P1 BRA 0x340 ; /* 0x000000d000001947 */
/* 0x000fea0003800000 */
/*0270*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fe2000001140a */
/*0280*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R10, P2, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a10 */
/* 0x000fe20007f5e0ff */
/*02a0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*02b0*/ RED.E.MIN.S32.STRONG.GPU [R4.64], R2 ; /* 0x000000020400798e */
/* 0x0001e2000c90e384 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fe200078e00ff */
/*02d0*/ IADD3.X R11, R11, c[0x0][0x184], RZ, P2, !PT ; /* 0x000061000b0b7a10 */
/* 0x000fe200017fe4ff */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fc400078e00ff */
/*02f0*/ IMAD.WIDE R14, R3, R14, c[0x0][0x160] ; /* 0x00005800030e7625 */
/* 0x000fe400078e020e */
/*0300*/ STG.E.U8 [R10.64], R18 ; /* 0x000000120a007986 */
/* 0x0001e8000c101104 */
/*0310*/ STG.E.U8 [R12.64], R18 ; /* 0x000000120c007986 */
/* 0x0001e8000c101104 */
/*0320*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R16, [R14.64+0x4] ; /* 0x000004040e107981 */
/* 0x000164000c1e1900 */
/*0340*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0350*/ IMAD.IADD R5, R16, 0x1, R17 ; /* 0x0000000110057824 */
/* 0x021fe200078e0211 */
/*0360*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007f7e0ff */
/*0370*/ @P1 SEL R4, R7, 0x1, !P0 ; /* 0x0000000107041807 */
/* 0x000fe40004000000 */
/*0380*/ ISETP.GE.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fe20003f46270 */
/*0390*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*03a0*/ @P1 PRMT R7, R4, 0x7610, R7 ; /* 0x0000761004071816 */
/* 0x000fd60000000007 */
/*03b0*/ @!P2 BRA 0x1c0 ; /* 0xfffffe000000a947 */
/* 0x000fea000383ffff */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*03d0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc800078ec0ff */
/*03e0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f05270 */
/*03f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0410*/ IADD3 R6, P0, R3.reuse, c[0x0][0x180], RZ ; /* 0x0000600003067a10 */
/* 0x040fe20007f1e0ff */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff087624 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD.WIDE R4, R3, R4, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fe200078e0204 */
/*0440*/ IADD3.X R7, R0, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610000077a10 */
/* 0x000fc600007fe4ff */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0460*/ RED.E.MIN.S32.STRONG.GPU [R4.64], R2 ; /* 0x000000020400798e */
/* 0x020fe2000c90e384 */
/*0470*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff097624 */
/* 0x000fc600078e00ff */
/*0480*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe8000c101104 */
/*0490*/ STG.E.U8 [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101104 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7Kernel3P4NodePiS1_PbS2_iS2_
.globl _Z7Kernel3P4NodePiS1_PbS2_iS2_
.p2align 8
.type _Z7Kernel3P4NodePiS1_PbS2_iS2_,@function
_Z7Kernel3P4NodePiS1_PbS2_iS2_:
s_load_b64 s[2:3], s[0:1], 0x18
v_lshl_add_u32 v0, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_u8 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v2
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x30
v_mov_b32_e32 v11, 0
s_mov_b32 s11, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v10, v[8:9], off offset:4
global_load_b32 v15, v[2:3], off
global_store_b8 v[4:5], v11, off
s_waitcnt vmcnt(1)
v_cmpx_lt_i32_e32 0, v10
s_cbranch_execz .LBB0_9
v_add_co_u32 v4, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v7, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v16, 0
s_mov_b32 s8, 0
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s0, v10
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v11, vcc_lo
s_mov_b32 s0, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s11
s_clause 0x1
global_load_b32 v11, v[4:5], off
global_load_b32 v12, v[7:8], off
v_dual_mov_b32 v15, v17 :: v_dual_add_nc_u32 v6, 1, v6
v_add_co_u32 v9, s0, v9, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, v12, v11
v_cmp_ge_i32_e32 vcc_lo, v6, v11
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 s0, s1, exec_lo
s_and_b32 s1, s9, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_mov_b32 s0, s9
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_8
.LBB0_4:
global_load_b32 v11, v[9:10], off
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[11:12]
v_add_co_u32 v13, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v17, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_ge_i32_e64 v15, v17
s_xor_b32 s11, exec_lo, s11
v_cmp_gt_i32_e32 vcc_lo, v15, v17
s_or_b32 s9, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s9, s9, exec_lo
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB0_3
global_atomic_min_i32 v[13:14], v15, off
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_mov_b32_e32 v13, 1
v_mov_b32_e32 v17, v15
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s9, s9, s0
global_store_b8 v[11:12], v13, off
global_store_b8 v16, v13, s[2:3]
s_branch .LBB0_3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v15, v17
s_and_b32 s11, s1, exec_lo
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
global_atomic_min_i32 v[2:3], v15, off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_dual_mov_b32 v2, 1 :: v_dual_mov_b32 v3, 0
global_store_b8 v[0:1], v2, off
global_store_b8 v3, v2, s[2:3]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7Kernel3P4NodePiS1_PbS2_iS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7Kernel3P4NodePiS1_PbS2_iS2_, .Lfunc_end0-_Z7Kernel3P4NodePiS1_PbS2_iS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7Kernel3P4NodePiS1_PbS2_iS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7Kernel3P4NodePiS1_PbS2_iS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000811e1_00000000-6_gpl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s <input_file>\n"
.text
.globl _Z5UsageiPPc
.type _Z5UsageiPPc, @function
_Z5UsageiPPc:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5UsageiPPc, .-_Z5UsageiPPc
.globl _Z11start_timerv
.type _Z11start_timerv, @function
_Z11start_timerv:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L8
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z11start_timerv, .-_Z11start_timerv
.section .rodata.str1.1
.LC2:
.string "%s: %.5f sec\n"
.text
.globl _Z10stop_timerxPc
.type _Z10stop_timerxPc, @function
_Z10stop_timerxPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000000, (%rsp), %rbx
addq 8(%rsp), %rbx
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
divss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L12
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z10stop_timerxPc, .-_Z10stop_timerxPc
.globl _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
.type _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_, @function
_Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_:
.LFB2086:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7Kernel3P4NodePiS1_PbS2_iS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_, .-_Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
.globl _Z7Kernel3P4NodePiS1_PbS2_iS2_
.type _Z7Kernel3P4NodePiS1_PbS2_iS2_, @function
_Z7Kernel3P4NodePiS1_PbS2_iS2_:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7Kernel3P4NodePiS1_PbS2_iS2_, .-_Z7Kernel3P4NodePiS1_PbS2_iS2_
.section .rodata.str1.1
.LC3:
.string "Reading File\n"
.LC4:
.string "r"
.LC5:
.string "Error Reading graph file\n"
.LC6:
.string "%d"
.LC11:
.string "%d %d"
.LC12:
.string "Read File\n"
.LC13:
.string "Copied Everything to Kernel"
.LC14:
.string "Start traversing the tree\n"
.LC15:
.string "Kernel Executed %d times\n"
.LC16:
.string "w"
.LC17:
.string "result.txt"
.LC18:
.string "%d) color:%d\n"
.LC19:
.string "Result stored in result.txt\n"
.LC20:
.string "Total Processing time"
.text
.globl _Z8GPLGraphiPPc
.type _Z8GPLGraphiPPc, @function
_Z8GPLGraphiPPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L22
call _Z5UsageiPPc
movl $0, %edi
call exit@PLT
.L22:
movq 8(%rsi), %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %rdi
movq %rax, fp(%rip)
testq %rax, %rax
je .L47
movl $0, 20(%rsp)
leaq no_of_nodes(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $0, %eax
call __isoc23_fscanf@PLT
movl no_of_nodes(%rip), %r14d
cmpl $512, %r14d
jle .L25
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC7(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC21(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC8(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L26
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC10(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L26:
cvttsd2sil %xmm3, %eax
movl %eax, 8(%rsp)
movslq %r14d, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl $512, %r14d
.L27:
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L29:
leaq 28(%rsp), %rcx
leaq 24(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %eax
movl %eax, (%r12,%rbx,8)
movl 28(%rsp), %eax
movl %eax, 4(%r12,%rbx,8)
addq $1, %rbx
cmpl no_of_nodes(%rip), %ebx
jb .L29
.L28:
leaq 20(%rsp), %rdx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $0, 20(%rsp)
leaq edge_list_size(%rip), %rdx
movq %rbx, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl edge_list_size(%rip), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rsp)
testl %ebx, %ebx
je .L30
movl $0, %ebx
leaq .LC6(%rip), %rbp
.L31:
leaq 32(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq 36(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 32(%rsp), %eax
movq (%rsp), %rcx
movl %eax, (%rcx,%rbx,4)
addq $1, %rbx
cmpl edge_list_size(%rip), %ebx
jb .L31
.L30:
movl no_of_nodes(%rip), %r15d
movslq %r15d, %rbx
leaq 0(,%rbx,4), %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r15d, %r15d
je .L32
movl %r15d, %r15d
movl $0, %eax
.L33:
movl %eax, 0(%r13,%rax,4)
movb $1, 0(%rbp,%rax)
movb $0, (%rbx,%rax)
addq $1, %rax
cmpq %rax, %r15
jne .L33
.L32:
movq fp(%rip), %rdi
testq %rdi, %rdi
je .L34
call fclose@PLT
.L34:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq no_of_nodes(%rip), %rsi
salq $3, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq edge_list_size(%rip), %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movslq edge_list_size(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq (%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %r14d, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
call _Z11start_timerv
movq %rax, 8(%rsp)
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq 19(%rsp), %r15
jmp .L36
.L47:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L25:
movslq %r14d, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl $1, 8(%rsp)
testl %r14d, %r14d
jne .L27
jmp .L28
.L49:
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq 96(%rsp)
.cfi_def_cfa_offset 208
movl no_of_nodes(%rip), %r9d
movq 88(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z44__device_stub__Z7Kernel3P4NodePiS1_PbS2_iS2_P4NodePiS1_PbS2_iS2_
addq $16, %rsp
.cfi_def_cfa_offset 192
.L35:
movslq no_of_nodes(%rip), %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rdx
movl $2, %ecx
movq 72(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq no_of_nodes(%rip), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %r14d
movl $2, %ecx
movl $1, %edx
movq 88(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
cmpb $0, 19(%rsp)
je .L48
.L36:
movb $0, 19(%rsp)
movl $1, %ecx
movl $1, %edx
movq %r15, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl 116(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
jmp .L49
.L48:
movl %r14d, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq no_of_nodes(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC16(%rip), %rsi
leaq .LC17(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
cmpl $0, no_of_nodes(%rip)
je .L37
movl $0, %ebx
leaq .LC18(%rip), %r14
.L38:
movl 0(%r13,%rbx,4), %r8d
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl no_of_nodes(%rip), %ebx
jb .L38
.L37:
movq %rbp, %rdi
call fclose@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
leaq .LC20(%rip), %rsi
movq 8(%rsp), %rdi
call _Z10stop_timerxPc
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z8GPLGraphiPPc, .-_Z8GPLGraphiPPc
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, no_of_nodes(%rip)
movl $0, edge_list_size(%rip)
call _Z8GPLGraphiPPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC22:
.string "_Z7Kernel3P4NodePiS1_PbS2_iS2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z7Kernel3P4NodePiS1_PbS2_iS2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl fp
.bss
.align 8
.type fp, @object
.size fp, 8
fp:
.zero 8
.globl edge_list_size
.align 4
.type edge_list_size, @object
.size edge_list_size, 4
edge_list_size:
.zero 4
.globl no_of_nodes
.align 4
.type no_of_nodes, @object
.size no_of_nodes, 4
no_of_nodes:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1232348160
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1063256064
.align 8
.LC8:
.long 0
.long 1127219200
.align 8
.LC10:
.long 0
.long 1072693248
.align 8
.LC21:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpl.hip"
.globl _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_ # -- Begin function _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.p2align 4, 0x90
.type _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_,@function
_Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_: # @_Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7Kernel3P4NodePiS1_PbS2_iS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_, .Lfunc_end0-_Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, no_of_nodes(%rip)
movl $0, edge_list_size(%rip)
callq _Z8GPLGraphiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8GPLGraphiPPc
.LCPI2_0:
.quad 0x3f60000000000000 # double 0.001953125
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z8GPLGraphiPPc
.p2align 4, 0x90
.type _Z8GPLGraphiPPc,@function
_Z8GPLGraphiPPc: # @_Z8GPLGraphiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_24
# %bb.1:
movq 8(%rsi), %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, fp(%rip)
testq %rax, %rax
je .LBB2_25
# %bb.2:
movabsq $4294967296, %r14 # imm = 0x100000000
movl $0, 28(%rsp)
movl $.L.str.4, %esi
movl $no_of_nodes, %edx
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq no_of_nodes(%rip), %rbx
cmpq $513, %rbx # imm = 0x201
jl .LBB2_3
# %bb.4:
cvtsi2sd %ebx, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
orq %r14, %rax
movq %rax, 104(%rsp) # 8-byte Spill
movl $512, 32(%rsp) # 4-byte Folded Spill
# imm = 0x200
jmp .LBB2_5
.LBB2_25:
movl $.Lstr.1, %edi
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB2_3:
.cfi_def_cfa_offset 352
leaq 1(%r14), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movl %ebx, %eax
movl %ebx, 32(%rsp) # 4-byte Spill
.LBB2_5:
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r12
cmpl $0, no_of_nodes(%rip)
je .LBB2_8
# %bb.6: # %.lr.ph.preheader
leaq 80(%rsp), %rbx
leaq 76(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq fp(%rip), %rdi
movl $.L.str.5, %esi
movq %rbx, %rdx
movq %r14, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl 80(%rsp), %eax
movl %eax, (%r12,%r15,8)
movl 76(%rsp), %eax
movl %eax, 4(%r12,%r15,8)
incq %r15
movl no_of_nodes(%rip), %eax
cmpq %rax, %r15
jb .LBB2_7
.LBB2_8: # %._crit_edge
movq %r12, 96(%rsp) # 8-byte Spill
movq fp(%rip), %rdi
leaq 28(%rsp), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq __isoc23_fscanf
movl $0, 28(%rsp)
movq fp(%rip), %rdi
movl $.L.str.4, %esi
movl $edge_list_size, %edx
xorl %eax, %eax
callq __isoc23_fscanf
movslq edge_list_size(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, %r12
testq %rbx, %rbx
je .LBB2_11
# %bb.9: # %.lr.ph77.preheader
leaq 72(%rsp), %rbx
leaq 284(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_10: # %.lr.ph77
# =>This Inner Loop Header: Depth=1
movq fp(%rip), %rdi
movl $.L.str.4, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
movl $.L.str.4, %esi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 72(%rsp), %eax
movl %eax, (%r12,%r15,4)
incq %r15
movl edge_list_size(%rip), %eax
cmpq %rax, %r15
jb .LBB2_10
.LBB2_11: # %._crit_edge78
movq %r12, 88(%rsp) # 8-byte Spill
movslq no_of_nodes(%rip), %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
testq %rbx, %rbx
je .LBB2_14
# %bb.12: # %.lr.ph81.preheader
movl %ebx, %ebx
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
callq memset@PLT
xorl %r14d, %r14d
movq %rbp, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
.p2align 4, 0x90
.LBB2_13: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
movl %r14d, (%r12,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB2_13
.LBB2_14: # %._crit_edge82
movq fp(%rip), %rdi
testq %rdi, %rdi
je .LBB2_16
# %bb.15:
callq fclose
.LBB2_16:
movl $.Lstr.2, %edi
callq puts@PLT
movslq no_of_nodes(%rip), %rsi
shlq $3, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movq 64(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
shlq $3, %rdx
movq 96(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movslq edge_list_size(%rip), %rsi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movq 56(%rsp), %rdi
movslq edge_list_size(%rip), %rdx
shlq $2, %rdx
movq 88(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movq 40(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movslq no_of_nodes(%rip), %rsi
leaq 288(%rsp), %rdi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $1, %esi
callq hipMalloc
xorl %r15d, %r15d
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 32(%rsp), %r14d # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 112(%rsp), %rax
movq %rax, 176(%rsp) # 8-byte Spill
movq 120(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl $.Lstr.3, %edi
callq puts@PLT
leaq 7(%rsp), %rbx
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
movq 16(%rsp), %rsi
movslq no_of_nodes(%rip), %rdx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movslq no_of_nodes(%rip), %rdx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movslq no_of_nodes(%rip), %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
incl %r15d
movq 48(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cmpb $0, 7(%rsp)
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
movb $0, 7(%rsp)
movq 48(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 40(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movl no_of_nodes(%rip), %r8d
movq 48(%rsp), %r9
movq %rax, 272(%rsp)
movq %rcx, 264(%rsp)
movq %rdx, 256(%rsp)
movq %rsi, 248(%rsp)
movq %rdi, 240(%rsp)
movl %r8d, 84(%rsp)
movq %r9, 232(%rsp)
leaq 272(%rsp), %rax
movq %rax, 112(%rsp)
leaq 264(%rsp), %rax
movq %rax, 120(%rsp)
leaq 256(%rsp), %rax
movq %rax, 128(%rsp)
leaq 248(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 152(%rsp)
leaq 232(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rdi
leaq 200(%rsp), %rsi
leaq 192(%rsp), %rdx
leaq 184(%rsp), %rcx
callq __hipPopCallConfiguration
movq 216(%rsp), %rsi
movl 224(%rsp), %edx
movq 200(%rsp), %rcx
movl 208(%rsp), %r8d
movl $_Z7Kernel3P4NodePiS1_PbS2_iS2_, %edi
leaq 112(%rsp), %r9
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_19
.LBB2_20:
movl $.L.str.9, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rsi
movslq no_of_nodes(%rip), %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.10, %edi
movl $.L.str.11, %esi
callq fopen
movq %rax, %rbx
cmpl $0, no_of_nodes(%rip)
je .LBB2_23
# %bb.21: # %.lr.ph85.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_22: # %.lr.ph85
# =>This Inner Loop Header: Depth=1
movl (%r12,%r14,4), %ecx
movl $.L.str.12, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
incq %r14
movl no_of_nodes(%rip), %eax
cmpq %rax, %r14
jb .LBB2_22
.LBB2_23: # %._crit_edge86
movq %rbx, %rdi
callq fclose
movl $.Lstr.4, %edi
callq puts@PLT
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 112(%rsp), %rax
subq 176(%rsp), %rax # 8-byte Folded Reload
movq 120(%rsp), %rcx
subq 32(%rsp), %rcx # 8-byte Folded Reload
imulq $1000000, %rax, %rax # imm = 0xF4240
addq %rcx, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movl $.L.str.14, %esi
movb $1, %al
callq printf
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_24:
.cfi_def_cfa_offset 352
callq _Z5UsageiPPc
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size _Z8GPLGraphiPPc, .Lfunc_end2-_Z8GPLGraphiPPc
.cfi_endproc
# -- End function
.globl _Z5UsageiPPc # -- Begin function _Z5UsageiPPc
.p2align 4, 0x90
.type _Z5UsageiPPc,@function
_Z5UsageiPPc: # @_Z5UsageiPPc
.cfi_startproc
# %bb.0:
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
jmp fprintf # TAILCALL
.Lfunc_end3:
.size _Z5UsageiPPc, .Lfunc_end3-_Z5UsageiPPc
.cfi_endproc
# -- End function
.globl _Z11start_timerv # -- Begin function _Z11start_timerv
.p2align 4, 0x90
.type _Z11start_timerv,@function
_Z11start_timerv: # @_Z11start_timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, 8(%rsp), %rax # imm = 0xF4240
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11start_timerv, .Lfunc_end4-_Z11start_timerv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10stop_timerxPc
.LCPI5_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z10stop_timerxPc
.p2align 4, 0x90
.type _Z10stop_timerxPc,@function
_Z10stop_timerxPc: # @_Z10stop_timerxPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, (%rsp), %rax # imm = 0xF4240
movq 8(%rsp), %r15
subq %r14, %r15
addq %rax, %r15
cvtsi2ss %r15, %xmm0
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movq %rbx, %rsi
movb $1, %al
callq printf
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z10stop_timerxPc, .Lfunc_end5-_Z10stop_timerxPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7Kernel3P4NodePiS1_PbS2_iS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type no_of_nodes,@object # @no_of_nodes
.bss
.globl no_of_nodes
.p2align 2, 0x0
no_of_nodes:
.long 0 # 0x0
.size no_of_nodes, 4
.type edge_list_size,@object # @edge_list_size
.globl edge_list_size
.p2align 2, 0x0
edge_list_size:
.long 0 # 0x0
.size edge_list_size, 4
.type fp,@object # @fp
.globl fp
.p2align 3, 0x0
fp:
.quad 0
.size fp, 8
.type _Z7Kernel3P4NodePiS1_PbS2_iS2_,@object # @_Z7Kernel3P4NodePiS1_PbS2_iS2_
.section .rodata,"a",@progbits
.globl _Z7Kernel3P4NodePiS1_PbS2_iS2_
.p2align 3, 0x0
_Z7Kernel3P4NodePiS1_PbS2_iS2_:
.quad _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.size _Z7Kernel3P4NodePiS1_PbS2_iS2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s <input_file>\n"
.size .L.str, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d"
.size .L.str.5, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Copied Everything to Kernel"
.size .L.str.7, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Kernel Executed %d times\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "result.txt"
.size .L.str.10, 11
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "w"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%d) color:%d\n"
.size .L.str.12, 14
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Total Processing time"
.size .L.str.14, 22
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%s: %.5f sec\n"
.size .L.str.15, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7Kernel3P4NodePiS1_PbS2_iS2_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Reading File"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error Reading graph file"
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Read File"
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Start traversing the tree"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Result stored in result.txt"
.size .Lstr.4, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__Kernel3P4NodePiS1_PbS2_iS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym no_of_nodes
.addrsig_sym edge_list_size
.addrsig_sym _Z7Kernel3P4NodePiS1_PbS2_iS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
cudaError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY);
void imprimeVector(int *v, int n) {
printf("{");
for (int i = 1; i <= n; i++) {
printf("%d", *v);
if (i != n) printf(", ");
v++;
}
printf("}");
}
void imprimeMatriz(int *v, int m, int n) {
int i, j;
printf("\n");
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++) {
printf("%d\t", v[i*n+j]);
}
printf("\n");
}
}
__global__ void rmKernel(int *x, int *y, int *m) {
int idx = threadIdx.x;
int idy = blockIdx.x;
int id = blockIdx.x * blockDim.x + threadIdx.x;
x[idx] = idx;
y[idy] = idy;
m[id] = idy*10 + idx;
}
int main()
{
const int sizeX = 5;
const int sizeY = 6;
int x[sizeX] = { 0, 0, 0, 0, 0 };
int y[sizeY] = { 0, 0, 0, 0, 0, 0 };
int m[sizeY*sizeX] = { 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = RellenaMatriz(x, y, m, sizeX, sizeY);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "Fallo en RellenaMatriz");
return 1;
}
imprimeVector(x, sizeX);
imprimeVector(y, sizeY);
imprimeMatriz(m, sizeY, sizeX);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY)
{
int *dev_x = 0;
int *dev_y = 0;
int *dev_m = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_x, sizeX * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_y, sizeY * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_m, sizeY * sizeX * sizeof(int *));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
/*
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_x, x, sizeX * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_y, y, sizeY * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}*/
// Launch a kernel on the GPU with one thread for each element.
rmKernel <<<sizeY, sizeX>>>(dev_x, dev_y, dev_m);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(x, dev_x, sizeX * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(y, dev_y, sizeY * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(m, dev_m, sizeY * sizeX * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_m);
return cudaStatus;
} | code for sm_80
Function : _Z8rmKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e6e0000002500 */
/*0050*/ IMAD.WIDE R2, R11, R7, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD R6, R0.reuse, c[0x0][0x0], R11 ; /* 0x0000000000067a24 */
/* 0x042fe200078e020b */
/*0070*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0080*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD R9, R0, 0xa, R11 ; /* 0x0000000a00097824 */
/* 0x000fe200078e020b */
/*00a0*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
cudaError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY);
void imprimeVector(int *v, int n) {
printf("{");
for (int i = 1; i <= n; i++) {
printf("%d", *v);
if (i != n) printf(", ");
v++;
}
printf("}");
}
void imprimeMatriz(int *v, int m, int n) {
int i, j;
printf("\n");
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++) {
printf("%d\t", v[i*n+j]);
}
printf("\n");
}
}
__global__ void rmKernel(int *x, int *y, int *m) {
int idx = threadIdx.x;
int idy = blockIdx.x;
int id = blockIdx.x * blockDim.x + threadIdx.x;
x[idx] = idx;
y[idy] = idy;
m[id] = idy*10 + idx;
}
int main()
{
const int sizeX = 5;
const int sizeY = 6;
int x[sizeX] = { 0, 0, 0, 0, 0 };
int y[sizeY] = { 0, 0, 0, 0, 0, 0 };
int m[sizeY*sizeX] = { 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = RellenaMatriz(x, y, m, sizeX, sizeY);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "Fallo en RellenaMatriz");
return 1;
}
imprimeVector(x, sizeX);
imprimeVector(y, sizeY);
imprimeMatriz(m, sizeY, sizeX);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY)
{
int *dev_x = 0;
int *dev_y = 0;
int *dev_m = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_x, sizeX * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_y, sizeY * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_m, sizeY * sizeX * sizeof(int *));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
/*
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_x, x, sizeX * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_y, y, sizeY * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}*/
// Launch a kernel on the GPU with one thread for each element.
rmKernel <<<sizeY, sizeX>>>(dev_x, dev_y, dev_m);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(x, dev_x, sizeX * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(y, dev_y, sizeY * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(m, dev_m, sizeY * sizeX * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_m);
return cudaStatus;
} | .file "tmpxft_0018f70f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{"
.LC1:
.string "%d"
.LC2:
.string ", "
.LC3:
.string "}"
.text
.globl _Z13imprimeVectorPii
.type _Z13imprimeVectorPii, @function
_Z13imprimeVectorPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movl %esi, %r12d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L4
movl $1, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
jmp .L5
.L8:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
addl $1, %ebx
cmpl %ebx, %r12d
jl .L4
.L5:
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, %r12d
jne .L8
.L4:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13imprimeVectorPii, .-_Z13imprimeVectorPii
.section .rodata.str1.1
.LC4:
.string "\n"
.LC5:
.string "%d\t"
.text
.globl _Z13imprimeMatrizPiii
.type _Z13imprimeMatrizPiii, @function
_Z13imprimeMatrizPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L9
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC5(%rip), %r12
jmp .L11
.L13:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdi
addq %rdi, %rax
leaq (%rcx,%rax,4), %rbp
.L12:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L9
.L11:
testl %r15d, %r15d
jg .L13
jmp .L14
.L9:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13imprimeMatrizPiii, .-_Z13imprimeMatrizPiii
.globl _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
.type _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_, @function
_Z31__device_stub__Z8rmKernelPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8rmKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_, .-_Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
.globl _Z8rmKernelPiS_S_
.type _Z8rmKernelPiS_S_, @function
_Z8rmKernelPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8rmKernelPiS_S_, .-_Z8rmKernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC7:
.string "cudaMalloc failed!"
.LC8:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC10:
.string "cudaMemcpy failed!"
.text
.globl _Z13RellenaMatrizPiS_S_jj
.type _Z13RellenaMatrizPiS_S_jj, @function
_Z13RellenaMatrizPiS_S_jj:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %ebp
movl %r8d, %r12d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L38
movl %ebp, %r13d
salq $2, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movl %r12d, %r14d
salq $2, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movl %ebp, %r15d
imull %r12d, %r15d
leaq 0(,%r15,8), %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L31:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L45
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L46
leaq 0(,%r15,4), %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L27
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L38:
movl %eax, %ebx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L27:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl %ebx, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L40:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L41:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L42:
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
jmp .L31
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L44:
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L45:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L46:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z13RellenaMatrizPiS_S_jj, .-_Z13RellenaMatrizPiS_S_jj
.section .rodata.str1.1
.LC11:
.string "Fallo en RellenaMatriz"
.LC12:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movl $0, 4(%rsp)
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, 16(%rsp)
movl $0, 32(%rsp)
movl $0, 36(%rsp)
movl $0, 40(%rsp)
movl $0, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 64(%rsp), %rdi
movl $15, %ecx
rep stosq
leaq 64(%rsp), %rdx
leaq 32(%rsp), %rsi
movq %rsp, %rdi
movl $6, %r8d
movl $5, %ecx
call _Z13RellenaMatrizPiS_S_jj
testl %eax, %eax
jne .L54
movq %rsp, %rdi
movl $5, %esi
call _Z13imprimeVectorPii
leaq 32(%rsp), %rdi
movl $6, %esi
call _Z13imprimeVectorPii
leaq 64(%rsp), %rdi
movl $5, %edx
movl $6, %esi
call _Z13imprimeMatrizPiii
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L55
.L48:
movq 184(%rsp), %rdx
subq %fs:40, %rdx
jne .L56
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L48
.L55:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L48
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8rmKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rmKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
cudaError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY);
void imprimeVector(int *v, int n) {
printf("{");
for (int i = 1; i <= n; i++) {
printf("%d", *v);
if (i != n) printf(", ");
v++;
}
printf("}");
}
void imprimeMatriz(int *v, int m, int n) {
int i, j;
printf("\n");
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++) {
printf("%d\t", v[i*n+j]);
}
printf("\n");
}
}
__global__ void rmKernel(int *x, int *y, int *m) {
int idx = threadIdx.x;
int idy = blockIdx.x;
int id = blockIdx.x * blockDim.x + threadIdx.x;
x[idx] = idx;
y[idy] = idy;
m[id] = idy*10 + idx;
}
int main()
{
const int sizeX = 5;
const int sizeY = 6;
int x[sizeX] = { 0, 0, 0, 0, 0 };
int y[sizeY] = { 0, 0, 0, 0, 0, 0 };
int m[sizeY*sizeX] = { 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = RellenaMatriz(x, y, m, sizeX, sizeY);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "Fallo en RellenaMatriz");
return 1;
}
imprimeVector(x, sizeX);
imprimeVector(y, sizeY);
imprimeMatriz(m, sizeY, sizeX);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY)
{
int *dev_x = 0;
int *dev_y = 0;
int *dev_m = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_x, sizeX * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_y, sizeY * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_m, sizeY * sizeX * sizeof(int *));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
/*
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_x, x, sizeX * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_y, y, sizeY * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}*/
// Launch a kernel on the GPU with one thread for each element.
rmKernel <<<sizeY, sizeX>>>(dev_x, dev_y, dev_m);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(x, dev_x, sizeX * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(y, dev_y, sizeY * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(m, dev_m, sizeY * sizeX * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_m);
return cudaStatus;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
hipError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY);
void imprimeVector(int *v, int n) {
printf("{");
for (int i = 1; i <= n; i++) {
printf("%d", *v);
if (i != n) printf(", ");
v++;
}
printf("}");
}
void imprimeMatriz(int *v, int m, int n) {
int i, j;
printf("\n");
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++) {
printf("%d\t", v[i*n+j]);
}
printf("\n");
}
}
__global__ void rmKernel(int *x, int *y, int *m) {
int idx = threadIdx.x;
int idy = blockIdx.x;
int id = blockIdx.x * blockDim.x + threadIdx.x;
x[idx] = idx;
y[idy] = idy;
m[id] = idy*10 + idx;
}
int main()
{
const int sizeX = 5;
const int sizeY = 6;
int x[sizeX] = { 0, 0, 0, 0, 0 };
int y[sizeY] = { 0, 0, 0, 0, 0, 0 };
int m[sizeY*sizeX] = { 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0 };
// Add vectors in parallel.
hipError_t cudaStatus = RellenaMatriz(x, y, m, sizeX, sizeY);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "Fallo en RellenaMatriz");
return 1;
}
imprimeVector(x, sizeX);
imprimeVector(y, sizeY);
imprimeMatriz(m, sizeY, sizeX);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY)
{
int *dev_x = 0;
int *dev_y = 0;
int *dev_m = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_x, sizeX * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_y, sizeY * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_m, sizeY * sizeX * sizeof(int *));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
/*
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_x, x, sizeX * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_y, y, sizeY * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}*/
// Launch a kernel on the GPU with one thread for each element.
rmKernel <<<sizeY, sizeX>>>(dev_x, dev_y, dev_m);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(x, dev_x, sizeX * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(y, dev_y, sizeY * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(m, dev_m, sizeY * sizeX * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_m);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
hipError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY);
void imprimeVector(int *v, int n) {
printf("{");
for (int i = 1; i <= n; i++) {
printf("%d", *v);
if (i != n) printf(", ");
v++;
}
printf("}");
}
void imprimeMatriz(int *v, int m, int n) {
int i, j;
printf("\n");
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++) {
printf("%d\t", v[i*n+j]);
}
printf("\n");
}
}
__global__ void rmKernel(int *x, int *y, int *m) {
int idx = threadIdx.x;
int idy = blockIdx.x;
int id = blockIdx.x * blockDim.x + threadIdx.x;
x[idx] = idx;
y[idy] = idy;
m[id] = idy*10 + idx;
}
int main()
{
const int sizeX = 5;
const int sizeY = 6;
int x[sizeX] = { 0, 0, 0, 0, 0 };
int y[sizeY] = { 0, 0, 0, 0, 0, 0 };
int m[sizeY*sizeX] = { 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0 };
// Add vectors in parallel.
hipError_t cudaStatus = RellenaMatriz(x, y, m, sizeX, sizeY);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "Fallo en RellenaMatriz");
return 1;
}
imprimeVector(x, sizeX);
imprimeVector(y, sizeY);
imprimeMatriz(m, sizeY, sizeX);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY)
{
int *dev_x = 0;
int *dev_y = 0;
int *dev_m = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_x, sizeX * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_y, sizeY * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_m, sizeY * sizeX * sizeof(int *));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
/*
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_x, x, sizeX * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_y, y, sizeY * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}*/
// Launch a kernel on the GPU with one thread for each element.
rmKernel <<<sizeY, sizeX>>>(dev_x, dev_y, dev_m);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(x, dev_x, sizeX * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(y, dev_y, sizeY * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(m, dev_m, sizeY * sizeX * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_m);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8rmKernelPiS_S_
.globl _Z8rmKernelPiS_S_
.p2align 8
.type _Z8rmKernelPiS_S_,@function
_Z8rmKernelPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
v_lshlrev_b32_e32 v7, 2, v0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s15
s_lshl_b64 s[8:9], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mad_u64_u32 v[3:4], null, s4, 10, v[0:1]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s8
s_addc_u32 s3, s3, s9
global_store_b32 v7, v0, s[0:1]
global_store_b32 v5, v6, s[2:3]
global_store_b32 v[1:2], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8rmKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8rmKernelPiS_S_, .Lfunc_end0-_Z8rmKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8rmKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8rmKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
hipError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY);
void imprimeVector(int *v, int n) {
printf("{");
for (int i = 1; i <= n; i++) {
printf("%d", *v);
if (i != n) printf(", ");
v++;
}
printf("}");
}
void imprimeMatriz(int *v, int m, int n) {
int i, j;
printf("\n");
for (i = 0; i < m; i++) {
for (j = 0; j < n; j++) {
printf("%d\t", v[i*n+j]);
}
printf("\n");
}
}
__global__ void rmKernel(int *x, int *y, int *m) {
int idx = threadIdx.x;
int idy = blockIdx.x;
int id = blockIdx.x * blockDim.x + threadIdx.x;
x[idx] = idx;
y[idy] = idy;
m[id] = idy*10 + idx;
}
int main()
{
const int sizeX = 5;
const int sizeY = 6;
int x[sizeX] = { 0, 0, 0, 0, 0 };
int y[sizeY] = { 0, 0, 0, 0, 0, 0 };
int m[sizeY*sizeX] = { 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0
, 0, 0, 0, 0, 0 };
// Add vectors in parallel.
hipError_t cudaStatus = RellenaMatriz(x, y, m, sizeX, sizeY);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "Fallo en RellenaMatriz");
return 1;
}
imprimeVector(x, sizeX);
imprimeVector(y, sizeY);
imprimeMatriz(m, sizeY, sizeX);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t RellenaMatriz(int *x, int *y, int *m, unsigned int sizeX, unsigned int sizeY)
{
int *dev_x = 0;
int *dev_y = 0;
int *dev_m = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_x, sizeX * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_y, sizeY * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_m, sizeY * sizeX * sizeof(int *));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
/*
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_x, x, sizeX * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_y, y, sizeY * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}*/
// Launch a kernel on the GPU with one thread for each element.
rmKernel <<<sizeY, sizeX>>>(dev_x, dev_y, dev_m);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(x, dev_x, sizeX * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(y, dev_y, sizeY * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(m, dev_m, sizeY * sizeX * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_m);
return cudaStatus;
} | .text
.file "kernel.hip"
.globl _Z13imprimeVectorPii # -- Begin function _Z13imprimeVectorPii
.p2align 4, 0x90
.type _Z13imprimeVectorPii,@function
_Z13imprimeVectorPii: # @_Z13imprimeVectorPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movl $123, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB0_5
# %bb.1: # %.lr.ph.preheader
negl %ebx
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
incq %r15
movl %ebx, %eax
addl %r15d, %eax
je .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rbx,%r15), %ebp
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $-1, %ebp
je .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %._crit_edge
movl $125, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z13imprimeVectorPii, .Lfunc_end0-_Z13imprimeVectorPii
.cfi_endproc
# -- End function
.globl _Z13imprimeMatrizPiii # -- Begin function _Z13imprimeMatrizPiii
.p2align 4, 0x90
.type _Z13imprimeMatrizPiii,@function
_Z13imprimeMatrizPiii: # @_Z13imprimeMatrizPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13imprimeMatrizPiii, .Lfunc_end1-_Z13imprimeMatrizPiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__rmKernelPiS_S_ # -- Begin function _Z23__device_stub__rmKernelPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__rmKernelPiS_S_,@function
_Z23__device_stub__rmKernelPiS_S_: # @_Z23__device_stub__rmKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8rmKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__rmKernelPiS_S_, .Lfunc_end2-_Z23__device_stub__rmKernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $192, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movq $0, 176(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rbx
movq %rbx, %rdx
movl $5, %ecx
movl $6, %r8d
callq _Z13RellenaMatrizPiS_S_jj
testl %eax, %eax
jne .LBB3_1
# %bb.2:
movl $123, %edi
callq putchar@PLT
xorl %r14d, %r14d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
incq %r14
cmpl $5, %r14d
je .LBB3_6
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rsp,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $4, %r14d
je .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_5
.LBB3_6: # %_Z13imprimeVectorPii.exit
movl $125, %edi
callq putchar@PLT
movl $123, %edi
callq putchar@PLT
xorl %r14d, %r14d
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
incq %r14
cmpl $6, %r14d
je .LBB3_10
.LBB3_7: # %.lr.ph.i5
# =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $5, %r14d
je .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_9
.LBB3_10: # %_Z13imprimeVectorPii.exit11
movl $125, %edi
callq putchar@PLT
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_11: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB3_12
# %bb.13: # %._crit_edge.i
# in Loop: Header=BB3_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $20, %rbx
cmpq $6, %r14
jne .LBB3_11
# %bb.14: # %_Z13imprimeMatrizPiii.exit
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB3_15
.LBB3_17:
addq $192, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 224
movl $.L.str.6, %edi
jmp .LBB3_16
.LBB3_15:
movl $.L.str.7, %edi
.LBB3_16: # %.sink.split
movq stderr(%rip), %rcx
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB3_17
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z13RellenaMatrizPiS_S_jj # -- Begin function _Z13RellenaMatrizPiS_S_jj
.p2align 4, 0x90
.type _Z13RellenaMatrizPiS_S_jj,@function
_Z13RellenaMatrizPiS_S_jj: # @_Z13RellenaMatrizPiS_S_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebx
movl %ecx, %r15d
movq %rdx, %r12
movq %rsi, %rbp
movq %rdi, %r14
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_18
# %bb.1:
movq %r14, 48(%rsp) # 8-byte Spill
movl %r15d, %r14d
leaq (,%r14,4), %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.2:
movq %rbp, 40(%rsp) # 8-byte Spill
movq %r12, 32(%rsp) # 8-byte Spill
movl %ebx, %r12d
leaq (,%r12,4), %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.3:
imull %r15d, %ebx
leaq (,%rbx,8), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.4:
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r14
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8rmKernelPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_19
# %bb.7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_20
# %bb.8:
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_13
# %bb.9:
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_13
# %bb.10:
movq 8(%rsp), %rsi
shlq $2, %rbx
movq 32(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB4_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB4_16
.LBB4_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
jmp .LBB4_14
.LBB4_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
.LBB4_14:
movl $17, %esi
.LBB4_15:
movl $1, %edx
.LBB4_16:
callq fwrite@PLT
.LBB4_17:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_18:
.cfi_def_cfa_offset 208
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $63, %esi
jmp .LBB4_15
.LBB4_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_17
.LBB4_20:
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB4_17
.Lfunc_end4:
.size _Z13RellenaMatrizPiS_S_jj, .Lfunc_end4-_Z13RellenaMatrizPiS_S_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rmKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type _Z8rmKernelPiS_S_,@object # @_Z8rmKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z8rmKernelPiS_S_
.p2align 3, 0x0
_Z8rmKernelPiS_S_:
.quad _Z23__device_stub__rmKernelPiS_S_
.size _Z8rmKernelPiS_S_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Fallo en RellenaMatriz"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceReset failed!"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.8, 64
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc failed!"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "addKernel launch failed: %s\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.11, 72
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipMemcpy failed!"
.size .L.str.12, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8rmKernelPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rmKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8rmKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8rmKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e6e0000002500 */
/*0050*/ IMAD.WIDE R2, R11, R7, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD R6, R0.reuse, c[0x0][0x0], R11 ; /* 0x0000000000067a24 */
/* 0x042fe200078e020b */
/*0070*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0080*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD R9, R0, 0xa, R11 ; /* 0x0000000a00097824 */
/* 0x000fe200078e020b */
/*00a0*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8rmKernelPiS_S_
.globl _Z8rmKernelPiS_S_
.p2align 8
.type _Z8rmKernelPiS_S_,@function
_Z8rmKernelPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s4, s15
s_ashr_i32 s5, s15, 31
v_lshlrev_b32_e32 v7, 2, v0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s15
s_lshl_b64 s[8:9], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mad_u64_u32 v[3:4], null, s4, 10, v[0:1]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s8
s_addc_u32 s3, s3, s9
global_store_b32 v7, v0, s[0:1]
global_store_b32 v5, v6, s[2:3]
global_store_b32 v[1:2], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8rmKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8rmKernelPiS_S_, .Lfunc_end0-_Z8rmKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8rmKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8rmKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f70f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "{"
.LC1:
.string "%d"
.LC2:
.string ", "
.LC3:
.string "}"
.text
.globl _Z13imprimeVectorPii
.type _Z13imprimeVectorPii, @function
_Z13imprimeVectorPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movl %esi, %r12d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L4
movl $1, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
jmp .L5
.L8:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
addl $1, %ebx
cmpl %ebx, %r12d
jl .L4
.L5:
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, %r12d
jne .L8
.L4:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13imprimeVectorPii, .-_Z13imprimeVectorPii
.section .rodata.str1.1
.LC4:
.string "\n"
.LC5:
.string "%d\t"
.text
.globl _Z13imprimeMatrizPiii
.type _Z13imprimeMatrizPiii, @function
_Z13imprimeMatrizPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L9
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC5(%rip), %r12
jmp .L11
.L13:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdi
addq %rdi, %rax
leaq (%rcx,%rax,4), %rbp
.L12:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
.L14:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L9
.L11:
testl %r15d, %r15d
jg .L13
jmp .L14
.L9:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13imprimeMatrizPiii, .-_Z13imprimeMatrizPiii
.globl _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
.type _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_, @function
_Z31__device_stub__Z8rmKernelPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8rmKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_, .-_Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
.globl _Z8rmKernelPiS_S_
.type _Z8rmKernelPiS_S_, @function
_Z8rmKernelPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8rmKernelPiS_S_, .-_Z8rmKernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC7:
.string "cudaMalloc failed!"
.LC8:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.section .rodata.str1.1
.LC10:
.string "cudaMemcpy failed!"
.text
.globl _Z13RellenaMatrizPiS_S_jj
.type _Z13RellenaMatrizPiS_S_jj, @function
_Z13RellenaMatrizPiS_S_jj:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %ebp
movl %r8d, %r12d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L38
movl %ebp, %r13d
salq $2, %r13
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movl %r12d, %r14d
salq $2, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L40
movl %ebp, %r15d
imull %r12d, %r15d
leaq 0(,%r15,8), %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L41
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L31:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L45
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L46
leaq 0(,%r15,4), %rdx
movl $2, %ecx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L27
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L38:
movl %eax, %ebx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L27:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl %ebx, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L40:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L41:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L42:
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z31__device_stub__Z8rmKernelPiS_S_PiS_S_
jmp .L31
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L44:
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L45:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L46:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L27
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z13RellenaMatrizPiS_S_jj, .-_Z13RellenaMatrizPiS_S_jj
.section .rodata.str1.1
.LC11:
.string "Fallo en RellenaMatriz"
.LC12:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $0, (%rsp)
movl $0, 4(%rsp)
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, 16(%rsp)
movl $0, 32(%rsp)
movl $0, 36(%rsp)
movl $0, 40(%rsp)
movl $0, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 64(%rsp), %rdi
movl $15, %ecx
rep stosq
leaq 64(%rsp), %rdx
leaq 32(%rsp), %rsi
movq %rsp, %rdi
movl $6, %r8d
movl $5, %ecx
call _Z13RellenaMatrizPiS_S_jj
testl %eax, %eax
jne .L54
movq %rsp, %rdi
movl $5, %esi
call _Z13imprimeVectorPii
leaq 32(%rsp), %rdi
movl $6, %esi
call _Z13imprimeVectorPii
leaq 64(%rsp), %rdi
movl $5, %edx
movl $6, %esi
call _Z13imprimeMatrizPiii
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L55
.L48:
movq 184(%rsp), %rdx
subq %fs:40, %rdx
jne .L56
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L48
.L55:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L48
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8rmKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8rmKernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z13imprimeVectorPii # -- Begin function _Z13imprimeVectorPii
.p2align 4, 0x90
.type _Z13imprimeVectorPii,@function
_Z13imprimeVectorPii: # @_Z13imprimeVectorPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movl $123, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB0_5
# %bb.1: # %.lr.ph.preheader
negl %ebx
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
incq %r15
movl %ebx, %eax
addl %r15d, %eax
je .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rbx,%r15), %ebp
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $-1, %ebp
je .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %._crit_edge
movl $125, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z13imprimeVectorPii, .Lfunc_end0-_Z13imprimeVectorPii
.cfi_endproc
# -- End function
.globl _Z13imprimeMatrizPiii # -- Begin function _Z13imprimeMatrizPiii
.p2align 4, 0x90
.type _Z13imprimeMatrizPiii,@function
_Z13imprimeMatrizPiii: # @_Z13imprimeMatrizPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13imprimeMatrizPiii, .Lfunc_end1-_Z13imprimeMatrizPiii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__rmKernelPiS_S_ # -- Begin function _Z23__device_stub__rmKernelPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__rmKernelPiS_S_,@function
_Z23__device_stub__rmKernelPiS_S_: # @_Z23__device_stub__rmKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8rmKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__rmKernelPiS_S_, .Lfunc_end2-_Z23__device_stub__rmKernelPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $192, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movq $0, 176(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rbx
movq %rbx, %rdx
movl $5, %ecx
movl $6, %r8d
callq _Z13RellenaMatrizPiS_S_jj
testl %eax, %eax
jne .LBB3_1
# %bb.2:
movl $123, %edi
callq putchar@PLT
xorl %r14d, %r14d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
incq %r14
cmpl $5, %r14d
je .LBB3_6
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rsp,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $4, %r14d
je .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_5
.LBB3_6: # %_Z13imprimeVectorPii.exit
movl $125, %edi
callq putchar@PLT
movl $123, %edi
callq putchar@PLT
xorl %r14d, %r14d
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
incq %r14
cmpl $6, %r14d
je .LBB3_10
.LBB3_7: # %.lr.ph.i5
# =>This Inner Loop Header: Depth=1
movl 32(%rsp,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $5, %r14d
je .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_9
.LBB3_10: # %_Z13imprimeVectorPii.exit11
movl $125, %edi
callq putchar@PLT
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_11: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB3_12
# %bb.13: # %._crit_edge.i
# in Loop: Header=BB3_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $20, %rbx
cmpq $6, %r14
jne .LBB3_11
# %bb.14: # %_Z13imprimeMatrizPiii.exit
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB3_15
.LBB3_17:
addq $192, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 224
movl $.L.str.6, %edi
jmp .LBB3_16
.LBB3_15:
movl $.L.str.7, %edi
.LBB3_16: # %.sink.split
movq stderr(%rip), %rcx
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB3_17
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z13RellenaMatrizPiS_S_jj # -- Begin function _Z13RellenaMatrizPiS_S_jj
.p2align 4, 0x90
.type _Z13RellenaMatrizPiS_S_jj,@function
_Z13RellenaMatrizPiS_S_jj: # @_Z13RellenaMatrizPiS_S_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebx
movl %ecx, %r15d
movq %rdx, %r12
movq %rsi, %rbp
movq %rdi, %r14
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB4_18
# %bb.1:
movq %r14, 48(%rsp) # 8-byte Spill
movl %r15d, %r14d
leaq (,%r14,4), %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.2:
movq %rbp, 40(%rsp) # 8-byte Spill
movq %r12, 32(%rsp) # 8-byte Spill
movl %ebx, %r12d
leaq (,%r12,4), %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.3:
imull %r15d, %ebx
leaq (,%rbx,8), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.4:
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r14
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8rmKernelPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_19
# %bb.7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_20
# %bb.8:
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_13
# %bb.9:
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_13
# %bb.10:
movq 8(%rsp), %rsi
shlq $2, %rbx
movq 32(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB4_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB4_16
.LBB4_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
jmp .LBB4_14
.LBB4_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
.LBB4_14:
movl $17, %esi
.LBB4_15:
movl $1, %edx
.LBB4_16:
callq fwrite@PLT
.LBB4_17:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_18:
.cfi_def_cfa_offset 208
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $63, %esi
jmp .LBB4_15
.LBB4_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB4_17
.LBB4_20:
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB4_17
.Lfunc_end4:
.size _Z13RellenaMatrizPiS_S_jj, .Lfunc_end4-_Z13RellenaMatrizPiS_S_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8rmKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type _Z8rmKernelPiS_S_,@object # @_Z8rmKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z8rmKernelPiS_S_
.p2align 3, 0x0
_Z8rmKernelPiS_S_:
.quad _Z23__device_stub__rmKernelPiS_S_
.size _Z8rmKernelPiS_S_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Fallo en RellenaMatriz"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceReset failed!"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.8, 64
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc failed!"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "addKernel launch failed: %s\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.11, 72
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipMemcpy failed!"
.size .L.str.12, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8rmKernelPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__rmKernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8rmKernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: cpyTestDrv_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (cpyTestDrv_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, int* memstruct, uint* single_out
*/
__global__ void
cpyTestDrv_kernel(float* d_array_out, float* d_array_in, int count,
unsigned int* memstruct,
unsigned int* d_single_out, unsigned int d_single_in)
{
// copy - single value
*d_single_out = d_single_in;
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
// copy of array variables
for(int j = 0 ; j < count ; j++)
{
*(d_array_out+j) = d_array_in[j];
*(d_array_out+j) = j;
}
} | code for sm_80
Function : cpyTestDrv_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R25, c[0x0][0x14] ; /* 0x0000050000197a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff137624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000ea20000002700 */
/*00a0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff157624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ee20000002100 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fc400078e00ff */
/*00f0*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff177624 */
/* 0x000fe200078e00ff */
/*0100*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000f220000002200 */
/*0110*/ IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff1b7624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R29, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff1d7624 */
/* 0x000fe200078e00ff */
/*0130*/ S2R R17, SR_TID.Z ; /* 0x0000000000117919 */
/* 0x000f620000002300 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff007624 */
/* 0x000fc600078e00ff */
/*0150*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x0001e8000c101908 */
/*0160*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101908 */
/*0170*/ STG.E [R2.64+0x4], R23 ; /* 0x0000041702007986 */
/* 0x0001e8000c101908 */
/*0180*/ STG.E [R2.64+0x8], R25 ; /* 0x0000081902007986 */
/* 0x0001e8000c101908 */
/*0190*/ STG.E [R2.64+0xc], R27 ; /* 0x00000c1b02007986 */
/* 0x0001e8000c101908 */
/*01a0*/ STG.E [R2.64+0x10], R29 ; /* 0x0000101d02007986 */
/* 0x0003e8000c101908 */
/*01b0*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x0005e8000c101908 */
/*01c0*/ STG.E [R2.64+0x18], R7 ; /* 0x0000180702007986 */
/* 0x0011e8000c101908 */
/*01d0*/ STG.E [R2.64+0x1c], R9 ; /* 0x00001c0902007986 */
/* 0x0021e8000c101908 */
/*01e0*/ STG.E [R2.64+0x20], R11 ; /* 0x0000200b02007986 */
/* 0x0041e8000c101908 */
/*01f0*/ STG.E [R2.64+0x24], R13 ; /* 0x0000240d02007986 */
/* 0x0081e8000c101908 */
/*0200*/ STG.E [R2.64+0x28], R15 ; /* 0x0000280f02007986 */
/* 0x0101e8000c101908 */
/*0210*/ STG.E [R2.64+0x2c], R17 ; /* 0x00002c1102007986 */
/* 0x0201e2000c101908 */
/*0220*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R0, R6, -0x1, RZ ; /* 0xffffffff06007810 */
/* 0x000fe20007ffe0ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0260*/ LOP3.LUT R0, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306007812 */
/* 0x000fd600078ec0ff */
/*0270*/ @!P0 BRA 0x9e0 ; /* 0x0000076000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R4, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fe20007ffe1ff */
/*0290*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*02b0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*02d0*/ @!P0 BRA 0x8b0 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*02e0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0300*/ @!P1 BRA 0x690 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0320*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0330*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x000e220008201400 */
/*0340*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*0350*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0360*/ UIADD3 UR7, UR4, 0xe, URZ ; /* 0x0000000e04077890 */
/* 0x000fc6000fffe03f */
/*0370*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0380*/ I2F R7, UR5 ; /* 0x0000000500077d06 */
/* 0x000e620008201400 */
/*0390*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fce000fffe03f */
/*03a0*/ I2F R9, UR6 ; /* 0x0000000600097d06 */
/* 0x000ea20008201400 */
/*03b0*/ UIADD3 UR6, UR4, 0x4, URZ ; /* 0x0000000404067890 */
/* 0x000fe2000fffe03f */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011ec000c101908 */
/*03d0*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x000ee20008201400 */
/*03e0*/ UIADD3 UR5, UR4, 0x5, URZ ; /* 0x0000000504057890 */
/* 0x000fe2000fffe03f */
/*03f0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x002fe2000c101908 */
/*0400*/ IADD3 R5, P2, R2, 0x40, RZ ; /* 0x0000004002057810 */
/* 0x001fca0007f5e0ff */
/*0410*/ I2F R13, UR6 ; /* 0x00000006000d7d06 */
/* 0x000e220008201400 */
/*0420*/ UIADD3 UR6, UR4, 0x6, URZ ; /* 0x0000000604067890 */
/* 0x000fe2000fffe03f */
/*0430*/ IADD3.X R12, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0c7210 */
/* 0x000fe200017fe4ff */
/*0440*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x004fea000c101908 */
/*0450*/ I2F R15, UR5 ; /* 0x00000005000f7d06 */
/* 0x000e620008201400 */
/*0460*/ UIADD3 UR5, UR4, 0x7, URZ ; /* 0x0000000704057890 */
/* 0x000fe2000fffe03f */
/*0470*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x008fec000c101908 */
/*0480*/ I2F R17, UR6 ; /* 0x0000000600117d06 */
/* 0x000ea20008201400 */
/*0490*/ UIADD3 UR6, UR4, 0x8, URZ ; /* 0x0000000804067890 */
/* 0x000fe2000fffe03f */
/*04a0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x001fec000c101908 */
/*04b0*/ I2F R19, UR5 ; /* 0x0000000500137d06 */
/* 0x000e220008201400 */
/*04c0*/ UIADD3 UR5, UR4, 0x9, URZ ; /* 0x0000000904057890 */
/* 0x000fe2000fffe03f */
/*04d0*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x002fec000c101908 */
/*04e0*/ I2F R21, UR6 ; /* 0x0000000600157d06 */
/* 0x000e620008201400 */
/*04f0*/ UIADD3 UR6, UR4, 0xa, URZ ; /* 0x0000000a04067890 */
/* 0x000fe2000fffe03f */
/*0500*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x004fec000c101908 */
/*0510*/ I2F R23, UR5 ; /* 0x0000000500177d06 */
/* 0x000ea20008201400 */
/*0520*/ UIADD3 UR5, UR4, 0xb, URZ ; /* 0x0000000b04057890 */
/* 0x000fe2000fffe03f */
/*0530*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x001fec000c101908 */
/*0540*/ I2F R25, UR6 ; /* 0x0000000600197d06 */
/* 0x000e220008201400 */
/*0550*/ UIADD3 UR6, UR4, 0xc, URZ ; /* 0x0000000c04067890 */
/* 0x000fe2000fffe03f */
/*0560*/ STG.E [R2.64+0x20], R21 ; /* 0x0000201502007986 */
/* 0x002fec000c101908 */
/*0570*/ I2F R27, UR5 ; /* 0x00000005001b7d06 */
/* 0x000e620008201400 */
/*0580*/ UIADD3 UR5, UR4, 0xd, URZ ; /* 0x0000000d04057890 */
/* 0x000fe2000fffe03f */
/*0590*/ STG.E [R2.64+0x24], R23 ; /* 0x0000241702007986 */
/* 0x004fec000c101908 */
/*05a0*/ I2F R29, UR6 ; /* 0x00000006001d7d06 */
/* 0x000ea20008201400 */
/*05b0*/ UIADD3 UR6, UR4, 0xf, URZ ; /* 0x0000000f04067890 */
/* 0x000fe2000fffe03f */
/*05c0*/ STG.E [R2.64+0x28], R25 ; /* 0x0000281902007986 */
/* 0x001fe2000c101908 */
/*05d0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fca000fffe03f */
/*05e0*/ I2F R6, UR5 ; /* 0x0000000500067d06 */
/* 0x000e220008201400 */
/*05f0*/ STG.E [R2.64+0x2c], R27 ; /* 0x00002c1b02007986 */
/* 0x002fee000c101908 */
/*0600*/ I2F R8, UR7 ; /* 0x0000000700087d06 */
/* 0x000e620008201400 */
/*0610*/ STG.E [R2.64+0x30], R29 ; /* 0x0000301d02007986 */
/* 0x004fee000c101908 */
/*0620*/ I2F R10, UR6 ; /* 0x00000006000a7d06 */
/* 0x000ea20008201400 */
/*0630*/ STG.E [R2.64+0x34], R6 ; /* 0x0000340602007986 */
/* 0x001fe8000c101908 */
/*0640*/ STG.E [R2.64+0x38], R8 ; /* 0x0000380802007986 */
/* 0x002fe8000c101908 */
/*0650*/ STG.E [R2.64+0x3c], R10 ; /* 0x00003c0a02007986 */
/* 0x0041e4000c101908 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0670*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000c */
/*0680*/ @P1 BRA 0x320 ; /* 0xfffffc9000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x890 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*06b0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*06c0*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x000e220008201400 */
/*06d0*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*06e0*/ IADD3 R6, P1, R2, 0x20, RZ ; /* 0x0000002002067810 */
/* 0x000fe20007f3e0ff */
/*06f0*/ UIADD3 UR7, UR4, 0x6, URZ ; /* 0x0000000604077890 */
/* 0x000fe2000fffe03f */
/*0700*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0710*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*0720*/ I2F R7, UR5 ; /* 0x0000000500077d06 */
/* 0x000e620008201400 */
/*0730*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fce000fffe03f */
/*0740*/ I2F R9, UR6 ; /* 0x0000000600097d06 */
/* 0x000ea20008201400 */
/*0750*/ UIADD3 UR6, UR4, 0x4, URZ ; /* 0x0000000404067890 */
/* 0x000fe2000fffe03f */
/*0760*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011ec000c101908 */
/*0770*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x000ee20008201400 */
/*0780*/ UIADD3 UR5, UR4, 0x5, URZ ; /* 0x0000000504057890 */
/* 0x000fe2000fffe03f */
/*0790*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x002fe2000c101908 */
/*07a0*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x001fca00008e0603 */
/*07b0*/ I2F R13, UR6 ; /* 0x00000006000d7d06 */
/* 0x000e220008201400 */
/*07c0*/ UIADD3 UR6, UR4, 0x7, URZ ; /* 0x0000000704067890 */
/* 0x000fe2000fffe03f */
/*07d0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x004fe2000c101908 */
/*07e0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fca000fffe03f */
/*07f0*/ I2F R15, UR5 ; /* 0x00000005000f7d06 */
/* 0x000e620008201400 */
/*0800*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x008fee000c101908 */
/*0810*/ I2F R17, UR7 ; /* 0x0000000700117d06 */
/* 0x000ea20008201400 */
/*0820*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x001fee000c101908 */
/*0830*/ I2F R19, UR6 ; /* 0x0000000600137d06 */
/* 0x000e220008201400 */
/*0840*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x002fe8000c101908 */
/*0850*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x004fe8000c101908 */
/*0860*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x0011e4000c101908 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*0890*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*08a0*/ @!P0 BRA 0x9e0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*08b0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*08c0*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201400 */
/*08d0*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*08e0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ UIADD3 UR7, UR4, 0x3, URZ ; /* 0x0000000304077890 */
/* 0x000fe2000fffe03f */
/*0900*/ IADD3 R5, P1, R2, 0x10, RZ ; /* 0x0000001002057810 */
/* 0x000fe20007f3e0ff */
/*0910*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0920*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0930*/ I2F R9, UR5 ; /* 0x0000000500097d06 */
/* 0x000e620008201400 */
/*0940*/ IADD3.X R6, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff067210 */
/* 0x000fce0000ffe4ff */
/*0950*/ I2F R11, UR6 ; /* 0x00000006000b7d06 */
/* 0x000ea20008201400 */
/*0960*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fee000c101908 */
/*0970*/ I2F R13, UR7 ; /* 0x00000007000d7d06 */
/* 0x000e220008201400 */
/*0980*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x002fe8000c101908 */
/*0990*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x004fe8000c101908 */
/*09a0*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0011e4000c101908 */
/*09b0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*09c0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*09d0*/ @P0 BRA 0x8b0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*09e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*09f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a00*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0a10*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0a20*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fc8000f8e0206 */
/*0a30*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x001e620008201400 */
/*0a40*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x001fe2000f8e00ff */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IMAD.U32 R3, RZ, RZ, UR7 ; /* 0x00000007ff037e24 */
/* 0x000fe2000f8e00ff */
/*0a80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0a90*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc4000fffe03f */
/*0aa0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ab0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0021f2000c101908 */
/*0ac0*/ @P0 BRA 0xa30 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: cpyTestDrv_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (cpyTestDrv_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, int* memstruct, uint* single_out
*/
__global__ void
cpyTestDrv_kernel(float* d_array_out, float* d_array_in, int count,
unsigned int* memstruct,
unsigned int* d_single_out, unsigned int d_single_in)
{
// copy - single value
*d_single_out = d_single_in;
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
// copy of array variables
for(int j = 0 ; j < count ; j++)
{
*(d_array_out+j) = d_array_in[j];
*(d_array_out+j) = j;
}
} | .file "tmpxft_0000672c_00000000-6_cpyTestDrv_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j
.type _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j, @function
_Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq cpyTestDrv_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j, .-_Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j
.globl cpyTestDrv_kernel
.type cpyTestDrv_kernel, @function
cpyTestDrv_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size cpyTestDrv_kernel, .-cpyTestDrv_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cpyTestDrv_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cpyTestDrv_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: cpyTestDrv_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (cpyTestDrv_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, int* memstruct, uint* single_out
*/
__global__ void
cpyTestDrv_kernel(float* d_array_out, float* d_array_in, int count,
unsigned int* memstruct,
unsigned int* d_single_out, unsigned int d_single_in)
{
// copy - single value
*d_single_out = d_single_in;
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
// copy of array variables
for(int j = 0 ; j < count ; j++)
{
*(d_array_out+j) = d_array_in[j];
*(d_array_out+j) = j;
}
} | #include <hip/hip_runtime.h>
//#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: cpyTestDrv_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (cpyTestDrv_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, int* memstruct, uint* single_out
*/
__global__ void
cpyTestDrv_kernel(float* d_array_out, float* d_array_in, int count,
unsigned int* memstruct,
unsigned int* d_single_out, unsigned int d_single_in)
{
// copy - single value
*d_single_out = d_single_in;
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
// copy of array variables
for(int j = 0 ; j < count ; j++)
{
*(d_array_out+j) = d_array_in[j];
*(d_array_out+j) = j;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: cpyTestDrv_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (cpyTestDrv_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, int* memstruct, uint* single_out
*/
__global__ void
cpyTestDrv_kernel(float* d_array_out, float* d_array_in, int count,
unsigned int* memstruct,
unsigned int* d_single_out, unsigned int d_single_in)
{
// copy - single value
*d_single_out = d_single_in;
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
// copy of array variables
for(int j = 0 ; j < count ; j++)
{
*(d_array_out+j) = d_array_in[j];
*(d_array_out+j) = j;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected cpyTestDrv_kernel
.globl cpyTestDrv_kernel
.p2align 8
.type cpyTestDrv_kernel,@function
cpyTestDrv_kernel:
s_clause 0x4
s_load_b32 s3, s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x30
s_load_b32 s12, s[0:1], 0x40
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v7, 0x3ff, v0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s13
v_dual_mov_b32 v5, s14 :: v_dual_mov_b32 v6, s15
v_bfe_u32 v8, v0, 10, 10
v_bfe_u32 v9, v0, 20, 10
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v14, s3
s_and_b32 s3, s11, 0xffff
v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
s_lshr_b32 s8, s11, 16
s_and_b32 s9, s12, 0xffff
v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s3
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
s_cmp_lt_i32 s2, 1
s_clause 0x3
global_store_b32 v1, v14, s[6:7]
global_store_b128 v1, v[10:13], s[4:5]
global_store_b128 v1, v[2:5], s[4:5] offset:16
global_store_b128 v1, v[6:9], s[4:5] offset:32
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, s3
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel cpyTestDrv_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size cpyTestDrv_kernel, .Lfunc_end0-cpyTestDrv_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: cpyTestDrv_kernel
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: cpyTestDrv_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: cpyTestDrv_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (cpyTestDrv_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, int* memstruct, uint* single_out
*/
__global__ void
cpyTestDrv_kernel(float* d_array_out, float* d_array_in, int count,
unsigned int* memstruct,
unsigned int* d_single_out, unsigned int d_single_in)
{
// copy - single value
*d_single_out = d_single_in;
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
// copy of array variables
for(int j = 0 ; j < count ; j++)
{
*(d_array_out+j) = d_array_in[j];
*(d_array_out+j) = j;
}
} | .text
.file "cpyTestDrv_kernel.hip"
.globl __device_stub__cpyTestDrv_kernel # -- Begin function __device_stub__cpyTestDrv_kernel
.p2align 4, 0x90
.type __device_stub__cpyTestDrv_kernel,@function
__device_stub__cpyTestDrv_kernel: # @__device_stub__cpyTestDrv_kernel
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $cpyTestDrv_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__cpyTestDrv_kernel, .Lfunc_end0-__device_stub__cpyTestDrv_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cpyTestDrv_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cpyTestDrv_kernel,@object # @cpyTestDrv_kernel
.section .rodata,"a",@progbits
.globl cpyTestDrv_kernel
.p2align 3, 0x0
cpyTestDrv_kernel:
.quad __device_stub__cpyTestDrv_kernel
.size cpyTestDrv_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cpyTestDrv_kernel"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cpyTestDrv_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cpyTestDrv_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : cpyTestDrv_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R25, c[0x0][0x14] ; /* 0x0000050000197a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff137624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000ea20000002700 */
/*00a0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff157624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ee20000002100 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fc400078e00ff */
/*00f0*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff177624 */
/* 0x000fe200078e00ff */
/*0100*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000f220000002200 */
/*0110*/ IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff1b7624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R29, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff1d7624 */
/* 0x000fe200078e00ff */
/*0130*/ S2R R17, SR_TID.Z ; /* 0x0000000000117919 */
/* 0x000f620000002300 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff007624 */
/* 0x000fc600078e00ff */
/*0150*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x0001e8000c101908 */
/*0160*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101908 */
/*0170*/ STG.E [R2.64+0x4], R23 ; /* 0x0000041702007986 */
/* 0x0001e8000c101908 */
/*0180*/ STG.E [R2.64+0x8], R25 ; /* 0x0000081902007986 */
/* 0x0001e8000c101908 */
/*0190*/ STG.E [R2.64+0xc], R27 ; /* 0x00000c1b02007986 */
/* 0x0001e8000c101908 */
/*01a0*/ STG.E [R2.64+0x10], R29 ; /* 0x0000101d02007986 */
/* 0x0003e8000c101908 */
/*01b0*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x0005e8000c101908 */
/*01c0*/ STG.E [R2.64+0x18], R7 ; /* 0x0000180702007986 */
/* 0x0011e8000c101908 */
/*01d0*/ STG.E [R2.64+0x1c], R9 ; /* 0x00001c0902007986 */
/* 0x0021e8000c101908 */
/*01e0*/ STG.E [R2.64+0x20], R11 ; /* 0x0000200b02007986 */
/* 0x0041e8000c101908 */
/*01f0*/ STG.E [R2.64+0x24], R13 ; /* 0x0000240d02007986 */
/* 0x0081e8000c101908 */
/*0200*/ STG.E [R2.64+0x28], R15 ; /* 0x0000280f02007986 */
/* 0x0101e8000c101908 */
/*0210*/ STG.E [R2.64+0x2c], R17 ; /* 0x00002c1102007986 */
/* 0x0201e2000c101908 */
/*0220*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R0, R6, -0x1, RZ ; /* 0xffffffff06007810 */
/* 0x000fe20007ffe0ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0260*/ LOP3.LUT R0, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306007812 */
/* 0x000fd600078ec0ff */
/*0270*/ @!P0 BRA 0x9e0 ; /* 0x0000076000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R4, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fe20007ffe1ff */
/*0290*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*02b0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*02d0*/ @!P0 BRA 0x8b0 ; /* 0x000005d000008947 */
/* 0x000fea0003800000 */
/*02e0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0300*/ @!P1 BRA 0x690 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0320*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0330*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x000e220008201400 */
/*0340*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*0350*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0360*/ UIADD3 UR7, UR4, 0xe, URZ ; /* 0x0000000e04077890 */
/* 0x000fc6000fffe03f */
/*0370*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0380*/ I2F R7, UR5 ; /* 0x0000000500077d06 */
/* 0x000e620008201400 */
/*0390*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fce000fffe03f */
/*03a0*/ I2F R9, UR6 ; /* 0x0000000600097d06 */
/* 0x000ea20008201400 */
/*03b0*/ UIADD3 UR6, UR4, 0x4, URZ ; /* 0x0000000404067890 */
/* 0x000fe2000fffe03f */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011ec000c101908 */
/*03d0*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x000ee20008201400 */
/*03e0*/ UIADD3 UR5, UR4, 0x5, URZ ; /* 0x0000000504057890 */
/* 0x000fe2000fffe03f */
/*03f0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x002fe2000c101908 */
/*0400*/ IADD3 R5, P2, R2, 0x40, RZ ; /* 0x0000004002057810 */
/* 0x001fca0007f5e0ff */
/*0410*/ I2F R13, UR6 ; /* 0x00000006000d7d06 */
/* 0x000e220008201400 */
/*0420*/ UIADD3 UR6, UR4, 0x6, URZ ; /* 0x0000000604067890 */
/* 0x000fe2000fffe03f */
/*0430*/ IADD3.X R12, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0c7210 */
/* 0x000fe200017fe4ff */
/*0440*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x004fea000c101908 */
/*0450*/ I2F R15, UR5 ; /* 0x00000005000f7d06 */
/* 0x000e620008201400 */
/*0460*/ UIADD3 UR5, UR4, 0x7, URZ ; /* 0x0000000704057890 */
/* 0x000fe2000fffe03f */
/*0470*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x008fec000c101908 */
/*0480*/ I2F R17, UR6 ; /* 0x0000000600117d06 */
/* 0x000ea20008201400 */
/*0490*/ UIADD3 UR6, UR4, 0x8, URZ ; /* 0x0000000804067890 */
/* 0x000fe2000fffe03f */
/*04a0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x001fec000c101908 */
/*04b0*/ I2F R19, UR5 ; /* 0x0000000500137d06 */
/* 0x000e220008201400 */
/*04c0*/ UIADD3 UR5, UR4, 0x9, URZ ; /* 0x0000000904057890 */
/* 0x000fe2000fffe03f */
/*04d0*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x002fec000c101908 */
/*04e0*/ I2F R21, UR6 ; /* 0x0000000600157d06 */
/* 0x000e620008201400 */
/*04f0*/ UIADD3 UR6, UR4, 0xa, URZ ; /* 0x0000000a04067890 */
/* 0x000fe2000fffe03f */
/*0500*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x004fec000c101908 */
/*0510*/ I2F R23, UR5 ; /* 0x0000000500177d06 */
/* 0x000ea20008201400 */
/*0520*/ UIADD3 UR5, UR4, 0xb, URZ ; /* 0x0000000b04057890 */
/* 0x000fe2000fffe03f */
/*0530*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x001fec000c101908 */
/*0540*/ I2F R25, UR6 ; /* 0x0000000600197d06 */
/* 0x000e220008201400 */
/*0550*/ UIADD3 UR6, UR4, 0xc, URZ ; /* 0x0000000c04067890 */
/* 0x000fe2000fffe03f */
/*0560*/ STG.E [R2.64+0x20], R21 ; /* 0x0000201502007986 */
/* 0x002fec000c101908 */
/*0570*/ I2F R27, UR5 ; /* 0x00000005001b7d06 */
/* 0x000e620008201400 */
/*0580*/ UIADD3 UR5, UR4, 0xd, URZ ; /* 0x0000000d04057890 */
/* 0x000fe2000fffe03f */
/*0590*/ STG.E [R2.64+0x24], R23 ; /* 0x0000241702007986 */
/* 0x004fec000c101908 */
/*05a0*/ I2F R29, UR6 ; /* 0x00000006001d7d06 */
/* 0x000ea20008201400 */
/*05b0*/ UIADD3 UR6, UR4, 0xf, URZ ; /* 0x0000000f04067890 */
/* 0x000fe2000fffe03f */
/*05c0*/ STG.E [R2.64+0x28], R25 ; /* 0x0000281902007986 */
/* 0x001fe2000c101908 */
/*05d0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fca000fffe03f */
/*05e0*/ I2F R6, UR5 ; /* 0x0000000500067d06 */
/* 0x000e220008201400 */
/*05f0*/ STG.E [R2.64+0x2c], R27 ; /* 0x00002c1b02007986 */
/* 0x002fee000c101908 */
/*0600*/ I2F R8, UR7 ; /* 0x0000000700087d06 */
/* 0x000e620008201400 */
/*0610*/ STG.E [R2.64+0x30], R29 ; /* 0x0000301d02007986 */
/* 0x004fee000c101908 */
/*0620*/ I2F R10, UR6 ; /* 0x00000006000a7d06 */
/* 0x000ea20008201400 */
/*0630*/ STG.E [R2.64+0x34], R6 ; /* 0x0000340602007986 */
/* 0x001fe8000c101908 */
/*0640*/ STG.E [R2.64+0x38], R8 ; /* 0x0000380802007986 */
/* 0x002fe8000c101908 */
/*0650*/ STG.E [R2.64+0x3c], R10 ; /* 0x00003c0a02007986 */
/* 0x0041e4000c101908 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*0670*/ IMAD.MOV.U32 R3, RZ, RZ, R12 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000c */
/*0680*/ @P1 BRA 0x320 ; /* 0xfffffc9000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x890 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*06b0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*06c0*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x000e220008201400 */
/*06d0*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*06e0*/ IADD3 R6, P1, R2, 0x20, RZ ; /* 0x0000002002067810 */
/* 0x000fe20007f3e0ff */
/*06f0*/ UIADD3 UR7, UR4, 0x6, URZ ; /* 0x0000000604077890 */
/* 0x000fe2000fffe03f */
/*0700*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0710*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*0720*/ I2F R7, UR5 ; /* 0x0000000500077d06 */
/* 0x000e620008201400 */
/*0730*/ UIADD3 UR5, UR4, 0x3, URZ ; /* 0x0000000304057890 */
/* 0x000fce000fffe03f */
/*0740*/ I2F R9, UR6 ; /* 0x0000000600097d06 */
/* 0x000ea20008201400 */
/*0750*/ UIADD3 UR6, UR4, 0x4, URZ ; /* 0x0000000404067890 */
/* 0x000fe2000fffe03f */
/*0760*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011ec000c101908 */
/*0770*/ I2F R11, UR5 ; /* 0x00000005000b7d06 */
/* 0x000ee20008201400 */
/*0780*/ UIADD3 UR5, UR4, 0x5, URZ ; /* 0x0000000504057890 */
/* 0x000fe2000fffe03f */
/*0790*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x002fe2000c101908 */
/*07a0*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x001fca00008e0603 */
/*07b0*/ I2F R13, UR6 ; /* 0x00000006000d7d06 */
/* 0x000e220008201400 */
/*07c0*/ UIADD3 UR6, UR4, 0x7, URZ ; /* 0x0000000704067890 */
/* 0x000fe2000fffe03f */
/*07d0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x004fe2000c101908 */
/*07e0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fca000fffe03f */
/*07f0*/ I2F R15, UR5 ; /* 0x00000005000f7d06 */
/* 0x000e620008201400 */
/*0800*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x008fee000c101908 */
/*0810*/ I2F R17, UR7 ; /* 0x0000000700117d06 */
/* 0x000ea20008201400 */
/*0820*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x001fee000c101908 */
/*0830*/ I2F R19, UR6 ; /* 0x0000000600137d06 */
/* 0x000e220008201400 */
/*0840*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x002fe8000c101908 */
/*0850*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x004fe8000c101908 */
/*0860*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x0011e4000c101908 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*0890*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*08a0*/ @!P0 BRA 0x9e0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*08b0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*08c0*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201400 */
/*08d0*/ UIADD3 UR6, UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe03f */
/*08e0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ UIADD3 UR7, UR4, 0x3, URZ ; /* 0x0000000304077890 */
/* 0x000fe2000fffe03f */
/*0900*/ IADD3 R5, P1, R2, 0x10, RZ ; /* 0x0000001002057810 */
/* 0x000fe20007f3e0ff */
/*0910*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0920*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0930*/ I2F R9, UR5 ; /* 0x0000000500097d06 */
/* 0x000e620008201400 */
/*0940*/ IADD3.X R6, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff067210 */
/* 0x000fce0000ffe4ff */
/*0950*/ I2F R11, UR6 ; /* 0x00000006000b7d06 */
/* 0x000ea20008201400 */
/*0960*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fee000c101908 */
/*0970*/ I2F R13, UR7 ; /* 0x00000007000d7d06 */
/* 0x000e220008201400 */
/*0980*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x002fe8000c101908 */
/*0990*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x004fe8000c101908 */
/*09a0*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0011e4000c101908 */
/*09b0*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0005 */
/*09c0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0006 */
/*09d0*/ @P0 BRA 0x8b0 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*09e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*09f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a00*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0a10*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0a20*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fc8000f8e0206 */
/*0a30*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x001e620008201400 */
/*0a40*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x001fe2000f8e00ff */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IMAD.U32 R3, RZ, RZ, UR7 ; /* 0x00000007ff037e24 */
/* 0x000fe2000f8e00ff */
/*0a80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0a90*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc4000fffe03f */
/*0aa0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ab0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0021f2000c101908 */
/*0ac0*/ @P0 BRA 0xa30 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0ad0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected cpyTestDrv_kernel
.globl cpyTestDrv_kernel
.p2align 8
.type cpyTestDrv_kernel,@function
cpyTestDrv_kernel:
s_clause 0x4
s_load_b32 s3, s[0:1], 0x28
s_load_b128 s[8:11], s[0:1], 0x30
s_load_b32 s12, s[0:1], 0x40
s_load_b32 s2, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v7, 0x3ff, v0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, s13
v_dual_mov_b32 v5, s14 :: v_dual_mov_b32 v6, s15
v_bfe_u32 v8, v0, 10, 10
v_bfe_u32 v9, v0, 20, 10
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v14, s3
s_and_b32 s3, s11, 0xffff
v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
s_lshr_b32 s8, s11, 16
s_and_b32 s9, s12, 0xffff
v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s3
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
s_cmp_lt_i32 s2, 1
s_clause 0x3
global_store_b32 v1, v14, s[6:7]
global_store_b128 v1, v[10:13], s[4:5]
global_store_b128 v1, v[2:5], s[4:5] offset:16
global_store_b128 v1, v[6:9], s[4:5] offset:32
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, s3
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, s3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel cpyTestDrv_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size cpyTestDrv_kernel, .Lfunc_end0-cpyTestDrv_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: cpyTestDrv_kernel
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: cpyTestDrv_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000672c_00000000-6_cpyTestDrv_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j
.type _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j, @function
_Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq cpyTestDrv_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j, .-_Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j
.globl cpyTestDrv_kernel
.type cpyTestDrv_kernel, @function
cpyTestDrv_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z17cpyTestDrv_kernelPfS_iPjS0_jPfS_iPjS0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size cpyTestDrv_kernel, .-cpyTestDrv_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cpyTestDrv_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cpyTestDrv_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cpyTestDrv_kernel.hip"
.globl __device_stub__cpyTestDrv_kernel # -- Begin function __device_stub__cpyTestDrv_kernel
.p2align 4, 0x90
.type __device_stub__cpyTestDrv_kernel,@function
__device_stub__cpyTestDrv_kernel: # @__device_stub__cpyTestDrv_kernel
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $cpyTestDrv_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__cpyTestDrv_kernel, .Lfunc_end0-__device_stub__cpyTestDrv_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cpyTestDrv_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cpyTestDrv_kernel,@object # @cpyTestDrv_kernel
.section .rodata,"a",@progbits
.globl cpyTestDrv_kernel
.p2align 3, 0x0
cpyTestDrv_kernel:
.quad __device_stub__cpyTestDrv_kernel
.size cpyTestDrv_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cpyTestDrv_kernel"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cpyTestDrv_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cpyTestDrv_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<cstring>
#include<cstdlib>
#define GMM_MAX_COMPONT 3
#define GMM_LEARN_ALPHA 0.005
#define GMM_THRESHOD_SUMW 0.7
#define HEIGHT 1080
#define WIDTH 1920
using namespace std;
__global__ void trainGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
int num_fit = 0;
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[0] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[0];
modelSData[k] = 15.0;
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[0];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
}
__global__ void testGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
unsigned char *maskData = mask + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[0] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[0] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[0] = 255;
break;
}
}
}
void trainGMM(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
/**************************** Train ******************************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
for (int j = 0; j < width; j++)
{
int num_fit = 0;
/**************************** Update parameters Start ******************************************/
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[j] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
/**************************** Update parameters End ******************************************/
/*********************** Sort Gaussian component by 'weight / sigma' Start ****************************/
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
/*********************** Sort Gaussian model by 'weight / sigma' End ****************************/
/*********************** Create new Gaussian component Start ****************************/
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
//if there is no exit component fit,then start a new component
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[j];
modelSData[k] = 15.0;
//normalization the weight,let they sum to 1
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
/****update the other unfit's weight,u and sigma remain unchanged****/
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[j];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
/*********************** Create new Gaussian component End ****************************/
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
void testGMM(unsigned char* _image, unsigned char* mask, float* modelW, float* modelS, unsigned char* modelM, int height, int width)
{
/*********************** Predict ****************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
unsigned char *maskData = mask + i * width;
for (int j = 0; j < width; j++)
{
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[j] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[j] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[j] = 255;
break;
}
}
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
int main()
{
float *modelW = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
float *modelS = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
unsigned char *modelM = new unsigned char[HEIGHT * GMM_MAX_COMPONT * WIDTH];;
unsigned char *frame = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask2 = new unsigned char[HEIGHT * WIDTH];
int height = HEIGHT;
int width = WIDTH;
memset(modelW, 0, sizeof(modelW));
memset(modelS, 0, sizeof(modelM));
memset(modelM, 0, sizeof(modelS));
memset(mask, 0, sizeof(mask));
// For GPU
float *dev_modelW, *dev_modelS;
unsigned char *dev_frame, *dev_mask, *dev_modelM;
cudaMalloc((void**)&dev_modelW, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
cudaMalloc((void**)&dev_modelS, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
cudaMalloc((void**)&dev_modelM, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(unsigned char));
cudaMalloc((void**)&dev_frame, (HEIGHT * WIDTH) * sizeof(unsigned char));
cudaMalloc((void**)&dev_mask, (HEIGHT * WIDTH) * sizeof(unsigned char));
cudaMemcpy(dev_modelW,
modelW,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(dev_modelS,
modelS,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(dev_modelM,
modelM,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(unsigned char),
cudaMemcpyHostToDevice);
dim3 block(32,8);
dim3 grid((HEIGHT + block.x - 1) / block.x,
(WIDTH + block.y - 1) / block.y);
clock_t start, end;
clock_t start2, end2;
double sum_t = 0;
double sum_t2 = 0;
srand(unsigned(time(0)));
int frame_num = 100;
for (int t = 0; t < frame_num; t++)
{
for (int i = 0; i < height; i++)
for (int j = 0; j < width; j++)
*(frame + i * width + j) = rand() % 255;
start = clock();
trainGMM(frame, mask, modelW, modelS, modelM, height, width);
testGMM(frame, mask, modelW, modelS, modelM, height, width);
end = clock();
sum_t += end - start;
start2 = clock();
cudaMemcpy(dev_frame,
frame,
HEIGHT * WIDTH * sizeof(unsigned char),
cudaMemcpyHostToDevice);
trainGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
testGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
cudaMemcpy(mask2,
dev_mask,
HEIGHT * WIDTH * sizeof(unsigned char),
cudaMemcpyDeviceToHost);
end2 = clock();
sum_t2 += end2 - start2;
// TEST
/*
int diff_count = 0;
for (int i = 0; i < height * width; i++)
if (mask[i] != mask2[i])
diff_count++;
cout <<"Diff: " << diff_count << endl;
*/
}
cout <<"CPU: " << (sum_t / frame_num) / CLOCKS_PER_SEC << endl;
cout <<"GPU: " << (sum_t2 / frame_num) / CLOCKS_PER_SEC << endl;
} | .file "tmpxft_000aa471_00000000-6_gmm_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8trainGMMPhS_PfS0_S_ii
.type _Z8trainGMMPhS_PfS0_S_ii, @function
_Z8trainGMMPhS_PfS0_S_ii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -32(%rsp)
movl %r9d, -20(%rsp)
movl 56(%rsp), %ebx
testl %r9d, %r9d
jle .L3
movq %rcx, %rsi
movslq %ebx, %r15
leal (%rbx,%rbx,2), %eax
movslq %eax, %r13
leaq 0(,%r13,4), %rax
movq %rdx, %rcx
movq %rsi, %r11
movq %r8, %rbp
movl $0, %edi
movl $0, %r9d
movsd .LC0(%rip), %xmm5
movsd .LC2(%rip), %xmm8
movss .LC1(%rip), %xmm7
movapd %xmm8, %xmm4
movl %r9d, %r8d
movq %rdi, %rsi
movq %r15, -16(%rsp)
movq %r13, -8(%rsp)
movl %ebx, %r12d
movq %r11, %rbx
jmp .L26
.L36:
movss (%rdi,%rax,4), %xmm1
movaps %xmm6, %xmm0
subss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm8, %xmm0
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdi,%rax,4)
addl $1, %r10d
.L9:
addq $1, %rax
cmpq $3, %rax
je .L40
.L10:
movzbl (%r11), %ecx
movzbl (%r9,%rax), %esi
subl %esi, %ecx
movl %ecx, %esi
imull %ecx, %esi
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
mulsd %xmm5, %xmm0
comisd %xmm1, %xmm0
jbe .L36
movss (%rdi,%rax,4), %xmm1
movaps %xmm7, %xmm0
subss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm4, %xmm0
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdi,%rax,4)
movl %ecx, %r8d
negl %r8d
cmovns %r8d, %ecx
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
cvtss2sd %xmm0, %xmm0
movapd %xmm4, %xmm2
divsd %xmm0, %xmm2
mulsd %xmm2, %xmm1
movapd %xmm1, %xmm0
movzbl (%r9,%rax), %ecx
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
addsd %xmm1, %xmm0
cvttsd2sil %xmm0, %ecx
movb %cl, (%r9,%rax)
movss (%rdx,%rax,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%rdi,%rax,4), %xmm1
movapd %xmm4, %xmm0
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
subss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
mulsd %xmm1, %xmm0
cvtss2sd %xmm2, %xmm2
addsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdx,%rax,4)
jmp .L9
.L40:
movq %rdi, -64(%rsp)
movq %rdx, %rcx
movq %r9, %r8
movq %rdi, %rsi
movl $0, %ebx
movl %r10d, -68(%rsp)
jmp .L11
.L12:
addq $1, %rax
cmpl $2, %eax
jg .L41
.L14:
movss (%rdi,%rax,4), %xmm0
movss (%rsi), %xmm1
movaps %xmm0, %xmm3
divss (%rdx,%rax,4), %xmm3
movaps %xmm1, %xmm2
divss (%rcx), %xmm2
comiss %xmm2, %xmm3
jbe .L12
movss %xmm1, (%rdi,%rax,4)
movss %xmm0, (%rsi)
movzbl (%r9,%rax), %r10d
movzbl (%r8), %r11d
movb %r11b, (%r9,%rax)
movb %r10b, (%r8)
movss (%rdx,%rax,4), %xmm0
movss (%rcx), %xmm1
movss %xmm1, (%rdx,%rax,4)
movss %xmm0, (%rcx)
jmp .L12
.L41:
movq -80(%rsp), %r11
addq $1, %rbx
addq $4, %rsi
addq $4, %rcx
addq $1, %r8
cmpq $3, %rbx
je .L15
.L11:
movq %rbx, %rax
movq %r11, -80(%rsp)
jmp .L14
.L15:
movl -68(%rsp), %r10d
cmpl $3, %r10d
je .L42
.L16:
addq $12, %rdi
addq $12, %rdx
addq $3, %r9
addq $1, %r11
cmpq %r13, %rdi
je .L38
.L6:
movl $0, %eax
movl $0, %r10d
movq %r11, %r14
jmp .L10
.L42:
ucomiss 8(%rdi), %xmm6
jp .L17
je .L43
.L17:
movzbl (%r14), %eax
movb %al, 2(%r9)
movss %xmm9, 8(%rdx)
jmp .L16
.L43:
pxor %xmm0, %xmm0
ucomiss (%rdi), %xmm0
jp .L30
je .L19
.L30:
pxor %xmm0, %xmm0
ucomiss 4(%rdi), %xmm0
jp .L31
je .L21
.L31:
movq -64(%rsp), %rax
addq $8, %rax
movl $2, %esi
movl $8, %r8d
movl $2, %ecx
.L23:
movl $0x3ba3d70a, (%rax)
movzbl (%r14), %eax
movb %al, (%r9,%rcx)
movl $0x41700000, (%rdx,%r8)
movl $1, %eax
movsd .LC4(%rip), %xmm1
.L24:
pxor %xmm0, %xmm0
cvtss2sd -4(%rdi,%rax,4), %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%rdi,%rax,4)
movl %eax, %ecx
addq $1, %rax
cmpl $2, %ecx
jg .L16
cmpl %esi, %ecx
jne .L24
jmp .L16
.L38:
movl -24(%rsp), %r8d
movq -56(%rsp), %rsi
movq -48(%rsp), %rcx
movq -40(%rsp), %rax
movq %r15, %rbx
.L5:
addl $1, %r8d
movq -16(%rsp), %rdi
addq %rdi, %rsi
addq %rax, %rcx
addq %rax, %rbx
movq -8(%rsp), %rdi
addq %rdi, %rbp
cmpl %r8d, -20(%rsp)
je .L3
.L26:
movq %rcx, %rdi
movq %rbx, %rdx
movq %rbp, %r9
testl %r12d, %r12d
jle .L5
movq -32(%rsp), %r15
leaq (%r15,%rsi), %r11
leaq (%rcx,%rax), %r13
pxor %xmm6, %xmm6
movss .LC5(%rip), %xmm9
movl %r8d, -24(%rsp)
movq %rsi, -56(%rsp)
movq %rcx, -48(%rsp)
movq %rax, -40(%rsp)
movq %rbx, %r15
jmp .L6
.L21:
movq -64(%rsp), %rax
addq $4, %rax
movl $1, %esi
movl $4, %r8d
movl $1, %ecx
jmp .L23
.L19:
movl $0x3f800000, (%rdi)
movzbl (%r14), %eax
movb %al, (%r9)
movl $0x41700000, (%rdx)
jmp .L16
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z8trainGMMPhS_PfS0_S_ii, .-_Z8trainGMMPhS_PfS0_S_ii
.globl _Z7testGMMPhS_PfS0_S_ii
.type _Z7testGMMPhS_PfS0_S_ii, @function
_Z7testGMMPhS_PfS0_S_ii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %r9d, -4(%rsp)
testl %r9d, %r9d
jle .L44
movq %rdi, %r11
movq %rsi, %r12
movq %rdx, %rbp
movq %rcx, %r10
movslq 56(%rsp), %rbx
movl 56(%rsp), %eax
leal (%rax,%rax,2), %eax
movslq %eax, %r15
leaq 0(,%r15,4), %rcx
movq %r8, %rdx
movl $0, %r13d
movsd .LC7(%rip), %xmm2
movsd .LC8(%rip), %xmm3
jmp .L53
.L63:
movq -24(%rsp), %r14
movb $0, (%rdx,%r14)
.L49:
addq $12, %r9
addq $12, %r8
addq $3, %rdi
addq $1, %r14
cmpq %rbx, %r14
je .L61
.L46:
movzbl (%r11,%r14), %r13d
movl $0, %eax
pxor %xmm1, %xmm1
movq %r14, -24(%rsp)
.L52:
movzbl (%rdi,%rax), %r14d
movl %r13d, %esi
subl %r14d, %esi
movl %esi, %r14d
negl %r14d
cmovs %esi, %r14d
pxor %xmm0, %xmm0
cvtss2sd (%r8,%rax,4), %xmm0
mulsd %xmm2, %xmm0
cvttsd2sil %xmm0, %esi
movzbl %sil, %esi
cmpl %esi, %r14d
jl .L63
addss (%r9,%rax,4), %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
comisd %xmm3, %xmm0
jnb .L64
addq $1, %rax
cmpq $3, %rax
jne .L52
movq -24(%rsp), %r14
jmp .L49
.L64:
movq -24(%rsp), %r14
movb $-1, (%rdx,%r14)
jmp .L49
.L61:
movl -8(%rsp), %r13d
movq -16(%rsp), %rdx
.L47:
addl $1, %r13d
addq %rbx, %r12
addq %rcx, %rbp
addq %rcx, %r10
addq %r15, %rdx
addq %rbx, %r11
cmpl %r13d, -4(%rsp)
je .L44
.L53:
movq %rbp, %r9
movq %r10, %r8
movq %rdx, %rdi
movl $0, %r14d
cmpl $0, 56(%rsp)
jle .L47
movl %r13d, -8(%rsp)
movq %rdx, -16(%rsp)
movq %r12, %rdx
jmp .L46
.L44:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z7testGMMPhS_PfS0_S_ii, .-_Z7testGMMPhS_PfS0_S_ii
.globl _Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
.type _Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii, @function
_Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L69
.L65:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13trainGMM_CUDAPhS_PfS0_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L65
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii, .-_Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
.globl _Z13trainGMM_CUDAPhS_PfS0_S_ii
.type _Z13trainGMM_CUDAPhS_PfS0_S_ii, @function
_Z13trainGMM_CUDAPhS_PfS0_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z13trainGMM_CUDAPhS_PfS0_S_ii, .-_Z13trainGMM_CUDAPhS_PfS0_S_ii
.globl _Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
.type _Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii, @function
_Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L77
.L73:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12testGMM_CUDAPhS_PfS0_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L73
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii, .-_Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
.globl _Z12testGMM_CUDAPhS_PfS0_S_ii
.type _Z12testGMM_CUDAPhS_PfS0_S_ii, @function
_Z12testGMM_CUDAPhS_PfS0_S_ii:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12testGMM_CUDAPhS_PfS0_S_ii, .-_Z12testGMM_CUDAPhS_PfS0_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "CPU: "
.LC13:
.string "GPU: "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $24883200, %edi
call _Znam@PLT
movq %rax, %r15
movl $24883200, %edi
call _Znam@PLT
movq %rax, %r14
movl $6220800, %edi
call _Znam@PLT
movq %rax, %rbx
movl $2073600, %edi
call _Znam@PLT
movq %rax, %r13
movl $2073600, %edi
call _Znam@PLT
movq %rax, 16(%rsp)
movl $2073600, %edi
call _Znam@PLT
movq %rax, 32(%rsp)
movq $0, (%r15)
movq $0, (%r14)
movq $0, (%rbx)
leaq 56(%rsp), %rdi
movl $24883200, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $24883200, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $6220800, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $2073600, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $2073600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $24883200, %edx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $24883200, %edx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $6220800, %edx
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 104(%rsp)
movl $34, 108(%rsp)
movl $240, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $100, 28(%rsp)
movq $0x000000000, 8(%rsp)
movq $0x000000000, (%rsp)
leaq 2075520(%r13), %r12
movq %r15, %rbp
jmp .L82
.L92:
addq $1920, %r15
cmpq %r12, %r15
je .L84
.L88:
leaq -1920(%r15), %rbp
.L83:
call rand@PLT
movl %eax, %edx
cltq
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
movl %eax, %ecx
sall $8, %ecx
subl %eax, %ecx
subl %ecx, %edx
movb %dl, 0(%rbp)
addq $1, %rbp
cmpq %r15, %rbp
jne .L83
jmp .L92
.L84:
movq 40(%rsp), %rbp
call clock@PLT
movq %rax, %r15
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq $1920
.cfi_def_cfa_offset 208
movl $1080, %r9d
movq %rbx, %r8
movq %r14, %rcx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r13, %rdi
call _Z8trainGMMPhS_PfS0_S_ii
movl $1920, (%rsp)
movl $1080, %r9d
movq %rbx, %r8
movq %r14, %rcx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r13, %rdi
call _Z7testGMMPhS_PfS0_S_ii
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
call clock@PLT
movq %rax, %r15
addq $16, %rsp
.cfi_def_cfa_offset 192
movl $1, %ecx
movl $2073600, %edx
movq %r13, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 96(%rsp)
movl $8, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L85:
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L86:
movl $2, %ecx
movl $2073600, %edx
movq 80(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
subl $1, 28(%rsp)
je .L87
.L82:
leaq 1920(%r13), %r15
movq %rbp, 40(%rsp)
jmp .L88
.L93:
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq $1920
.cfi_def_cfa_offset 208
movl $1080, %r9d
movq 104(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z44__device_stub__Z13trainGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L85
.L94:
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq $1920
.cfi_def_cfa_offset 208
movl $1080, %r9d
movq 104(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z43__device_stub__Z12testGMM_CUDAPhS_PfS0_S_iiPhS_PfS0_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L86
.L87:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%rsp), %xmm0
divsd .LC11(%rip), %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L95
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12testGMM_CUDAPhS_PfS0_S_ii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC15:
.string "_Z13trainGMM_CUDAPhS_PfS0_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12testGMM_CUDAPhS_PfS0_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z13trainGMM_CUDAPhS_PfS0_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074266112
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8
.align 8
.LC2:
.long 1202590843
.long 1064598241
.align 8
.LC4:
.long 1030792151
.long 1072682762
.section .rodata.cst4
.align 4
.LC5:
.long 1097859072
.section .rodata.cst8
.align 8
.LC7:
.long 0
.long 1074003968
.align 8
.LC8:
.long 1717986918
.long 1072064102
.align 8
.LC11:
.long 0
.long 1079574528
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<cstring>
#include<cstdlib>
#define GMM_MAX_COMPONT 3
#define GMM_LEARN_ALPHA 0.005
#define GMM_THRESHOD_SUMW 0.7
#define HEIGHT 1080
#define WIDTH 1920
using namespace std;
__global__ void trainGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
int num_fit = 0;
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[0] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[0];
modelSData[k] = 15.0;
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[0];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
}
__global__ void testGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
unsigned char *maskData = mask + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[0] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[0] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[0] = 255;
break;
}
}
}
void trainGMM(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
/**************************** Train ******************************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
for (int j = 0; j < width; j++)
{
int num_fit = 0;
/**************************** Update parameters Start ******************************************/
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[j] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
/**************************** Update parameters End ******************************************/
/*********************** Sort Gaussian component by 'weight / sigma' Start ****************************/
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
/*********************** Sort Gaussian model by 'weight / sigma' End ****************************/
/*********************** Create new Gaussian component Start ****************************/
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
//if there is no exit component fit,then start a new component
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[j];
modelSData[k] = 15.0;
//normalization the weight,let they sum to 1
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
/****update the other unfit's weight,u and sigma remain unchanged****/
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[j];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
/*********************** Create new Gaussian component End ****************************/
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
void testGMM(unsigned char* _image, unsigned char* mask, float* modelW, float* modelS, unsigned char* modelM, int height, int width)
{
/*********************** Predict ****************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
unsigned char *maskData = mask + i * width;
for (int j = 0; j < width; j++)
{
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[j] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[j] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[j] = 255;
break;
}
}
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
int main()
{
float *modelW = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
float *modelS = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
unsigned char *modelM = new unsigned char[HEIGHT * GMM_MAX_COMPONT * WIDTH];;
unsigned char *frame = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask2 = new unsigned char[HEIGHT * WIDTH];
int height = HEIGHT;
int width = WIDTH;
memset(modelW, 0, sizeof(modelW));
memset(modelS, 0, sizeof(modelM));
memset(modelM, 0, sizeof(modelS));
memset(mask, 0, sizeof(mask));
// For GPU
float *dev_modelW, *dev_modelS;
unsigned char *dev_frame, *dev_mask, *dev_modelM;
cudaMalloc((void**)&dev_modelW, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
cudaMalloc((void**)&dev_modelS, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
cudaMalloc((void**)&dev_modelM, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(unsigned char));
cudaMalloc((void**)&dev_frame, (HEIGHT * WIDTH) * sizeof(unsigned char));
cudaMalloc((void**)&dev_mask, (HEIGHT * WIDTH) * sizeof(unsigned char));
cudaMemcpy(dev_modelW,
modelW,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(dev_modelS,
modelS,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(dev_modelM,
modelM,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(unsigned char),
cudaMemcpyHostToDevice);
dim3 block(32,8);
dim3 grid((HEIGHT + block.x - 1) / block.x,
(WIDTH + block.y - 1) / block.y);
clock_t start, end;
clock_t start2, end2;
double sum_t = 0;
double sum_t2 = 0;
srand(unsigned(time(0)));
int frame_num = 100;
for (int t = 0; t < frame_num; t++)
{
for (int i = 0; i < height; i++)
for (int j = 0; j < width; j++)
*(frame + i * width + j) = rand() % 255;
start = clock();
trainGMM(frame, mask, modelW, modelS, modelM, height, width);
testGMM(frame, mask, modelW, modelS, modelM, height, width);
end = clock();
sum_t += end - start;
start2 = clock();
cudaMemcpy(dev_frame,
frame,
HEIGHT * WIDTH * sizeof(unsigned char),
cudaMemcpyHostToDevice);
trainGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
testGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
cudaMemcpy(mask2,
dev_mask,
HEIGHT * WIDTH * sizeof(unsigned char),
cudaMemcpyDeviceToHost);
end2 = clock();
sum_t2 += end2 - start2;
// TEST
/*
int diff_count = 0;
for (int i = 0; i < height * width; i++)
if (mask[i] != mask2[i])
diff_count++;
cout <<"Diff: " << diff_count << endl;
*/
}
cout <<"CPU: " << (sum_t / frame_num) / CLOCKS_PER_SEC << endl;
cout <<"GPU: " << (sum_t2 / frame_num) / CLOCKS_PER_SEC << endl;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstring>
#include<cstdlib>
#define GMM_MAX_COMPONT 3
#define GMM_LEARN_ALPHA 0.005
#define GMM_THRESHOD_SUMW 0.7
#define HEIGHT 1080
#define WIDTH 1920
using namespace std;
__global__ void trainGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
int num_fit = 0;
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[0] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[0];
modelSData[k] = 15.0;
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[0];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
}
__global__ void testGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
unsigned char *maskData = mask + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[0] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[0] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[0] = 255;
break;
}
}
}
void trainGMM(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
/**************************** Train ******************************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
for (int j = 0; j < width; j++)
{
int num_fit = 0;
/**************************** Update parameters Start ******************************************/
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[j] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
/**************************** Update parameters End ******************************************/
/*********************** Sort Gaussian component by 'weight / sigma' Start ****************************/
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
/*********************** Sort Gaussian model by 'weight / sigma' End ****************************/
/*********************** Create new Gaussian component Start ****************************/
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
//if there is no exit component fit,then start a new component
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[j];
modelSData[k] = 15.0;
//normalization the weight,let they sum to 1
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
/****update the other unfit's weight,u and sigma remain unchanged****/
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[j];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
/*********************** Create new Gaussian component End ****************************/
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
void testGMM(unsigned char* _image, unsigned char* mask, float* modelW, float* modelS, unsigned char* modelM, int height, int width)
{
/*********************** Predict ****************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
unsigned char *maskData = mask + i * width;
for (int j = 0; j < width; j++)
{
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[j] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[j] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[j] = 255;
break;
}
}
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
int main()
{
float *modelW = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
float *modelS = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
unsigned char *modelM = new unsigned char[HEIGHT * GMM_MAX_COMPONT * WIDTH];;
unsigned char *frame = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask2 = new unsigned char[HEIGHT * WIDTH];
int height = HEIGHT;
int width = WIDTH;
memset(modelW, 0, sizeof(modelW));
memset(modelS, 0, sizeof(modelM));
memset(modelM, 0, sizeof(modelS));
memset(mask, 0, sizeof(mask));
// For GPU
float *dev_modelW, *dev_modelS;
unsigned char *dev_frame, *dev_mask, *dev_modelM;
hipMalloc((void**)&dev_modelW, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
hipMalloc((void**)&dev_modelS, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
hipMalloc((void**)&dev_modelM, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(unsigned char));
hipMalloc((void**)&dev_frame, (HEIGHT * WIDTH) * sizeof(unsigned char));
hipMalloc((void**)&dev_mask, (HEIGHT * WIDTH) * sizeof(unsigned char));
hipMemcpy(dev_modelW,
modelW,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(dev_modelS,
modelS,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(dev_modelM,
modelM,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(unsigned char),
hipMemcpyHostToDevice);
dim3 block(32,8);
dim3 grid((HEIGHT + block.x - 1) / block.x,
(WIDTH + block.y - 1) / block.y);
clock_t start, end;
clock_t start2, end2;
double sum_t = 0;
double sum_t2 = 0;
srand(unsigned(time(0)));
int frame_num = 100;
for (int t = 0; t < frame_num; t++)
{
for (int i = 0; i < height; i++)
for (int j = 0; j < width; j++)
*(frame + i * width + j) = rand() % 255;
start = clock();
trainGMM(frame, mask, modelW, modelS, modelM, height, width);
testGMM(frame, mask, modelW, modelS, modelM, height, width);
end = clock();
sum_t += end - start;
start2 = clock();
hipMemcpy(dev_frame,
frame,
HEIGHT * WIDTH * sizeof(unsigned char),
hipMemcpyHostToDevice);
trainGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
testGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
hipMemcpy(mask2,
dev_mask,
HEIGHT * WIDTH * sizeof(unsigned char),
hipMemcpyDeviceToHost);
end2 = clock();
sum_t2 += end2 - start2;
// TEST
/*
int diff_count = 0;
for (int i = 0; i < height * width; i++)
if (mask[i] != mask2[i])
diff_count++;
cout <<"Diff: " << diff_count << endl;
*/
}
cout <<"CPU: " << (sum_t / frame_num) / CLOCKS_PER_SEC << endl;
cout <<"GPU: " << (sum_t2 / frame_num) / CLOCKS_PER_SEC << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstring>
#include<cstdlib>
#define GMM_MAX_COMPONT 3
#define GMM_LEARN_ALPHA 0.005
#define GMM_THRESHOD_SUMW 0.7
#define HEIGHT 1080
#define WIDTH 1920
using namespace std;
__global__ void trainGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
int num_fit = 0;
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[0] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[0];
modelSData[k] = 15.0;
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[0];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
}
__global__ void testGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
unsigned char *maskData = mask + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[0] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[0] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[0] = 255;
break;
}
}
}
void trainGMM(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
/**************************** Train ******************************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
for (int j = 0; j < width; j++)
{
int num_fit = 0;
/**************************** Update parameters Start ******************************************/
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[j] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
/**************************** Update parameters End ******************************************/
/*********************** Sort Gaussian component by 'weight / sigma' Start ****************************/
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
/*********************** Sort Gaussian model by 'weight / sigma' End ****************************/
/*********************** Create new Gaussian component Start ****************************/
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
//if there is no exit component fit,then start a new component
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[j];
modelSData[k] = 15.0;
//normalization the weight,let they sum to 1
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
/****update the other unfit's weight,u and sigma remain unchanged****/
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[j];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
/*********************** Create new Gaussian component End ****************************/
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
void testGMM(unsigned char* _image, unsigned char* mask, float* modelW, float* modelS, unsigned char* modelM, int height, int width)
{
/*********************** Predict ****************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
unsigned char *maskData = mask + i * width;
for (int j = 0; j < width; j++)
{
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[j] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[j] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[j] = 255;
break;
}
}
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
int main()
{
float *modelW = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
float *modelS = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
unsigned char *modelM = new unsigned char[HEIGHT * GMM_MAX_COMPONT * WIDTH];;
unsigned char *frame = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask2 = new unsigned char[HEIGHT * WIDTH];
int height = HEIGHT;
int width = WIDTH;
memset(modelW, 0, sizeof(modelW));
memset(modelS, 0, sizeof(modelM));
memset(modelM, 0, sizeof(modelS));
memset(mask, 0, sizeof(mask));
// For GPU
float *dev_modelW, *dev_modelS;
unsigned char *dev_frame, *dev_mask, *dev_modelM;
hipMalloc((void**)&dev_modelW, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
hipMalloc((void**)&dev_modelS, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
hipMalloc((void**)&dev_modelM, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(unsigned char));
hipMalloc((void**)&dev_frame, (HEIGHT * WIDTH) * sizeof(unsigned char));
hipMalloc((void**)&dev_mask, (HEIGHT * WIDTH) * sizeof(unsigned char));
hipMemcpy(dev_modelW,
modelW,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(dev_modelS,
modelS,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(dev_modelM,
modelM,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(unsigned char),
hipMemcpyHostToDevice);
dim3 block(32,8);
dim3 grid((HEIGHT + block.x - 1) / block.x,
(WIDTH + block.y - 1) / block.y);
clock_t start, end;
clock_t start2, end2;
double sum_t = 0;
double sum_t2 = 0;
srand(unsigned(time(0)));
int frame_num = 100;
for (int t = 0; t < frame_num; t++)
{
for (int i = 0; i < height; i++)
for (int j = 0; j < width; j++)
*(frame + i * width + j) = rand() % 255;
start = clock();
trainGMM(frame, mask, modelW, modelS, modelM, height, width);
testGMM(frame, mask, modelW, modelS, modelM, height, width);
end = clock();
sum_t += end - start;
start2 = clock();
hipMemcpy(dev_frame,
frame,
HEIGHT * WIDTH * sizeof(unsigned char),
hipMemcpyHostToDevice);
trainGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
testGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
hipMemcpy(mask2,
dev_mask,
HEIGHT * WIDTH * sizeof(unsigned char),
hipMemcpyDeviceToHost);
end2 = clock();
sum_t2 += end2 - start2;
// TEST
/*
int diff_count = 0;
for (int i = 0; i < height * width; i++)
if (mask[i] != mask2[i])
diff_count++;
cout <<"Diff: " << diff_count << endl;
*/
}
cout <<"CPU: " << (sum_t / frame_num) / CLOCKS_PER_SEC << endl;
cout <<"GPU: " << (sum_t2 / frame_num) / CLOCKS_PER_SEC << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13trainGMM_CUDAPhS_PfS0_S_ii
.globl _Z13trainGMM_CUDAPhS_PfS0_S_ii
.p2align 8
.type _Z13trainGMM_CUDAPhS_PfS0_S_ii,@function
_Z13trainGMM_CUDAPhS_PfS0_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_27
v_mul_lo_u32 v1, v2, s3
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b128 s[0:3], s[0:1], 0x10
v_ashrrev_i32_e32 v5, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v1, v0
v_ashrrev_i32_e32 v4, 31, v1
v_lshl_add_u32 v2, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v1, v0
v_add_co_ci_u32_e32 v5, vcc_lo, v8, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_dual_mov_b32 v22, 0 :: v_dual_mov_b32 v9, v3
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_mov_b32_e32 v8, v2
s_mov_b64 s[0:1], 0
s_mov_b32 s3, 0x3f747ae1
s_mov_b32 s2, 0x47ae147b
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v8, vcc_lo, v8, 1
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 12
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_add_co_u32 v10, vcc_lo, v6, s0
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v12, v[10:11], off
global_load_u8 v13, v[4:5], off
global_load_u8 v16, v[8:9], off
s_waitcnt vmcnt(2)
v_cvt_f64_f32_e32 v[14:15], v12
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v13, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v12, v13, v13
v_cvt_f64_u32_e32 v[16:17], v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[14:15], 0x40080000
v_cmpx_ngt_f64_e32 v[14:15], v[16:17]
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_5
v_add_co_u32 v10, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v1, vcc_lo
v_add_nc_u32_e32 v22, 1, v22
global_load_b32 v14, v[10:11], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e64 v[12:13], -v14
v_cvt_f64_f32_e32 v[14:15], v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], s[2:3], v[14:15]
v_cvt_f32_f64_e32 v12, v[12:13]
global_store_b32 v[10:11], v12, off
.LBB0_5:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_2
v_add_co_u32 v14, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v1, vcc_lo
v_cvt_f32_u32_e32 v12, v12
global_load_b32 v16, v[14:15], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v18, 1.0, v16
v_cvt_f64_f32_e32 v[16:17], v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[18:19], v18
v_fma_f64 v[16:17], v[18:19], s[2:3], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v20, v[16:17]
v_cvt_f64_f32_e32 v[16:17], v20
global_store_b32 v[14:15], v20, off
global_load_u8 v27, v[8:9], off
v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], s[2:3]
v_div_scale_f64 v[25:26], vcc_lo, s[2:3], v[16:17], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[20:21], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[23:24], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[23:24], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[23:24], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[23:24], v[25:26], v[20:21]
v_fma_f64 v[18:19], -v[18:19], v[23:24], v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[23:24]
v_sub_nc_u32_e32 v20, 0, v13
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[23:24], v27
v_max_i32_e32 v13, v13, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[20:21], v13
v_div_fixup_f64 v[16:17], v[18:19], v[16:17], s[2:3]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[23:24]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v13, v[16:17]
global_store_b8 v[8:9], v13, off
global_load_b32 v13, v[14:15], off
global_load_b32 v21, v[10:11], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[13:14], v13
s_waitcnt vmcnt(0)
v_sub_f32_e32 v12, v12, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[15:16], null, v[13:14], v[13:14], s[2:3]
v_div_scale_f64 v[23:24], vcc_lo, s[2:3], v[13:14], s[2:3]
v_rcp_f64_e32 v[17:18], v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
v_mul_f64 v[19:20], v[23:24], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[15:16], v[19:20], v[23:24]
v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
v_cvt_f64_f32_e32 v[17:18], v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[12:13], v[15:16], v[13:14], s[2:3]
v_cvt_f64_f32_e32 v[14:15], v21
v_fma_f64 v[12:13], v[12:13], v[17:18], v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v12, v[12:13]
global_store_b32 v[10:11], v12, off
s_branch .LBB0_2
.LBB0_7:
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
s_mov_b64 s[2:3], 0
s_mov_b32 s1, 0
s_branch .LBB0_9
.LBB0_8:
v_add_co_u32 v10, vcc_lo, v10, 4
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 3
s_cbranch_scc1 .LBB0_13
.LBB0_9:
s_mov_b32 s0, s2
v_dual_mov_b32 v19, v9 :: v_dual_mov_b32 v18, v8
s_lshl_b64 s[4:5], s[0:1], 2
v_dual_mov_b32 v21, v11 :: v_dual_mov_b32 v20, v10
v_add_co_u32 v12, vcc_lo, v0, s4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, v6, s4
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v16, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v17, vcc_lo, 0, v3, vcc_lo
s_mov_b64 s[4:5], s[2:3]
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v20, vcc_lo, v20, 4
v_add_co_ci_u32_e32 v21, vcc_lo, 0, v21, vcc_lo
v_add_co_u32 v18, vcc_lo, v18, 4
s_add_u32 s4, s4, 1
v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
s_addc_u32 s5, s5, 0
s_add_i32 s0, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s0, 1
s_cbranch_scc1 .LBB0_8
.LBB0_11:
global_load_b32 v23, v[20:21], off
global_load_b32 v25, v[18:19], off
global_load_b32 v24, v[12:13], off
global_load_b32 v26, v[14:15], off
s_waitcnt vmcnt(2)
v_div_scale_f32 v27, null, v25, v25, v23
s_waitcnt vmcnt(0)
v_div_scale_f32 v28, null, v26, v26, v24
v_div_scale_f32 v33, vcc_lo, v23, v25, v23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v29, v27
v_rcp_f32_e32 v30, v28
s_waitcnt_depctr 0xfff
v_fma_f32 v31, -v27, v29, 1.0
v_fma_f32 v32, -v28, v30, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v29, v31, v29 :: v_dual_fmac_f32 v30, v32, v30
v_div_scale_f32 v31, s0, v24, v26, v24
v_mul_f32_e32 v32, v33, v29
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v34, v31, v30
v_fma_f32 v35, -v27, v32, v33
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v36, -v28, v34, v31
v_fmac_f32_e32 v32, v35, v29
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v34, v36, v30
v_fma_f32 v27, -v27, v32, v33
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v28, -v28, v34, v31
v_div_fmas_f32 v27, v27, v29, v32
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v28, v28, v30, v34
v_div_fixup_f32 v25, v27, v25, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v26, v28, v26, v24
v_cmpx_gt_f32_e32 v25, v26
s_cbranch_execz .LBB0_10
v_add_co_u32 v25, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v3, vcc_lo
global_store_b32 v[20:21], v24, off
global_store_b32 v[12:13], v23, off
s_clause 0x1
global_load_u8 v23, v[16:17], off
global_load_u8 v24, v[25:26], off
s_waitcnt vmcnt(1)
global_store_b8 v[25:26], v23, off
s_waitcnt vmcnt(0)
global_store_b8 v[16:17], v24, off
global_load_b32 v23, v[14:15], off
global_load_b32 v24, v[18:19], off
s_waitcnt vmcnt(1)
global_store_b32 v[18:19], v23, off
s_waitcnt vmcnt(0)
global_store_b32 v[14:15], v24, off
s_branch .LBB0_10
.LBB0_13:
v_cmp_eq_u32_e32 vcc_lo, 3, v22
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_27
global_load_b32 v8, v[0:1], off offset:8
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0, v8
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_18
s_mov_b32 s1, exec_lo
v_cmpx_neq_f32_e32 0, v8
s_cbranch_execz .LBB0_17
global_load_u8 v0, v[4:5], off
v_mov_b32_e32 v1, 0x41700000
s_waitcnt vmcnt(0)
global_store_b8 v[2:3], v0, off offset:2
global_store_b32 v[6:7], v1, off offset:8
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_18:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_27
v_dual_mov_b32 v15, v1 :: v_dual_mov_b32 v14, v0
s_mov_b64 s[0:1], 0
s_mov_b32 s4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_21
.p2align 6
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
v_dual_mov_b32 v13, s1 :: v_dual_mov_b32 v12, s0
s_or_b32 s4, s8, s4
s_and_not1_b32 s0, s5, exec_lo
s_and_b32 s1, s6, exec_lo
s_or_b32 s5, s0, s1
s_mov_b64 s[0:1], s[2:3]
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_23
.LBB0_21:
global_load_b32 v12, v[14:15], off
v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_or_b32 s6, s6, exec_lo
s_or_b32 s7, s7, exec_lo
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0, v12
s_cbranch_execz .LBB0_20
s_add_u32 s2, s0, 1
v_add_co_u32 v6, vcc_lo, v8, 4
s_addc_u32 s3, s1, 0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
s_cmp_eq_u32 s2, 3
v_add_co_u32 v14, vcc_lo, v10, 4
s_cselect_b32 s9, -1, 0
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v11, vcc_lo
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_and_not1_b32 s6, s6, exec_lo
s_or_b32 s7, s7, s9
s_branch .LBB0_20
.LBB0_23:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s0, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_27
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_mov_b32 s1, 0
s_mov_b32 s0, exec_lo
v_cndmask_b32_e64 v6, 0x3ba3d70a, 1.0, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v13, vcc_lo
global_store_b32 v[10:11], v6, off
global_load_u8 v4, v[4:5], off
v_mov_b32_e32 v5, 0x41700000
s_waitcnt vmcnt(0)
global_store_b8 v[2:3], v4, off
global_store_b32 v[8:9], v5, off
v_cmpx_ne_u32_e32 0, v12
s_cbranch_execz .LBB0_27
s_mov_b32 s3, 0x3fefd70a
s_mov_b32 s2, 0x3d70a3d7
.p2align 6
.LBB0_26:
global_load_b32 v2, v[0:1], off
v_add_nc_u32_e32 v12, -1, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, s0, v0, 4
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_26
.LBB0_27:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13trainGMM_CUDAPhS_PfS0_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 37
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13trainGMM_CUDAPhS_PfS0_S_ii, .Lfunc_end0-_Z13trainGMM_CUDAPhS_PfS0_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12testGMM_CUDAPhS_PfS0_S_ii
.globl _Z12testGMM_CUDAPhS_PfS0_S_ii
.p2align 8
.type _Z12testGMM_CUDAPhS_PfS0_S_ii,@function
_Z12testGMM_CUDAPhS_PfS0_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_9
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v1, v2, s3
v_ashrrev_i32_e32 v3, 31, v0
s_load_b64 s[2:3], s[0:1], 0x20
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
global_load_u8 v4, v[4:5], off
v_add_nc_u32_e32 v5, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v9, v5, 1, v5
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[9:10]
v_add_co_u32 v5, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
s_mov_b32 s4, 0
s_mov_b32 s3, 0x3fe66666
s_mov_b32 s2, 0x66666666
s_branch .LBB1_4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s11
v_mov_b32_e32 v14, 0xff
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s10, s10, exec_lo
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s9, s9, exec_lo
s_or_b32 s7, s7, s10
s_or_b32 s6, s6, s9
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s6
s_or_b32 s4, s8, s4
s_and_not1_b32 s5, s5, exec_lo
s_and_b32 s8, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s8
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB1_7
.LBB1_4:
v_and_b32_e32 v13, 0xff, v12
s_or_b32 s7, s7, exec_lo
s_or_b32 s6, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v12, 2, v13
v_add_co_u32 v14, vcc_lo, v7, v12
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v8, vcc_lo
global_load_b32 v12, v[14:15], off
v_add_co_u32 v14, vcc_lo, v9, v13
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v10, vcc_lo
global_load_u8 v16, v[14:15], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[14:15], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[14:15], 0x40040000
v_cvt_i32_f64_e32 v12, v[14:15]
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v14, v4, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v15, 0, v14
v_max_i32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v14, v12
v_mov_b32_e32 v14, 0
s_and_saveexec_b32 s8, vcc_lo
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB1_3
v_lshlrev_b32_e32 v12, 2, v13
s_mov_b32 s9, -1
s_mov_b32 s10, -1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v14, vcc_lo, v5, v12
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v6, vcc_lo
global_load_b32 v12, v[14:15], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v11, v11, v12
v_cvt_f64_f32_e32 v[14:15], v11
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nle_f64_e32 s[2:3], v[14:15]
s_cbranch_execz .LBB1_2
v_cmp_lt_u16_e32 vcc_lo, 1, v13
v_add_nc_u16 v12, v13, 1
s_xor_b32 s10, exec_lo, -1
s_or_not1_b32 s9, vcc_lo, exec_lo
s_branch .LBB1_2
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_9
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v1, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v3, vcc_lo
global_store_b8 v[0:1], v14, off
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12testGMM_CUDAPhS_PfS0_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12testGMM_CUDAPhS_PfS0_S_ii, .Lfunc_end1-_Z12testGMM_CUDAPhS_PfS0_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13trainGMM_CUDAPhS_PfS0_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13trainGMM_CUDAPhS_PfS0_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 37
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12testGMM_CUDAPhS_PfS0_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12testGMM_CUDAPhS_PfS0_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<cstring>
#include<cstdlib>
#define GMM_MAX_COMPONT 3
#define GMM_LEARN_ALPHA 0.005
#define GMM_THRESHOD_SUMW 0.7
#define HEIGHT 1080
#define WIDTH 1920
using namespace std;
__global__ void trainGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
int num_fit = 0;
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[0] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[0];
modelSData[k] = 15.0;
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[0];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
}
__global__ void testGMM_CUDA(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= height || y >= width)
return;
unsigned char *_imageData = _image + x * width + y;
unsigned char *maskData = mask + x * width + y;
float *modelWData = modelW + GMM_MAX_COMPONT * (x * width + y);
float *modelSData = modelS + GMM_MAX_COMPONT * (x * width + y);
unsigned char *modelMData = modelM + GMM_MAX_COMPONT * (x * width + y);
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[0] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[0] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[0] = 255;
break;
}
}
}
void trainGMM(unsigned char *_image, unsigned char *mask, float *modelW, float *modelS, unsigned char *modelM, int height, int width)
{
/**************************** Train ******************************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
for (int j = 0; j < width; j++)
{
int num_fit = 0;
/**************************** Update parameters Start ******************************************/
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
int delm = abs(_imageData[j] - modelMData[k]);
long dist = delm * delm;
if (dist < 3.0 * modelSData[k])
{
modelWData[k] += GMM_LEARN_ALPHA * (1 - modelWData[k]);
modelMData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * delm;
modelSData[k] += (GMM_LEARN_ALPHA / modelWData[k]) * (dist - modelSData[k]);
}
else
{
modelWData[k] += GMM_LEARN_ALPHA * (0 - modelWData[k]);
num_fit++;
}
}
/**************************** Update parameters End ******************************************/
/*********************** Sort Gaussian component by 'weight / sigma' Start ****************************/
for (int kk = 0; kk < GMM_MAX_COMPONT; kk++)
{
for (int rr = kk; rr< GMM_MAX_COMPONT; rr++)
{
if (modelWData[rr] / modelSData[rr] > modelWData[kk] / modelSData[kk])
{
float temp_weight = modelWData[rr];
modelWData[rr] = modelWData[kk];
modelWData[kk] = temp_weight;
unsigned char temp_mean = modelMData[rr];
modelMData[rr] = modelMData[kk];
modelMData[kk] = temp_mean;
float temp_sigma = modelSData[rr];
modelSData[rr] = modelSData[kk];
modelSData[kk] = temp_sigma;
}
}
}
/*********************** Sort Gaussian model by 'weight / sigma' End ****************************/
/*********************** Create new Gaussian component Start ****************************/
if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] == 0)
{
//if there is no exit component fit,then start a new component
for (int k = 0; k < GMM_MAX_COMPONT; k++)
{
if (0 == modelWData[k])
{
if (k == 0)
modelWData[k] = 1;
else
modelWData[k] = GMM_LEARN_ALPHA;
modelMData[k] = _imageData[j];
modelSData[k] = 15.0;
//normalization the weight,let they sum to 1
for (int q = 0; q < GMM_MAX_COMPONT && q != k; q++)
{
/****update the other unfit's weight,u and sigma remain unchanged****/
modelWData[q] *= (1 - GMM_LEARN_ALPHA);
}
break;
}
}
}
else if (num_fit == GMM_MAX_COMPONT && modelWData[GMM_MAX_COMPONT - 1] != 0)
{
modelMData[GMM_MAX_COMPONT - 1] = _imageData[j];
modelSData[GMM_MAX_COMPONT - 1] = 15.0;
}
/*********************** Create new Gaussian component End ****************************/
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
void testGMM(unsigned char* _image, unsigned char* mask, float* modelW, float* modelS, unsigned char* modelM, int height, int width)
{
/*********************** Predict ****************************/
for (int i = 0; i < height; i++)
{
float *modelWData = modelW + i * width * GMM_MAX_COMPONT;
float *modelSData = modelS + i * width * GMM_MAX_COMPONT;
unsigned char *modelMData = modelM + i * width * GMM_MAX_COMPONT;
const unsigned char *_imageData = _image + i * width;
unsigned char *maskData = mask + i * width;
for (int j = 0; j < width; j++)
{
float sum_w = 0.0;
for (unsigned char k = 0; k < GMM_MAX_COMPONT; k++)
{
if (abs(_imageData[j] - modelMData[k]) < (unsigned char)(2.5 * modelSData[k]))
{
maskData[j] = 0;
break;
}
sum_w += modelWData[k];
if (sum_w >= GMM_THRESHOD_SUMW)
{
maskData[j] = 255;
break;
}
}
modelWData += GMM_MAX_COMPONT;
modelSData += GMM_MAX_COMPONT;
modelMData += GMM_MAX_COMPONT;
}
}
}
int main()
{
float *modelW = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
float *modelS = new float[HEIGHT * GMM_MAX_COMPONT * WIDTH];
unsigned char *modelM = new unsigned char[HEIGHT * GMM_MAX_COMPONT * WIDTH];;
unsigned char *frame = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask = new unsigned char[HEIGHT * WIDTH];
unsigned char *mask2 = new unsigned char[HEIGHT * WIDTH];
int height = HEIGHT;
int width = WIDTH;
memset(modelW, 0, sizeof(modelW));
memset(modelS, 0, sizeof(modelM));
memset(modelM, 0, sizeof(modelS));
memset(mask, 0, sizeof(mask));
// For GPU
float *dev_modelW, *dev_modelS;
unsigned char *dev_frame, *dev_mask, *dev_modelM;
hipMalloc((void**)&dev_modelW, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
hipMalloc((void**)&dev_modelS, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(float));
hipMalloc((void**)&dev_modelM, (HEIGHT * GMM_MAX_COMPONT * WIDTH) * sizeof(unsigned char));
hipMalloc((void**)&dev_frame, (HEIGHT * WIDTH) * sizeof(unsigned char));
hipMalloc((void**)&dev_mask, (HEIGHT * WIDTH) * sizeof(unsigned char));
hipMemcpy(dev_modelW,
modelW,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(dev_modelS,
modelS,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(dev_modelM,
modelM,
HEIGHT * GMM_MAX_COMPONT * WIDTH * sizeof(unsigned char),
hipMemcpyHostToDevice);
dim3 block(32,8);
dim3 grid((HEIGHT + block.x - 1) / block.x,
(WIDTH + block.y - 1) / block.y);
clock_t start, end;
clock_t start2, end2;
double sum_t = 0;
double sum_t2 = 0;
srand(unsigned(time(0)));
int frame_num = 100;
for (int t = 0; t < frame_num; t++)
{
for (int i = 0; i < height; i++)
for (int j = 0; j < width; j++)
*(frame + i * width + j) = rand() % 255;
start = clock();
trainGMM(frame, mask, modelW, modelS, modelM, height, width);
testGMM(frame, mask, modelW, modelS, modelM, height, width);
end = clock();
sum_t += end - start;
start2 = clock();
hipMemcpy(dev_frame,
frame,
HEIGHT * WIDTH * sizeof(unsigned char),
hipMemcpyHostToDevice);
trainGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
testGMM_CUDA<<<grid, block>>>(dev_frame, dev_mask, dev_modelW, dev_modelS, dev_modelM, height, width);
hipMemcpy(mask2,
dev_mask,
HEIGHT * WIDTH * sizeof(unsigned char),
hipMemcpyDeviceToHost);
end2 = clock();
sum_t2 += end2 - start2;
// TEST
/*
int diff_count = 0;
for (int i = 0; i < height * width; i++)
if (mask[i] != mask2[i])
diff_count++;
cout <<"Diff: " << diff_count << endl;
*/
}
cout <<"CPU: " << (sum_t / frame_num) / CLOCKS_PER_SEC << endl;
cout <<"GPU: " << (sum_t2 / frame_num) / CLOCKS_PER_SEC << endl;
} | .text
.file "gmm_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii # -- Begin function _Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii
.p2align 4, 0x90
.type _Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii,@function
_Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii: # @_Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13trainGMM_CUDAPhS_PfS0_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii, .Lfunc_end0-_Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii # -- Begin function _Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii,@function
_Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii: # @_Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12testGMM_CUDAPhS_PfS0_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii, .Lfunc_end1-_Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8trainGMMPhS_PfS0_S_ii
.LCPI2_0:
.quad 0x4008000000000000 # double 3
.LCPI2_1:
.quad 0x3f747ae147ae147b # double 0.0050000000000000001
.LCPI2_3:
.long 0x3ba3d70a # float 0.00499999989
.long 0x3f800000 # float 1
.LCPI2_4:
.quad 0x3fefd70a3d70a3d7 # double 0.99499999999999999
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x3f800000 # float 1
.text
.globl _Z8trainGMMPhS_PfS0_S_ii
.p2align 4, 0x90
.type _Z8trainGMMPhS_PfS0_S_ii,@function
_Z8trainGMMPhS_PfS0_S_ii: # @_Z8trainGMMPhS_PfS0_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, -16(%rsp) # 8-byte Spill
movq %rcx, -24(%rsp) # 8-byte Spill
movq %rdx, -32(%rsp) # 8-byte Spill
movq %rdi, -40(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB2_8
# %bb.1: # %.lr.ph150
movslq 56(%rsp), %rax
movl %r9d, %ecx
movq %rcx, -8(%rsp) # 8-byte Spill
movq %rax, -48(%rsp) # 8-byte Spill
movl %eax, %r10d
xorl %r11d, %r11d
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movsd .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero
xorps %xmm3, %xmm3
movsd .LCPI2_4(%rip), %xmm4 # xmm4 = mem[0],zero
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r11
cmpq -8(%rsp), %r11 # 8-byte Folded Reload
je .LBB2_8
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_12 Depth 3
# Child Loop BB2_13 Depth 4
# Child Loop BB2_20 Depth 3
# Child Loop BB2_23 Depth 3
cmpl $0, 56(%rsp)
jle .LBB2_7
# %bb.3: # %.preheader134.preheader
# in Loop: Header=BB2_2 Depth=1
movq %r11, %rax
imulq -48(%rsp), %rax # 8-byte Folded Reload
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax), %r14
leaq (%rax,%rax,2), %rax
movq -16(%rsp), %rcx # 8-byte Reload
addq %rax, %rcx
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r8
movq -32(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_27: # %.critedge
# in Loop: Header=BB2_4 Depth=2
addq $12, %r13
addq $12, %r8
addq $3, %rcx
incq %rbp
cmpq %r10, %rbp
je .LBB2_7
.LBB2_4: # %.preheader134
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_12 Depth 3
# Child Loop BB2_13 Depth 4
# Child Loop BB2_20 Depth 3
# Child Loop BB2_23 Depth 3
xorl %esi, %esi
xorl %eax, %eax
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_5 Depth=3
movss (%r13,%rsi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
xorpd %xmm6, %xmm6
subss %xmm5, %xmm6
cvtss2sd %xmm6, %xmm6
mulsd %xmm2, %xmm6
cvtss2sd %xmm5, %xmm5
addsd %xmm6, %xmm5
cvtsd2ss %xmm5, %xmm5
movss %xmm5, (%r13,%rsi,4)
incl %eax
.LBB2_10: # in Loop: Header=BB2_5 Depth=3
incq %rsi
cmpq $3, %rsi
je .LBB2_11
.LBB2_5: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%r14,%rbp), %edi
movzbl (%rcx,%rsi), %edx
subl %edx, %edi
movl %edi, %edx
imull %edi, %edx
xorps %xmm5, %xmm5
cvtsi2sd %edx, %xmm5
movss (%r8,%rsi,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
mulsd %xmm0, %xmm6
ucomisd %xmm5, %xmm6
jbe .LBB2_9
# %bb.6: # in Loop: Header=BB2_5 Depth=3
movl %edi, %r15d
negl %r15d
cmovsl %edi, %r15d
movss (%r13,%rsi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movaps %xmm1, %xmm6
subss %xmm5, %xmm6
cvtss2sd %xmm6, %xmm6
mulsd %xmm2, %xmm6
cvtss2sd %xmm5, %xmm5
addsd %xmm6, %xmm5
cvtsd2ss %xmm5, %xmm5
movss %xmm5, (%r13,%rsi,4)
cvtss2sd %xmm5, %xmm5
movapd %xmm2, %xmm6
divsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsi2sd %r15d, %xmm5
mulsd %xmm6, %xmm5
movzbl (%rcx,%rsi), %edi
xorps %xmm6, %xmm6
cvtsi2sd %edi, %xmm6
addsd %xmm5, %xmm6
cvttsd2si %xmm6, %edi
movb %dil, (%rcx,%rsi)
movss (%r13,%rsi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
cvtss2sd %xmm5, %xmm5
movapd %xmm2, %xmm6
divsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsi2ss %edx, %xmm5
movss (%r8,%rsi,4), %xmm7 # xmm7 = mem[0],zero,zero,zero
subss %xmm7, %xmm5
cvtss2sd %xmm5, %xmm5
mulsd %xmm6, %xmm5
xorps %xmm6, %xmm6
cvtss2sd %xmm7, %xmm6
addsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsd2ss %xmm6, %xmm5
movss %xmm5, (%r8,%rsi,4)
jmp .LBB2_10
.p2align 4, 0x90
.LBB2_11: # %.preheader.preheader
# in Loop: Header=BB2_4 Depth=2
movq %r13, %rsi
movq %r8, %r12
movq %rcx, %r15
xorl %edx, %edx
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_12 Depth=3
incq %rdx
incq %r15
addq $4, %r12
addq $4, %rsi
cmpq $3, %rdx
je .LBB2_17
.LBB2_12: # %.preheader
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_13 Depth 4
movq $-3, %rdi
jmp .LBB2_13
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_13 Depth=4
incq %rdi
movq %rdx, %r9
addq %rdi, %r9
je .LBB2_16
.LBB2_13: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# Parent Loop BB2_12 Depth=3
# => This Inner Loop Header: Depth=4
movss 12(%rsi,%rdi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
divss 12(%r12,%rdi,4), %xmm7
movss (%r13,%rdx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm6, %xmm8
divss (%r8,%rdx,4), %xmm8
ucomiss %xmm8, %xmm7
jbe .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=4
movss %xmm6, 12(%rsi,%rdi,4)
movss %xmm5, (%r13,%rdx,4)
movzbl 3(%r15,%rdi), %r9d
movzbl (%rcx,%rdx), %ebx
movb %bl, 3(%r15,%rdi)
movb %r9b, (%rcx,%rdx)
movss 12(%r12,%rdi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%r8,%rdx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss %xmm6, 12(%r12,%rdi,4)
movss %xmm5, (%r8,%rdx,4)
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_4 Depth=2
cmpl $3, %eax
jne .LBB2_27
# %bb.18: # in Loop: Header=BB2_4 Depth=2
movss 8(%r13), %xmm5 # xmm5 = mem[0],zero,zero,zero
ucomiss %xmm3, %xmm5
jne .LBB2_25
jp .LBB2_25
# %bb.19: # %.preheader131.preheader
# in Loop: Header=BB2_4 Depth=2
movl $-1, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_20: # %.preheader131
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13,%rdx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
ucomiss %xmm3, %xmm5
jne .LBB2_24
jnp .LBB2_21
.LBB2_24: # in Loop: Header=BB2_20 Depth=3
incq %rdx
incl %eax
cmpq $3, %rdx
jne .LBB2_20
jmp .LBB2_27
.LBB2_25: # in Loop: Header=BB2_4 Depth=2
jne .LBB2_26
jnp .LBB2_27
.LBB2_26: # in Loop: Header=BB2_4 Depth=2
movzbl (%r14,%rbp), %eax
movb %al, 2(%rcx)
movl $1097859072, 8(%r8) # imm = 0x41700000
jmp .LBB2_27
.LBB2_21: # in Loop: Header=BB2_4 Depth=2
xorl %esi, %esi
testl %edx, %edx
sete %sil
movss .LCPI2_3(,%rsi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss %xmm5, (%r13,%rdx,4)
movzbl (%r14,%rbp), %esi
movb %sil, (%rcx,%rdx)
movl $1097859072, (%r8,%rdx,4) # imm = 0x41700000
je .LBB2_27
# %bb.22: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movl %eax, %eax
cmpq $2, %rax
movl $2, %edx
cmovaeq %rdx, %rax
incq %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_23: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13,%rdx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
cvtss2sd %xmm5, %xmm5
mulsd %xmm4, %xmm5
cvtsd2ss %xmm5, %xmm5
movss %xmm5, (%r13,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB2_23
jmp .LBB2_27
.LBB2_8: # %._crit_edge151
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8trainGMMPhS_PfS0_S_ii, .Lfunc_end2-_Z8trainGMMPhS_PfS0_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7testGMMPhS_PfS0_S_ii
.LCPI3_0:
.quad 0x4004000000000000 # double 2.5
.LCPI3_1:
.quad 0x3fe6666666666666 # double 0.69999999999999996
.text
.globl _Z7testGMMPhS_PfS0_S_ii
.p2align 4, 0x90
.type _Z7testGMMPhS_PfS0_S_ii,@function
_Z7testGMMPhS_PfS0_S_ii: # @_Z7testGMMPhS_PfS0_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, -8(%rsp) # 8-byte Spill
movq %rcx, -16(%rsp) # 8-byte Spill
movq %rdx, -24(%rsp) # 8-byte Spill
movq %rsi, -32(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB3_6
# %bb.1: # %.lr.ph
movslq 56(%rsp), %rsi
movl %r9d, %r9d
movl %esi, %r11d
xorl %ebx, %ebx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbx
cmpq %r9, %rbx
je .LBB3_6
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_8 Depth 3
cmpl $0, 56(%rsp)
jle .LBB3_5
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB3_2 Depth=1
movq %rbx, %rax
imulq %rsi, %rax
leaq (%rdi,%rax), %r14
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax), %r15
leaq (%rax,%rax,2), %rax
movq -8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax), %r12
movq -16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %eax, %eax
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_4 Depth=2
xorl %r8d, %r8d
.LBB3_12: # %.loopexit.sink.split
# in Loop: Header=BB3_4 Depth=2
movb %r8b, (%r15,%rax)
.LBB3_13: # %.loopexit
# in Loop: Header=BB3_4 Depth=2
addq $12, %rbp
addq $12, %r13
addq $3, %r12
incq %rax
cmpq %r11, %rax
je .LBB3_5
.LBB3_4: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_8 Depth 3
movzbl (%r14,%rax), %edx
xorps %xmm2, %xmm2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%r12,%r8), %ecx
movl %edx, %r10d
subl %ecx, %r10d
movl %r10d, %ecx
negl %ecx
cmovsl %r10d, %ecx
movss (%r13,%r8,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
cvttsd2si %xmm3, %r10d
movzbl %r10b, %r10d
cmpl %r10d, %ecx
jb .LBB3_9
# %bb.10: # in Loop: Header=BB3_8 Depth=3
addss (%rbp,%r8,4), %xmm2
xorps %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
ucomisd %xmm1, %xmm3
jae .LBB3_11
# %bb.7: # in Loop: Header=BB3_8 Depth=3
incq %r8
cmpq $3, %r8
jne .LBB3_8
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_4 Depth=2
movb $-1, %r8b
jmp .LBB3_12
.LBB3_6: # %._crit_edge54
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7testGMMPhS_PfS0_S_ii, .Lfunc_end3-_Z7testGMMPhS_PfS0_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x4004000000000000 # double 2.5
.LCPI4_1:
.quad 0x3fe6666666666666 # double 0.69999999999999996
.LCPI4_2:
.quad 0x4059000000000000 # double 100
.LCPI4_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $24883200, %edi # imm = 0x17BB000
callq _Znam
movq %rax, %rbx
movl $24883200, %edi # imm = 0x17BB000
callq _Znam
movq %rax, %r12
movl $6220800, %edi # imm = 0x5EEC00
callq _Znam
movq %rax, %r13
movl $2073600, %edi # imm = 0x1FA400
callq _Znam
movq %rax, %rbp
movl $2073600, %edi # imm = 0x1FA400
callq _Znam
movq %rax, 224(%rsp) # 8-byte Spill
movq $0, (%rbx)
movq $0, (%r12)
movq $0, (%r13)
leaq 64(%rsp), %rdi
movl $24883200, %esi # imm = 0x17BB000
callq hipMalloc
leaq 56(%rsp), %rdi
movl $24883200, %esi # imm = 0x17BB000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $6220800, %esi # imm = 0x5EEC00
callq hipMalloc
leaq 48(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
leaq 40(%rsp), %rdi
movl $2073600, %esi # imm = 0x1FA400
callq hipMalloc
movq 64(%rsp), %rdi
movl $24883200, %edx # imm = 0x17BB000
movq %rbx, 232(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movl $24883200, %edx # imm = 0x17BB000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $6220800, %edx # imm = 0x5EEC00
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorps %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd %xmm0, 24(%rsp) # 8-byte Spill
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_1 Depth=1
subq 248(%rsp), %r14 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movq 40(%rsp), %rsi
movl $2073600, %edx # imm = 0x1FA400
movq 224(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
subq 240(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
incl %ebx
cmpl $100, %ebx
je .LBB4_18
.LBB4_1: # %.preheader86
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
# Child Loop BB4_6 Depth 2
# Child Loop BB4_7 Depth 3
# Child Loop BB4_8 Depth 4
movq %rbx, 256(%rsp) # 8-byte Spill
movq %rbp, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.preheader
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
movq $-1920, %r15 # imm = 0xF880
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
cltq
imulq $-2139062143, %rax, %rcx # imm = 0x80808081
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
shrl $7, %ecx
addl %edx, %ecx
addl %eax, %ecx
movb %cl, 1920(%r14,%r15)
incq %r15
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rbx
addq $1920, %r14 # imm = 0x780
cmpq $1080, %rbx # imm = 0x438
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
callq clock
movq %rax, 248(%rsp) # 8-byte Spill
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %rbp, %rdi
movq 240(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movq %r12, %rcx
movq %r13, %r8
movl $1080, %r9d # imm = 0x438
pushq $1920 # imm = 0x780
.cfi_adjust_cfa_offset 8
callq _Z8trainGMMPhS_PfS0_S_ii
addq $16, %rsp
.cfi_adjust_cfa_offset -16
xorl %eax, %eax
movabsq $34359738400, %r15 # imm = 0x800000020
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI4_1(%rip), %xmm3 # xmm3 = mem[0],zero
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_12: # %._crit_edge.i
# in Loop: Header=BB4_6 Depth=2
incq %rax
cmpq $1080, %rax # imm = 0x438
je .LBB4_13
.LBB4_6: # Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_7 Depth 3
# Child Loop BB4_8 Depth 4
imulq $1920, %rax, %rcx # imm = 0x780
addq %rbp, %rcx
imulq $5760, %rax, %rdi # imm = 0x1680
leaq (%rdi,%r13), %rdx
leaq (%r12,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorl %r8d, %r8d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_11: # %.loopexit.i
# in Loop: Header=BB4_7 Depth=3
addq $12, %rdi
addq $12, %rsi
addq $3, %rdx
incq %r8
cmpq $1920, %r8 # imm = 0x780
je .LBB4_12
.LBB4_7: # %.preheader.i
# Parent Loop BB4_1 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_8 Depth 4
movzbl (%rcx,%r8), %r9d
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_8: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_6 Depth=2
# Parent Loop BB4_7 Depth=3
# => This Inner Loop Header: Depth=4
movzbl (%rdx,%r10), %r11d
movl %r9d, %ebx
subl %r11d, %ebx
movl %ebx, %r11d
negl %r11d
cmovsl %ebx, %r11d
movss (%rsi,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd %xmm2, %xmm1
cvttsd2si %xmm1, %ebx
movzbl %bl, %ebx
cmpl %ebx, %r11d
jb .LBB4_11
# %bb.9: # in Loop: Header=BB4_8 Depth=4
addss (%rdi,%r10,4), %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
ucomisd %xmm3, %xmm1
jae .LBB4_11
# %bb.10: # in Loop: Header=BB4_8 Depth=4
leaq 1(%r10), %r11
cmpq $2, %r10
movq %r11, %r10
jne .LBB4_8
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_13: # %_Z7testGMMPhS_PfS0_S_ii.exit
# in Loop: Header=BB4_1 Depth=1
callq clock
movq %rax, %r14
callq clock
movq %rax, 240(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movl $2073600, %edx # imm = 0x1FA400
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $1030792151074, %rbx # imm = 0xF000000022
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14: # in Loop: Header=BB4_1 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 32(%rsp), %rdi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdi, 120(%rsp)
movl $1080, 12(%rsp) # imm = 0x438
movl $1920, 8(%rsp) # imm = 0x780
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z13trainGMM_CUDAPhS_PfS0_S_ii, %edi
leaq 160(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15: # in Loop: Header=BB4_1 Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 256(%rsp), %rbx # 8-byte Reload
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_1 Depth=1
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 32(%rsp), %rdi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdi, 120(%rsp)
movl $1080, 12(%rsp) # imm = 0x438
movl $1920, 8(%rsp) # imm = 0x780
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z12testGMM_CUDAPhS_PfS0_S_ii, %edi
leaq 160(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI4_2(%rip), %xmm0
divsd .LCPI4_3(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_27
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_21
# %bb.20:
movzbl 67(%rbx), %ecx
jmp .LBB4_22
.LBB4_21:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI4_2(%rip), %xmm0
divsd .LCPI4_3(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_27
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB4_25
# %bb.24:
movzbl 67(%rbx), %ecx
jmp .LBB4_26
.LBB4_25:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_27:
.cfi_def_cfa_offset 320
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13trainGMM_CUDAPhS_PfS0_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12testGMM_CUDAPhS_PfS0_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13trainGMM_CUDAPhS_PfS0_S_ii,@object # @_Z13trainGMM_CUDAPhS_PfS0_S_ii
.section .rodata,"a",@progbits
.globl _Z13trainGMM_CUDAPhS_PfS0_S_ii
.p2align 3, 0x0
_Z13trainGMM_CUDAPhS_PfS0_S_ii:
.quad _Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii
.size _Z13trainGMM_CUDAPhS_PfS0_S_ii, 8
.type _Z12testGMM_CUDAPhS_PfS0_S_ii,@object # @_Z12testGMM_CUDAPhS_PfS0_S_ii
.globl _Z12testGMM_CUDAPhS_PfS0_S_ii
.p2align 3, 0x0
_Z12testGMM_CUDAPhS_PfS0_S_ii:
.quad _Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii
.size _Z12testGMM_CUDAPhS_PfS0_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU: "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU: "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13trainGMM_CUDAPhS_PfS0_S_ii"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12testGMM_CUDAPhS_PfS0_S_ii"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__trainGMM_CUDAPhS_PfS0_S_ii
.addrsig_sym _Z27__device_stub__testGMM_CUDAPhS_PfS0_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13trainGMM_CUDAPhS_PfS0_S_ii
.addrsig_sym _Z12testGMM_CUDAPhS_PfS0_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_includes.cuh"
#include <stdlib.h>
#include <stdio.h>
void HandleError(cudaError_t err, const char* file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
struct Sphere; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_includes.cuh"
#include <stdlib.h>
#include <stdio.h>
void HandleError(cudaError_t err, const char* file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
struct Sphere; | .file "tmpxft_00075528_00000000-6_cuda_includes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
.text
.globl _Z11HandleError9cudaErrorPKci
.type _Z11HandleError9cudaErrorPKci, @function
_Z11HandleError9cudaErrorPKci:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11HandleError9cudaErrorPKci, .-_Z11HandleError9cudaErrorPKci
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_includes.cuh"
#include <stdlib.h>
#include <stdio.h>
void HandleError(cudaError_t err, const char* file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
struct Sphere; | #pragma once
#include "hip/hip_runtime.h"
#include <math.h>
#define INF 2e10f
#define DIM_GPU 1000
void HandleError(hipError_t err, const char* file, int line);
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
struct Sphere {
float r, g, b;
float radius;
float x, y, z;
__device__ float hit(float ox, float oy, float* n) {
float dx = ox - x;
float dy = oy - y;
if (dx * dx + dy * dy < radius * radius) {
float dz = sqrtf(radius * radius - dx * dx - dy * dy);
*n = dz / sqrtf(radius * radius);
return dz + z;
}
return -INF;
}
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include "hip/hip_runtime.h"
#include <math.h>
#define INF 2e10f
#define DIM_GPU 1000
void HandleError(hipError_t err, const char* file, int line);
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
struct Sphere {
float r, g, b;
float radius;
float x, y, z;
__device__ float hit(float ox, float oy, float* n) {
float dx = ox - x;
float dy = oy - y;
if (dx * dx + dy * dy < radius * radius) {
float dz = sqrtf(radius * radius - dx * dx - dy * dy);
*n = dz / sqrtf(radius * radius);
return dz + z;
}
return -INF;
}
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include "hip/hip_runtime.h"
#include <math.h>
#define INF 2e10f
#define DIM_GPU 1000
void HandleError(hipError_t err, const char* file, int line);
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
struct Sphere {
float r, g, b;
float radius;
float x, y, z;
__device__ float hit(float ox, float oy, float* n) {
float dx = ox - x;
float dy = oy - y;
if (dx * dx + dy * dy < radius * radius) {
float dz = sqrtf(radius * radius - dx * dx - dy * dy);
*n = dz / sqrtf(radius * radius);
return dz + z;
}
return -INF;
}
}; | .text
.file "cuda_includes.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00075528_00000000-6_cuda_includes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
.text
.globl _Z11HandleError9cudaErrorPKci
.type _Z11HandleError9cudaErrorPKci, @function
_Z11HandleError9cudaErrorPKci:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11HandleError9cudaErrorPKci, .-_Z11HandleError9cudaErrorPKci
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_includes.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdlib>
#include <cstdio>
__global__ void kernel(int* arr,int n){
int idx=blockDim.x*blockIdx.x+threadIdx.x;
if(idx<n){
arr[idx]=5;
}
return;
}
__host__ int main(int argc,char* argv[]){
int* arr=NULL;
int* cuArr=NULL;
const int n=100;
size_t size=n*sizeof(int);
arr=(int*)malloc(size);
cudaMalloc((void**)&cuArr,size);
kernel<<<2,64>>>(cuArr,n);
cudaMemcpy(arr,cuArr,size,cudaMemcpyDeviceToHost);
cudaFree(cuArr);
for(int i=0;i<n;i++){
printf("%d ",arr[i]);
}
printf("\n");
free(arr);
return 0;
} | code for sm_80
Function : _Z6kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x5 ; /* 0x0000000500057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdlib>
#include <cstdio>
__global__ void kernel(int* arr,int n){
int idx=blockDim.x*blockIdx.x+threadIdx.x;
if(idx<n){
arr[idx]=5;
}
return;
}
__host__ int main(int argc,char* argv[]){
int* arr=NULL;
int* cuArr=NULL;
const int n=100;
size_t size=n*sizeof(int);
arr=(int*)malloc(size);
cudaMalloc((void**)&cuArr,size);
kernel<<<2,64>>>(cuArr,n);
cudaMemcpy(arr,cuArr,size,cudaMemcpyDeviceToHost);
cudaFree(cuArr);
for(int i=0;i<n;i++){
printf("%d ",arr[i]);
}
printf("\n");
free(arr);
return 0;
} | .file "tmpxft_0013cf53_00000000-6_sample_0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl _Z6kernelPii
.type _Z6kernelPii, @function
_Z6kernelPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPii, .-_Z6kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $400, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rbx
leaq 400(%r13), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6kernelPiiPii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdlib>
#include <cstdio>
__global__ void kernel(int* arr,int n){
int idx=blockDim.x*blockIdx.x+threadIdx.x;
if(idx<n){
arr[idx]=5;
}
return;
}
__host__ int main(int argc,char* argv[]){
int* arr=NULL;
int* cuArr=NULL;
const int n=100;
size_t size=n*sizeof(int);
arr=(int*)malloc(size);
cudaMalloc((void**)&cuArr,size);
kernel<<<2,64>>>(cuArr,n);
cudaMemcpy(arr,cuArr,size,cudaMemcpyDeviceToHost);
cudaFree(cuArr);
for(int i=0;i<n;i++){
printf("%d ",arr[i]);
}
printf("\n");
free(arr);
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <cstdio>
__global__ void kernel(int* arr,int n){
int idx=blockDim.x*blockIdx.x+threadIdx.x;
if(idx<n){
arr[idx]=5;
}
return;
}
__host__ int main(int argc,char* argv[]){
int* arr=NULL;
int* cuArr=NULL;
const int n=100;
size_t size=n*sizeof(int);
arr=(int*)malloc(size);
hipMalloc((void**)&cuArr,size);
kernel<<<2,64>>>(cuArr,n);
hipMemcpy(arr,cuArr,size,hipMemcpyDeviceToHost);
hipFree(cuArr);
for(int i=0;i<n;i++){
printf("%d ",arr[i]);
}
printf("\n");
free(arr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <cstdio>
__global__ void kernel(int* arr,int n){
int idx=blockDim.x*blockIdx.x+threadIdx.x;
if(idx<n){
arr[idx]=5;
}
return;
}
__host__ int main(int argc,char* argv[]){
int* arr=NULL;
int* cuArr=NULL;
const int n=100;
size_t size=n*sizeof(int);
arr=(int*)malloc(size);
hipMalloc((void**)&cuArr,size);
kernel<<<2,64>>>(cuArr,n);
hipMemcpy(arr,cuArr,size,hipMemcpyDeviceToHost);
hipFree(cuArr);
for(int i=0;i<n;i++){
printf("%d ",arr[i]);
}
printf("\n");
free(arr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPii
.globl _Z6kernelPii
.p2align 8
.type _Z6kernelPii,@function
_Z6kernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPii, .Lfunc_end0-_Z6kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <cstdio>
__global__ void kernel(int* arr,int n){
int idx=blockDim.x*blockIdx.x+threadIdx.x;
if(idx<n){
arr[idx]=5;
}
return;
}
__host__ int main(int argc,char* argv[]){
int* arr=NULL;
int* cuArr=NULL;
const int n=100;
size_t size=n*sizeof(int);
arr=(int*)malloc(size);
hipMalloc((void**)&cuArr,size);
kernel<<<2,64>>>(cuArr,n);
hipMemcpy(arr,cuArr,size,hipMemcpyDeviceToHost);
hipFree(cuArr);
for(int i=0;i<n;i++){
printf("%d ",arr[i]);
}
printf("\n");
free(arr);
return 0;
} | .text
.file "sample_0.hip"
.globl _Z21__device_stub__kernelPii # -- Begin function _Z21__device_stub__kernelPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPii,@function
_Z21__device_stub__kernelPii: # @_Z21__device_stub__kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPii, .Lfunc_end0-_Z21__device_stub__kernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $100, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $100, %r14
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPii,@object # @_Z6kernelPii
.section .rodata,"a",@progbits
.globl _Z6kernelPii
.p2align 3, 0x0
_Z6kernelPii:
.quad _Z21__device_stub__kernelPii
.size _Z6kernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x5 ; /* 0x0000000500057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPii
.globl _Z6kernelPii
.p2align 8
.type _Z6kernelPii,@function
_Z6kernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPii, .Lfunc_end0-_Z6kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013cf53_00000000-6_sample_0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl _Z6kernelPii
.type _Z6kernelPii, @function
_Z6kernelPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPii, .-_Z6kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $400, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rbx
leaq 400(%r13), %r12
leaq .LC0(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100, %esi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z6kernelPiiPii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample_0.hip"
.globl _Z21__device_stub__kernelPii # -- Begin function _Z21__device_stub__kernelPii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPii,@function
_Z21__device_stub__kernelPii: # @_Z21__device_stub__kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPii, .Lfunc_end0-_Z21__device_stub__kernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $100, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $100, %r14
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPii,@object # @_Z6kernelPii
.section .rodata,"a",@progbits
.globl _Z6kernelPii
.p2align 3, 0x0
_Z6kernelPii:
.quad _Z21__device_stub__kernelPii
.size _Z6kernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void lifter(float* cepstrum, int nCoefs, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int k = i + nCoefs;
if (k < nhalf+2-nCoefs) {
cepstrum[k] = 0.0; // kill all the cepstrum coefficients above nCoefs
}
} | code for sm_80
Function : _Z6lifterPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, -UR4, 0x2, UR5 ; /* 0x0000000204047890 */
/* 0x000fe2000fffe105 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void lifter(float* cepstrum, int nCoefs, int nhalf) {
int i = threadIdx.x + blockDim.x*blockIdx.x;
int k = i + nCoefs;
if (k < nhalf+2-nCoefs) {
cepstrum[k] = 0.0; // kill all the cepstrum coefficients above nCoefs
}
} | .file "tmpxft_00136fe7_00000000-6_lifter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6lifterPfiiPfii
.type _Z27__device_stub__Z6lifterPfiiPfii, @function
_Z27__device_stub__Z6lifterPfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6lifterPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6lifterPfiiPfii, .-_Z27__device_stub__Z6lifterPfiiPfii
.globl _Z6lifterPfii
.type _Z6lifterPfii, @function
_Z6lifterPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6lifterPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6lifterPfii, .-_Z6lifterPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6lifterPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6lifterPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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