system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define ROWS 32
#define COLS 16
#define CHECK(res) if(res!=hipSuccess){exit(-1);}
__global__ void Kerneltest(int **da, unsigned int rows, unsigned int cols)
{
unsigned int row = blockDim.y*blockIdx.y + threadIdx.y;
unsigned int col = blockDim.x*blockIdx.x + threadIdx.x;
if (row < rows && col < cols)
{
da[row][col] = row*cols + col;
}
}
int main(int argc, char **argv)
{
int **da = NULL;
int **ha = NULL;
int *dc = NULL;
int *hc = NULL;
hipError_t res;
int r, c;
bool is_right=true;
res = hipMalloc((void**)(&da), ROWS*sizeof(int*));CHECK(res)
res = hipMalloc((void**)(&dc), ROWS*COLS*sizeof(int));CHECK(res)
ha = (int**)malloc(ROWS*sizeof(int*));
hc = (int*)malloc(ROWS*COLS*sizeof(int));
for (r = 0; r < ROWS; r++)
{
ha[r] = dc + r*COLS;
}
res = hipMemcpy((void*)(da), (void*)(ha), ROWS*sizeof(int*), hipMemcpyHostToDevice);CHECK(res)
dim3 dimBlock(16,16);
dim3 dimGrid((COLS+dimBlock.x-1)/(dimBlock.x), (ROWS+dimBlock.y-1)/(dimBlock.y));
Kerneltest<<<dimGrid, dimBlock>>>(da, ROWS, COLS);
res = hipMemcpy((void*)(hc), (void*)(dc), ROWS*COLS*sizeof(int), hipMemcpyDeviceToHost);CHECK(res)
for (r = 0; r < ROWS; r++)
{
for (c = 0; c < COLS; c++)
{
printf("%4d ", hc[r*COLS+c]);
if (hc[r*COLS+c] != (r*COLS+c))
{
is_right = false;
}
}
printf("\n");
}
printf("the result is %s!\n", is_right? "right":"false");
hipFree((void*)da);
hipFree((void*)dc);
free(ha);
free(hc);
getchar();
return 0;
} | .text
.file "2Dvec_add.hip"
.globl _Z25__device_stub__KerneltestPPijj # -- Begin function _Z25__device_stub__KerneltestPPijj
.p2align 4, 0x90
.type _Z25__device_stub__KerneltestPPijj,@function
_Z25__device_stub__KerneltestPPijj: # @_Z25__device_stub__KerneltestPPijj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10KerneltestPPijj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__KerneltestPPijj, .Lfunc_end0-_Z25__device_stub__KerneltestPPijj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.1:
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.2:
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
incq %rax
addq $64, %rcx
cmpq $32, %rax
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.5:
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $32, 20(%rsp)
movl $16, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10KerneltestPPijj, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq %rbx, 24(%rsp) # 8-byte Spill
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.8: # %.preheader.preheader
movb $1, %bpl
xorl %r15d, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movl $16, %ebx
movq %r12, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%r14,%r12,4), %eax
cmpq %rax, %r12
movzbl %bpl, %ebp
cmovnel %r15d, %ebp
incq %r12
decq %rbx
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
movq 32(%rsp), %r12 # 8-byte Reload
addq $16, %r12
cmpq $32, %r13
jne .LBB1_9
# %bb.12:
testb $1, %bpl
movl $.L.str.4, %eax
movl $.L.str.3, %esi
cmoveq %rax, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 176
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10KerneltestPPijj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10KerneltestPPijj,@object # @_Z10KerneltestPPijj
.section .rodata,"a",@progbits
.globl _Z10KerneltestPPijj
.p2align 3, 0x0
_Z10KerneltestPPijj:
.quad _Z25__device_stub__KerneltestPPijj
.size _Z10KerneltestPPijj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "the result is %s!\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "right"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "false"
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10KerneltestPPijj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__KerneltestPPijj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10KerneltestPPijj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10KerneltestPPijj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*00d0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD R7, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000077a24 */
/* 0x000fe400078e0205 */
/*00f0*/ IMAD.WIDE.U32 R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x004fca00078e0002 */
/*0100*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10KerneltestPPijj
.globl _Z10KerneltestPPijj
.p2align 8
.type _Z10KerneltestPPijj,@function
_Z10KerneltestPPijj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
v_cmp_gt_u32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_mad_u64_u32 v[6:7], null, v0, s3, v[2:3]
global_load_b64 v[4:5], v[3:4], off
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
flat_store_b32 v[0:1], v6
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10KerneltestPPijj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10KerneltestPPijj, .Lfunc_end0-_Z10KerneltestPPijj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10KerneltestPPijj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10KerneltestPPijj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001367da_00000000-6_2Dvec_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10KerneltestPPijjPPijj
.type _Z33__device_stub__Z10KerneltestPPijjPPijj, @function
_Z33__device_stub__Z10KerneltestPPijjPPijj:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10KerneltestPPijj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z10KerneltestPPijjPPijj, .-_Z33__device_stub__Z10KerneltestPPijjPPijj
.globl _Z10KerneltestPPijj
.type _Z10KerneltestPPijj, @function
_Z10KerneltestPPijj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10KerneltestPPijjPPijj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10KerneltestPPijj, .-_Z10KerneltestPPijj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "right"
.LC1:
.string "false"
.LC2:
.string "%4d "
.LC3:
.string "\n"
.LC4:
.string "the result is %s!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 32(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L29
leaq 40(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
movl $2048, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movq 40(%rsp), %rax
movq %rbx, %rdx
leaq 2048(%rax), %rcx
.L14:
movq %rax, (%rdx)
addq $64, %rax
addq $8, %rdx
cmpq %rcx, %rax
jne .L14
movl $1, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
movl $1, 60(%rsp)
movl $2, 64(%rsp)
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L16:
movl $2, %ecx
movl $2048, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L17
movq %rbx, %rax
leaq 64(%rbx), %r13
addq $2112, %rax
movq %rax, 8(%rsp)
movl $1, %r12d
leaq .LC2(%rip), %r14
jmp .L18
.L29:
movl $-1, %edi
call exit@PLT
.L30:
movl $-1, %edi
call exit@PLT
.L31:
movl $-1, %edi
call exit@PLT
.L32:
movl $16, %edx
movl $32, %esi
movq 32(%rsp), %rdi
call _Z33__device_stub__Z10KerneltestPPijjPPijj
jmp .L16
.L17:
movl $-1, %edi
call exit@PLT
.L33:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
addq $64, %r13
addl $16, %r15d
movq 8(%rsp), %rax
cmpq %rax, %r13
je .L21
.L18:
leaq -64(%r13), %rbx
movl %r15d, %ebp
.L20:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebp, (%rbx)
movl $0, %eax
cmovne %eax, %r12d
addq $4, %rbx
addl $1, %ebp
cmpq %r13, %rbx
jne .L20
jmp .L33
.L21:
testb %r12b, %r12b
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10KerneltestPPijj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10KerneltestPPijj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2Dvec_add.hip"
.globl _Z25__device_stub__KerneltestPPijj # -- Begin function _Z25__device_stub__KerneltestPPijj
.p2align 4, 0x90
.type _Z25__device_stub__KerneltestPPijj,@function
_Z25__device_stub__KerneltestPPijj: # @_Z25__device_stub__KerneltestPPijj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10KerneltestPPijj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__KerneltestPPijj, .Lfunc_end0-_Z25__device_stub__KerneltestPPijj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.1:
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
# %bb.2:
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
xorl %eax, %eax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
incq %rax
addq $64, %rcx
cmpq $32, %rax
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.5:
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $32, 20(%rsp)
movl $16, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10KerneltestPPijj, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq %rbx, 24(%rsp) # 8-byte Spill
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.8: # %.preheader.preheader
movb $1, %bpl
xorl %r15d, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movl $16, %ebx
movq %r12, 32(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%r14,%r12,4), %eax
cmpq %rax, %r12
movzbl %bpl, %ebp
cmovnel %r15d, %ebp
incq %r12
decq %rbx
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
movq 32(%rsp), %r12 # 8-byte Reload
addq $16, %r12
cmpq $32, %r13
jne .LBB1_9
# %bb.12:
testb $1, %bpl
movl $.L.str.4, %eax
movl $.L.str.3, %esi
cmoveq %rax, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 176
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10KerneltestPPijj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10KerneltestPPijj,@object # @_Z10KerneltestPPijj
.section .rodata,"a",@progbits
.globl _Z10KerneltestPPijj
.p2align 3, 0x0
_Z10KerneltestPPijj:
.quad _Z25__device_stub__KerneltestPPijj
.size _Z10KerneltestPPijj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4d "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "the result is %s!\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "right"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "false"
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10KerneltestPPijj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__KerneltestPPijj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10KerneltestPPijj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //RSQF.cu
/*
* Copyright 2021 Regents of the University of California
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include "RSQF.cuh"
#define LOW_BIT_MASK(n) ((1U << n) - 1U)
#define LOW_BIT_MASKLL(n) (n >= 64 ? 0xFFFFFFFFFFFFFFFF : (1ULL << n) - 1ULL)
__host__ __device__ size_t calcNumBlocksGPU(unsigned int q)
{
return (((1 << q) + (SLOTS_PER_BLOCK - 1)) / SLOTS_PER_BLOCK) + 1;
}
__host__ void initCQFGPU(struct countingQuotientFilterGPU* cqf, unsigned int q)
{
cqf->qbits = q;
cqf->numBlocks = calcNumBlocksGPU(q);
cqf_gpu_block* d_filterBlocks;
cudaMalloc((void**) &d_filterBlocks, cqf->numBlocks * sizeof(cqf_gpu_block));
cudaMemset(d_filterBlocks, 0, cqf->numBlocks * sizeof(cqf_gpu_block));
cqf->blocks = d_filterBlocks;
}
__host__ __device__ bool isOccupiedGPU(long long unsigned int occupieds, unsigned int slotNumber)
{
return (1ULL << slotNumber) & occupieds;
}
__device__ long long unsigned int setOccupiedGPU(long long unsigned int occupieds, unsigned int slotNumber)
{
return (1ULL << slotNumber) | occupieds;
}
__host__ __device__ bool isRunEndGPU(long long unsigned int runends, unsigned int slotNumber)
{
return (1ULL << slotNumber) & runends;
}
__device__ long long unsigned int setRunEndGPU(long long unsigned int runends, unsigned int slotNumber)
{
return (1ULL << slotNumber) | runends;
}
__device__ long long unsigned int clearRunEndGPU(long long unsigned int runends, unsigned int slotNumber)
{
return ~(1ULL << slotNumber) & runends;
}
__device__ unsigned int findBlockNumberGPU(unsigned int globalSlotNumber)
{
return globalSlotNumber / SLOTS_PER_BLOCK;
}
__device__ unsigned int findPositionInBlockGPU(unsigned int globalSlotNumber)
{
return globalSlotNumber % SLOTS_PER_BLOCK;
}
__host__ __device__ unsigned int findRemainderIntSlotGPU(unsigned int blockPosition)
{
return blockPosition * RBITS / 64;
}
__host__ __device__ unsigned int findRemainderStartBitGPU(unsigned int blockPosition)
{
return (blockPosition * RBITS) % 64;
}
__device__ unsigned int globalSlotIndexGPU(unsigned int blockNum, unsigned int slotNumInBlock){
return (slotNumInBlock + (blockNum * SLOTS_PER_BLOCK));
}
__host__ __device__ unsigned int getRemainderGPU(struct countingQuotientFilterGPU* cqf, unsigned int blockNum, unsigned int slotNum)
{
unsigned int integerSlot = findRemainderIntSlotGPU(slotNum);
unsigned int startBit = findRemainderStartBitGPU(slotNum);
int spillover = startBit + RBITS - 64;
unsigned int remainder;
if(spillover <= 0){
remainder = (cqf->blocks[blockNum].remainders[integerSlot] >> startBit) & LOW_BIT_MASKLL(RBITS);
}
else{
unsigned int mainBlockBits = RBITS - spillover;
remainder = (cqf->blocks[blockNum].remainders[integerSlot] >> startBit) & LOW_BIT_MASKLL(mainBlockBits);
unsigned int spilledOverBits = (cqf->blocks[blockNum].remainders[integerSlot + 1] & LOW_BIT_MASKLL(spillover)) << mainBlockBits;
remainder = remainder | spilledOverBits;
}
return remainder;
}
__device__ void setRemainderGPU(struct countingQuotientFilterGPU* cqf, unsigned int blockNum, unsigned int slotNum, unsigned int value)
{
unsigned int integerSlot = findRemainderIntSlotGPU(slotNum);
unsigned int startBit = findRemainderStartBitGPU(slotNum);
int spillover = startBit + RBITS - 64;
if(spillover <= 0){
cqf->blocks[blockNum].remainders[integerSlot] &= ~(LOW_BIT_MASKLL(RBITS) << startBit);
cqf->blocks[blockNum].remainders[integerSlot] |= ((long long unsigned int)value << startBit);
}
else{
unsigned int mainBlockBits = RBITS - spillover;
cqf->blocks[blockNum].remainders[integerSlot] &= ~(LOW_BIT_MASKLL(mainBlockBits) << startBit);
cqf->blocks[blockNum].remainders[integerSlot] |= (LOW_BIT_MASKLL(mainBlockBits) & (long long unsigned int)value) << startBit;
cqf->blocks[blockNum].remainders[integerSlot + 1] &= ~(LOW_BIT_MASKLL(spillover));
cqf->blocks[blockNum].remainders[integerSlot + 1] |= (long long unsigned int)value >> mainBlockBits;
}
}
__host__ void printGPUFilter(struct countingQuotientFilterGPU* cqf)
{
cqf_gpu_block* h_filterBlocks = new cqf_gpu_block[cqf->numBlocks];
cudaMemcpy(h_filterBlocks, cqf->blocks, cqf->numBlocks * sizeof(cqf_gpu_block), cudaMemcpyDeviceToHost);
cqf_gpu_block* d_filterBlocks = cqf->blocks;
cqf->blocks = h_filterBlocks;
printf("Filter contents:\n");
for(int i = 0; i < cqf->numBlocks; i++){
printf("block: %i\t", i);
printf("offset: %u\n", cqf->blocks[i].offset);
int rowsPerBlock = SLOTS_PER_BLOCK / 10;
for(int j = 0; j < rowsPerBlock; j++){
printf("\noccupieds:\t");
for(int k = 0; k < 10; k++){
printf("%u\t", isOccupiedGPU(cqf->blocks[i].occupieds, 10 * j + k));
}
printf("\nrunEnds:\t");
for(int k = 0; k < 10; k++){
printf("%u\t", isRunEndGPU(cqf->blocks[i].runEnds, 10 * j + k));
}
printf("\nremainders:\t");
for(int k = 0; k < 10; k++){
printf("%u\t", getRemainderGPU(cqf, i, 10 * j + k));
}
printf("\n");
}
if(SLOTS_PER_BLOCK % 10 != 0){
int numLeft = SLOTS_PER_BLOCK % 10;
printf("\noccupieds:\t");
for(int k = 0; k < numLeft; k++){
printf("%u\t", isOccupiedGPU(cqf->blocks[i].occupieds, rowsPerBlock * 10 + k));
}
printf("\nrunEnds:\t");
for(int k = 0; k < numLeft; k++){
printf("%u\t", isRunEndGPU(cqf->blocks[i].runEnds, rowsPerBlock * 10 + k));
}
printf("\nremainders:\t");
for(int k = 0; k < numLeft; k++){
printf("%u\t", getRemainderGPU(cqf, i, rowsPerBlock * 10 + k));
}
printf("\n");
}
printf("\n --------------------------------------------------------------------- \n");
}
cqf->blocks = d_filterBlocks;
}
__device__ __host__ unsigned int Normal_APHashGPU(unsigned int value, unsigned int maxHashValue)
{
unsigned char p[4];
p[0] = (value >> 24) & 0xFF;
p[1] = (value >> 16) & 0xFF;
p[2] = (value >> 8) & 0xFF;
p[3] = value & 0xFF;
unsigned int hash = 0xAAAAAAAA;
for (int i = 0; i < 4; i++){
hash ^= ((i & 1) == 0) ? ((hash << 7) ^ p[i] ^ (hash >> 3)) : (~((hash << 11) ^ p[i] ^ (hash >> 5)));
}
return hash % maxHashValue;
}
__device__ unsigned int rankBitGPU(long long unsigned int bitArray, unsigned int index)
{
unsigned int rank = __popcll(bitArray & LOW_BIT_MASKLL(index + 1));
return rank;
}
__device__ unsigned int selectBitGPU_old(long long unsigned int bitArray, unsigned int rank)
{
//using iterative method for first basic implementation
if(rank == 0){
return 0;
}
unsigned int nextOne = 0;
for(int i = 1; i <= rank; i++){
if(bitArray == 0) return UINT_MAX; //if runEnd is in next block
nextOne = __ffsll(bitArray);
bitArray &= ~LOW_BIT_MASKLL(nextOne);
}
return nextOne - 1;
}
__device__ const unsigned char kSelectInByte[2048] = {
8, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0,
1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0,
2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0,
1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2, 0, 1, 0,
3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 7, 0,
1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0,
2, 0, 1, 0, 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0,
1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2, 0, 1, 0, 3, 0,
1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 8, 8, 8, 1,
8, 2, 2, 1, 8, 3, 3, 1, 3, 2, 2, 1, 8, 4, 4, 1, 4, 2, 2, 1, 4, 3, 3, 1, 3, 2,
2, 1, 8, 5, 5, 1, 5, 2, 2, 1, 5, 3, 3, 1, 3, 2, 2, 1, 5, 4, 4, 1, 4, 2, 2, 1,
4, 3, 3, 1, 3, 2, 2, 1, 8, 6, 6, 1, 6, 2, 2, 1, 6, 3, 3, 1, 3, 2, 2, 1, 6, 4,
4, 1, 4, 2, 2, 1, 4, 3, 3, 1, 3, 2, 2, 1, 6, 5, 5, 1, 5, 2, 2, 1, 5, 3, 3, 1,
3, 2, 2, 1, 5, 4, 4, 1, 4, 2, 2, 1, 4, 3, 3, 1, 3, 2, 2, 1, 8, 7, 7, 1, 7, 2,
2, 1, 7, 3, 3, 1, 3, 2, 2, 1, 7, 4, 4, 1, 4, 2, 2, 1, 4, 3, 3, 1, 3, 2, 2, 1,
7, 5, 5, 1, 5, 2, 2, 1, 5, 3, 3, 1, 3, 2, 2, 1, 5, 4, 4, 1, 4, 2, 2, 1, 4, 3,
3, 1, 3, 2, 2, 1, 7, 6, 6, 1, 6, 2, 2, 1, 6, 3, 3, 1, 3, 2, 2, 1, 6, 4, 4, 1,
4, 2, 2, 1, 4, 3, 3, 1, 3, 2, 2, 1, 6, 5, 5, 1, 5, 2, 2, 1, 5, 3, 3, 1, 3, 2,
2, 1, 5, 4, 4, 1, 4, 2, 2, 1, 4, 3, 3, 1, 3, 2, 2, 1, 8, 8, 8, 8, 8, 8, 8, 2,
8, 8, 8, 3, 8, 3, 3, 2, 8, 8, 8, 4, 8, 4, 4, 2, 8, 4, 4, 3, 4, 3, 3, 2, 8, 8,
8, 5, 8, 5, 5, 2, 8, 5, 5, 3, 5, 3, 3, 2, 8, 5, 5, 4, 5, 4, 4, 2, 5, 4, 4, 3,
4, 3, 3, 2, 8, 8, 8, 6, 8, 6, 6, 2, 8, 6, 6, 3, 6, 3, 3, 2, 8, 6, 6, 4, 6, 4,
4, 2, 6, 4, 4, 3, 4, 3, 3, 2, 8, 6, 6, 5, 6, 5, 5, 2, 6, 5, 5, 3, 5, 3, 3, 2,
6, 5, 5, 4, 5, 4, 4, 2, 5, 4, 4, 3, 4, 3, 3, 2, 8, 8, 8, 7, 8, 7, 7, 2, 8, 7,
7, 3, 7, 3, 3, 2, 8, 7, 7, 4, 7, 4, 4, 2, 7, 4, 4, 3, 4, 3, 3, 2, 8, 7, 7, 5,
7, 5, 5, 2, 7, 5, 5, 3, 5, 3, 3, 2, 7, 5, 5, 4, 5, 4, 4, 2, 5, 4, 4, 3, 4, 3,
3, 2, 8, 7, 7, 6, 7, 6, 6, 2, 7, 6, 6, 3, 6, 3, 3, 2, 7, 6, 6, 4, 6, 4, 4, 2,
6, 4, 4, 3, 4, 3, 3, 2, 7, 6, 6, 5, 6, 5, 5, 2, 6, 5, 5, 3, 5, 3, 3, 2, 6, 5,
5, 4, 5, 4, 4, 2, 5, 4, 4, 3, 4, 3, 3, 2, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 3, 8, 8, 8, 8, 8, 8, 8, 4, 8, 8, 8, 4, 8, 4, 4, 3, 8, 8, 8, 8, 8, 8,
8, 5, 8, 8, 8, 5, 8, 5, 5, 3, 8, 8, 8, 5, 8, 5, 5, 4, 8, 5, 5, 4, 5, 4, 4, 3,
8, 8, 8, 8, 8, 8, 8, 6, 8, 8, 8, 6, 8, 6, 6, 3, 8, 8, 8, 6, 8, 6, 6, 4, 8, 6,
6, 4, 6, 4, 4, 3, 8, 8, 8, 6, 8, 6, 6, 5, 8, 6, 6, 5, 6, 5, 5, 3, 8, 6, 6, 5,
6, 5, 5, 4, 6, 5, 5, 4, 5, 4, 4, 3, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 7, 8, 7,
7, 3, 8, 8, 8, 7, 8, 7, 7, 4, 8, 7, 7, 4, 7, 4, 4, 3, 8, 8, 8, 7, 8, 7, 7, 5,
8, 7, 7, 5, 7, 5, 5, 3, 8, 7, 7, 5, 7, 5, 5, 4, 7, 5, 5, 4, 5, 4, 4, 3, 8, 8,
8, 7, 8, 7, 7, 6, 8, 7, 7, 6, 7, 6, 6, 3, 8, 7, 7, 6, 7, 6, 6, 4, 7, 6, 6, 4,
6, 4, 4, 3, 8, 7, 7, 6, 7, 6, 6, 5, 7, 6, 6, 5, 6, 5, 5, 3, 7, 6, 6, 5, 6, 5,
5, 4, 6, 5, 5, 4, 5, 4, 4, 3, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 5, 8, 8, 8, 8, 8, 8, 8, 5, 8, 8, 8, 5, 8, 5, 5, 4, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 6, 8, 8, 8, 8, 8, 8, 8, 6, 8, 8, 8, 6, 8, 6,
6, 4, 8, 8, 8, 8, 8, 8, 8, 6, 8, 8, 8, 6, 8, 6, 6, 5, 8, 8, 8, 6, 8, 6, 6, 5,
8, 6, 6, 5, 6, 5, 5, 4, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8,
8, 8, 8, 8, 8, 7, 8, 8, 8, 7, 8, 7, 7, 4, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 7,
8, 7, 7, 5, 8, 8, 8, 7, 8, 7, 7, 5, 8, 7, 7, 5, 7, 5, 5, 4, 8, 8, 8, 8, 8, 8,
8, 7, 8, 8, 8, 7, 8, 7, 7, 6, 8, 8, 8, 7, 8, 7, 7, 6, 8, 7, 7, 6, 7, 6, 6, 4,
8, 8, 8, 7, 8, 7, 7, 6, 8, 7, 7, 6, 7, 6, 6, 5, 8, 7, 7, 6, 7, 6, 6, 5, 7, 6,
6, 5, 6, 5, 5, 4, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 5, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 6, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 6, 8, 8, 8, 8, 8, 8, 8, 6, 8, 8, 8, 6,
8, 6, 6, 5, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7,
8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 7, 8, 7, 7, 5, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 7, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 7, 8, 7, 7, 6, 8, 8, 8, 8,
8, 8, 8, 7, 8, 8, 8, 7, 8, 7, 7, 6, 8, 8, 8, 7, 8, 7, 7, 6, 8, 7, 7, 6, 7, 6,
6, 5, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 6,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 8, 8, 8, 8, 7, 8, 8, 8, 7, 8, 7, 7, 6, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7
};
__device__ unsigned int selectBitGPU(long long unsigned int x, unsigned int k)
{
if(k == 0)return 0;
k--;
if (k >= __popcll(x)) { return UINT_MAX; }
const long long unsigned int kOnesStep4 = 0x1111111111111111ULL;
const long long unsigned int kOnesStep8 = 0x0101010101010101ULL;
const long long unsigned int kMSBsStep8 = 0x80ULL * kOnesStep8;
long long unsigned int s = x;
s = s - ((s & 0xA * kOnesStep4) >> 1);
s = (s & 0x3 * kOnesStep4) + ((s >> 2) & 0x3 * kOnesStep4);
s = (s + (s >> 4)) & 0xF * kOnesStep8;
long long unsigned int byteSums = s * kOnesStep8;
long long unsigned int kStep8 = k * kOnesStep8;
long long unsigned int geqKStep8 = (((kStep8 | kMSBsStep8) - byteSums) & kMSBsStep8);
long long unsigned int place = __popcll(geqKStep8) * 8;
long long unsigned int byteRank = k - (((byteSums << 8) >> place) & (long long unsigned int)(0xFF));
return place + kSelectInByte[((x >> place) & 0xFF) | (byteRank << 8)];
}
__global__ void lookupGPU(int numItems, struct countingQuotientFilterGPU cqf, unsigned int* hashValues, int* slotValues)
{
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x +blockIdx.y * gridDim.x * blockDim.x;
if(idx >= numItems) return;
//compute hash value
unsigned int q = cqf.qbits;
unsigned int hashValue = hashValues[idx];
//separate into quotient and remainder
unsigned int fq = (hashValue >> RBITS) & LOW_BIT_MASK(q);
unsigned int fr = hashValue & LOW_BIT_MASK(RBITS);
unsigned int blockNum = findBlockNumberGPU(fq);
unsigned int slotNum = findPositionInBlockGPU(fq);
//check occupied bit
if(!isOccupiedGPU(cqf.blocks[blockNum].occupieds, slotNum)){
slotValues[idx] = -1;
return;
}
//find rank of quotient slot
unsigned char blockOffset = cqf.blocks[blockNum].offset;
unsigned int rank = rankBitGPU(cqf.blocks[blockNum].occupieds, slotNum);
//select slot with runEnd rank = quotient rank
//mask off the runEnds for any runs in blocks i-1 or earlier
unsigned int endOfRun = selectBitGPU((cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset)), rank);
//if end of run is in next block
while(endOfRun == UINT_MAX){
rank -= __popcll(cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset));
if(blockOffset - SLOTS_PER_BLOCK > 0){
blockOffset = blockOffset - SLOTS_PER_BLOCK;
}
else{
blockOffset = 0;
}
blockNum++;
if(blockNum > cqf.numBlocks){
slotValues[idx] = -1;
return;
}
//select on remaining rank
endOfRun = selectBitGPU((cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset)), rank);
}
//endOfRun now points to runEnd for correct quotient
//search backwards through run
//end search if: we reach another set runEnd bit; we find the remainder; we reach canonical slot
unsigned int currentRemainder = getRemainderGPU(&cqf, blockNum, endOfRun);
// printf("remainder in last run slot: %u\n", currentRemainder);
unsigned int currentSlot = endOfRun;
do{
if(currentRemainder == fr){
//return index of slot where remainder is stored
slotValues[idx] = globalSlotIndexGPU(blockNum, currentSlot);
return;
}
if(currentRemainder < fr){
slotValues[idx] = -1;
return;
}
if(currentSlot > 0){
currentSlot--;
}
else{
currentSlot = SLOTS_PER_BLOCK - 1;
if(blockNum == 0){
slotValues[idx] = -1;
return;
}
blockNum--;
}
currentRemainder = getRemainderGPU(&cqf, blockNum, currentSlot);
}while(!isRunEndGPU(cqf.blocks[blockNum].runEnds, currentSlot) && (globalSlotIndexGPU(blockNum, currentSlot) >= fq));
slotValues[idx] = -1;
return;
}
__global__ void hashInputs(int numItems, struct countingQuotientFilterGPU cqf, unsigned int* insertValues, unsigned int* fingerprints)
{
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * gridDim.x * blockDim.x;
if(idx >= numItems) return;
//hash values to get fingerprints
unsigned int hashValue = Normal_APHashGPU(insertValues[idx], (1 << (cqf.qbits + RBITS)));
fingerprints[idx] = hashValue;
}
__host__ float launchLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* d_slotValuesArray)
{
thrust::device_vector<unsigned int> d_hashValues(numValues);
thrust::fill(d_hashValues.begin(), d_hashValues.end(), 0);
unsigned int* d_hashValuesArray = thrust::raw_pointer_cast(&d_hashValues[0]);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//Hash items
int numBlocks = (numValues + 1023) / 1024;
dim3 hashBlockDims((numBlocks + 31) / 32, 32);
hashInputs<<<hashBlockDims, 1024>>>(numValues, cqf, d_lookupValues, d_hashValuesArray);//was 128
//Create index array to track inputs -> outputs
thrust::device_vector<unsigned int> d_indices(numValues);
thrust::fill(d_indices.begin(), d_indices.end(), 1);
thrust::exclusive_scan(d_indices.begin(), d_indices.end(), d_indices.begin(), 0);
//Sort by fingerprint
thrust::sort_by_key(d_hashValues.begin(), d_hashValues.end(), d_indices.begin());
//Launch lookup kernel
numBlocks = (numValues + 511) / 512;
dim3 blockDims((numBlocks + 31) / 32, 32);
lookupGPU<<<blockDims, 512>>>(numValues, cqf, d_hashValuesArray, d_slotValuesArray); //was 1024
//Sort outputs
thrust::device_ptr<int> d_slotValues(d_slotValuesArray);
thrust::sort_by_key(d_indices.begin(), d_indices.end(), d_slotValues);
cudaEventRecord(stop);
//Calculate timing results
cudaEventSynchronize(stop);
float lookupTime = 0;
cudaEventElapsedTime(&lookupTime, start, stop);
//Free Memory
d_hashValues.~device_vector<unsigned int>();
cudaEventDestroy(start);
cudaEventDestroy(stop);
return lookupTime;
}
__global__ void hashAndLookupGPU(int numItems, struct countingQuotientFilterGPU cqf, unsigned int* lookupValues, int* slotValues)
{
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x +blockIdx.y * gridDim.x * blockDim.x;
if(idx >= numItems) return;
//compute hash value
unsigned int q = cqf.qbits;
unsigned int hashValue = Normal_APHashGPU(lookupValues[idx], (1 << (q + RBITS)));
//separate into quotient and remainder
unsigned int fq = (hashValue >> RBITS) & LOW_BIT_MASK(q);
unsigned int fr = hashValue & LOW_BIT_MASK(RBITS);
unsigned int blockNum = findBlockNumberGPU(fq);
unsigned int slotNum = findPositionInBlockGPU(fq);
//check occupied bit
if(!isOccupiedGPU(cqf.blocks[blockNum].occupieds, slotNum)){
slotValues[idx] = -1;
return;
}
//find rank of quotient slot
unsigned char blockOffset = cqf.blocks[blockNum].offset;
unsigned int rank = rankBitGPU(cqf.blocks[blockNum].occupieds, slotNum);
//select slot with runEnd rank = quotient rank
//mask off the runEnds for any runs in blocks i-1 or earlier
unsigned int endOfRun = selectBitGPU((cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset)), rank);
//if end of run is in next block
while(endOfRun == UINT_MAX){
rank -= __popcll(cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset));
if(blockOffset - SLOTS_PER_BLOCK > 0){
blockOffset = blockOffset - SLOTS_PER_BLOCK;
}
else{
blockOffset = 0;
}
blockNum++;
if(blockNum > cqf.numBlocks){
slotValues[idx] = -1;
return;
}
//select on remaining rank
endOfRun = selectBitGPU((cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset)), rank);
}
//endOfRun now points to runEnd for correct quotient
//search backwards through run
//end search if: we reach another set runEnd bit; we find the remainder; we reach canonical slot
unsigned int currentRemainder = getRemainderGPU(&cqf, blockNum, endOfRun);
// printf("remainder in last run slot: %u\n", currentRemainder);
unsigned int currentSlot = endOfRun;
do{
if(currentRemainder == fr){
//return index of slot where remainder is stored
slotValues[idx] = globalSlotIndexGPU(blockNum, currentSlot);
return;
}
if(currentRemainder < fr){
slotValues[idx] = -1;
return;
}
if(currentSlot > 0){
currentSlot--;
}
else{
currentSlot = SLOTS_PER_BLOCK - 1;
if(blockNum == 0){
slotValues[idx] = -1;
return;
}
blockNum--;
}
currentRemainder = getRemainderGPU(&cqf, blockNum, currentSlot);
}while(!isRunEndGPU(cqf.blocks[blockNum].runEnds, currentSlot) && (globalSlotIndexGPU(blockNum, currentSlot) >= fq));
slotValues[idx] = -1;
return;
}
__host__ float launchUnsortedLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* d_slotValuesArray)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//Launch lookup kernel
int numBlocks = (numValues + 511) / 512;
dim3 blockDims((numBlocks + 31) / 32, 32);
hashAndLookupGPU<<<blockDims, 512>>>(numValues, cqf, d_lookupValues, d_slotValuesArray); //was 1024
cudaEventRecord(stop);
//Calculate timing results
cudaEventSynchronize(stop);
float lookupTime = 0;
cudaEventElapsedTime(&lookupTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return lookupTime;
}
__device__ unsigned int findFirstUnusedSlotGPU(struct countingQuotientFilterGPU* cqf, int* blockNum, unsigned int currentSlot)
{
long long unsigned int occupieds = cqf->blocks[*blockNum].occupieds;
long long unsigned int runEnds = cqf->blocks[*blockNum].runEnds;
unsigned char offset = cqf->blocks[*blockNum].offset;
unsigned int rank = rankBitGPU(occupieds, currentSlot);
unsigned int select = selectBitGPU((runEnds & ~LOW_BIT_MASKLL(offset)), rank);
if(rank == 0){
select = offset;
}
while(currentSlot <= select){
if(select == UINT_MAX || select == SLOTS_PER_BLOCK - 1){
(*blockNum)++;
if(*blockNum > cqf->numBlocks) return UINT_MAX;
occupieds = cqf->blocks[*blockNum].occupieds;
runEnds = cqf->blocks[*blockNum].runEnds;
offset = cqf->blocks[*blockNum].offset;
select = offset - 1; //want currentSlot to be first slot after offset values
}
currentSlot = select + 1;
rank = rankBitGPU(occupieds, currentSlot);
select = selectBitGPU((runEnds & ~LOW_BIT_MASKLL(offset)), rank);
}
return currentSlot;
}
__global__ void quotienting(int numItems, unsigned int qbits, unsigned int* quotients, unsigned int* remainders)
{
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * gridDim.x * blockDim.x;
if(idx >= numItems) return;
//return quotients and remainders
unsigned int hashValue = quotients[idx]; //quotients array initially stores the fingerprint values
quotients[idx] = (hashValue >> RBITS) & LOW_BIT_MASK(qbits);
remainders[idx] = hashValue & LOW_BIT_MASK(RBITS);
}
__global__ void findBlockStartIndices(int numItems, unsigned int* quotients, unsigned int* blockStarts)
{
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * gridDim.x * blockDim.x;
if(idx >= numItems) return;
unsigned int blockNumber = findBlockNumberGPU(quotients[idx]);
if(idx == 0){
blockStarts[blockNumber] = 0;
return;
}
unsigned int previousItemBlock = findBlockNumberGPU(quotients[idx - 1]);
if(blockNumber != previousItemBlock){
blockStarts[blockNumber] = idx;
}
}
__device__ void incrementQueuePointer(unsigned int nextValue, unsigned int* blockInsertQueues, int blockNum, unsigned int lastRegionBlock, unsigned int* blockStarts, int numBlocks, bool* itemsLeft)
{
int nextBlockNum = blockNum + 1;
unsigned int nextBlockStart = blockStarts[nextBlockNum];
while(nextBlockStart == UINT_MAX && nextBlockNum < (numBlocks - 1)){
nextBlockNum++;
nextBlockStart = blockStarts[nextBlockNum];
}
if(nextValue + 1 < nextBlockStart){
blockInsertQueues[blockNum]++;
itemsLeft[0] = true;
}
else{
blockInsertQueues[blockNum] = UINT_MAX;
while(blockNum < lastRegionBlock){
blockNum++;
if(blockInsertQueues[blockNum] != UINT_MAX){
itemsLeft[0] = true;
return;
}
}
}
}
__global__ void insertIntoRegions(int numRegions, int numBlocksPerRegion, int numItems, struct countingQuotientFilterGPU cqf, unsigned int* blockStarts, unsigned int* nextItems, unsigned int* quotients, unsigned int* remainders, int* finalSlotValues, bool* itemsLeft)
{
//TODO: reduce resources used
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x +blockIdx.y * gridDim.x * blockDim.x;
if(idx >= numRegions) return;
//find next item to insert for region
//find start block for region
unsigned int firstRegionBlock = idx * numBlocksPerRegion;
unsigned int lastRegionBlock = (idx * numBlocksPerRegion) + numBlocksPerRegion - 1;
if(lastRegionBlock >= cqf.numBlocks) lastRegionBlock = cqf.numBlocks - 1;
unsigned int nextValue = nextItems[firstRegionBlock];
int blockNum = firstRegionBlock;
while(nextValue == UINT_MAX && blockNum < lastRegionBlock){
blockNum++;
nextValue = nextItems[blockNum];
}
if(nextValue >= numItems) return;
// printf("index of item to be inserted=%u\n", nextValue);
unsigned int fq = quotients[nextValue];
unsigned int fr = remainders[nextValue];
int homeBlockNum = blockNum;
unsigned int homeSlotNum = findPositionInBlockGPU(fq);
// printf("quotient: %u\tslot:%u\tremainder: %u\n", fq, homeSlotNum, fr);
long long unsigned int occupieds = cqf.blocks[blockNum].occupieds;
// printf("blockNum = %u\t lastRegionBlock=%u\n", blockNum, lastRegionBlock);
// printf("homeSlotNum = %u\n", homeSlotNum);
//check occupied bit
bool occupiedBit = isOccupiedGPU(occupieds, homeSlotNum);
// printf("occupied? %u\n", (unsigned int)occupiedBit);
//find rank of quotient slot
unsigned char blockOffset = cqf.blocks[blockNum].offset;
// printf("offset = %u\n", blockOffset);
unsigned int rank = rankBitGPU(occupieds, homeSlotNum);
// printf("rank = %u\n", rank);
//select slot with runEnd rank = quotient rank
//mask off the runEnds for any runs in blocks i-1 or earlier
long long unsigned int runEnds = cqf.blocks[blockNum].runEnds;
//printf("runEnds = %llu\n", runEnds);
unsigned int endOfRun = selectBitGPU((runEnds & ~LOW_BIT_MASKLL(blockOffset)), rank);
if(rank == 0){
if(blockOffset == 0){
endOfRun = 0;
}
else{
endOfRun = blockOffset - 1;
}
}
// printf("select(rank) = %u\n", endOfRun);
//if end of run is in next block
while(endOfRun == UINT_MAX){
rank -= __popcll(cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset));
if(blockOffset - SLOTS_PER_BLOCK > 0){
blockOffset = blockOffset - SLOTS_PER_BLOCK;
}
else{
blockOffset = 0;
}
blockNum++;
//select on remaining rank
endOfRun = selectBitGPU((cqf.blocks[blockNum].runEnds & ~LOW_BIT_MASKLL(blockOffset)), rank);
}
//TODO: block num check during or after loop?
if(blockNum > lastRegionBlock){
//the insert will affect the next region
itemsLeft[0] = true;
return;
}
//endOfRun now points to runEnd for correct quotient
//if select returns location earlier than fq, slot is empty and we can insert the item there
//(also if there are no occupied slots at all in the start block)
if(globalSlotIndexGPU(blockNum, endOfRun) < globalSlotIndexGPU(homeBlockNum, homeSlotNum) | blockOffset + rank == 0){
cqf.blocks[homeBlockNum].runEnds = setRunEndGPU(runEnds, homeSlotNum);
setRemainderGPU(&cqf, homeBlockNum, homeSlotNum, fr);
cqf.blocks[homeBlockNum].occupieds = setOccupiedGPU(occupieds, homeSlotNum);
finalSlotValues[nextValue] = globalSlotIndexGPU(homeBlockNum, homeSlotNum);
//move pointer to next item in queue
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
//if slot is not empty, search through the filter for the first empty slot
else{
endOfRun++;
if(endOfRun == SLOTS_PER_BLOCK){
endOfRun = 0;
blockNum++;
if(blockNum > lastRegionBlock){
//the insert will affect the next region
itemsLeft[0] = true;
return;
}
if(blockNum > cqf.numBlocks){ //insert fails
finalSlotValues[nextValue] = -1;
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
}
unsigned int runEndBlock = blockNum;
unsigned int unusedSlot = findFirstUnusedSlotGPU(&cqf, &blockNum, endOfRun);
if(unusedSlot == UINT_MAX){ //insert fails
finalSlotValues[nextValue] = -1;
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
if(blockNum > lastRegionBlock){
//the insert will affect the next region
itemsLeft[0] = true;
return;
}
if(blockNum > homeBlockNum){
for(int i = 0; i < blockNum - homeBlockNum; i++){
cqf.blocks[blockNum - i].offset++;
}
}
// printf("unused slot idx = %u\n", unusedSlot);
// printf("usused slot block = %u\n", blockNum);
// printf("canonical end of run (block, slot) = (%u, %u)\n", runEndBlock, endOfRun);
//move items over until we get back to the run the item belongs in
while(globalSlotIndexGPU(blockNum, unusedSlot) > globalSlotIndexGPU(runEndBlock, endOfRun)){
// printf("next slot: %u\n", unusedSlot);
if(unusedSlot == 0){
int nextBlock = blockNum - 1;
unsigned int nextSlot = SLOTS_PER_BLOCK - 1;
setRemainderGPU(&cqf, blockNum, unusedSlot, getRemainderGPU(&cqf, nextBlock, nextSlot));
if(isRunEndGPU(cqf.blocks[nextBlock].runEnds, nextSlot)){
cqf.blocks[blockNum].runEnds = setRunEndGPU(cqf.blocks[blockNum].runEnds, unusedSlot);
}
else{
cqf.blocks[blockNum].runEnds = clearRunEndGPU(cqf.blocks[blockNum].runEnds, unusedSlot);
}
unusedSlot = SLOTS_PER_BLOCK - 1;
blockNum--;
}
else{
setRemainderGPU(&cqf, blockNum, unusedSlot, getRemainderGPU(&cqf, blockNum, (unusedSlot - 1)));
if(isRunEndGPU(cqf.blocks[blockNum].runEnds, (unusedSlot - 1))){
cqf.blocks[blockNum].runEnds = setRunEndGPU(cqf.blocks[blockNum].runEnds, unusedSlot);
}
else{
cqf.blocks[blockNum].runEnds = clearRunEndGPU(cqf.blocks[blockNum].runEnds, unusedSlot);
}
unusedSlot--;
}
}
//if the home slot was not previously occupied, then new item is its run
if(!isOccupiedGPU(cqf.blocks[homeBlockNum].occupieds, homeSlotNum)){
setRemainderGPU(&cqf, blockNum, unusedSlot, fr);
cqf.blocks[blockNum].runEnds = setRunEndGPU(cqf.blocks[blockNum].runEnds, unusedSlot);
cqf.blocks[homeBlockNum].occupieds = setOccupiedGPU(cqf.blocks[homeBlockNum].occupieds, homeSlotNum);
finalSlotValues[nextValue] = globalSlotIndexGPU(blockNum, unusedSlot);
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
//if home slot already has a run, put new item in correct sequential location
else{
//move run end over by one slot
unsigned int nextSlot = unusedSlot - 1;
int nextBlock = blockNum;
if(unusedSlot == 0){
nextSlot = SLOTS_PER_BLOCK - 1;
nextBlock = blockNum - 1;
if(nextBlock < 0){ //insert fails
finalSlotValues[nextValue] = -1;
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
}
// printf("nextSlot: %u\tnextBlock:%u\n", nextSlot, nextBlock);
// printf("unusedSlot: %u\tblockNum: %u\n", unusedSlot, blockNum);
cqf.blocks[blockNum].runEnds = setRunEndGPU(cqf.blocks[blockNum].runEnds, unusedSlot);
cqf.blocks[nextBlock].runEnds = clearRunEndGPU(cqf.blocks[nextBlock].runEnds, nextSlot);
//search backwards through run
//end search if: we reach another set runEnd bit; we find remainder <= new remainder; we reach canonical slot
unsigned int nextRemainder = getRemainderGPU(&cqf, nextBlock, nextSlot);
// printf("remainder in last run slot: %u\n", nextRemainder);
do{
if(nextRemainder <= fr){
// printf("setting remainder in block %u, slot %u.\n", blockNum, unusedSlot);
setRemainderGPU(&cqf, blockNum, unusedSlot, fr);
//this stores duplicates
//return index of slot where remainder is stored
finalSlotValues[nextValue] = globalSlotIndexGPU(blockNum, unusedSlot);
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
setRemainderGPU(&cqf, blockNum, unusedSlot, nextRemainder);
if(unusedSlot > 0){
unusedSlot--;
if(unusedSlot == 0){
if(blockNum == 0){
setRemainderGPU(&cqf, blockNum, unusedSlot, fr);
finalSlotValues[nextValue] = globalSlotIndexGPU(blockNum, unusedSlot);
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
nextSlot = SLOTS_PER_BLOCK - 1;
nextBlock--;
}
else{
nextSlot = unusedSlot - 1;
}
}
else{
unusedSlot = SLOTS_PER_BLOCK - 1;
blockNum--;
if(blockNum < 0){ //insert fails
finalSlotValues[nextValue] = -1;
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
nextSlot = unusedSlot - 1;
}
nextRemainder = getRemainderGPU(&cqf, nextBlock, nextSlot);
}while(!isRunEndGPU(cqf.blocks[nextBlock].runEnds, nextSlot) && (globalSlotIndexGPU(nextBlock, nextSlot) >= fq));
//unusedSlot is now head of run. Insert the remainder there.
setRemainderGPU(&cqf, blockNum, unusedSlot, fr);
finalSlotValues[nextValue] = globalSlotIndexGPU(blockNum, unusedSlot);
incrementQueuePointer(nextValue, nextItems, homeBlockNum, lastRegionBlock, blockStarts, cqf.numBlocks, itemsLeft);
return;
}
}
}
//Some possible versions:
// 1. Sort items and divide them up to be inserted into groups of blocks. Groups grow with more iterations.
// 2. Items bid to be inserted into groups of blocks. Flag items that succeed insert and compact them out.
//TODO: Groupings of blocks could also have the start of the group change indices, rather than just changing group sizes. This would keep the number of threads high, while still avoiding too many reptitions on insert failures for less full filters.
__host__ float insertGPU(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_insertValues, int* d_returnValues)
{
//Allocate memory
thrust::device_vector<unsigned int> d_quotients(numValues);
thrust::fill(d_quotients.begin(), d_quotients.end(), 0);
unsigned int* d_quotientsArray = thrust::raw_pointer_cast(&d_quotients[0]);
unsigned int* d_remaindersArray;
cudaMalloc((void**) &d_remaindersArray, numValues * sizeof(unsigned int));
cudaMemset(d_remaindersArray, 0, numValues * sizeof(unsigned int));
unsigned int* d_blockStarts;
cudaMalloc((void**) &d_blockStarts, cqf.numBlocks * sizeof(unsigned int));
cudaMemset(d_blockStarts, 0xFF, cqf.numBlocks * sizeof(unsigned int));
unsigned int* d_nextItems;
cudaMalloc((void**) &d_nextItems, cqf.numBlocks * sizeof(unsigned int));
cudaMemset(d_nextItems, 0xFF, cqf.numBlocks * sizeof(unsigned int));
bool* h_itemsLeft = new bool[1];
h_itemsLeft[0] = 1;
bool* d_itemsLeft;
cudaMalloc((void**) &d_itemsLeft, sizeof(bool));
cudaMemset(d_itemsLeft, 0, sizeof(bool));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//Hash items
hashInputs<<<(numValues + 1023)/1024, 1024>>>(numValues, cqf, d_insertValues, d_quotientsArray);
//Sort by fingerprint
thrust::sort(d_quotients.begin(), d_quotients.end());
//Split fingerprints into quotients and remainders
quotienting<<<(numValues + 1023)/1024, 1024>>>(numValues, cqf.qbits, d_quotientsArray, d_remaindersArray);
//Compute block ID & write to region start array if first item in region
findBlockStartIndices<<<(numValues + 1023)/1024, 1024>>>(numValues, d_quotientsArray, d_blockStarts);
cudaMemcpy(d_nextItems, d_blockStarts, cqf.numBlocks * sizeof(unsigned int), cudaMemcpyDeviceToDevice);
/* unsigned int* h_printBlockHolder = new unsigned int[cqf.numBlocks];
cudaMemcpy(h_printBlockHolder, d_blockStarts, cqf.numBlocks * sizeof(unsigned int), cudaMemcpyDeviceToHost);
printf("blockStarts after kernel:\n");
for(int i = 0; i < cqf.numBlocks; i++){
printf("%i\t", h_printBlockHolder[i]);
}
printf("\n");
unsigned int* h_quotientsArray = new unsigned int[numValues];
cudaMemcpy(h_quotientsArray, d_quotientsArray, numValues * sizeof(unsigned int), cudaMemcpyDeviceToHost);
unsigned int* h_remaindersArray = new unsigned int[numValues];
cudaMemcpy(h_remaindersArray, d_remaindersArray, numValues * sizeof(unsigned int), cudaMemcpyDeviceToHost);
int numBlockItems = 0;
printf("numBlocks=%u\n", cqf.numBlocks);
for(int i = 0; i < cqf.numBlocks - 1; i++){
printf("\n***Block %i***:\n", i);
if(i == cqf.numBlocks - 2) numBlockItems = numValues - h_printBlockHolder[i];
else{
numBlockItems = h_printBlockHolder[i+1] - h_printBlockHolder[i];
}
if(h_printBlockHolder[i] == UINT_MAX) numBlockItems = 0;
for(int j = 0; j < numBlockItems; j++){
printf("quotient: %u\t remainder: %u\n", h_quotientsArray[h_printBlockHolder[i] + j], h_remaindersArray[h_printBlockHolder[i] + j]);
}
}
*/
//Loop over insert kernel
//If insert overflows, then next iteration has same region size, thread should return (all later items in the region will also overflow, since they are sorted)
int numIterations = 0;
int blocksPerRegion = 1;
int numRegions = cqf.numBlocks;
while(h_itemsLeft[0] == 1){
// printf("--------------------\niteration #: %i\n", numIterations);
numRegions = (cqf.numBlocks + blocksPerRegion - 1) / blocksPerRegion;
//Launch insert kernel with one thread per insert region
insertIntoRegions<<<(numRegions + 127)/128, 128>>>(numRegions, blocksPerRegion, numValues, cqf, d_blockStarts, d_nextItems, d_quotientsArray, d_remaindersArray, d_returnValues, d_itemsLeft);
cudaMemcpy(h_itemsLeft, d_itemsLeft, sizeof(bool), cudaMemcpyDeviceToHost);
cudaMemset(d_itemsLeft, 0, sizeof(bool));
numIterations++;
blocksPerRegion = numIterations / 16 + 1;
// printGPUFilter(&cqf);
}
cudaEventRecord(stop);
//Calculate and print timing results
cudaEventSynchronize(stop);
float insertTime = 0;
cudaEventElapsedTime(&insertTime, start, stop);
// printf("total iterations: %i\n", numIterations);
//Free memory
d_quotients.~device_vector<unsigned int>();
cudaFree(d_remaindersArray);
cudaFree(d_blockStarts);
cudaFree(d_nextItems);
delete[] h_itemsLeft;
cudaFree(d_itemsLeft);
return insertTime;
} | //RSQF.cuh
/*
* Copyright 2021 Regents of the University of California
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RSQF_GPU_H
#define RSQF_GPU_H
#define RBITS 5
#define SLOTS_PER_BLOCK 64
struct __attribute__ ((packed)) cqf_gpu_block
{
unsigned char offset;
long unsigned int occupieds;
long unsigned int runEnds;
long unsigned int remainders[RBITS];
};
struct countingQuotientFilterGPU
{
unsigned int qbits;
unsigned int numBlocks;
cqf_gpu_block* blocks;
};
__host__ __device__ size_t calcNumBlocksGPU(unsigned int q);
__host__ void initCQFGPU(struct countingQuotientFilterGPU *cqf, unsigned int q);
/* Allocates memory for the counting quotient filter on the GPU
* based on number of quotient bits.
* Filter Capacity = 2 ^ q */
__host__ void printGPUFilter(struct countingQuotientFilterGPU *cqf);
__device__ __host__ unsigned int Normal_APHashGPU(unsigned int value, unsigned int maxHashValue);
__host__ float launchLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* slotValuesArray);
/* Looks up value in RSQF.
* Hashes all inputs and sorts before performing lookups, then sorts again to match with inputs.
* Returns the location of the remainder in slotValuesArray if it is found.
* Returns -1 if the remainder is not found.
* Return value is time for CUDA code. */
__host__ float launchUnsortedLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* d_slotValuesArray);
/* Looks up value in RSQF.
* This operation generally has lower throughput than the sorted version.
* Returns the location of the remainder in slotValuesArray if it is found.
* Returns -1 if the remainder is not found.
* Return value is time for CUDA code. */
__host__ float insertGPU(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_insertValues, int* d_returnValues);
/* Inserts values into RSQF.
* Returns the final location of the remainders in d_returnValues.
* Return value is time for CUDA code. */
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //RSQF.cuh
/*
* Copyright 2021 Regents of the University of California
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RSQF_GPU_H
#define RSQF_GPU_H
#define RBITS 5
#define SLOTS_PER_BLOCK 64
struct __attribute__ ((packed)) cqf_gpu_block
{
unsigned char offset;
long unsigned int occupieds;
long unsigned int runEnds;
long unsigned int remainders[RBITS];
};
struct countingQuotientFilterGPU
{
unsigned int qbits;
unsigned int numBlocks;
cqf_gpu_block* blocks;
};
__host__ __device__ size_t calcNumBlocksGPU(unsigned int q);
__host__ void initCQFGPU(struct countingQuotientFilterGPU *cqf, unsigned int q);
/* Allocates memory for the counting quotient filter on the GPU
* based on number of quotient bits.
* Filter Capacity = 2 ^ q */
__host__ void printGPUFilter(struct countingQuotientFilterGPU *cqf);
__device__ __host__ unsigned int Normal_APHashGPU(unsigned int value, unsigned int maxHashValue);
__host__ float launchLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* slotValuesArray);
/* Looks up value in RSQF.
* Hashes all inputs and sorts before performing lookups, then sorts again to match with inputs.
* Returns the location of the remainder in slotValuesArray if it is found.
* Returns -1 if the remainder is not found.
* Return value is time for CUDA code. */
__host__ float launchUnsortedLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* d_slotValuesArray);
/* Looks up value in RSQF.
* This operation generally has lower throughput than the sorted version.
* Returns the location of the remainder in slotValuesArray if it is found.
* Returns -1 if the remainder is not found.
* Return value is time for CUDA code. */
__host__ float insertGPU(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_insertValues, int* d_returnValues);
/* Inserts values into RSQF.
* Returns the final location of the remainders in d_returnValues.
* Return value is time for CUDA code. */
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //RSQF.cuh
/*
* Copyright 2021 Regents of the University of California
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RSQF_GPU_H
#define RSQF_GPU_H
#define RBITS 5
#define SLOTS_PER_BLOCK 64
struct __attribute__ ((packed)) cqf_gpu_block
{
unsigned char offset;
long unsigned int occupieds;
long unsigned int runEnds;
long unsigned int remainders[RBITS];
};
struct countingQuotientFilterGPU
{
unsigned int qbits;
unsigned int numBlocks;
cqf_gpu_block* blocks;
};
__host__ __device__ size_t calcNumBlocksGPU(unsigned int q);
__host__ void initCQFGPU(struct countingQuotientFilterGPU *cqf, unsigned int q);
/* Allocates memory for the counting quotient filter on the GPU
* based on number of quotient bits.
* Filter Capacity = 2 ^ q */
__host__ void printGPUFilter(struct countingQuotientFilterGPU *cqf);
__device__ __host__ unsigned int Normal_APHashGPU(unsigned int value, unsigned int maxHashValue);
__host__ float launchLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* slotValuesArray);
/* Looks up value in RSQF.
* Hashes all inputs and sorts before performing lookups, then sorts again to match with inputs.
* Returns the location of the remainder in slotValuesArray if it is found.
* Returns -1 if the remainder is not found.
* Return value is time for CUDA code. */
__host__ float launchUnsortedLookups(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_lookupValues, int* d_slotValuesArray);
/* Looks up value in RSQF.
* This operation generally has lower throughput than the sorted version.
* Returns the location of the remainder in slotValuesArray if it is found.
* Returns -1 if the remainder is not found.
* Return value is time for CUDA code. */
__host__ float insertGPU(countingQuotientFilterGPU cqf, int numValues, unsigned int* d_insertValues, int* d_returnValues);
/* Inserts values into RSQF.
* Returns the final location of the remainders in d_returnValues.
* Return value is time for CUDA code. */
#endif | .text
.file "RSQF.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeOffsetOfMatrixB(const int32_t* row_sum, int32_t* output, int32_t N) {
for (int32_t i = threadIdx.x; i < N; i += blockDim.x) {
*(output + blockIdx.x * N + i) = -row_sum[blockIdx.x];
}
} | code for sm_80
Function : _Z22ComputeOffsetOfMatrixBPKiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0002 */
/*0080*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD R5, R7, c[0x0][0x170], RZ ; /* 0x00005c0007057a24 */
/* 0x001fca00078e02ff */
/*00a0*/ IADD3 R5, P0, R5, R0, RZ ; /* 0x0000000005057210 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R8, R0.reuse, RZ, 0x1, P0 ; /* 0x000000ff00087211 */
/* 0x040fe400000f0eff */
/*00c0*/ LEA R4, P0, R5.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x040fe400078010ff */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ LEA.HI.X R5, R5, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0005057a11 */
/* 0x000fe400000f1408 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x004fca00078e0a06 */
/*0110*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x80 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeOffsetOfMatrixB(const int32_t* row_sum, int32_t* output, int32_t N) {
for (int32_t i = threadIdx.x; i < N; i += blockDim.x) {
*(output + blockIdx.x * N + i) = -row_sum[blockIdx.x];
}
} | .file "tmpxft_0001b941_00000000-6_ComputeOffsetOfMatrixB.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii
.type _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii, @function
_Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22ComputeOffsetOfMatrixBPKiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii, .-_Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii
.globl _Z22ComputeOffsetOfMatrixBPKiPii
.type _Z22ComputeOffsetOfMatrixBPKiPii, @function
_Z22ComputeOffsetOfMatrixBPKiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22ComputeOffsetOfMatrixBPKiPii, .-_Z22ComputeOffsetOfMatrixBPKiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22ComputeOffsetOfMatrixBPKiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22ComputeOffsetOfMatrixBPKiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeOffsetOfMatrixB(const int32_t* row_sum, int32_t* output, int32_t N) {
for (int32_t i = threadIdx.x; i < N; i += blockDim.x) {
*(output + blockIdx.x * N + i) = -row_sum[blockIdx.x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeOffsetOfMatrixB(const int32_t* row_sum, int32_t* output, int32_t N) {
for (int32_t i = threadIdx.x; i < N; i += blockDim.x) {
*(output + blockIdx.x * N + i) = -row_sum[blockIdx.x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeOffsetOfMatrixB(const int32_t* row_sum, int32_t* output, int32_t N) {
for (int32_t i = threadIdx.x; i < N; i += blockDim.x) {
*(output + blockIdx.x * N + i) = -row_sum[blockIdx.x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22ComputeOffsetOfMatrixBPKiPii
.globl _Z22ComputeOffsetOfMatrixBPKiPii
.p2align 8
.type _Z22ComputeOffsetOfMatrixBPKiPii,@function
_Z22ComputeOffsetOfMatrixBPKiPii:
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x24
s_mov_b32 s2, s15
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_mul_i32 s2, s15, s6
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s0
s_addc_u32 s5, s9, s1
s_lshl_b64 s[8:9], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s1, s10, s8
s_addc_u32 s2, s11, s9
s_and_b32 s7, s7, 0xffff
.p2align 6
.LBB0_2:
global_load_b32 v5, v2, s[4:5]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_cmp_le_i32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s1, v3
v_add_co_ci_u32_e64 v4, s0, s2, v4, s0
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, 0, v5
global_store_b32 v[3:4], v1, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22ComputeOffsetOfMatrixBPKiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22ComputeOffsetOfMatrixBPKiPii, .Lfunc_end0-_Z22ComputeOffsetOfMatrixBPKiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22ComputeOffsetOfMatrixBPKiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22ComputeOffsetOfMatrixBPKiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeOffsetOfMatrixB(const int32_t* row_sum, int32_t* output, int32_t N) {
for (int32_t i = threadIdx.x; i < N; i += blockDim.x) {
*(output + blockIdx.x * N + i) = -row_sum[blockIdx.x];
}
} | .text
.file "ComputeOffsetOfMatrixB.hip"
.globl _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii # -- Begin function _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.p2align 4, 0x90
.type _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii,@function
_Z37__device_stub__ComputeOffsetOfMatrixBPKiPii: # @_Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22ComputeOffsetOfMatrixBPKiPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii, .Lfunc_end0-_Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22ComputeOffsetOfMatrixBPKiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22ComputeOffsetOfMatrixBPKiPii,@object # @_Z22ComputeOffsetOfMatrixBPKiPii
.section .rodata,"a",@progbits
.globl _Z22ComputeOffsetOfMatrixBPKiPii
.p2align 3, 0x0
_Z22ComputeOffsetOfMatrixBPKiPii:
.quad _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.size _Z22ComputeOffsetOfMatrixBPKiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22ComputeOffsetOfMatrixBPKiPii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22ComputeOffsetOfMatrixBPKiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22ComputeOffsetOfMatrixBPKiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0002 */
/*0080*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD R5, R7, c[0x0][0x170], RZ ; /* 0x00005c0007057a24 */
/* 0x001fca00078e02ff */
/*00a0*/ IADD3 R5, P0, R5, R0, RZ ; /* 0x0000000005057210 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R8, R0.reuse, RZ, 0x1, P0 ; /* 0x000000ff00087211 */
/* 0x040fe400000f0eff */
/*00c0*/ LEA R4, P0, R5.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x040fe400078010ff */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ LEA.HI.X R5, R5, c[0x0][0x16c], R8, 0x2, P0 ; /* 0x00005b0005057a11 */
/* 0x000fe400000f1408 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x004fca00078e0a06 */
/*0110*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x80 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22ComputeOffsetOfMatrixBPKiPii
.globl _Z22ComputeOffsetOfMatrixBPKiPii
.p2align 8
.type _Z22ComputeOffsetOfMatrixBPKiPii,@function
_Z22ComputeOffsetOfMatrixBPKiPii:
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x24
s_mov_b32 s2, s15
s_mov_b32 s3, 0
v_mov_b32_e32 v2, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_mul_i32 s2, s15, s6
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s0
s_addc_u32 s5, s9, s1
s_lshl_b64 s[8:9], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s1, s10, s8
s_addc_u32 s2, s11, s9
s_and_b32 s7, s7, 0xffff
.p2align 6
.LBB0_2:
global_load_b32 v5, v2, s[4:5]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_cmp_le_i32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s1, v3
v_add_co_ci_u32_e64 v4, s0, s2, v4, s0
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, 0, v5
global_store_b32 v[3:4], v1, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22ComputeOffsetOfMatrixBPKiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22ComputeOffsetOfMatrixBPKiPii, .Lfunc_end0-_Z22ComputeOffsetOfMatrixBPKiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22ComputeOffsetOfMatrixBPKiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22ComputeOffsetOfMatrixBPKiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b941_00000000-6_ComputeOffsetOfMatrixB.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii
.type _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii, @function
_Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22ComputeOffsetOfMatrixBPKiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii, .-_Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii
.globl _Z22ComputeOffsetOfMatrixBPKiPii
.type _Z22ComputeOffsetOfMatrixBPKiPii, @function
_Z22ComputeOffsetOfMatrixBPKiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22ComputeOffsetOfMatrixBPKiPiiPKiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22ComputeOffsetOfMatrixBPKiPii, .-_Z22ComputeOffsetOfMatrixBPKiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22ComputeOffsetOfMatrixBPKiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22ComputeOffsetOfMatrixBPKiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeOffsetOfMatrixB.hip"
.globl _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii # -- Begin function _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.p2align 4, 0x90
.type _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii,@function
_Z37__device_stub__ComputeOffsetOfMatrixBPKiPii: # @_Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22ComputeOffsetOfMatrixBPKiPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii, .Lfunc_end0-_Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22ComputeOffsetOfMatrixBPKiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22ComputeOffsetOfMatrixBPKiPii,@object # @_Z22ComputeOffsetOfMatrixBPKiPii
.section .rodata,"a",@progbits
.globl _Z22ComputeOffsetOfMatrixBPKiPii
.p2align 3, 0x0
_Z22ComputeOffsetOfMatrixBPKiPii:
.quad _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.size _Z22ComputeOffsetOfMatrixBPKiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22ComputeOffsetOfMatrixBPKiPii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__ComputeOffsetOfMatrixBPKiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22ComputeOffsetOfMatrixBPKiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Last name: Gupta
* First name: Vaibhav
* Net ID: vvg239
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
void seq_gen_primes(int);
__global__ void gen_primes(bool*, unsigned int, int);
void gpu_gen_primes(unsigned int);
int main(int argc, char * argv[])
{
int N;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc == 2)
{
N = atoi(argv[1]);
}
else
{
printf("Please give a value for N\n");
}
start = clock();
gpu_gen_primes(N);
end = clock();
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n","GPU", time_taken);
}
/******************** The GPU parallel version **************/
void gpu_gen_primes(unsigned int N)
{
FILE * fPtr;
char fileName[15];
sprintf(fileName, "%d", N);
strcat(fileName, ".txt");
fPtr = fopen(fileName, "w");
int size = (N+1) * sizeof(bool);
bool * n_series;
cudaMallocManaged((void**) &n_series, size);
int last_divisor = (N+1)/2;
for(int divisor = 2; divisor < last_divisor; divisor++) {
if(n_series[divisor]) continue;
int num_threads = 512;
int num_blocks = N/(divisor*num_threads) + 1;
gen_primes<<<num_blocks, num_threads>>>(n_series, N, divisor);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess) {
printf("CUDA error %s \n", cudaGetErrorString(error));
break;
}
}
int i;
for(i = 2; i < N+1; i++)
{
if(!n_series[i]) {
fprintf(fPtr, "%d ", i);
}
}
fprintf(fPtr, "\n");
cudaFree(n_series);
}
__global__
void gen_primes(bool* n_series, unsigned int N, int divisor) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int e = divisor*(i+2);
if(e <= N) {
n_series[e] = true;
}
} | code for sm_80
Function : _Z10gen_primesPbji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fca0007ffe0ff */
/*0050*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x000fca00078e02ff */
/*0060*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fe400000f0eff */
/*00c0*/ PRMT R0, R4, 0x7610, R0 ; /* 0x0000761004007816 */
/* 0x000fca0000000000 */
/*00d0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Last name: Gupta
* First name: Vaibhav
* Net ID: vvg239
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
void seq_gen_primes(int);
__global__ void gen_primes(bool*, unsigned int, int);
void gpu_gen_primes(unsigned int);
int main(int argc, char * argv[])
{
int N;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc == 2)
{
N = atoi(argv[1]);
}
else
{
printf("Please give a value for N\n");
}
start = clock();
gpu_gen_primes(N);
end = clock();
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n","GPU", time_taken);
}
/******************** The GPU parallel version **************/
void gpu_gen_primes(unsigned int N)
{
FILE * fPtr;
char fileName[15];
sprintf(fileName, "%d", N);
strcat(fileName, ".txt");
fPtr = fopen(fileName, "w");
int size = (N+1) * sizeof(bool);
bool * n_series;
cudaMallocManaged((void**) &n_series, size);
int last_divisor = (N+1)/2;
for(int divisor = 2; divisor < last_divisor; divisor++) {
if(n_series[divisor]) continue;
int num_threads = 512;
int num_blocks = N/(divisor*num_threads) + 1;
gen_primes<<<num_blocks, num_threads>>>(n_series, N, divisor);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess) {
printf("CUDA error %s \n", cudaGetErrorString(error));
break;
}
}
int i;
for(i = 2; i < N+1; i++)
{
if(!n_series[i]) {
fprintf(fPtr, "%d ", i);
}
}
fprintf(fPtr, "\n");
cudaFree(n_series);
}
__global__
void gen_primes(bool* n_series, unsigned int N, int divisor) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int e = divisor*(i+2);
if(e <= N) {
n_series[e] = true;
}
} | .file "tmpxft_000c5912_00000000-6_genprimes_unified_mem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10gen_primesPbjiPbji
.type _Z32__device_stub__Z10gen_primesPbjiPbji, @function
_Z32__device_stub__Z10gen_primesPbjiPbji:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10gen_primesPbji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z10gen_primesPbjiPbji, .-_Z32__device_stub__Z10gen_primesPbjiPbji
.globl _Z10gen_primesPbji
.type _Z10gen_primesPbji, @function
_Z10gen_primesPbji:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10gen_primesPbjiPbji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10gen_primesPbji, .-_Z10gen_primesPbji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string ".txt"
.LC2:
.string "w"
.LC3:
.string "CUDA error %s \n"
.LC4:
.string "%d "
.LC5:
.string "\n"
.text
.globl _Z14gpu_gen_primesj
.type _Z14gpu_gen_primesj, @function
_Z14gpu_gen_primesj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 41(%rsp), %rbx
movl %edi, %r8d
leaq .LC0(%rip), %rcx
movl $15, %edx
movl $2, %esi
movq %rbx, %rdi
call __sprintf_chk@PLT
movl $15, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r12
leal 1(%rbp), %r13d
movslq %r13d, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl %r13d, %r14d
shrl %r14d
cmpl $5, %r13d
jbe .L12
movl %r14d, %r14d
movl $2, %ebx
jmp .L17
.L14:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
.L13:
addq $1, %rbx
cmpq %r14, %rbx
je .L12
.L17:
movq 8(%rsp), %rax
cmpb $0, (%rax,%rbx)
jne .L13
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, %ecx
sall $9, %ecx
movl %ebp, %eax
movl $0, %edx
divl %ecx
addl $1, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %ebx, %edx
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10gen_primesPbjiPbji
jmp .L14
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
leal 1(%rbp), %ebp
movl $2, %ebx
leaq .LC4(%rip), %r14
cmpl $2, %r13d
ja .L19
.L16:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
addq $1, %rbx
cmpq %rbp, %rbx
je .L16
.L19:
movq 8(%rsp), %rax
cmpb $0, (%rax,%rbx)
jne .L18
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14gpu_gen_primesj, .-_Z14gpu_gen_primesj
.section .rodata.str1.1
.LC6:
.string "Please give a value for N\n"
.LC8:
.string "GPU"
.LC9:
.string "Time taken for %s is %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $2, %edi
je .L31
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L29:
call clock@PLT
movq %rax, %rbx
movl %ebp, %edi
call _Z14gpu_gen_primesj
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L29
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10gen_primesPbji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gen_primesPbji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Last name: Gupta
* First name: Vaibhav
* Net ID: vvg239
*
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
void seq_gen_primes(int);
__global__ void gen_primes(bool*, unsigned int, int);
void gpu_gen_primes(unsigned int);
int main(int argc, char * argv[])
{
int N;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc == 2)
{
N = atoi(argv[1]);
}
else
{
printf("Please give a value for N\n");
}
start = clock();
gpu_gen_primes(N);
end = clock();
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n","GPU", time_taken);
}
/******************** The GPU parallel version **************/
void gpu_gen_primes(unsigned int N)
{
FILE * fPtr;
char fileName[15];
sprintf(fileName, "%d", N);
strcat(fileName, ".txt");
fPtr = fopen(fileName, "w");
int size = (N+1) * sizeof(bool);
bool * n_series;
cudaMallocManaged((void**) &n_series, size);
int last_divisor = (N+1)/2;
for(int divisor = 2; divisor < last_divisor; divisor++) {
if(n_series[divisor]) continue;
int num_threads = 512;
int num_blocks = N/(divisor*num_threads) + 1;
gen_primes<<<num_blocks, num_threads>>>(n_series, N, divisor);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess) {
printf("CUDA error %s \n", cudaGetErrorString(error));
break;
}
}
int i;
for(i = 2; i < N+1; i++)
{
if(!n_series[i]) {
fprintf(fPtr, "%d ", i);
}
}
fprintf(fPtr, "\n");
cudaFree(n_series);
}
__global__
void gen_primes(bool* n_series, unsigned int N, int divisor) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int e = divisor*(i+2);
if(e <= N) {
n_series[e] = true;
}
} | /*
* Last name: Gupta
* First name: Vaibhav
* Net ID: vvg239
*
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
void seq_gen_primes(int);
__global__ void gen_primes(bool*, unsigned int, int);
void gpu_gen_primes(unsigned int);
int main(int argc, char * argv[])
{
int N;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc == 2)
{
N = atoi(argv[1]);
}
else
{
printf("Please give a value for N\n");
}
start = clock();
gpu_gen_primes(N);
end = clock();
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n","GPU", time_taken);
}
/******************** The GPU parallel version **************/
void gpu_gen_primes(unsigned int N)
{
FILE * fPtr;
char fileName[15];
sprintf(fileName, "%d", N);
strcat(fileName, ".txt");
fPtr = fopen(fileName, "w");
int size = (N+1) * sizeof(bool);
bool * n_series;
hipMallocManaged((void**) &n_series, size);
int last_divisor = (N+1)/2;
for(int divisor = 2; divisor < last_divisor; divisor++) {
if(n_series[divisor]) continue;
int num_threads = 512;
int num_blocks = N/(divisor*num_threads) + 1;
gen_primes<<<num_blocks, num_threads>>>(n_series, N, divisor);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error != hipSuccess) {
printf("CUDA error %s \n", hipGetErrorString(error));
break;
}
}
int i;
for(i = 2; i < N+1; i++)
{
if(!n_series[i]) {
fprintf(fPtr, "%d ", i);
}
}
fprintf(fPtr, "\n");
hipFree(n_series);
}
__global__
void gen_primes(bool* n_series, unsigned int N, int divisor) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int e = divisor*(i+2);
if(e <= N) {
n_series[e] = true;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Last name: Gupta
* First name: Vaibhav
* Net ID: vvg239
*
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
void seq_gen_primes(int);
__global__ void gen_primes(bool*, unsigned int, int);
void gpu_gen_primes(unsigned int);
int main(int argc, char * argv[])
{
int N;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc == 2)
{
N = atoi(argv[1]);
}
else
{
printf("Please give a value for N\n");
}
start = clock();
gpu_gen_primes(N);
end = clock();
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n","GPU", time_taken);
}
/******************** The GPU parallel version **************/
void gpu_gen_primes(unsigned int N)
{
FILE * fPtr;
char fileName[15];
sprintf(fileName, "%d", N);
strcat(fileName, ".txt");
fPtr = fopen(fileName, "w");
int size = (N+1) * sizeof(bool);
bool * n_series;
hipMallocManaged((void**) &n_series, size);
int last_divisor = (N+1)/2;
for(int divisor = 2; divisor < last_divisor; divisor++) {
if(n_series[divisor]) continue;
int num_threads = 512;
int num_blocks = N/(divisor*num_threads) + 1;
gen_primes<<<num_blocks, num_threads>>>(n_series, N, divisor);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error != hipSuccess) {
printf("CUDA error %s \n", hipGetErrorString(error));
break;
}
}
int i;
for(i = 2; i < N+1; i++)
{
if(!n_series[i]) {
fprintf(fPtr, "%d ", i);
}
}
fprintf(fPtr, "\n");
hipFree(n_series);
}
__global__
void gen_primes(bool* n_series, unsigned int N, int divisor) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int e = divisor*(i+2);
if(e <= N) {
n_series[e] = true;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gen_primesPbji
.globl _Z10gen_primesPbji
.p2align 8
.type _Z10gen_primesPbji,@function
_Z10gen_primesPbji:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add3_u32 v0, v0, s15, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s3
v_cmp_ge_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gen_primesPbji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gen_primesPbji, .Lfunc_end0-_Z10gen_primesPbji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gen_primesPbji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gen_primesPbji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Last name: Gupta
* First name: Vaibhav
* Net ID: vvg239
*
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
void seq_gen_primes(int);
__global__ void gen_primes(bool*, unsigned int, int);
void gpu_gen_primes(unsigned int);
int main(int argc, char * argv[])
{
int N;
// to measure time taken by a specific part of the code
double time_taken;
clock_t start, end;
if(argc == 2)
{
N = atoi(argv[1]);
}
else
{
printf("Please give a value for N\n");
}
start = clock();
gpu_gen_primes(N);
end = clock();
time_taken = ((double)(end - start))/ CLOCKS_PER_SEC;
printf("Time taken for %s is %lf\n","GPU", time_taken);
}
/******************** The GPU parallel version **************/
void gpu_gen_primes(unsigned int N)
{
FILE * fPtr;
char fileName[15];
sprintf(fileName, "%d", N);
strcat(fileName, ".txt");
fPtr = fopen(fileName, "w");
int size = (N+1) * sizeof(bool);
bool * n_series;
hipMallocManaged((void**) &n_series, size);
int last_divisor = (N+1)/2;
for(int divisor = 2; divisor < last_divisor; divisor++) {
if(n_series[divisor]) continue;
int num_threads = 512;
int num_blocks = N/(divisor*num_threads) + 1;
gen_primes<<<num_blocks, num_threads>>>(n_series, N, divisor);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error != hipSuccess) {
printf("CUDA error %s \n", hipGetErrorString(error));
break;
}
}
int i;
for(i = 2; i < N+1; i++)
{
if(!n_series[i]) {
fprintf(fPtr, "%d ", i);
}
}
fprintf(fPtr, "\n");
hipFree(n_series);
}
__global__
void gen_primes(bool* n_series, unsigned int N, int divisor) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int e = divisor*(i+2);
if(e <= N) {
n_series[e] = true;
}
} | .text
.file "genprimes_unified_mem.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $2, %edi
jne .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB0_3
.LBB0_2:
movl $.Lstr, %edi
callq puts@PLT
# implicit-def: $ebx
.LBB0_3:
callq clock
movq %rax, %r14
movl %ebx, %edi
callq _Z14gpu_gen_primesj
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z14gpu_gen_primesj # -- Begin function _Z14gpu_gen_primesj
.p2align 4, 0x90
.type _Z14gpu_gen_primesj,@function
_Z14gpu_gen_primesj: # @_Z14gpu_gen_primesj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r14d
leaq 81(%rsp), %rbx
movl $.L.str.3, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq sprintf
movq %rbx, %rdi
callq strlen@PLT
movl $1954051118, 81(%rsp,%rax) # imm = 0x7478742E
movb $0, 85(%rsp,%rax)
movl $.L.str.5, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
leal 1(%r14), %eax
movl %eax, 4(%rsp) # 4-byte Spill
movslq %eax, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
cmpl $6, %r15d
jb .LBB1_8
# %bb.1: # %.lr.ph
movabsq $4294967296, %rcx # imm = 0x100000000
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, %r13d
shrl %r13d
movl $2, %r12d
movl $1024, %ebp # imm = 0x400
leaq 512(%rcx), %r15
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
.LBB1_7: # %.critedge
# in Loop: Header=BB1_2 Depth=1
incq %r12
addl $512, %ebp # imm = 0x200
cmpq %r12, %r13
je .LBB1_8
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
cmpb $0, (%rax,%r12)
jne .LBB1_7
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
xorl %edx, %edx
divl %ebp
# kill: def $eax killed $eax def $rax
leal 1(%rax), %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r14d, 20(%rsp)
movl %r12d, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10gen_primesPbji, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_8: # %.loopexit
movl 4(%rsp), %eax # 4-byte Reload
cmpl $3, %eax
jb .LBB1_13
# %bb.9: # %.lr.ph38.preheader
movl %eax, %r15d
movl $2, %r14d
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
incq %r14
cmpq %r14, %r15
je .LBB1_13
.LBB1_10: # %.lr.ph38
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
cmpb $0, (%rax,%r14)
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movl $.L.str.7, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.LBB1_13: # %._crit_edge
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14gpu_gen_primesj, .Lfunc_end1-_Z14gpu_gen_primesj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__gen_primesPbji # -- Begin function _Z25__device_stub__gen_primesPbji
.p2align 4, 0x90
.type _Z25__device_stub__gen_primesPbji,@function
_Z25__device_stub__gen_primesPbji: # @_Z25__device_stub__gen_primesPbji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10gen_primesPbji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z25__device_stub__gen_primesPbji, .Lfunc_end2-_Z25__device_stub__gen_primesPbji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gen_primesPbji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Time taken for %s is %lf\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ".txt"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type _Z10gen_primesPbji,@object # @_Z10gen_primesPbji
.section .rodata,"a",@progbits
.globl _Z10gen_primesPbji
.p2align 3, 0x0
_Z10gen_primesPbji:
.quad _Z25__device_stub__gen_primesPbji
.size _Z10gen_primesPbji, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "CUDA error %s \n"
.size .L.str.6, 16
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d "
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gen_primesPbji"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please give a value for N"
.size .Lstr, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gen_primesPbji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gen_primesPbji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10gen_primesPbji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fca0007ffe0ff */
/*0050*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x000fca00078e02ff */
/*0060*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fe400000f0eff */
/*00c0*/ PRMT R0, R4, 0x7610, R0 ; /* 0x0000761004007816 */
/* 0x000fca0000000000 */
/*00d0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gen_primesPbji
.globl _Z10gen_primesPbji
.p2align 8
.type _Z10gen_primesPbji,@function
_Z10gen_primesPbji:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add3_u32 v0, v0, s15, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s3
v_cmp_ge_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gen_primesPbji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gen_primesPbji, .Lfunc_end0-_Z10gen_primesPbji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gen_primesPbji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gen_primesPbji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c5912_00000000-6_genprimes_unified_mem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10gen_primesPbjiPbji
.type _Z32__device_stub__Z10gen_primesPbjiPbji, @function
_Z32__device_stub__Z10gen_primesPbjiPbji:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10gen_primesPbji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z10gen_primesPbjiPbji, .-_Z32__device_stub__Z10gen_primesPbjiPbji
.globl _Z10gen_primesPbji
.type _Z10gen_primesPbji, @function
_Z10gen_primesPbji:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10gen_primesPbjiPbji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10gen_primesPbji, .-_Z10gen_primesPbji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string ".txt"
.LC2:
.string "w"
.LC3:
.string "CUDA error %s \n"
.LC4:
.string "%d "
.LC5:
.string "\n"
.text
.globl _Z14gpu_gen_primesj
.type _Z14gpu_gen_primesj, @function
_Z14gpu_gen_primesj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 41(%rsp), %rbx
movl %edi, %r8d
leaq .LC0(%rip), %rcx
movl $15, %edx
movl $2, %esi
movq %rbx, %rdi
call __sprintf_chk@PLT
movl $15, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r12
leal 1(%rbp), %r13d
movslq %r13d, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl %r13d, %r14d
shrl %r14d
cmpl $5, %r13d
jbe .L12
movl %r14d, %r14d
movl $2, %ebx
jmp .L17
.L14:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L25
.L13:
addq $1, %rbx
cmpq %r14, %rbx
je .L12
.L17:
movq 8(%rsp), %rax
cmpb $0, (%rax,%rbx)
jne .L13
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, %ecx
sall $9, %ecx
movl %ebp, %eax
movl $0, %edx
divl %ecx
addl $1, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %ebx, %edx
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10gen_primesPbjiPbji
jmp .L14
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
leal 1(%rbp), %ebp
movl $2, %ebx
leaq .LC4(%rip), %r14
cmpl $2, %r13d
ja .L19
.L16:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
addq $1, %rbx
cmpq %rbp, %rbx
je .L16
.L19:
movq 8(%rsp), %rax
cmpb $0, (%rax,%rbx)
jne .L18
movl %ebx, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14gpu_gen_primesj, .-_Z14gpu_gen_primesj
.section .rodata.str1.1
.LC6:
.string "Please give a value for N\n"
.LC8:
.string "GPU"
.LC9:
.string "Time taken for %s is %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $2, %edi
je .L31
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L29:
call clock@PLT
movq %rax, %rbx
movl %ebp, %edi
call _Z14gpu_gen_primesj
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L29
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10gen_primesPbji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gen_primesPbji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "genprimes_unified_mem.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $2, %edi
jne .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB0_3
.LBB0_2:
movl $.Lstr, %edi
callq puts@PLT
# implicit-def: $ebx
.LBB0_3:
callq clock
movq %rax, %r14
movl %ebx, %edi
callq _Z14gpu_gen_primesj
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movb $1, %al
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z14gpu_gen_primesj # -- Begin function _Z14gpu_gen_primesj
.p2align 4, 0x90
.type _Z14gpu_gen_primesj,@function
_Z14gpu_gen_primesj: # @_Z14gpu_gen_primesj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r14d
leaq 81(%rsp), %rbx
movl $.L.str.3, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq sprintf
movq %rbx, %rdi
callq strlen@PLT
movl $1954051118, 81(%rsp,%rax) # imm = 0x7478742E
movb $0, 85(%rsp,%rax)
movl $.L.str.5, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
leal 1(%r14), %eax
movl %eax, 4(%rsp) # 4-byte Spill
movslq %eax, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
cmpl $6, %r15d
jb .LBB1_8
# %bb.1: # %.lr.ph
movabsq $4294967296, %rcx # imm = 0x100000000
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, %r13d
shrl %r13d
movl $2, %r12d
movl $1024, %ebp # imm = 0x400
leaq 512(%rcx), %r15
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
.LBB1_7: # %.critedge
# in Loop: Header=BB1_2 Depth=1
incq %r12
addl $512, %ebp # imm = 0x200
cmpq %r12, %r13
je .LBB1_8
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
cmpb $0, (%rax,%r12)
jne .LBB1_7
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
xorl %edx, %edx
divl %ebp
# kill: def $eax killed $eax def $rax
leal 1(%rax), %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r14d, 20(%rsp)
movl %r12d, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10gen_primesPbji, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_8: # %.loopexit
movl 4(%rsp), %eax # 4-byte Reload
cmpl $3, %eax
jb .LBB1_13
# %bb.9: # %.lr.ph38.preheader
movl %eax, %r15d
movl $2, %r14d
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
incq %r14
cmpq %r14, %r15
je .LBB1_13
.LBB1_10: # %.lr.ph38
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
cmpb $0, (%rax,%r14)
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movl $.L.str.7, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.LBB1_13: # %._crit_edge
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
movq 8(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14gpu_gen_primesj, .Lfunc_end1-_Z14gpu_gen_primesj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__gen_primesPbji # -- Begin function _Z25__device_stub__gen_primesPbji
.p2align 4, 0x90
.type _Z25__device_stub__gen_primesPbji,@function
_Z25__device_stub__gen_primesPbji: # @_Z25__device_stub__gen_primesPbji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10gen_primesPbji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z25__device_stub__gen_primesPbji, .Lfunc_end2-_Z25__device_stub__gen_primesPbji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gen_primesPbji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Time taken for %s is %lf\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ".txt"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type _Z10gen_primesPbji,@object # @_Z10gen_primesPbji
.section .rodata,"a",@progbits
.globl _Z10gen_primesPbji
.p2align 3, 0x0
_Z10gen_primesPbji:
.quad _Z25__device_stub__gen_primesPbji
.size _Z10gen_primesPbji, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "CUDA error %s \n"
.size .L.str.6, 16
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d "
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gen_primesPbji"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please give a value for N"
.size .Lstr, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gen_primesPbji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gen_primesPbji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuSubPixelOffset_kernel(const int2 *offsetInit, const int2 *offsetZoomIn, float2 *offsetFinal, const float OSratio, const float xoffset, const float yoffset, const int size)
{
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx >= size) return;
offsetFinal[idx].x = OSratio*(offsetZoomIn[idx].x ) + offsetInit[idx].x - xoffset;
offsetFinal[idx].y = OSratio*(offsetZoomIn[idx].y ) + offsetInit[idx].y - yoffset;
} | code for sm_80
Function : _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x184], PT ; /* 0x0000610006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R11, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e020b */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004ff00000201400 */
/*00d0*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x008e240000201400 */
/*00e0*/ FFMA R9, R0, c[0x0][0x178], R7 ; /* 0x00005e0000097a23 */
/* 0x001fc40000000007 */
/*00f0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e020b */
/*0100*/ FADD R9, R9, -c[0x0][0x17c] ; /* 0x80005f0009097621 */
/* 0x000fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0120*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004ff00000201400 */
/*0150*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x008e240000201400 */
/*0160*/ FFMA R12, R10, c[0x0][0x178], R11 ; /* 0x00005e000a0c7a23 */
/* 0x001fc8000000000b */
/*0170*/ FADD R13, R12, -c[0x0][0x180] ; /* 0x800060000c0d7621 */
/* 0x000fca0000000000 */
/*0180*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuSubPixelOffset_kernel(const int2 *offsetInit, const int2 *offsetZoomIn, float2 *offsetFinal, const float OSratio, const float xoffset, const float yoffset, const int size)
{
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx >= size) return;
offsetFinal[idx].x = OSratio*(offsetZoomIn[idx].x ) + offsetInit[idx].x - xoffset;
offsetFinal[idx].y = OSratio*(offsetZoomIn[idx].y ) + offsetInit[idx].y - yoffset;
} | .file "tmpxft_00087965_00000000-6_cuSubPixelOffset_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi
.type _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi, @function
_Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi, .-_Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi
.globl _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi
.type _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi, @function
_Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi, .-_Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuSubPixelOffset_kernel(const int2 *offsetInit, const int2 *offsetZoomIn, float2 *offsetFinal, const float OSratio, const float xoffset, const float yoffset, const int size)
{
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx >= size) return;
offsetFinal[idx].x = OSratio*(offsetZoomIn[idx].x ) + offsetInit[idx].x - xoffset;
offsetFinal[idx].y = OSratio*(offsetZoomIn[idx].y ) + offsetInit[idx].y - yoffset;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuSubPixelOffset_kernel(const int2 *offsetInit, const int2 *offsetZoomIn, float2 *offsetFinal, const float OSratio, const float xoffset, const float yoffset, const int size)
{
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx >= size) return;
offsetFinal[idx].x = OSratio*(offsetZoomIn[idx].x ) + offsetInit[idx].x - xoffset;
offsetFinal[idx].y = OSratio*(offsetZoomIn[idx].y ) + offsetInit[idx].y - yoffset;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuSubPixelOffset_kernel(const int2 *offsetInit, const int2 *offsetZoomIn, float2 *offsetFinal, const float OSratio, const float xoffset, const float yoffset, const int size)
{
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx >= size) return;
offsetFinal[idx].x = OSratio*(offsetZoomIn[idx].x ) + offsetInit[idx].x - xoffset;
offsetFinal[idx].y = OSratio*(offsetZoomIn[idx].y ) + offsetInit[idx].y - yoffset;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.globl _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.p2align 8
.type _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi,@function
_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v6, v6
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, s10, v6
v_subrev_f32_e32 v6, s11, v7
global_store_b32 v[0:1], v6, off
global_load_b32 v2, v[2:3], off offset:4
global_load_b32 v3, v[4:5], off offset:4
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, s10, v2
v_subrev_f32_e32 v2, s0, v3
global_store_b32 v[0:1], v2, off offset:4
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, .Lfunc_end0-_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuSubPixelOffset_kernel(const int2 *offsetInit, const int2 *offsetZoomIn, float2 *offsetFinal, const float OSratio, const float xoffset, const float yoffset, const int size)
{
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx >= size) return;
offsetFinal[idx].x = OSratio*(offsetZoomIn[idx].x ) + offsetInit[idx].x - xoffset;
offsetFinal[idx].y = OSratio*(offsetZoomIn[idx].y ) + offsetInit[idx].y - yoffset;
} | .text
.file "cuSubPixelOffset_kernel.hip"
.globl _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi # -- Begin function _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.p2align 4, 0x90
.type _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi,@function
_Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi: # @_Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, .Lfunc_end0-_Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi,@object # @_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.section .rodata,"a",@progbits
.globl _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.p2align 3, 0x0
_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi:
.quad _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.size _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi"
.size .L__unnamed_1, 71
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x184], PT ; /* 0x0000610006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R11, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD.WIDE R4, R6, R11, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe200078e020b */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x004ff00000201400 */
/*00d0*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x008e240000201400 */
/*00e0*/ FFMA R9, R0, c[0x0][0x178], R7 ; /* 0x00005e0000097a23 */
/* 0x001fc40000000007 */
/*00f0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e020b */
/*0100*/ FADD R9, R9, -c[0x0][0x17c] ; /* 0x80005f0009097621 */
/* 0x000fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0120*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004ff00000201400 */
/*0150*/ I2F R11, R11 ; /* 0x0000000b000b7306 */
/* 0x008e240000201400 */
/*0160*/ FFMA R12, R10, c[0x0][0x178], R11 ; /* 0x00005e000a0c7a23 */
/* 0x001fc8000000000b */
/*0170*/ FADD R13, R12, -c[0x0][0x180] ; /* 0x800060000c0d7621 */
/* 0x000fca0000000000 */
/*0180*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.globl _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.p2align 8
.type _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi,@function
_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v6, v6
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, s10, v6
v_subrev_f32_e32 v6, s11, v7
global_store_b32 v[0:1], v6, off
global_load_b32 v2, v[2:3], off offset:4
global_load_b32 v3, v[4:5], off offset:4
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, s10, v2
v_subrev_f32_e32 v2, s0, v3
global_store_b32 v[0:1], v2, off offset:4
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, .Lfunc_end0-_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00087965_00000000-6_cuSubPixelOffset_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi
.type _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi, @function
_Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi, .-_Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi
.globl _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi
.type _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi, @function
_Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z63__device_stub__Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffiPK4int2S1_P6float2fffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi, .-_Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuSubPixelOffset_kernelPK4int2S1_P6float2fffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuSubPixelOffset_kernel.hip"
.globl _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi # -- Begin function _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.p2align 4, 0x90
.type _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi,@function
_Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi: # @_Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, .Lfunc_end0-_Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi,@object # @_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.section .rodata,"a",@progbits
.globl _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.p2align 3, 0x0
_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi:
.quad _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.size _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi"
.size .L__unnamed_1, 71
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cuSubPixelOffset_kernelPK15HIP_vector_typeIiLj2EES2_PS_IfLj2EEfffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Template code for convolution. CS6023, IITM */
#include<stdio.h>
#include<cuda.h>
#include<math.h>
#define W 1024 // Input DIM
#define OW (W-4) // Output DIM
#define D 8 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define BLOCK_DIM_Z 8
#define BLOCK_DIM_Y 8
#define BLOCK_DIM_X 8
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(float *kernel){
float (*t)[T][T][D]=(float (*)[T][T][D])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l]=fmod(-(i+1)*2.1+(j+1)*3.2-(k+1)*4.8+(l+1)*7.1,1.0);
}
}
}
}
}
void print_matrix_to_file(float *m){
const char *fname = "assignment4_out";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++)
for(unsigned k=0;k<OW;k++)
fprintf(f,"%4.4f ", mat[i][j][k]);
fprintf(f,"\n");
}
fclose(f);
}
__global__ void convolution_3d(unsigned char *matrix,float* kernel,float *output){
__shared__ float s_matrix[BLOCK_DIM_Z+(T-1)][BLOCK_DIM_Y+(T-1)][D]; /* Shared memory for the matrix values */
__shared__ float s_conv[BLOCK_DIM_Z][BLOCK_DIM_Y][BLOCK_DIM_X];
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
int gid_x = blockDim.x*bx+tx;
int gid_y = blockDim.y*by+ty;
int gid_z = blockDim.z*bz+tz;
int num_tasks = D/BLOCK_DIM_X;
s_conv[tz][ty][tx] = 0;
for(int k=0;k<(T-1)/2;k++){
for(int i=0;i<(T-1)/2;i++){
for(int j=0;j<num_tasks;j++){
if( ((ty+i*BLOCK_DIM_Y) < (BLOCK_DIM_Y+T-1)) && (tz+k*BLOCK_DIM_Z < BLOCK_DIM_Z+T-1) ){
s_matrix[tz+k*BLOCK_DIM_Z][ty+i*BLOCK_DIM_Y][tx+j*BLOCK_DIM_X] = matrix[(gid_z+k*BLOCK_DIM_Z)*W*D+(gid_y+i*BLOCK_DIM_Y)*D+tx+j*BLOCK_DIM_X];
}
}
}
}
__syncthreads();
/* Now perform the multiplication to find the convolution */
if(gid_z<OW && gid_y<OW){
for(int id=bx*BLOCK_DIM_X;id<(bx+1)*BLOCK_DIM_X;id++){
if( id<N ){
float conv = 0;
for(int k=0;k<num_tasks;k++){
for(int i=-(T-1)/2;i<=(T-1)/2;i++){
for(int j=-(T-1)/2;j<=(T-1)/2;j++){
conv += s_matrix[tz+i+(T-1)/2][ty+j+(T-1)/2][tx+BLOCK_DIM_X*k] * kernel[id*T*T*D+(i+(T-1)/2)*T*D+(j+(T-1)/2)*D+tx+BLOCK_DIM_X*k];
}
}
}
atomicAdd(&(s_conv[tz][ty][id-bx*BLOCK_DIM_X]),conv);
}
}
output[gid_x*OW*OW+gid_z*OW+gid_y] = s_conv[tz][ty][tx];
}
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
float *kernel=(float*)malloc(sizeof(float)*T*T*D*N);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;cudaMalloc((void **)&Dmatrix,sizeof(unsigned char)*W*W*D);
float *Dkernel;cudaMalloc((void **)&Dkernel,sizeof(float)*N*T*T*D);
float *Doutput;cudaMalloc((void **)&Doutput,sizeof(float)*N*OW*OW);
cudaMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,cudaMemcpyHostToDevice);
cudaMemcpy(Dkernel, kernel, sizeof(float)*T*T*D*N,cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
//Make your cuda kernel call
dim3 blockd(BLOCK_DIM_X,BLOCK_DIM_Y,BLOCK_DIM_Z);
dim3 gridd((N+BLOCK_DIM_X-1)/BLOCK_DIM_X,(OW+BLOCK_DIM_Y-1)/(BLOCK_DIM_Y),(OW+BLOCK_DIM_Z-1)/BLOCK_DIM_Z);
convolution_3d<<<gridd,blockd>>>(Dmatrix,Dkernel,Doutput);
cudaDeviceSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
cudaMemcpy(output, Doutput, sizeof(float)*N*OW*OW,cudaMemcpyDeviceToHost);
//Use print_matrix_to_file function only
print_matrix_to_file(output);
cudaFree(Dmatrix);
cudaFree(Dkernel);
cudaFree(Doutput);
free(matrix);
free(kernel);
free(output);
} | code for sm_80
Function : _Z14convolution_3dPhPfS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e220000002700 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002300 */
/*0040*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x8], R0 ; /* 0x0000020005057a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R6, R6, c[0x0][0x4], R7 ; /* 0x0000010006067a24 */
/* 0x002fe200078e0207 */
/*0090*/ ISETP.GT.AND P0, PT, R7.reuse, 0xb, PT ; /* 0x0000000b0700780c */
/* 0x040fe40003f04270 */
/*00a0*/ ISETP.GT.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f24270 */
/*00b0*/ LEA R3, R5, R4, 0xd ; /* 0x0000000405037211 */
/* 0x004fe400078e68ff */
/*00c0*/ ISETP.GT.OR P2, PT, R0, 0xb, P0 ; /* 0x0000000b0000780c */
/* 0x000fe40000744670 */
/*00d0*/ LEA R3, R6, R3, 0x3 ; /* 0x0000000306037211 */
/* 0x000fe400078e18ff */
/*00e0*/ ISETP.GT.OR P3, PT, R0, 0xb, P1 ; /* 0x0000000b0000780c */
/* 0x000fc40000f64670 */
/*00f0*/ ISETP.GT.OR P0, PT, R0.reuse, 0x3, P0 ; /* 0x000000030000780c */
/* 0x040fe40000704670 */
/*0100*/ ISETP.GT.OR P1, PT, R0, 0x3, P1 ; /* 0x000000030000780c */
/* 0x000fe40000f24670 */
/*0110*/ IADD3 R2, P4, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f9e0ff */
/*0120*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P4 ; /* 0x0000590003037a11 */
/* 0x000fca00020f0eff */
/*0130*/ @!P2 LDG.E.U8 R9, [R2.64] ; /* 0x000000040209a981 */
/* 0x0000a8000c1e1100 */
/*0140*/ @!P3 LDG.E.U8 R10, [R2.64+0x40] ; /* 0x00004004020ab981 */
/* 0x0000e8000c1e1100 */
/*0150*/ @!P0 LDG.E.U8 R12, [R2.64+0x10000] ; /* 0x01000004020c8981 */
/* 0x000128000c1e1100 */
/*0160*/ @!P1 LDG.E.U8 R14, [R2.64+0x10040] ; /* 0x01004004020e9981 */
/* 0x000162000c1e1100 */
/*0170*/ SHF.L.U32 R7, R7, 0x5, RZ ; /* 0x0000000507077819 */
/* 0x000fc400000006ff */
/*0180*/ LEA R8, R0, 0x1200, 0x8 ; /* 0x0000120000087811 */
/* 0x000fe400078e40ff */
/*0190*/ ISETP.GT.AND P4, PT, R6, 0x3fb, PT ; /* 0x000003fb0600780c */
/* 0x000fe20003f84270 */
/*01a0*/ @!P2 IMAD R13, R0, 0x180, R7.reuse ; /* 0x00000180000da824 */
/* 0x100fe200078e0207 */
/*01b0*/ IADD3 R11, R8, R7, RZ ; /* 0x00000007080b7210 */
/* 0x000fe20007ffe0ff */
/*01c0*/ @!P0 IMAD R15, R0.reuse, 0x180, R7.reuse ; /* 0x00000180000f8824 */
/* 0x140fe200078e0207 */
/*01d0*/ ISETP.GT.OR P4, PT, R5, 0x3fb, P4 ; /* 0x000003fb0500780c */
/* 0x000fe20002784670 */
/*01e0*/ @!P3 IMAD R3, R0, 0x180, R7.reuse ; /* 0x000001800003b824 */
/* 0x101fe200078e0207 */
/*01f0*/ LEA R8, R4, R11, 0x2 ; /* 0x0000000b04087211 */
/* 0x000fe200078e10ff */
/*0200*/ @!P1 IMAD R17, R0, 0x180, R7 ; /* 0x0000018000119824 */
/* 0x000fe200078e0207 */
/*0210*/ @!P2 LEA R2, R4, R13, 0x2 ; /* 0x0000000d0402a211 */
/* 0x000fc400078e10ff */
/*0220*/ @!P3 LEA R3, R4.reuse, R3, 0x2 ; /* 0x000000030403b211 */
/* 0x040fe200078e10ff */
/*0230*/ STS [R8], RZ ; /* 0x000000ff08007388 */
/* 0x0001e20000000800 */
/*0240*/ @!P0 LEA R15, R4.reuse, R15, 0x2 ; /* 0x0000000f040f8211 */
/* 0x040fe400078e10ff */
/*0250*/ @!P1 LEA R17, R4, R17, 0x2 ; /* 0x0000001104119211 */
/* 0x000fe200078e10ff */
/*0260*/ @!P2 I2F.U16 R9, R9 ; /* 0x000000090009a306 */
/* 0x004e700000101000 */
/*0270*/ @!P3 I2F.U16 R10, R10 ; /* 0x0000000a000ab306 */
/* 0x008eb00000101000 */
/*0280*/ @!P0 I2F.U16 R12, R12 ; /* 0x0000000c000c8306 */
/* 0x010ee20000101000 */
/*0290*/ @!P2 STS [R2], R9 ; /* 0x000000090200a388 */
/* 0x0021ee0000000800 */
/*02a0*/ @!P1 I2F.U16 R14, R14 ; /* 0x0000000e000e9306 */
/* 0x020e620000101000 */
/*02b0*/ @!P3 STS [R3+0x100], R10 ; /* 0x0001000a0300b388 */
/* 0x0041e80000000800 */
/*02c0*/ @!P0 STS [R15+0xc00], R12 ; /* 0x000c000c0f008388 */
/* 0x0081e80000000800 */
/*02d0*/ @!P1 STS [R17+0xd00], R14 ; /* 0x000d000e11009388 */
/* 0x0021e80000000800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @P4 EXIT ; /* 0x000000000000494d */
/* 0x000fea0003800000 */
/*0300*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x001e240000002500 */
/*0310*/ SHF.L.U32 R10, R9, 0x3, RZ ; /* 0x00000003090a7819 */
/* 0x001fc800000006ff */
/*0320*/ ISETP.NE.AND P0, PT, R10, 0x7ffffff8, PT ; /* 0x7ffffff80a00780c */
/* 0x000fda0003f05270 */
/*0330*/ @!P0 BRA 0x930 ; /* 0x000005f000008947 */
/* 0x000fea0003800000 */
/*0340*/ IMAD R12, R9, 0x640, R4 ; /* 0x00000640090c7824 */
/* 0x000fe200078e0204 */
/*0350*/ IADD3 R13, R10, 0x8, RZ ; /* 0x000000080a0d7810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.GT.AND P0, PT, R10.reuse, 0x7f, PT ; /* 0x0000007f0a00780c */
/* 0x040fe40003f04270 */
/*0370*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.AND P1, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fce0003f26270 */
/*0390*/ @P0 BRA 0x900 ; /* 0x0000056000000947 */
/* 0x000fea0003800000 */
/*03a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*03b0*/ IMAD.WIDE R2, R12, R3, c[0x0][0x168] ; /* 0x00005a000c027625 */
/* 0x000fca00078e0203 */
/*03c0*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R25, [R2.64+0x20] ; /* 0x0000200402197981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R19, [R2.64+0x40] ; /* 0x0000400402137981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R17, [R2.64+0x60] ; /* 0x0000600402117981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R24, [R2.64+0x80] ; /* 0x0000800402187981 */
/* 0x000f68000c1e1900 */
/*0410*/ LDG.E R16, [R2.64+0xa0] ; /* 0x0000a00402107981 */
/* 0x000f62000c1e1900 */
/*0420*/ IMAD R15, R0, 0x180, R7 ; /* 0x00000180000f7824 */
/* 0x000fc600078e0207 */
/*0430*/ LDG.E R14, [R2.64+0xc0] ; /* 0x0000c004020e7981 */
/* 0x000f64000c1e1900 */
/*0440*/ LEA R15, R4, R15, 0x2 ; /* 0x0000000f040f7211 */
/* 0x000fe400078e10ff */
/*0450*/ LDG.E R23, [R2.64+0xe0] ; /* 0x0000e00402177981 */
/* 0x000f68000c1e1900 */
/*0460*/ LDS R21, [R15] ; /* 0x000000000f157984 */
/* 0x000ea80000000800 */
/*0470*/ LDS R26, [R15+0x20] ; /* 0x000020000f1a7984 */
/* 0x000ee80000000800 */
/*0480*/ LDS R18, [R15+0x40] ; /* 0x000040000f127984 */
/* 0x000f280000000800 */
/*0490*/ LDG.E R22, [R2.64+0x100] ; /* 0x0001000402167981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDS R27, [R15+0x60] ; /* 0x000060000f1b7984 */
/* 0x000f680000000800 */
/*04b0*/ LDS R28, [R15+0x4c0] ; /* 0x0004c0000f1c7984 */
/* 0x000fe20000000800 */
/*04c0*/ FFMA R20, R20, R21, RZ ; /* 0x0000001514147223 */
/* 0x004fc600000000ff */
/*04d0*/ LDG.E R21, [R2.64+0x120] ; /* 0x0001200402157981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ FFMA R25, R25, R26, R20 ; /* 0x0000001a19197223 */
/* 0x008fc60000000014 */
/*04f0*/ LDG.E R20, [R2.64+0x140] ; /* 0x0001400402147981 */
/* 0x000ee2000c1e1900 */
/*0500*/ FFMA R26, R19, R18, R25 ; /* 0x00000012131a7223 */
/* 0x010fc60000000019 */
/*0510*/ LDG.E R19, [R2.64+0x160] ; /* 0x0001600402137981 */
/* 0x000f28000c1e1900 */
/*0520*/ LDG.E R18, [R2.64+0x180] ; /* 0x0001800402127981 */
/* 0x000f22000c1e1900 */
/*0530*/ FFMA R27, R17, R27, R26 ; /* 0x0000001b111b7223 */
/* 0x020fc6000000001a */
/*0540*/ LDG.E R17, [R2.64+0x1a0] ; /* 0x0001a00402117981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDS R25, [R15+0x80] ; /* 0x000080000f197984 */
/* 0x000e280000000800 */
/*0560*/ LDS R26, [R15+0x1a0] ; /* 0x0001a0000f1a7984 */
/* 0x000fe20000000800 */
/*0570*/ FFMA R25, R24, R25, R27 ; /* 0x0000001918197223 */
/* 0x001fc6000000001b */
/*0580*/ LDS R24, [R15+0x180] ; /* 0x000180000f187984 */
/* 0x000e280000000800 */
/*0590*/ LDS R27, [R15+0x200] ; /* 0x000200000f1b7984 */
/* 0x000fe20000000800 */
/*05a0*/ FFMA R25, R16, R24, R25 ; /* 0x0000001810197223 */
/* 0x001fc60000000019 */
/*05b0*/ LDS R24, [R15+0x1c0] ; /* 0x0001c0000f187984 */
/* 0x000e280000000800 */
/*05c0*/ LDG.E R16, [R2.64+0x1c0] ; /* 0x0001c00402107981 */
/* 0x000362000c1e1900 */
/*05d0*/ FFMA R14, R14, R26, R25 ; /* 0x0000001a0e0e7223 */
/* 0x000fc60000000019 */
/*05e0*/ LDS R26, [R15+0x1e0] ; /* 0x0001e0000f1a7984 */
/* 0x000e620000000800 */
/*05f0*/ FFMA R25, R23, R24, R14 ; /* 0x0000001817197223 */
/* 0x001fc6000000000e */
/*0600*/ LDS R23, [R15+0x300] ; /* 0x000300000f177984 */
/* 0x000ee80000000800 */
/*0610*/ LDG.E R14, [R2.64+0x1e0] ; /* 0x0001e004020e7981 */
/* 0x000168000c1e1900 */
/*0620*/ LDS R24, [R15+0x320] ; /* 0x000320000f187984 */
/* 0x000f220000000800 */
/*0630*/ FFMA R26, R22, R26, R25 ; /* 0x0000001a161a7223 */
/* 0x002fc60000000019 */
/*0640*/ LDG.E R22, [R2.64+0x200] ; /* 0x0002000402167981 */
/* 0x000168000c1e1900 */
/*0650*/ LDS R25, [R15+0x340] ; /* 0x000340000f197984 */
/* 0x000e620000000800 */
/*0660*/ FFMA R26, R21, R27, R26 ; /* 0x0000001b151a7223 */
/* 0x004fc6000000001a */
/*0670*/ LDG.E R21, [R2.64+0x220] ; /* 0x0002200402157981 */
/* 0x0000a2000c1e1900 */
/*0680*/ FFMA R23, R20, R23, R26 ; /* 0x0000001714177223 */
/* 0x008fc6000000001a */
/*0690*/ LDS R26, [R15+0x360] ; /* 0x000360000f1a7984 */
/* 0x000f680000000800 */
/*06a0*/ LDG.E R20, [R2.64+0x240] ; /* 0x0002400402147981 */
/* 0x0000e2000c1e1900 */
/*06b0*/ FFMA R24, R19, R24, R23 ; /* 0x0000001813187223 */
/* 0x010fc60000000017 */
/*06c0*/ LDG.E R23, [R2.64+0x260] ; /* 0x0002600402177981 */
/* 0x000122000c1e1900 */
/*06d0*/ FFMA R25, R18, R25, R24 ; /* 0x0000001912197223 */
/* 0x002fc60000000018 */
/*06e0*/ LDG.E R19, [R2.64+0x280] ; /* 0x0002800402137981 */
/* 0x000128000c1e1900 */
/*06f0*/ LDG.E R24, [R2.64+0x2a0] ; /* 0x0002a00402187981 */
/* 0x000128000c1e1900 */
/*0700*/ LDG.E R18, [R2.64+0x2c0] ; /* 0x0002c00402127981 */
/* 0x000122000c1e1900 */
/*0710*/ FFMA R27, R17, R26, R25 ; /* 0x0000001a111b7223 */
/* 0x020fc60000000019 */
/*0720*/ LDG.E R17, [R2.64+0x2e0] ; /* 0x0002e00402117981 */
/* 0x000168000c1e1900 */
/*0730*/ LDG.E R25, [R2.64+0x300] ; /* 0x0003000402197981 */
/* 0x000168000c1e1900 */
/*0740*/ LDS R26, [R15+0x380] ; /* 0x000380000f1a7984 */
/* 0x000e680000000800 */
/*0750*/ LDS R3, [R15+0x640] ; /* 0x000640000f037984 */
/* 0x001fe80000000800 */
/*0760*/ LDS R2, [R15+0x660] ; /* 0x000660000f027984 */
/* 0x000fe20000000800 */
/*0770*/ FFMA R27, R16, R26, R27 ; /* 0x0000001a101b7223 */
/* 0x002fc6000000001b */
/*0780*/ LDS R16, [R15+0x480] ; /* 0x000480000f107984 */
/* 0x000e280000000800 */
/*0790*/ LDS R26, [R15+0x4a0] ; /* 0x0004a0000f1a7984 */
/* 0x000e620000000800 */
/*07a0*/ FFMA R29, R14, R16, R27 ; /* 0x000000100e1d7223 */
/* 0x001fc6000000001b */
/*07b0*/ LDS R27, [R15+0x4e0] ; /* 0x0004e0000f1b7984 */
/* 0x000ee80000000800 */
/*07c0*/ LDS R16, [R15+0x500] ; /* 0x000500000f107984 */
/* 0x000f220000000800 */
/*07d0*/ FFMA R22, R22, R26, R29 ; /* 0x0000001a16167223 */
/* 0x002fc6000000001d */
/*07e0*/ LDS R14, [R15+0x600] ; /* 0x000600000f0e7984 */
/* 0x000e220000000800 */
/*07f0*/ BSSY B0, 0x900 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0800*/ FFMA R22, R21, R28, R22 ; /* 0x0000001c15167223 */
/* 0x004fe40000000016 */
/*0810*/ LDS R21, [R15+0x620] ; /* 0x000620000f157984 */
/* 0x000e640000000800 */
/*0820*/ FFMA R20, R20, R27, R22 ; /* 0x0000001b14147223 */
/* 0x008fe40000000016 */
/*0830*/ LDS R22, [R15+0x680] ; /* 0x000680000f167984 */
/* 0x000ea40000000800 */
/*0840*/ FFMA R16, R23, R16, R20 ; /* 0x0000001017107223 */
/* 0x010fc80000000014 */
/*0850*/ FFMA R14, R19, R14, R16 ; /* 0x0000000e130e7223 */
/* 0x001fc80000000010 */
/*0860*/ FFMA R14, R24, R21, R14 ; /* 0x00000015180e7223 */
/* 0x002fc8000000000e */
/*0870*/ FFMA R14, R18, R3, R14 ; /* 0x00000003120e7223 */
/* 0x000fc8000000000e */
/*0880*/ FFMA R2, R17, R2, R14 ; /* 0x0000000211027223 */
/* 0x020fc8000000000e */
/*0890*/ FFMA R25, R25, R22, R2 ; /* 0x0000001619197223 */
/* 0x004fe40000000002 */
/*08a0*/ LDS R2, [R11] ; /* 0x000000000b027984 */
/* 0x000e240000000800 */
/*08b0*/ FADD R3, R25, R2 ; /* 0x0000000219037221 */
/* 0x001fcc0000000000 */
/*08c0*/ ATOMS.CAST.SPIN R3, [R11], R2, R3 ; /* 0x000000020b03738d */
/* 0x000e240001800003 */
/*08d0*/ ISETP.EQ.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x001fda0003f02070 */
/*08e0*/ @!P0 BRA 0x8a0 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0910*/ IADD3 R12, R12, 0xc8, RZ ; /* 0x000000c80c0c7810 */
/* 0x000fe20007ffe0ff */
/*0920*/ @!P1 BRA 0x360 ; /* 0xfffffa3000009947 */
/* 0x000fea000383ffff */
/*0930*/ LDS R7, [R8] ; /* 0x0000000008077984 */
/* 0x000e220000000800 */
/*0940*/ IMAD R4, R9, c[0x0][0x0], R4 ; /* 0x0000000009047a24 */
/* 0x000fe200078e0204 */
/*0950*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0960*/ IMAD R5, R5, 0x3fc, R6 ; /* 0x000003fc05057824 */
/* 0x000fc800078e0206 */
/*0970*/ IMAD R2, R4, 0xfe010, R5 ; /* 0x000fe01004027824 */
/* 0x000fc800078e0205 */
/*0980*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0990*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*09a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Template code for convolution. CS6023, IITM */
#include<stdio.h>
#include<cuda.h>
#include<math.h>
#define W 1024 // Input DIM
#define OW (W-4) // Output DIM
#define D 8 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define BLOCK_DIM_Z 8
#define BLOCK_DIM_Y 8
#define BLOCK_DIM_X 8
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(float *kernel){
float (*t)[T][T][D]=(float (*)[T][T][D])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l]=fmod(-(i+1)*2.1+(j+1)*3.2-(k+1)*4.8+(l+1)*7.1,1.0);
}
}
}
}
}
void print_matrix_to_file(float *m){
const char *fname = "assignment4_out";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++)
for(unsigned k=0;k<OW;k++)
fprintf(f,"%4.4f ", mat[i][j][k]);
fprintf(f,"\n");
}
fclose(f);
}
__global__ void convolution_3d(unsigned char *matrix,float* kernel,float *output){
__shared__ float s_matrix[BLOCK_DIM_Z+(T-1)][BLOCK_DIM_Y+(T-1)][D]; /* Shared memory for the matrix values */
__shared__ float s_conv[BLOCK_DIM_Z][BLOCK_DIM_Y][BLOCK_DIM_X];
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
int gid_x = blockDim.x*bx+tx;
int gid_y = blockDim.y*by+ty;
int gid_z = blockDim.z*bz+tz;
int num_tasks = D/BLOCK_DIM_X;
s_conv[tz][ty][tx] = 0;
for(int k=0;k<(T-1)/2;k++){
for(int i=0;i<(T-1)/2;i++){
for(int j=0;j<num_tasks;j++){
if( ((ty+i*BLOCK_DIM_Y) < (BLOCK_DIM_Y+T-1)) && (tz+k*BLOCK_DIM_Z < BLOCK_DIM_Z+T-1) ){
s_matrix[tz+k*BLOCK_DIM_Z][ty+i*BLOCK_DIM_Y][tx+j*BLOCK_DIM_X] = matrix[(gid_z+k*BLOCK_DIM_Z)*W*D+(gid_y+i*BLOCK_DIM_Y)*D+tx+j*BLOCK_DIM_X];
}
}
}
}
__syncthreads();
/* Now perform the multiplication to find the convolution */
if(gid_z<OW && gid_y<OW){
for(int id=bx*BLOCK_DIM_X;id<(bx+1)*BLOCK_DIM_X;id++){
if( id<N ){
float conv = 0;
for(int k=0;k<num_tasks;k++){
for(int i=-(T-1)/2;i<=(T-1)/2;i++){
for(int j=-(T-1)/2;j<=(T-1)/2;j++){
conv += s_matrix[tz+i+(T-1)/2][ty+j+(T-1)/2][tx+BLOCK_DIM_X*k] * kernel[id*T*T*D+(i+(T-1)/2)*T*D+(j+(T-1)/2)*D+tx+BLOCK_DIM_X*k];
}
}
}
atomicAdd(&(s_conv[tz][ty][id-bx*BLOCK_DIM_X]),conv);
}
}
output[gid_x*OW*OW+gid_z*OW+gid_y] = s_conv[tz][ty][tx];
}
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
float *kernel=(float*)malloc(sizeof(float)*T*T*D*N);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;cudaMalloc((void **)&Dmatrix,sizeof(unsigned char)*W*W*D);
float *Dkernel;cudaMalloc((void **)&Dkernel,sizeof(float)*N*T*T*D);
float *Doutput;cudaMalloc((void **)&Doutput,sizeof(float)*N*OW*OW);
cudaMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,cudaMemcpyHostToDevice);
cudaMemcpy(Dkernel, kernel, sizeof(float)*T*T*D*N,cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
//Make your cuda kernel call
dim3 blockd(BLOCK_DIM_X,BLOCK_DIM_Y,BLOCK_DIM_Z);
dim3 gridd((N+BLOCK_DIM_X-1)/BLOCK_DIM_X,(OW+BLOCK_DIM_Y-1)/(BLOCK_DIM_Y),(OW+BLOCK_DIM_Z-1)/BLOCK_DIM_Z);
convolution_3d<<<gridd,blockd>>>(Dmatrix,Dkernel,Doutput);
cudaDeviceSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
cudaMemcpy(output, Doutput, sizeof(float)*N*OW*OW,cudaMemcpyDeviceToHost);
//Use print_matrix_to_file function only
print_matrix_to_file(output);
cudaFree(Dmatrix);
cudaFree(Dkernel);
cudaFree(Doutput);
free(matrix);
free(kernel);
free(output);
} | .file "tmpxft_000fe6c7_00000000-6_ee16b105.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fillMatrixPh
.type _Z10fillMatrixPh, @function
_Z10fillMatrixPh:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbp
movl $0, %r12d
movl $0, %ebx
jmp .L4
.L11:
addl $1, %r8d
addl %r11d, %r9d
addq $8, %rsi
cmpl $1024, %r8d
je .L6
.L8:
leal (%r10,%r8), %edi
leaq -8(%rsi), %rcx
movl %r9d, %edx
.L5:
movslq %edx, %rax
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %r13d
sarl $31, %r13d
subl %r13d, %eax
movl %eax, %r13d
sall $8, %r13d
subl %eax, %r13d
movl %edx, %eax
subl %r13d, %eax
movb %al, (%rcx)
addl %edi, %edx
addq $1, %rcx
cmpq %rsi, %rcx
jne .L5
jmp .L11
.L6:
addl $1, %ebx
addl $2, %r12d
addq $8192, %rbp
cmpl $1024, %ebx
je .L3
.L4:
leal 3(%rbx), %r11d
leaq 8(%rbp), %rsi
movl %r12d, %r9d
movl $0, %r8d
leal 4(%rbx), %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10fillMatrixPh, .-_Z10fillMatrixPh
.globl _Z10fillKernelPf
.type _Z10fillKernelPf, @function
_Z10fillKernelPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 40(%rsp)
movl $-1, %r15d
jmp .L13
.L25:
movsd .LC2(%rip), %xmm1
movsd 8(%rsp), %xmm0
call fmod@PLT
jmp .L15
.L18:
subl $1, %r15d
addq $800, 40(%rsp)
cmpl $-129, %r15d
je .L12
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC5(%rip), %xmm0
movsd %xmm0, 32(%rsp)
movq 40(%rsp), %r14
movl $0, %r13d
.L21:
addl $1, %r13d
pxor %xmm0, %xmm0
cvtsi2sdl %r13d, %xmm0
mulsd .LC4(%rip), %xmm0
addsd 32(%rsp), %xmm0
movsd %xmm0, 24(%rsp)
movq %r14, %rbp
movl $0, %r12d
.L19:
addl $1, %r12d
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC3(%rip), %xmm0
movsd 24(%rsp), %xmm4
subsd %xmm0, %xmm4
movsd %xmm4, 16(%rsp)
movl $1, %ebx
.L16:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC0(%rip), %xmm0
addsd 16(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
fld1
fldl 8(%rsp)
.L14:
fprem
fnstsw %ax
testb $4, %ah
jne .L14
fstp %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm2
ucomisd %xmm2, %xmm2
jp .L25
.L15:
pxor %xmm0, %xmm0
cvtsd2ss (%rsp), %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
addq $1, %rbx
cmpq $9, %rbx
jne .L16
addq $32, %rbp
cmpl $5, %r12d
jne .L19
addq $160, %r14
cmpl $5, %r13d
jne .L21
jmp .L18
.L12:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10fillKernelPf, .-_Z10fillKernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "w"
.LC8:
.string "assignment4_out"
.LC9:
.string "%4.4f "
.LC10:
.string "\n"
.text
.globl _Z20print_matrix_to_filePf
.type _Z20print_matrix_to_filePf, @function
_Z20print_matrix_to_filePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %r15, %r14
addq $532684800, %r15
leaq .LC9(%rip), %r13
.L27:
leaq 4080(%r14), %rbp
.L31:
leaq -4080(%rbp), %rbx
.L28:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
addq $4080, %rbp
leaq 4165680(%r14), %rax
cmpq %rax, %rbp
jne .L31
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4161600, %r14
cmpq %r15, %r14
jne .L27
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z20print_matrix_to_filePf, .-_Z20print_matrix_to_filePf
.globl _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
.type _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_, @function
_Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14convolution_3dPhPfS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_, .-_Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
.globl _Z14convolution_3dPhPfS0_
.type _Z14convolution_3dPhPfS0_, @function
_Z14convolution_3dPhPfS0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z14convolution_3dPhPfS0_, .-_Z14convolution_3dPhPfS0_
.section .rodata.str1.1
.LC12:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call malloc@PLT
movq %rax, %r12
movl $102400, %edi
call malloc@PLT
movq %rax, %rbp
movl $532684800, %edi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call _Z10fillMatrixPh
movq %rbp, %rdi
call _Z10fillKernelPf
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $102400, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $532684800, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $102400, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 4(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl $16, 60(%rsp)
movl $128, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $8, %ecx
movq 60(%rsp), %rdi
movl $128, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L43:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $532684800, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z20print_matrix_to_filePf
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
jmp .L43
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z14convolution_3dPhPfS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z14convolution_3dPhPfS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1717986918
.long 1075603046
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 858993459
.long 1075000115
.align 8
.LC4:
.long -1717986918
.long 1074370969
.align 8
.LC5:
.long -858993459
.long 1073794252
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Template code for convolution. CS6023, IITM */
#include<stdio.h>
#include<cuda.h>
#include<math.h>
#define W 1024 // Input DIM
#define OW (W-4) // Output DIM
#define D 8 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define BLOCK_DIM_Z 8
#define BLOCK_DIM_Y 8
#define BLOCK_DIM_X 8
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(float *kernel){
float (*t)[T][T][D]=(float (*)[T][T][D])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l]=fmod(-(i+1)*2.1+(j+1)*3.2-(k+1)*4.8+(l+1)*7.1,1.0);
}
}
}
}
}
void print_matrix_to_file(float *m){
const char *fname = "assignment4_out";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++)
for(unsigned k=0;k<OW;k++)
fprintf(f,"%4.4f ", mat[i][j][k]);
fprintf(f,"\n");
}
fclose(f);
}
__global__ void convolution_3d(unsigned char *matrix,float* kernel,float *output){
__shared__ float s_matrix[BLOCK_DIM_Z+(T-1)][BLOCK_DIM_Y+(T-1)][D]; /* Shared memory for the matrix values */
__shared__ float s_conv[BLOCK_DIM_Z][BLOCK_DIM_Y][BLOCK_DIM_X];
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
int gid_x = blockDim.x*bx+tx;
int gid_y = blockDim.y*by+ty;
int gid_z = blockDim.z*bz+tz;
int num_tasks = D/BLOCK_DIM_X;
s_conv[tz][ty][tx] = 0;
for(int k=0;k<(T-1)/2;k++){
for(int i=0;i<(T-1)/2;i++){
for(int j=0;j<num_tasks;j++){
if( ((ty+i*BLOCK_DIM_Y) < (BLOCK_DIM_Y+T-1)) && (tz+k*BLOCK_DIM_Z < BLOCK_DIM_Z+T-1) ){
s_matrix[tz+k*BLOCK_DIM_Z][ty+i*BLOCK_DIM_Y][tx+j*BLOCK_DIM_X] = matrix[(gid_z+k*BLOCK_DIM_Z)*W*D+(gid_y+i*BLOCK_DIM_Y)*D+tx+j*BLOCK_DIM_X];
}
}
}
}
__syncthreads();
/* Now perform the multiplication to find the convolution */
if(gid_z<OW && gid_y<OW){
for(int id=bx*BLOCK_DIM_X;id<(bx+1)*BLOCK_DIM_X;id++){
if( id<N ){
float conv = 0;
for(int k=0;k<num_tasks;k++){
for(int i=-(T-1)/2;i<=(T-1)/2;i++){
for(int j=-(T-1)/2;j<=(T-1)/2;j++){
conv += s_matrix[tz+i+(T-1)/2][ty+j+(T-1)/2][tx+BLOCK_DIM_X*k] * kernel[id*T*T*D+(i+(T-1)/2)*T*D+(j+(T-1)/2)*D+tx+BLOCK_DIM_X*k];
}
}
}
atomicAdd(&(s_conv[tz][ty][id-bx*BLOCK_DIM_X]),conv);
}
}
output[gid_x*OW*OW+gid_z*OW+gid_y] = s_conv[tz][ty][tx];
}
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
float *kernel=(float*)malloc(sizeof(float)*T*T*D*N);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;cudaMalloc((void **)&Dmatrix,sizeof(unsigned char)*W*W*D);
float *Dkernel;cudaMalloc((void **)&Dkernel,sizeof(float)*N*T*T*D);
float *Doutput;cudaMalloc((void **)&Doutput,sizeof(float)*N*OW*OW);
cudaMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,cudaMemcpyHostToDevice);
cudaMemcpy(Dkernel, kernel, sizeof(float)*T*T*D*N,cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
//Make your cuda kernel call
dim3 blockd(BLOCK_DIM_X,BLOCK_DIM_Y,BLOCK_DIM_Z);
dim3 gridd((N+BLOCK_DIM_X-1)/BLOCK_DIM_X,(OW+BLOCK_DIM_Y-1)/(BLOCK_DIM_Y),(OW+BLOCK_DIM_Z-1)/BLOCK_DIM_Z);
convolution_3d<<<gridd,blockd>>>(Dmatrix,Dkernel,Doutput);
cudaDeviceSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
cudaMemcpy(output, Doutput, sizeof(float)*N*OW*OW,cudaMemcpyDeviceToHost);
//Use print_matrix_to_file function only
print_matrix_to_file(output);
cudaFree(Dmatrix);
cudaFree(Dkernel);
cudaFree(Doutput);
free(matrix);
free(kernel);
free(output);
} | /*
Template code for convolution. CS6023, IITM */
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#define W 1024 // Input DIM
#define OW (W-4) // Output DIM
#define D 8 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define BLOCK_DIM_Z 8
#define BLOCK_DIM_Y 8
#define BLOCK_DIM_X 8
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(float *kernel){
float (*t)[T][T][D]=(float (*)[T][T][D])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l]=fmod(-(i+1)*2.1+(j+1)*3.2-(k+1)*4.8+(l+1)*7.1,1.0);
}
}
}
}
}
void print_matrix_to_file(float *m){
const char *fname = "assignment4_out";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++)
for(unsigned k=0;k<OW;k++)
fprintf(f,"%4.4f ", mat[i][j][k]);
fprintf(f,"\n");
}
fclose(f);
}
__global__ void convolution_3d(unsigned char *matrix,float* kernel,float *output){
__shared__ float s_matrix[BLOCK_DIM_Z+(T-1)][BLOCK_DIM_Y+(T-1)][D]; /* Shared memory for the matrix values */
__shared__ float s_conv[BLOCK_DIM_Z][BLOCK_DIM_Y][BLOCK_DIM_X];
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
int gid_x = blockDim.x*bx+tx;
int gid_y = blockDim.y*by+ty;
int gid_z = blockDim.z*bz+tz;
int num_tasks = D/BLOCK_DIM_X;
s_conv[tz][ty][tx] = 0;
for(int k=0;k<(T-1)/2;k++){
for(int i=0;i<(T-1)/2;i++){
for(int j=0;j<num_tasks;j++){
if( ((ty+i*BLOCK_DIM_Y) < (BLOCK_DIM_Y+T-1)) && (tz+k*BLOCK_DIM_Z < BLOCK_DIM_Z+T-1) ){
s_matrix[tz+k*BLOCK_DIM_Z][ty+i*BLOCK_DIM_Y][tx+j*BLOCK_DIM_X] = matrix[(gid_z+k*BLOCK_DIM_Z)*W*D+(gid_y+i*BLOCK_DIM_Y)*D+tx+j*BLOCK_DIM_X];
}
}
}
}
__syncthreads();
/* Now perform the multiplication to find the convolution */
if(gid_z<OW && gid_y<OW){
for(int id=bx*BLOCK_DIM_X;id<(bx+1)*BLOCK_DIM_X;id++){
if( id<N ){
float conv = 0;
for(int k=0;k<num_tasks;k++){
for(int i=-(T-1)/2;i<=(T-1)/2;i++){
for(int j=-(T-1)/2;j<=(T-1)/2;j++){
conv += s_matrix[tz+i+(T-1)/2][ty+j+(T-1)/2][tx+BLOCK_DIM_X*k] * kernel[id*T*T*D+(i+(T-1)/2)*T*D+(j+(T-1)/2)*D+tx+BLOCK_DIM_X*k];
}
}
}
atomicAdd(&(s_conv[tz][ty][id-bx*BLOCK_DIM_X]),conv);
}
}
output[gid_x*OW*OW+gid_z*OW+gid_y] = s_conv[tz][ty][tx];
}
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
float *kernel=(float*)malloc(sizeof(float)*T*T*D*N);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;hipMalloc((void **)&Dmatrix,sizeof(unsigned char)*W*W*D);
float *Dkernel;hipMalloc((void **)&Dkernel,sizeof(float)*N*T*T*D);
float *Doutput;hipMalloc((void **)&Doutput,sizeof(float)*N*OW*OW);
hipMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,hipMemcpyHostToDevice);
hipMemcpy(Dkernel, kernel, sizeof(float)*T*T*D*N,hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
//Make your cuda kernel call
dim3 blockd(BLOCK_DIM_X,BLOCK_DIM_Y,BLOCK_DIM_Z);
dim3 gridd((N+BLOCK_DIM_X-1)/BLOCK_DIM_X,(OW+BLOCK_DIM_Y-1)/(BLOCK_DIM_Y),(OW+BLOCK_DIM_Z-1)/BLOCK_DIM_Z);
convolution_3d<<<gridd,blockd>>>(Dmatrix,Dkernel,Doutput);
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
hipMemcpy(output, Doutput, sizeof(float)*N*OW*OW,hipMemcpyDeviceToHost);
//Use print_matrix_to_file function only
print_matrix_to_file(output);
hipFree(Dmatrix);
hipFree(Dkernel);
hipFree(Doutput);
free(matrix);
free(kernel);
free(output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Template code for convolution. CS6023, IITM */
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#define W 1024 // Input DIM
#define OW (W-4) // Output DIM
#define D 8 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define BLOCK_DIM_Z 8
#define BLOCK_DIM_Y 8
#define BLOCK_DIM_X 8
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(float *kernel){
float (*t)[T][T][D]=(float (*)[T][T][D])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l]=fmod(-(i+1)*2.1+(j+1)*3.2-(k+1)*4.8+(l+1)*7.1,1.0);
}
}
}
}
}
void print_matrix_to_file(float *m){
const char *fname = "assignment4_out";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++)
for(unsigned k=0;k<OW;k++)
fprintf(f,"%4.4f ", mat[i][j][k]);
fprintf(f,"\n");
}
fclose(f);
}
__global__ void convolution_3d(unsigned char *matrix,float* kernel,float *output){
__shared__ float s_matrix[BLOCK_DIM_Z+(T-1)][BLOCK_DIM_Y+(T-1)][D]; /* Shared memory for the matrix values */
__shared__ float s_conv[BLOCK_DIM_Z][BLOCK_DIM_Y][BLOCK_DIM_X];
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
int gid_x = blockDim.x*bx+tx;
int gid_y = blockDim.y*by+ty;
int gid_z = blockDim.z*bz+tz;
int num_tasks = D/BLOCK_DIM_X;
s_conv[tz][ty][tx] = 0;
for(int k=0;k<(T-1)/2;k++){
for(int i=0;i<(T-1)/2;i++){
for(int j=0;j<num_tasks;j++){
if( ((ty+i*BLOCK_DIM_Y) < (BLOCK_DIM_Y+T-1)) && (tz+k*BLOCK_DIM_Z < BLOCK_DIM_Z+T-1) ){
s_matrix[tz+k*BLOCK_DIM_Z][ty+i*BLOCK_DIM_Y][tx+j*BLOCK_DIM_X] = matrix[(gid_z+k*BLOCK_DIM_Z)*W*D+(gid_y+i*BLOCK_DIM_Y)*D+tx+j*BLOCK_DIM_X];
}
}
}
}
__syncthreads();
/* Now perform the multiplication to find the convolution */
if(gid_z<OW && gid_y<OW){
for(int id=bx*BLOCK_DIM_X;id<(bx+1)*BLOCK_DIM_X;id++){
if( id<N ){
float conv = 0;
for(int k=0;k<num_tasks;k++){
for(int i=-(T-1)/2;i<=(T-1)/2;i++){
for(int j=-(T-1)/2;j<=(T-1)/2;j++){
conv += s_matrix[tz+i+(T-1)/2][ty+j+(T-1)/2][tx+BLOCK_DIM_X*k] * kernel[id*T*T*D+(i+(T-1)/2)*T*D+(j+(T-1)/2)*D+tx+BLOCK_DIM_X*k];
}
}
}
atomicAdd(&(s_conv[tz][ty][id-bx*BLOCK_DIM_X]),conv);
}
}
output[gid_x*OW*OW+gid_z*OW+gid_y] = s_conv[tz][ty][tx];
}
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
float *kernel=(float*)malloc(sizeof(float)*T*T*D*N);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;hipMalloc((void **)&Dmatrix,sizeof(unsigned char)*W*W*D);
float *Dkernel;hipMalloc((void **)&Dkernel,sizeof(float)*N*T*T*D);
float *Doutput;hipMalloc((void **)&Doutput,sizeof(float)*N*OW*OW);
hipMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,hipMemcpyHostToDevice);
hipMemcpy(Dkernel, kernel, sizeof(float)*T*T*D*N,hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
//Make your cuda kernel call
dim3 blockd(BLOCK_DIM_X,BLOCK_DIM_Y,BLOCK_DIM_Z);
dim3 gridd((N+BLOCK_DIM_X-1)/BLOCK_DIM_X,(OW+BLOCK_DIM_Y-1)/(BLOCK_DIM_Y),(OW+BLOCK_DIM_Z-1)/BLOCK_DIM_Z);
convolution_3d<<<gridd,blockd>>>(Dmatrix,Dkernel,Doutput);
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
hipMemcpy(output, Doutput, sizeof(float)*N*OW*OW,hipMemcpyDeviceToHost);
//Use print_matrix_to_file function only
print_matrix_to_file(output);
hipFree(Dmatrix);
hipFree(Dkernel);
hipFree(Doutput);
free(matrix);
free(kernel);
free(output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14convolution_3dPhPfS0_
.globl _Z14convolution_3dPhPfS0_
.p2align 8
.type _Z14convolution_3dPhPfS0_,@function
_Z14convolution_3dPhPfS0_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v7, 2, v1
v_lshlrev_b32_e32 v8, 5, v6
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
v_lshlrev_b32_e32 v5, 8, v0
s_lshr_b32 s3, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v9, v5, v8, v7
v_mul_u32_u24_e32 v5, 0x180, v0
v_lshl_or_b32 v10, v4, 13, v1
s_mov_b32 s3, 0
v_add_nc_u32_e32 v3, 0x1200, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v5, v5, v8, v7
v_lshl_add_u32 v7, v2, 3, v10
ds_store_b32 v9, v11 offset:4608
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
v_add_nc_u32_e32 v5, 0xc00, v5
v_add_nc_u32_e32 v7, 0x10000, v7
s_add_i32 s6, s3, 1
s_cmp_lg_u32 s3, 0
s_mov_b32 s3, s6
s_cbranch_scc1 .LBB0_6
.LBB0_2:
v_lshl_add_u32 v8, s3, 3, v0
s_mov_b32 s7, 0
v_mov_b32_e32 v9, v6
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 11, v8
v_mov_b32_e32 v8, v7
s_xor_b32 s6, vcc_lo, -1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v9, 8, v9
v_add_nc_u32_e32 v8, 64, v8
s_addk_i32 s7, 0x100
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s7, 0x100
s_cbranch_scc1 .LBB0_1
.LBB0_4:
v_cmp_gt_u32_e32 vcc_lo, 12, v9
s_and_b32 s9, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s8, s9
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v11, 31, v8
v_add_co_u32 v10, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_u8 v10, v[10:11], off
v_add_nc_u32_e32 v11, s7, v5
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v10, v10
ds_store_b32 v11, v10
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_max_i32_e32 v5, v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e32 0x3fc, v5
s_cbranch_execz .LBB0_17
s_lshl_b32 s3, s13, 3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0x7ffffff8
s_cbranch_scc1 .LBB0_16
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_u32_u24_e32 v7, 0x180, v0
v_lshlrev_b32_e32 v8, 5, v6
v_lshlrev_b32_e32 v9, 2, v1
v_mad_u64_u32 v[5:6], null, s13, 0x640, v[1:2]
v_lshlrev_b32_e32 v0, 8, v0
s_add_i32 s6, s3, 8
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v9, v7, v8, v9
s_mov_b32 s7, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v5, 0xc8, v5
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s7, s6
s_cbranch_scc1 .LBB0_16
.LBB0_10:
s_cmpk_gt_i32 s7, 0x7f
s_cbranch_scc1 .LBB0_9
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, v9
v_mov_b32_e32 v12, v5
s_mov_b32 s8, -2
.p2align 6
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v12
s_mov_b32 s9, 0
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[13:14], 2, v[6:7]
v_add_nc_u32_e32 v6, 8, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
global_load_b32 v7, v[13:14], off
v_add_nc_u32_e32 v13, s9, v11
s_add_i32 s9, s9, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s9, 0xa0
ds_load_b32 v13, v13
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v10, v13, v7
s_cbranch_scc0 .LBB0_13
v_add_nc_u32_e32 v12, 40, v12
v_add_nc_u32_e32 v11, 0x180, v11
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 3
s_cbranch_scc0 .LBB0_12
s_sub_i32 s8, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s8, s8, 2
v_add3_u32 v6, v0, v8, s8
ds_add_f32 v6, v10 offset:4608
s_branch .LBB0_9
.LBB0_16:
s_set_inst_prefetch_distance 0x2
s_and_b32 s2, 0xffff, s2
v_mul_lo_u32 v0, v4, 0x3fc
v_mad_u64_u32 v[5:6], null, s13, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v5, 0xfe010
v_add3_u32 v0, v2, v1, v0
ds_load_b32 v2, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14convolution_3dPhPfS0_
.amdhsa_group_segment_fixed_size 6656
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14convolution_3dPhPfS0_, .Lfunc_end0-_Z14convolution_3dPhPfS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 6656
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14convolution_3dPhPfS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14convolution_3dPhPfS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Template code for convolution. CS6023, IITM */
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#define W 1024 // Input DIM
#define OW (W-4) // Output DIM
#define D 8 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define BLOCK_DIM_Z 8
#define BLOCK_DIM_Y 8
#define BLOCK_DIM_X 8
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(float *kernel){
float (*t)[T][T][D]=(float (*)[T][T][D])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l]=fmod(-(i+1)*2.1+(j+1)*3.2-(k+1)*4.8+(l+1)*7.1,1.0);
}
}
}
}
}
void print_matrix_to_file(float *m){
const char *fname = "assignment4_out";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++)
for(unsigned k=0;k<OW;k++)
fprintf(f,"%4.4f ", mat[i][j][k]);
fprintf(f,"\n");
}
fclose(f);
}
__global__ void convolution_3d(unsigned char *matrix,float* kernel,float *output){
__shared__ float s_matrix[BLOCK_DIM_Z+(T-1)][BLOCK_DIM_Y+(T-1)][D]; /* Shared memory for the matrix values */
__shared__ float s_conv[BLOCK_DIM_Z][BLOCK_DIM_Y][BLOCK_DIM_X];
int tx = threadIdx.x;
int ty = threadIdx.y;
int tz = threadIdx.z;
int bx = blockIdx.x;
int by = blockIdx.y;
int bz = blockIdx.z;
int gid_x = blockDim.x*bx+tx;
int gid_y = blockDim.y*by+ty;
int gid_z = blockDim.z*bz+tz;
int num_tasks = D/BLOCK_DIM_X;
s_conv[tz][ty][tx] = 0;
for(int k=0;k<(T-1)/2;k++){
for(int i=0;i<(T-1)/2;i++){
for(int j=0;j<num_tasks;j++){
if( ((ty+i*BLOCK_DIM_Y) < (BLOCK_DIM_Y+T-1)) && (tz+k*BLOCK_DIM_Z < BLOCK_DIM_Z+T-1) ){
s_matrix[tz+k*BLOCK_DIM_Z][ty+i*BLOCK_DIM_Y][tx+j*BLOCK_DIM_X] = matrix[(gid_z+k*BLOCK_DIM_Z)*W*D+(gid_y+i*BLOCK_DIM_Y)*D+tx+j*BLOCK_DIM_X];
}
}
}
}
__syncthreads();
/* Now perform the multiplication to find the convolution */
if(gid_z<OW && gid_y<OW){
for(int id=bx*BLOCK_DIM_X;id<(bx+1)*BLOCK_DIM_X;id++){
if( id<N ){
float conv = 0;
for(int k=0;k<num_tasks;k++){
for(int i=-(T-1)/2;i<=(T-1)/2;i++){
for(int j=-(T-1)/2;j<=(T-1)/2;j++){
conv += s_matrix[tz+i+(T-1)/2][ty+j+(T-1)/2][tx+BLOCK_DIM_X*k] * kernel[id*T*T*D+(i+(T-1)/2)*T*D+(j+(T-1)/2)*D+tx+BLOCK_DIM_X*k];
}
}
}
atomicAdd(&(s_conv[tz][ty][id-bx*BLOCK_DIM_X]),conv);
}
}
output[gid_x*OW*OW+gid_z*OW+gid_y] = s_conv[tz][ty][tx];
}
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
float *kernel=(float*)malloc(sizeof(float)*T*T*D*N);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;hipMalloc((void **)&Dmatrix,sizeof(unsigned char)*W*W*D);
float *Dkernel;hipMalloc((void **)&Dkernel,sizeof(float)*N*T*T*D);
float *Doutput;hipMalloc((void **)&Doutput,sizeof(float)*N*OW*OW);
hipMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,hipMemcpyHostToDevice);
hipMemcpy(Dkernel, kernel, sizeof(float)*T*T*D*N,hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
//Make your cuda kernel call
dim3 blockd(BLOCK_DIM_X,BLOCK_DIM_Y,BLOCK_DIM_Z);
dim3 gridd((N+BLOCK_DIM_X-1)/BLOCK_DIM_X,(OW+BLOCK_DIM_Y-1)/(BLOCK_DIM_Y),(OW+BLOCK_DIM_Z-1)/BLOCK_DIM_Z);
convolution_3d<<<gridd,blockd>>>(Dmatrix,Dkernel,Doutput);
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
hipMemcpy(output, Doutput, sizeof(float)*N*OW*OW,hipMemcpyDeviceToHost);
//Use print_matrix_to_file function only
print_matrix_to_file(output);
hipFree(Dmatrix);
hipFree(Dkernel);
hipFree(Doutput);
free(matrix);
free(kernel);
free(output);
} | .text
.file "ee16b105.hip"
.globl _Z10fillMatrixPh # -- Begin function _Z10fillMatrixPh
.p2align 4, 0x90
.type _Z10fillMatrixPh,@function
_Z10fillMatrixPh: # @_Z10fillMatrixPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_2: # %.preheader
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
movl %r10d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, (%r11,%r14)
incq %r14
addl %r9d, %ebp
cmpq $8, %r14
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=2
incq %rbx
addq $8, %r11
addl %ecx, %r10d
incl %r9d
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_2
# %bb.5: # in Loop: Header=BB0_1 Depth=1
incq %r8
addq $8192, %rdi # imm = 0x2000
addl $2, %eax
incl %ecx
incl %edx
cmpq $1024, %r8 # imm = 0x400
jne .LBB0_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10fillMatrixPh, .Lfunc_end0-_Z10fillMatrixPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10fillKernelPf
.LCPI1_0:
.quad 0x4000cccccccccccd # double 2.1000000000000001
.LCPI1_1:
.quad 0x400999999999999a # double 3.2000000000000002
.LCPI1_2:
.quad 0xc013333333333333 # double -4.7999999999999998
.LCPI1_3:
.quad 0x401c666666666666 # double 7.0999999999999996
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z10fillKernelPf
.p2align 4, 0x90
.type _Z10fillKernelPf,@function
_Z10fillKernelPf: # @_Z10fillKernelPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
# Child Loop BB1_4 Depth 4
movq %rax, (%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
notl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
movq %rdi, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader20
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
# Child Loop BB1_4 Depth 4
incq %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
addsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_4 Depth 4
incq %rbp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
addsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# Parent Loop BB1_3 Depth=3
# => This Inner Loop Header: Depth=4
leaq 1(%rbx), %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
mulsd %xmm1, %xmm0
addsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movaps %xmm2, %xmm1
callq fmod
movsd .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbx,4)
movq %r14, %rbx
cmpq $8, %r14
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=3
addq $32, %r13
cmpq $5, %rbp
jne .LBB1_3
# %bb.6: # in Loop: Header=BB1_2 Depth=2
addq $160, %r15
cmpq $5, %r12
jne .LBB1_2
# %bb.7: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rax # 8-byte Reload
incq %rax
movq 8(%rsp), %rdi # 8-byte Reload
addq $800, %rdi # imm = 0x320
cmpq $128, %rax
jne .LBB1_1
# %bb.8:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10fillKernelPf, .Lfunc_end1-_Z10fillKernelPf
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePf # -- Begin function _Z20print_matrix_to_filePf
.p2align 4, 0x90
.type _Z20print_matrix_to_filePf,@function
_Z20print_matrix_to_filePf: # @_Z20print_matrix_to_filePf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $1020, %rbp # imm = 0x3FC
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=2
incq %r13
addq $4080, %r12 # imm = 0xFF0
cmpq $1020, %r13 # imm = 0x3FC
jne .LBB2_2
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addq $4161600, %rbx # imm = 0x3F8040
cmpq $128, %r15
jne .LBB2_1
# %bb.6:
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end2:
.size _Z20print_matrix_to_filePf, .Lfunc_end2-_Z20print_matrix_to_filePf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__convolution_3dPhPfS0_ # -- Begin function _Z29__device_stub__convolution_3dPhPfS0_
.p2align 4, 0x90
.type _Z29__device_stub__convolution_3dPhPfS0_,@function
_Z29__device_stub__convolution_3dPhPfS0_: # @_Z29__device_stub__convolution_3dPhPfS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14convolution_3dPhPfS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__convolution_3dPhPfS0_, .Lfunc_end3-_Z29__device_stub__convolution_3dPhPfS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x4000cccccccccccd # double 2.1000000000000001
.LCPI4_1:
.quad 0x400999999999999a # double 3.2000000000000002
.LCPI4_2:
.quad 0xc013333333333333 # double -4.7999999999999998
.LCPI4_3:
.quad 0x401c666666666666 # double 7.0999999999999996
.LCPI4_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
movl $102400, %edi # imm = 0x19000
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $532684800, %edi # imm = 0x1FC02000
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
movq %rbx, 64(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_1: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
movl %r10d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, (%r11,%r14)
incq %r14
addl %r9d, %ebp
cmpq $8, %r14
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rbx
addq $8, %r11
addl %ecx, %r10d
incl %r9d
cmpq $1024, %rbx # imm = 0x400
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %r8
addq $8192, %rdi # imm = 0x2000
addl $2, %eax
incl %ecx
incl %edx
cmpq $1024, %r8 # imm = 0x400
jne .LBB4_1
# %bb.6: # %.preheader21.i.preheader
xorl %eax, %eax
movsd .LCPI4_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI4_4(%rip), %xmm2 # xmm2 = mem[0],zero
movq 16(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB4_7: # %.preheader21.i
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
movq %rax, 88(%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
notl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq %r13, 80(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_8: # %.preheader20.i
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
incq %rbx
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
addsd 96(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq %r13, %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_9: # %.preheader.i18
# Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_10 Depth 4
incq %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd .LCPI4_2(%rip), %xmm0
addsd 104(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 112(%rsp) # 8-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# Parent Loop BB4_9 Depth=3
# => This Inner Loop Header: Depth=4
leaq 1(%r14), %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd %xmm1, %xmm0
addsd 112(%rsp), %xmm0 # 8-byte Folded Reload
movaps %xmm2, %xmm1
callq fmod
movsd .LCPI4_4(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI4_3(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r14,4)
movq %r12, %r14
cmpq $8, %r12
jne .LBB4_10
# %bb.11: # in Loop: Header=BB4_9 Depth=3
addq $32, %rbp
cmpq $5, %r15
jne .LBB4_9
# %bb.12: # in Loop: Header=BB4_8 Depth=2
addq $160, %r13
cmpq $5, %rbx
jne .LBB4_8
# %bb.13: # in Loop: Header=BB4_7 Depth=1
movq 88(%rsp), %rax # 8-byte Reload
incq %rax
movq 80(%rsp), %r13 # 8-byte Reload
addq $800, %r13 # imm = 0x320
cmpq $128, %rax
jne .LBB4_7
# %bb.14: # %_Z10fillKernelPf.exit
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $102400, %esi # imm = 0x19000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $532684800, %esi # imm = 0x1FC02000
callq hipMalloc
movq 48(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq 64(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $102400, %edx # imm = 0x19000
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $549755813904, %rdi # imm = 0x8000000010
movabsq $34359738376, %rdx # imm = 0x800000008
movl $128, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z14convolution_3dPhPfS0_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $532684800, %edx # imm = 0x1FC02000
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
.p2align 4, 0x90
.LBB4_17: # %.preheader16.i
# =>This Loop Header: Depth=1
# Child Loop BB4_18 Depth 2
# Child Loop BB4_19 Depth 3
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # %.preheader.i24
# Parent Loop BB4_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_19 Depth 3
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_17 Depth=1
# Parent Loop BB4_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $1020, %rbp # imm = 0x3FC
jne .LBB4_19
# %bb.20: # in Loop: Header=BB4_18 Depth=2
incq %r15
addq $4080, %r14 # imm = 0xFF0
cmpq $1020, %r15 # imm = 0x3FC
jne .LBB4_18
# %bb.21: # in Loop: Header=BB4_17 Depth=1
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
incq %r13
addq $4161600, %rbx # imm = 0x3F8040
cmpq $128, %r13
jne .LBB4_17
# %bb.22: # %_Z20print_matrix_to_filePf.exit
movq %r12, %rdi
callq fclose
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14convolution_3dPhPfS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "assignment4_out"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type _Z14convolution_3dPhPfS0_,@object # @_Z14convolution_3dPhPfS0_
.section .rodata,"a",@progbits
.globl _Z14convolution_3dPhPfS0_
.p2align 3, 0x0
_Z14convolution_3dPhPfS0_:
.quad _Z29__device_stub__convolution_3dPhPfS0_
.size _Z14convolution_3dPhPfS0_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%f\n"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14convolution_3dPhPfS0_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__convolution_3dPhPfS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14convolution_3dPhPfS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14convolution_3dPhPfS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e220000002700 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002300 */
/*0040*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x8], R0 ; /* 0x0000020005057a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R6, R6, c[0x0][0x4], R7 ; /* 0x0000010006067a24 */
/* 0x002fe200078e0207 */
/*0090*/ ISETP.GT.AND P0, PT, R7.reuse, 0xb, PT ; /* 0x0000000b0700780c */
/* 0x040fe40003f04270 */
/*00a0*/ ISETP.GT.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f24270 */
/*00b0*/ LEA R3, R5, R4, 0xd ; /* 0x0000000405037211 */
/* 0x004fe400078e68ff */
/*00c0*/ ISETP.GT.OR P2, PT, R0, 0xb, P0 ; /* 0x0000000b0000780c */
/* 0x000fe40000744670 */
/*00d0*/ LEA R3, R6, R3, 0x3 ; /* 0x0000000306037211 */
/* 0x000fe400078e18ff */
/*00e0*/ ISETP.GT.OR P3, PT, R0, 0xb, P1 ; /* 0x0000000b0000780c */
/* 0x000fc40000f64670 */
/*00f0*/ ISETP.GT.OR P0, PT, R0.reuse, 0x3, P0 ; /* 0x000000030000780c */
/* 0x040fe40000704670 */
/*0100*/ ISETP.GT.OR P1, PT, R0, 0x3, P1 ; /* 0x000000030000780c */
/* 0x000fe40000f24670 */
/*0110*/ IADD3 R2, P4, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f9e0ff */
/*0120*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P4 ; /* 0x0000590003037a11 */
/* 0x000fca00020f0eff */
/*0130*/ @!P2 LDG.E.U8 R9, [R2.64] ; /* 0x000000040209a981 */
/* 0x0000a8000c1e1100 */
/*0140*/ @!P3 LDG.E.U8 R10, [R2.64+0x40] ; /* 0x00004004020ab981 */
/* 0x0000e8000c1e1100 */
/*0150*/ @!P0 LDG.E.U8 R12, [R2.64+0x10000] ; /* 0x01000004020c8981 */
/* 0x000128000c1e1100 */
/*0160*/ @!P1 LDG.E.U8 R14, [R2.64+0x10040] ; /* 0x01004004020e9981 */
/* 0x000162000c1e1100 */
/*0170*/ SHF.L.U32 R7, R7, 0x5, RZ ; /* 0x0000000507077819 */
/* 0x000fc400000006ff */
/*0180*/ LEA R8, R0, 0x1200, 0x8 ; /* 0x0000120000087811 */
/* 0x000fe400078e40ff */
/*0190*/ ISETP.GT.AND P4, PT, R6, 0x3fb, PT ; /* 0x000003fb0600780c */
/* 0x000fe20003f84270 */
/*01a0*/ @!P2 IMAD R13, R0, 0x180, R7.reuse ; /* 0x00000180000da824 */
/* 0x100fe200078e0207 */
/*01b0*/ IADD3 R11, R8, R7, RZ ; /* 0x00000007080b7210 */
/* 0x000fe20007ffe0ff */
/*01c0*/ @!P0 IMAD R15, R0.reuse, 0x180, R7.reuse ; /* 0x00000180000f8824 */
/* 0x140fe200078e0207 */
/*01d0*/ ISETP.GT.OR P4, PT, R5, 0x3fb, P4 ; /* 0x000003fb0500780c */
/* 0x000fe20002784670 */
/*01e0*/ @!P3 IMAD R3, R0, 0x180, R7.reuse ; /* 0x000001800003b824 */
/* 0x101fe200078e0207 */
/*01f0*/ LEA R8, R4, R11, 0x2 ; /* 0x0000000b04087211 */
/* 0x000fe200078e10ff */
/*0200*/ @!P1 IMAD R17, R0, 0x180, R7 ; /* 0x0000018000119824 */
/* 0x000fe200078e0207 */
/*0210*/ @!P2 LEA R2, R4, R13, 0x2 ; /* 0x0000000d0402a211 */
/* 0x000fc400078e10ff */
/*0220*/ @!P3 LEA R3, R4.reuse, R3, 0x2 ; /* 0x000000030403b211 */
/* 0x040fe200078e10ff */
/*0230*/ STS [R8], RZ ; /* 0x000000ff08007388 */
/* 0x0001e20000000800 */
/*0240*/ @!P0 LEA R15, R4.reuse, R15, 0x2 ; /* 0x0000000f040f8211 */
/* 0x040fe400078e10ff */
/*0250*/ @!P1 LEA R17, R4, R17, 0x2 ; /* 0x0000001104119211 */
/* 0x000fe200078e10ff */
/*0260*/ @!P2 I2F.U16 R9, R9 ; /* 0x000000090009a306 */
/* 0x004e700000101000 */
/*0270*/ @!P3 I2F.U16 R10, R10 ; /* 0x0000000a000ab306 */
/* 0x008eb00000101000 */
/*0280*/ @!P0 I2F.U16 R12, R12 ; /* 0x0000000c000c8306 */
/* 0x010ee20000101000 */
/*0290*/ @!P2 STS [R2], R9 ; /* 0x000000090200a388 */
/* 0x0021ee0000000800 */
/*02a0*/ @!P1 I2F.U16 R14, R14 ; /* 0x0000000e000e9306 */
/* 0x020e620000101000 */
/*02b0*/ @!P3 STS [R3+0x100], R10 ; /* 0x0001000a0300b388 */
/* 0x0041e80000000800 */
/*02c0*/ @!P0 STS [R15+0xc00], R12 ; /* 0x000c000c0f008388 */
/* 0x0081e80000000800 */
/*02d0*/ @!P1 STS [R17+0xd00], R14 ; /* 0x000d000e11009388 */
/* 0x0021e80000000800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @P4 EXIT ; /* 0x000000000000494d */
/* 0x000fea0003800000 */
/*0300*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x001e240000002500 */
/*0310*/ SHF.L.U32 R10, R9, 0x3, RZ ; /* 0x00000003090a7819 */
/* 0x001fc800000006ff */
/*0320*/ ISETP.NE.AND P0, PT, R10, 0x7ffffff8, PT ; /* 0x7ffffff80a00780c */
/* 0x000fda0003f05270 */
/*0330*/ @!P0 BRA 0x930 ; /* 0x000005f000008947 */
/* 0x000fea0003800000 */
/*0340*/ IMAD R12, R9, 0x640, R4 ; /* 0x00000640090c7824 */
/* 0x000fe200078e0204 */
/*0350*/ IADD3 R13, R10, 0x8, RZ ; /* 0x000000080a0d7810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.GT.AND P0, PT, R10.reuse, 0x7f, PT ; /* 0x0000007f0a00780c */
/* 0x040fe40003f04270 */
/*0370*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.AND P1, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fce0003f26270 */
/*0390*/ @P0 BRA 0x900 ; /* 0x0000056000000947 */
/* 0x000fea0003800000 */
/*03a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*03b0*/ IMAD.WIDE R2, R12, R3, c[0x0][0x168] ; /* 0x00005a000c027625 */
/* 0x000fca00078e0203 */
/*03c0*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R25, [R2.64+0x20] ; /* 0x0000200402197981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R19, [R2.64+0x40] ; /* 0x0000400402137981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R17, [R2.64+0x60] ; /* 0x0000600402117981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R24, [R2.64+0x80] ; /* 0x0000800402187981 */
/* 0x000f68000c1e1900 */
/*0410*/ LDG.E R16, [R2.64+0xa0] ; /* 0x0000a00402107981 */
/* 0x000f62000c1e1900 */
/*0420*/ IMAD R15, R0, 0x180, R7 ; /* 0x00000180000f7824 */
/* 0x000fc600078e0207 */
/*0430*/ LDG.E R14, [R2.64+0xc0] ; /* 0x0000c004020e7981 */
/* 0x000f64000c1e1900 */
/*0440*/ LEA R15, R4, R15, 0x2 ; /* 0x0000000f040f7211 */
/* 0x000fe400078e10ff */
/*0450*/ LDG.E R23, [R2.64+0xe0] ; /* 0x0000e00402177981 */
/* 0x000f68000c1e1900 */
/*0460*/ LDS R21, [R15] ; /* 0x000000000f157984 */
/* 0x000ea80000000800 */
/*0470*/ LDS R26, [R15+0x20] ; /* 0x000020000f1a7984 */
/* 0x000ee80000000800 */
/*0480*/ LDS R18, [R15+0x40] ; /* 0x000040000f127984 */
/* 0x000f280000000800 */
/*0490*/ LDG.E R22, [R2.64+0x100] ; /* 0x0001000402167981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDS R27, [R15+0x60] ; /* 0x000060000f1b7984 */
/* 0x000f680000000800 */
/*04b0*/ LDS R28, [R15+0x4c0] ; /* 0x0004c0000f1c7984 */
/* 0x000fe20000000800 */
/*04c0*/ FFMA R20, R20, R21, RZ ; /* 0x0000001514147223 */
/* 0x004fc600000000ff */
/*04d0*/ LDG.E R21, [R2.64+0x120] ; /* 0x0001200402157981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ FFMA R25, R25, R26, R20 ; /* 0x0000001a19197223 */
/* 0x008fc60000000014 */
/*04f0*/ LDG.E R20, [R2.64+0x140] ; /* 0x0001400402147981 */
/* 0x000ee2000c1e1900 */
/*0500*/ FFMA R26, R19, R18, R25 ; /* 0x00000012131a7223 */
/* 0x010fc60000000019 */
/*0510*/ LDG.E R19, [R2.64+0x160] ; /* 0x0001600402137981 */
/* 0x000f28000c1e1900 */
/*0520*/ LDG.E R18, [R2.64+0x180] ; /* 0x0001800402127981 */
/* 0x000f22000c1e1900 */
/*0530*/ FFMA R27, R17, R27, R26 ; /* 0x0000001b111b7223 */
/* 0x020fc6000000001a */
/*0540*/ LDG.E R17, [R2.64+0x1a0] ; /* 0x0001a00402117981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDS R25, [R15+0x80] ; /* 0x000080000f197984 */
/* 0x000e280000000800 */
/*0560*/ LDS R26, [R15+0x1a0] ; /* 0x0001a0000f1a7984 */
/* 0x000fe20000000800 */
/*0570*/ FFMA R25, R24, R25, R27 ; /* 0x0000001918197223 */
/* 0x001fc6000000001b */
/*0580*/ LDS R24, [R15+0x180] ; /* 0x000180000f187984 */
/* 0x000e280000000800 */
/*0590*/ LDS R27, [R15+0x200] ; /* 0x000200000f1b7984 */
/* 0x000fe20000000800 */
/*05a0*/ FFMA R25, R16, R24, R25 ; /* 0x0000001810197223 */
/* 0x001fc60000000019 */
/*05b0*/ LDS R24, [R15+0x1c0] ; /* 0x0001c0000f187984 */
/* 0x000e280000000800 */
/*05c0*/ LDG.E R16, [R2.64+0x1c0] ; /* 0x0001c00402107981 */
/* 0x000362000c1e1900 */
/*05d0*/ FFMA R14, R14, R26, R25 ; /* 0x0000001a0e0e7223 */
/* 0x000fc60000000019 */
/*05e0*/ LDS R26, [R15+0x1e0] ; /* 0x0001e0000f1a7984 */
/* 0x000e620000000800 */
/*05f0*/ FFMA R25, R23, R24, R14 ; /* 0x0000001817197223 */
/* 0x001fc6000000000e */
/*0600*/ LDS R23, [R15+0x300] ; /* 0x000300000f177984 */
/* 0x000ee80000000800 */
/*0610*/ LDG.E R14, [R2.64+0x1e0] ; /* 0x0001e004020e7981 */
/* 0x000168000c1e1900 */
/*0620*/ LDS R24, [R15+0x320] ; /* 0x000320000f187984 */
/* 0x000f220000000800 */
/*0630*/ FFMA R26, R22, R26, R25 ; /* 0x0000001a161a7223 */
/* 0x002fc60000000019 */
/*0640*/ LDG.E R22, [R2.64+0x200] ; /* 0x0002000402167981 */
/* 0x000168000c1e1900 */
/*0650*/ LDS R25, [R15+0x340] ; /* 0x000340000f197984 */
/* 0x000e620000000800 */
/*0660*/ FFMA R26, R21, R27, R26 ; /* 0x0000001b151a7223 */
/* 0x004fc6000000001a */
/*0670*/ LDG.E R21, [R2.64+0x220] ; /* 0x0002200402157981 */
/* 0x0000a2000c1e1900 */
/*0680*/ FFMA R23, R20, R23, R26 ; /* 0x0000001714177223 */
/* 0x008fc6000000001a */
/*0690*/ LDS R26, [R15+0x360] ; /* 0x000360000f1a7984 */
/* 0x000f680000000800 */
/*06a0*/ LDG.E R20, [R2.64+0x240] ; /* 0x0002400402147981 */
/* 0x0000e2000c1e1900 */
/*06b0*/ FFMA R24, R19, R24, R23 ; /* 0x0000001813187223 */
/* 0x010fc60000000017 */
/*06c0*/ LDG.E R23, [R2.64+0x260] ; /* 0x0002600402177981 */
/* 0x000122000c1e1900 */
/*06d0*/ FFMA R25, R18, R25, R24 ; /* 0x0000001912197223 */
/* 0x002fc60000000018 */
/*06e0*/ LDG.E R19, [R2.64+0x280] ; /* 0x0002800402137981 */
/* 0x000128000c1e1900 */
/*06f0*/ LDG.E R24, [R2.64+0x2a0] ; /* 0x0002a00402187981 */
/* 0x000128000c1e1900 */
/*0700*/ LDG.E R18, [R2.64+0x2c0] ; /* 0x0002c00402127981 */
/* 0x000122000c1e1900 */
/*0710*/ FFMA R27, R17, R26, R25 ; /* 0x0000001a111b7223 */
/* 0x020fc60000000019 */
/*0720*/ LDG.E R17, [R2.64+0x2e0] ; /* 0x0002e00402117981 */
/* 0x000168000c1e1900 */
/*0730*/ LDG.E R25, [R2.64+0x300] ; /* 0x0003000402197981 */
/* 0x000168000c1e1900 */
/*0740*/ LDS R26, [R15+0x380] ; /* 0x000380000f1a7984 */
/* 0x000e680000000800 */
/*0750*/ LDS R3, [R15+0x640] ; /* 0x000640000f037984 */
/* 0x001fe80000000800 */
/*0760*/ LDS R2, [R15+0x660] ; /* 0x000660000f027984 */
/* 0x000fe20000000800 */
/*0770*/ FFMA R27, R16, R26, R27 ; /* 0x0000001a101b7223 */
/* 0x002fc6000000001b */
/*0780*/ LDS R16, [R15+0x480] ; /* 0x000480000f107984 */
/* 0x000e280000000800 */
/*0790*/ LDS R26, [R15+0x4a0] ; /* 0x0004a0000f1a7984 */
/* 0x000e620000000800 */
/*07a0*/ FFMA R29, R14, R16, R27 ; /* 0x000000100e1d7223 */
/* 0x001fc6000000001b */
/*07b0*/ LDS R27, [R15+0x4e0] ; /* 0x0004e0000f1b7984 */
/* 0x000ee80000000800 */
/*07c0*/ LDS R16, [R15+0x500] ; /* 0x000500000f107984 */
/* 0x000f220000000800 */
/*07d0*/ FFMA R22, R22, R26, R29 ; /* 0x0000001a16167223 */
/* 0x002fc6000000001d */
/*07e0*/ LDS R14, [R15+0x600] ; /* 0x000600000f0e7984 */
/* 0x000e220000000800 */
/*07f0*/ BSSY B0, 0x900 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0800*/ FFMA R22, R21, R28, R22 ; /* 0x0000001c15167223 */
/* 0x004fe40000000016 */
/*0810*/ LDS R21, [R15+0x620] ; /* 0x000620000f157984 */
/* 0x000e640000000800 */
/*0820*/ FFMA R20, R20, R27, R22 ; /* 0x0000001b14147223 */
/* 0x008fe40000000016 */
/*0830*/ LDS R22, [R15+0x680] ; /* 0x000680000f167984 */
/* 0x000ea40000000800 */
/*0840*/ FFMA R16, R23, R16, R20 ; /* 0x0000001017107223 */
/* 0x010fc80000000014 */
/*0850*/ FFMA R14, R19, R14, R16 ; /* 0x0000000e130e7223 */
/* 0x001fc80000000010 */
/*0860*/ FFMA R14, R24, R21, R14 ; /* 0x00000015180e7223 */
/* 0x002fc8000000000e */
/*0870*/ FFMA R14, R18, R3, R14 ; /* 0x00000003120e7223 */
/* 0x000fc8000000000e */
/*0880*/ FFMA R2, R17, R2, R14 ; /* 0x0000000211027223 */
/* 0x020fc8000000000e */
/*0890*/ FFMA R25, R25, R22, R2 ; /* 0x0000001619197223 */
/* 0x004fe40000000002 */
/*08a0*/ LDS R2, [R11] ; /* 0x000000000b027984 */
/* 0x000e240000000800 */
/*08b0*/ FADD R3, R25, R2 ; /* 0x0000000219037221 */
/* 0x001fcc0000000000 */
/*08c0*/ ATOMS.CAST.SPIN R3, [R11], R2, R3 ; /* 0x000000020b03738d */
/* 0x000e240001800003 */
/*08d0*/ ISETP.EQ.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x001fda0003f02070 */
/*08e0*/ @!P0 BRA 0x8a0 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007ffe0ff */
/*0910*/ IADD3 R12, R12, 0xc8, RZ ; /* 0x000000c80c0c7810 */
/* 0x000fe20007ffe0ff */
/*0920*/ @!P1 BRA 0x360 ; /* 0xfffffa3000009947 */
/* 0x000fea000383ffff */
/*0930*/ LDS R7, [R8] ; /* 0x0000000008077984 */
/* 0x000e220000000800 */
/*0940*/ IMAD R4, R9, c[0x0][0x0], R4 ; /* 0x0000000009047a24 */
/* 0x000fe200078e0204 */
/*0950*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0960*/ IMAD R5, R5, 0x3fc, R6 ; /* 0x000003fc05057824 */
/* 0x000fc800078e0206 */
/*0970*/ IMAD R2, R4, 0xfe010, R5 ; /* 0x000fe01004027824 */
/* 0x000fc800078e0205 */
/*0980*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0990*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*09a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14convolution_3dPhPfS0_
.globl _Z14convolution_3dPhPfS0_
.p2align 8
.type _Z14convolution_3dPhPfS0_,@function
_Z14convolution_3dPhPfS0_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v7, 2, v1
v_lshlrev_b32_e32 v8, 5, v6
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1]
v_lshlrev_b32_e32 v5, 8, v0
s_lshr_b32 s3, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v9, v5, v8, v7
v_mul_u32_u24_e32 v5, 0x180, v0
v_lshl_or_b32 v10, v4, 13, v1
s_mov_b32 s3, 0
v_add_nc_u32_e32 v3, 0x1200, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v5, v5, v8, v7
v_lshl_add_u32 v7, v2, 3, v10
ds_store_b32 v9, v11 offset:4608
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
v_add_nc_u32_e32 v5, 0xc00, v5
v_add_nc_u32_e32 v7, 0x10000, v7
s_add_i32 s6, s3, 1
s_cmp_lg_u32 s3, 0
s_mov_b32 s3, s6
s_cbranch_scc1 .LBB0_6
.LBB0_2:
v_lshl_add_u32 v8, s3, 3, v0
s_mov_b32 s7, 0
v_mov_b32_e32 v9, v6
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_u32_e32 vcc_lo, 11, v8
v_mov_b32_e32 v8, v7
s_xor_b32 s6, vcc_lo, -1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v9, 8, v9
v_add_nc_u32_e32 v8, 64, v8
s_addk_i32 s7, 0x100
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s7, 0x100
s_cbranch_scc1 .LBB0_1
.LBB0_4:
v_cmp_gt_u32_e32 vcc_lo, 12, v9
s_and_b32 s9, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s8, s9
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v11, 31, v8
v_add_co_u32 v10, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_u8 v10, v[10:11], off
v_add_nc_u32_e32 v11, s7, v5
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v10, v10
ds_store_b32 v11, v10
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_max_i32_e32 v5, v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e32 0x3fc, v5
s_cbranch_execz .LBB0_17
s_lshl_b32 s3, s13, 3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0x7ffffff8
s_cbranch_scc1 .LBB0_16
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_u32_u24_e32 v7, 0x180, v0
v_lshlrev_b32_e32 v8, 5, v6
v_lshlrev_b32_e32 v9, 2, v1
v_mad_u64_u32 v[5:6], null, s13, 0x640, v[1:2]
v_lshlrev_b32_e32 v0, 8, v0
s_add_i32 s6, s3, 8
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v9, v7, v8, v9
s_mov_b32 s7, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v5, 0xc8, v5
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s7, s6
s_cbranch_scc1 .LBB0_16
.LBB0_10:
s_cmpk_gt_i32 s7, 0x7f
s_cbranch_scc1 .LBB0_9
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, v9
v_mov_b32_e32 v12, v5
s_mov_b32 s8, -2
.p2align 6
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v12
s_mov_b32 s9, 0
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[13:14], 2, v[6:7]
v_add_nc_u32_e32 v6, 8, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
global_load_b32 v7, v[13:14], off
v_add_nc_u32_e32 v13, s9, v11
s_add_i32 s9, s9, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s9, 0xa0
ds_load_b32 v13, v13
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v10, v13, v7
s_cbranch_scc0 .LBB0_13
v_add_nc_u32_e32 v12, 40, v12
v_add_nc_u32_e32 v11, 0x180, v11
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 3
s_cbranch_scc0 .LBB0_12
s_sub_i32 s8, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s8, s8, 2
v_add3_u32 v6, v0, v8, s8
ds_add_f32 v6, v10 offset:4608
s_branch .LBB0_9
.LBB0_16:
s_set_inst_prefetch_distance 0x2
s_and_b32 s2, 0xffff, s2
v_mul_lo_u32 v0, v4, 0x3fc
v_mad_u64_u32 v[5:6], null, s13, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v5, 0xfe010
v_add3_u32 v0, v2, v1, v0
ds_load_b32 v2, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14convolution_3dPhPfS0_
.amdhsa_group_segment_fixed_size 6656
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14convolution_3dPhPfS0_, .Lfunc_end0-_Z14convolution_3dPhPfS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 6656
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14convolution_3dPhPfS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14convolution_3dPhPfS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fe6c7_00000000-6_ee16b105.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fillMatrixPh
.type _Z10fillMatrixPh, @function
_Z10fillMatrixPh:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbp
movl $0, %r12d
movl $0, %ebx
jmp .L4
.L11:
addl $1, %r8d
addl %r11d, %r9d
addq $8, %rsi
cmpl $1024, %r8d
je .L6
.L8:
leal (%r10,%r8), %edi
leaq -8(%rsi), %rcx
movl %r9d, %edx
.L5:
movslq %edx, %rax
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %r13d
sarl $31, %r13d
subl %r13d, %eax
movl %eax, %r13d
sall $8, %r13d
subl %eax, %r13d
movl %edx, %eax
subl %r13d, %eax
movb %al, (%rcx)
addl %edi, %edx
addq $1, %rcx
cmpq %rsi, %rcx
jne .L5
jmp .L11
.L6:
addl $1, %ebx
addl $2, %r12d
addq $8192, %rbp
cmpl $1024, %ebx
je .L3
.L4:
leal 3(%rbx), %r11d
leaq 8(%rbp), %rsi
movl %r12d, %r9d
movl $0, %r8d
leal 4(%rbx), %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10fillMatrixPh, .-_Z10fillMatrixPh
.globl _Z10fillKernelPf
.type _Z10fillKernelPf, @function
_Z10fillKernelPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 40(%rsp)
movl $-1, %r15d
jmp .L13
.L25:
movsd .LC2(%rip), %xmm1
movsd 8(%rsp), %xmm0
call fmod@PLT
jmp .L15
.L18:
subl $1, %r15d
addq $800, 40(%rsp)
cmpl $-129, %r15d
je .L12
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC5(%rip), %xmm0
movsd %xmm0, 32(%rsp)
movq 40(%rsp), %r14
movl $0, %r13d
.L21:
addl $1, %r13d
pxor %xmm0, %xmm0
cvtsi2sdl %r13d, %xmm0
mulsd .LC4(%rip), %xmm0
addsd 32(%rsp), %xmm0
movsd %xmm0, 24(%rsp)
movq %r14, %rbp
movl $0, %r12d
.L19:
addl $1, %r12d
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC3(%rip), %xmm0
movsd 24(%rsp), %xmm4
subsd %xmm0, %xmm4
movsd %xmm4, 16(%rsp)
movl $1, %ebx
.L16:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC0(%rip), %xmm0
addsd 16(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
fld1
fldl 8(%rsp)
.L14:
fprem
fnstsw %ax
testb $4, %ah
jne .L14
fstp %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm2
ucomisd %xmm2, %xmm2
jp .L25
.L15:
pxor %xmm0, %xmm0
cvtsd2ss (%rsp), %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
addq $1, %rbx
cmpq $9, %rbx
jne .L16
addq $32, %rbp
cmpl $5, %r12d
jne .L19
addq $160, %r14
cmpl $5, %r13d
jne .L21
jmp .L18
.L12:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10fillKernelPf, .-_Z10fillKernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "w"
.LC8:
.string "assignment4_out"
.LC9:
.string "%4.4f "
.LC10:
.string "\n"
.text
.globl _Z20print_matrix_to_filePf
.type _Z20print_matrix_to_filePf, @function
_Z20print_matrix_to_filePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %r15, %r14
addq $532684800, %r15
leaq .LC9(%rip), %r13
.L27:
leaq 4080(%r14), %rbp
.L31:
leaq -4080(%rbp), %rbx
.L28:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
addq $4080, %rbp
leaq 4165680(%r14), %rax
cmpq %rax, %rbp
jne .L31
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4161600, %r14
cmpq %r15, %r14
jne .L27
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z20print_matrix_to_filePf, .-_Z20print_matrix_to_filePf
.globl _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
.type _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_, @function
_Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14convolution_3dPhPfS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_, .-_Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
.globl _Z14convolution_3dPhPfS0_
.type _Z14convolution_3dPhPfS0_, @function
_Z14convolution_3dPhPfS0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z14convolution_3dPhPfS0_, .-_Z14convolution_3dPhPfS0_
.section .rodata.str1.1
.LC12:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call malloc@PLT
movq %rax, %r12
movl $102400, %edi
call malloc@PLT
movq %rax, %rbp
movl $532684800, %edi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call _Z10fillMatrixPh
movq %rbp, %rdi
call _Z10fillKernelPf
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $102400, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $532684800, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $102400, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 4(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl $16, 60(%rsp)
movl $128, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $8, %ecx
movq 60(%rsp), %rdi
movl $128, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L43:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $532684800, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z20print_matrix_to_filePf
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z14convolution_3dPhPfS0_PhPfS0_
jmp .L43
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z14convolution_3dPhPfS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z14convolution_3dPhPfS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1717986918
.long 1075603046
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 858993459
.long 1075000115
.align 8
.LC4:
.long -1717986918
.long 1074370969
.align 8
.LC5:
.long -858993459
.long 1073794252
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ee16b105.hip"
.globl _Z10fillMatrixPh # -- Begin function _Z10fillMatrixPh
.p2align 4, 0x90
.type _Z10fillMatrixPh,@function
_Z10fillMatrixPh: # @_Z10fillMatrixPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_2: # %.preheader
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
movl %r10d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, (%r11,%r14)
incq %r14
addl %r9d, %ebp
cmpq $8, %r14
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=2
incq %rbx
addq $8, %r11
addl %ecx, %r10d
incl %r9d
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_2
# %bb.5: # in Loop: Header=BB0_1 Depth=1
incq %r8
addq $8192, %rdi # imm = 0x2000
addl $2, %eax
incl %ecx
incl %edx
cmpq $1024, %r8 # imm = 0x400
jne .LBB0_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10fillMatrixPh, .Lfunc_end0-_Z10fillMatrixPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10fillKernelPf
.LCPI1_0:
.quad 0x4000cccccccccccd # double 2.1000000000000001
.LCPI1_1:
.quad 0x400999999999999a # double 3.2000000000000002
.LCPI1_2:
.quad 0xc013333333333333 # double -4.7999999999999998
.LCPI1_3:
.quad 0x401c666666666666 # double 7.0999999999999996
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z10fillKernelPf
.p2align 4, 0x90
.type _Z10fillKernelPf,@function
_Z10fillKernelPf: # @_Z10fillKernelPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader21
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
# Child Loop BB1_4 Depth 4
movq %rax, (%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
notl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
movq %rdi, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader20
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
# Child Loop BB1_4 Depth 4
incq %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
addsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_4 Depth 4
incq %rbp
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
addsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# Parent Loop BB1_3 Depth=3
# => This Inner Loop Header: Depth=4
leaq 1(%rbx), %r14
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
mulsd %xmm1, %xmm0
addsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movaps %xmm2, %xmm1
callq fmod
movsd .LCPI1_4(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbx,4)
movq %r14, %rbx
cmpq $8, %r14
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=3
addq $32, %r13
cmpq $5, %rbp
jne .LBB1_3
# %bb.6: # in Loop: Header=BB1_2 Depth=2
addq $160, %r15
cmpq $5, %r12
jne .LBB1_2
# %bb.7: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rax # 8-byte Reload
incq %rax
movq 8(%rsp), %rdi # 8-byte Reload
addq $800, %rdi # imm = 0x320
cmpq $128, %rax
jne .LBB1_1
# %bb.8:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10fillKernelPf, .Lfunc_end1-_Z10fillKernelPf
.cfi_endproc
# -- End function
.globl _Z20print_matrix_to_filePf # -- Begin function _Z20print_matrix_to_filePf
.p2align 4, 0x90
.type _Z20print_matrix_to_filePf,@function
_Z20print_matrix_to_filePf: # @_Z20print_matrix_to_filePf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $1020, %rbp # imm = 0x3FC
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=2
incq %r13
addq $4080, %r12 # imm = 0xFF0
cmpq $1020, %r13 # imm = 0x3FC
jne .LBB2_2
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addq $4161600, %rbx # imm = 0x3F8040
cmpq $128, %r15
jne .LBB2_1
# %bb.6:
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end2:
.size _Z20print_matrix_to_filePf, .Lfunc_end2-_Z20print_matrix_to_filePf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__convolution_3dPhPfS0_ # -- Begin function _Z29__device_stub__convolution_3dPhPfS0_
.p2align 4, 0x90
.type _Z29__device_stub__convolution_3dPhPfS0_,@function
_Z29__device_stub__convolution_3dPhPfS0_: # @_Z29__device_stub__convolution_3dPhPfS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14convolution_3dPhPfS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__convolution_3dPhPfS0_, .Lfunc_end3-_Z29__device_stub__convolution_3dPhPfS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x4000cccccccccccd # double 2.1000000000000001
.LCPI4_1:
.quad 0x400999999999999a # double 3.2000000000000002
.LCPI4_2:
.quad 0xc013333333333333 # double -4.7999999999999998
.LCPI4_3:
.quad 0x401c666666666666 # double 7.0999999999999996
.LCPI4_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
movl $102400, %edi # imm = 0x19000
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl $532684800, %edi # imm = 0x1FC02000
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
movq %rbx, 64(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_1: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
movl %r10d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, (%r11,%r14)
incq %r14
addl %r9d, %ebp
cmpq $8, %r14
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rbx
addq $8, %r11
addl %ecx, %r10d
incl %r9d
cmpq $1024, %rbx # imm = 0x400
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %r8
addq $8192, %rdi # imm = 0x2000
addl $2, %eax
incl %ecx
incl %edx
cmpq $1024, %r8 # imm = 0x400
jne .LBB4_1
# %bb.6: # %.preheader21.i.preheader
xorl %eax, %eax
movsd .LCPI4_3(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI4_4(%rip), %xmm2 # xmm2 = mem[0],zero
movq 16(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB4_7: # %.preheader21.i
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
movq %rax, 88(%rsp) # 8-byte Spill
# kill: def $eax killed $eax killed $rax
notl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
movq %r13, 80(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_8: # %.preheader20.i
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
incq %rbx
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
addsd 96(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq %r13, %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_9: # %.preheader.i18
# Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_10 Depth 4
incq %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd .LCPI4_2(%rip), %xmm0
addsd 104(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 112(%rsp) # 8-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# Parent Loop BB4_9 Depth=3
# => This Inner Loop Header: Depth=4
leaq 1(%r14), %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
mulsd %xmm1, %xmm0
addsd 112(%rsp), %xmm0 # 8-byte Folded Reload
movaps %xmm2, %xmm1
callq fmod
movsd .LCPI4_4(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI4_3(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%r14,4)
movq %r12, %r14
cmpq $8, %r12
jne .LBB4_10
# %bb.11: # in Loop: Header=BB4_9 Depth=3
addq $32, %rbp
cmpq $5, %r15
jne .LBB4_9
# %bb.12: # in Loop: Header=BB4_8 Depth=2
addq $160, %r13
cmpq $5, %rbx
jne .LBB4_8
# %bb.13: # in Loop: Header=BB4_7 Depth=1
movq 88(%rsp), %rax # 8-byte Reload
incq %rax
movq 80(%rsp), %r13 # 8-byte Reload
addq $800, %r13 # imm = 0x320
cmpq $128, %rax
jne .LBB4_7
# %bb.14: # %_Z10fillKernelPf.exit
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $102400, %esi # imm = 0x19000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $532684800, %esi # imm = 0x1FC02000
callq hipMalloc
movq 48(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq 64(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $102400, %edx # imm = 0x19000
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $549755813904, %rdi # imm = 0x8000000010
movabsq $34359738376, %rdx # imm = 0x800000008
movl $128, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z14convolution_3dPhPfS0_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movl $532684800, %edx # imm = 0x1FC02000
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
.p2align 4, 0x90
.LBB4_17: # %.preheader16.i
# =>This Loop Header: Depth=1
# Child Loop BB4_18 Depth 2
# Child Loop BB4_19 Depth 3
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # %.preheader.i24
# Parent Loop BB4_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_19 Depth 3
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_17 Depth=1
# Parent Loop BB4_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $1020, %rbp # imm = 0x3FC
jne .LBB4_19
# %bb.20: # in Loop: Header=BB4_18 Depth=2
incq %r15
addq $4080, %r14 # imm = 0xFF0
cmpq $1020, %r15 # imm = 0x3FC
jne .LBB4_18
# %bb.21: # in Loop: Header=BB4_17 Depth=1
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
incq %r13
addq $4161600, %rbx # imm = 0x3F8040
cmpq $128, %r13
jne .LBB4_17
# %bb.22: # %_Z20print_matrix_to_filePf.exit
movq %r12, %rdi
callq fclose
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14convolution_3dPhPfS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "assignment4_out"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type _Z14convolution_3dPhPfS0_,@object # @_Z14convolution_3dPhPfS0_
.section .rodata,"a",@progbits
.globl _Z14convolution_3dPhPfS0_
.p2align 3, 0x0
_Z14convolution_3dPhPfS0_:
.quad _Z29__device_stub__convolution_3dPhPfS0_
.size _Z14convolution_3dPhPfS0_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%f\n"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14convolution_3dPhPfS0_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__convolution_3dPhPfS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14convolution_3dPhPfS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void breadth_first_search_csr_gpu(unsigned int* cum_row_indexes, unsigned int* column_indexes, int* matrix_data, unsigned int* in_infections, unsigned int* out_infections, unsigned int rows) {
unsigned int row = blockDim.x * blockIdx.x + threadIdx.x;
if (row < rows) {
if (in_infections[row] == 1) {
out_infections[row] = 1;
unsigned int row_start = cum_row_indexes[row];
unsigned int row_end = cum_row_indexes[row+1];
for (int i = row_start; i < row_end; i++) {
int timesteps_to_transmission = matrix_data[i];
if (timesteps_to_transmission != 0) {
if (timesteps_to_transmission == 1) {
out_infections[column_indexes[i]] = 1;
}
matrix_data[i] -= 1;
}
}
}
}
} | code for sm_80
Function : _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R8, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fcc00078e0008 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x1e, R0 ; /* 0x0000001eff037819 */
/* 0x000fe20000011600 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe40007ffe0ff */
/*0100*/ IADD3 R4, P0, R6.reuse, c[0x0][0x180], RZ ; /* 0x0000600006047a10 */
/* 0x040fe40007f1e0ff */
/*0110*/ IADD3 R6, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R5, R3.reuse, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610003057a10 */
/* 0x040fe400007fe4ff */
/*0130*/ IADD3.X R7, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003077a10 */
/* 0x000fe20000ffe4ff */
/*0140*/ IMAD.WIDE.U32 R2, R2, R8, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc400078e0008 */
/*0150*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c101904 */
/*0160*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0180*/ ISETP.GT.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f04070 */
/*0190*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.IADD R2, R0, 0x1, -R11 ; /* 0x0000000100027824 */
/* 0x001fe200078e0a0b */
/*01b0*/ BSSY B0, 0x400 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*01c0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*01d0*/ LOP3.LUT P0, R6, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302067812 */
/* 0x000fda000780c0ff */
/*01e0*/ @!P0 BRA 0x3f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.WIDE R2, R11, R8, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fc800078e0208 */
/*0200*/ IMAD.WIDE R4, R11, R8, c[0x0][0x170] ; /* 0x00005c000b047625 */
/* 0x000fc800078e0208 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0250*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0270*/ BSSY B1, 0x390 ; /* 0x0000011000017945 */
/* 0x000fe60003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f05270 */
/*0290*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f25270 */
/*02a0*/ @!P1 BRA 0x380 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*02b0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*02c0*/ BSSY B2, 0x360 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*02d0*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f25270 */
/*02e0*/ @P1 BRA 0x350 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x004fca00078e0007 */
/*0330*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000164000c1e1900 */
/*0350*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0360*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x021fca0007ffe0ff */
/*0370*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0380*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*03a0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe40007f5e0ff */
/*03b0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*03d0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*03e0*/ @P0 BRA 0x250 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT R5, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff057212 */
/* 0x000fc800078e33ff */
/*0410*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0460*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0206 */
/*0470*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0480*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0490*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0006 */
/*04b0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ BSSY B0, 0x5e0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*04e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*04f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0500*/ @!P0 BRA 0x5d0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0520*/ BSSY B1, 0x5b0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0530*/ @P0 BRA 0x5a0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0540*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*0580*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*0590*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000164000c1e1900 */
/*05a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05b0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*05c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040404027981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ BSSY B0, 0x6f0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0610*/ @!P0 BRA 0x6e0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0630*/ BSSY B1, 0x6c0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0640*/ @P0 BRA 0x6b0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x000ea2000c1e1900 */
/*0660*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fe200000001ff */
/*0670*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fd200078e00ff */
/*0680*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*0690*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*06a0*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040404027981 */
/* 0x000164000c1e1900 */
/*06b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06c0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*06d0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e4000c101904 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ LDG.E R2, [R4.64+0x8] ; /* 0x0000080404027981 */
/* 0x000ea2000c1e1900 */
/*0700*/ BSSY B0, 0x800 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0710*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0720*/ @!P0 BRA 0x7f0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0740*/ BSSY B1, 0x7d0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0750*/ @P0 BRA 0x7c0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x001fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0790*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*07a0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*07b0*/ LDG.E R2, [R4.64+0x8] ; /* 0x0000080404027981 */
/* 0x000164000c1e1900 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*07e0*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0001e4000c101904 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E R2, [R4.64+0xc] ; /* 0x00000c0404027981 */
/* 0x000ea2000c1e1900 */
/*0810*/ BSSY B0, 0x910 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0830*/ @!P0 BRA 0x900 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0850*/ BSSY B1, 0x8e0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0860*/ @P0 BRA 0x8d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0870*/ LDG.E R8, [R6.64+0xc] ; /* 0x00000c0406087981 */
/* 0x000ea2000c1e1900 */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x001fe200078e00ff */
/*0890*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fc60000000f00 */
/*08a0*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*08b0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*08c0*/ LDG.E R2, [R4.64+0xc] ; /* 0x00000c0404027981 */
/* 0x000164000c1e1900 */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*08f0*/ STG.E [R4.64+0xc], R9 ; /* 0x00000c0904007986 */
/* 0x0001e4000c101904 */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x001fe40007f3e0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe40003f06070 */
/*0940*/ IADD3 R8, P2, R6, 0x10, RZ ; /* 0x0000001006087810 */
/* 0x000fe20007f5e0ff */
/*0950*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0605 */
/*0960*/ IMAD.X R9, RZ, RZ, R7, P2 ; /* 0x000000ffff097224 */
/* 0x000fcc00010e0607 */
/*0970*/ @!P0 BRA 0x4b0 ; /* 0xfffffb3000008947 */
/* 0x000fea000383ffff */
/*0980*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0990*/ BRA 0x990; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void breadth_first_search_csr_gpu(unsigned int* cum_row_indexes, unsigned int* column_indexes, int* matrix_data, unsigned int* in_infections, unsigned int* out_infections, unsigned int rows) {
unsigned int row = blockDim.x * blockIdx.x + threadIdx.x;
if (row < rows) {
if (in_infections[row] == 1) {
out_infections[row] = 1;
unsigned int row_start = cum_row_indexes[row];
unsigned int row_end = cum_row_indexes[row+1];
for (int i = row_start; i < row_end; i++) {
int timesteps_to_transmission = matrix_data[i];
if (timesteps_to_transmission != 0) {
if (timesteps_to_transmission == 1) {
out_infections[column_indexes[i]] = 1;
}
matrix_data[i] -= 1;
}
}
}
}
} | .file "tmpxft_000646c9_00000000-6_breadth_first_search_csr_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j
.type _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j, @function
_Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28breadth_first_search_csr_gpuPjS_PiS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j, .-_Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j
.globl _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.type _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, @function
_Z28breadth_first_search_csr_gpuPjS_PiS_S_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, .-_Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28breadth_first_search_csr_gpuPjS_PiS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28breadth_first_search_csr_gpuPjS_PiS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void breadth_first_search_csr_gpu(unsigned int* cum_row_indexes, unsigned int* column_indexes, int* matrix_data, unsigned int* in_infections, unsigned int* out_infections, unsigned int rows) {
unsigned int row = blockDim.x * blockIdx.x + threadIdx.x;
if (row < rows) {
if (in_infections[row] == 1) {
out_infections[row] = 1;
unsigned int row_start = cum_row_indexes[row];
unsigned int row_end = cum_row_indexes[row+1];
for (int i = row_start; i < row_end; i++) {
int timesteps_to_transmission = matrix_data[i];
if (timesteps_to_transmission != 0) {
if (timesteps_to_transmission == 1) {
out_infections[column_indexes[i]] = 1;
}
matrix_data[i] -= 1;
}
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void breadth_first_search_csr_gpu(unsigned int* cum_row_indexes, unsigned int* column_indexes, int* matrix_data, unsigned int* in_infections, unsigned int* out_infections, unsigned int rows) {
unsigned int row = blockDim.x * blockIdx.x + threadIdx.x;
if (row < rows) {
if (in_infections[row] == 1) {
out_infections[row] = 1;
unsigned int row_start = cum_row_indexes[row];
unsigned int row_end = cum_row_indexes[row+1];
for (int i = row_start; i < row_end; i++) {
int timesteps_to_transmission = matrix_data[i];
if (timesteps_to_transmission != 0) {
if (timesteps_to_transmission == 1) {
out_infections[column_indexes[i]] = 1;
}
matrix_data[i] -= 1;
}
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void breadth_first_search_csr_gpu(unsigned int* cum_row_indexes, unsigned int* column_indexes, int* matrix_data, unsigned int* in_infections, unsigned int* out_infections, unsigned int rows) {
unsigned int row = blockDim.x * blockIdx.x + threadIdx.x;
if (row < rows) {
if (in_infections[row] == 1) {
out_infections[row] = 1;
unsigned int row_start = cum_row_indexes[row];
unsigned int row_end = cum_row_indexes[row+1];
for (int i = row_start; i < row_end; i++) {
int timesteps_to_transmission = matrix_data[i];
if (timesteps_to_transmission != 0) {
if (timesteps_to_transmission == 1) {
out_infections[column_indexes[i]] = 1;
}
matrix_data[i] -= 1;
}
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.globl _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.p2align 8
.type _Z28breadth_first_search_csr_gpuPjS_PiS_S_j,@function
_Z28breadth_first_search_csr_gpuPjS_PiS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v1, 1, v1
v_mov_b32_e32 v7, 1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[5:6], v7, off
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v6, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v0, v8
v_add_co_u32 v3, s0, v3, 4
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_13
.LBB0_5:
global_load_b32 v5, v[1:2], off
s_mov_b32 s0, 0
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v5
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_9
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 1, v5
s_cbranch_execz .LBB0_8
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_store_b32 v[9:10], v7, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s4, s4
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s5
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_4
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, -1, v5
global_store_b32 v[1:2], v5, off
s_branch .LBB0_4
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, .Lfunc_end0-_Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28breadth_first_search_csr_gpuPjS_PiS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void breadth_first_search_csr_gpu(unsigned int* cum_row_indexes, unsigned int* column_indexes, int* matrix_data, unsigned int* in_infections, unsigned int* out_infections, unsigned int rows) {
unsigned int row = blockDim.x * blockIdx.x + threadIdx.x;
if (row < rows) {
if (in_infections[row] == 1) {
out_infections[row] = 1;
unsigned int row_start = cum_row_indexes[row];
unsigned int row_end = cum_row_indexes[row+1];
for (int i = row_start; i < row_end; i++) {
int timesteps_to_transmission = matrix_data[i];
if (timesteps_to_transmission != 0) {
if (timesteps_to_transmission == 1) {
out_infections[column_indexes[i]] = 1;
}
matrix_data[i] -= 1;
}
}
}
}
} | .text
.file "breadth_first_search_csr_gpu.hip"
.globl _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j # -- Begin function _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.p2align 4, 0x90
.type _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j,@function
_Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j: # @_Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28breadth_first_search_csr_gpuPjS_PiS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j, .Lfunc_end0-_Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28breadth_first_search_csr_gpuPjS_PiS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28breadth_first_search_csr_gpuPjS_PiS_S_j,@object # @_Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.section .rodata,"a",@progbits
.globl _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.p2align 3, 0x0
_Z28breadth_first_search_csr_gpuPjS_PiS_S_j:
.quad _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.size _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28breadth_first_search_csr_gpuPjS_PiS_S_j"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R8, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fcc00078e0008 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x1e, R0 ; /* 0x0000001eff037819 */
/* 0x000fe20000011600 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe40007ffe0ff */
/*0100*/ IADD3 R4, P0, R6.reuse, c[0x0][0x180], RZ ; /* 0x0000600006047a10 */
/* 0x040fe40007f1e0ff */
/*0110*/ IADD3 R6, P1, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R5, R3.reuse, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610003057a10 */
/* 0x040fe400007fe4ff */
/*0130*/ IADD3.X R7, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003077a10 */
/* 0x000fe20000ffe4ff */
/*0140*/ IMAD.WIDE.U32 R2, R2, R8, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc400078e0008 */
/*0150*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c101904 */
/*0160*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0180*/ ISETP.GT.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f04070 */
/*0190*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.IADD R2, R0, 0x1, -R11 ; /* 0x0000000100027824 */
/* 0x001fe200078e0a0b */
/*01b0*/ BSSY B0, 0x400 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*01c0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*01d0*/ LOP3.LUT P0, R6, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302067812 */
/* 0x000fda000780c0ff */
/*01e0*/ @!P0 BRA 0x3f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.WIDE R2, R11, R8, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fc800078e0208 */
/*0200*/ IMAD.WIDE R4, R11, R8, c[0x0][0x170] ; /* 0x00005c000b047625 */
/* 0x000fc800078e0208 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0003 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0250*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0270*/ BSSY B1, 0x390 ; /* 0x0000011000017945 */
/* 0x000fe60003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f05270 */
/*0290*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f25270 */
/*02a0*/ @!P1 BRA 0x380 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*02b0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*02c0*/ BSSY B2, 0x360 ; /* 0x0000009000027945 */
/* 0x000fe60003800000 */
/*02d0*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f25270 */
/*02e0*/ @P1 BRA 0x350 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x004fca00078e0007 */
/*0330*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000164000c1e1900 */
/*0350*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0360*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x021fca0007ffe0ff */
/*0370*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0380*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*03a0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe40007f5e0ff */
/*03b0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0609 */
/*03d0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*03e0*/ @P0 BRA 0x250 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT R5, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff057212 */
/* 0x000fc800078e33ff */
/*0410*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0460*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0206 */
/*0470*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0480*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0490*/ MOV R5, R7 ; /* 0x0000000700057202 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0006 */
/*04b0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ BSSY B0, 0x5e0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*04e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*04f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0500*/ @!P0 BRA 0x5d0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0520*/ BSSY B1, 0x5b0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0530*/ @P0 BRA 0x5a0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0540*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*0580*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*0590*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000164000c1e1900 */
/*05a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05b0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*05c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040404027981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ BSSY B0, 0x6f0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0600*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0610*/ @!P0 BRA 0x6e0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0630*/ BSSY B1, 0x6c0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0640*/ @P0 BRA 0x6b0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x000ea2000c1e1900 */
/*0660*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fe200000001ff */
/*0670*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fd200078e00ff */
/*0680*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*0690*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*06a0*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040404027981 */
/* 0x000164000c1e1900 */
/*06b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06c0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*06d0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e4000c101904 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06f0*/ LDG.E R2, [R4.64+0x8] ; /* 0x0000080404027981 */
/* 0x000ea2000c1e1900 */
/*0700*/ BSSY B0, 0x800 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0710*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0720*/ @!P0 BRA 0x7f0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0740*/ BSSY B1, 0x7d0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0750*/ @P0 BRA 0x7c0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x001fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0790*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*07a0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*07b0*/ LDG.E R2, [R4.64+0x8] ; /* 0x0000080404027981 */
/* 0x000164000c1e1900 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*07e0*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0001e4000c101904 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ LDG.E R2, [R4.64+0xc] ; /* 0x00000c0404027981 */
/* 0x000ea2000c1e1900 */
/*0810*/ BSSY B0, 0x910 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0830*/ @!P0 BRA 0x900 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0850*/ BSSY B1, 0x8e0 ; /* 0x0000008000017945 */
/* 0x000fd80003800000 */
/*0860*/ @P0 BRA 0x8d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0870*/ LDG.E R8, [R6.64+0xc] ; /* 0x00000c0406087981 */
/* 0x000ea2000c1e1900 */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x001fe200078e00ff */
/*0890*/ MOV R11, 0x1 ; /* 0x00000001000b7802 */
/* 0x000fc60000000f00 */
/*08a0*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x004fca00078e0009 */
/*08b0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e8000c101904 */
/*08c0*/ LDG.E R2, [R4.64+0xc] ; /* 0x00000c0404027981 */
/* 0x000164000c1e1900 */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R9, R2, -0x1, RZ ; /* 0xffffffff02097810 */
/* 0x021fca0007ffe0ff */
/*08f0*/ STG.E [R4.64+0xc], R9 ; /* 0x00000c0904007986 */
/* 0x0001e4000c101904 */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x001fe40007f3e0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fe40003f06070 */
/*0940*/ IADD3 R8, P2, R6, 0x10, RZ ; /* 0x0000001006087810 */
/* 0x000fe20007f5e0ff */
/*0950*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0605 */
/*0960*/ IMAD.X R9, RZ, RZ, R7, P2 ; /* 0x000000ffff097224 */
/* 0x000fcc00010e0607 */
/*0970*/ @!P0 BRA 0x4b0 ; /* 0xfffffb3000008947 */
/* 0x000fea000383ffff */
/*0980*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0990*/ BRA 0x990; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.globl _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.p2align 8
.type _Z28breadth_first_search_csr_gpuPjS_PiS_S_j,@function
_Z28breadth_first_search_csr_gpuPjS_PiS_S_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_13
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v1, 1, v1
v_mov_b32_e32 v7, 1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[5:6], v7, off
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v6, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v0, v8
v_add_co_u32 v3, s0, v3, 4
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_13
.LBB0_5:
global_load_b32 v5, v[1:2], off
s_mov_b32 s0, 0
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v5
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_9
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 1, v5
s_cbranch_execz .LBB0_8
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_store_b32 v[9:10], v7, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s4, s4
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s5
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_4
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, -1, v5
global_store_b32 v[1:2], v5, off
s_branch .LBB0_4
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, .Lfunc_end0-_Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28breadth_first_search_csr_gpuPjS_PiS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000646c9_00000000-6_breadth_first_search_csr_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j
.type _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j, @function
_Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28breadth_first_search_csr_gpuPjS_PiS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j, .-_Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j
.globl _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.type _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, @function
_Z28breadth_first_search_csr_gpuPjS_PiS_S_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z28breadth_first_search_csr_gpuPjS_PiS_S_jPjS_PiS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, .-_Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28breadth_first_search_csr_gpuPjS_PiS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28breadth_first_search_csr_gpuPjS_PiS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "breadth_first_search_csr_gpu.hip"
.globl _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j # -- Begin function _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.p2align 4, 0x90
.type _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j,@function
_Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j: # @_Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28breadth_first_search_csr_gpuPjS_PiS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j, .Lfunc_end0-_Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28breadth_first_search_csr_gpuPjS_PiS_S_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28breadth_first_search_csr_gpuPjS_PiS_S_j,@object # @_Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.section .rodata,"a",@progbits
.globl _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.p2align 3, 0x0
_Z28breadth_first_search_csr_gpuPjS_PiS_S_j:
.quad _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.size _Z28breadth_first_search_csr_gpuPjS_PiS_S_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28breadth_first_search_csr_gpuPjS_PiS_S_j"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__breadth_first_search_csr_gpuPjS_PiS_S_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28breadth_first_search_csr_gpuPjS_PiS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#define FLOAT_N 3214212.01
void init_arrays(double* data, int M, int N)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
/* Determine mean of column vectors of input data matrix */
__global__ void calcmean(double* d_data, double* d_mean, int M, int N)
{
int i;
int j = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j<=(M+1)) {
d_mean[j] = 0.0;
for (i = 1; i < (N+1); i++) {
d_mean[j] += d_data[i*(M+1) + j];
}
d_mean[j] /= FLOAT_N;
}
}
/* Center the column vectors. */
__global__ void calcdata(double* d_data, double* d_mean, int M, int N)
{
int j;
int i = blockDim.x * blockIdx.x + threadIdx.x+1;
if (i<=(N+1)) {
for (j = 1; j < (M+1); j++) {
d_data[i*(M+1) + j] -= d_mean[j];
}
}
}
/* Calculate the m * m covariance matrix. */
__global__ void calcsymmat(double* d_data, double* d_symmat, int M, int N)
{
int i, j2;
int j1 = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j1<=(M+1)) {
for (j2 = j1; j2 < (M+1); j2++) {
d_symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < N+1; i++) {
d_symmat[j1*(M+1) + j2] += d_data[i*(M+1) + j1] * d_data[i*(M+1) + j2];
}
d_symmat[j2*(M+1) + j1] = d_symmat[j1*(M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data;
double *symmat;
double *mean;
cudaEvent_t start, stop;
float elapsedTime;
int i, j;
FILE *output1;
output1 = fopen("covgpu.out", "w");
cudaError_t err = cudaSuccess;
int M = atoi(argv[1]), N = atoi(argv[2]);
int sizedata = (M+1)*(N+1)*sizeof(double);
int sizesymmat = (M+1)*(M+1)*sizeof(double);
int sizemean = (M+1)*sizeof(double);
data = (double*)malloc(sizedata);
symmat = (double*)malloc(sizesymmat);
mean = (double*)malloc(sizemean);
int threadsPerBlock = 128;
int threadsPerBlock2 = 128;
int threadsPerBlock3 = 128;
int blocksPerGrid;
int blocksPerGrid2;
int blocksPerGrid3;
if (M%threadsPerBlock != 0){
blocksPerGrid = M/128+1;
}else {
blocksPerGrid=M/128+1;
}
if (N%threadsPerBlock2 != 0){
blocksPerGrid2 = N/128+1;
}else {
blocksPerGrid2=N/128+1;
}
if (M%threadsPerBlock3 != 0){
blocksPerGrid3 = M/128+1;
}
else {
blocksPerGrid3=M/128+1;
}
printf("blocksPerGrid %d\n", blocksPerGrid);
printf("blocksPerGrid2 %d\n", blocksPerGrid2);
printf("blocksPerGrid3 %d\n", blocksPerGrid3);
//Matrix data
double *d_data = NULL;
err = cudaMalloc((void **)&d_data, sizedata);
if (err != cudaSuccess){
fprintf(stderr, "Failed to allocate device matrix DATA (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Matrix symmat
double *d_symmat = NULL;
err = cudaMalloc((void **)&d_symmat, sizesymmat);
if (err != cudaSuccess){
fprintf(stderr, "Failed to allocate device vector SYMMAT (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Vector mean
double *d_mean = NULL;
err = cudaMalloc((void **)&d_mean, sizemean);
if (err != cudaSuccess){
fprintf(stderr, "Failed to allocate device vector MEAN (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
init_arrays(data, M, N);
err = cudaMemcpy(d_data, data, sizedata, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
fprintf(stderr, "Failed to copy matrix DATA from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
calcmean<<<blocksPerGrid, threadsPerBlock>>>(d_data, d_mean, M, N);
calcdata<<<blocksPerGrid2, threadsPerBlock2>>>(d_data, d_mean, M, N);
calcsymmat<<<blocksPerGrid3, threadsPerBlock3>>>(d_data, d_symmat, M, N);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
printf("Elapsed time : %f s\n" ,elapsedTime/1000);
/*Return results*/
err = cudaMemcpy(symmat, d_symmat, sizesymmat, cudaMemcpyDeviceToHost);
if (err != cudaSuccess){
fprintf(stderr, "Failed to return results from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Print results to file*/
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
fprintf(output1, "%f ", symmat[i*(M+1)+j]);
}
fprintf(output1, "\n");
}
free(data);
free(symmat);
free(mean);
fclose(output1);
return 0;
} | .file "tmpxft_00144681_00000000-6_cov.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_arraysPdii
.type _Z11init_arraysPdii, @function
_Z11init_arraysPdii:
.LFB2070:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movl %esi, %r9d
leal 1(%rdx), %r11d
leal 1(%rsi), %ebx
movl %r11d, %r8d
movl $1, %edi
leal 1(%rdx), %esi
jmp .L5
.L7:
movslq %r8d, %rax
leaq (%r10,%rax,8), %rcx
movl $1, %eax
pxor %xmm2, %xmm2
cvtsi2sdl %edi, %xmm2
pxor %xmm1, %xmm1
cvtsi2sdl %r9d, %xmm1
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rcx,%rax,8)
addq $1, %rax
cmpq %rsi, %rax
jne .L6
.L8:
addl $1, %edi
addl %r11d, %r8d
cmpl %ebx, %edi
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
ret
.cfi_endproc
.LFE2070:
.size _Z11init_arraysPdii, .-_Z11init_arraysPdii
.globl _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
.type _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii, @function
_Z31__device_stub__Z8calcmeanPdS_iiPdS_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8calcmeanPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii, .-_Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
.globl _Z8calcmeanPdS_ii
.type _Z8calcmeanPdS_ii, @function
_Z8calcmeanPdS_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8calcmeanPdS_ii, .-_Z8calcmeanPdS_ii
.globl _Z31__device_stub__Z8calcdataPdS_iiPdS_ii
.type _Z31__device_stub__Z8calcdataPdS_iiPdS_ii, @function
_Z31__device_stub__Z8calcdataPdS_iiPdS_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8calcdataPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z31__device_stub__Z8calcdataPdS_iiPdS_ii, .-_Z31__device_stub__Z8calcdataPdS_iiPdS_ii
.globl _Z8calcdataPdS_ii
.type _Z8calcdataPdS_ii, @function
_Z8calcdataPdS_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8calcdataPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z8calcdataPdS_ii, .-_Z8calcdataPdS_ii
.globl _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
.type _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii, @function
_Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10calcsymmatPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii, .-_Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
.globl _Z10calcsymmatPdS_ii
.type _Z10calcsymmatPdS_ii, @function
_Z10calcsymmatPdS_ii:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z10calcsymmatPdS_ii, .-_Z10calcsymmatPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "covgpu.out"
.LC2:
.string "blocksPerGrid %d\n"
.LC3:
.string "blocksPerGrid2 %d\n"
.LC4:
.string "blocksPerGrid3 %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Failed to allocate device matrix DATA (error code %s)!\n"
.align 8
.LC6:
.string "Failed to allocate device vector SYMMAT (error code %s)!\n"
.align 8
.LC7:
.string "Failed to allocate device vector MEAN (error code %s)!\n"
.align 8
.LC8:
.string "Failed to copy matrix DATA from host to device (error code %s)!\n"
.section .rodata.str1.1
.LC10:
.string "Elapsed time : %f s\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Failed to return results from device to host (error code %s)!\n"
.section .rodata.str1.1
.LC12:
.string "%f "
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 24(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
leal 1(%r14), %r12d
movl %r12d, 28(%rsp)
leal 1(%rax), %eax
imull %r12d, %eax
sall $3, %eax
movslq %eax, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movl %r12d, %eax
imull %r12d, %eax
sall $3, %eax
movslq %eax, %rcx
movq %rcx, 8(%rsp)
movq %rcx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leal 0(,%r12,8), %eax
movslq %eax, %rcx
movq %rcx, 40(%rsp)
testb $127, %r14b
je .L39
movl $128, %ecx
movl 24(%rsp), %eax
cltd
idivl %ecx
leal 1(%rax), %r12d
.L40:
testb $127, %bl
je .L41
movl $128, %ecx
movl %r15d, %eax
cltd
idivl %ecx
leal 1(%rax), %ebx
.L42:
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 72(%rsp)
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
movq $0, 80(%rsp)
leaq 80(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L61
movq $0, 88(%rsp)
leaq 88(%rsp), %rdi
movq 40(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L62
movl %r15d, %edx
movl 24(%rsp), %esi
movq 32(%rsp), %rdi
call _Z11init_arraysPdii
movl $1, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r12d, %r13d
movl %r12d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L47:
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %ebx, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L48:
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L49:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 108(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 108(%rsp), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 80(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
testl %r14d, %r14d
jle .L51
movl 28(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, %r14d
leaq .LC12(%rip), %r13
jmp .L52
.L39:
movl $128, %ecx
movl 24(%rsp), %eax
cltd
idivl %ecx
leal 1(%rax), %r12d
jmp .L40
.L41:
movl $128, %ecx
movl %r15d, %eax
cltd
idivl %ecx
leal 1(%rax), %ebx
jmp .L42
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %r15d, %ecx
movl 24(%rsp), %edx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
jmp .L47
.L65:
movl %r15d, %ecx
movl 24(%rsp), %edx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z31__device_stub__Z8calcdataPdS_iiPdS_ii
jmp .L48
.L66:
movl %r15d, %ecx
movl 24(%rsp), %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
jmp .L49
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movslq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,8), %r12
movl $1, %ebx
.L53:
movsd (%r12,%rbx,8), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, %r15d
jge .L53
.L55:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r14d
movl 28(%rsp), %ecx
addl %ecx, 8(%rsp)
movl 24(%rsp), %eax
cmpl %eax, %r14d
jg .L51
.L52:
testl %r15d, %r15d
jg .L54
jmp .L55
.L51:
movq 32(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call fclose@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10calcsymmatPdS_ii"
.LC15:
.string "_Z8calcdataPdS_ii"
.LC16:
.string "_Z8calcmeanPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calcsymmatPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8calcdataPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8calcmeanPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#define FLOAT_N 3214212.01
void init_arrays(double* data, int M, int N)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
/* Determine mean of column vectors of input data matrix */
__global__ void calcmean(double* d_data, double* d_mean, int M, int N)
{
int i;
int j = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j<=(M+1)) {
d_mean[j] = 0.0;
for (i = 1; i < (N+1); i++) {
d_mean[j] += d_data[i*(M+1) + j];
}
d_mean[j] /= FLOAT_N;
}
}
/* Center the column vectors. */
__global__ void calcdata(double* d_data, double* d_mean, int M, int N)
{
int j;
int i = blockDim.x * blockIdx.x + threadIdx.x+1;
if (i<=(N+1)) {
for (j = 1; j < (M+1); j++) {
d_data[i*(M+1) + j] -= d_mean[j];
}
}
}
/* Calculate the m * m covariance matrix. */
__global__ void calcsymmat(double* d_data, double* d_symmat, int M, int N)
{
int i, j2;
int j1 = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j1<=(M+1)) {
for (j2 = j1; j2 < (M+1); j2++) {
d_symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < N+1; i++) {
d_symmat[j1*(M+1) + j2] += d_data[i*(M+1) + j1] * d_data[i*(M+1) + j2];
}
d_symmat[j2*(M+1) + j1] = d_symmat[j1*(M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data;
double *symmat;
double *mean;
cudaEvent_t start, stop;
float elapsedTime;
int i, j;
FILE *output1;
output1 = fopen("covgpu.out", "w");
cudaError_t err = cudaSuccess;
int M = atoi(argv[1]), N = atoi(argv[2]);
int sizedata = (M+1)*(N+1)*sizeof(double);
int sizesymmat = (M+1)*(M+1)*sizeof(double);
int sizemean = (M+1)*sizeof(double);
data = (double*)malloc(sizedata);
symmat = (double*)malloc(sizesymmat);
mean = (double*)malloc(sizemean);
int threadsPerBlock = 128;
int threadsPerBlock2 = 128;
int threadsPerBlock3 = 128;
int blocksPerGrid;
int blocksPerGrid2;
int blocksPerGrid3;
if (M%threadsPerBlock != 0){
blocksPerGrid = M/128+1;
}else {
blocksPerGrid=M/128+1;
}
if (N%threadsPerBlock2 != 0){
blocksPerGrid2 = N/128+1;
}else {
blocksPerGrid2=N/128+1;
}
if (M%threadsPerBlock3 != 0){
blocksPerGrid3 = M/128+1;
}
else {
blocksPerGrid3=M/128+1;
}
printf("blocksPerGrid %d\n", blocksPerGrid);
printf("blocksPerGrid2 %d\n", blocksPerGrid2);
printf("blocksPerGrid3 %d\n", blocksPerGrid3);
//Matrix data
double *d_data = NULL;
err = cudaMalloc((void **)&d_data, sizedata);
if (err != cudaSuccess){
fprintf(stderr, "Failed to allocate device matrix DATA (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Matrix symmat
double *d_symmat = NULL;
err = cudaMalloc((void **)&d_symmat, sizesymmat);
if (err != cudaSuccess){
fprintf(stderr, "Failed to allocate device vector SYMMAT (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Vector mean
double *d_mean = NULL;
err = cudaMalloc((void **)&d_mean, sizemean);
if (err != cudaSuccess){
fprintf(stderr, "Failed to allocate device vector MEAN (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
init_arrays(data, M, N);
err = cudaMemcpy(d_data, data, sizedata, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
fprintf(stderr, "Failed to copy matrix DATA from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
calcmean<<<blocksPerGrid, threadsPerBlock>>>(d_data, d_mean, M, N);
calcdata<<<blocksPerGrid2, threadsPerBlock2>>>(d_data, d_mean, M, N);
calcsymmat<<<blocksPerGrid3, threadsPerBlock3>>>(d_data, d_symmat, M, N);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start,stop);
printf("Elapsed time : %f s\n" ,elapsedTime/1000);
/*Return results*/
err = cudaMemcpy(symmat, d_symmat, sizesymmat, cudaMemcpyDeviceToHost);
if (err != cudaSuccess){
fprintf(stderr, "Failed to return results from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Print results to file*/
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
fprintf(output1, "%f ", symmat[i*(M+1)+j]);
}
fprintf(output1, "\n");
}
free(data);
free(symmat);
free(mean);
fclose(output1);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define FLOAT_N 3214212.01
void init_arrays(double* data, int M, int N)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
/* Determine mean of column vectors of input data matrix */
__global__ void calcmean(double* d_data, double* d_mean, int M, int N)
{
int i;
int j = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j<=(M+1)) {
d_mean[j] = 0.0;
for (i = 1; i < (N+1); i++) {
d_mean[j] += d_data[i*(M+1) + j];
}
d_mean[j] /= FLOAT_N;
}
}
/* Center the column vectors. */
__global__ void calcdata(double* d_data, double* d_mean, int M, int N)
{
int j;
int i = blockDim.x * blockIdx.x + threadIdx.x+1;
if (i<=(N+1)) {
for (j = 1; j < (M+1); j++) {
d_data[i*(M+1) + j] -= d_mean[j];
}
}
}
/* Calculate the m * m covariance matrix. */
__global__ void calcsymmat(double* d_data, double* d_symmat, int M, int N)
{
int i, j2;
int j1 = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j1<=(M+1)) {
for (j2 = j1; j2 < (M+1); j2++) {
d_symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < N+1; i++) {
d_symmat[j1*(M+1) + j2] += d_data[i*(M+1) + j1] * d_data[i*(M+1) + j2];
}
d_symmat[j2*(M+1) + j1] = d_symmat[j1*(M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data;
double *symmat;
double *mean;
hipEvent_t start, stop;
float elapsedTime;
int i, j;
FILE *output1;
output1 = fopen("covgpu.out", "w");
hipError_t err = hipSuccess;
int M = atoi(argv[1]), N = atoi(argv[2]);
int sizedata = (M+1)*(N+1)*sizeof(double);
int sizesymmat = (M+1)*(M+1)*sizeof(double);
int sizemean = (M+1)*sizeof(double);
data = (double*)malloc(sizedata);
symmat = (double*)malloc(sizesymmat);
mean = (double*)malloc(sizemean);
int threadsPerBlock = 128;
int threadsPerBlock2 = 128;
int threadsPerBlock3 = 128;
int blocksPerGrid;
int blocksPerGrid2;
int blocksPerGrid3;
if (M%threadsPerBlock != 0){
blocksPerGrid = M/128+1;
}else {
blocksPerGrid=M/128+1;
}
if (N%threadsPerBlock2 != 0){
blocksPerGrid2 = N/128+1;
}else {
blocksPerGrid2=N/128+1;
}
if (M%threadsPerBlock3 != 0){
blocksPerGrid3 = M/128+1;
}
else {
blocksPerGrid3=M/128+1;
}
printf("blocksPerGrid %d\n", blocksPerGrid);
printf("blocksPerGrid2 %d\n", blocksPerGrid2);
printf("blocksPerGrid3 %d\n", blocksPerGrid3);
//Matrix data
double *d_data = NULL;
err = hipMalloc((void **)&d_data, sizedata);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device matrix DATA (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Matrix symmat
double *d_symmat = NULL;
err = hipMalloc((void **)&d_symmat, sizesymmat);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device vector SYMMAT (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Vector mean
double *d_mean = NULL;
err = hipMalloc((void **)&d_mean, sizemean);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device vector MEAN (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
init_arrays(data, M, N);
err = hipMemcpy(d_data, data, sizedata, hipMemcpyHostToDevice);
if (err != hipSuccess){
fprintf(stderr, "Failed to copy matrix DATA from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
calcmean<<<blocksPerGrid, threadsPerBlock>>>(d_data, d_mean, M, N);
calcdata<<<blocksPerGrid2, threadsPerBlock2>>>(d_data, d_mean, M, N);
calcsymmat<<<blocksPerGrid3, threadsPerBlock3>>>(d_data, d_symmat, M, N);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
printf("Elapsed time : %f s\n" ,elapsedTime/1000);
/*Return results*/
err = hipMemcpy(symmat, d_symmat, sizesymmat, hipMemcpyDeviceToHost);
if (err != hipSuccess){
fprintf(stderr, "Failed to return results from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Print results to file*/
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
fprintf(output1, "%f ", symmat[i*(M+1)+j]);
}
fprintf(output1, "\n");
}
free(data);
free(symmat);
free(mean);
fclose(output1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define FLOAT_N 3214212.01
void init_arrays(double* data, int M, int N)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
/* Determine mean of column vectors of input data matrix */
__global__ void calcmean(double* d_data, double* d_mean, int M, int N)
{
int i;
int j = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j<=(M+1)) {
d_mean[j] = 0.0;
for (i = 1; i < (N+1); i++) {
d_mean[j] += d_data[i*(M+1) + j];
}
d_mean[j] /= FLOAT_N;
}
}
/* Center the column vectors. */
__global__ void calcdata(double* d_data, double* d_mean, int M, int N)
{
int j;
int i = blockDim.x * blockIdx.x + threadIdx.x+1;
if (i<=(N+1)) {
for (j = 1; j < (M+1); j++) {
d_data[i*(M+1) + j] -= d_mean[j];
}
}
}
/* Calculate the m * m covariance matrix. */
__global__ void calcsymmat(double* d_data, double* d_symmat, int M, int N)
{
int i, j2;
int j1 = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j1<=(M+1)) {
for (j2 = j1; j2 < (M+1); j2++) {
d_symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < N+1; i++) {
d_symmat[j1*(M+1) + j2] += d_data[i*(M+1) + j1] * d_data[i*(M+1) + j2];
}
d_symmat[j2*(M+1) + j1] = d_symmat[j1*(M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data;
double *symmat;
double *mean;
hipEvent_t start, stop;
float elapsedTime;
int i, j;
FILE *output1;
output1 = fopen("covgpu.out", "w");
hipError_t err = hipSuccess;
int M = atoi(argv[1]), N = atoi(argv[2]);
int sizedata = (M+1)*(N+1)*sizeof(double);
int sizesymmat = (M+1)*(M+1)*sizeof(double);
int sizemean = (M+1)*sizeof(double);
data = (double*)malloc(sizedata);
symmat = (double*)malloc(sizesymmat);
mean = (double*)malloc(sizemean);
int threadsPerBlock = 128;
int threadsPerBlock2 = 128;
int threadsPerBlock3 = 128;
int blocksPerGrid;
int blocksPerGrid2;
int blocksPerGrid3;
if (M%threadsPerBlock != 0){
blocksPerGrid = M/128+1;
}else {
blocksPerGrid=M/128+1;
}
if (N%threadsPerBlock2 != 0){
blocksPerGrid2 = N/128+1;
}else {
blocksPerGrid2=N/128+1;
}
if (M%threadsPerBlock3 != 0){
blocksPerGrid3 = M/128+1;
}
else {
blocksPerGrid3=M/128+1;
}
printf("blocksPerGrid %d\n", blocksPerGrid);
printf("blocksPerGrid2 %d\n", blocksPerGrid2);
printf("blocksPerGrid3 %d\n", blocksPerGrid3);
//Matrix data
double *d_data = NULL;
err = hipMalloc((void **)&d_data, sizedata);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device matrix DATA (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Matrix symmat
double *d_symmat = NULL;
err = hipMalloc((void **)&d_symmat, sizesymmat);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device vector SYMMAT (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Vector mean
double *d_mean = NULL;
err = hipMalloc((void **)&d_mean, sizemean);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device vector MEAN (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
init_arrays(data, M, N);
err = hipMemcpy(d_data, data, sizedata, hipMemcpyHostToDevice);
if (err != hipSuccess){
fprintf(stderr, "Failed to copy matrix DATA from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
calcmean<<<blocksPerGrid, threadsPerBlock>>>(d_data, d_mean, M, N);
calcdata<<<blocksPerGrid2, threadsPerBlock2>>>(d_data, d_mean, M, N);
calcsymmat<<<blocksPerGrid3, threadsPerBlock3>>>(d_data, d_symmat, M, N);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
printf("Elapsed time : %f s\n" ,elapsedTime/1000);
/*Return results*/
err = hipMemcpy(symmat, d_symmat, sizesymmat, hipMemcpyDeviceToHost);
if (err != hipSuccess){
fprintf(stderr, "Failed to return results from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Print results to file*/
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
fprintf(output1, "%f ", symmat[i*(M+1)+j]);
}
fprintf(output1, "\n");
}
free(data);
free(symmat);
free(mean);
fclose(output1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8calcmeanPdS_ii
.globl _Z8calcmeanPdS_ii
.p2align 8
.type _Z8calcmeanPdS_ii,@function
_Z8calcmeanPdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s5, s15, s2
s_add_i32 s2, s4, 1
v_add3_u32 v1, v0, s5, 1
v_cmpx_ge_i32_e64 s2, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x14
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_mov_b32_e32 v4, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_cmp_lt_i32 s3, 1
global_store_b64 v[1:2], v[3:4], off
s_cbranch_scc1 .LBB0_4
global_load_b64 v[3:4], v[1:2], off
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v5, s5, v0, 2
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[5:6]
v_add_nc_u32_e32 v5, s2, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_add_f64 v[3:4], v[6:7], v[3:4]
global_store_b64 v[1:2], v[3:4], off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
global_load_b64 v[3:4], v[1:2], off
s_mov_b32 s1, 0x414885c2
s_mov_b32 s0, 0x147ae14
s_waitcnt vmcnt(0)
v_div_scale_f64 v[5:6], null, s[0:1], s[0:1], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_div_scale_f64 v[9:10], vcc_lo, v[3:4], s[0:1], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[9:10], v[7:8]
v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
v_div_fixup_f64 v[3:4], v[5:6], s[0:1], v[3:4]
global_store_b64 v[1:2], v[3:4], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8calcmeanPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8calcmeanPdS_ii, .Lfunc_end0-_Z8calcmeanPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8calcdataPdS_ii
.globl _Z8calcdataPdS_ii
.p2align 8
.type _Z8calcdataPdS_ii,@function
_Z8calcdataPdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_add_i32 s2, s5, 1
v_add3_u32 v0, v0, s15, 1
s_cmp_gt_i32 s4, 0
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v1, v0, s4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v0, v1, v0, 1
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s4, s4, -1
v_lshlrev_b64 v[3:4], 3, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_load_b64 v[5:6], v2, s[2:3]
global_load_b64 v[7:8], v[3:4], off
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[7:8], -v[5:6]
global_store_b64 v[3:4], v[5:6], off
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8calcdataPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8calcdataPdS_ii, .Lfunc_end1-_Z8calcdataPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10calcsymmatPdS_ii
.globl _Z10calcsymmatPdS_ii
.p2align 8
.type _Z10calcsymmatPdS_ii,@function
_Z10calcsymmatPdS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s9, s15, s3
s_add_i32 s3, s2, 1
v_add3_u32 v1, v0, s9, 1
s_min_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB2_6
s_clause 0x1
s_load_b32 s8, s[0:1], 0x14
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v10, v1, s3
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v11, v1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s8, 0
s_cselect_b32 s1, -1, 0
s_add_i32 s9, s9, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v0, s9, v0, 2
s_mov_b32 s9, 0
s_branch .LBB2_3
.LBB2_2:
global_load_b64 v[3:4], v[4:5], off
v_mad_u64_u32 v[5:6], null, v11, s3, v[1:2]
v_add_nc_u32_e32 v7, 1, v11
v_cmp_le_i32_e32 vcc_lo, s2, v11
s_add_i32 s10, s10, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v11, v7
v_ashrrev_i32_e32 v6, 31, v5
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB2_6
.LBB2_3:
v_add_nc_u32_e32 v3, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[4:5], 3, v[3:4]
v_mov_b32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s1
global_store_b64 v[4:5], v[2:3], off
s_cbranch_vccnz .LBB2_2
global_load_b64 v[6:7], v[4:5], off
v_mov_b32_e32 v8, v0
s_mov_b32 s0, s8
.p2align 6
.LBB2_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v12, s10, v8
v_ashrrev_i32_e32 v9, 31, v8
s_add_i32 s0, s0, -1
s_cmp_lg_u32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[14:15], 3, v[8:9]
v_add_nc_u32_e32 v8, s3, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
s_clause 0x1
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(0)
v_fma_f64 v[6:7], v[14:15], v[12:13], v[6:7]
global_store_b64 v[4:5], v[6:7], off
s_cbranch_scc1 .LBB2_5
s_branch .LBB2_2
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10calcsymmatPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10calcsymmatPdS_ii, .Lfunc_end2-_Z10calcsymmatPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8calcmeanPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8calcmeanPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8calcdataPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8calcdataPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10calcsymmatPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10calcsymmatPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <unistd.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define FLOAT_N 3214212.01
void init_arrays(double* data, int M, int N)
{
int i, j;
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
data[i*(N+1) + j] = ((double) i*j) / M;
}
}
}
/* Determine mean of column vectors of input data matrix */
__global__ void calcmean(double* d_data, double* d_mean, int M, int N)
{
int i;
int j = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j<=(M+1)) {
d_mean[j] = 0.0;
for (i = 1; i < (N+1); i++) {
d_mean[j] += d_data[i*(M+1) + j];
}
d_mean[j] /= FLOAT_N;
}
}
/* Center the column vectors. */
__global__ void calcdata(double* d_data, double* d_mean, int M, int N)
{
int j;
int i = blockDim.x * blockIdx.x + threadIdx.x+1;
if (i<=(N+1)) {
for (j = 1; j < (M+1); j++) {
d_data[i*(M+1) + j] -= d_mean[j];
}
}
}
/* Calculate the m * m covariance matrix. */
__global__ void calcsymmat(double* d_data, double* d_symmat, int M, int N)
{
int i, j2;
int j1 = blockDim.x * blockIdx.x + threadIdx.x+1;
if (j1<=(M+1)) {
for (j2 = j1; j2 < (M+1); j2++) {
d_symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < N+1; i++) {
d_symmat[j1*(M+1) + j2] += d_data[i*(M+1) + j1] * d_data[i*(M+1) + j2];
}
d_symmat[j2*(M+1) + j1] = d_symmat[j1*(M+1) + j2];
}
}
}
int main(int argc, char *argv[])
{
double *data;
double *symmat;
double *mean;
hipEvent_t start, stop;
float elapsedTime;
int i, j;
FILE *output1;
output1 = fopen("covgpu.out", "w");
hipError_t err = hipSuccess;
int M = atoi(argv[1]), N = atoi(argv[2]);
int sizedata = (M+1)*(N+1)*sizeof(double);
int sizesymmat = (M+1)*(M+1)*sizeof(double);
int sizemean = (M+1)*sizeof(double);
data = (double*)malloc(sizedata);
symmat = (double*)malloc(sizesymmat);
mean = (double*)malloc(sizemean);
int threadsPerBlock = 128;
int threadsPerBlock2 = 128;
int threadsPerBlock3 = 128;
int blocksPerGrid;
int blocksPerGrid2;
int blocksPerGrid3;
if (M%threadsPerBlock != 0){
blocksPerGrid = M/128+1;
}else {
blocksPerGrid=M/128+1;
}
if (N%threadsPerBlock2 != 0){
blocksPerGrid2 = N/128+1;
}else {
blocksPerGrid2=N/128+1;
}
if (M%threadsPerBlock3 != 0){
blocksPerGrid3 = M/128+1;
}
else {
blocksPerGrid3=M/128+1;
}
printf("blocksPerGrid %d\n", blocksPerGrid);
printf("blocksPerGrid2 %d\n", blocksPerGrid2);
printf("blocksPerGrid3 %d\n", blocksPerGrid3);
//Matrix data
double *d_data = NULL;
err = hipMalloc((void **)&d_data, sizedata);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device matrix DATA (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Matrix symmat
double *d_symmat = NULL;
err = hipMalloc((void **)&d_symmat, sizesymmat);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device vector SYMMAT (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Vector mean
double *d_mean = NULL;
err = hipMalloc((void **)&d_mean, sizemean);
if (err != hipSuccess){
fprintf(stderr, "Failed to allocate device vector MEAN (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
init_arrays(data, M, N);
err = hipMemcpy(d_data, data, sizedata, hipMemcpyHostToDevice);
if (err != hipSuccess){
fprintf(stderr, "Failed to copy matrix DATA from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
calcmean<<<blocksPerGrid, threadsPerBlock>>>(d_data, d_mean, M, N);
calcdata<<<blocksPerGrid2, threadsPerBlock2>>>(d_data, d_mean, M, N);
calcsymmat<<<blocksPerGrid3, threadsPerBlock3>>>(d_data, d_symmat, M, N);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start,stop);
printf("Elapsed time : %f s\n" ,elapsedTime/1000);
/*Return results*/
err = hipMemcpy(symmat, d_symmat, sizesymmat, hipMemcpyDeviceToHost);
if (err != hipSuccess){
fprintf(stderr, "Failed to return results from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Print results to file*/
for (i = 1; i < (M+1); i++) {
for (j = 1; j < (N+1); j++) {
fprintf(output1, "%f ", symmat[i*(M+1)+j]);
}
fprintf(output1, "\n");
}
free(data);
free(symmat);
free(mean);
fclose(output1);
return 0;
} | .text
.file "cov.hip"
.globl _Z11init_arraysPdii # -- Begin function _Z11init_arraysPdii
.p2align 4, 0x90
.type _Z11init_arraysPdii,@function
_Z11init_arraysPdii: # @_Z11init_arraysPdii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
cvtsi2sd %esi, %xmm0
leal 1(%rdx), %eax
incl %esi
movl $1, %ecx
movl %eax, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rcx
addl %eax, %r8d
cmpq %rsi, %rcx
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r9d
leaq (%rdi,%r9,8), %r9
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movl $1, %r10d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %r10d, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%r9,%r10,8)
incq %r10
cmpq %r10, %rax
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge19
retq
.Lfunc_end0:
.size _Z11init_arraysPdii, .Lfunc_end0-_Z11init_arraysPdii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__calcmeanPdS_ii # -- Begin function _Z23__device_stub__calcmeanPdS_ii
.p2align 4, 0x90
.type _Z23__device_stub__calcmeanPdS_ii,@function
_Z23__device_stub__calcmeanPdS_ii: # @_Z23__device_stub__calcmeanPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8calcmeanPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__calcmeanPdS_ii, .Lfunc_end1-_Z23__device_stub__calcmeanPdS_ii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__calcdataPdS_ii # -- Begin function _Z23__device_stub__calcdataPdS_ii
.p2align 4, 0x90
.type _Z23__device_stub__calcdataPdS_ii,@function
_Z23__device_stub__calcdataPdS_ii: # @_Z23__device_stub__calcdataPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8calcdataPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__calcdataPdS_ii, .Lfunc_end2-_Z23__device_stub__calcdataPdS_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__calcsymmatPdS_ii # -- Begin function _Z25__device_stub__calcsymmatPdS_ii
.p2align 4, 0x90
.type _Z25__device_stub__calcsymmatPdS_ii,@function
_Z25__device_stub__calcsymmatPdS_ii: # @_Z25__device_stub__calcsymmatPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10calcsymmatPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__calcsymmatPdS_ii, .Lfunc_end3-_Z25__device_stub__calcsymmatPdS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leal 1(%r13), %ecx
leal 1(%rax), %ebp
leal 8(,%r13,8), %r12d
movl %r12d, %eax
imull %ebp, %eax
movl %r12d, %r14d
movl %ecx, 28(%rsp) # 4-byte Spill
imull %ecx, %r14d
movslq %eax, %rdi
movq %rdi, 216(%rsp) # 8-byte Spill
callq malloc
movq %rax, 192(%rsp) # 8-byte Spill
movslq %r14d, %rax
movq %r13, %r14
movq %rax, %r13
movq %rax, %rdi
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
movq %r14, 8(%rsp) # 8-byte Spill
testb $127, %r14b
je .LBB4_2
# %bb.1:
movq 8(%rsp), %rax # 8-byte Reload
leal 127(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
jmp .LBB4_3
.LBB4_2:
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %esi
.LBB4_3:
sarl $7, %esi
testb $127, %r15b
je .LBB4_5
# %bb.4:
leal 127(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
jmp .LBB4_6
.LBB4_5:
movl %r15d, %eax
.LBB4_6:
sarl $7, %eax
incl %esi
incl %eax
testb $127, 8(%rsp) # 1-byte Folded Reload
movl %eax, 104(%rsp) # 4-byte Spill
je .LBB4_8
# %bb.7:
movq 8(%rsp), %rax # 8-byte Reload
leal 127(%rax), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
jmp .LBB4_9
.LBB4_8:
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
.LBB4_9:
sarl $7, %r14d
incl %r14d
movl $.L.str.2, %edi
movl %esi, 184(%rsp) # 4-byte Spill
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl 104(%rsp), %esi # 4-byte Reload
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r14d, 188(%rsp) # 4-byte Spill
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq 216(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.12:
movq $0, 168(%rsp)
leaq 168(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14:
movq %r13, 208(%rsp) # 8-byte Spill
movslq %r12d, %rsi
movq $0, 160(%rsp)
leaq 160(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16:
movl 28(%rsp), %r12d # 4-byte Reload
movl %ebp, %r13d
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movq 192(%rsp), %rsi # 8-byte Reload
jle .LBB4_22
# %bb.17: # %.preheader.lr.ph.i
cvtsi2sdl 8(%rsp), %xmm0 # 4-byte Folded Reload
movl $1, %eax
movl %ebp, %ecx
jmp .LBB4_18
.p2align 4, 0x90
.LBB4_21: # %._crit_edge.i
# in Loop: Header=BB4_18 Depth=1
incq %rax
addl %ebp, %ecx
cmpq %r12, %rax
je .LBB4_22
.LBB4_18: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_20 Depth 2
testl %r15d, %r15d
jle .LBB4_21
# %bb.19: # %.lr.ph.i
# in Loop: Header=BB4_18 Depth=1
movl %ecx, %edx
leaq (%rsi,%rdx,8), %rdx
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movl $1, %edi
.p2align 4, 0x90
.LBB4_20: # Parent Loop BB4_18 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %edi, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%rdx,%rdi,8)
incq %rdi
cmpq %rdi, %r13
jne .LBB4_20
jmp .LBB4_21
.LBB4_22: # %_Z11init_arraysPdii.exit
movq 32(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.24:
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 200(%rsp), %rdi
callq hipEventCreate
leaq 176(%rsp), %rdi
callq hipEventCreate
movq 200(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 184(%rsp), %edi # 4-byte Reload
orq %r14, %rdi
leaq 128(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 32(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl %r15d, 20(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8calcmeanPdS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movl 104(%rsp), %edi # 4-byte Reload
orq %r14, %rdi
leaq 128(%r14), %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27:
movq 32(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl %r15d, 20(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8calcdataPdS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_28:
movl 188(%rsp), %edi # 4-byte Reload
orq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_30
# %bb.29:
movq 32(%rsp), %rax
movq 168(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl %r15d, 20(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10calcsymmatPdS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_30:
movq %r15, 104(%rsp) # 8-byte Spill
movq 176(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 176(%rsp), %rdi
callq hipEventSynchronize
movq 200(%rsp), %rsi
movq 176(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 168(%rsp), %rsi
movq 152(%rsp), %rdi # 8-byte Reload
movq 208(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_38
# %bb.31: # %.preheader130
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB4_37
# %bb.32: # %.preheader.lr.ph
movl $1, %ebp
movl 28(%rsp), %r15d # 4-byte Reload
movq %r12, 224(%rsp) # 8-byte Spill
jmp .LBB4_33
.p2align 4, 0x90
.LBB4_36: # %._crit_edge
# in Loop: Header=BB4_33 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %rbp
addl 28(%rsp), %r15d # 4-byte Folded Reload
movq 224(%rsp), %r12 # 8-byte Reload
cmpq %r12, %rbp
je .LBB4_37
.LBB4_33: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_35 Depth 2
cmpl $0, 104(%rsp) # 4-byte Folded Reload
jle .LBB4_36
# %bb.34: # %.lr.ph
# in Loop: Header=BB4_33 Depth=1
movl %r15d, %eax
movq 152(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
movl $1, %r12d
.p2align 4, 0x90
.LBB4_35: # Parent Loop BB4_33 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.11, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r13
jne .LBB4_35
jmp .LBB4_36
.LBB4_37: # %._crit_edge135
movq 192(%rsp), %rdi # 8-byte Reload
callq free
movq 152(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_10:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB4_11
.LBB4_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB4_11
.LBB4_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB4_11
.LBB4_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB4_11
.LBB4_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
.LBB4_11:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8calcmeanPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8calcdataPdS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calcsymmatPdS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8calcmeanPdS_ii,@object # @_Z8calcmeanPdS_ii
.section .rodata,"a",@progbits
.globl _Z8calcmeanPdS_ii
.p2align 3, 0x0
_Z8calcmeanPdS_ii:
.quad _Z23__device_stub__calcmeanPdS_ii
.size _Z8calcmeanPdS_ii, 8
.type _Z8calcdataPdS_ii,@object # @_Z8calcdataPdS_ii
.globl _Z8calcdataPdS_ii
.p2align 3, 0x0
_Z8calcdataPdS_ii:
.quad _Z23__device_stub__calcdataPdS_ii
.size _Z8calcdataPdS_ii, 8
.type _Z10calcsymmatPdS_ii,@object # @_Z10calcsymmatPdS_ii
.globl _Z10calcsymmatPdS_ii
.p2align 3, 0x0
_Z10calcsymmatPdS_ii:
.quad _Z25__device_stub__calcsymmatPdS_ii
.size _Z10calcsymmatPdS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "covgpu.out"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "blocksPerGrid %d\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "blocksPerGrid2 %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "blocksPerGrid3 %d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device matrix DATA (error code %s)!\n"
.size .L.str.5, 56
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device vector SYMMAT (error code %s)!\n"
.size .L.str.6, 58
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device vector MEAN (error code %s)!\n"
.size .L.str.7, 56
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy matrix DATA from host to device (error code %s)!\n"
.size .L.str.8, 65
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Elapsed time : %f s\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to return results from device to host (error code %s)!\n"
.size .L.str.10, 63
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%f "
.size .L.str.11, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8calcmeanPdS_ii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8calcdataPdS_ii"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10calcsymmatPdS_ii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__calcmeanPdS_ii
.addrsig_sym _Z23__device_stub__calcdataPdS_ii
.addrsig_sym _Z25__device_stub__calcsymmatPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8calcmeanPdS_ii
.addrsig_sym _Z8calcdataPdS_ii
.addrsig_sym _Z10calcsymmatPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144681_00000000-6_cov.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_arraysPdii
.type _Z11init_arraysPdii, @function
_Z11init_arraysPdii:
.LFB2070:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movl %esi, %r9d
leal 1(%rdx), %r11d
leal 1(%rsi), %ebx
movl %r11d, %r8d
movl $1, %edi
leal 1(%rdx), %esi
jmp .L5
.L7:
movslq %r8d, %rax
leaq (%r10,%rax,8), %rcx
movl $1, %eax
pxor %xmm2, %xmm2
cvtsi2sdl %edi, %xmm2
pxor %xmm1, %xmm1
cvtsi2sdl %r9d, %xmm1
.L6:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rcx,%rax,8)
addq $1, %rax
cmpq %rsi, %rax
jne .L6
.L8:
addl $1, %edi
addl %r11d, %r8d
cmpl %ebx, %edi
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
ret
.cfi_endproc
.LFE2070:
.size _Z11init_arraysPdii, .-_Z11init_arraysPdii
.globl _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
.type _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii, @function
_Z31__device_stub__Z8calcmeanPdS_iiPdS_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8calcmeanPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii, .-_Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
.globl _Z8calcmeanPdS_ii
.type _Z8calcmeanPdS_ii, @function
_Z8calcmeanPdS_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z8calcmeanPdS_ii, .-_Z8calcmeanPdS_ii
.globl _Z31__device_stub__Z8calcdataPdS_iiPdS_ii
.type _Z31__device_stub__Z8calcdataPdS_iiPdS_ii, @function
_Z31__device_stub__Z8calcdataPdS_iiPdS_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8calcdataPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z31__device_stub__Z8calcdataPdS_iiPdS_ii, .-_Z31__device_stub__Z8calcdataPdS_iiPdS_ii
.globl _Z8calcdataPdS_ii
.type _Z8calcdataPdS_ii, @function
_Z8calcdataPdS_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8calcdataPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z8calcdataPdS_ii, .-_Z8calcdataPdS_ii
.globl _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
.type _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii, @function
_Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10calcsymmatPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii, .-_Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
.globl _Z10calcsymmatPdS_ii
.type _Z10calcsymmatPdS_ii, @function
_Z10calcsymmatPdS_ii:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z10calcsymmatPdS_ii, .-_Z10calcsymmatPdS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "covgpu.out"
.LC2:
.string "blocksPerGrid %d\n"
.LC3:
.string "blocksPerGrid2 %d\n"
.LC4:
.string "blocksPerGrid3 %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Failed to allocate device matrix DATA (error code %s)!\n"
.align 8
.LC6:
.string "Failed to allocate device vector SYMMAT (error code %s)!\n"
.align 8
.LC7:
.string "Failed to allocate device vector MEAN (error code %s)!\n"
.align 8
.LC8:
.string "Failed to copy matrix DATA from host to device (error code %s)!\n"
.section .rodata.str1.1
.LC10:
.string "Elapsed time : %f s\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Failed to return results from device to host (error code %s)!\n"
.section .rodata.str1.1
.LC12:
.string "%f "
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 24(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
leal 1(%r14), %r12d
movl %r12d, 28(%rsp)
leal 1(%rax), %eax
imull %r12d, %eax
sall $3, %eax
movslq %eax, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movl %r12d, %eax
imull %r12d, %eax
sall $3, %eax
movslq %eax, %rcx
movq %rcx, 8(%rsp)
movq %rcx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leal 0(,%r12,8), %eax
movslq %eax, %rcx
movq %rcx, 40(%rsp)
testb $127, %r14b
je .L39
movl $128, %ecx
movl 24(%rsp), %eax
cltd
idivl %ecx
leal 1(%rax), %r12d
.L40:
testb $127, %bl
je .L41
movl $128, %ecx
movl %r15d, %eax
cltd
idivl %ecx
leal 1(%rax), %ebx
.L42:
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 72(%rsp)
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
movq $0, 80(%rsp)
leaq 80(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L61
movq $0, 88(%rsp)
leaq 88(%rsp), %rdi
movq 40(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L62
movl %r15d, %edx
movl 24(%rsp), %esi
movq 32(%rsp), %rdi
call _Z11init_arraysPdii
movl $1, %ecx
movq %r13, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r12d, %r13d
movl %r12d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L47:
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %ebx, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L48:
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L49:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 108(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 108(%rsp), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 80(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
testl %r14d, %r14d
jle .L51
movl 28(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, %r14d
leaq .LC12(%rip), %r13
jmp .L52
.L39:
movl $128, %ecx
movl 24(%rsp), %eax
cltd
idivl %ecx
leal 1(%rax), %r12d
jmp .L40
.L41:
movl $128, %ecx
movl %r15d, %eax
cltd
idivl %ecx
leal 1(%rax), %ebx
jmp .L42
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %r15d, %ecx
movl 24(%rsp), %edx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z31__device_stub__Z8calcmeanPdS_iiPdS_ii
jmp .L47
.L65:
movl %r15d, %ecx
movl 24(%rsp), %edx
movq 88(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z31__device_stub__Z8calcdataPdS_iiPdS_ii
jmp .L48
.L66:
movl %r15d, %ecx
movl 24(%rsp), %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z34__device_stub__Z10calcsymmatPdS_iiPdS_ii
jmp .L49
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movslq 8(%rsp), %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,8), %r12
movl $1, %ebx
.L53:
movsd (%r12,%rbx,8), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, %r15d
jge .L53
.L55:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r14d
movl 28(%rsp), %ecx
addl %ecx, 8(%rsp)
movl 24(%rsp), %eax
cmpl %eax, %r14d
jg .L51
.L52:
testl %r15d, %r15d
jg .L54
jmp .L55
.L51:
movq 32(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call fclose@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10calcsymmatPdS_ii"
.LC15:
.string "_Z8calcdataPdS_ii"
.LC16:
.string "_Z8calcmeanPdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calcsymmatPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8calcdataPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8calcmeanPdS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cov.hip"
.globl _Z11init_arraysPdii # -- Begin function _Z11init_arraysPdii
.p2align 4, 0x90
.type _Z11init_arraysPdii,@function
_Z11init_arraysPdii: # @_Z11init_arraysPdii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
cvtsi2sd %esi, %xmm0
leal 1(%rdx), %eax
incl %esi
movl $1, %ecx
movl %eax, %r8d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %rcx
addl %eax, %r8d
cmpq %rsi, %rcx
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r8d, %r9d
leaq (%rdi,%r9,8), %r9
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movl $1, %r10d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %r10d, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%r9,%r10,8)
incq %r10
cmpq %r10, %rax
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge19
retq
.Lfunc_end0:
.size _Z11init_arraysPdii, .Lfunc_end0-_Z11init_arraysPdii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__calcmeanPdS_ii # -- Begin function _Z23__device_stub__calcmeanPdS_ii
.p2align 4, 0x90
.type _Z23__device_stub__calcmeanPdS_ii,@function
_Z23__device_stub__calcmeanPdS_ii: # @_Z23__device_stub__calcmeanPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8calcmeanPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__calcmeanPdS_ii, .Lfunc_end1-_Z23__device_stub__calcmeanPdS_ii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__calcdataPdS_ii # -- Begin function _Z23__device_stub__calcdataPdS_ii
.p2align 4, 0x90
.type _Z23__device_stub__calcdataPdS_ii,@function
_Z23__device_stub__calcdataPdS_ii: # @_Z23__device_stub__calcdataPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8calcdataPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__calcdataPdS_ii, .Lfunc_end2-_Z23__device_stub__calcdataPdS_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__calcsymmatPdS_ii # -- Begin function _Z25__device_stub__calcsymmatPdS_ii
.p2align 4, 0x90
.type _Z25__device_stub__calcsymmatPdS_ii,@function
_Z25__device_stub__calcsymmatPdS_ii: # @_Z25__device_stub__calcsymmatPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10calcsymmatPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__calcsymmatPdS_ii, .Lfunc_end3-_Z25__device_stub__calcsymmatPdS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leal 1(%r13), %ecx
leal 1(%rax), %ebp
leal 8(,%r13,8), %r12d
movl %r12d, %eax
imull %ebp, %eax
movl %r12d, %r14d
movl %ecx, 28(%rsp) # 4-byte Spill
imull %ecx, %r14d
movslq %eax, %rdi
movq %rdi, 216(%rsp) # 8-byte Spill
callq malloc
movq %rax, 192(%rsp) # 8-byte Spill
movslq %r14d, %rax
movq %r13, %r14
movq %rax, %r13
movq %rax, %rdi
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
movq %r14, 8(%rsp) # 8-byte Spill
testb $127, %r14b
je .LBB4_2
# %bb.1:
movq 8(%rsp), %rax # 8-byte Reload
leal 127(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
jmp .LBB4_3
.LBB4_2:
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %esi
.LBB4_3:
sarl $7, %esi
testb $127, %r15b
je .LBB4_5
# %bb.4:
leal 127(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
jmp .LBB4_6
.LBB4_5:
movl %r15d, %eax
.LBB4_6:
sarl $7, %eax
incl %esi
incl %eax
testb $127, 8(%rsp) # 1-byte Folded Reload
movl %eax, 104(%rsp) # 4-byte Spill
je .LBB4_8
# %bb.7:
movq 8(%rsp), %rax # 8-byte Reload
leal 127(%rax), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
jmp .LBB4_9
.LBB4_8:
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
.LBB4_9:
sarl $7, %r14d
incl %r14d
movl $.L.str.2, %edi
movl %esi, 184(%rsp) # 4-byte Spill
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl 104(%rsp), %esi # 4-byte Reload
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %r14d, 188(%rsp) # 4-byte Spill
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movq 216(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.12:
movq $0, 168(%rsp)
leaq 168(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14:
movq %r13, 208(%rsp) # 8-byte Spill
movslq %r12d, %rsi
movq $0, 160(%rsp)
leaq 160(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16:
movl 28(%rsp), %r12d # 4-byte Reload
movl %ebp, %r13d
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movq 192(%rsp), %rsi # 8-byte Reload
jle .LBB4_22
# %bb.17: # %.preheader.lr.ph.i
cvtsi2sdl 8(%rsp), %xmm0 # 4-byte Folded Reload
movl $1, %eax
movl %ebp, %ecx
jmp .LBB4_18
.p2align 4, 0x90
.LBB4_21: # %._crit_edge.i
# in Loop: Header=BB4_18 Depth=1
incq %rax
addl %ebp, %ecx
cmpq %r12, %rax
je .LBB4_22
.LBB4_18: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_20 Depth 2
testl %r15d, %r15d
jle .LBB4_21
# %bb.19: # %.lr.ph.i
# in Loop: Header=BB4_18 Depth=1
movl %ecx, %edx
leaq (%rsi,%rdx,8), %rdx
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movl $1, %edi
.p2align 4, 0x90
.LBB4_20: # Parent Loop BB4_18 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2sd %edi, %xmm2
mulsd %xmm1, %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, (%rdx,%rdi,8)
incq %rdi
cmpq %rdi, %r13
jne .LBB4_20
jmp .LBB4_21
.LBB4_22: # %_Z11init_arraysPdii.exit
movq 32(%rsp), %rdi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.24:
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 200(%rsp), %rdi
callq hipEventCreate
leaq 176(%rsp), %rdi
callq hipEventCreate
movq 200(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 184(%rsp), %edi # 4-byte Reload
orq %r14, %rdi
leaq 128(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 32(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl %r15d, 20(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8calcmeanPdS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
movl 104(%rsp), %edi # 4-byte Reload
orq %r14, %rdi
leaq 128(%r14), %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27:
movq 32(%rsp), %rax
movq 160(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl %r15d, 20(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8calcdataPdS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_28:
movl 188(%rsp), %edi # 4-byte Reload
orq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_30
# %bb.29:
movq 32(%rsp), %rax
movq 168(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 24(%rsp)
movl %r15d, 20(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10calcsymmatPdS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_30:
movq %r15, 104(%rsp) # 8-byte Spill
movq 176(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 176(%rsp), %rdi
callq hipEventSynchronize
movq 200(%rsp), %rsi
movq 176(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 168(%rsp), %rsi
movq 152(%rsp), %rdi # 8-byte Reload
movq 208(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_38
# %bb.31: # %.preheader130
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB4_37
# %bb.32: # %.preheader.lr.ph
movl $1, %ebp
movl 28(%rsp), %r15d # 4-byte Reload
movq %r12, 224(%rsp) # 8-byte Spill
jmp .LBB4_33
.p2align 4, 0x90
.LBB4_36: # %._crit_edge
# in Loop: Header=BB4_33 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %rbp
addl 28(%rsp), %r15d # 4-byte Folded Reload
movq 224(%rsp), %r12 # 8-byte Reload
cmpq %r12, %rbp
je .LBB4_37
.LBB4_33: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_35 Depth 2
cmpl $0, 104(%rsp) # 4-byte Folded Reload
jle .LBB4_36
# %bb.34: # %.lr.ph
# in Loop: Header=BB4_33 Depth=1
movl %r15d, %eax
movq 152(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
movl $1, %r12d
.p2align 4, 0x90
.LBB4_35: # Parent Loop BB4_33 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.11, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r13
jne .LBB4_35
jmp .LBB4_36
.LBB4_37: # %._crit_edge135
movq 192(%rsp), %rdi # 8-byte Reload
callq free
movq 152(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_10:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB4_11
.LBB4_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB4_11
.LBB4_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB4_11
.LBB4_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB4_11
.LBB4_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
.LBB4_11:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8calcmeanPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8calcdataPdS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calcsymmatPdS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8calcmeanPdS_ii,@object # @_Z8calcmeanPdS_ii
.section .rodata,"a",@progbits
.globl _Z8calcmeanPdS_ii
.p2align 3, 0x0
_Z8calcmeanPdS_ii:
.quad _Z23__device_stub__calcmeanPdS_ii
.size _Z8calcmeanPdS_ii, 8
.type _Z8calcdataPdS_ii,@object # @_Z8calcdataPdS_ii
.globl _Z8calcdataPdS_ii
.p2align 3, 0x0
_Z8calcdataPdS_ii:
.quad _Z23__device_stub__calcdataPdS_ii
.size _Z8calcdataPdS_ii, 8
.type _Z10calcsymmatPdS_ii,@object # @_Z10calcsymmatPdS_ii
.globl _Z10calcsymmatPdS_ii
.p2align 3, 0x0
_Z10calcsymmatPdS_ii:
.quad _Z25__device_stub__calcsymmatPdS_ii
.size _Z10calcsymmatPdS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "covgpu.out"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "blocksPerGrid %d\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "blocksPerGrid2 %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "blocksPerGrid3 %d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device matrix DATA (error code %s)!\n"
.size .L.str.5, 56
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device vector SYMMAT (error code %s)!\n"
.size .L.str.6, 58
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device vector MEAN (error code %s)!\n"
.size .L.str.7, 56
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to copy matrix DATA from host to device (error code %s)!\n"
.size .L.str.8, 65
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Elapsed time : %f s\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to return results from device to host (error code %s)!\n"
.size .L.str.10, 63
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%f "
.size .L.str.11, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8calcmeanPdS_ii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8calcdataPdS_ii"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10calcsymmatPdS_ii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__calcmeanPdS_ii
.addrsig_sym _Z23__device_stub__calcdataPdS_ii
.addrsig_sym _Z25__device_stub__calcsymmatPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8calcmeanPdS_ii
.addrsig_sym _Z8calcdataPdS_ii
.addrsig_sym _Z10calcsymmatPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
/*******************************************************
****************** Device code ************************
******************************************************/
__constant__ double d_alpha;
__global__ void axpy (const double* A, const double* B, double* C, const unsigned int num_elements) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < num_elements)
C[idx] = d_alpha*A[idx]+B[idx];
}
/*******************************************************
******************** Host code ************************
******************************************************/
#define cudaErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void h_init_value(double* mem, const unsigned int num_elements) {
for (int i=0; i<num_elements; i++)
mem[i] = (double) rand();
}
void h_test (const double* A, const double* B, const double* C, const double alpha, const unsigned int num_elements) {
bool success = true;
for (int i=0; i<num_elements; i++) {
if (alpha*A[i]+B[i] != C[i])
success = false;
}
if (success) {
printf("[TEST] Test passed\n");
} else {
printf("[TEST] Test failed\n");
}
}
int main(int argc, char** argv) {
printf("\n");
printf("=========================================================================\n");
printf("[BLAS} axpy implementation \n");
printf("=========================================================================\n");
printf("\n");
/*** Configuration ***/
unsigned int num_elements = 3e+8;
size_t size = num_elements*sizeof(double);
timeval stime, etime;
double alpha = 1.0;
if (argc == 2)
alpha = atof(argv[1]);
/*** Mem allocation ***/
double *h_A=nullptr, *h_B=nullptr, *h_C=nullptr; // host(CPU)-side variable
double *d_A=nullptr, *d_B=nullptr, *d_C=nullptr; // device(GPU)-side variable
h_A = (double*) malloc (size);
h_B = (double*) malloc (size);
h_C = (double*) malloc (size);
cudaErrChk ( cudaMalloc ((void**)&d_A, size) );
cudaErrChk ( cudaMalloc ((void**)&d_B, size) );
cudaErrChk ( cudaMalloc ((void**)&d_C, size) );
cudaErrChk ( cudaMemcpyToSymbol (d_alpha, &alpha, sizeof(double)) );
printf("[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
, num_elements, 3*(double)size/1024/1024/1024);
/*** Program init ***/
h_init_value (h_A, num_elements);
h_init_value (h_B, num_elements);
cudaErrChk ( cudaMemcpy (d_A, h_A, size, cudaMemcpyHostToDevice) );
cudaErrChk ( cudaMemcpy (d_B, h_B, size, cudaMemcpyHostToDevice) );
/*** Launch a kernel ***/
unsigned int num_threads = 1024;
unsigned int num_blocks = (num_elements + (num_threads-1))/num_threads;
printf("[kernel] <%u, %u>-size grid launched\n"
, num_blocks, num_threads);
gettimeofday(&stime, NULL);
axpy<<<num_blocks, num_threads>>>(d_A, d_B, d_C, num_elements);
cudaErrChk ( cudaDeviceSynchronize () )
cudaErrChk ( cudaGetLastError () );
gettimeofday(&etime, NULL);
printf("[kernel] Elapsed time: %.4f\n"
, ((etime.tv_sec-stime.tv_sec)+(etime.tv_usec-stime.tv_usec)*10e-6) );
/*** Test computed result ***/
cudaErrChk ( cudaMemcpy (h_C, d_C, size, cudaMemcpyDeviceToHost) );
h_test (h_A, h_B, h_C, alpha, num_elements);
/*** Finalize ***/
free (h_A);
free (h_B);
free (h_C);
cudaErrChk (cudaFree (d_A));
cudaErrChk (cudaFree (d_B));
cudaErrChk (cudaFree (d_C));
return 0;
} | code for sm_80
Function : _Z4axpyPKdS0_Pdj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DFMA R6, R2, c[0x3][0x0], R4 ; /* 0x00c0000002067a2b */
/* 0x004e0e0000000004 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
/*******************************************************
****************** Device code ************************
******************************************************/
__constant__ double d_alpha;
__global__ void axpy (const double* A, const double* B, double* C, const unsigned int num_elements) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < num_elements)
C[idx] = d_alpha*A[idx]+B[idx];
}
/*******************************************************
******************** Host code ************************
******************************************************/
#define cudaErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void h_init_value(double* mem, const unsigned int num_elements) {
for (int i=0; i<num_elements; i++)
mem[i] = (double) rand();
}
void h_test (const double* A, const double* B, const double* C, const double alpha, const unsigned int num_elements) {
bool success = true;
for (int i=0; i<num_elements; i++) {
if (alpha*A[i]+B[i] != C[i])
success = false;
}
if (success) {
printf("[TEST] Test passed\n");
} else {
printf("[TEST] Test failed\n");
}
}
int main(int argc, char** argv) {
printf("\n");
printf("=========================================================================\n");
printf("[BLAS} axpy implementation \n");
printf("=========================================================================\n");
printf("\n");
/*** Configuration ***/
unsigned int num_elements = 3e+8;
size_t size = num_elements*sizeof(double);
timeval stime, etime;
double alpha = 1.0;
if (argc == 2)
alpha = atof(argv[1]);
/*** Mem allocation ***/
double *h_A=nullptr, *h_B=nullptr, *h_C=nullptr; // host(CPU)-side variable
double *d_A=nullptr, *d_B=nullptr, *d_C=nullptr; // device(GPU)-side variable
h_A = (double*) malloc (size);
h_B = (double*) malloc (size);
h_C = (double*) malloc (size);
cudaErrChk ( cudaMalloc ((void**)&d_A, size) );
cudaErrChk ( cudaMalloc ((void**)&d_B, size) );
cudaErrChk ( cudaMalloc ((void**)&d_C, size) );
cudaErrChk ( cudaMemcpyToSymbol (d_alpha, &alpha, sizeof(double)) );
printf("[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
, num_elements, 3*(double)size/1024/1024/1024);
/*** Program init ***/
h_init_value (h_A, num_elements);
h_init_value (h_B, num_elements);
cudaErrChk ( cudaMemcpy (d_A, h_A, size, cudaMemcpyHostToDevice) );
cudaErrChk ( cudaMemcpy (d_B, h_B, size, cudaMemcpyHostToDevice) );
/*** Launch a kernel ***/
unsigned int num_threads = 1024;
unsigned int num_blocks = (num_elements + (num_threads-1))/num_threads;
printf("[kernel] <%u, %u>-size grid launched\n"
, num_blocks, num_threads);
gettimeofday(&stime, NULL);
axpy<<<num_blocks, num_threads>>>(d_A, d_B, d_C, num_elements);
cudaErrChk ( cudaDeviceSynchronize () )
cudaErrChk ( cudaGetLastError () );
gettimeofday(&etime, NULL);
printf("[kernel] Elapsed time: %.4f\n"
, ((etime.tv_sec-stime.tv_sec)+(etime.tv_usec-stime.tv_usec)*10e-6) );
/*** Test computed result ***/
cudaErrChk ( cudaMemcpy (h_C, d_C, size, cudaMemcpyDeviceToHost) );
h_test (h_A, h_B, h_C, alpha, num_elements);
/*** Finalize ***/
free (h_A);
free (h_B);
free (h_C);
cudaErrChk (cudaFree (d_A));
cudaErrChk (cudaFree (d_B));
cudaErrChk (cudaFree (d_C));
return 0;
} | .file "tmpxft_0001a633_00000000-6_axpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4147:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4147:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA assert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4141:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4141:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z12h_init_valuePdj
.type _Z12h_init_valuePdj, @function
_Z12h_init_valuePdj:
.LFB4142:
.cfi_startproc
endbr64
testl %esi, %esi
je .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %esi
leaq (%rdi,%rsi,8), %rbp
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE4142:
.size _Z12h_init_valuePdj, .-_Z12h_init_valuePdj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "[TEST] Test passed\n"
.LC2:
.string "[TEST] Test failed\n"
.text
.globl _Z6h_testPKdS0_S0_dj
.type _Z6h_testPKdS0_S0_dj, @function
_Z6h_testPKdS0_S0_dj:
.LFB4143:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %ecx, %ecx
je .L20
movl %ecx, %ecx
salq $3, %rcx
movl $0, %eax
movl $1, %r8d
movl $0, %r9d
jmp .L23
.L26:
movl %r9d, %r8d
.L21:
addq $8, %rax
cmpq %rcx, %rax
je .L29
.L23:
movapd %xmm0, %xmm1
mulsd (%rdi,%rax), %xmm1
addsd (%rsi,%rax), %xmm1
ucomisd (%rdx,%rax), %xmm1
jp .L26
je .L21
jmp .L26
.L29:
testb %r8b, %r8b
jne .L20
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4143:
.size _Z6h_testPKdS0_S0_dj, .-_Z6h_testPKdS0_S0_dj
.globl _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
.type _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj, @function
_Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj:
.LFB4169:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyPKdS0_Pdj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4169:
.size _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj, .-_Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
.globl _Z4axpyPKdS0_Pdj
.type _Z4axpyPKdS0_Pdj, @function
_Z4axpyPKdS0_Pdj:
.LFB4170:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4170:
.size _Z4axpyPKdS0_Pdj, .-_Z4axpyPKdS0_Pdj
.section .rodata.str1.1
.LC3:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "=========================================================================\n"
.section .rodata.str1.1
.LC5:
.string "[BLAS} axpy implementation \n"
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jhson989/cuda_study/main/jhBLAS/axpy/axpy.cu"
.align 8
.LC9:
.string "[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
.align 8
.LC10:
.string "[kernel] <%u, %u>-size grid launched\n"
.section .rodata.str1.1
.LC12:
.string "[kernel] Elapsed time: %.4f\n"
.text
.globl main
.type main, @function
main:
.LFB4144:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %r12
movq %r12, %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC4(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq .LC6(%rip), %rax
movq %rax, (%rsp)
cmpl $2, %ebx
je .L43
.L39:
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $2400000000, %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $83, %edx
leaq .LC7(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7d_alpha(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movsd .LC8(%rip), %xmm0
movl $300000000, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $300000000, %esi
movq %r12, %rdi
call _Z12h_init_valuePdj
movl $300000000, %esi
movq %rbp, %rdi
call _Z12h_init_valuePdj
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $94, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $95, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1024, %ecx
movl $292969, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $292969, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $106, %edx
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaGetLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $107, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC11(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $2400000000, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $114, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $300000000, %ecx
movsd (%rsp), %xmm0
movq %r14, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z6h_testPKdS0_S0_dj
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $122, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $123, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $124, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 8(%rbp), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
jmp .L39
.L44:
movl $300000000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4144:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z4axpyPKdS0_Pdj"
.LC14:
.string "d_alpha"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4172:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyPKdS0_Pdj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_alpha(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4172:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7d_alpha
.comm _ZL7d_alpha,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC8:
.long -2147483648
.long 1075499636
.align 8
.LC11:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
/*******************************************************
****************** Device code ************************
******************************************************/
__constant__ double d_alpha;
__global__ void axpy (const double* A, const double* B, double* C, const unsigned int num_elements) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < num_elements)
C[idx] = d_alpha*A[idx]+B[idx];
}
/*******************************************************
******************** Host code ************************
******************************************************/
#define cudaErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void h_init_value(double* mem, const unsigned int num_elements) {
for (int i=0; i<num_elements; i++)
mem[i] = (double) rand();
}
void h_test (const double* A, const double* B, const double* C, const double alpha, const unsigned int num_elements) {
bool success = true;
for (int i=0; i<num_elements; i++) {
if (alpha*A[i]+B[i] != C[i])
success = false;
}
if (success) {
printf("[TEST] Test passed\n");
} else {
printf("[TEST] Test failed\n");
}
}
int main(int argc, char** argv) {
printf("\n");
printf("=========================================================================\n");
printf("[BLAS} axpy implementation \n");
printf("=========================================================================\n");
printf("\n");
/*** Configuration ***/
unsigned int num_elements = 3e+8;
size_t size = num_elements*sizeof(double);
timeval stime, etime;
double alpha = 1.0;
if (argc == 2)
alpha = atof(argv[1]);
/*** Mem allocation ***/
double *h_A=nullptr, *h_B=nullptr, *h_C=nullptr; // host(CPU)-side variable
double *d_A=nullptr, *d_B=nullptr, *d_C=nullptr; // device(GPU)-side variable
h_A = (double*) malloc (size);
h_B = (double*) malloc (size);
h_C = (double*) malloc (size);
cudaErrChk ( cudaMalloc ((void**)&d_A, size) );
cudaErrChk ( cudaMalloc ((void**)&d_B, size) );
cudaErrChk ( cudaMalloc ((void**)&d_C, size) );
cudaErrChk ( cudaMemcpyToSymbol (d_alpha, &alpha, sizeof(double)) );
printf("[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
, num_elements, 3*(double)size/1024/1024/1024);
/*** Program init ***/
h_init_value (h_A, num_elements);
h_init_value (h_B, num_elements);
cudaErrChk ( cudaMemcpy (d_A, h_A, size, cudaMemcpyHostToDevice) );
cudaErrChk ( cudaMemcpy (d_B, h_B, size, cudaMemcpyHostToDevice) );
/*** Launch a kernel ***/
unsigned int num_threads = 1024;
unsigned int num_blocks = (num_elements + (num_threads-1))/num_threads;
printf("[kernel] <%u, %u>-size grid launched\n"
, num_blocks, num_threads);
gettimeofday(&stime, NULL);
axpy<<<num_blocks, num_threads>>>(d_A, d_B, d_C, num_elements);
cudaErrChk ( cudaDeviceSynchronize () )
cudaErrChk ( cudaGetLastError () );
gettimeofday(&etime, NULL);
printf("[kernel] Elapsed time: %.4f\n"
, ((etime.tv_sec-stime.tv_sec)+(etime.tv_usec-stime.tv_usec)*10e-6) );
/*** Test computed result ***/
cudaErrChk ( cudaMemcpy (h_C, d_C, size, cudaMemcpyDeviceToHost) );
h_test (h_A, h_B, h_C, alpha, num_elements);
/*** Finalize ***/
free (h_A);
free (h_B);
free (h_C);
cudaErrChk (cudaFree (d_A));
cudaErrChk (cudaFree (d_B));
cudaErrChk (cudaFree (d_C));
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
/*******************************************************
****************** Device code ************************
******************************************************/
__constant__ double d_alpha;
__global__ void axpy (const double* A, const double* B, double* C, const unsigned int num_elements) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < num_elements)
C[idx] = d_alpha*A[idx]+B[idx];
}
/*******************************************************
******************** Host code ************************
******************************************************/
#define cudaErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void h_init_value(double* mem, const unsigned int num_elements) {
for (int i=0; i<num_elements; i++)
mem[i] = (double) rand();
}
void h_test (const double* A, const double* B, const double* C, const double alpha, const unsigned int num_elements) {
bool success = true;
for (int i=0; i<num_elements; i++) {
if (alpha*A[i]+B[i] != C[i])
success = false;
}
if (success) {
printf("[TEST] Test passed\n");
} else {
printf("[TEST] Test failed\n");
}
}
int main(int argc, char** argv) {
printf("\n");
printf("=========================================================================\n");
printf("[BLAS} axpy implementation \n");
printf("=========================================================================\n");
printf("\n");
/*** Configuration ***/
unsigned int num_elements = 3e+8;
size_t size = num_elements*sizeof(double);
timeval stime, etime;
double alpha = 1.0;
if (argc == 2)
alpha = atof(argv[1]);
/*** Mem allocation ***/
double *h_A=nullptr, *h_B=nullptr, *h_C=nullptr; // host(CPU)-side variable
double *d_A=nullptr, *d_B=nullptr, *d_C=nullptr; // device(GPU)-side variable
h_A = (double*) malloc (size);
h_B = (double*) malloc (size);
h_C = (double*) malloc (size);
cudaErrChk ( hipMalloc ((void**)&d_A, size) );
cudaErrChk ( hipMalloc ((void**)&d_B, size) );
cudaErrChk ( hipMalloc ((void**)&d_C, size) );
cudaErrChk ( hipMemcpyToSymbol (HIP_SYMBOL(d_alpha), &alpha, sizeof(double)) );
printf("[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
, num_elements, 3*(double)size/1024/1024/1024);
/*** Program init ***/
h_init_value (h_A, num_elements);
h_init_value (h_B, num_elements);
cudaErrChk ( hipMemcpy (d_A, h_A, size, hipMemcpyHostToDevice) );
cudaErrChk ( hipMemcpy (d_B, h_B, size, hipMemcpyHostToDevice) );
/*** Launch a kernel ***/
unsigned int num_threads = 1024;
unsigned int num_blocks = (num_elements + (num_threads-1))/num_threads;
printf("[kernel] <%u, %u>-size grid launched\n"
, num_blocks, num_threads);
gettimeofday(&stime, NULL);
axpy<<<num_blocks, num_threads>>>(d_A, d_B, d_C, num_elements);
cudaErrChk ( hipDeviceSynchronize () )
cudaErrChk ( hipGetLastError () );
gettimeofday(&etime, NULL);
printf("[kernel] Elapsed time: %.4f\n"
, ((etime.tv_sec-stime.tv_sec)+(etime.tv_usec-stime.tv_usec)*10e-6) );
/*** Test computed result ***/
cudaErrChk ( hipMemcpy (h_C, d_C, size, hipMemcpyDeviceToHost) );
h_test (h_A, h_B, h_C, alpha, num_elements);
/*** Finalize ***/
free (h_A);
free (h_B);
free (h_C);
cudaErrChk (hipFree (d_A));
cudaErrChk (hipFree (d_B));
cudaErrChk (hipFree (d_C));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
/*******************************************************
****************** Device code ************************
******************************************************/
__constant__ double d_alpha;
__global__ void axpy (const double* A, const double* B, double* C, const unsigned int num_elements) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < num_elements)
C[idx] = d_alpha*A[idx]+B[idx];
}
/*******************************************************
******************** Host code ************************
******************************************************/
#define cudaErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void h_init_value(double* mem, const unsigned int num_elements) {
for (int i=0; i<num_elements; i++)
mem[i] = (double) rand();
}
void h_test (const double* A, const double* B, const double* C, const double alpha, const unsigned int num_elements) {
bool success = true;
for (int i=0; i<num_elements; i++) {
if (alpha*A[i]+B[i] != C[i])
success = false;
}
if (success) {
printf("[TEST] Test passed\n");
} else {
printf("[TEST] Test failed\n");
}
}
int main(int argc, char** argv) {
printf("\n");
printf("=========================================================================\n");
printf("[BLAS} axpy implementation \n");
printf("=========================================================================\n");
printf("\n");
/*** Configuration ***/
unsigned int num_elements = 3e+8;
size_t size = num_elements*sizeof(double);
timeval stime, etime;
double alpha = 1.0;
if (argc == 2)
alpha = atof(argv[1]);
/*** Mem allocation ***/
double *h_A=nullptr, *h_B=nullptr, *h_C=nullptr; // host(CPU)-side variable
double *d_A=nullptr, *d_B=nullptr, *d_C=nullptr; // device(GPU)-side variable
h_A = (double*) malloc (size);
h_B = (double*) malloc (size);
h_C = (double*) malloc (size);
cudaErrChk ( hipMalloc ((void**)&d_A, size) );
cudaErrChk ( hipMalloc ((void**)&d_B, size) );
cudaErrChk ( hipMalloc ((void**)&d_C, size) );
cudaErrChk ( hipMemcpyToSymbol (HIP_SYMBOL(d_alpha), &alpha, sizeof(double)) );
printf("[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
, num_elements, 3*(double)size/1024/1024/1024);
/*** Program init ***/
h_init_value (h_A, num_elements);
h_init_value (h_B, num_elements);
cudaErrChk ( hipMemcpy (d_A, h_A, size, hipMemcpyHostToDevice) );
cudaErrChk ( hipMemcpy (d_B, h_B, size, hipMemcpyHostToDevice) );
/*** Launch a kernel ***/
unsigned int num_threads = 1024;
unsigned int num_blocks = (num_elements + (num_threads-1))/num_threads;
printf("[kernel] <%u, %u>-size grid launched\n"
, num_blocks, num_threads);
gettimeofday(&stime, NULL);
axpy<<<num_blocks, num_threads>>>(d_A, d_B, d_C, num_elements);
cudaErrChk ( hipDeviceSynchronize () )
cudaErrChk ( hipGetLastError () );
gettimeofday(&etime, NULL);
printf("[kernel] Elapsed time: %.4f\n"
, ((etime.tv_sec-stime.tv_sec)+(etime.tv_usec-stime.tv_usec)*10e-6) );
/*** Test computed result ***/
cudaErrChk ( hipMemcpy (h_C, d_C, size, hipMemcpyDeviceToHost) );
h_test (h_A, h_B, h_C, alpha, num_elements);
/*** Finalize ***/
free (h_A);
free (h_B);
free (h_C);
cudaErrChk (hipFree (d_A));
cudaErrChk (hipFree (d_B));
cudaErrChk (hipFree (d_C));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyPKdS0_Pdj
.globl _Z4axpyPKdS0_Pdj
.p2align 8
.type _Z4axpyPKdS0_Pdj,@function
_Z4axpyPKdS0_Pdj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_alpha@rel32@lo+4
s_addc_u32 s3, s3, d_alpha@rel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x10
s_load_b64 s[2:3], s[2:3], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], s[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyPKdS0_Pdj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4axpyPKdS0_Pdj, .Lfunc_end0-_Z4axpyPKdS0_Pdj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_alpha
.type d_alpha,@object
.section .bss,"aw",@nobits
.globl d_alpha
.p2align 3, 0x0
d_alpha:
.quad 0x0000000000000000
.size d_alpha, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_alpha
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyPKdS0_Pdj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4axpyPKdS0_Pdj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
/*******************************************************
****************** Device code ************************
******************************************************/
__constant__ double d_alpha;
__global__ void axpy (const double* A, const double* B, double* C, const unsigned int num_elements) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < num_elements)
C[idx] = d_alpha*A[idx]+B[idx];
}
/*******************************************************
******************** Host code ************************
******************************************************/
#define cudaErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void h_init_value(double* mem, const unsigned int num_elements) {
for (int i=0; i<num_elements; i++)
mem[i] = (double) rand();
}
void h_test (const double* A, const double* B, const double* C, const double alpha, const unsigned int num_elements) {
bool success = true;
for (int i=0; i<num_elements; i++) {
if (alpha*A[i]+B[i] != C[i])
success = false;
}
if (success) {
printf("[TEST] Test passed\n");
} else {
printf("[TEST] Test failed\n");
}
}
int main(int argc, char** argv) {
printf("\n");
printf("=========================================================================\n");
printf("[BLAS} axpy implementation \n");
printf("=========================================================================\n");
printf("\n");
/*** Configuration ***/
unsigned int num_elements = 3e+8;
size_t size = num_elements*sizeof(double);
timeval stime, etime;
double alpha = 1.0;
if (argc == 2)
alpha = atof(argv[1]);
/*** Mem allocation ***/
double *h_A=nullptr, *h_B=nullptr, *h_C=nullptr; // host(CPU)-side variable
double *d_A=nullptr, *d_B=nullptr, *d_C=nullptr; // device(GPU)-side variable
h_A = (double*) malloc (size);
h_B = (double*) malloc (size);
h_C = (double*) malloc (size);
cudaErrChk ( hipMalloc ((void**)&d_A, size) );
cudaErrChk ( hipMalloc ((void**)&d_B, size) );
cudaErrChk ( hipMalloc ((void**)&d_C, size) );
cudaErrChk ( hipMemcpyToSymbol (HIP_SYMBOL(d_alpha), &alpha, sizeof(double)) );
printf("[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
, num_elements, 3*(double)size/1024/1024/1024);
/*** Program init ***/
h_init_value (h_A, num_elements);
h_init_value (h_B, num_elements);
cudaErrChk ( hipMemcpy (d_A, h_A, size, hipMemcpyHostToDevice) );
cudaErrChk ( hipMemcpy (d_B, h_B, size, hipMemcpyHostToDevice) );
/*** Launch a kernel ***/
unsigned int num_threads = 1024;
unsigned int num_blocks = (num_elements + (num_threads-1))/num_threads;
printf("[kernel] <%u, %u>-size grid launched\n"
, num_blocks, num_threads);
gettimeofday(&stime, NULL);
axpy<<<num_blocks, num_threads>>>(d_A, d_B, d_C, num_elements);
cudaErrChk ( hipDeviceSynchronize () )
cudaErrChk ( hipGetLastError () );
gettimeofday(&etime, NULL);
printf("[kernel] Elapsed time: %.4f\n"
, ((etime.tv_sec-stime.tv_sec)+(etime.tv_usec-stime.tv_usec)*10e-6) );
/*** Test computed result ***/
cudaErrChk ( hipMemcpy (h_C, d_C, size, hipMemcpyDeviceToHost) );
h_test (h_A, h_B, h_C, alpha, num_elements);
/*** Finalize ***/
free (h_A);
free (h_B);
free (h_C);
cudaErrChk (hipFree (d_A));
cudaErrChk (hipFree (d_B));
cudaErrChk (hipFree (d_C));
return 0;
} | .text
.file "axpy.hip"
.globl _Z19__device_stub__axpyPKdS0_Pdj # -- Begin function _Z19__device_stub__axpyPKdS0_Pdj
.p2align 4, 0x90
.type _Z19__device_stub__axpyPKdS0_Pdj,@function
_Z19__device_stub__axpyPKdS0_Pdj: # @_Z19__device_stub__axpyPKdS0_Pdj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyPKdS0_Pdj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__axpyPKdS0_Pdj, .Lfunc_end0-_Z19__device_stub__axpyPKdS0_Pdj
.cfi_endproc
# -- End function
.globl _Z12h_init_valuePdj # -- Begin function _Z12h_init_valuePdj
.p2align 4, 0x90
.type _Z12h_init_valuePdj,@function
_Z12h_init_valuePdj: # @_Z12h_init_valuePdj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12h_init_valuePdj, .Lfunc_end1-_Z12h_init_valuePdj
.cfi_endproc
# -- End function
.globl _Z6h_testPKdS0_S0_dj # -- Begin function _Z6h_testPKdS0_S0_dj
.p2align 4, 0x90
.type _Z6h_testPKdS0_S0_dj,@function
_Z6h_testPKdS0_S0_dj: # @_Z6h_testPKdS0_S0_dj
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB2_1
# %bb.2: # %.lr.ph.preheader
movl %ecx, %eax
movb $1, %cl
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%rsi,%r9,8), %xmm1
ucomisd (%rdx,%r9,8), %xmm1
movzbl %cl, %ecx
cmovnel %r8d, %ecx
cmovpl %r8d, %ecx
incq %r9
cmpq %r9, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge.loopexit
testb $1, %cl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
jmp puts@PLT # TAILCALL
.LBB2_1:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z6h_testPKdS0_S0_dj, .Lfunc_end2-_Z6h_testPKdS0_S0_dj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x401ad27480000000 # double 6.7055225372314453
.LCPI3_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $10, %edi
callq putchar@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $10, %edi
callq putchar@PLT
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 32(%rsp)
cmpl $2, %ebp
jne .LBB3_2
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 32(%rsp)
.LBB3_2:
movl $2400000000, %r12d # imm = 0x8F0D1800
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $2400000000, %edi # imm = 0x8F0D1800
callq malloc
movq %rax, %rbx
movl $2400000000, %edi # imm = 0x8F0D1800
callq malloc
movq %rax, %r14
movl $2400000000, %edi # imm = 0x8F0D1800
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $2400000000, %esi # imm = 0x8F0D1800
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $2400000000, %esi # imm = 0x8F0D1800
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit41
leaq 8(%rsp), %rdi
movl $2400000000, %esi # imm = 0x8F0D1800
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit43
leaq 32(%rsp), %rsi
movl $d_alpha, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit45
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movl $300000000, %esi # imm = 0x11E1A300
movb $1, %al
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r13,8)
incq %r13
cmpq $300000000, %r13 # imm = 0x11E1A300
jne .LBB3_12
# %bb.13: # %.lr.ph.i46.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_14: # %.lr.ph.i46
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%r13,8)
incq %r13
cmpq $300000000, %r13 # imm = 0x11E1A300
jne .LBB3_14
# %bb.15: # %_Z12h_init_valuePdj.exit50
movq 24(%rsp), %rdi
movl $2400000000, %edx # imm = 0x8F0D1800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit52
movq 16(%rsp), %rdi
movl $2400000000, %edx # imm = 0x8F0D1800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit54
movl $.L.str.7, %edi
movl $292969, %esi # imm = 0x47869
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 1894968320(%r12), %rdx
leaq 1895260265(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $300000000, 44(%rsp) # imm = 0x11E1A300
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4axpyPKdS0_Pdj, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit56
callq hipGetLastError
testl %eax, %eax
jne .LBB3_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit58
xorl %r12d, %r12d
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
subq 152(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 160(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
addsd %xmm1, %xmm0
movb $1, %bpl
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $2400000000, %edx # imm = 0x8F0D1800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit60
movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_28: # %.lr.ph.i61
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%r14,%rax,8), %xmm1
ucomisd (%r15,%rax,8), %xmm1
movzbl %bpl, %ebp
cmovnel %r12d, %ebp
cmovpl %r12d, %ebp
incq %rax
cmpq $300000000, %rax # imm = 0x11E1A300
jne .LBB3_28
# %bb.29: # %._crit_edge.loopexit.i
testb $1, %bpl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit66
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_32
# %bb.33: # %_Z9gpuAssert10hipError_tPKcib.exit68
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit70
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB3_4
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB3_4
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
jmp .LBB3_4
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB3_4
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB3_4
.LBB3_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %r8d
jmp .LBB3_4
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %r8d
jmp .LBB3_4
.LBB3_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %r8d
jmp .LBB3_4
.LBB3_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %r8d
jmp .LBB3_4
.LBB3_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB3_4
.LBB3_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB3_4
.LBB3_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
.LBB3_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyPKdS0_Pdj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_alpha, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_alpha,@object # @d_alpha
.local d_alpha
.comm d_alpha,8,8
.type _Z4axpyPKdS0_Pdj,@object # @_Z4axpyPKdS0_Pdj
.section .rodata,"a",@progbits
.globl _Z4axpyPKdS0_Pdj
.p2align 3, 0x0
_Z4axpyPKdS0_Pdj:
.quad _Z19__device_stub__axpyPKdS0_Pdj
.size _Z4axpyPKdS0_Pdj, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jhson989/cuda_study/main/jhBLAS/axpy/axpy.hip"
.size .L.str.5, 103
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
.size .L.str.6, 88
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "[kernel] <%u, %u>-size grid launched\n"
.size .L.str.7, 38
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "[kernel] Elapsed time: %.4f\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CUDA assert: %s %s %d\n"
.size .L.str.9, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4axpyPKdS0_Pdj"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_alpha"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[TEST] Test failed"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "[TEST] Test passed"
.size .Lstr.1, 19
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "[BLAS} axpy implementation "
.size .Lstr.3, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "========================================================================="
.size .Lstr.4, 74
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyPKdS0_Pdj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_alpha
.addrsig_sym _Z4axpyPKdS0_Pdj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4axpyPKdS0_Pdj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DFMA R6, R2, c[0x3][0x0], R4 ; /* 0x00c0000002067a2b */
/* 0x004e0e0000000004 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyPKdS0_Pdj
.globl _Z4axpyPKdS0_Pdj
.p2align 8
.type _Z4axpyPKdS0_Pdj,@function
_Z4axpyPKdS0_Pdj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_alpha@rel32@lo+4
s_addc_u32 s3, s3, d_alpha@rel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x10
s_load_b64 s[2:3], s[2:3], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], s[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyPKdS0_Pdj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4axpyPKdS0_Pdj, .Lfunc_end0-_Z4axpyPKdS0_Pdj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_alpha
.type d_alpha,@object
.section .bss,"aw",@nobits
.globl d_alpha
.p2align 3, 0x0
d_alpha:
.quad 0x0000000000000000
.size d_alpha, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_alpha
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyPKdS0_Pdj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4axpyPKdS0_Pdj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001a633_00000000-6_axpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4147:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4147:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA assert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4141:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4141:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z12h_init_valuePdj
.type _Z12h_init_valuePdj, @function
_Z12h_init_valuePdj:
.LFB4142:
.cfi_startproc
endbr64
testl %esi, %esi
je .L16
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %esi
leaq (%rdi,%rsi,8), %rbp
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE4142:
.size _Z12h_init_valuePdj, .-_Z12h_init_valuePdj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "[TEST] Test passed\n"
.LC2:
.string "[TEST] Test failed\n"
.text
.globl _Z6h_testPKdS0_S0_dj
.type _Z6h_testPKdS0_S0_dj, @function
_Z6h_testPKdS0_S0_dj:
.LFB4143:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %ecx, %ecx
je .L20
movl %ecx, %ecx
salq $3, %rcx
movl $0, %eax
movl $1, %r8d
movl $0, %r9d
jmp .L23
.L26:
movl %r9d, %r8d
.L21:
addq $8, %rax
cmpq %rcx, %rax
je .L29
.L23:
movapd %xmm0, %xmm1
mulsd (%rdi,%rax), %xmm1
addsd (%rsi,%rax), %xmm1
ucomisd (%rdx,%rax), %xmm1
jp .L26
je .L21
jmp .L26
.L29:
testb %r8b, %r8b
jne .L20
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L20:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4143:
.size _Z6h_testPKdS0_S0_dj, .-_Z6h_testPKdS0_S0_dj
.globl _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
.type _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj, @function
_Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj:
.LFB4169:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4axpyPKdS0_Pdj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4169:
.size _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj, .-_Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
.globl _Z4axpyPKdS0_Pdj
.type _Z4axpyPKdS0_Pdj, @function
_Z4axpyPKdS0_Pdj:
.LFB4170:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4170:
.size _Z4axpyPKdS0_Pdj, .-_Z4axpyPKdS0_Pdj
.section .rodata.str1.1
.LC3:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "=========================================================================\n"
.section .rodata.str1.1
.LC5:
.string "[BLAS} axpy implementation \n"
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jhson989/cuda_study/main/jhBLAS/axpy/axpy.cu"
.align 8
.LC9:
.string "[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
.align 8
.LC10:
.string "[kernel] <%u, %u>-size grid launched\n"
.section .rodata.str1.1
.LC12:
.string "[kernel] Elapsed time: %.4f\n"
.text
.globl main
.type main, @function
main:
.LFB4144:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %r12
movq %r12, %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC4(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq .LC6(%rip), %rax
movq %rax, (%rsp)
cmpl $2, %ebx
je .L43
.L39:
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $2400000000, %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $83, %edx
leaq .LC7(%rip), %r13
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $84, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $85, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL7d_alpha(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movsd .LC8(%rip), %xmm0
movl $300000000, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $300000000, %esi
movq %r12, %rdi
call _Z12h_init_valuePdj
movl $300000000, %esi
movq %rbp, %rdi
call _Z12h_init_valuePdj
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $94, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $95, %edx
movq %r13, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1024, %ecx
movl $292969, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $292969, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $106, %edx
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaGetLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $107, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC11(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $2400000000, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $114, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $300000000, %ecx
movsd (%rsp), %xmm0
movq %r14, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z6h_testPKdS0_S0_dj
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $122, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $123, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $124, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq 8(%rbp), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
jmp .L39
.L44:
movl $300000000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z4axpyPKdS0_PdjPKdS0_Pdj
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4144:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z4axpyPKdS0_Pdj"
.LC14:
.string "d_alpha"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4172:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyPKdS0_Pdj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_alpha(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4172:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7d_alpha
.comm _ZL7d_alpha,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC8:
.long -2147483648
.long 1075499636
.align 8
.LC11:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "axpy.hip"
.globl _Z19__device_stub__axpyPKdS0_Pdj # -- Begin function _Z19__device_stub__axpyPKdS0_Pdj
.p2align 4, 0x90
.type _Z19__device_stub__axpyPKdS0_Pdj,@function
_Z19__device_stub__axpyPKdS0_Pdj: # @_Z19__device_stub__axpyPKdS0_Pdj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4axpyPKdS0_Pdj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__axpyPKdS0_Pdj, .Lfunc_end0-_Z19__device_stub__axpyPKdS0_Pdj
.cfi_endproc
# -- End function
.globl _Z12h_init_valuePdj # -- Begin function _Z12h_init_valuePdj
.p2align 4, 0x90
.type _Z12h_init_valuePdj,@function
_Z12h_init_valuePdj: # @_Z12h_init_valuePdj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z12h_init_valuePdj, .Lfunc_end1-_Z12h_init_valuePdj
.cfi_endproc
# -- End function
.globl _Z6h_testPKdS0_S0_dj # -- Begin function _Z6h_testPKdS0_S0_dj
.p2align 4, 0x90
.type _Z6h_testPKdS0_S0_dj,@function
_Z6h_testPKdS0_S0_dj: # @_Z6h_testPKdS0_S0_dj
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB2_1
# %bb.2: # %.lr.ph.preheader
movl %ecx, %eax
movb $1, %cl
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%rsi,%r9,8), %xmm1
ucomisd (%rdx,%r9,8), %xmm1
movzbl %cl, %ecx
cmovnel %r8d, %ecx
cmovpl %r8d, %ecx
incq %r9
cmpq %r9, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge.loopexit
testb $1, %cl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
jmp puts@PLT # TAILCALL
.LBB2_1:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z6h_testPKdS0_S0_dj, .Lfunc_end2-_Z6h_testPKdS0_S0_dj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x401ad27480000000 # double 6.7055225372314453
.LCPI3_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $10, %edi
callq putchar@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $10, %edi
callq putchar@PLT
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 32(%rsp)
cmpl $2, %ebp
jne .LBB3_2
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 32(%rsp)
.LBB3_2:
movl $2400000000, %r12d # imm = 0x8F0D1800
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $2400000000, %edi # imm = 0x8F0D1800
callq malloc
movq %rax, %rbx
movl $2400000000, %edi # imm = 0x8F0D1800
callq malloc
movq %rax, %r14
movl $2400000000, %edi # imm = 0x8F0D1800
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $2400000000, %esi # imm = 0x8F0D1800
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $2400000000, %esi # imm = 0x8F0D1800
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit41
leaq 8(%rsp), %rdi
movl $2400000000, %esi # imm = 0x8F0D1800
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit43
leaq 32(%rsp), %rsi
movl $d_alpha, %edi
movl $8, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit45
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movl $300000000, %esi # imm = 0x11E1A300
movb $1, %al
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r13,8)
incq %r13
cmpq $300000000, %r13 # imm = 0x11E1A300
jne .LBB3_12
# %bb.13: # %.lr.ph.i46.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_14: # %.lr.ph.i46
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%r13,8)
incq %r13
cmpq $300000000, %r13 # imm = 0x11E1A300
jne .LBB3_14
# %bb.15: # %_Z12h_init_valuePdj.exit50
movq 24(%rsp), %rdi
movl $2400000000, %edx # imm = 0x8F0D1800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit52
movq 16(%rsp), %rdi
movl $2400000000, %edx # imm = 0x8F0D1800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit54
movl $.L.str.7, %edi
movl $292969, %esi # imm = 0x47869
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
leaq 152(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 1894968320(%r12), %rdx
leaq 1895260265(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $300000000, 44(%rsp) # imm = 0x11E1A300
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 44(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4axpyPKdS0_Pdj, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit56
callq hipGetLastError
testl %eax, %eax
jne .LBB3_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit58
xorl %r12d, %r12d
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq 56(%rsp), %rcx
subq 152(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 160(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
addsd %xmm1, %xmm0
movb $1, %bpl
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $2400000000, %edx # imm = 0x8F0D1800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit60
movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_28: # %.lr.ph.i61
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%r14,%rax,8), %xmm1
ucomisd (%r15,%rax,8), %xmm1
movzbl %bpl, %ebp
cmovnel %r12d, %ebp
cmovpl %r12d, %ebp
incq %rax
cmpq $300000000, %rax # imm = 0x11E1A300
jne .LBB3_28
# %bb.29: # %._crit_edge.loopexit.i
testb $1, %bpl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit66
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_32
# %bb.33: # %_Z9gpuAssert10hipError_tPKcib.exit68
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit70
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %r8d
jmp .LBB3_4
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB3_4
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %r8d
jmp .LBB3_4
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB3_4
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB3_4
.LBB3_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %r8d
jmp .LBB3_4
.LBB3_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %r8d
jmp .LBB3_4
.LBB3_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %r8d
jmp .LBB3_4
.LBB3_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %r8d
jmp .LBB3_4
.LBB3_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB3_4
.LBB3_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB3_4
.LBB3_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
.LBB3_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyPKdS0_Pdj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_alpha, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_alpha,@object # @d_alpha
.local d_alpha
.comm d_alpha,8,8
.type _Z4axpyPKdS0_Pdj,@object # @_Z4axpyPKdS0_Pdj
.section .rodata,"a",@progbits
.globl _Z4axpyPKdS0_Pdj
.p2align 3, 0x0
_Z4axpyPKdS0_Pdj:
.quad _Z19__device_stub__axpyPKdS0_Pdj
.size _Z4axpyPKdS0_Pdj, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jhson989/cuda_study/main/jhBLAS/axpy/axpy.hip"
.size .L.str.5, 103
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "[mem] Allocated : 3 doulbe precision vectors[%u-D]. %.2fGB for each devices [CPU, GPU]\n"
.size .L.str.6, 88
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "[kernel] <%u, %u>-size grid launched\n"
.size .L.str.7, 38
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "[kernel] Elapsed time: %.4f\n"
.size .L.str.8, 29
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CUDA assert: %s %s %d\n"
.size .L.str.9, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4axpyPKdS0_Pdj"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_alpha"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[TEST] Test failed"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "[TEST] Test passed"
.size .Lstr.1, 19
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "[BLAS} axpy implementation "
.size .Lstr.3, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "========================================================================="
.size .Lstr.4, 74
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyPKdS0_Pdj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_alpha
.addrsig_sym _Z4axpyPKdS0_Pdj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void trapz_kernel(float* y, float* x, float* auc, int num_selected) {
__shared__ float s_auc;
s_auc = 0.0f;
__syncthreads();
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected - 1; gid += blockDim.x * gridDim.x) {
float a = x[gid];
float b = x[gid + 1];
float fa = y[gid];
float fb = y[gid + 1];
float area = (b - a) * (fa + fb) / 2.0f;
if (gid == 0) {
area += (a * fa / 2.0f);
}
atomicAdd(&s_auc, area);
}
__syncthreads();
if (threadIdx.x == 0) {
atomicAdd(auc, s_auc);
}
} | code for sm_80
Function : _Z12trapz_kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x001fc600078e020d */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 BRA 0x240 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x040fe200078e0205 */
/*00e0*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040604087981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ee2000c1e1900 */
/*0120*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0130*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0140*/ BSSY B0, 0x200 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0150*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x004fc40000000000 */
/*0160*/ FADD R11, R8, R9 ; /* 0x00000009080b7221 */
/* 0x008fe40000000000 */
/*0170*/ FMUL R7, R7, R9 ; /* 0x0000000907077220 */
/* 0x000fe40000400000 */
/*0180*/ FMUL.D2 R6, R6, R11 ; /* 0x0000000b06067220 */
/* 0x000fc80000300000 */
/*0190*/ @!P0 FFMA R6, R7, 0.5, R6 ; /* 0x3f00000007068823 */
/* 0x000fe40000000006 */
/*01a0*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e240000000800 */
/*01b0*/ FADD R3, R6, R2 ; /* 0x0000000206037221 */
/* 0x001fcc0000000000 */
/*01c0*/ ATOMS.CAST.SPIN R3, [RZ], R2, R3 ; /* 0x00000002ff03738d */
/* 0x000e240001800003 */
/*01d0*/ ISETP.EQ.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x001fda0003f02070 */
/*01e0*/ @!P0 BRA 0x1a0 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fca0000000f00 */
/*0210*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0220*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0230*/ @!P0 BRA 0xb0 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0240*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05270 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0290*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*02a0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*02b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e786 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void trapz_kernel(float* y, float* x, float* auc, int num_selected) {
__shared__ float s_auc;
s_auc = 0.0f;
__syncthreads();
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected - 1; gid += blockDim.x * gridDim.x) {
float a = x[gid];
float b = x[gid + 1];
float fa = y[gid];
float fb = y[gid + 1];
float area = (b - a) * (fa + fb) / 2.0f;
if (gid == 0) {
area += (a * fa / 2.0f);
}
atomicAdd(&s_auc, area);
}
__syncthreads();
if (threadIdx.x == 0) {
atomicAdd(auc, s_auc);
}
} | .file "tmpxft_00077852_00000000-6_trapz_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12trapz_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i
.globl _Z12trapz_kernelPfS_S_i
.type _Z12trapz_kernelPfS_S_i, @function
_Z12trapz_kernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12trapz_kernelPfS_S_i, .-_Z12trapz_kernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12trapz_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12trapz_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void trapz_kernel(float* y, float* x, float* auc, int num_selected) {
__shared__ float s_auc;
s_auc = 0.0f;
__syncthreads();
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected - 1; gid += blockDim.x * gridDim.x) {
float a = x[gid];
float b = x[gid + 1];
float fa = y[gid];
float fb = y[gid + 1];
float area = (b - a) * (fa + fb) / 2.0f;
if (gid == 0) {
area += (a * fa / 2.0f);
}
atomicAdd(&s_auc, area);
}
__syncthreads();
if (threadIdx.x == 0) {
atomicAdd(auc, s_auc);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void trapz_kernel(float* y, float* x, float* auc, int num_selected) {
__shared__ float s_auc;
s_auc = 0.0f;
__syncthreads();
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected - 1; gid += blockDim.x * gridDim.x) {
float a = x[gid];
float b = x[gid + 1];
float fa = y[gid];
float fb = y[gid + 1];
float area = (b - a) * (fa + fb) / 2.0f;
if (gid == 0) {
area += (a * fa / 2.0f);
}
atomicAdd(&s_auc, area);
}
__syncthreads();
if (threadIdx.x == 0) {
atomicAdd(auc, s_auc);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void trapz_kernel(float* y, float* x, float* auc, int num_selected) {
__shared__ float s_auc;
s_auc = 0.0f;
__syncthreads();
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected - 1; gid += blockDim.x * gridDim.x) {
float a = x[gid];
float b = x[gid + 1];
float fa = y[gid];
float fb = y[gid + 1];
float area = (b - a) * (fa + fb) / 2.0f;
if (gid == 0) {
area += (a * fa / 2.0f);
}
atomicAdd(&s_auc, area);
}
__syncthreads();
if (threadIdx.x == 0) {
atomicAdd(auc, s_auc);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12trapz_kernelPfS_S_i
.globl _Z12trapz_kernelPfS_S_i
.p2align 8
.type _Z12trapz_kernelPfS_S_i,@function
_Z12trapz_kernelPfS_S_i:
v_mov_b32_e32 v3, 0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s9, exec_lo
ds_store_b32 v3, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_add_i32 s8, s8, -1
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s10
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, v4, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v2, v[4:5], off
s_clause 0x1
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[8:9], off
global_load_b32 v6, v[10:11], off
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_waitcnt vmcnt(1)
v_dual_mul_f32 v7, v4, v2 :: v_dual_sub_f32 v4, v5, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, v2, v6 :: v_dual_mul_f32 v5, 0.5, v7
v_mul_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x80000000, v5, vcc_lo
v_fmac_f32_e32 v4, 0.5, v2
v_bfrev_b32_e32 v2, 1
.LBB0_4:
s_ctz_i32_b32 s11, s10
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_readlane_b32 s12, v4, s11
s_lshl_b32 s11, 1, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s10, s10, s11
s_cmp_lg_u32 s10, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s12, v2
s_cbranch_scc1 .LBB0_4
v_mbcnt_lo_u32_b32 v4, exec_lo, 0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v4
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_2
ds_add_f32 v3, v2
s_branch .LBB0_2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_ubyte0_e32 v1, s2
v_mov_b32_e32 v2, 0
s_mov_b32 s2, 0
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
v_mul_f32_e32 v3, v0, v1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v3
global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12trapz_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12trapz_kernelPfS_S_i, .Lfunc_end0-_Z12trapz_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12trapz_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12trapz_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void trapz_kernel(float* y, float* x, float* auc, int num_selected) {
__shared__ float s_auc;
s_auc = 0.0f;
__syncthreads();
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected - 1; gid += blockDim.x * gridDim.x) {
float a = x[gid];
float b = x[gid + 1];
float fa = y[gid];
float fb = y[gid + 1];
float area = (b - a) * (fa + fb) / 2.0f;
if (gid == 0) {
area += (a * fa / 2.0f);
}
atomicAdd(&s_auc, area);
}
__syncthreads();
if (threadIdx.x == 0) {
atomicAdd(auc, s_auc);
}
} | .text
.file "trapz_kernel.hip"
.globl _Z27__device_stub__trapz_kernelPfS_S_i # -- Begin function _Z27__device_stub__trapz_kernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__trapz_kernelPfS_S_i,@function
_Z27__device_stub__trapz_kernelPfS_S_i: # @_Z27__device_stub__trapz_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12trapz_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__trapz_kernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__trapz_kernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12trapz_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12trapz_kernelPfS_S_i,@object # @_Z12trapz_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12trapz_kernelPfS_S_i
.p2align 3, 0x0
_Z12trapz_kernelPfS_S_i:
.quad _Z27__device_stub__trapz_kernelPfS_S_i
.size _Z12trapz_kernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12trapz_kernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__trapz_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12trapz_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12trapz_kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000800 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x001fc600078e020d */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 BRA 0x240 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x040fe200078e0205 */
/*00e0*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040602067981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040604087981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ee2000c1e1900 */
/*0120*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0130*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0140*/ BSSY B0, 0x200 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0150*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x004fc40000000000 */
/*0160*/ FADD R11, R8, R9 ; /* 0x00000009080b7221 */
/* 0x008fe40000000000 */
/*0170*/ FMUL R7, R7, R9 ; /* 0x0000000907077220 */
/* 0x000fe40000400000 */
/*0180*/ FMUL.D2 R6, R6, R11 ; /* 0x0000000b06067220 */
/* 0x000fc80000300000 */
/*0190*/ @!P0 FFMA R6, R7, 0.5, R6 ; /* 0x3f00000007068823 */
/* 0x000fe40000000006 */
/*01a0*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e240000000800 */
/*01b0*/ FADD R3, R6, R2 ; /* 0x0000000206037221 */
/* 0x001fcc0000000000 */
/*01c0*/ ATOMS.CAST.SPIN R3, [RZ], R2, R3 ; /* 0x00000002ff03738d */
/* 0x000e240001800003 */
/*01d0*/ ISETP.EQ.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x001fda0003f02070 */
/*01e0*/ @!P0 BRA 0x1a0 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fca0000000f00 */
/*0210*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*0220*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0230*/ @!P0 BRA 0xb0 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0240*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05270 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0290*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*02a0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*02b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e786 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12trapz_kernelPfS_S_i
.globl _Z12trapz_kernelPfS_S_i
.p2align 8
.type _Z12trapz_kernelPfS_S_i,@function
_Z12trapz_kernelPfS_S_i:
v_mov_b32_e32 v3, 0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s9, exec_lo
ds_store_b32 v3, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s4, 0xffff
s_add_i32 s8, s8, -1
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s10
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, v4, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_load_b32 v2, v[4:5], off
s_clause 0x1
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[8:9], off
global_load_b32 v6, v[10:11], off
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_waitcnt vmcnt(1)
v_dual_mul_f32 v7, v4, v2 :: v_dual_sub_f32 v4, v5, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, v2, v6 :: v_dual_mul_f32 v5, 0.5, v7
v_mul_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x80000000, v5, vcc_lo
v_fmac_f32_e32 v4, 0.5, v2
v_bfrev_b32_e32 v2, 1
.LBB0_4:
s_ctz_i32_b32 s11, s10
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_readlane_b32 s12, v4, s11
s_lshl_b32 s11, 1, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s10, s10, s11
s_cmp_lg_u32 s10, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s12, v2
s_cbranch_scc1 .LBB0_4
v_mbcnt_lo_u32_b32 v4, exec_lo, 0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v4
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_2
ds_add_f32 v3, v2
s_branch .LBB0_2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_ubyte0_e32 v1, s2
v_mov_b32_e32 v2, 0
s_mov_b32 s2, 0
ds_load_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
v_mul_f32_e32 v3, v0, v1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v3
global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12trapz_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12trapz_kernelPfS_S_i, .Lfunc_end0-_Z12trapz_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12trapz_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12trapz_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00077852_00000000-6_trapz_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12trapz_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i
.globl _Z12trapz_kernelPfS_S_i
.type _Z12trapz_kernelPfS_S_i, @function
_Z12trapz_kernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12trapz_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12trapz_kernelPfS_S_i, .-_Z12trapz_kernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12trapz_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12trapz_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "trapz_kernel.hip"
.globl _Z27__device_stub__trapz_kernelPfS_S_i # -- Begin function _Z27__device_stub__trapz_kernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__trapz_kernelPfS_S_i,@function
_Z27__device_stub__trapz_kernelPfS_S_i: # @_Z27__device_stub__trapz_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12trapz_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__trapz_kernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__trapz_kernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12trapz_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12trapz_kernelPfS_S_i,@object # @_Z12trapz_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12trapz_kernelPfS_S_i
.p2align 3, 0x0
_Z12trapz_kernelPfS_S_i:
.quad _Z27__device_stub__trapz_kernelPfS_S_i
.size _Z12trapz_kernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12trapz_kernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__trapz_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12trapz_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void nullkernel( void) {
}
int main(void) {
nullkernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
} | code for sm_80
Function : _Z10nullkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void nullkernel( void) {
}
int main(void) {
nullkernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
} | .file "tmpxft_000fbbeb_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10nullkernelvv
.type _Z29__device_stub__Z10nullkernelvv, @function
_Z29__device_stub__Z10nullkernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10nullkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10nullkernelvv, .-_Z29__device_stub__Z10nullkernelvv
.globl _Z10nullkernelv
.type _Z10nullkernelv, @function
_Z10nullkernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10nullkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10nullkernelv, .-_Z10nullkernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10nullkernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10nullkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10nullkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void nullkernel( void) {
}
int main(void) {
nullkernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void nullkernel( void) {
}
int main(void) {
nullkernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void nullkernel( void) {
}
int main(void) {
nullkernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10nullkernelv
.globl _Z10nullkernelv
.p2align 8
.type _Z10nullkernelv,@function
_Z10nullkernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10nullkernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10nullkernelv, .Lfunc_end0-_Z10nullkernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10nullkernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10nullkernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void nullkernel( void) {
}
int main(void) {
nullkernel<<<1,1>>>();
printf("Hello World!\n");
return 0;
} | .text
.file "hello_world.hip"
.globl _Z25__device_stub__nullkernelv # -- Begin function _Z25__device_stub__nullkernelv
.p2align 4, 0x90
.type _Z25__device_stub__nullkernelv,@function
_Z25__device_stub__nullkernelv: # @_Z25__device_stub__nullkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10nullkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__nullkernelv, .Lfunc_end0-_Z25__device_stub__nullkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10nullkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10nullkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10nullkernelv,@object # @_Z10nullkernelv
.section .rodata,"a",@progbits
.globl _Z10nullkernelv
.p2align 3, 0x0
_Z10nullkernelv:
.quad _Z25__device_stub__nullkernelv
.size _Z10nullkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10nullkernelv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__nullkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10nullkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10nullkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10nullkernelv
.globl _Z10nullkernelv
.p2align 8
.type _Z10nullkernelv,@function
_Z10nullkernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10nullkernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10nullkernelv, .Lfunc_end0-_Z10nullkernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10nullkernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10nullkernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fbbeb_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10nullkernelvv
.type _Z29__device_stub__Z10nullkernelvv, @function
_Z29__device_stub__Z10nullkernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10nullkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10nullkernelvv, .-_Z29__device_stub__Z10nullkernelvv
.globl _Z10nullkernelv
.type _Z10nullkernelv, @function
_Z10nullkernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10nullkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10nullkernelv, .-_Z10nullkernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10nullkernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10nullkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10nullkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z25__device_stub__nullkernelv # -- Begin function _Z25__device_stub__nullkernelv
.p2align 4, 0x90
.type _Z25__device_stub__nullkernelv,@function
_Z25__device_stub__nullkernelv: # @_Z25__device_stub__nullkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10nullkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__nullkernelv, .Lfunc_end0-_Z25__device_stub__nullkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10nullkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10nullkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10nullkernelv,@object # @_Z10nullkernelv
.section .rodata,"a",@progbits
.globl _Z10nullkernelv
.p2align 3, 0x0
_Z10nullkernelv:
.quad _Z25__device_stub__nullkernelv
.size _Z10nullkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10nullkernelv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__nullkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10nullkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include <cassert>
__device__ inline void swapf(float & a, float & b)
{
float tmp = a;
a = b;
b = tmp;
}
__device__ inline void swap(int & a, int & b)
{
int tmp = a;
a = b ;
b = tmp;
}
__global__ void KnnKernel(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
const int size = 4096;
__shared__ float dist[size];
__shared__ int idx[size];
assert( n <= size );
for ( int bi = blockIdx.x ; bi < b ; bi += gridDim.x )
{
for ( int i = blockIdx.y ; i < n ; i += gridDim.y )
{
for ( int j = threadIdx.x ; j < n ; j += blockDim.x )
{
if( i == j ){
dist[j] = 0;
idx[j] = j;
continue;
}
float d = 0.0;
for ( int di = 0 ; di < d ; ++di )
{
float dif = xyz[(bi*n+i)*3+di] - xyz[(bi*n+j)*3+di];
d += dif*dif;
}
dist[j] = d;
idx[j] = j;
}
__syncthreads();
//odd-even sort
int pownum = int(log2(float(n)));
if ( n != pow(2, pownum) ){
for ( int cnt = 0 ; cnt < ( n + 1 ) / 2 ; ++cnt )
{
for ( int j = 2*threadIdx.x + 1 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
for ( int j = 2*threadIdx.x + 2 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
}
}else{
//Bitonic Sort
for (unsigned int t = 2; t <= n ; t *= 2)
{
// Bitonic merge:
for (unsigned int j = t / 2; j>0; j /= 2)
{
for (unsigned int tid = threadIdx.x ; tid < n ; tid += blockDim.x )
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & t) == 0)
{
if (dist[tid] > dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
else
{
if (dist[tid] < dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
}
}
__syncthreads();
}
}
}
__syncthreads();
//copy result
for ( int j = threadIdx.x ; j < k ; j += blockDim.x )
{
result[(bi*n+i)*k+j] = dist[j+1];
result_i[ ((bi*n+i)*k+j)*2+0 ] = bi;
result_i[ ((bi*n+i)*k+j)*2+1 ] = idx[j+1];
}
}
}
}
void KnnKernelLauncher(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
KnnKernel<<<dim3(b,16,1),512>>>(b,n,d,xyz,k,result,result_i);
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include <cassert>
__device__ inline void swapf(float & a, float & b)
{
float tmp = a;
a = b;
b = tmp;
}
__device__ inline void swap(int & a, int & b)
{
int tmp = a;
a = b ;
b = tmp;
}
__global__ void KnnKernel(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
const int size = 4096;
__shared__ float dist[size];
__shared__ int idx[size];
assert( n <= size );
for ( int bi = blockIdx.x ; bi < b ; bi += gridDim.x )
{
for ( int i = blockIdx.y ; i < n ; i += gridDim.y )
{
for ( int j = threadIdx.x ; j < n ; j += blockDim.x )
{
if( i == j ){
dist[j] = 0;
idx[j] = j;
continue;
}
float d = 0.0;
for ( int di = 0 ; di < d ; ++di )
{
float dif = xyz[(bi*n+i)*3+di] - xyz[(bi*n+j)*3+di];
d += dif*dif;
}
dist[j] = d;
idx[j] = j;
}
__syncthreads();
//odd-even sort
int pownum = int(log2(float(n)));
if ( n != pow(2, pownum) ){
for ( int cnt = 0 ; cnt < ( n + 1 ) / 2 ; ++cnt )
{
for ( int j = 2*threadIdx.x + 1 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
for ( int j = 2*threadIdx.x + 2 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
}
}else{
//Bitonic Sort
for (unsigned int t = 2; t <= n ; t *= 2)
{
// Bitonic merge:
for (unsigned int j = t / 2; j>0; j /= 2)
{
for (unsigned int tid = threadIdx.x ; tid < n ; tid += blockDim.x )
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & t) == 0)
{
if (dist[tid] > dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
else
{
if (dist[tid] < dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
}
}
__syncthreads();
}
}
}
__syncthreads();
//copy result
for ( int j = threadIdx.x ; j < k ; j += blockDim.x )
{
result[(bi*n+i)*k+j] = dist[j+1];
result_i[ ((bi*n+i)*k+j)*2+0 ] = bi;
result_i[ ((bi*n+i)*k+j)*2+1 ] = idx[j+1];
}
}
}
}
void KnnKernelLauncher(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
KnnKernel<<<dim3(b,16,1),512>>>(b,n,d,xyz,k,result,result_i);
}
#endif | .file "tmpxft_0000aa1d_00000000-6_group.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include <cassert>
__device__ inline void swapf(float & a, float & b)
{
float tmp = a;
a = b;
b = tmp;
}
__device__ inline void swap(int & a, int & b)
{
int tmp = a;
a = b ;
b = tmp;
}
__global__ void KnnKernel(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
const int size = 4096;
__shared__ float dist[size];
__shared__ int idx[size];
assert( n <= size );
for ( int bi = blockIdx.x ; bi < b ; bi += gridDim.x )
{
for ( int i = blockIdx.y ; i < n ; i += gridDim.y )
{
for ( int j = threadIdx.x ; j < n ; j += blockDim.x )
{
if( i == j ){
dist[j] = 0;
idx[j] = j;
continue;
}
float d = 0.0;
for ( int di = 0 ; di < d ; ++di )
{
float dif = xyz[(bi*n+i)*3+di] - xyz[(bi*n+j)*3+di];
d += dif*dif;
}
dist[j] = d;
idx[j] = j;
}
__syncthreads();
//odd-even sort
int pownum = int(log2(float(n)));
if ( n != pow(2, pownum) ){
for ( int cnt = 0 ; cnt < ( n + 1 ) / 2 ; ++cnt )
{
for ( int j = 2*threadIdx.x + 1 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
for ( int j = 2*threadIdx.x + 2 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
}
}else{
//Bitonic Sort
for (unsigned int t = 2; t <= n ; t *= 2)
{
// Bitonic merge:
for (unsigned int j = t / 2; j>0; j /= 2)
{
for (unsigned int tid = threadIdx.x ; tid < n ; tid += blockDim.x )
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & t) == 0)
{
if (dist[tid] > dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
else
{
if (dist[tid] < dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
}
}
__syncthreads();
}
}
}
__syncthreads();
//copy result
for ( int j = threadIdx.x ; j < k ; j += blockDim.x )
{
result[(bi*n+i)*k+j] = dist[j+1];
result_i[ ((bi*n+i)*k+j)*2+0 ] = bi;
result_i[ ((bi*n+i)*k+j)*2+1 ] = idx[j+1];
}
}
}
}
void KnnKernelLauncher(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
KnnKernel<<<dim3(b,16,1),512>>>(b,n,d,xyz,k,result,result_i);
}
#endif | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include <hip/hip_runtime.h>
#include <cassert>
__device__ inline void swapf(float & a, float & b)
{
float tmp = a;
a = b;
b = tmp;
}
__device__ inline void swap(int & a, int & b)
{
int tmp = a;
a = b ;
b = tmp;
}
__global__ void KnnKernel(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
const int size = 4096;
__shared__ float dist[size];
__shared__ int idx[size];
assert( n <= size );
for ( int bi = blockIdx.x ; bi < b ; bi += gridDim.x )
{
for ( int i = blockIdx.y ; i < n ; i += gridDim.y )
{
for ( int j = threadIdx.x ; j < n ; j += blockDim.x )
{
if( i == j ){
dist[j] = 0;
idx[j] = j;
continue;
}
float d = 0.0;
for ( int di = 0 ; di < d ; ++di )
{
float dif = xyz[(bi*n+i)*3+di] - xyz[(bi*n+j)*3+di];
d += dif*dif;
}
dist[j] = d;
idx[j] = j;
}
__syncthreads();
//odd-even sort
int pownum = int(log2(float(n)));
if ( n != pow(2, pownum) ){
for ( int cnt = 0 ; cnt < ( n + 1 ) / 2 ; ++cnt )
{
for ( int j = 2*threadIdx.x + 1 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
for ( int j = 2*threadIdx.x + 2 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
}
}else{
//Bitonic Sort
for (unsigned int t = 2; t <= n ; t *= 2)
{
// Bitonic merge:
for (unsigned int j = t / 2; j>0; j /= 2)
{
for (unsigned int tid = threadIdx.x ; tid < n ; tid += blockDim.x )
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & t) == 0)
{
if (dist[tid] > dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
else
{
if (dist[tid] < dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
}
}
__syncthreads();
}
}
}
__syncthreads();
//copy result
for ( int j = threadIdx.x ; j < k ; j += blockDim.x )
{
result[(bi*n+i)*k+j] = dist[j+1];
result_i[ ((bi*n+i)*k+j)*2+0 ] = bi;
result_i[ ((bi*n+i)*k+j)*2+1 ] = idx[j+1];
}
}
}
}
void KnnKernelLauncher(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
KnnKernel<<<dim3(b,16,1),512>>>(b,n,d,xyz,k,result,result_i);
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include <hip/hip_runtime.h>
#include <cassert>
__device__ inline void swapf(float & a, float & b)
{
float tmp = a;
a = b;
b = tmp;
}
__device__ inline void swap(int & a, int & b)
{
int tmp = a;
a = b ;
b = tmp;
}
__global__ void KnnKernel(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
const int size = 4096;
__shared__ float dist[size];
__shared__ int idx[size];
assert( n <= size );
for ( int bi = blockIdx.x ; bi < b ; bi += gridDim.x )
{
for ( int i = blockIdx.y ; i < n ; i += gridDim.y )
{
for ( int j = threadIdx.x ; j < n ; j += blockDim.x )
{
if( i == j ){
dist[j] = 0;
idx[j] = j;
continue;
}
float d = 0.0;
for ( int di = 0 ; di < d ; ++di )
{
float dif = xyz[(bi*n+i)*3+di] - xyz[(bi*n+j)*3+di];
d += dif*dif;
}
dist[j] = d;
idx[j] = j;
}
__syncthreads();
//odd-even sort
int pownum = int(log2(float(n)));
if ( n != pow(2, pownum) ){
for ( int cnt = 0 ; cnt < ( n + 1 ) / 2 ; ++cnt )
{
for ( int j = 2*threadIdx.x + 1 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
for ( int j = 2*threadIdx.x + 2 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
}
}else{
//Bitonic Sort
for (unsigned int t = 2; t <= n ; t *= 2)
{
// Bitonic merge:
for (unsigned int j = t / 2; j>0; j /= 2)
{
for (unsigned int tid = threadIdx.x ; tid < n ; tid += blockDim.x )
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & t) == 0)
{
if (dist[tid] > dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
else
{
if (dist[tid] < dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
}
}
__syncthreads();
}
}
}
__syncthreads();
//copy result
for ( int j = threadIdx.x ; j < k ; j += blockDim.x )
{
result[(bi*n+i)*k+j] = dist[j+1];
result_i[ ((bi*n+i)*k+j)*2+0 ] = bi;
result_i[ ((bi*n+i)*k+j)*2+1 ] = idx[j+1];
}
}
}
}
void KnnKernelLauncher(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
KnnKernel<<<dim3(b,16,1),512>>>(b,n,d,xyz,k,result,result_i);
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #if GOOGLE_CUDA
#define EIGEN_USE_GPU
#include <hip/hip_runtime.h>
#include <cassert>
__device__ inline void swapf(float & a, float & b)
{
float tmp = a;
a = b;
b = tmp;
}
__device__ inline void swap(int & a, int & b)
{
int tmp = a;
a = b ;
b = tmp;
}
__global__ void KnnKernel(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
const int size = 4096;
__shared__ float dist[size];
__shared__ int idx[size];
assert( n <= size );
for ( int bi = blockIdx.x ; bi < b ; bi += gridDim.x )
{
for ( int i = blockIdx.y ; i < n ; i += gridDim.y )
{
for ( int j = threadIdx.x ; j < n ; j += blockDim.x )
{
if( i == j ){
dist[j] = 0;
idx[j] = j;
continue;
}
float d = 0.0;
for ( int di = 0 ; di < d ; ++di )
{
float dif = xyz[(bi*n+i)*3+di] - xyz[(bi*n+j)*3+di];
d += dif*dif;
}
dist[j] = d;
idx[j] = j;
}
__syncthreads();
//odd-even sort
int pownum = int(log2(float(n)));
if ( n != pow(2, pownum) ){
for ( int cnt = 0 ; cnt < ( n + 1 ) / 2 ; ++cnt )
{
for ( int j = 2*threadIdx.x + 1 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
for ( int j = 2*threadIdx.x + 2 ; j < n ; j += 2*blockDim.x )
{
if ( dist[j] < dist[ j - 1 ] )
{
swapf(dist[j], dist[j-1]);
swap(idx[j], idx[j-1]);
}
}
__syncthreads();
}
}else{
//Bitonic Sort
for (unsigned int t = 2; t <= n ; t *= 2)
{
// Bitonic merge:
for (unsigned int j = t / 2; j>0; j /= 2)
{
for (unsigned int tid = threadIdx.x ; tid < n ; tid += blockDim.x )
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & t) == 0)
{
if (dist[tid] > dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
else
{
if (dist[tid] < dist[ixj])
{
swapf(dist[tid], dist[ixj]);
swap(idx[tid], idx[ixj]);
}
}
}
}
__syncthreads();
}
}
}
__syncthreads();
//copy result
for ( int j = threadIdx.x ; j < k ; j += blockDim.x )
{
result[(bi*n+i)*k+j] = dist[j+1];
result_i[ ((bi*n+i)*k+j)*2+0 ] = bi;
result_i[ ((bi*n+i)*k+j)*2+1 ] = idx[j+1];
}
}
}
}
void KnnKernelLauncher(int b,const int n,const int d,const float * xyz,const int k,float * result,int * result_i){
KnnKernel<<<dim3(b,16,1),512>>>(b,n,d,xyz,k,result,result_i);
}
#endif | .text
.file "group.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000aa1d_00000000-6_group.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "group.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include "cuComplex.h"
#define WARP_SIZE 32
// Kernel that executes on the CUDA device
template <int N>
__global__ void test(float *in, float *mul, float *out)
{
int lane_id = threadIdx.x % WARP_SIZE;
int warp_id = threadIdx.x / WARP_SIZE;
__shared__ float smem [WARP_SIZE*2];
volatile float* my_smem = &smem[WARP_SIZE*warp_id];
__shared__ float smul[N];
my_smem[lane_id] = in[lane_id];
if (lane_id < N)
smul[lane_id] = mul[lane_id];
my_smem[lane_id] = smul[lane_id%N] * my_smem[lane_id];
out[lane_id] = my_smem[lane_id];
}
// main routine that executes on the host
int main(void)
{
const int N = 8; // Number of elements in arrays
size_t elems = 256;
size_t size = elems * sizeof(float);
float* in_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
float* mul_h = (float*)calloc(N, sizeof(float));
float* out_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
for (int i = 0; i < elems; i++)
{
in_h[i] = (float)i;
}
for (int i = 0; i < N; i++)
{
mul_h[i] = 1.f;
}
float *in_d, *out_d, *mul_d;
cudaMalloc((void **) &in_d, size); // Allocate array on device
cudaMalloc((void **) &out_d, size); // Allocate array on device
cudaMalloc((void **) &mul_d, N*sizeof(float)); // Allocate array on device
cudaMemcpy(in_d, in_h, size, cudaMemcpyDefault);
cudaMemcpy(out_d, out_h, size, cudaMemcpyDefault);
cudaMemcpy(mul_d, mul_h, N*sizeof(float), cudaMemcpyDefault);
cudaDeviceSynchronize();
{
test<N> <<< 1, WARP_SIZE >>> (in_d, mul_d, out_d);
cudaDeviceSynchronize();
cudaMemcpy(out_h, out_d, WARP_SIZE*sizeof(float), cudaMemcpyDefault);
cudaDeviceSynchronize();
float expected = 0.0, got = 0.0, test = 0.0;
for (int j = 0; j < 32; j++)
{
expected += in_h[j]*mul_h[j%N];
got += out_h[j];
}
// Print results
printf("sz: %d, Expected: %f, Got: %f\n", 32, expected, got);
}
// Cleanup
free(in_h);
free(mul_h);
free(out_h);
cudaFree(in_d);
cudaFree(out_d);
cudaFree(mul_d);
return 0;
} | code for sm_80
Function : _Z4testILi8EEvPfS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ LOP3.LUT R0, R10.reuse, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0a007812 */
/* 0x041fe200078ec0ff */
/*0040*/ IMAD.SHL.U32 R6, R10, 0x4, RZ ; /* 0x000000040a067824 */
/* 0x000fc600078e00ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fe40003f04070 */
/*0060*/ LOP3.LUT R2, R6, 0x7c, RZ, 0xc0, !PT ; /* 0x0000007c06027812 */
/* 0x000fc800078ec0ff */
/*0070*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fca0007f3e0ff */
/*0080*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff037624 */
/* 0x000fe400008e06ff */
/*0090*/ @!P0 LEA R4, P2, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000048a11 */
/* 0x000fc600078410ff */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ @!P0 IMAD.X R5, RZ, RZ, c[0x0][0x16c], P2 ; /* 0x00005b00ff058624 */
/* 0x000fcc00010e06ff */
/*00c0*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000404058981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ LOP3.LUT R8, R6, 0x1c, RZ, 0xc0, !PT ; /* 0x0000001c06087812 */
/* 0x000fc600078ec0ff */
/*00e0*/ STS [R10.X4], R2 ; /* 0x000000020a007388 */
/* 0x004fe80000004800 */
/*00f0*/ @!P0 STS [R0.X4+0x100], R5 ; /* 0x0001000500008388 */
/* 0x008fe80000004800 */
/*0100*/ LDS R7, [R8+0x100] ; /* 0x0001000008077984 */
/* 0x000fe80000000800 */
/*0110*/ LDS R6, [R10.X4] ; /* 0x000000000a067984 */
/* 0x000e240000004800 */
/*0120*/ FMUL R9, R6, R7 ; /* 0x0000000706097220 */
/* 0x001fca0000400000 */
/*0130*/ STS [R10.X4], R9 ; /* 0x000000090a007388 */
/* 0x000fe80000004800 */
/*0140*/ LDS R11, [R10.X4] ; /* 0x000000000a0b7984 */
/* 0x000e220000004800 */
/*0150*/ LEA R6, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000067a11 */
/* 0x000fca00078010ff */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff077624 */
/* 0x000fca00000e06ff */
/*0170*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x001fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include "cuComplex.h"
#define WARP_SIZE 32
// Kernel that executes on the CUDA device
template <int N>
__global__ void test(float *in, float *mul, float *out)
{
int lane_id = threadIdx.x % WARP_SIZE;
int warp_id = threadIdx.x / WARP_SIZE;
__shared__ float smem [WARP_SIZE*2];
volatile float* my_smem = &smem[WARP_SIZE*warp_id];
__shared__ float smul[N];
my_smem[lane_id] = in[lane_id];
if (lane_id < N)
smul[lane_id] = mul[lane_id];
my_smem[lane_id] = smul[lane_id%N] * my_smem[lane_id];
out[lane_id] = my_smem[lane_id];
}
// main routine that executes on the host
int main(void)
{
const int N = 8; // Number of elements in arrays
size_t elems = 256;
size_t size = elems * sizeof(float);
float* in_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
float* mul_h = (float*)calloc(N, sizeof(float));
float* out_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
for (int i = 0; i < elems; i++)
{
in_h[i] = (float)i;
}
for (int i = 0; i < N; i++)
{
mul_h[i] = 1.f;
}
float *in_d, *out_d, *mul_d;
cudaMalloc((void **) &in_d, size); // Allocate array on device
cudaMalloc((void **) &out_d, size); // Allocate array on device
cudaMalloc((void **) &mul_d, N*sizeof(float)); // Allocate array on device
cudaMemcpy(in_d, in_h, size, cudaMemcpyDefault);
cudaMemcpy(out_d, out_h, size, cudaMemcpyDefault);
cudaMemcpy(mul_d, mul_h, N*sizeof(float), cudaMemcpyDefault);
cudaDeviceSynchronize();
{
test<N> <<< 1, WARP_SIZE >>> (in_d, mul_d, out_d);
cudaDeviceSynchronize();
cudaMemcpy(out_h, out_d, WARP_SIZE*sizeof(float), cudaMemcpyDefault);
cudaDeviceSynchronize();
float expected = 0.0, got = 0.0, test = 0.0;
for (int j = 0; j < 32; j++)
{
expected += in_h[j]*mul_h[j%N];
got += out_h[j];
}
// Print results
printf("sz: %d, Expected: %f, Got: %f\n", 32, expected, got);
}
// Cleanup
free(in_h);
free(mul_h);
free(out_h);
cudaFree(in_d);
cudaFree(out_d);
cudaFree(mul_d);
return 0;
} | .file "tmpxft_00059720_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z4testILi8EEvPfS0_S0_,"axG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.weak _Z4testILi8EEvPfS0_S0_
.type _Z4testILi8EEvPfS0_S0_, @function
_Z4testILi8EEvPfS0_S0_:
.LFB2156:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4testILi8EEvPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2156:
.size _Z4testILi8EEvPfS0_S0_, .-_Z4testILi8EEvPfS0_S0_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "sz: %d, Expected: %f, Got: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2082:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $256, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $8, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $256, %edi
call calloc@PLT
movq %rax, %r12
movl $0, %eax
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L10
movq %rbp, %rax
leaq 32(%rbp), %rdx
movss .LC1(%rip), %xmm0
.L11:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L11
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $4, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %ecx
movl $1024, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %ecx
movl $32, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
movl $4, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %edx
pxor %xmm1, %xmm1
movaps %xmm1, %xmm2
.L13:
movl %edx, %ecx
sarl $31, %ecx
shrl $29, %ecx
leal (%rcx,%rdx), %eax
andl $7, %eax
subl %ecx, %eax
cltq
movss 0(%rbp,%rax,4), %xmm0
mulss (%rbx,%rdx,4), %xmm0
addss %xmm0, %xmm2
addss (%r12,%rdx,4), %xmm1
addq $1, %rdx
cmpq $32, %rdx
jne .L13
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z4testILi8EEvPfS0_S0_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z4testILi8EEvPfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testILi8EEvPfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include "cuComplex.h"
#define WARP_SIZE 32
// Kernel that executes on the CUDA device
template <int N>
__global__ void test(float *in, float *mul, float *out)
{
int lane_id = threadIdx.x % WARP_SIZE;
int warp_id = threadIdx.x / WARP_SIZE;
__shared__ float smem [WARP_SIZE*2];
volatile float* my_smem = &smem[WARP_SIZE*warp_id];
__shared__ float smul[N];
my_smem[lane_id] = in[lane_id];
if (lane_id < N)
smul[lane_id] = mul[lane_id];
my_smem[lane_id] = smul[lane_id%N] * my_smem[lane_id];
out[lane_id] = my_smem[lane_id];
}
// main routine that executes on the host
int main(void)
{
const int N = 8; // Number of elements in arrays
size_t elems = 256;
size_t size = elems * sizeof(float);
float* in_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
float* mul_h = (float*)calloc(N, sizeof(float));
float* out_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
for (int i = 0; i < elems; i++)
{
in_h[i] = (float)i;
}
for (int i = 0; i < N; i++)
{
mul_h[i] = 1.f;
}
float *in_d, *out_d, *mul_d;
cudaMalloc((void **) &in_d, size); // Allocate array on device
cudaMalloc((void **) &out_d, size); // Allocate array on device
cudaMalloc((void **) &mul_d, N*sizeof(float)); // Allocate array on device
cudaMemcpy(in_d, in_h, size, cudaMemcpyDefault);
cudaMemcpy(out_d, out_h, size, cudaMemcpyDefault);
cudaMemcpy(mul_d, mul_h, N*sizeof(float), cudaMemcpyDefault);
cudaDeviceSynchronize();
{
test<N> <<< 1, WARP_SIZE >>> (in_d, mul_d, out_d);
cudaDeviceSynchronize();
cudaMemcpy(out_h, out_d, WARP_SIZE*sizeof(float), cudaMemcpyDefault);
cudaDeviceSynchronize();
float expected = 0.0, got = 0.0, test = 0.0;
for (int j = 0; j < 32; j++)
{
expected += in_h[j]*mul_h[j%N];
got += out_h[j];
}
// Print results
printf("sz: %d, Expected: %f, Got: %f\n", 32, expected, got);
}
// Cleanup
free(in_h);
free(mul_h);
free(out_h);
cudaFree(in_d);
cudaFree(out_d);
cudaFree(mul_d);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include "hip/hip_complex.h"
#define WARP_SIZE 32
// Kernel that executes on the CUDA device
template <int N>
__global__ void test(float *in, float *mul, float *out)
{
int lane_id = threadIdx.x % WARP_SIZE;
int warp_id = threadIdx.x / WARP_SIZE;
__shared__ float smem [WARP_SIZE*2];
volatile float* my_smem = &smem[WARP_SIZE*warp_id];
__shared__ float smul[N];
my_smem[lane_id] = in[lane_id];
if (lane_id < N)
smul[lane_id] = mul[lane_id];
my_smem[lane_id] = smul[lane_id%N] * my_smem[lane_id];
out[lane_id] = my_smem[lane_id];
}
// main routine that executes on the host
int main(void)
{
const int N = 8; // Number of elements in arrays
size_t elems = 256;
size_t size = elems * sizeof(float);
float* in_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
float* mul_h = (float*)calloc(N, sizeof(float));
float* out_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
for (int i = 0; i < elems; i++)
{
in_h[i] = (float)i;
}
for (int i = 0; i < N; i++)
{
mul_h[i] = 1.f;
}
float *in_d, *out_d, *mul_d;
hipMalloc((void **) &in_d, size); // Allocate array on device
hipMalloc((void **) &out_d, size); // Allocate array on device
hipMalloc((void **) &mul_d, N*sizeof(float)); // Allocate array on device
hipMemcpy(in_d, in_h, size, hipMemcpyDefault);
hipMemcpy(out_d, out_h, size, hipMemcpyDefault);
hipMemcpy(mul_d, mul_h, N*sizeof(float), hipMemcpyDefault);
hipDeviceSynchronize();
{
test<N> <<< 1, WARP_SIZE >>> (in_d, mul_d, out_d);
hipDeviceSynchronize();
hipMemcpy(out_h, out_d, WARP_SIZE*sizeof(float), hipMemcpyDefault);
hipDeviceSynchronize();
float expected = 0.0, got = 0.0, test = 0.0;
for (int j = 0; j < 32; j++)
{
expected += in_h[j]*mul_h[j%N];
got += out_h[j];
}
// Print results
printf("sz: %d, Expected: %f, Got: %f\n", 32, expected, got);
}
// Cleanup
free(in_h);
free(mul_h);
free(out_h);
hipFree(in_d);
hipFree(out_d);
hipFree(mul_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include "hip/hip_complex.h"
#define WARP_SIZE 32
// Kernel that executes on the CUDA device
template <int N>
__global__ void test(float *in, float *mul, float *out)
{
int lane_id = threadIdx.x % WARP_SIZE;
int warp_id = threadIdx.x / WARP_SIZE;
__shared__ float smem [WARP_SIZE*2];
volatile float* my_smem = &smem[WARP_SIZE*warp_id];
__shared__ float smul[N];
my_smem[lane_id] = in[lane_id];
if (lane_id < N)
smul[lane_id] = mul[lane_id];
my_smem[lane_id] = smul[lane_id%N] * my_smem[lane_id];
out[lane_id] = my_smem[lane_id];
}
// main routine that executes on the host
int main(void)
{
const int N = 8; // Number of elements in arrays
size_t elems = 256;
size_t size = elems * sizeof(float);
float* in_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
float* mul_h = (float*)calloc(N, sizeof(float));
float* out_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
for (int i = 0; i < elems; i++)
{
in_h[i] = (float)i;
}
for (int i = 0; i < N; i++)
{
mul_h[i] = 1.f;
}
float *in_d, *out_d, *mul_d;
hipMalloc((void **) &in_d, size); // Allocate array on device
hipMalloc((void **) &out_d, size); // Allocate array on device
hipMalloc((void **) &mul_d, N*sizeof(float)); // Allocate array on device
hipMemcpy(in_d, in_h, size, hipMemcpyDefault);
hipMemcpy(out_d, out_h, size, hipMemcpyDefault);
hipMemcpy(mul_d, mul_h, N*sizeof(float), hipMemcpyDefault);
hipDeviceSynchronize();
{
test<N> <<< 1, WARP_SIZE >>> (in_d, mul_d, out_d);
hipDeviceSynchronize();
hipMemcpy(out_h, out_d, WARP_SIZE*sizeof(float), hipMemcpyDefault);
hipDeviceSynchronize();
float expected = 0.0, got = 0.0, test = 0.0;
for (int j = 0; j < 32; j++)
{
expected += in_h[j]*mul_h[j%N];
got += out_h[j];
}
// Print results
printf("sz: %d, Expected: %f, Got: %f\n", 32, expected, got);
}
// Cleanup
free(in_h);
free(mul_h);
free(out_h);
hipFree(in_d);
hipFree(out_d);
hipFree(mul_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4testILi8EEvPfS0_S0_,"axG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.protected _Z4testILi8EEvPfS0_S0_
.globl _Z4testILi8EEvPfS0_S0_
.p2align 8
.type _Z4testILi8EEvPfS0_S0_,@function
_Z4testILi8EEvPfS0_S0_:
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v3, 31, v0
v_and_b32_e32 v2, 0x3e0, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v1, 2, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v1, s[2:3]
v_lshl_or_b32 v1, v2, 2, v1
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s3, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
v_cmpx_gt_u32_e32 8, v3
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v4, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5 offset:256
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v0, 7, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v0, v0 offset:256
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v0, v0, v4
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testILi8EEvPfS0_S0_
.amdhsa_group_segment_fixed_size 288
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4testILi8EEvPfS0_S0_,"axG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.Lfunc_end0:
.size _Z4testILi8EEvPfS0_S0_, .Lfunc_end0-_Z4testILi8EEvPfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 288
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testILi8EEvPfS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z4testILi8EEvPfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include "hip/hip_complex.h"
#define WARP_SIZE 32
// Kernel that executes on the CUDA device
template <int N>
__global__ void test(float *in, float *mul, float *out)
{
int lane_id = threadIdx.x % WARP_SIZE;
int warp_id = threadIdx.x / WARP_SIZE;
__shared__ float smem [WARP_SIZE*2];
volatile float* my_smem = &smem[WARP_SIZE*warp_id];
__shared__ float smul[N];
my_smem[lane_id] = in[lane_id];
if (lane_id < N)
smul[lane_id] = mul[lane_id];
my_smem[lane_id] = smul[lane_id%N] * my_smem[lane_id];
out[lane_id] = my_smem[lane_id];
}
// main routine that executes on the host
int main(void)
{
const int N = 8; // Number of elements in arrays
size_t elems = 256;
size_t size = elems * sizeof(float);
float* in_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
float* mul_h = (float*)calloc(N, sizeof(float));
float* out_h = (float*)calloc(elems, sizeof(float)); // Allocate array on host
for (int i = 0; i < elems; i++)
{
in_h[i] = (float)i;
}
for (int i = 0; i < N; i++)
{
mul_h[i] = 1.f;
}
float *in_d, *out_d, *mul_d;
hipMalloc((void **) &in_d, size); // Allocate array on device
hipMalloc((void **) &out_d, size); // Allocate array on device
hipMalloc((void **) &mul_d, N*sizeof(float)); // Allocate array on device
hipMemcpy(in_d, in_h, size, hipMemcpyDefault);
hipMemcpy(out_d, out_h, size, hipMemcpyDefault);
hipMemcpy(mul_d, mul_h, N*sizeof(float), hipMemcpyDefault);
hipDeviceSynchronize();
{
test<N> <<< 1, WARP_SIZE >>> (in_d, mul_d, out_d);
hipDeviceSynchronize();
hipMemcpy(out_h, out_d, WARP_SIZE*sizeof(float), hipMemcpyDefault);
hipDeviceSynchronize();
float expected = 0.0, got = 0.0, test = 0.0;
for (int j = 0; j < 32; j++)
{
expected += in_h[j]*mul_h[j%N];
got += out_h[j];
}
// Print results
printf("sz: %d, Expected: %f, Got: %f\n", 32, expected, got);
}
// Cleanup
free(in_h);
free(mul_h);
free(out_h);
hipFree(in_d);
hipFree(out_d);
hipFree(mul_d);
return 0;
} | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $8, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
movl $4, %esi
callq calloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB0_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $8, %rax
jne .LBB0_3
# %bb.4:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $4, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r15, %rsi
movl $4, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $32, %edx
movq %r14, %rsi
movl $4, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4testILi8EEvPfS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $4, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorps %xmm1, %xmm1
xorl %eax, %eax
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movl %eax, %ecx
andl $7, %ecx
mulss (%r14,%rcx,4), %xmm2
addss %xmm2, %xmm0
addss (%r15,%rax,4), %xmm1
incq %rax
cmpq $32, %rax
jne .LBB0_7
# %bb.8:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl $32, %esi
movb $2, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__testILi8EEvPfS0_S0_,"axG",@progbits,_Z19__device_stub__testILi8EEvPfS0_S0_,comdat
.weak _Z19__device_stub__testILi8EEvPfS0_S0_ # -- Begin function _Z19__device_stub__testILi8EEvPfS0_S0_
.p2align 4, 0x90
.type _Z19__device_stub__testILi8EEvPfS0_S0_,@function
_Z19__device_stub__testILi8EEvPfS0_S0_: # @_Z19__device_stub__testILi8EEvPfS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4testILi8EEvPfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z19__device_stub__testILi8EEvPfS0_S0_, .Lfunc_end1-_Z19__device_stub__testILi8EEvPfS0_S0_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testILi8EEvPfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testILi8EEvPfS0_S0_,@object # @_Z4testILi8EEvPfS0_S0_
.section .rodata._Z4testILi8EEvPfS0_S0_,"aG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.weak _Z4testILi8EEvPfS0_S0_
.p2align 3, 0x0
_Z4testILi8EEvPfS0_S0_:
.quad _Z19__device_stub__testILi8EEvPfS0_S0_
.size _Z4testILi8EEvPfS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sz: %d, Expected: %f, Got: %f\n"
.size .L.str, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testILi8EEvPfS0_S0_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testILi8EEvPfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testILi8EEvPfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testILi8EEvPfS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ LOP3.LUT R0, R10.reuse, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0a007812 */
/* 0x041fe200078ec0ff */
/*0040*/ IMAD.SHL.U32 R6, R10, 0x4, RZ ; /* 0x000000040a067824 */
/* 0x000fc600078e00ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fe40003f04070 */
/*0060*/ LOP3.LUT R2, R6, 0x7c, RZ, 0xc0, !PT ; /* 0x0000007c06027812 */
/* 0x000fc800078ec0ff */
/*0070*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fca0007f3e0ff */
/*0080*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff037624 */
/* 0x000fe400008e06ff */
/*0090*/ @!P0 LEA R4, P2, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000048a11 */
/* 0x000fc600078410ff */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ @!P0 IMAD.X R5, RZ, RZ, c[0x0][0x16c], P2 ; /* 0x00005b00ff058624 */
/* 0x000fcc00010e06ff */
/*00c0*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000404058981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ LOP3.LUT R8, R6, 0x1c, RZ, 0xc0, !PT ; /* 0x0000001c06087812 */
/* 0x000fc600078ec0ff */
/*00e0*/ STS [R10.X4], R2 ; /* 0x000000020a007388 */
/* 0x004fe80000004800 */
/*00f0*/ @!P0 STS [R0.X4+0x100], R5 ; /* 0x0001000500008388 */
/* 0x008fe80000004800 */
/*0100*/ LDS R7, [R8+0x100] ; /* 0x0001000008077984 */
/* 0x000fe80000000800 */
/*0110*/ LDS R6, [R10.X4] ; /* 0x000000000a067984 */
/* 0x000e240000004800 */
/*0120*/ FMUL R9, R6, R7 ; /* 0x0000000706097220 */
/* 0x001fca0000400000 */
/*0130*/ STS [R10.X4], R9 ; /* 0x000000090a007388 */
/* 0x000fe80000004800 */
/*0140*/ LDS R11, [R10.X4] ; /* 0x000000000a0b7984 */
/* 0x000e220000004800 */
/*0150*/ LEA R6, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000067a11 */
/* 0x000fca00078010ff */
/*0160*/ IMAD.X R7, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff077624 */
/* 0x000fca00000e06ff */
/*0170*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x001fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4testILi8EEvPfS0_S0_,"axG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.protected _Z4testILi8EEvPfS0_S0_
.globl _Z4testILi8EEvPfS0_S0_
.p2align 8
.type _Z4testILi8EEvPfS0_S0_,@function
_Z4testILi8EEvPfS0_S0_:
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v3, 31, v0
v_and_b32_e32 v2, 0x3e0, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v1, 2, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v1, s[2:3]
v_lshl_or_b32 v1, v2, 2, v1
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s3, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
v_cmpx_gt_u32_e32 8, v3
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 2, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v4, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5 offset:256
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v0, 7, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v0, v0 offset:256
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v0, v0, v4
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testILi8EEvPfS0_S0_
.amdhsa_group_segment_fixed_size 288
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4testILi8EEvPfS0_S0_,"axG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.Lfunc_end0:
.size _Z4testILi8EEvPfS0_S0_, .Lfunc_end0-_Z4testILi8EEvPfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 288
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testILi8EEvPfS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z4testILi8EEvPfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00059720_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z4testILi8EEvPfS0_S0_,"axG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.weak _Z4testILi8EEvPfS0_S0_
.type _Z4testILi8EEvPfS0_S0_, @function
_Z4testILi8EEvPfS0_S0_:
.LFB2156:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4testILi8EEvPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2156:
.size _Z4testILi8EEvPfS0_S0_, .-_Z4testILi8EEvPfS0_S0_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "sz: %d, Expected: %f, Got: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2082:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $256, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $8, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $256, %edi
call calloc@PLT
movq %rax, %r12
movl $0, %eax
.L10:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L10
movq %rbp, %rax
leaq 32(%rbp), %rdx
movss .LC1(%rip), %xmm0
.L11:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L11
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $4, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %ecx
movl $1024, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %ecx
movl $32, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
movl $4, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %edx
pxor %xmm1, %xmm1
movaps %xmm1, %xmm2
.L13:
movl %edx, %ecx
sarl $31, %ecx
shrl $29, %ecx
leal (%rcx,%rdx), %eax
andl $7, %eax
subl %ecx, %eax
cltq
movss 0(%rbp,%rax,4), %xmm0
mulss (%rbx,%rdx,4), %xmm0
addss %xmm0, %xmm2
addss (%r12,%rdx,4), %xmm1
addq $1, %rdx
cmpq $32, %rdx
jne .L13
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z4testILi8EEvPfS0_S0_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z4testILi8EEvPfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testILi8EEvPfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $8, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
movl $4, %esi
callq calloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB0_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $8, %rax
jne .LBB0_3
# %bb.4:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $4, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r15, %rsi
movl $4, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $32, %edx
movq %r14, %rsi
movl $4, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4testILi8EEvPfS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $128, %edx
movq %r15, %rdi
movl $4, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorps %xmm1, %xmm1
xorl %eax, %eax
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movl %eax, %ecx
andl $7, %ecx
mulss (%r14,%rcx,4), %xmm2
addss %xmm2, %xmm0
addss (%r15,%rax,4), %xmm1
incq %rax
cmpq $32, %rax
jne .LBB0_7
# %bb.8:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl $32, %esi
movb $2, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__testILi8EEvPfS0_S0_,"axG",@progbits,_Z19__device_stub__testILi8EEvPfS0_S0_,comdat
.weak _Z19__device_stub__testILi8EEvPfS0_S0_ # -- Begin function _Z19__device_stub__testILi8EEvPfS0_S0_
.p2align 4, 0x90
.type _Z19__device_stub__testILi8EEvPfS0_S0_,@function
_Z19__device_stub__testILi8EEvPfS0_S0_: # @_Z19__device_stub__testILi8EEvPfS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4testILi8EEvPfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z19__device_stub__testILi8EEvPfS0_S0_, .Lfunc_end1-_Z19__device_stub__testILi8EEvPfS0_S0_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testILi8EEvPfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testILi8EEvPfS0_S0_,@object # @_Z4testILi8EEvPfS0_S0_
.section .rodata._Z4testILi8EEvPfS0_S0_,"aG",@progbits,_Z4testILi8EEvPfS0_S0_,comdat
.weak _Z4testILi8EEvPfS0_S0_
.p2align 3, 0x0
_Z4testILi8EEvPfS0_S0_:
.quad _Z19__device_stub__testILi8EEvPfS0_S0_
.size _Z4testILi8EEvPfS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sz: %d, Expected: %f, Got: %f\n"
.size .L.str, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testILi8EEvPfS0_S0_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testILi8EEvPfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testILi8EEvPfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* CUDA API header files*/
extern "C"
__global__ void matrixMult(const double *Md, const double *Nd, double *Pd, int size)
{
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row < size) { // Don't do anything to the memory if we're above the size of the matrix
if (col < size) {
double Pvalue = 0;
for (int k = 0; k < size; k++) {
// Elements of 2d-arrays are stored in column-major ordering (i.e. column by column)
// This is a consequence of this code being called in R (where column-major ordering is the norm)
// whereas C usually stores 2d-array in row-major ordering
Pvalue += Md[k*size + row] * Nd[col*size + k];
}
Pd[col*size + row] = Pvalue;
}
}
} | code for sm_80
Function : matrixMult
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc10 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0100*/ HFMA2.MMA R26, -RZ, RZ, 0, 0 ; /* 0x00000000ff1a7435 */
/* 0x000fe200000001ff */
/*0110*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fd600078ec0ff */
/*0140*/ @!P0 BRA 0xad0 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD.MOV.U32 R28, RZ, RZ, 0x8 ; /* 0x00000008ff1c7424 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*01b0*/ IMAD.WIDE R6, R6, R28, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e021c */
/*01c0*/ IMAD.WIDE R28, R3, R28, c[0x0][0x160] ; /* 0x00005800031c7625 */
/* 0x000fcc00078e021c */
/*01d0*/ @!P0 BRA 0x950 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6a0 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0010a2000c1e1b00 */
/*0240*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fc600078e021c */
/*0250*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0260*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0270*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*0290*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x002322000c1e1b00 */
/*02a0*/ IMAD.WIDE R28, R2, 0x8, R22 ; /* 0x00000008021c7825 */
/* 0x001fca00078e0216 */
/*02b0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002162000c1e1b00 */
/*02c0*/ DFMA R18, R20, R10, R18 ; /* 0x0000000a1412722b */
/* 0x0042c60000000012 */
/*02d0*/ LDG.E.64 R10, [R6.64+0x18] ; /* 0x00001804060a7981 */
/* 0x002f62000c1e1b00 */
/*02e0*/ IMAD.WIDE R28, R2.reuse, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x041fe400078e021c */
/*02f0*/ DFMA R18, R16, R8, R18 ; /* 0x000000081012722b */
/* 0x0081240000000012 */
/*0300*/ LDG.E.64 R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x001ea8000c1e1b00 */
/*0310*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000ea2000c1e1b00 */
/*0320*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fe200078e021c */
/*0330*/ DFMA R18, R14, R12, R18 ; /* 0x0000000c0e12722b */
/* 0x0101440000000012 */
/*0340*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001ee8000c1e1b00 */
/*0350*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee2000c1e1b00 */
/*0360*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fe200078e0218 */
/*0370*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0200a40000000012 */
/*0380*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x00003004060a7981 */
/* 0x001f28000c1e1b00 */
/*0390*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000122000c1e1b00 */
/*03a0*/ DFMA R16, R8, R16, R22 ; /* 0x000000100810722b */
/* 0x0042c60000000016 */
/*03b0*/ LDG.E.64 R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x002ea2000c1e1b00 */
/*03c0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*03d0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IMAD.WIDE R28, R2.reuse, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x040fe200078e0214 */
/*03f0*/ DFMA R12, R14, R12, R16 ; /* 0x0000000c0e0c722b */
/* 0x0081240000000010 */
/*0400*/ LDG.E.64 R16, [R6.64+0x40] ; /* 0x0000400406107981 */
/* 0x001ee8000c1e1b00 */
/*0410*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ee2000c1e1b00 */
/*0420*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fe200078e021c */
/*0430*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x010084000000000c */
/*0440*/ LDG.E.64 R12, [R6.64+0x48] ; /* 0x00004804060c7981 */
/* 0x001f28000c1e1b00 */
/*0450*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000124000c1e1b00 */
/*0460*/ IMAD.WIDE R24, R2.reuse, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x041fe200078e0218 */
/*0470*/ DFMA R22, R8, R22, R18 ; /* 0x000000160816722b */
/* 0x0040e40000000012 */
/*0480*/ LDG.E.64 R8, [R6.64+0x50] ; /* 0x0000500406087981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fe200078e0218 */
/*04b0*/ DFMA R14, R16, R14, R22 ; /* 0x0000000e100e722b */
/* 0x0081040000000016 */
/*04c0*/ LDG.E.64 R16, [R6.64+0x58] ; /* 0x0000580406107981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ee2000c1e1b00 */
/*04e0*/ IMAD.WIDE R28, R2.reuse, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x040fe200078e0214 */
/*04f0*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0100a4000000000e */
/*0500*/ LDG.E.64 R14, [R6.64+0x60] ; /* 0x00006004060e7981 */
/* 0x001f28000c1e1b00 */
/*0510*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000124000c1e1b00 */
/*0520*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x001fe200078e021c */
/*0530*/ DFMA R18, R8, R18, R10 ; /* 0x000000120812722b */
/* 0x0040c4000000000a */
/*0540*/ LDG.E.64 R8, [R6.64+0x68] ; /* 0x0000680406087981 */
/* 0x001ea6000c1e1b00 */
/*0550*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fe200078e021c */
/*0560*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0570*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0081060000000012 */
/*0580*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001ee2000c1e1b00 */
/*0590*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fc600078e0218 */
/*05a0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ee2000c1e1b00 */
/*05b0*/ DFMA R22, R14, R12, R22 ; /* 0x0000000c0e16722b */
/* 0x0100860000000016 */
/*05c0*/ LDG.E.64 R12, [R6.64+0x78] ; /* 0x00007804060c7981 */
/* 0x001128000c1e1b00 */
/*05d0*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000f22000c1e1b00 */
/*05e0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0600*/ DFMA R8, R8, R10, R22 ; /* 0x0000000a0808722b */
/* 0x004ecc0000000016 */
/*0610*/ DFMA R18, R16, R18, R8 ; /* 0x000000121012722b */
/* 0x0083240000000008 */
/*0620*/ IADD3 R8, P2, R6, 0x80, RZ ; /* 0x0000008006087810 */
/* 0x002fc80007f5e0ff */
/*0630*/ IADD3.X R9, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff097210 */
/* 0x000fe200017fe4ff */
/*0640*/ IMAD.WIDE R28, R2, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0214 */
/*0650*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fe40007ffe0ff */
/*0660*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x001fe20000000f00 */
/*0670*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0680*/ DFMA R18, R12, R14, R18 ; /* 0x0000000e0c12722b */
/* 0x0100620000000012 */
/*0690*/ @P1 BRA 0x220 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x930 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*06d0*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x0010a2000c1e1b00 */
/*06e0*/ IMAD.WIDE R22, R2, 0x8, R28 ; /* 0x0000000802167825 */
/* 0x000fc600078e021c */
/*06f0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0700*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0008e8000c1e1b00 */
/*0710*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000f62000c1e1b00 */
/*0720*/ IMAD.WIDE R22, R2, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x010fca00078e0216 */
/*0730*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000f62000c1e1b00 */
/*0740*/ IMAD.WIDE R24, R2, 0x8, R22 ; /* 0x0000000802187825 */
/* 0x000fcc00078e0216 */
/*0750*/ IMAD.WIDE R28, R2, 0x8, R24 ; /* 0x00000008021c7825 */
/* 0x001fe200078e0218 */
/*0760*/ DFMA R18, R20, R12, R18 ; /* 0x0000000c1412722b */
/* 0x0060e40000000012 */
/*0770*/ LDG.E.64 R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0780*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x0000a2000c1e1b00 */
/*0790*/ DFMA R10, R16, R10, R18 ; /* 0x0000000a100a722b */
/* 0x0083460000000012 */
/*07a0*/ LDG.E.64 R16, [R6.64+0x20] ; /* 0x0000200406107981 */
/* 0x002ee8000c1e1b00 */
/*07b0*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0002e2000c1e1b00 */
/*07c0*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x0208a2000000000a */
/*07d0*/ IMAD.WIDE R28, R2.reuse, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x042fe400078e021c */
/*07e0*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x010f28000c1e1b00 */
/*07f0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000f22000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R28 ; /* 0x0000000802167825 */
/* 0x000fcc00078e021c */
/*0810*/ IMAD.WIDE R24, R2, 0x8, R22 ; /* 0x0000000802187825 */
/* 0x001fe200078e0216 */
/*0820*/ DFMA R20, R12, R20, R14 ; /* 0x000000140c14722b */
/* 0x0040e4000000000e */
/*0830*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x0010a8000c1e1b00 */
/*0840*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000ea2000c1e1b00 */
/*0850*/ DFMA R20, R16, R18, R20 ; /* 0x000000121014722b */
/* 0x0083060000000014 */
/*0860*/ LDG.E.64 R18, [R6.64+0x38] ; /* 0x0000380406127981 */
/* 0x0020e8000c1e1b00 */
/*0870*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000ee2000c1e1b00 */
/*0880*/ DFMA R8, R8, R10, R20 ; /* 0x0000000a0808722b */
/* 0x0102a40000000014 */
/*0890*/ IADD3 R10, P1, R6, 0x40, RZ ; /* 0x00000040060a7810 */
/* 0x002fc80007f3e0ff */
/*08a0*/ IADD3.X R11, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fe20000ffe4ff */
/*08b0*/ IMAD.WIDE R28, R2, 0x8, R24 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0218 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08d0*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000a */
/*08f0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0900*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0910*/ DFMA R8, R12, R14, R8 ; /* 0x0000000e0c08722b */
/* 0x004ecc0000000008 */
/*0920*/ DFMA R18, R18, R16, R8 ; /* 0x000000101212722b */
/* 0x0080480000000008 */
/*0930*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0940*/ @!P0 BRA 0xad0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0950*/ LDG.E.64 R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea8000c1e1b00 */
/*0960*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x001ea2000c1e1b00 */
/*0970*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fc600078e021c */
/*0980*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0990*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x0000e8000c1e1b00 */
/*09a0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f22000c1e1b00 */
/*09b0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*09c0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000f22000c1e1b00 */
/*09d0*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fe200078e0218 */
/*09e0*/ DFMA R22, R22, R8, R18 ; /* 0x000000081616722b */
/* 0x0060e40000000012 */
/*09f0*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x0010a8000c1e1b00 */
/*0a00*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea2000c1e1b00 */
/*0a10*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ DFMA R10, R10, R12, R22 ; /* 0x0000000c0a0a722b */
/* 0x0083060000000016 */
/*0a30*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0a40*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fc80007f3e0ff */
/*0a50*/ IADD3.X R13, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe20000ffe4ff */
/*0a60*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x010ea2000000000a */
/*0a70*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe20007ffe0ff */
/*0a80*/ IMAD.WIDE R28, R2, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0214 */
/*0a90*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fc60000000f00 */
/*0aa0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0ab0*/ DFMA R18, R18, R8, R10 ; /* 0x000000081212722b */
/* 0x004064000000000a */
/*0ac0*/ @P0 BRA 0x950 ; /* 0xfffffe8000000947 */
/* 0x003fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xc10 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fe200000001ff */
/*0b00*/ IMAD R6, R0, c[0x0][0x178], R26 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e021a */
/*0b10*/ IMAD R8, R26, c[0x0][0x178], R3 ; /* 0x00005e001a087a24 */
/* 0x000fce00078e0203 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*0b40*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe40000000f00 */
/*0b50*/ MOV R12, R7 ; /* 0x00000007000c7202 */
/* 0x000fc60000000f00 */
/*0b60*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe200078e0005 */
/*0b70*/ MOV R7, R12 ; /* 0x0000000c00077202 */
/* 0x000fe20000000f00 */
/*0b80*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000aa000c1e1b00 */
/*0b90*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0ba0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc40007ffe0ff */
/*0bb0*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f3e0ff */
/*0bc0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0bd0*/ IMAD.WIDE R8, R2, 0x8, R8 ; /* 0x0000000802087825 */
/* 0x001fe200078e0208 */
/*0be0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ DFMA R18, R6, R10, R18 ; /* 0x0000000a0612722b */
/* 0x0060540000000012 */
/*0c00*/ @P0 BRA 0xb60 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* CUDA API header files*/
extern "C"
__global__ void matrixMult(const double *Md, const double *Nd, double *Pd, int size)
{
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row < size) { // Don't do anything to the memory if we're above the size of the matrix
if (col < size) {
double Pvalue = 0;
for (int k = 0; k < size; k++) {
// Elements of 2d-arrays are stored in column-major ordering (i.e. column by column)
// This is a consequence of this code being called in R (where column-major ordering is the norm)
// whereas C usually stores 2d-array in row-major ordering
Pvalue += Md[k*size + row] * Nd[col*size + k];
}
Pd[col*size + row] = Pvalue;
}
}
} | .file "tmpxft_00183d07_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi
.type _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi, @function
_Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrixMult(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi, .-_Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi
.globl matrixMult
.type matrixMult, @function
matrixMult:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixMult, .-matrixMult
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixMult"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixMult(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* CUDA API header files*/
extern "C"
__global__ void matrixMult(const double *Md, const double *Nd, double *Pd, int size)
{
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row < size) { // Don't do anything to the memory if we're above the size of the matrix
if (col < size) {
double Pvalue = 0;
for (int k = 0; k < size; k++) {
// Elements of 2d-arrays are stored in column-major ordering (i.e. column by column)
// This is a consequence of this code being called in R (where column-major ordering is the norm)
// whereas C usually stores 2d-array in row-major ordering
Pvalue += Md[k*size + row] * Nd[col*size + k];
}
Pd[col*size + row] = Pvalue;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* CUDA API header files*/
extern "C"
__global__ void matrixMult(const double *Md, const double *Nd, double *Pd, int size)
{
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row < size) { // Don't do anything to the memory if we're above the size of the matrix
if (col < size) {
double Pvalue = 0;
for (int k = 0; k < size; k++) {
// Elements of 2d-arrays are stored in column-major ordering (i.e. column by column)
// This is a consequence of this code being called in R (where column-major ordering is the norm)
// whereas C usually stores 2d-array in row-major ordering
Pvalue += Md[k*size + row] * Nd[col*size + k];
}
Pd[col*size + row] = Pvalue;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* CUDA API header files*/
extern "C"
__global__ void matrixMult(const double *Md, const double *Nd, double *Pd, int size)
{
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row < size) { // Don't do anything to the memory if we're above the size of the matrix
if (col < size) {
double Pvalue = 0;
for (int k = 0; k < size; k++) {
// Elements of 2d-arrays are stored in column-major ordering (i.e. column by column)
// This is a consequence of this code being called in R (where column-major ordering is the norm)
// whereas C usually stores 2d-array in row-major ordering
Pvalue += Md[k*size + row] * Nd[col*size + k];
}
Pd[col*size + row] = Pvalue;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixMult
.globl matrixMult
.p2align 8
.type matrixMult,@function
matrixMult:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], v[9:10], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixMult
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixMult, .Lfunc_end0-matrixMult
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixMult
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixMult.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* CUDA API header files*/
extern "C"
__global__ void matrixMult(const double *Md, const double *Nd, double *Pd, int size)
{
int row = blockDim.x * blockIdx.x + threadIdx.x;
int col = blockDim.y * blockIdx.y + threadIdx.y;
if (row < size) { // Don't do anything to the memory if we're above the size of the matrix
if (col < size) {
double Pvalue = 0;
for (int k = 0; k < size; k++) {
// Elements of 2d-arrays are stored in column-major ordering (i.e. column by column)
// This is a consequence of this code being called in R (where column-major ordering is the norm)
// whereas C usually stores 2d-array in row-major ordering
Pvalue += Md[k*size + row] * Nd[col*size + k];
}
Pd[col*size + row] = Pvalue;
}
}
} | .text
.file "matrixMult.hip"
.globl __device_stub__matrixMult # -- Begin function __device_stub__matrixMult
.p2align 4, 0x90
.type __device_stub__matrixMult,@function
__device_stub__matrixMult: # @__device_stub__matrixMult
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrixMult, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__matrixMult, .Lfunc_end0-__device_stub__matrixMult
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixMult, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixMult,@object # @matrixMult
.section .rodata,"a",@progbits
.globl matrixMult
.p2align 3, 0x0
matrixMult:
.quad __device_stub__matrixMult
.size matrixMult, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixMult"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixMult
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixMult
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : matrixMult
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc10 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0100*/ HFMA2.MMA R26, -RZ, RZ, 0, 0 ; /* 0x00000000ff1a7435 */
/* 0x000fe200000001ff */
/*0110*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fd600078ec0ff */
/*0140*/ @!P0 BRA 0xad0 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD.MOV.U32 R28, RZ, RZ, 0x8 ; /* 0x00000008ff1c7424 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*01b0*/ IMAD.WIDE R6, R6, R28, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e021c */
/*01c0*/ IMAD.WIDE R28, R3, R28, c[0x0][0x160] ; /* 0x00005800031c7625 */
/* 0x000fcc00078e021c */
/*01d0*/ @!P0 BRA 0x950 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6a0 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0010a2000c1e1b00 */
/*0240*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fc600078e021c */
/*0250*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0260*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0270*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*0290*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x002322000c1e1b00 */
/*02a0*/ IMAD.WIDE R28, R2, 0x8, R22 ; /* 0x00000008021c7825 */
/* 0x001fca00078e0216 */
/*02b0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002162000c1e1b00 */
/*02c0*/ DFMA R18, R20, R10, R18 ; /* 0x0000000a1412722b */
/* 0x0042c60000000012 */
/*02d0*/ LDG.E.64 R10, [R6.64+0x18] ; /* 0x00001804060a7981 */
/* 0x002f62000c1e1b00 */
/*02e0*/ IMAD.WIDE R28, R2.reuse, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x041fe400078e021c */
/*02f0*/ DFMA R18, R16, R8, R18 ; /* 0x000000081012722b */
/* 0x0081240000000012 */
/*0300*/ LDG.E.64 R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x001ea8000c1e1b00 */
/*0310*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000ea2000c1e1b00 */
/*0320*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fe200078e021c */
/*0330*/ DFMA R18, R14, R12, R18 ; /* 0x0000000c0e12722b */
/* 0x0101440000000012 */
/*0340*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001ee8000c1e1b00 */
/*0350*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee2000c1e1b00 */
/*0360*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fe200078e0218 */
/*0370*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0200a40000000012 */
/*0380*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x00003004060a7981 */
/* 0x001f28000c1e1b00 */
/*0390*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000122000c1e1b00 */
/*03a0*/ DFMA R16, R8, R16, R22 ; /* 0x000000100810722b */
/* 0x0042c60000000016 */
/*03b0*/ LDG.E.64 R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x002ea2000c1e1b00 */
/*03c0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*03d0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IMAD.WIDE R28, R2.reuse, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x040fe200078e0214 */
/*03f0*/ DFMA R12, R14, R12, R16 ; /* 0x0000000c0e0c722b */
/* 0x0081240000000010 */
/*0400*/ LDG.E.64 R16, [R6.64+0x40] ; /* 0x0000400406107981 */
/* 0x001ee8000c1e1b00 */
/*0410*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ee2000c1e1b00 */
/*0420*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fe200078e021c */
/*0430*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x010084000000000c */
/*0440*/ LDG.E.64 R12, [R6.64+0x48] ; /* 0x00004804060c7981 */
/* 0x001f28000c1e1b00 */
/*0450*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000124000c1e1b00 */
/*0460*/ IMAD.WIDE R24, R2.reuse, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x041fe200078e0218 */
/*0470*/ DFMA R22, R8, R22, R18 ; /* 0x000000160816722b */
/* 0x0040e40000000012 */
/*0480*/ LDG.E.64 R8, [R6.64+0x50] ; /* 0x0000500406087981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fe200078e0218 */
/*04b0*/ DFMA R14, R16, R14, R22 ; /* 0x0000000e100e722b */
/* 0x0081040000000016 */
/*04c0*/ LDG.E.64 R16, [R6.64+0x58] ; /* 0x0000580406107981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ee2000c1e1b00 */
/*04e0*/ IMAD.WIDE R28, R2.reuse, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x040fe200078e0214 */
/*04f0*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0100a4000000000e */
/*0500*/ LDG.E.64 R14, [R6.64+0x60] ; /* 0x00006004060e7981 */
/* 0x001f28000c1e1b00 */
/*0510*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000124000c1e1b00 */
/*0520*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x001fe200078e021c */
/*0530*/ DFMA R18, R8, R18, R10 ; /* 0x000000120812722b */
/* 0x0040c4000000000a */
/*0540*/ LDG.E.64 R8, [R6.64+0x68] ; /* 0x0000680406087981 */
/* 0x001ea6000c1e1b00 */
/*0550*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fe200078e021c */
/*0560*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0570*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0081060000000012 */
/*0580*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001ee2000c1e1b00 */
/*0590*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fc600078e0218 */
/*05a0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ee2000c1e1b00 */
/*05b0*/ DFMA R22, R14, R12, R22 ; /* 0x0000000c0e16722b */
/* 0x0100860000000016 */
/*05c0*/ LDG.E.64 R12, [R6.64+0x78] ; /* 0x00007804060c7981 */
/* 0x001128000c1e1b00 */
/*05d0*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000f22000c1e1b00 */
/*05e0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0600*/ DFMA R8, R8, R10, R22 ; /* 0x0000000a0808722b */
/* 0x004ecc0000000016 */
/*0610*/ DFMA R18, R16, R18, R8 ; /* 0x000000121012722b */
/* 0x0083240000000008 */
/*0620*/ IADD3 R8, P2, R6, 0x80, RZ ; /* 0x0000008006087810 */
/* 0x002fc80007f5e0ff */
/*0630*/ IADD3.X R9, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff097210 */
/* 0x000fe200017fe4ff */
/*0640*/ IMAD.WIDE R28, R2, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0214 */
/*0650*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fe40007ffe0ff */
/*0660*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x001fe20000000f00 */
/*0670*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0680*/ DFMA R18, R12, R14, R18 ; /* 0x0000000e0c12722b */
/* 0x0100620000000012 */
/*0690*/ @P1 BRA 0x220 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x930 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*06d0*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x0010a2000c1e1b00 */
/*06e0*/ IMAD.WIDE R22, R2, 0x8, R28 ; /* 0x0000000802167825 */
/* 0x000fc600078e021c */
/*06f0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0700*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0008e8000c1e1b00 */
/*0710*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000f62000c1e1b00 */
/*0720*/ IMAD.WIDE R22, R2, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x010fca00078e0216 */
/*0730*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000f62000c1e1b00 */
/*0740*/ IMAD.WIDE R24, R2, 0x8, R22 ; /* 0x0000000802187825 */
/* 0x000fcc00078e0216 */
/*0750*/ IMAD.WIDE R28, R2, 0x8, R24 ; /* 0x00000008021c7825 */
/* 0x001fe200078e0218 */
/*0760*/ DFMA R18, R20, R12, R18 ; /* 0x0000000c1412722b */
/* 0x0060e40000000012 */
/*0770*/ LDG.E.64 R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0780*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x0000a2000c1e1b00 */
/*0790*/ DFMA R10, R16, R10, R18 ; /* 0x0000000a100a722b */
/* 0x0083460000000012 */
/*07a0*/ LDG.E.64 R16, [R6.64+0x20] ; /* 0x0000200406107981 */
/* 0x002ee8000c1e1b00 */
/*07b0*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0002e2000c1e1b00 */
/*07c0*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x0208a2000000000a */
/*07d0*/ IMAD.WIDE R28, R2.reuse, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x042fe400078e021c */
/*07e0*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x010f28000c1e1b00 */
/*07f0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000f22000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R28 ; /* 0x0000000802167825 */
/* 0x000fcc00078e021c */
/*0810*/ IMAD.WIDE R24, R2, 0x8, R22 ; /* 0x0000000802187825 */
/* 0x001fe200078e0216 */
/*0820*/ DFMA R20, R12, R20, R14 ; /* 0x000000140c14722b */
/* 0x0040e4000000000e */
/*0830*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x0010a8000c1e1b00 */
/*0840*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000ea2000c1e1b00 */
/*0850*/ DFMA R20, R16, R18, R20 ; /* 0x000000121014722b */
/* 0x0083060000000014 */
/*0860*/ LDG.E.64 R18, [R6.64+0x38] ; /* 0x0000380406127981 */
/* 0x0020e8000c1e1b00 */
/*0870*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000ee2000c1e1b00 */
/*0880*/ DFMA R8, R8, R10, R20 ; /* 0x0000000a0808722b */
/* 0x0102a40000000014 */
/*0890*/ IADD3 R10, P1, R6, 0x40, RZ ; /* 0x00000040060a7810 */
/* 0x002fc80007f3e0ff */
/*08a0*/ IADD3.X R11, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fe20000ffe4ff */
/*08b0*/ IMAD.WIDE R28, R2, 0x8, R24 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0218 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08d0*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe20007ffe0ff */
/*08e0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000a */
/*08f0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0900*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0910*/ DFMA R8, R12, R14, R8 ; /* 0x0000000e0c08722b */
/* 0x004ecc0000000008 */
/*0920*/ DFMA R18, R18, R16, R8 ; /* 0x000000101212722b */
/* 0x0080480000000008 */
/*0930*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0940*/ @!P0 BRA 0xad0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0950*/ LDG.E.64 R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea8000c1e1b00 */
/*0960*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x001ea2000c1e1b00 */
/*0970*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x000fc600078e021c */
/*0980*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0990*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x0000e8000c1e1b00 */
/*09a0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f22000c1e1b00 */
/*09b0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*09c0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000f22000c1e1b00 */
/*09d0*/ IMAD.WIDE R20, R2, 0x8, R24 ; /* 0x0000000802147825 */
/* 0x000fe200078e0218 */
/*09e0*/ DFMA R22, R22, R8, R18 ; /* 0x000000081616722b */
/* 0x0060e40000000012 */
/*09f0*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x0010a8000c1e1b00 */
/*0a00*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea2000c1e1b00 */
/*0a10*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ DFMA R10, R10, R12, R22 ; /* 0x0000000c0a0a722b */
/* 0x0083060000000016 */
/*0a30*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0a40*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fc80007f3e0ff */
/*0a50*/ IADD3.X R13, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe20000ffe4ff */
/*0a60*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x010ea2000000000a */
/*0a70*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe20007ffe0ff */
/*0a80*/ IMAD.WIDE R28, R2, 0x8, R20 ; /* 0x00000008021c7825 */
/* 0x000fe200078e0214 */
/*0a90*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fc60000000f00 */
/*0aa0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0ab0*/ DFMA R18, R18, R8, R10 ; /* 0x000000081212722b */
/* 0x004064000000000a */
/*0ac0*/ @P0 BRA 0x950 ; /* 0xfffffe8000000947 */
/* 0x003fea000383ffff */
/*0ad0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0ae0*/ @!P0 BRA 0xc10 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0af0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fe200000001ff */
/*0b00*/ IMAD R6, R0, c[0x0][0x178], R26 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e021a */
/*0b10*/ IMAD R8, R26, c[0x0][0x178], R3 ; /* 0x00005e001a087a24 */
/* 0x000fce00078e0203 */
/*0b20*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b30*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*0b40*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe40000000f00 */
/*0b50*/ MOV R12, R7 ; /* 0x00000007000c7202 */
/* 0x000fc60000000f00 */
/*0b60*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe200078e0005 */
/*0b70*/ MOV R7, R12 ; /* 0x0000000c00077202 */
/* 0x000fe20000000f00 */
/*0b80*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000aa000c1e1b00 */
/*0b90*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0ba0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc40007ffe0ff */
/*0bb0*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f3e0ff */
/*0bc0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0bd0*/ IMAD.WIDE R8, R2, 0x8, R8 ; /* 0x0000000802087825 */
/* 0x001fe200078e0208 */
/*0be0*/ IADD3.X R12, RZ, R12, RZ, P1, !PT ; /* 0x0000000cff0c7210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ DFMA R18, R6, R10, R18 ; /* 0x0000000a0612722b */
/* 0x0060540000000012 */
/*0c00*/ @P0 BRA 0xb60 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c10*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0c20*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c40*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixMult
.globl matrixMult
.p2align 8
.type matrixMult,@function
matrixMult:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], v[9:10], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixMult
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixMult, .Lfunc_end0-matrixMult
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixMult
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixMult.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00183d07_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi
.type _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi, @function
_Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrixMult(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi, .-_Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi
.globl matrixMult
.type matrixMult, @function
matrixMult:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10matrixMultPKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixMult, .-matrixMult
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixMult"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixMult(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMult.hip"
.globl __device_stub__matrixMult # -- Begin function __device_stub__matrixMult
.p2align 4, 0x90
.type __device_stub__matrixMult,@function
__device_stub__matrixMult: # @__device_stub__matrixMult
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrixMult, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__matrixMult, .Lfunc_end0-__device_stub__matrixMult
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixMult, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixMult,@object # @matrixMult
.section .rodata,"a",@progbits
.globl matrixMult
.p2align 3, 0x0
matrixMult:
.quad __device_stub__matrixMult
.size matrixMult, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixMult"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixMult
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixMult
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define CHECK_STATUS(status) \
if (status != cudaSuccess) \
fprintf(stderr, "File: %s\nLine:%d Function:%s>>>%s\n", __FILE__, __LINE__, __FUNCTION__,\
cudaGetErrorString(status))
// Device code
__global__ void MyKernel(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = (char*)devPitchedPtr.ptr; //获取数据指针
size_t pitch = devPitchedPtr.pitch; //获取一行所占的字节数
size_t slicePitch = pitch * height; //获取一层的大小，单位为字节
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch; // 得到第z层的起始地址
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch); //得到第z层中，第y行的起始地址
for (int x = 0; x < width; ++x) {
float element = row[x]; //得到第y行的第x个元素
}
}
}
}
int main(int argc, char **argv) {
CHECK_STATUS(cudaSetDevice(0));
size_t width = 64, height = 64, depth = 64;
// 定义三维数组大小
cudaExtent extent = make_cudaExtent(width * sizeof(float), height, depth);
// 三维数组的一个数据结构
cudaPitchedPtr devPitchedPtr;
// 分配三维数组
CHECK_STATUS(cudaMalloc3D(&devPitchedPtr,extent));
// 调用内核
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);
// 检查错误
CHECK_STATUS(cudaGetLastError());
// 释放内存
CHECK_STATUS(cudaFree(devPitchedPtr.ptr));
return 0;
} | code for sm_80
Function : _Z8MyKernel14cudaPitchedPtriii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define CHECK_STATUS(status) \
if (status != cudaSuccess) \
fprintf(stderr, "File: %s\nLine:%d Function:%s>>>%s\n", __FILE__, __LINE__, __FUNCTION__,\
cudaGetErrorString(status))
// Device code
__global__ void MyKernel(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = (char*)devPitchedPtr.ptr; //获取数据指针
size_t pitch = devPitchedPtr.pitch; //获取一行所占的字节数
size_t slicePitch = pitch * height; //获取一层的大小，单位为字节
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch; // 得到第z层的起始地址
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch); //得到第z层中，第y行的起始地址
for (int x = 0; x < width; ++x) {
float element = row[x]; //得到第y行的第x个元素
}
}
}
}
int main(int argc, char **argv) {
CHECK_STATUS(cudaSetDevice(0));
size_t width = 64, height = 64, depth = 64;
// 定义三维数组大小
cudaExtent extent = make_cudaExtent(width * sizeof(float), height, depth);
// 三维数组的一个数据结构
cudaPitchedPtr devPitchedPtr;
// 分配三维数组
CHECK_STATUS(cudaMalloc3D(&devPitchedPtr,extent));
// 调用内核
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);
// 检查错误
CHECK_STATUS(cudaGetLastError());
// 释放内存
CHECK_STATUS(cudaFree(devPitchedPtr.ptr));
return 0;
} | .file "tmpxft_00162a3b_00000000-6_sample_3.2.2-3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
.type _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii, @function
_Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8MyKernel14cudaPitchedPtriii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii, .-_Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
.globl _Z8MyKernel14cudaPitchedPtriii
.type _Z8MyKernel14cudaPitchedPtriii, @function
_Z8MyKernel14cudaPitchedPtriii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %ecx
movl %esi, %edx
movl %edi, %esi
leaq 16(%rsp), %rdi
call _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8MyKernel14cudaPitchedPtriii, .-_Z8MyKernel14cudaPitchedPtriii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "main"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Mannix1994/CUDA_Document_Samples/master/3/sample_3.2.2-3.cu"
.align 8
.LC2:
.string "File: %s\nLine:%d Function:%s>>>%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L19
.L12:
movq $256, 32(%rsp)
movq $64, 40(%rsp)
movq $64, 48(%rsp)
leaq 64(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 192
movdqa 64(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $64, 16(%rsp)
call cudaMalloc3D@PLT
addq $32, %rsp
.cfi_def_cfa_offset 160
testl %eax, %eax
jne .L20
.L13:
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $100, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
.L15:
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L23
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $30, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L20:
leaq 64(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 192
movdqa 64(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
call cudaMalloc3D@PLT
movl %eax, %edi
addq $32, %rsp
.cfi_def_cfa_offset 160
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $41, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L21:
movdqa 64(%rsp), %xmm2
movaps %xmm2, 96(%rsp)
movdqa 80(%rsp), %xmm3
movaps %xmm3, 112(%rsp)
leaq 96(%rsp), %rdi
movl $64, %ecx
movl $64, %edx
movl $64, %esi
call _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
jmp .L14
.L22:
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $47, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L23:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $50, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z8MyKernel14cudaPitchedPtriii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernel14cudaPitchedPtriii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define CHECK_STATUS(status) \
if (status != cudaSuccess) \
fprintf(stderr, "File: %s\nLine:%d Function:%s>>>%s\n", __FILE__, __LINE__, __FUNCTION__,\
cudaGetErrorString(status))
// Device code
__global__ void MyKernel(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = (char*)devPitchedPtr.ptr; //获取数据指针
size_t pitch = devPitchedPtr.pitch; //获取一行所占的字节数
size_t slicePitch = pitch * height; //获取一层的大小，单位为字节
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch; // 得到第z层的起始地址
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch); //得到第z层中，第y行的起始地址
for (int x = 0; x < width; ++x) {
float element = row[x]; //得到第y行的第x个元素
}
}
}
}
int main(int argc, char **argv) {
CHECK_STATUS(cudaSetDevice(0));
size_t width = 64, height = 64, depth = 64;
// 定义三维数组大小
cudaExtent extent = make_cudaExtent(width * sizeof(float), height, depth);
// 三维数组的一个数据结构
cudaPitchedPtr devPitchedPtr;
// 分配三维数组
CHECK_STATUS(cudaMalloc3D(&devPitchedPtr,extent));
// 调用内核
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);
// 检查错误
CHECK_STATUS(cudaGetLastError());
// 释放内存
CHECK_STATUS(cudaFree(devPitchedPtr.ptr));
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define CHECK_STATUS(status) \
if (status != hipSuccess) \
fprintf(stderr, "File: %s\nLine:%d Function:%s>>>%s\n", __FILE__, __LINE__, __FUNCTION__,\
hipGetErrorString(status))
// Device code
__global__ void MyKernel(hipPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = (char*)devPitchedPtr.ptr; //获取数据指针
size_t pitch = devPitchedPtr.pitch; //获取一行所占的字节数
size_t slicePitch = pitch * height; //获取一层的大小，单位为字节
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch; // 得到第z层的起始地址
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch); //得到第z层中，第y行的起始地址
for (int x = 0; x < width; ++x) {
float element = row[x]; //得到第y行的第x个元素
}
}
}
}
int main(int argc, char **argv) {
CHECK_STATUS(hipSetDevice(0));
size_t width = 64, height = 64, depth = 64;
// 定义三维数组大小
hipExtent extent = make_hipExtent(width * sizeof(float), height, depth);
// 三维数组的一个数据结构
hipPitchedPtr devPitchedPtr;
// 分配三维数组
CHECK_STATUS(hipMalloc3D(&devPitchedPtr,extent));
// 调用内核
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);
// 检查错误
CHECK_STATUS(hipGetLastError());
// 释放内存
CHECK_STATUS(hipFree(devPitchedPtr.ptr));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define CHECK_STATUS(status) \
if (status != hipSuccess) \
fprintf(stderr, "File: %s\nLine:%d Function:%s>>>%s\n", __FILE__, __LINE__, __FUNCTION__,\
hipGetErrorString(status))
// Device code
__global__ void MyKernel(hipPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = (char*)devPitchedPtr.ptr; //获取数据指针
size_t pitch = devPitchedPtr.pitch; //获取一行所占的字节数
size_t slicePitch = pitch * height; //获取一层的大小，单位为字节
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch; // 得到第z层的起始地址
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch); //得到第z层中，第y行的起始地址
for (int x = 0; x < width; ++x) {
float element = row[x]; //得到第y行的第x个元素
}
}
}
}
int main(int argc, char **argv) {
CHECK_STATUS(hipSetDevice(0));
size_t width = 64, height = 64, depth = 64;
// 定义三维数组大小
hipExtent extent = make_hipExtent(width * sizeof(float), height, depth);
// 三维数组的一个数据结构
hipPitchedPtr devPitchedPtr;
// 分配三维数组
CHECK_STATUS(hipMalloc3D(&devPitchedPtr,extent));
// 调用内核
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);
// 检查错误
CHECK_STATUS(hipGetLastError());
// 释放内存
CHECK_STATUS(hipFree(devPitchedPtr.ptr));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernel13hipPitchedPtriii
.globl _Z8MyKernel13hipPitchedPtriii
.p2align 8
.type _Z8MyKernel13hipPitchedPtriii,@function
_Z8MyKernel13hipPitchedPtriii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernel13hipPitchedPtriii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernel13hipPitchedPtriii, .Lfunc_end0-_Z8MyKernel13hipPitchedPtriii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernel13hipPitchedPtriii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8MyKernel13hipPitchedPtriii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define CHECK_STATUS(status) \
if (status != hipSuccess) \
fprintf(stderr, "File: %s\nLine:%d Function:%s>>>%s\n", __FILE__, __LINE__, __FUNCTION__,\
hipGetErrorString(status))
// Device code
__global__ void MyKernel(hipPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = (char*)devPitchedPtr.ptr; //获取数据指针
size_t pitch = devPitchedPtr.pitch; //获取一行所占的字节数
size_t slicePitch = pitch * height; //获取一层的大小，单位为字节
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch; // 得到第z层的起始地址
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch); //得到第z层中，第y行的起始地址
for (int x = 0; x < width; ++x) {
float element = row[x]; //得到第y行的第x个元素
}
}
}
}
int main(int argc, char **argv) {
CHECK_STATUS(hipSetDevice(0));
size_t width = 64, height = 64, depth = 64;
// 定义三维数组大小
hipExtent extent = make_hipExtent(width * sizeof(float), height, depth);
// 三维数组的一个数据结构
hipPitchedPtr devPitchedPtr;
// 分配三维数组
CHECK_STATUS(hipMalloc3D(&devPitchedPtr,extent));
// 调用内核
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);
// 检查错误
CHECK_STATUS(hipGetLastError());
// 释放内存
CHECK_STATUS(hipFree(devPitchedPtr.ptr));
return 0;
} | .text
.file "sample_3.2.2-3.hip"
.globl _Z23__device_stub__MyKernel13hipPitchedPtriii # -- Begin function _Z23__device_stub__MyKernel13hipPitchedPtriii
.p2align 4, 0x90
.type _Z23__device_stub__MyKernel13hipPitchedPtriii,@function
_Z23__device_stub__MyKernel13hipPitchedPtriii: # @_Z23__device_stub__MyKernel13hipPitchedPtriii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
leaq 112(%rsp), %rax
movq %rax, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8MyKernel13hipPitchedPtriii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernel13hipPitchedPtriii, .Lfunc_end0-_Z23__device_stub__MyKernel13hipPitchedPtriii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
.LBB1_2:
movq $256, 152(%rsp) # imm = 0x100
movq $64, 160(%rsp)
movq $64, 168(%rsp)
movups 152(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $64, 16(%rsp)
leaq 96(%rsp), %rdi
callq hipMalloc3D
testl %eax, %eax
jne .LBB1_3
.LBB1_4:
movabsq $4294967396, %rdi # imm = 0x100000064
leaq 412(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movups 96(%rsp), %xmm0
movups 112(%rsp), %xmm1
movaps %xmm1, 224(%rsp)
movaps %xmm0, 208(%rsp)
movl $64, 44(%rsp)
movl $64, 40(%rsp)
movl $64, 36(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rax
movq 48(%rsp), %rdi
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 176(%rsp), %r9
movl $_Z8MyKernel13hipPitchedPtriii, %edi
callq hipLaunchKernel
.LBB1_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
.LBB1_8:
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_9
.LBB1_10:
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
xorl %edi, %edi
callq hipSetDevice
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $30, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_2
.LBB1_3:
movq stderr(%rip), %rbx
movq $256, 128(%rsp) # imm = 0x100
movq $64, 136(%rsp)
movq $64, 144(%rsp)
movups 128(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $64, 16(%rsp)
leaq 96(%rsp), %rdi
callq hipMalloc3D
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $41, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_4
.LBB1_7:
movq stderr(%rip), %rbx
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $47, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %rbx
movq 96(%rsp), %rdi
callq hipFree
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $50, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernel13hipPitchedPtriii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernel13hipPitchedPtriii,@object # @_Z8MyKernel13hipPitchedPtriii
.section .rodata,"a",@progbits
.globl _Z8MyKernel13hipPitchedPtriii
.p2align 3, 0x0
_Z8MyKernel13hipPitchedPtriii:
.quad _Z23__device_stub__MyKernel13hipPitchedPtriii
.size _Z8MyKernel13hipPitchedPtriii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "File: %s\nLine:%d Function:%s>>>%s\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Mannix1994/CUDA_Document_Samples/master/3/sample_3.2.2-3.hip"
.size .L.str.1, 118
.type .L__FUNCTION__.main,@object # @__FUNCTION__.main
.L__FUNCTION__.main:
.asciz "main"
.size .L__FUNCTION__.main, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernel13hipPitchedPtriii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernel13hipPitchedPtriii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernel13hipPitchedPtriii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8MyKernel14cudaPitchedPtriii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MyKernel13hipPitchedPtriii
.globl _Z8MyKernel13hipPitchedPtriii
.p2align 8
.type _Z8MyKernel13hipPitchedPtriii,@function
_Z8MyKernel13hipPitchedPtriii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MyKernel13hipPitchedPtriii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MyKernel13hipPitchedPtriii, .Lfunc_end0-_Z8MyKernel13hipPitchedPtriii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MyKernel13hipPitchedPtriii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8MyKernel13hipPitchedPtriii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00162a3b_00000000-6_sample_3.2.2-3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
.type _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii, @function
_Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8MyKernel14cudaPitchedPtriii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii, .-_Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
.globl _Z8MyKernel14cudaPitchedPtriii
.type _Z8MyKernel14cudaPitchedPtriii, @function
_Z8MyKernel14cudaPitchedPtriii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %ecx
movl %esi, %edx
movl %edi, %esi
leaq 16(%rsp), %rdi
call _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8MyKernel14cudaPitchedPtriii, .-_Z8MyKernel14cudaPitchedPtriii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "main"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Mannix1994/CUDA_Document_Samples/master/3/sample_3.2.2-3.cu"
.align 8
.LC2:
.string "File: %s\nLine:%d Function:%s>>>%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L19
.L12:
movq $256, 32(%rsp)
movq $64, 40(%rsp)
movq $64, 48(%rsp)
leaq 64(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 192
movdqa 64(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $64, 16(%rsp)
call cudaMalloc3D@PLT
addq $32, %rsp
.cfi_def_cfa_offset 160
testl %eax, %eax
jne .L20
.L13:
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $100, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
.L15:
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L23
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $30, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L20:
leaq 64(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 192
movdqa 64(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
call cudaMalloc3D@PLT
movl %eax, %edi
addq $32, %rsp
.cfi_def_cfa_offset 160
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $41, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L21:
movdqa 64(%rsp), %xmm2
movaps %xmm2, 96(%rsp)
movdqa 80(%rsp), %xmm3
movaps %xmm3, 112(%rsp)
leaq 96(%rsp), %rdi
movl $64, %ecx
movl $64, %edx
movl $64, %esi
call _Z44__device_stub__Z8MyKernel14cudaPitchedPtriiiR14cudaPitchedPtriii
jmp .L14
.L22:
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $47, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L23:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC0(%rip), %r9
movl $50, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z8MyKernel14cudaPitchedPtriii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MyKernel14cudaPitchedPtriii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample_3.2.2-3.hip"
.globl _Z23__device_stub__MyKernel13hipPitchedPtriii # -- Begin function _Z23__device_stub__MyKernel13hipPitchedPtriii
.p2align 4, 0x90
.type _Z23__device_stub__MyKernel13hipPitchedPtriii,@function
_Z23__device_stub__MyKernel13hipPitchedPtriii: # @_Z23__device_stub__MyKernel13hipPitchedPtriii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
leaq 112(%rsp), %rax
movq %rax, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8MyKernel13hipPitchedPtriii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__MyKernel13hipPitchedPtriii, .Lfunc_end0-_Z23__device_stub__MyKernel13hipPitchedPtriii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
.LBB1_2:
movq $256, 152(%rsp) # imm = 0x100
movq $64, 160(%rsp)
movq $64, 168(%rsp)
movups 152(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $64, 16(%rsp)
leaq 96(%rsp), %rdi
callq hipMalloc3D
testl %eax, %eax
jne .LBB1_3
.LBB1_4:
movabsq $4294967396, %rdi # imm = 0x100000064
leaq 412(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movups 96(%rsp), %xmm0
movups 112(%rsp), %xmm1
movaps %xmm1, 224(%rsp)
movaps %xmm0, 208(%rsp)
movl $64, 44(%rsp)
movl $64, 40(%rsp)
movl $64, 36(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rax
movq 48(%rsp), %rdi
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 176(%rsp), %r9
movl $_Z8MyKernel13hipPitchedPtriii, %edi
callq hipLaunchKernel
.LBB1_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
.LBB1_8:
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_9
.LBB1_10:
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
xorl %edi, %edi
callq hipSetDevice
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $30, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_2
.LBB1_3:
movq stderr(%rip), %rbx
movq $256, 128(%rsp) # imm = 0x100
movq $64, 136(%rsp)
movq $64, 144(%rsp)
movups 128(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $64, 16(%rsp)
leaq 96(%rsp), %rdi
callq hipMalloc3D
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $41, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_4
.LBB1_7:
movq stderr(%rip), %rbx
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $47, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %rbx
movq 96(%rsp), %rdi
callq hipFree
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L__FUNCTION__.main, %r8d
movq %rbx, %rdi
movl $50, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MyKernel13hipPitchedPtriii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MyKernel13hipPitchedPtriii,@object # @_Z8MyKernel13hipPitchedPtriii
.section .rodata,"a",@progbits
.globl _Z8MyKernel13hipPitchedPtriii
.p2align 3, 0x0
_Z8MyKernel13hipPitchedPtriii:
.quad _Z23__device_stub__MyKernel13hipPitchedPtriii
.size _Z8MyKernel13hipPitchedPtriii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "File: %s\nLine:%d Function:%s>>>%s\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Mannix1994/CUDA_Document_Samples/master/3/sample_3.2.2-3.hip"
.size .L.str.1, 118
.type .L__FUNCTION__.main,@object # @__FUNCTION__.main
.L__FUNCTION__.main:
.asciz "main"
.size .L__FUNCTION__.main, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MyKernel13hipPitchedPtriii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MyKernel13hipPitchedPtriii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MyKernel13hipPitchedPtriii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// So, a __global__ to tell NVCC this is a device function for calling from the host
// and a pointer to some memory to write the result to
__global__ void addTwoNumbers(int x, int y, int *result) {
*result = x + y;
}
int main(int argc, char** args)
{
// This is in system memory
int cpuVisibleResult;
// This is just an unitialized pointer
int *gpuVisibleResult;
// This sets that pointer to point at a memory location on device memory
cudaMalloc( (void**)&gpuVisibleResult, sizeof(int) );
// Call the method, ignore 1,1 for now
addTwoNumbers<<<1,1>>>(2,7, gpuVisibleResult);
// Download the result from the device to the host
cudaMemcpy( &cpuVisibleResult, gpuVisibleResult, sizeof(int), cudaMemcpyDeviceToHost );
// Print the results
printf( " 2 + 7 = %d\n", cpuVisibleResult);
// Free up that memory on the device
cudaFree( gpuVisibleResult );
return 1;
} | code for sm_80
Function : _Z13addTwoNumbersiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// So, a __global__ to tell NVCC this is a device function for calling from the host
// and a pointer to some memory to write the result to
__global__ void addTwoNumbers(int x, int y, int *result) {
*result = x + y;
}
int main(int argc, char** args)
{
// This is in system memory
int cpuVisibleResult;
// This is just an unitialized pointer
int *gpuVisibleResult;
// This sets that pointer to point at a memory location on device memory
cudaMalloc( (void**)&gpuVisibleResult, sizeof(int) );
// Call the method, ignore 1,1 for now
addTwoNumbers<<<1,1>>>(2,7, gpuVisibleResult);
// Download the result from the device to the host
cudaMemcpy( &cpuVisibleResult, gpuVisibleResult, sizeof(int), cudaMemcpyDeviceToHost );
// Print the results
printf( " 2 + 7 = %d\n", cpuVisibleResult);
// Free up that memory on the device
cudaFree( gpuVisibleResult );
return 1;
} | .file "tmpxft_00012ec2_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13addTwoNumbersiiPiiiPi
.type _Z35__device_stub__Z13addTwoNumbersiiPiiiPi, @function
_Z35__device_stub__Z13addTwoNumbersiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13addTwoNumbersiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z13addTwoNumbersiiPiiiPi, .-_Z35__device_stub__Z13addTwoNumbersiiPiiiPi
.globl _Z13addTwoNumbersiiPi
.type _Z13addTwoNumbersiiPi, @function
_Z13addTwoNumbersiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13addTwoNumbersiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13addTwoNumbersiiPi, .-_Z13addTwoNumbersiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " 2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $1, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z35__device_stub__Z13addTwoNumbersiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13addTwoNumbersiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13addTwoNumbersiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// So, a __global__ to tell NVCC this is a device function for calling from the host
// and a pointer to some memory to write the result to
__global__ void addTwoNumbers(int x, int y, int *result) {
*result = x + y;
}
int main(int argc, char** args)
{
// This is in system memory
int cpuVisibleResult;
// This is just an unitialized pointer
int *gpuVisibleResult;
// This sets that pointer to point at a memory location on device memory
cudaMalloc( (void**)&gpuVisibleResult, sizeof(int) );
// Call the method, ignore 1,1 for now
addTwoNumbers<<<1,1>>>(2,7, gpuVisibleResult);
// Download the result from the device to the host
cudaMemcpy( &cpuVisibleResult, gpuVisibleResult, sizeof(int), cudaMemcpyDeviceToHost );
// Print the results
printf( " 2 + 7 = %d\n", cpuVisibleResult);
// Free up that memory on the device
cudaFree( gpuVisibleResult );
return 1;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// So, a __global__ to tell NVCC this is a device function for calling from the host
// and a pointer to some memory to write the result to
__global__ void addTwoNumbers(int x, int y, int *result) {
*result = x + y;
}
int main(int argc, char** args)
{
// This is in system memory
int cpuVisibleResult;
// This is just an unitialized pointer
int *gpuVisibleResult;
// This sets that pointer to point at a memory location on device memory
hipMalloc( (void**)&gpuVisibleResult, sizeof(int) );
// Call the method, ignore 1,1 for now
addTwoNumbers<<<1,1>>>(2,7, gpuVisibleResult);
// Download the result from the device to the host
hipMemcpy( &cpuVisibleResult, gpuVisibleResult, sizeof(int), hipMemcpyDeviceToHost );
// Print the results
printf( " 2 + 7 = %d\n", cpuVisibleResult);
// Free up that memory on the device
hipFree( gpuVisibleResult );
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// So, a __global__ to tell NVCC this is a device function for calling from the host
// and a pointer to some memory to write the result to
__global__ void addTwoNumbers(int x, int y, int *result) {
*result = x + y;
}
int main(int argc, char** args)
{
// This is in system memory
int cpuVisibleResult;
// This is just an unitialized pointer
int *gpuVisibleResult;
// This sets that pointer to point at a memory location on device memory
hipMalloc( (void**)&gpuVisibleResult, sizeof(int) );
// Call the method, ignore 1,1 for now
addTwoNumbers<<<1,1>>>(2,7, gpuVisibleResult);
// Download the result from the device to the host
hipMemcpy( &cpuVisibleResult, gpuVisibleResult, sizeof(int), hipMemcpyDeviceToHost );
// Print the results
printf( " 2 + 7 = %d\n", cpuVisibleResult);
// Free up that memory on the device
hipFree( gpuVisibleResult );
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13addTwoNumbersiiPi
.globl _Z13addTwoNumbersiiPi
.p2align 8
.type _Z13addTwoNumbersiiPi,@function
_Z13addTwoNumbersiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13addTwoNumbersiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13addTwoNumbersiiPi, .Lfunc_end0-_Z13addTwoNumbersiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13addTwoNumbersiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z13addTwoNumbersiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// So, a __global__ to tell NVCC this is a device function for calling from the host
// and a pointer to some memory to write the result to
__global__ void addTwoNumbers(int x, int y, int *result) {
*result = x + y;
}
int main(int argc, char** args)
{
// This is in system memory
int cpuVisibleResult;
// This is just an unitialized pointer
int *gpuVisibleResult;
// This sets that pointer to point at a memory location on device memory
hipMalloc( (void**)&gpuVisibleResult, sizeof(int) );
// Call the method, ignore 1,1 for now
addTwoNumbers<<<1,1>>>(2,7, gpuVisibleResult);
// Download the result from the device to the host
hipMemcpy( &cpuVisibleResult, gpuVisibleResult, sizeof(int), hipMemcpyDeviceToHost );
// Print the results
printf( " 2 + 7 = %d\n", cpuVisibleResult);
// Free up that memory on the device
hipFree( gpuVisibleResult );
return 1;
} | .text
.file "main.hip"
.globl _Z28__device_stub__addTwoNumbersiiPi # -- Begin function _Z28__device_stub__addTwoNumbersiiPi
.p2align 4, 0x90
.type _Z28__device_stub__addTwoNumbersiiPi,@function
_Z28__device_stub__addTwoNumbersiiPi: # @_Z28__device_stub__addTwoNumbersiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13addTwoNumbersiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__addTwoNumbersiiPi, .Lfunc_end0-_Z28__device_stub__addTwoNumbersiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13addTwoNumbersiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
movl $1, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13addTwoNumbersiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13addTwoNumbersiiPi,@object # @_Z13addTwoNumbersiiPi
.section .rodata,"a",@progbits
.globl _Z13addTwoNumbersiiPi
.p2align 3, 0x0
_Z13addTwoNumbersiiPi:
.quad _Z28__device_stub__addTwoNumbersiiPi
.size _Z13addTwoNumbersiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " 2 + 7 = %d\n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13addTwoNumbersiiPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__addTwoNumbersiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13addTwoNumbersiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.