system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vec_add ( int * l, int * r, int n ){
int thid = threadIdx.x + blockDim.x * blockIdx.x;
if(thid >= n) return;
l[thid] += r[thid];
}
int main(){
int l[] = {1,2,3,4};
int * gpu_l;
hipMalloc( &gpu_l, sizeof(int) * 4);
hipMemcpy(gpu_l, l, sizeof(int) * 4, hipMemcpyHostToDevice);
int r[] = {4, 3, 2, 1};
int * gpu_r;
hipMalloc( &gpu_r, sizeof(int) * 4);
hipMemcpy(gpu_r, r, sizeof(int) * 4, hipMemcpyHostToDevice);
vec_add<<<2,2>>>( gpu_l,gpu_r,4);
printf("Last error: %s \n", hipGetErrorString(hipDeviceSynchronize()));
hipMemcpy(l, gpu_l, sizeof(int) * 4, hipMemcpyDeviceToHost);
hipFree( gpu_l);
for(int i = 0; i < 4; i++)
printf("l[%d] : %d\n", i, l[i]);
hipMemcpy(r, gpu_r, sizeof(int) * 4, hipMemcpyDeviceToHost);
hipFree( gpu_r);
for(int i = 0; i < 4; i++)
printf("r[%d] : %d\n", i, r[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vec_addPiS_i
.globl _Z7vec_addPiS_i
.p2align 8
.type _Z7vec_addPiS_i,@function
_Z7vec_addPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vec_addPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vec_addPiS_i, .Lfunc_end0-_Z7vec_addPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vec_addPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vec_addPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vec_add ( int * l, int * r, int n ){
int thid = threadIdx.x + blockDim.x * blockIdx.x;
if(thid >= n) return;
l[thid] += r[thid];
}
int main(){
int l[] = {1,2,3,4};
int * gpu_l;
hipMalloc( &gpu_l, sizeof(int) * 4);
hipMemcpy(gpu_l, l, sizeof(int) * 4, hipMemcpyHostToDevice);
int r[] = {4, 3, 2, 1};
int * gpu_r;
hipMalloc( &gpu_r, sizeof(int) * 4);
hipMemcpy(gpu_r, r, sizeof(int) * 4, hipMemcpyHostToDevice);
vec_add<<<2,2>>>( gpu_l,gpu_r,4);
printf("Last error: %s \n", hipGetErrorString(hipDeviceSynchronize()));
hipMemcpy(l, gpu_l, sizeof(int) * 4, hipMemcpyDeviceToHost);
hipFree( gpu_l);
for(int i = 0; i < 4; i++)
printf("l[%d] : %d\n", i, l[i]);
hipMemcpy(r, gpu_r, sizeof(int) * 4, hipMemcpyDeviceToHost);
hipFree( gpu_r);
for(int i = 0; i < 4; i++)
printf("r[%d] : %d\n", i, r[i]);
} | .text
.file "test.hip"
.globl _Z22__device_stub__vec_addPiS_i # -- Begin function _Z22__device_stub__vec_addPiS_i
.p2align 4, 0x90
.type _Z22__device_stub__vec_addPiS_i,@function
_Z22__device_stub__vec_addPiS_i: # @_Z22__device_stub__vec_addPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vec_addPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__vec_addPiS_i, .Lfunc_end0-_Z22__device_stub__vec_addPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 4 # 0x4
.long 3 # 0x3
.long 2 # 0x2
.long 1 # 0x1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $160, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 48(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [4,3,2,1]
movaps %xmm0, 32(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $4, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7vec_addPiS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 48(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vec_addPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vec_addPiS_i,@object # @_Z7vec_addPiS_i
.section .rodata,"a",@progbits
.globl _Z7vec_addPiS_i
.p2align 3, 0x0
_Z7vec_addPiS_i:
.quad _Z22__device_stub__vec_addPiS_i
.size _Z7vec_addPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Last error: %s \n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "l[%d] : %d\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r[%d] : %d\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7vec_addPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vec_addPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vec_addPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7vec_addPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vec_addPiS_i
.globl _Z7vec_addPiS_i
.p2align 8
.type _Z7vec_addPiS_i,@function
_Z7vec_addPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vec_addPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vec_addPiS_i, .Lfunc_end0-_Z7vec_addPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vec_addPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vec_addPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000521b5_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7vec_addPiS_iPiS_i
.type _Z29__device_stub__Z7vec_addPiS_iPiS_i, @function
_Z29__device_stub__Z7vec_addPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vec_addPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7vec_addPiS_iPiS_i, .-_Z29__device_stub__Z7vec_addPiS_iPiS_i
.globl _Z7vec_addPiS_i
.type _Z7vec_addPiS_i, @function
_Z7vec_addPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7vec_addPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7vec_addPiS_i, .-_Z7vec_addPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Last error: %s \n"
.LC1:
.string "l[%d] : %d\n"
.LC2:
.string "r[%d] : %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 64(%rsp)
movl $3, 68(%rsp)
movl $2, 72(%rsp)
movl $1, 76(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L13:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L13
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L14:
movl 64(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L14
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $4, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z7vec_addPiS_iPiS_i
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7vec_addPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vec_addPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__vec_addPiS_i # -- Begin function _Z22__device_stub__vec_addPiS_i
.p2align 4, 0x90
.type _Z22__device_stub__vec_addPiS_i,@function
_Z22__device_stub__vec_addPiS_i: # @_Z22__device_stub__vec_addPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vec_addPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__vec_addPiS_i, .Lfunc_end0-_Z22__device_stub__vec_addPiS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 4 # 0x4
.long 3 # 0x3
.long 2 # 0x2
.long 1 # 0x1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $160, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 48(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [4,3,2,1]
movaps %xmm0, 32(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $4, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7vec_addPiS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 48(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_5
# %bb.6:
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vec_addPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vec_addPiS_i,@object # @_Z7vec_addPiS_i
.section .rodata,"a",@progbits
.globl _Z7vec_addPiS_i
.p2align 3, 0x0
_Z7vec_addPiS_i:
.quad _Z22__device_stub__vec_addPiS_i
.size _Z7vec_addPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Last error: %s \n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "l[%d] : %d\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r[%d] : %d\n"
.size .L.str.2, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7vec_addPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vec_addPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vec_addPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
/* Publish topic GPU code: set an topic array to a value */
__global__ void pub_topic(float *topic,float param) {
int i=threadIdx.x; /* find my index */
topic[i]=i+param;
}
/* Subscribe topic CPU code: get antopic value */
void sub_topic(float *topic, int i) {
/* Copy elements back to CPU for subscriber */
int s=1;
i=0;
float f=0.0; /* CPU copy of value */
cudaMemcpy(&f,&topic[i],sizeof(float),cudaMemcpyDeviceToHost);
std::cout<<"subscriber "<< s <<":topic["<<i<<"] = "<<f<<"\n";
}
/* CPU code: memory movement and kernel calls */
int main(int argc,char *argv[]) {
int i=0;
int n=20; /* total number of floats */
float *topic; /* device array of n values */
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMalloc( (void**) &topic, n*sizeof(float) ); //Allocate GPU space
pub_topic<<<1,n>>>(topic,0.1543); /* Initialize the space on the GPU */
sub_topic(topic,i);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout<<"Elapsed time = "<<milliseconds<<" milliseconds\n";
return 0;
} | code for sm_80
Function : _Z9pub_topicPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x001e300000201400 */
/*0050*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*0060*/ FADD R5, R0, c[0x0][0x168] ; /* 0x00005a0000057621 */
/* 0x001fca0000000000 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
/* Publish topic GPU code: set an topic array to a value */
__global__ void pub_topic(float *topic,float param) {
int i=threadIdx.x; /* find my index */
topic[i]=i+param;
}
/* Subscribe topic CPU code: get antopic value */
void sub_topic(float *topic, int i) {
/* Copy elements back to CPU for subscriber */
int s=1;
i=0;
float f=0.0; /* CPU copy of value */
cudaMemcpy(&f,&topic[i],sizeof(float),cudaMemcpyDeviceToHost);
std::cout<<"subscriber "<< s <<":topic["<<i<<"] = "<<f<<"\n";
}
/* CPU code: memory movement and kernel calls */
int main(int argc,char *argv[]) {
int i=0;
int n=20; /* total number of floats */
float *topic; /* device array of n values */
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMalloc( (void**) &topic, n*sizeof(float) ); //Allocate GPU space
pub_topic<<<1,n>>>(topic,0.1543); /* Initialize the space on the GPU */
sub_topic(topic,i);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout<<"Elapsed time = "<<milliseconds<<" milliseconds\n";
return 0;
} | .file "tmpxft_0019e6e4_00000000-6_pubsub1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "subscriber "
.LC2:
.string ":topic["
.LC3:
.string "] = "
.LC4:
.string "\n"
.text
.globl _Z9sub_topicPfi
.type _Z9sub_topicPfi, @function
_Z9sub_topicPfi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl $11, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $7, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z9sub_topicPfi, .-_Z9sub_topicPfi
.globl _Z29__device_stub__Z9pub_topicPffPff
.type _Z29__device_stub__Z9pub_topicPffPff, @function
_Z29__device_stub__Z9pub_topicPffPff:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9pub_topicPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z9pub_topicPffPff, .-_Z29__device_stub__Z9pub_topicPffPff
.globl _Z9pub_topicPff
.type _Z9pub_topicPff, @function
_Z9pub_topicPff:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9pub_topicPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9pub_topicPff, .-_Z9pub_topicPff
.section .rodata.str1.1
.LC6:
.string "Elapsed time = "
.LC7:
.string " milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $20, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $0, %esi
movq 8(%rsp), %rdi
call _Z9sub_topicPfi
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movss .LC5(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9pub_topicPffPff
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9pub_topicPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pub_topicPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1042153682
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
/* Publish topic GPU code: set an topic array to a value */
__global__ void pub_topic(float *topic,float param) {
int i=threadIdx.x; /* find my index */
topic[i]=i+param;
}
/* Subscribe topic CPU code: get antopic value */
void sub_topic(float *topic, int i) {
/* Copy elements back to CPU for subscriber */
int s=1;
i=0;
float f=0.0; /* CPU copy of value */
cudaMemcpy(&f,&topic[i],sizeof(float),cudaMemcpyDeviceToHost);
std::cout<<"subscriber "<< s <<":topic["<<i<<"] = "<<f<<"\n";
}
/* CPU code: memory movement and kernel calls */
int main(int argc,char *argv[]) {
int i=0;
int n=20; /* total number of floats */
float *topic; /* device array of n values */
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMalloc( (void**) &topic, n*sizeof(float) ); //Allocate GPU space
pub_topic<<<1,n>>>(topic,0.1543); /* Initialize the space on the GPU */
sub_topic(topic,i);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout<<"Elapsed time = "<<milliseconds<<" milliseconds\n";
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
/* Publish topic GPU code: set an topic array to a value */
__global__ void pub_topic(float *topic,float param) {
int i=threadIdx.x; /* find my index */
topic[i]=i+param;
}
/* Subscribe topic CPU code: get antopic value */
void sub_topic(float *topic, int i) {
/* Copy elements back to CPU for subscriber */
int s=1;
i=0;
float f=0.0; /* CPU copy of value */
hipMemcpy(&f,&topic[i],sizeof(float),hipMemcpyDeviceToHost);
std::cout<<"subscriber "<< s <<":topic["<<i<<"] = "<<f<<"\n";
}
/* CPU code: memory movement and kernel calls */
int main(int argc,char *argv[]) {
int i=0;
int n=20; /* total number of floats */
float *topic; /* device array of n values */
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMalloc( (void**) &topic, n*sizeof(float) ); //Allocate GPU space
pub_topic<<<1,n>>>(topic,0.1543); /* Initialize the space on the GPU */
sub_topic(topic,i);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout<<"Elapsed time = "<<milliseconds<<" milliseconds\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
/* Publish topic GPU code: set an topic array to a value */
__global__ void pub_topic(float *topic,float param) {
int i=threadIdx.x; /* find my index */
topic[i]=i+param;
}
/* Subscribe topic CPU code: get antopic value */
void sub_topic(float *topic, int i) {
/* Copy elements back to CPU for subscriber */
int s=1;
i=0;
float f=0.0; /* CPU copy of value */
hipMemcpy(&f,&topic[i],sizeof(float),hipMemcpyDeviceToHost);
std::cout<<"subscriber "<< s <<":topic["<<i<<"] = "<<f<<"\n";
}
/* CPU code: memory movement and kernel calls */
int main(int argc,char *argv[]) {
int i=0;
int n=20; /* total number of floats */
float *topic; /* device array of n values */
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMalloc( (void**) &topic, n*sizeof(float) ); //Allocate GPU space
pub_topic<<<1,n>>>(topic,0.1543); /* Initialize the space on the GPU */
sub_topic(topic,i);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout<<"Elapsed time = "<<milliseconds<<" milliseconds\n";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9pub_topicPff
.globl _Z9pub_topicPff
.p2align 8
.type _Z9pub_topicPff,@function
_Z9pub_topicPff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_i32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v1, s2, v1 :: v_dual_lshlrev_b32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9pub_topicPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9pub_topicPff, .Lfunc_end0-_Z9pub_topicPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9pub_topicPff
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z9pub_topicPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
/* Publish topic GPU code: set an topic array to a value */
__global__ void pub_topic(float *topic,float param) {
int i=threadIdx.x; /* find my index */
topic[i]=i+param;
}
/* Subscribe topic CPU code: get antopic value */
void sub_topic(float *topic, int i) {
/* Copy elements back to CPU for subscriber */
int s=1;
i=0;
float f=0.0; /* CPU copy of value */
hipMemcpy(&f,&topic[i],sizeof(float),hipMemcpyDeviceToHost);
std::cout<<"subscriber "<< s <<":topic["<<i<<"] = "<<f<<"\n";
}
/* CPU code: memory movement and kernel calls */
int main(int argc,char *argv[]) {
int i=0;
int n=20; /* total number of floats */
float *topic; /* device array of n values */
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMalloc( (void**) &topic, n*sizeof(float) ); //Allocate GPU space
pub_topic<<<1,n>>>(topic,0.1543); /* Initialize the space on the GPU */
sub_topic(topic,i);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout<<"Elapsed time = "<<milliseconds<<" milliseconds\n";
return 0;
} | .text
.file "pubsub1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__pub_topicPff # -- Begin function _Z24__device_stub__pub_topicPff
.p2align 4, 0x90
.type _Z24__device_stub__pub_topicPff,@function
_Z24__device_stub__pub_topicPff: # @_Z24__device_stub__pub_topicPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9pub_topicPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__pub_topicPff, .Lfunc_end0-_Z24__device_stub__pub_topicPff
.cfi_endproc
# -- End function
.globl _Z9sub_topicPfi # -- Begin function _Z9sub_topicPfi
.p2align 4, 0x90
.type _Z9sub_topicPfi,@function
_Z9sub_topicPfi: # @_Z9sub_topicPfi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rsi
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9sub_topicPfi, .Lfunc_end1-_Z9sub_topicPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 48(%rsp), %rax
movq %rax, 104(%rsp)
movl $1042153682, 36(%rsp) # imm = 0x3E1E00D2
leaq 104(%rsp), %rax
movq %rax, (%rsp)
leaq 36(%rsp), %rax
movq %rax, 8(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movq %rsp, %r9
movl $_Z9pub_topicPff, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 48(%rsp), %rsi
movl $0, (%rsp)
movq %rsp, %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, (%rsp)
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9pub_topicPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9pub_topicPff,@object # @_Z9pub_topicPff
.section .rodata,"a",@progbits
.globl _Z9pub_topicPff
.p2align 3, 0x0
_Z9pub_topicPff:
.quad _Z24__device_stub__pub_topicPff
.size _Z9pub_topicPff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "subscriber "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ":topic["
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "] = "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Elapsed time = "
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " milliseconds\n"
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9pub_topicPff"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__pub_topicPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9pub_topicPff
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9pub_topicPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x001e300000201400 */
/*0050*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*0060*/ FADD R5, R0, c[0x0][0x168] ; /* 0x00005a0000057621 */
/* 0x001fca0000000000 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9pub_topicPff
.globl _Z9pub_topicPff
.p2align 8
.type _Z9pub_topicPff,@function
_Z9pub_topicPff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_i32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v1, s2, v1 :: v_dual_lshlrev_b32 v0, 2, v0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9pub_topicPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9pub_topicPff, .Lfunc_end0-_Z9pub_topicPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9pub_topicPff
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z9pub_topicPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019e6e4_00000000-6_pubsub1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "subscriber "
.LC2:
.string ":topic["
.LC3:
.string "] = "
.LC4:
.string "\n"
.text
.globl _Z9sub_topicPfi
.type _Z9sub_topicPfi, @function
_Z9sub_topicPfi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl $11, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $7, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z9sub_topicPfi, .-_Z9sub_topicPfi
.globl _Z29__device_stub__Z9pub_topicPffPff
.type _Z29__device_stub__Z9pub_topicPffPff, @function
_Z29__device_stub__Z9pub_topicPffPff:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9pub_topicPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z9pub_topicPffPff, .-_Z29__device_stub__Z9pub_topicPffPff
.globl _Z9pub_topicPff
.type _Z9pub_topicPff, @function
_Z9pub_topicPff:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9pub_topicPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9pub_topicPff, .-_Z9pub_topicPff
.section .rodata.str1.1
.LC6:
.string "Elapsed time = "
.LC7:
.string " milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $20, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movl $0, %esi
movq 8(%rsp), %rdi
call _Z9sub_topicPfi
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movss .LC5(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9pub_topicPffPff
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9pub_topicPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pub_topicPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1042153682
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pubsub1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__pub_topicPff # -- Begin function _Z24__device_stub__pub_topicPff
.p2align 4, 0x90
.type _Z24__device_stub__pub_topicPff,@function
_Z24__device_stub__pub_topicPff: # @_Z24__device_stub__pub_topicPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9pub_topicPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__pub_topicPff, .Lfunc_end0-_Z24__device_stub__pub_topicPff
.cfi_endproc
# -- End function
.globl _Z9sub_topicPfi # -- Begin function _Z9sub_topicPfi
.p2align 4, 0x90
.type _Z9sub_topicPfi,@function
_Z9sub_topicPfi: # @_Z9sub_topicPfi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rsi
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9sub_topicPfi, .Lfunc_end1-_Z9sub_topicPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 48(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 19(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 48(%rsp), %rax
movq %rax, 104(%rsp)
movl $1042153682, 36(%rsp) # imm = 0x3E1E00D2
leaq 104(%rsp), %rax
movq %rax, (%rsp)
leaq 36(%rsp), %rax
movq %rax, 8(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movq %rsp, %r9
movl $_Z9pub_topicPff, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 48(%rsp), %rsi
movl $0, (%rsp)
movq %rsp, %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
xorl %esi, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, (%rsp)
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9pub_topicPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9pub_topicPff,@object # @_Z9pub_topicPff
.section .rodata,"a",@progbits
.globl _Z9pub_topicPff
.p2align 3, 0x0
_Z9pub_topicPff:
.quad _Z24__device_stub__pub_topicPff
.size _Z9pub_topicPff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "subscriber "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ":topic["
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "] = "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Elapsed time = "
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " milliseconds\n"
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9pub_topicPff"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__pub_topicPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9pub_topicPff
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | int MaxVectorComp(float *result, int size)
{
float max = *result;
int j = 0;
for (int i = 1; i < size; i++){
if (max < result[i]){
max = result[i];
j = i;
}
}
return j;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | int MaxVectorComp(float *result, int size)
{
float max = *result;
int j = 0;
for (int i = 1; i < size; i++){
if (max < result[i]){
max = result[i];
j = i;
}
}
return j;
} | .file "tmpxft_00194613_00000000-6_MaxVectorComp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13MaxVectorCompPfi
.type _Z13MaxVectorCompPfi, @function
_Z13MaxVectorCompPfi:
.LFB2027:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
cmpl $1, %esi
jle .L8
movl %esi, %esi
movl $1, %eax
movl $0, %edx
.L7:
movss (%rdi,%rax,4), %xmm1
comiss %xmm0, %xmm1
cmova %eax, %edx
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $1, %rax
cmpq %rsi, %rax
jne .L7
.L3:
movl %edx, %eax
ret
.L8:
movl $0, %edx
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z13MaxVectorCompPfi, .-_Z13MaxVectorCompPfi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | int MaxVectorComp(float *result, int size)
{
float max = *result;
int j = 0;
for (int i = 1; i < size; i++){
if (max < result[i]){
max = result[i];
j = i;
}
}
return j;
} | #include <hip/hip_runtime.h>
int MaxVectorComp(float *result, int size)
{
float max = *result;
int j = 0;
for (int i = 1; i < size; i++){
if (max < result[i]){
max = result[i];
j = i;
}
}
return j;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
int MaxVectorComp(float *result, int size)
{
float max = *result;
int j = 0;
for (int i = 1; i < size; i++){
if (max < result[i]){
max = result[i];
j = i;
}
}
return j;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
int MaxVectorComp(float *result, int size)
{
float max = *result;
int j = 0;
for (int i = 1; i < size; i++){
if (max < result[i]){
max = result[i];
j = i;
}
}
return j;
} | .text
.file "MaxVectorComp.hip"
.globl _Z13MaxVectorCompPfi # -- Begin function _Z13MaxVectorCompPfi
.p2align 4, 0x90
.type _Z13MaxVectorCompPfi,@function
_Z13MaxVectorCompPfi: # @_Z13MaxVectorCompPfi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl $2, %esi
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %esi, %ecx
xorl %eax, %eax
movl $1, %edx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
cmoval %edx, %eax
maxss %xmm0, %xmm1
incq %rdx
movaps %xmm1, %xmm0
cmpq %rdx, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z13MaxVectorCompPfi, .Lfunc_end0-_Z13MaxVectorCompPfi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00194613_00000000-6_MaxVectorComp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13MaxVectorCompPfi
.type _Z13MaxVectorCompPfi, @function
_Z13MaxVectorCompPfi:
.LFB2027:
.cfi_startproc
endbr64
movss (%rdi), %xmm0
cmpl $1, %esi
jle .L8
movl %esi, %esi
movl $1, %eax
movl $0, %edx
.L7:
movss (%rdi,%rax,4), %xmm1
comiss %xmm0, %xmm1
cmova %eax, %edx
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $1, %rax
cmpq %rsi, %rax
jne .L7
.L3:
movl %edx, %eax
ret
.L8:
movl $0, %edx
jmp .L3
.cfi_endproc
.LFE2027:
.size _Z13MaxVectorCompPfi, .-_Z13MaxVectorCompPfi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MaxVectorComp.hip"
.globl _Z13MaxVectorCompPfi # -- Begin function _Z13MaxVectorCompPfi
.p2align 4, 0x90
.type _Z13MaxVectorCompPfi,@function
_Z13MaxVectorCompPfi: # @_Z13MaxVectorCompPfi
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl $2, %esi
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %esi, %ecx
xorl %eax, %eax
movl $1, %edx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
cmoval %edx, %eax
maxss %xmm0, %xmm1
incq %rdx
movaps %xmm1, %xmm0
cmpq %rdx, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z13MaxVectorCompPfi, .Lfunc_end0-_Z13MaxVectorCompPfi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void redunction_neighbored_pairs_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int gid = blockDim.x * blockIdx.x + threadIdx.x;
if (gid > size)
return;
for (int offset = 1; offset <= blockDim.x / 2; offset *= 2)
{
if (tid % (2 * offset) == 0)
{
input[gid] += input[gid + offset];
}
__syncthreads();
}
if (tid == 0)
{
temp[blockIdx.x] = input[gid];
}
} | code for sm_80
Function : _Z29redunction_neighbored_pairs_1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R5 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0203 */
/*00b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*00c0*/ @!P0 BRA 0x340 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00e0*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fd20000000000 */
/*00f0*/ IMAD.SHL.U32 R6, R7, 0x2, RZ ; /* 0x0000000207067824 */
/* 0x000fe200078e00ff */
/*0100*/ IABS R14, R5 ; /* 0x00000005000e7213 */
/* 0x000fe20000000000 */
/*0110*/ BSSY B0, 0x300 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0120*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f46270 */
/*0130*/ IABS R12, R6.reuse ; /* 0x00000006000c7213 */
/* 0x080fe40000000000 */
/*0140*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0150*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */
/* 0x000e300000209400 */
/*0160*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0170*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fe20007ffe0ff */
/*0180*/ IMAD.MOV R10, RZ, RZ, -R13 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0a0d */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*01a0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x001fe20000000f00 */
/*01b0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*01c0*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e02ff */
/*01d0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*01e0*/ IMAD.MOV.U32 R11, RZ, RZ, R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000e */
/*01f0*/ IMAD.HI.U32 R9, R9, R4, RZ ; /* 0x0000000409097227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R9, R9, R10, R11 ; /* 0x0000000a09097224 */
/* 0x000fca00078e020b */
/*0210*/ ISETP.GT.U32.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f04070 */
/*0220*/ @!P0 IADD3 R9, R9, -R12, RZ ; /* 0x8000000c09098210 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f24070 */
/*0250*/ @!P1 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a0c */
/*0260*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0270*/ @!P0 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff098212 */
/* 0x000fc800078e33ff */
/*0280*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0290*/ @P0 BRA 0x2f0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.WIDE R8, R7, 0x4, R2 ; /* 0x0000000407087825 */
/* 0x000fe400078e0202 */
/*02b0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x004fca0007ffe0ff */
/*02e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ ISETP.GT.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf04070 */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x001fd800078e0006 */
/*0330*/ @!P0 BRA 0xf0 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*0340*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0370*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0380*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0390*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void redunction_neighbored_pairs_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int gid = blockDim.x * blockIdx.x + threadIdx.x;
if (gid > size)
return;
for (int offset = 1; offset <= blockDim.x / 2; offset *= 2)
{
if (tid % (2 * offset) == 0)
{
input[gid] += input[gid + offset];
}
__syncthreads();
}
if (tid == 0)
{
temp[blockIdx.x] = input[gid];
}
} | .file "tmpxft_0016f2fa_00000000-6_redunction_neighbored_pairs_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i
.type _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i, @function
_Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29redunction_neighbored_pairs_1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i, .-_Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i
.globl _Z29redunction_neighbored_pairs_1PiS_i
.type _Z29redunction_neighbored_pairs_1PiS_i, @function
_Z29redunction_neighbored_pairs_1PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z29redunction_neighbored_pairs_1PiS_i, .-_Z29redunction_neighbored_pairs_1PiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29redunction_neighbored_pairs_1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29redunction_neighbored_pairs_1PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void redunction_neighbored_pairs_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int gid = blockDim.x * blockIdx.x + threadIdx.x;
if (gid > size)
return;
for (int offset = 1; offset <= blockDim.x / 2; offset *= 2)
{
if (tid % (2 * offset) == 0)
{
input[gid] += input[gid + offset];
}
__syncthreads();
}
if (tid == 0)
{
temp[blockIdx.x] = input[gid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void redunction_neighbored_pairs_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int gid = blockDim.x * blockIdx.x + threadIdx.x;
if (gid > size)
return;
for (int offset = 1; offset <= blockDim.x / 2; offset *= 2)
{
if (tid % (2 * offset) == 0)
{
input[gid] += input[gid + offset];
}
__syncthreads();
}
if (tid == 0)
{
temp[blockIdx.x] = input[gid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void redunction_neighbored_pairs_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int gid = blockDim.x * blockIdx.x + threadIdx.x;
if (gid > size)
return;
for (int offset = 1; offset <= blockDim.x / 2; offset *= 2)
{
if (tid % (2 * offset) == 0)
{
input[gid] += input[gid + offset];
}
__syncthreads();
}
if (tid == 0)
{
temp[blockIdx.x] = input[gid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29redunction_neighbored_pairs_1PiS_i
.globl _Z29redunction_neighbored_pairs_1PiS_i
.p2align 8
.type _Z29redunction_neighbored_pairs_1PiS_i,@function
_Z29redunction_neighbored_pairs_1PiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_ge_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s7, 1
s_lshr_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_gt_u32 s6, s3
s_mov_b32 s7, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshl_b32 s6, s7, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s6, -1
v_and_b32_e32 v5, s8, v0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v5, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
global_store_b32 v[3:4], v5, off
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29redunction_neighbored_pairs_1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29redunction_neighbored_pairs_1PiS_i, .Lfunc_end0-_Z29redunction_neighbored_pairs_1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29redunction_neighbored_pairs_1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29redunction_neighbored_pairs_1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void redunction_neighbored_pairs_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int gid = blockDim.x * blockIdx.x + threadIdx.x;
if (gid > size)
return;
for (int offset = 1; offset <= blockDim.x / 2; offset *= 2)
{
if (tid % (2 * offset) == 0)
{
input[gid] += input[gid + offset];
}
__syncthreads();
}
if (tid == 0)
{
temp[blockIdx.x] = input[gid];
}
} | .text
.file "redunction_neighbored_pairs_1.hip"
.globl _Z44__device_stub__redunction_neighbored_pairs_1PiS_i # -- Begin function _Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.p2align 4, 0x90
.type _Z44__device_stub__redunction_neighbored_pairs_1PiS_i,@function
_Z44__device_stub__redunction_neighbored_pairs_1PiS_i: # @_Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29redunction_neighbored_pairs_1PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z44__device_stub__redunction_neighbored_pairs_1PiS_i, .Lfunc_end0-_Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29redunction_neighbored_pairs_1PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29redunction_neighbored_pairs_1PiS_i,@object # @_Z29redunction_neighbored_pairs_1PiS_i
.section .rodata,"a",@progbits
.globl _Z29redunction_neighbored_pairs_1PiS_i
.p2align 3, 0x0
_Z29redunction_neighbored_pairs_1PiS_i:
.quad _Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.size _Z29redunction_neighbored_pairs_1PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29redunction_neighbored_pairs_1PiS_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29redunction_neighbored_pairs_1PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29redunction_neighbored_pairs_1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R5 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0203 */
/*00b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*00c0*/ @!P0 BRA 0x340 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00e0*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fd20000000000 */
/*00f0*/ IMAD.SHL.U32 R6, R7, 0x2, RZ ; /* 0x0000000207067824 */
/* 0x000fe200078e00ff */
/*0100*/ IABS R14, R5 ; /* 0x00000005000e7213 */
/* 0x000fe20000000000 */
/*0110*/ BSSY B0, 0x300 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0120*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f46270 */
/*0130*/ IABS R12, R6.reuse ; /* 0x00000006000c7213 */
/* 0x080fe40000000000 */
/*0140*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe40000000000 */
/*0150*/ I2F.RP R10, R12 ; /* 0x0000000c000a7306 */
/* 0x000e300000209400 */
/*0160*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*0170*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fe20007ffe0ff */
/*0180*/ IMAD.MOV R10, RZ, RZ, -R13 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0a0d */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*01a0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x001fe20000000f00 */
/*01b0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*01c0*/ IMAD R11, R11, R12, RZ ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e02ff */
/*01d0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*01e0*/ IMAD.MOV.U32 R11, RZ, RZ, R14 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000e */
/*01f0*/ IMAD.HI.U32 R9, R9, R4, RZ ; /* 0x0000000409097227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R9, R9, R10, R11 ; /* 0x0000000a09097224 */
/* 0x000fca00078e020b */
/*0210*/ ISETP.GT.U32.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f04070 */
/*0220*/ @!P0 IADD3 R9, R9, -R12, RZ ; /* 0x8000000c09098210 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x000fda0003f24070 */
/*0250*/ @!P1 IMAD.IADD R9, R9, 0x1, -R12 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a0c */
/*0260*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*0270*/ @!P0 LOP3.LUT R9, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff098212 */
/* 0x000fc800078e33ff */
/*0280*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0290*/ @P0 BRA 0x2f0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.WIDE R8, R7, 0x4, R2 ; /* 0x0000000407087825 */
/* 0x000fe400078e0202 */
/*02b0*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x004fca0007ffe0ff */
/*02e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ ISETP.GT.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf04070 */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x001fd800078e0006 */
/*0330*/ @!P0 BRA 0xf0 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*0340*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0370*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0380*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0390*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29redunction_neighbored_pairs_1PiS_i
.globl _Z29redunction_neighbored_pairs_1PiS_i
.p2align 8
.type _Z29redunction_neighbored_pairs_1PiS_i,@function
_Z29redunction_neighbored_pairs_1PiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_ge_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s3, 2
s_cbranch_scc1 .LBB0_6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s7, 1
s_lshr_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_gt_u32 s6, s3
s_mov_b32 s7, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_lshl_b32 s6, s7, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s6, -1
v_and_b32_e32 v5, s8, v0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v5, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
global_store_b32 v[3:4], v5, off
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29redunction_neighbored_pairs_1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29redunction_neighbored_pairs_1PiS_i, .Lfunc_end0-_Z29redunction_neighbored_pairs_1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29redunction_neighbored_pairs_1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29redunction_neighbored_pairs_1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016f2fa_00000000-6_redunction_neighbored_pairs_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i
.type _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i, @function
_Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29redunction_neighbored_pairs_1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i, .-_Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i
.globl _Z29redunction_neighbored_pairs_1PiS_i
.type _Z29redunction_neighbored_pairs_1PiS_i, @function
_Z29redunction_neighbored_pairs_1PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z29redunction_neighbored_pairs_1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z29redunction_neighbored_pairs_1PiS_i, .-_Z29redunction_neighbored_pairs_1PiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29redunction_neighbored_pairs_1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29redunction_neighbored_pairs_1PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "redunction_neighbored_pairs_1.hip"
.globl _Z44__device_stub__redunction_neighbored_pairs_1PiS_i # -- Begin function _Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.p2align 4, 0x90
.type _Z44__device_stub__redunction_neighbored_pairs_1PiS_i,@function
_Z44__device_stub__redunction_neighbored_pairs_1PiS_i: # @_Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29redunction_neighbored_pairs_1PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z44__device_stub__redunction_neighbored_pairs_1PiS_i, .Lfunc_end0-_Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29redunction_neighbored_pairs_1PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29redunction_neighbored_pairs_1PiS_i,@object # @_Z29redunction_neighbored_pairs_1PiS_i
.section .rodata,"a",@progbits
.globl _Z29redunction_neighbored_pairs_1PiS_i
.p2align 3, 0x0
_Z29redunction_neighbored_pairs_1PiS_i:
.quad _Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.size _Z29redunction_neighbored_pairs_1PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29redunction_neighbored_pairs_1PiS_i"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__redunction_neighbored_pairs_1PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29redunction_neighbored_pairs_1PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void topp_initialization_kernel(bool* finished, int* sequence_length, int* word_ids, int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size, const int start_id)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
for(int i = tid; i < batch_size; i+= blockDim.x)
{
finished[i] = false;
sequence_length[i] = 0;
word_ids[i] = start_id;
}
}
int index = tid + bid * blockDim.x;
while(index < batch_size * vocab_size)
{
topp_id_val_buf[index] = index % vocab_size;
index += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fda0003f05270 */
/*0050*/ @P0 BRA 0x230 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GT.AND P0, PT, R8.reuse, c[0x0][0x188], PT ; /* 0x0000620008007a0c */
/* 0x042fe20003f04270 */
/*0070*/ BSSY B0, 0x130 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0080*/ ISETP.GE.AND P1, PT, R8, c[0x0][0x188], PT ; /* 0x0000620008007a0c */
/* 0x000fd60003f26270 */
/*0090*/ @P0 BRA 0x120 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R5, R0.reuse, c[0x0][0x18c], RZ ; /* 0x0000630000057a24 */
/* 0x040fe400078e02ff */
/*00d0*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x040fe200078e0207 */
/*00e0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101906 */
/*0100*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f04270 */
/*0110*/ @!P0 BRA 0xc0 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ BSSY B0, 0x230 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0140*/ @P1 BRA 0x220 ; /* 0x000000d000001947 */
/* 0x000fea0003800000 */
/*0150*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0b7624 */
/* 0x000fe400078e00ff */
/*0180*/ IADD3 R6, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x041fe20007f1e0ff */
/*0190*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e020d */
/*01a0*/ LEA.HI.X.SX32 R7, R0.reuse, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000077a11 */
/* 0x040fe200000f0eff */
/*01b0*/ IMAD.WIDE R4, R0.reuse, R13, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x040fe200078e020d */
/*01c0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*01d0*/ STG.E.U8 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e2000c101106 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fc60003f06270 */
/*01f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101906 */
/*0200*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001ec000c101906 */
/*0210*/ @!P0 BRA 0x180 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x002fe20000000a00 */
/*0240*/ IMAD R0, R9, c[0x0][0x0], R8 ; /* 0x0000000009007a24 */
/* 0x000fe200078e0208 */
/*0250*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fcc000f8e023f */
/*0260*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ IABS R11, c[0x0][0x18c] ; /* 0x00006300000b7a13 */
/* 0x001fe20000000000 */
/*0290*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*02c0*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*02d0*/ IABS R17, c[0x0][0x18c] ; /* 0x0000630000117a13 */
/* 0x000fe40000000000 */
/*02e0*/ LOP3.LUT R7, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff077a12 */
/* 0x000fca00078e33ff */
/*02f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0300*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0310*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0320*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0330*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0340*/ IMAD R5, R6, R11, RZ ; /* 0x0000000b06057224 */
/* 0x000fca00078e02ff */
/*0350*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fc800078e0002 */
/*0360*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0370*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f46270 */
/*0380*/ IMAD.HI.U32 R2, R5, R4, RZ ; /* 0x0000000405027227 */
/* 0x001fca00078e00ff */
/*0390*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*03a0*/ IMAD R2, R17, R3, R4 ; /* 0x0000000311027224 */
/* 0x000fca00078e0204 */
/*03b0*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*03c0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R17 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a11 */
/*03d0*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*03e0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R17 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a11 */
/*03f0*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0400*/ IMAD.WIDE R2, R0, R15, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e020f */
/*0410*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe400078e0a04 */
/*0420*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */
/* 0x000fc600078e0200 */
/*0430*/ SEL R9, R7, R4, !P0 ; /* 0x0000000407097207 */
/* 0x000fe40004000000 */
/*0440*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc6000bf26270 */
/*0450*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001f4000c101906 */
/*0460*/ @!P1 BRA 0x360 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void topp_initialization_kernel(bool* finished, int* sequence_length, int* word_ids, int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size, const int start_id)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
for(int i = tid; i < batch_size; i+= blockDim.x)
{
finished[i] = false;
sequence_length[i] = 0;
word_ids[i] = start_id;
}
}
int index = tid + bid * blockDim.x;
while(index < batch_size * vocab_size)
{
topp_id_val_buf[index] = index % vocab_size;
index += blockDim.x * gridDim.x;
}
} | .file "tmpxft_00087500_00000000-6_topp_initialization_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii
.type _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii, @function
_Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26topp_initialization_kernelPbPiS0_S0_S0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii, .-_Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii
.globl _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.type _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, @function
_Z26topp_initialization_kernelPbPiS0_S0_S0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, .-_Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26topp_initialization_kernelPbPiS0_S0_S0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26topp_initialization_kernelPbPiS0_S0_S0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void topp_initialization_kernel(bool* finished, int* sequence_length, int* word_ids, int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size, const int start_id)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
for(int i = tid; i < batch_size; i+= blockDim.x)
{
finished[i] = false;
sequence_length[i] = 0;
word_ids[i] = start_id;
}
}
int index = tid + bid * blockDim.x;
while(index < batch_size * vocab_size)
{
topp_id_val_buf[index] = index % vocab_size;
index += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void topp_initialization_kernel(bool* finished, int* sequence_length, int* word_ids, int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size, const int start_id)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
for(int i = tid; i < batch_size; i+= blockDim.x)
{
finished[i] = false;
sequence_length[i] = 0;
word_ids[i] = start_id;
}
}
int index = tid + bid * blockDim.x;
while(index < batch_size * vocab_size)
{
topp_id_val_buf[index] = index % vocab_size;
index += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void topp_initialization_kernel(bool* finished, int* sequence_length, int* word_ids, int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size, const int start_id)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
for(int i = tid; i < batch_size; i+= blockDim.x)
{
finished[i] = false;
sequence_length[i] = 0;
word_ids[i] = start_id;
}
}
int index = tid + bid * blockDim.x;
while(index < batch_size * vocab_size)
{
topp_id_val_buf[index] = index % vocab_size;
index += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.globl _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.p2align 8
.type _Z26topp_initialization_kernelPbPiS0_S0_S0_iii,@function
_Z26topp_initialization_kernelPbPiS0_S0_S0_iii:
s_load_b64 s[8:9], s[0:1], 0x28
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_8
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ge_i32_e64 s8, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s5, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x20
v_mul_lo_u32 v3, v0, s9
v_mov_b32_e32 v1, v0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s6, s9, s5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, s8, v1
global_store_b32 v[4:5], v3, off
v_add_nc_u32_e32 v3, s6, v3
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_7
s_clause 0x3
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s12, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s2
s_and_b32 s12, s12, 0xffff
.p2align 6
.LBB0_6:
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v8, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s12, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, s6, v6
v_add_co_ci_u32_e64 v11, s2, s7, v7, s2
v_add_co_u32 v6, s2, s10, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, s11, v7, s2
s_or_b32 s13, vcc_lo, s13
global_store_b8 v[8:9], v3, off
global_store_b32 v[10:11], v4, off
global_store_b32 v[6:7], v5, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_load_b32 s4, s[0:1], 0x44
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_mul_i32 s4, s9, s8
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_11
s_ashr_i32 s5, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s9, s5
s_xor_b32 s5, s7, s5
s_load_b32 s7, s[2:3], 0x0
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s7, s6
s_mov_b32 s6, 0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
.p2align 6
.LBB0_10:
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v0
v_mul_lo_u32 v3, v3, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_subrev_nc_u32_e32 v3, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v6, s5, v5
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s4, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v4
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s6, vcc_lo, s6
v_sub_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, .Lfunc_end0-_Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26topp_initialization_kernelPbPiS0_S0_S0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void topp_initialization_kernel(bool* finished, int* sequence_length, int* word_ids, int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size, const int start_id)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
for(int i = tid; i < batch_size; i+= blockDim.x)
{
finished[i] = false;
sequence_length[i] = 0;
word_ids[i] = start_id;
}
}
int index = tid + bid * blockDim.x;
while(index < batch_size * vocab_size)
{
topp_id_val_buf[index] = index % vocab_size;
index += blockDim.x * gridDim.x;
}
} | .text
.file "topp_initialization_kernel.hip"
.globl _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii # -- Begin function _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.p2align 4, 0x90
.type _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii,@function
_Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii: # @_Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26topp_initialization_kernelPbPiS0_S0_S0_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii, .Lfunc_end0-_Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26topp_initialization_kernelPbPiS0_S0_S0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26topp_initialization_kernelPbPiS0_S0_S0_iii,@object # @_Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.section .rodata,"a",@progbits
.globl _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.p2align 3, 0x0
_Z26topp_initialization_kernelPbPiS0_S0_S0_iii:
.quad _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.size _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26topp_initialization_kernelPbPiS0_S0_S0_iii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fda0003f05270 */
/*0050*/ @P0 BRA 0x230 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GT.AND P0, PT, R8.reuse, c[0x0][0x188], PT ; /* 0x0000620008007a0c */
/* 0x042fe20003f04270 */
/*0070*/ BSSY B0, 0x130 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0080*/ ISETP.GE.AND P1, PT, R8, c[0x0][0x188], PT ; /* 0x0000620008007a0c */
/* 0x000fd60003f26270 */
/*0090*/ @P0 BRA 0x120 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R5, R0.reuse, c[0x0][0x18c], RZ ; /* 0x0000630000057a24 */
/* 0x040fe400078e02ff */
/*00d0*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x040fe200078e0207 */
/*00e0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101906 */
/*0100*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f04270 */
/*0110*/ @!P0 BRA 0xc0 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ BSSY B0, 0x230 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0140*/ @P1 BRA 0x220 ; /* 0x000000d000001947 */
/* 0x000fea0003800000 */
/*0150*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0b7624 */
/* 0x000fe400078e00ff */
/*0180*/ IADD3 R6, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x041fe20007f1e0ff */
/*0190*/ IMAD.WIDE R2, R0, R13, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e020d */
/*01a0*/ LEA.HI.X.SX32 R7, R0.reuse, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000077a11 */
/* 0x040fe200000f0eff */
/*01b0*/ IMAD.WIDE R4, R0.reuse, R13, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x040fe200078e020d */
/*01c0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*01d0*/ STG.E.U8 [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0001e2000c101106 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fc60003f06270 */
/*01f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101906 */
/*0200*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001ec000c101906 */
/*0210*/ @!P0 BRA 0x180 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x002fe20000000a00 */
/*0240*/ IMAD R0, R9, c[0x0][0x0], R8 ; /* 0x0000000009007a24 */
/* 0x000fe200078e0208 */
/*0250*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fcc000f8e023f */
/*0260*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ IABS R11, c[0x0][0x18c] ; /* 0x00006300000b7a13 */
/* 0x001fe20000000000 */
/*0290*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*02c0*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*02d0*/ IABS R17, c[0x0][0x18c] ; /* 0x0000630000117a13 */
/* 0x000fe40000000000 */
/*02e0*/ LOP3.LUT R7, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff077a12 */
/* 0x000fca00078e33ff */
/*02f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0300*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0310*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0320*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0330*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0340*/ IMAD R5, R6, R11, RZ ; /* 0x0000000b06057224 */
/* 0x000fca00078e02ff */
/*0350*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fc800078e0002 */
/*0360*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0370*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f46270 */
/*0380*/ IMAD.HI.U32 R2, R5, R4, RZ ; /* 0x0000000405027227 */
/* 0x001fca00078e00ff */
/*0390*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*03a0*/ IMAD R2, R17, R3, R4 ; /* 0x0000000311027224 */
/* 0x000fca00078e0204 */
/*03b0*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*03c0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R17 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a11 */
/*03d0*/ ISETP.GT.U32.AND P1, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f24070 */
/*03e0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R17 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a11 */
/*03f0*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0400*/ IMAD.WIDE R2, R0, R15, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e020f */
/*0410*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe400078e0a04 */
/*0420*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */
/* 0x000fc600078e0200 */
/*0430*/ SEL R9, R7, R4, !P0 ; /* 0x0000000407097207 */
/* 0x000fe40004000000 */
/*0440*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc6000bf26270 */
/*0450*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001f4000c101906 */
/*0460*/ @!P1 BRA 0x360 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.globl _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.p2align 8
.type _Z26topp_initialization_kernelPbPiS0_S0_S0_iii,@function
_Z26topp_initialization_kernelPbPiS0_S0_S0_iii:
s_load_b64 s[8:9], s[0:1], 0x28
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_8
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ge_i32_e64 s8, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s5, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x20
v_mul_lo_u32 v3, v0, s9
v_mov_b32_e32 v1, v0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s6, s9, s5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, s8, v1
global_store_b32 v[4:5], v3, off
v_add_nc_u32_e32 v3, s6, v3
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_7
s_clause 0x3
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s12, s[0:1], 0x44
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v5, s2
s_and_b32 s12, s12, 0xffff
.p2align 6
.LBB0_6:
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v8, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s12, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, s6, v6
v_add_co_ci_u32_e64 v11, s2, s7, v7, s2
v_add_co_u32 v6, s2, s10, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, s11, v7, s2
s_or_b32 s13, vcc_lo, s13
global_store_b8 v[8:9], v3, off
global_store_b32 v[10:11], v4, off
global_store_b32 v[6:7], v5, off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_load_b32 s4, s[0:1], 0x44
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_mul_i32 s4, s9, s8
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_11
s_ashr_i32 s5, s9, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s9, s5
s_xor_b32 s5, s7, s5
s_load_b32 s7, s[2:3], 0x0
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s7, s6
s_mov_b32 s6, 0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
.p2align 6
.LBB0_10:
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v0
v_mul_lo_u32 v3, v3, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_subrev_nc_u32_e32 v3, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v6, s5, v5
v_cmp_le_u32_e32 vcc_lo, s5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s4, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v4
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s6, vcc_lo, s6
v_sub_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_10
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, .Lfunc_end0-_Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26topp_initialization_kernelPbPiS0_S0_S0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00087500_00000000-6_topp_initialization_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii
.type _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii, @function
_Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26topp_initialization_kernelPbPiS0_S0_S0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii, .-_Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii
.globl _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.type _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, @function
_Z26topp_initialization_kernelPbPiS0_S0_S0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z26topp_initialization_kernelPbPiS0_S0_S0_iiiPbPiS0_S0_S0_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, .-_Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26topp_initialization_kernelPbPiS0_S0_S0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26topp_initialization_kernelPbPiS0_S0_S0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "topp_initialization_kernel.hip"
.globl _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii # -- Begin function _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.p2align 4, 0x90
.type _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii,@function
_Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii: # @_Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26topp_initialization_kernelPbPiS0_S0_S0_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii, .Lfunc_end0-_Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26topp_initialization_kernelPbPiS0_S0_S0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26topp_initialization_kernelPbPiS0_S0_S0_iii,@object # @_Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.section .rodata,"a",@progbits
.globl _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.p2align 3, 0x0
_Z26topp_initialization_kernelPbPiS0_S0_S0_iii:
.quad _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.size _Z26topp_initialization_kernelPbPiS0_S0_S0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26topp_initialization_kernelPbPiS0_S0_S0_iii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__topp_initialization_kernelPbPiS0_S0_S0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26topp_initialization_kernelPbPiS0_S0_S0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
typedef struct {
double _r;
double _g;
double _b;
double _m;
double _n;
} Point;
#define CUDA_CALL(x) {if((x) != cudaSuccess){ \
printf("CUDA error at %s:%d\n",__FILE__,__LINE__); \
printf(" %s\n", cudaGetErrorString(cudaGetLastError())); \
exit(EXIT_FAILURE);}}
//Leer las dimensiones de la imagen a x b pixeles
void readImageSize(FILE *ifp,int* K,int* a,int* b) {
fscanf(ifp,"%d\n",K);
printf("%d\n",*K);
fscanf(ifp,"%d\n",a);
printf("%d\n",*a);
fscanf(ifp,"%d\n",b);
printf("%d\n",*b);
}
//Leer archivo ifp y lo almacena en el struct
void readPoints(FILE* ifp,Point *points, int num_points) {
int i;
for(i=0;i<num_points;i++) {
fscanf(ifp,"%lf,%lf,%lf,%lf,%lf", &points[i]._r, &points[i]._g, &points[i]._b, &points[i]._m, &points[i]._n);
}
}
//Inicializar puntos aleatorios como los medios (k numero de clusters)
void initialize(Point* mean,int K, int num_points, Point* points) {
int i, a, p=2;
srand(time(NULL));
for(i=0;i<K;i++) {
a = num_points/p;
//printf("\n num_points: %d\n", num_points/p);
mean[i]._r = points[a]._r;
mean[i]._g = points[a]._g;
mean[i]._b = points[a]._b;
mean[i]._m = points[a]._m;
mean[i]._n = points[a]._n;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
//printf("%lf,%lf,%lf,%lf,%lf\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
p++;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
}
}
//Todos los puntos sin clusters
void IntClusterMem(int *cluster, int num_points) {
int i;
for(i=0;i < num_points; i ++) {
cluster[i]=-1;
}
}
//Para calcular a que cluster pertenece el punto. (k numero de clusters)
__global__ void pointsCluster(int* after_cluster_d, Point* point_d,Point* Dmean,int K, int x, int y) {
int j, k, i;
j = blockIdx.x*blockDim.x+threadIdx.x;
k = blockIdx.y*blockDim.y+threadIdx.y;
int parent=0;
double dist=0;
int t = (k*(x)+j);
double minDist= sqrt((pow((point_d[t]._r-Dmean[0]._r),2)+pow((point_d[t]._g-Dmean[0]._g),2)+pow((point_d[t]._b-Dmean[0]._b),2)+pow((point_d[t]._m-Dmean[0]._m),2)+pow((point_d[t]._n-Dmean[0]._n),2)));
for(i=1;i<K;i++) {
dist = sqrt((pow((point_d[t]._r-Dmean[i]._r),2)+pow((point_d[t]._g-Dmean[i]._g),2)+pow((point_d[t]._b-Dmean[i]._b),2)+pow((point_d[t]._m-Dmean[i]._m),2)+pow((point_d[t]._n-Dmean[i]._n),2)));
if(minDist>=dist) {
parent=i;
minDist=dist;
}
}
after_cluster_d[t] = parent;
}
//Calcular nueva media
void calcNewMean(Point* points,int* cluster,Point* mean,int K,int num_points) {
Point* newMean=(Point*)malloc(sizeof(Point)*K);
int* members=(int*)malloc(sizeof(int)*(K));
int i;
for(i=0;i<K;i++) {
members[i]=0;
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
for(i=0;i<num_points;i++) {
members[cluster[i]]++;
newMean[cluster[i]]._r+=points[i]._r;
newMean[cluster[i]]._g+=points[i]._g;
newMean[cluster[i]]._b+=points[i]._b;
newMean[cluster[i]]._m+=points[i]._m;
newMean[cluster[i]]._n+=points[i]._n;
}
for(i=0;i<K;i++) {
if(members[i]!=0.0) {
newMean[i]._r/=members[i];
newMean[i]._g/=members[i];
newMean[i]._b/=members[i];
newMean[i]._m/=members[i];
newMean[i]._n/=members[i];
}
else {
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
}
for(i=0;i<K;i++) {
mean[i]._r=newMean[i]._r;
mean[i]._g=newMean[i]._g;
mean[i]._b=newMean[i]._b;
mean[i]._m=newMean[i]._m;
mean[i]._n=newMean[i]._n;
}
}
//Comprobamos la convergencia
//Comprueba que cada clúster de puntos permanece igual
int chkConvrg(int *before_clusters,int *after_cluster,int num_points, float tol) {
int i;
tol = num_points*tol;
for(i=0;i<num_points;i++) {
if(abs(before_clusters[i]-after_cluster[i])>tol) {
//check = abs(before_clusters[i]-after_cluster[i]);
//printf("check = %d, after_cluster[%d]=%d, before_clusters[%d]=%d\n",check,i,after_cluster[i],i,before_clusters[i]);
return -1;
}
}
return 0;
}
int main(int argc, char* argv[]) {
//Variables CPU
int K;
int num_points;
int * before_clusters;
int i;
int job_done=0;
int x,y,iter=0;
Point* mean;
Point* points;
int * after_cluster;
float tol;
//Variables GPU
Point* points_d;
Point* mean_d;
int * after_cluster_d;
int * before_cluster_d;
cudaEvent_t startinit, endinit, startmean, endmean, startcal, endcal, startindex, endindex;
cudaEvent_t start1, end1;
float timeinit, timemean, timecal, timeindex;
float time1;
//float totTime = 0;
tol = atof(argv[3]);
//iterations = atof(argv[3]);
//printf("Ingrese tolerancia: ");
//scanf("%f",&tol);
printf("Tolerancia = %f \n",tol);
cudaEventCreate(&start1);
cudaEventCreate(&end1);
cudaEventRecord(start1, 0);
//Leyendo archivo
FILE *ifp;
ifp=fopen(argv[1],"r");
readImageSize(ifp,&K,&x,&y);
K = atoi(argv[6]);
num_points = x*y;
int blockX=atoi(argv[4]);
int blockY=atoi(argv[5]);
//asignar memoria a la CPU
points=(Point*)malloc(sizeof(Point)*num_points);
readPoints(ifp,points,num_points);
fclose(ifp);
//printf("Entrada leida con exito \n");
before_clusters=(int*)malloc(sizeof(int)*num_points);
after_cluster=(int*)malloc(sizeof(int)*num_points);
mean=(Point*)malloc(sizeof(Point)*K);
//inicializando valores por defecto
initialize(mean,K, num_points, points);
IntClusterMem(before_clusters,num_points);
IntClusterMem(after_cluster,num_points);
CUDA_CALL(cudaMalloc((void**) &after_cluster_d, sizeof(int)*num_points));
CUDA_CALL(cudaMalloc((void**) &before_cluster_d, sizeof(int)*num_points));
CUDA_CALL(cudaMalloc((void**) &points_d, sizeof(Point)*num_points));
CUDA_CALL(cudaMalloc((void**) &mean_d, sizeof(Point)*K));
cudaEventCreate(&startinit);
cudaEventCreate(&endinit);
cudaEventRecord(startinit, 0);
//copiar los puntos al device
CUDA_CALL(cudaMemcpy(points_d, points, sizeof(Point)*num_points, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, cudaMemcpyHostToDevice));
cudaEventRecord(endinit, 0);
cudaEventSynchronize(endinit);
cudaEventElapsedTime(&timeinit, startinit, endinit);
int iter_max=0;
char *fcentroid;
if(K==10){
iter_max=4;
fcentroid="Centroid_10.txt";
}
else if(K==30){
iter_max=14;
fcentroid="Centroid_30.txt";
}
else if(K==50){
iter_max=63;
fcentroid="Centroid_50.txt";
}
else{
iter_max=87;
fcentroid="Centroid_100.txt";
}
while(1) {
cudaEventCreate(&startmean);
cudaEventCreate(&endmean);
cudaEventRecord(startmean, 0);
//copiar los centroides iniciales al device
CUDA_CALL(cudaMemcpy(mean_d, mean, sizeof(Point)*K, cudaMemcpyHostToDevice));
cudaEventRecord(endmean, 0);
cudaEventSynchronize(endmean);
cudaEventElapsedTime(&timemean, startmean, endmean);
//copia de memoria cuda
//CUDA_CALL(cudaMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(before_cluster_d, before_clusters, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(x_d, &x, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(y_d, &y, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(K_d, &K, sizeof(int), cudaMemcpyHostToDevice));
cudaEventCreate(&startcal);
cudaEventCreate(&endcal);
cudaEventRecord(startcal, 0);
dim3 block(blockX, blockY);
dim3 grid((x+blockX-1)/blockX, (y+blockY-1)/blockY);
pointsCluster<<<grid,block>>>(after_cluster_d, points_d,mean_d,K,x,y);
cudaDeviceSynchronize();
cudaEventRecord(endcal, 0);
cudaEventSynchronize(endcal);
cudaEventElapsedTime(&timecal, startcal, endcal);
cudaEventCreate(&startindex);
cudaEventCreate(&endindex);
cudaEventRecord(startindex, 0);
CUDA_CALL(cudaMemcpy(after_cluster, after_cluster_d, sizeof(int)*num_points, cudaMemcpyDeviceToHost));
cudaEventRecord(endindex, 0);
cudaEventSynchronize(endindex);
cudaEventElapsedTime(&timeindex, startindex, endindex);
calcNewMean(points,after_cluster,mean,K,num_points);
//printf("Nuevos centroides son calculados!\n");
if(iter>iter_max) {
// printf("El algoritmo kmeans converge con = %d!\n",iter);
job_done=1;
}
else {
//printf("No converge!\n");
for(i=0;i<num_points;i++) {
//printf("1 after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
before_clusters[i]=after_cluster[i];
//printf("after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
}
}
if(job_done==1)
break;
++iter;
}
//Salida en archivos
FILE* ofp=fopen(argv[2],"w");
FILE* ofpc=fopen(fcentroid,"w");
fprintf(ofp,"%d\n",K);
fprintf(ofp,"%d\n",x);
fprintf(ofp,"%d\n",y);
for(i=0;i<K;i++)
fprintf(ofpc,"%.0f,%.0f,%.0f,%.0f,%.0f\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
for(i=0;i<num_points;i++)
fprintf(ofp,"%.0f,%.0f,%.0f,%.0f,%.0f,%d\n",points[i]._r,points[i]._g,points[i]._b,points[i]._m,points[i]._n,after_cluster[i]+1);
fclose(ofp);
fclose(ofpc);
cudaEventRecord(end1, 0);
cudaEventSynchronize(end1);
cudaEventElapsedTime(&time1, start1, end1);
printf("Total Iteraciones = %d\n",iter-1);
printf("CUDA:Tiempo total transcurrido en la ejecucion. k= %d con tolerancia= %f en clusters : %f sec\n", K,tol,time1/1000);
//printf("Tiempo Total : %f\t sec\n",time1/1000);
CUDA_CALL(cudaFree(after_cluster_d));
CUDA_CALL(cudaFree(mean_d));
CUDA_CALL(cudaFree(points_d));
free(before_clusters);
free(mean);
free(points);
free(after_cluster);
return 0;
} | .file "tmpxft_00077d83_00000000-6_kmean_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z13readImageSizeP8_IO_FILEPiS1_S1_
.type _Z13readImageSizeP8_IO_FILEPiS1_S1_, @function
_Z13readImageSizeP8_IO_FILEPiS1_S1_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r14
movq %rdx, %r13
movq %rcx, %r12
movq %rsi, %rdx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%r14), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 0(%r13), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%r12), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z13readImageSizeP8_IO_FILEPiS1_S1_, .-_Z13readImageSizeP8_IO_FILEPiS1_S1_
.section .rodata.str1.1
.LC1:
.string "%lf,%lf,%lf,%lf,%lf"
.text
.globl _Z10readPointsP8_IO_FILEP5Pointi
.type _Z10readPointsP8_IO_FILEP5Pointi, @function
_Z10readPointsP8_IO_FILEP5Pointi:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L10
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rax
leaq (%rsi,%rax,8), %r13
leaq .LC1(%rip), %r12
.L7:
leaq 8(%rbx), %rcx
subq $8, %rsp
.cfi_def_cfa_offset 56
leaq 32(%rbx), %rax
pushq %rax
.cfi_def_cfa_offset 64
leaq 24(%rbx), %r9
leaq 16(%rbx), %r8
movq %rbx, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $40, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 48
cmpq %r13, %rbx
jne .L7
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2058:
.size _Z10readPointsP8_IO_FILEP5Pointi, .-_Z10readPointsP8_IO_FILEP5Pointi
.globl _Z10initializeP5PointiiS0_
.type _Z10initializeP5PointiiS0_, @function
_Z10initializeP5PointiiS0_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %esi, %r13d
movl %edx, %ebp
movq %rcx, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r13d, %r13d
jle .L13
movq %rbx, %rcx
leal 2(%r13), %edi
movl $2, %esi
.L15:
movl %ebp, %eax
cltd
idivl %esi
cltq
leaq (%rax,%rax,4), %rax
leaq (%r12,%rax,8), %rdx
movsd (%rdx), %xmm0
movsd %xmm0, (%rcx)
movsd 8(%rdx), %xmm0
movsd %xmm0, 8(%rcx)
movsd 16(%rdx), %xmm0
movsd %xmm0, 16(%rcx)
movsd 24(%rdx), %xmm0
movsd %xmm0, 24(%rcx)
movsd 32(%rdx), %xmm0
movsd %xmm0, 32(%rcx)
addl $1, %esi
addq $40, %rcx
cmpl %edi, %esi
jne .L15
.L13:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10initializeP5PointiiS0_, .-_Z10initializeP5PointiiS0_
.globl _Z13IntClusterMemPii
.type _Z13IntClusterMemPii, @function
_Z13IntClusterMemPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L18
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L20:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
.L18:
ret
.cfi_endproc
.LFE2060:
.size _Z13IntClusterMemPii, .-_Z13IntClusterMemPii
.globl _Z11calcNewMeanP5PointPiS0_ii
.type _Z11calcNewMeanP5PointPiS0_ii, @function
_Z11calcNewMeanP5PointPiS0_ii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, (%rsp)
movq %rsi, %r14
movq %rdx, 8(%rsp)
movl %ecx, %r13d
movl %r8d, %r12d
movslq %ecx, %rbp
leaq 0(,%rbp,4), %r15
addq %r15, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r15, %rdi
call malloc@PLT
movq %rax, %rsi
testl %r13d, %r13d
jle .L23
movq %rax, %rdx
movq %rbx, %rax
leaq (%rsi,%r15), %rcx
.L24:
movl $0, (%rdx)
movq $0x000000000, (%rax)
movq $0x000000000, 8(%rax)
movq $0x000000000, 16(%rax)
movq $0x000000000, 24(%rax)
movq $0x000000000, 32(%rax)
addq $4, %rdx
addq $40, %rax
cmpq %rcx, %rdx
jne .L24
testl %r12d, %r12d
jle .L33
.L32:
movq %r14, %rcx
movq (%rsp), %rdx
movslq %r12d, %r12
leaq (%r14,%r12,4), %rdi
.L26:
movslq (%rcx), %r8
leaq 0(,%r8,4), %rax
addl $1, (%rsi,%rax)
addq %r8, %rax
leaq (%rbx,%rax,8), %rax
movsd (%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rax)
movsd 8(%rax), %xmm0
addsd 8(%rdx), %xmm0
movsd %xmm0, 8(%rax)
movsd 16(%rax), %xmm0
addsd 16(%rdx), %xmm0
movsd %xmm0, 16(%rax)
movsd 24(%rax), %xmm0
addsd 24(%rdx), %xmm0
movsd %xmm0, 24(%rax)
movsd 32(%rax), %xmm0
addsd 32(%rdx), %xmm0
movsd %xmm0, 32(%rax)
addq $4, %rcx
addq $40, %rdx
cmpq %rdi, %rcx
jne .L26
testl %r13d, %r13d
jle .L22
.L33:
movq %rsi, %rcx
movq %rbx, %rdx
addq %r15, %rsi
movq %rbx, %rax
jmp .L30
.L28:
movq $0x000000000, (%rax)
movq $0x000000000, 8(%rax)
movq $0x000000000, 16(%rax)
movq $0x000000000, 24(%rax)
movq $0x000000000, 32(%rax)
.L29:
addq $4, %rcx
addq $40, %rax
cmpq %rsi, %rcx
je .L40
.L30:
movl (%rcx), %edi
testl %edi, %edi
je .L28
pxor %xmm0, %xmm0
cvtsi2sdl %edi, %xmm0
movsd (%rax), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%rax)
movsd 8(%rax), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rax)
movsd 16(%rax), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 16(%rax)
movsd 24(%rax), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 24(%rax)
movsd 32(%rax), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 32(%rax)
jmp .L29
.L40:
movq 8(%rsp), %rax
addq %rbp, %rbx
.L31:
movsd (%rdx), %xmm0
movsd %xmm0, (%rax)
movsd 8(%rdx), %xmm0
movsd %xmm0, 8(%rax)
movsd 16(%rdx), %xmm0
movsd %xmm0, 16(%rax)
movsd 24(%rdx), %xmm0
movsd %xmm0, 24(%rax)
movsd 32(%rdx), %xmm0
movsd %xmm0, 32(%rax)
addq $40, %rdx
addq $40, %rax
cmpq %rbx, %rdx
jne .L31
.L22:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
testl %r12d, %r12d
jg .L32
jmp .L22
.cfi_endproc
.LFE2061:
.size _Z11calcNewMeanP5PointPiS0_ii, .-_Z11calcNewMeanP5PointPiS0_ii
.globl _Z9chkConvrgPiS_if
.type _Z9chkConvrgPiS_if, @function
_Z9chkConvrgPiS_if:
.LFB2062:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
mulss %xmm0, %xmm1
testl %edx, %edx
jle .L44
movslq %edx, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %edx
.L43:
movl (%rdi,%rdx), %eax
subl (%rsi,%rdx), %eax
movl %eax, %ecx
negl %ecx
cmovns %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
comiss %xmm1, %xmm0
ja .L45
addq $4, %rdx
cmpq %r8, %rdx
jne .L43
movl $0, %eax
ret
.L44:
movl $0, %eax
ret
.L45:
movl $-1, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z9chkConvrgPiS_if, .-_Z9chkConvrgPiS_if
.globl _Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii
.type _Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii, @function
_Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13pointsClusterPiP5PointS1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii, .-_Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii
.globl _Z13pointsClusterPiP5PointS1_iii
.type _Z13pointsClusterPiP5PointS1_iii, @function
_Z13pointsClusterPiP5PointS1_iii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z13pointsClusterPiP5PointS1_iii, .-_Z13pointsClusterPiP5PointS1_iii
.section .rodata.str1.1
.LC3:
.string "Centroid_10.txt"
.LC4:
.string "Centroid_30.txt"
.LC5:
.string "Centroid_50.txt"
.LC6:
.string "Centroid_100.txt"
.LC7:
.string "Tolerancia = %f \n"
.LC8:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dbellidor/Comp_Molecular/master/Paper/CUDA/kmean_cuda.cu"
.section .rodata.str1.1
.LC10:
.string "CUDA error at %s:%d\n"
.LC11:
.string " %s\n"
.LC12:
.string "w"
.LC13:
.string "%.0f,%.0f,%.0f,%.0f,%.0f\n"
.LC14:
.string "%.0f,%.0f,%.0f,%.0f,%.0f,%d\n"
.LC15:
.string "Total Iteraciones = %d\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "CUDA:Tiempo total transcurrido en la ejecucion. k= %d con tolerancia= %f en clusters : %f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbp
movq %rsi, 72(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq 24(%rsi), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
pxor %xmm5, %xmm5
cvtss2sd %xmm0, %xmm5
movsd %xmm5, 64(%rsp)
movapd %xmm5, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 208(%rsp), %rdi
call cudaEventCreate@PLT
leaq 216(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 208(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rbp), %rdi
leaq .LC8(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq 92(%rsp), %rcx
leaq 88(%rsp), %rdx
leaq 84(%rsp), %rsi
movq %rax, %rdi
call _Z13readImageSizeP8_IO_FILEPiS1_S1_
movq 48(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 84(%rsp)
movl 88(%rsp), %eax
imull 92(%rsp), %eax
movl %eax, %r12d
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, %r14d
movq 40(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl %eax, %r13d
movslq %r12d, %rax
leaq 0(,%rax,4), %rbp
addq %rbp, %rax
leaq 0(,%rax,8), %r15
movq %r15, %rdi
call malloc@PLT
movl %r12d, 40(%rsp)
movl %r12d, %edx
movq %rax, 16(%rsp)
movq %rax, %rsi
movq %rbx, %rdi
call _Z10readPointsP8_IO_FILEP5Pointi
movq %rbx, %rdi
call fclose@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl 84(%rsp), %eax
movl %eax, 44(%rsp)
cltq
leaq (%rax,%rax,4), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%rsp)
movq 16(%rsp), %rcx
movl 40(%rsp), %edx
movl 44(%rsp), %esi
call _Z10initializeP5PointiiS0_
movl 40(%rsp), %esi
movq %r12, %rdi
call _Z13IntClusterMemPii
movl 40(%rsp), %esi
movq %rbx, %rdi
call _Z13IntClusterMemPii
leaq 128(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L85
leaq 136(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L86
leaq 112(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
movslq 84(%rsp), %rax
leaq (%rax,%rax,4), %rsi
salq $3, %rsi
leaq 120(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L88
leaq 144(%rsp), %rdi
call cudaEventCreate@PLT
leaq 152(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 144(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L89
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L90
movl $0, %esi
movq 152(%rsp), %rdi
call cudaEventRecord@PLT
movq 152(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 96(%rsp), %rdi
movq 152(%rsp), %rdx
movq 144(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 84(%rsp), %eax
cmpl $30, %eax
je .L78
leaq .LC5(%rip), %rcx
movq %rcx, 56(%rsp)
movl $63, %edx
cmpl $50, %eax
je .L62
cmpl $10, %eax
leaq .LC3(%rip), %rcx
leaq .LC6(%rip), %rdx
cmove %rcx, %rdx
movq %rdx, 56(%rsp)
movl $4, %edx
movl $87, %eax
cmovne %eax, %edx
.L62:
leal 1(%rdx), %eax
movl %eax, 44(%rsp)
movl $0, %r15d
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
jmp .L69
.L85:
movl $230, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
movl $231, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movl $232, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl $233, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl $240, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl $241, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
leaq .LC4(%rip), %rax
movq %rax, 56(%rsp)
movl $14, %edx
jmp .L62
.L92:
movl $273, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 184(%rsp), %rdi
call cudaEventRecord@PLT
movq 184(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 104(%rsp), %rdi
movq 184(%rsp), %rdx
movq 176(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 192(%rsp), %rdi
call cudaEventCreate@PLT
leaq 200(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 192(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 128(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L91
movl $0, %esi
movq 200(%rsp), %rdi
call cudaEventRecord@PLT
movq 200(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 108(%rsp), %rdi
movq 200(%rsp), %rdx
movq 192(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 40(%rsp), %r8d
movl 84(%rsp), %ecx
movq 8(%rsp), %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call _Z11calcNewMeanP5PointPiS0_ii
movl 44(%rsp), %ecx
cmpl %ecx, %r15d
je .L66
cmpl $0, 40(%rsp)
jle .L67
movl $0, %eax
.L68:
movl (%rbx,%rax), %edx
movl %edx, (%r12,%rax)
addq $4, %rax
cmpq %rax, %rbp
jne .L68
.L67:
addl $1, %r15d
.L69:
movq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 168(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 160(%rsp), %rdi
call cudaEventRecord@PLT
movslq 84(%rsp), %rax
leaq (%rax,%rax,4), %rdx
salq $3, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L92
movl $0, %esi
movq 168(%rsp), %rdi
call cudaEventRecord@PLT
movq 168(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 100(%rsp), %rdi
movq 168(%rsp), %rdx
movq 160(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 176(%rsp), %rdi
call cudaEventCreate@PLT
leaq 184(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 176(%rsp), %rdi
call cudaEventRecord@PLT
movl 32(%rsp), %eax
movl %eax, 224(%rsp)
movl 24(%rsp), %eax
movl %eax, 228(%rsp)
movl %r13d, %eax
addl 92(%rsp), %eax
subl $1, %eax
cltd
idivl %r13d
movl %eax, %ecx
movl %r14d, %eax
addl 88(%rsp), %eax
subl $1, %eax
cltd
idivl %r14d
movl %eax, 236(%rsp)
movl %ecx, 240(%rsp)
movl $1, 244(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 224(%rsp), %rdx
movl $1, %ecx
movq 236(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L64
movl 92(%rsp), %r9d
movl 88(%rsp), %r8d
movl 84(%rsp), %ecx
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
movq 128(%rsp), %rdi
call _Z46__device_stub__Z13pointsClusterPiP5PointS1_iiiPiP5PointS1_iii
jmp .L64
.L91:
movl $302, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L66:
movq 72(%rsp), %rax
movq 16(%rax), %rdi
leaq .LC12(%rip), %r13
movq %r13, %rsi
call fopen@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movq %r13, %rsi
movq 56(%rsp), %rdi
call fopen@PLT
movq %rax, 32(%rsp)
movl 84(%rsp), %ecx
leaq .LC0(%rip), %r13
movq %r13, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 88(%rsp), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 92(%rsp), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, 84(%rsp)
jle .L70
movq 8(%rsp), %r13
movl $0, %ecx
leaq .LC13(%rip), %r14
movl %r15d, 44(%rsp)
movq %r12, 48(%rsp)
movq 32(%rsp), %r15
movl %ecx, %r12d
.L71:
movsd 0(%r13), %xmm0
movsd 32(%r13), %xmm4
movsd 24(%r13), %xmm3
movsd 16(%r13), %xmm2
movsd 8(%r13), %xmm1
movq %r14, %rdx
movl $2, %esi
movq %r15, %rdi
movl $5, %eax
call __fprintf_chk@PLT
addl $1, %r12d
addq $40, %r13
cmpl %r12d, 84(%rsp)
jg .L71
movl 44(%rsp), %r15d
movq 48(%rsp), %r12
.L70:
cmpl $0, 40(%rsp)
jle .L72
movq %rbx, %r14
movq 16(%rsp), %r13
addq %rbx, %rbp
movl %r15d, 40(%rsp)
movq 24(%rsp), %r15
.L73:
movl (%r14), %eax
leal 1(%rax), %ecx
movsd 0(%r13), %xmm0
movsd 32(%r13), %xmm4
movsd 24(%r13), %xmm3
movsd 16(%r13), %xmm2
movsd 8(%r13), %xmm1
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $5, %eax
call __fprintf_chk@PLT
addq $4, %r14
addq $40, %r13
cmpq %rbp, %r14
jne .L73
movl 40(%rsp), %r15d
.L72:
movq 24(%rsp), %rdi
call fclose@PLT
movq 32(%rsp), %rdi
call fclose@PLT
movl $0, %esi
movq 216(%rsp), %rdi
call cudaEventRecord@PLT
movq 216(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 236(%rsp), %rdi
movq 216(%rsp), %rdx
movq 208(%rsp), %rsi
call cudaEventElapsedTime@PLT
leal -1(%r15), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movss 236(%rsp), %xmm1
divss .LC16(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movsd 64(%rsp), %xmm0
movl 84(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L93
movq 120(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L94
movq 112(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L95
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L96
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L93:
.cfi_restore_state
movl $351, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
movl $352, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L95:
movl $353, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z13pointsClusterPiP5PointS1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pointsClusterPiP5PointS1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC16:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
typedef struct {
double _r;
double _g;
double _b;
double _m;
double _n;
} Point;
#define CUDA_CALL(x) {if((x) != cudaSuccess){ \
printf("CUDA error at %s:%d\n",__FILE__,__LINE__); \
printf(" %s\n", cudaGetErrorString(cudaGetLastError())); \
exit(EXIT_FAILURE);}}
//Leer las dimensiones de la imagen a x b pixeles
void readImageSize(FILE *ifp,int* K,int* a,int* b) {
fscanf(ifp,"%d\n",K);
printf("%d\n",*K);
fscanf(ifp,"%d\n",a);
printf("%d\n",*a);
fscanf(ifp,"%d\n",b);
printf("%d\n",*b);
}
//Leer archivo ifp y lo almacena en el struct
void readPoints(FILE* ifp,Point *points, int num_points) {
int i;
for(i=0;i<num_points;i++) {
fscanf(ifp,"%lf,%lf,%lf,%lf,%lf", &points[i]._r, &points[i]._g, &points[i]._b, &points[i]._m, &points[i]._n);
}
}
//Inicializar puntos aleatorios como los medios (k numero de clusters)
void initialize(Point* mean,int K, int num_points, Point* points) {
int i, a, p=2;
srand(time(NULL));
for(i=0;i<K;i++) {
a = num_points/p;
//printf("\n num_points: %d\n", num_points/p);
mean[i]._r = points[a]._r;
mean[i]._g = points[a]._g;
mean[i]._b = points[a]._b;
mean[i]._m = points[a]._m;
mean[i]._n = points[a]._n;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
//printf("%lf,%lf,%lf,%lf,%lf\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
p++;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
}
}
//Todos los puntos sin clusters
void IntClusterMem(int *cluster, int num_points) {
int i;
for(i=0;i < num_points; i ++) {
cluster[i]=-1;
}
}
//Para calcular a que cluster pertenece el punto. (k numero de clusters)
__global__ void pointsCluster(int* after_cluster_d, Point* point_d,Point* Dmean,int K, int x, int y) {
int j, k, i;
j = blockIdx.x*blockDim.x+threadIdx.x;
k = blockIdx.y*blockDim.y+threadIdx.y;
int parent=0;
double dist=0;
int t = (k*(x)+j);
double minDist= sqrt((pow((point_d[t]._r-Dmean[0]._r),2)+pow((point_d[t]._g-Dmean[0]._g),2)+pow((point_d[t]._b-Dmean[0]._b),2)+pow((point_d[t]._m-Dmean[0]._m),2)+pow((point_d[t]._n-Dmean[0]._n),2)));
for(i=1;i<K;i++) {
dist = sqrt((pow((point_d[t]._r-Dmean[i]._r),2)+pow((point_d[t]._g-Dmean[i]._g),2)+pow((point_d[t]._b-Dmean[i]._b),2)+pow((point_d[t]._m-Dmean[i]._m),2)+pow((point_d[t]._n-Dmean[i]._n),2)));
if(minDist>=dist) {
parent=i;
minDist=dist;
}
}
after_cluster_d[t] = parent;
}
//Calcular nueva media
void calcNewMean(Point* points,int* cluster,Point* mean,int K,int num_points) {
Point* newMean=(Point*)malloc(sizeof(Point)*K);
int* members=(int*)malloc(sizeof(int)*(K));
int i;
for(i=0;i<K;i++) {
members[i]=0;
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
for(i=0;i<num_points;i++) {
members[cluster[i]]++;
newMean[cluster[i]]._r+=points[i]._r;
newMean[cluster[i]]._g+=points[i]._g;
newMean[cluster[i]]._b+=points[i]._b;
newMean[cluster[i]]._m+=points[i]._m;
newMean[cluster[i]]._n+=points[i]._n;
}
for(i=0;i<K;i++) {
if(members[i]!=0.0) {
newMean[i]._r/=members[i];
newMean[i]._g/=members[i];
newMean[i]._b/=members[i];
newMean[i]._m/=members[i];
newMean[i]._n/=members[i];
}
else {
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
}
for(i=0;i<K;i++) {
mean[i]._r=newMean[i]._r;
mean[i]._g=newMean[i]._g;
mean[i]._b=newMean[i]._b;
mean[i]._m=newMean[i]._m;
mean[i]._n=newMean[i]._n;
}
}
//Comprobamos la convergencia
//Comprueba que cada clúster de puntos permanece igual
int chkConvrg(int *before_clusters,int *after_cluster,int num_points, float tol) {
int i;
tol = num_points*tol;
for(i=0;i<num_points;i++) {
if(abs(before_clusters[i]-after_cluster[i])>tol) {
//check = abs(before_clusters[i]-after_cluster[i]);
//printf("check = %d, after_cluster[%d]=%d, before_clusters[%d]=%d\n",check,i,after_cluster[i],i,before_clusters[i]);
return -1;
}
}
return 0;
}
int main(int argc, char* argv[]) {
//Variables CPU
int K;
int num_points;
int * before_clusters;
int i;
int job_done=0;
int x,y,iter=0;
Point* mean;
Point* points;
int * after_cluster;
float tol;
//Variables GPU
Point* points_d;
Point* mean_d;
int * after_cluster_d;
int * before_cluster_d;
cudaEvent_t startinit, endinit, startmean, endmean, startcal, endcal, startindex, endindex;
cudaEvent_t start1, end1;
float timeinit, timemean, timecal, timeindex;
float time1;
//float totTime = 0;
tol = atof(argv[3]);
//iterations = atof(argv[3]);
//printf("Ingrese tolerancia: ");
//scanf("%f",&tol);
printf("Tolerancia = %f \n",tol);
cudaEventCreate(&start1);
cudaEventCreate(&end1);
cudaEventRecord(start1, 0);
//Leyendo archivo
FILE *ifp;
ifp=fopen(argv[1],"r");
readImageSize(ifp,&K,&x,&y);
K = atoi(argv[6]);
num_points = x*y;
int blockX=atoi(argv[4]);
int blockY=atoi(argv[5]);
//asignar memoria a la CPU
points=(Point*)malloc(sizeof(Point)*num_points);
readPoints(ifp,points,num_points);
fclose(ifp);
//printf("Entrada leida con exito \n");
before_clusters=(int*)malloc(sizeof(int)*num_points);
after_cluster=(int*)malloc(sizeof(int)*num_points);
mean=(Point*)malloc(sizeof(Point)*K);
//inicializando valores por defecto
initialize(mean,K, num_points, points);
IntClusterMem(before_clusters,num_points);
IntClusterMem(after_cluster,num_points);
CUDA_CALL(cudaMalloc((void**) &after_cluster_d, sizeof(int)*num_points));
CUDA_CALL(cudaMalloc((void**) &before_cluster_d, sizeof(int)*num_points));
CUDA_CALL(cudaMalloc((void**) &points_d, sizeof(Point)*num_points));
CUDA_CALL(cudaMalloc((void**) &mean_d, sizeof(Point)*K));
cudaEventCreate(&startinit);
cudaEventCreate(&endinit);
cudaEventRecord(startinit, 0);
//copiar los puntos al device
CUDA_CALL(cudaMemcpy(points_d, points, sizeof(Point)*num_points, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, cudaMemcpyHostToDevice));
cudaEventRecord(endinit, 0);
cudaEventSynchronize(endinit);
cudaEventElapsedTime(&timeinit, startinit, endinit);
int iter_max=0;
char *fcentroid;
if(K==10){
iter_max=4;
fcentroid="Centroid_10.txt";
}
else if(K==30){
iter_max=14;
fcentroid="Centroid_30.txt";
}
else if(K==50){
iter_max=63;
fcentroid="Centroid_50.txt";
}
else{
iter_max=87;
fcentroid="Centroid_100.txt";
}
while(1) {
cudaEventCreate(&startmean);
cudaEventCreate(&endmean);
cudaEventRecord(startmean, 0);
//copiar los centroides iniciales al device
CUDA_CALL(cudaMemcpy(mean_d, mean, sizeof(Point)*K, cudaMemcpyHostToDevice));
cudaEventRecord(endmean, 0);
cudaEventSynchronize(endmean);
cudaEventElapsedTime(&timemean, startmean, endmean);
//copia de memoria cuda
//CUDA_CALL(cudaMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(before_cluster_d, before_clusters, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(x_d, &x, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(y_d, &y, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(K_d, &K, sizeof(int), cudaMemcpyHostToDevice));
cudaEventCreate(&startcal);
cudaEventCreate(&endcal);
cudaEventRecord(startcal, 0);
dim3 block(blockX, blockY);
dim3 grid((x+blockX-1)/blockX, (y+blockY-1)/blockY);
pointsCluster<<<grid,block>>>(after_cluster_d, points_d,mean_d,K,x,y);
cudaDeviceSynchronize();
cudaEventRecord(endcal, 0);
cudaEventSynchronize(endcal);
cudaEventElapsedTime(&timecal, startcal, endcal);
cudaEventCreate(&startindex);
cudaEventCreate(&endindex);
cudaEventRecord(startindex, 0);
CUDA_CALL(cudaMemcpy(after_cluster, after_cluster_d, sizeof(int)*num_points, cudaMemcpyDeviceToHost));
cudaEventRecord(endindex, 0);
cudaEventSynchronize(endindex);
cudaEventElapsedTime(&timeindex, startindex, endindex);
calcNewMean(points,after_cluster,mean,K,num_points);
//printf("Nuevos centroides son calculados!\n");
if(iter>iter_max) {
// printf("El algoritmo kmeans converge con = %d!\n",iter);
job_done=1;
}
else {
//printf("No converge!\n");
for(i=0;i<num_points;i++) {
//printf("1 after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
before_clusters[i]=after_cluster[i];
//printf("after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
}
}
if(job_done==1)
break;
++iter;
}
//Salida en archivos
FILE* ofp=fopen(argv[2],"w");
FILE* ofpc=fopen(fcentroid,"w");
fprintf(ofp,"%d\n",K);
fprintf(ofp,"%d\n",x);
fprintf(ofp,"%d\n",y);
for(i=0;i<K;i++)
fprintf(ofpc,"%.0f,%.0f,%.0f,%.0f,%.0f\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
for(i=0;i<num_points;i++)
fprintf(ofp,"%.0f,%.0f,%.0f,%.0f,%.0f,%d\n",points[i]._r,points[i]._g,points[i]._b,points[i]._m,points[i]._n,after_cluster[i]+1);
fclose(ofp);
fclose(ofpc);
cudaEventRecord(end1, 0);
cudaEventSynchronize(end1);
cudaEventElapsedTime(&time1, start1, end1);
printf("Total Iteraciones = %d\n",iter-1);
printf("CUDA:Tiempo total transcurrido en la ejecucion. k= %d con tolerancia= %f en clusters : %f sec\n", K,tol,time1/1000);
//printf("Tiempo Total : %f\t sec\n",time1/1000);
CUDA_CALL(cudaFree(after_cluster_d));
CUDA_CALL(cudaFree(mean_d));
CUDA_CALL(cudaFree(points_d));
free(before_clusters);
free(mean);
free(points);
free(after_cluster);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
typedef struct {
double _r;
double _g;
double _b;
double _m;
double _n;
} Point;
#define CUDA_CALL(x) {if((x) != hipSuccess){ \
printf("CUDA error at %s:%d\n",__FILE__,__LINE__); \
printf(" %s\n", hipGetErrorString(hipGetLastError())); \
exit(EXIT_FAILURE);}}
//Leer las dimensiones de la imagen a x b pixeles
void readImageSize(FILE *ifp,int* K,int* a,int* b) {
fscanf(ifp,"%d\n",K);
printf("%d\n",*K);
fscanf(ifp,"%d\n",a);
printf("%d\n",*a);
fscanf(ifp,"%d\n",b);
printf("%d\n",*b);
}
//Leer archivo ifp y lo almacena en el struct
void readPoints(FILE* ifp,Point *points, int num_points) {
int i;
for(i=0;i<num_points;i++) {
fscanf(ifp,"%lf,%lf,%lf,%lf,%lf", &points[i]._r, &points[i]._g, &points[i]._b, &points[i]._m, &points[i]._n);
}
}
//Inicializar puntos aleatorios como los medios (k numero de clusters)
void initialize(Point* mean,int K, int num_points, Point* points) {
int i, a, p=2;
srand(time(NULL));
for(i=0;i<K;i++) {
a = num_points/p;
//printf("\n num_points: %d\n", num_points/p);
mean[i]._r = points[a]._r;
mean[i]._g = points[a]._g;
mean[i]._b = points[a]._b;
mean[i]._m = points[a]._m;
mean[i]._n = points[a]._n;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
//printf("%lf,%lf,%lf,%lf,%lf\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
p++;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
}
}
//Todos los puntos sin clusters
void IntClusterMem(int *cluster, int num_points) {
int i;
for(i=0;i < num_points; i ++) {
cluster[i]=-1;
}
}
//Para calcular a que cluster pertenece el punto. (k numero de clusters)
__global__ void pointsCluster(int* after_cluster_d, Point* point_d,Point* Dmean,int K, int x, int y) {
int j, k, i;
j = blockIdx.x*blockDim.x+threadIdx.x;
k = blockIdx.y*blockDim.y+threadIdx.y;
int parent=0;
double dist=0;
int t = (k*(x)+j);
double minDist= sqrt((pow((point_d[t]._r-Dmean[0]._r),2)+pow((point_d[t]._g-Dmean[0]._g),2)+pow((point_d[t]._b-Dmean[0]._b),2)+pow((point_d[t]._m-Dmean[0]._m),2)+pow((point_d[t]._n-Dmean[0]._n),2)));
for(i=1;i<K;i++) {
dist = sqrt((pow((point_d[t]._r-Dmean[i]._r),2)+pow((point_d[t]._g-Dmean[i]._g),2)+pow((point_d[t]._b-Dmean[i]._b),2)+pow((point_d[t]._m-Dmean[i]._m),2)+pow((point_d[t]._n-Dmean[i]._n),2)));
if(minDist>=dist) {
parent=i;
minDist=dist;
}
}
after_cluster_d[t] = parent;
}
//Calcular nueva media
void calcNewMean(Point* points,int* cluster,Point* mean,int K,int num_points) {
Point* newMean=(Point*)malloc(sizeof(Point)*K);
int* members=(int*)malloc(sizeof(int)*(K));
int i;
for(i=0;i<K;i++) {
members[i]=0;
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
for(i=0;i<num_points;i++) {
members[cluster[i]]++;
newMean[cluster[i]]._r+=points[i]._r;
newMean[cluster[i]]._g+=points[i]._g;
newMean[cluster[i]]._b+=points[i]._b;
newMean[cluster[i]]._m+=points[i]._m;
newMean[cluster[i]]._n+=points[i]._n;
}
for(i=0;i<K;i++) {
if(members[i]!=0.0) {
newMean[i]._r/=members[i];
newMean[i]._g/=members[i];
newMean[i]._b/=members[i];
newMean[i]._m/=members[i];
newMean[i]._n/=members[i];
}
else {
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
}
for(i=0;i<K;i++) {
mean[i]._r=newMean[i]._r;
mean[i]._g=newMean[i]._g;
mean[i]._b=newMean[i]._b;
mean[i]._m=newMean[i]._m;
mean[i]._n=newMean[i]._n;
}
}
//Comprobamos la convergencia
//Comprueba que cada clúster de puntos permanece igual
int chkConvrg(int *before_clusters,int *after_cluster,int num_points, float tol) {
int i;
tol = num_points*tol;
for(i=0;i<num_points;i++) {
if(abs(before_clusters[i]-after_cluster[i])>tol) {
//check = abs(before_clusters[i]-after_cluster[i]);
//printf("check = %d, after_cluster[%d]=%d, before_clusters[%d]=%d\n",check,i,after_cluster[i],i,before_clusters[i]);
return -1;
}
}
return 0;
}
int main(int argc, char* argv[]) {
//Variables CPU
int K;
int num_points;
int * before_clusters;
int i;
int job_done=0;
int x,y,iter=0;
Point* mean;
Point* points;
int * after_cluster;
float tol;
//Variables GPU
Point* points_d;
Point* mean_d;
int * after_cluster_d;
int * before_cluster_d;
hipEvent_t startinit, endinit, startmean, endmean, startcal, endcal, startindex, endindex;
hipEvent_t start1, end1;
float timeinit, timemean, timecal, timeindex;
float time1;
//float totTime = 0;
tol = atof(argv[3]);
//iterations = atof(argv[3]);
//printf("Ingrese tolerancia: ");
//scanf("%f",&tol);
printf("Tolerancia = %f \n",tol);
hipEventCreate(&start1);
hipEventCreate(&end1);
hipEventRecord(start1, 0);
//Leyendo archivo
FILE *ifp;
ifp=fopen(argv[1],"r");
readImageSize(ifp,&K,&x,&y);
K = atoi(argv[6]);
num_points = x*y;
int blockX=atoi(argv[4]);
int blockY=atoi(argv[5]);
//asignar memoria a la CPU
points=(Point*)malloc(sizeof(Point)*num_points);
readPoints(ifp,points,num_points);
fclose(ifp);
//printf("Entrada leida con exito \n");
before_clusters=(int*)malloc(sizeof(int)*num_points);
after_cluster=(int*)malloc(sizeof(int)*num_points);
mean=(Point*)malloc(sizeof(Point)*K);
//inicializando valores por defecto
initialize(mean,K, num_points, points);
IntClusterMem(before_clusters,num_points);
IntClusterMem(after_cluster,num_points);
CUDA_CALL(hipMalloc((void**) &after_cluster_d, sizeof(int)*num_points));
CUDA_CALL(hipMalloc((void**) &before_cluster_d, sizeof(int)*num_points));
CUDA_CALL(hipMalloc((void**) &points_d, sizeof(Point)*num_points));
CUDA_CALL(hipMalloc((void**) &mean_d, sizeof(Point)*K));
hipEventCreate(&startinit);
hipEventCreate(&endinit);
hipEventRecord(startinit, 0);
//copiar los puntos al device
CUDA_CALL(hipMemcpy(points_d, points, sizeof(Point)*num_points, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, hipMemcpyHostToDevice));
hipEventRecord(endinit, 0);
hipEventSynchronize(endinit);
hipEventElapsedTime(&timeinit, startinit, endinit);
int iter_max=0;
char *fcentroid;
if(K==10){
iter_max=4;
fcentroid="Centroid_10.txt";
}
else if(K==30){
iter_max=14;
fcentroid="Centroid_30.txt";
}
else if(K==50){
iter_max=63;
fcentroid="Centroid_50.txt";
}
else{
iter_max=87;
fcentroid="Centroid_100.txt";
}
while(1) {
hipEventCreate(&startmean);
hipEventCreate(&endmean);
hipEventRecord(startmean, 0);
//copiar los centroides iniciales al device
CUDA_CALL(hipMemcpy(mean_d, mean, sizeof(Point)*K, hipMemcpyHostToDevice));
hipEventRecord(endmean, 0);
hipEventSynchronize(endmean);
hipEventElapsedTime(&timemean, startmean, endmean);
//copia de memoria cuda
//CUDA_CALL(cudaMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(before_cluster_d, before_clusters, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(x_d, &x, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(y_d, &y, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(K_d, &K, sizeof(int), cudaMemcpyHostToDevice));
hipEventCreate(&startcal);
hipEventCreate(&endcal);
hipEventRecord(startcal, 0);
dim3 block(blockX, blockY);
dim3 grid((x+blockX-1)/blockX, (y+blockY-1)/blockY);
pointsCluster<<<grid,block>>>(after_cluster_d, points_d,mean_d,K,x,y);
hipDeviceSynchronize();
hipEventRecord(endcal, 0);
hipEventSynchronize(endcal);
hipEventElapsedTime(&timecal, startcal, endcal);
hipEventCreate(&startindex);
hipEventCreate(&endindex);
hipEventRecord(startindex, 0);
CUDA_CALL(hipMemcpy(after_cluster, after_cluster_d, sizeof(int)*num_points, hipMemcpyDeviceToHost));
hipEventRecord(endindex, 0);
hipEventSynchronize(endindex);
hipEventElapsedTime(&timeindex, startindex, endindex);
calcNewMean(points,after_cluster,mean,K,num_points);
//printf("Nuevos centroides son calculados!\n");
if(iter>iter_max) {
// printf("El algoritmo kmeans converge con = %d!\n",iter);
job_done=1;
}
else {
//printf("No converge!\n");
for(i=0;i<num_points;i++) {
//printf("1 after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
before_clusters[i]=after_cluster[i];
//printf("after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
}
}
if(job_done==1)
break;
++iter;
}
//Salida en archivos
FILE* ofp=fopen(argv[2],"w");
FILE* ofpc=fopen(fcentroid,"w");
fprintf(ofp,"%d\n",K);
fprintf(ofp,"%d\n",x);
fprintf(ofp,"%d\n",y);
for(i=0;i<K;i++)
fprintf(ofpc,"%.0f,%.0f,%.0f,%.0f,%.0f\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
for(i=0;i<num_points;i++)
fprintf(ofp,"%.0f,%.0f,%.0f,%.0f,%.0f,%d\n",points[i]._r,points[i]._g,points[i]._b,points[i]._m,points[i]._n,after_cluster[i]+1);
fclose(ofp);
fclose(ofpc);
hipEventRecord(end1, 0);
hipEventSynchronize(end1);
hipEventElapsedTime(&time1, start1, end1);
printf("Total Iteraciones = %d\n",iter-1);
printf("CUDA:Tiempo total transcurrido en la ejecucion. k= %d con tolerancia= %f en clusters : %f sec\n", K,tol,time1/1000);
//printf("Tiempo Total : %f\t sec\n",time1/1000);
CUDA_CALL(hipFree(after_cluster_d));
CUDA_CALL(hipFree(mean_d));
CUDA_CALL(hipFree(points_d));
free(before_clusters);
free(mean);
free(points);
free(after_cluster);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
typedef struct {
double _r;
double _g;
double _b;
double _m;
double _n;
} Point;
#define CUDA_CALL(x) {if((x) != hipSuccess){ \
printf("CUDA error at %s:%d\n",__FILE__,__LINE__); \
printf(" %s\n", hipGetErrorString(hipGetLastError())); \
exit(EXIT_FAILURE);}}
//Leer las dimensiones de la imagen a x b pixeles
void readImageSize(FILE *ifp,int* K,int* a,int* b) {
fscanf(ifp,"%d\n",K);
printf("%d\n",*K);
fscanf(ifp,"%d\n",a);
printf("%d\n",*a);
fscanf(ifp,"%d\n",b);
printf("%d\n",*b);
}
//Leer archivo ifp y lo almacena en el struct
void readPoints(FILE* ifp,Point *points, int num_points) {
int i;
for(i=0;i<num_points;i++) {
fscanf(ifp,"%lf,%lf,%lf,%lf,%lf", &points[i]._r, &points[i]._g, &points[i]._b, &points[i]._m, &points[i]._n);
}
}
//Inicializar puntos aleatorios como los medios (k numero de clusters)
void initialize(Point* mean,int K, int num_points, Point* points) {
int i, a, p=2;
srand(time(NULL));
for(i=0;i<K;i++) {
a = num_points/p;
//printf("\n num_points: %d\n", num_points/p);
mean[i]._r = points[a]._r;
mean[i]._g = points[a]._g;
mean[i]._b = points[a]._b;
mean[i]._m = points[a]._m;
mean[i]._n = points[a]._n;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
//printf("%lf,%lf,%lf,%lf,%lf\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
p++;
/*mean[i]._r=((double)(rand()%1000))/1000;
mean[i]._g=((double)(2*rand()%1000))/1000;
mean[i]._b=((double)(3*rand()%1000))/1000;
mean[i]._m=((double)(4*rand()%1000))/1000;
mean[i]._n=((double)(5*rand()%1000))/1000;*/
}
}
//Todos los puntos sin clusters
void IntClusterMem(int *cluster, int num_points) {
int i;
for(i=0;i < num_points; i ++) {
cluster[i]=-1;
}
}
//Para calcular a que cluster pertenece el punto. (k numero de clusters)
__global__ void pointsCluster(int* after_cluster_d, Point* point_d,Point* Dmean,int K, int x, int y) {
int j, k, i;
j = blockIdx.x*blockDim.x+threadIdx.x;
k = blockIdx.y*blockDim.y+threadIdx.y;
int parent=0;
double dist=0;
int t = (k*(x)+j);
double minDist= sqrt((pow((point_d[t]._r-Dmean[0]._r),2)+pow((point_d[t]._g-Dmean[0]._g),2)+pow((point_d[t]._b-Dmean[0]._b),2)+pow((point_d[t]._m-Dmean[0]._m),2)+pow((point_d[t]._n-Dmean[0]._n),2)));
for(i=1;i<K;i++) {
dist = sqrt((pow((point_d[t]._r-Dmean[i]._r),2)+pow((point_d[t]._g-Dmean[i]._g),2)+pow((point_d[t]._b-Dmean[i]._b),2)+pow((point_d[t]._m-Dmean[i]._m),2)+pow((point_d[t]._n-Dmean[i]._n),2)));
if(minDist>=dist) {
parent=i;
minDist=dist;
}
}
after_cluster_d[t] = parent;
}
//Calcular nueva media
void calcNewMean(Point* points,int* cluster,Point* mean,int K,int num_points) {
Point* newMean=(Point*)malloc(sizeof(Point)*K);
int* members=(int*)malloc(sizeof(int)*(K));
int i;
for(i=0;i<K;i++) {
members[i]=0;
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
for(i=0;i<num_points;i++) {
members[cluster[i]]++;
newMean[cluster[i]]._r+=points[i]._r;
newMean[cluster[i]]._g+=points[i]._g;
newMean[cluster[i]]._b+=points[i]._b;
newMean[cluster[i]]._m+=points[i]._m;
newMean[cluster[i]]._n+=points[i]._n;
}
for(i=0;i<K;i++) {
if(members[i]!=0.0) {
newMean[i]._r/=members[i];
newMean[i]._g/=members[i];
newMean[i]._b/=members[i];
newMean[i]._m/=members[i];
newMean[i]._n/=members[i];
}
else {
newMean[i]._r=0;
newMean[i]._g=0;
newMean[i]._b=0;
newMean[i]._m=0;
newMean[i]._n=0;
}
}
for(i=0;i<K;i++) {
mean[i]._r=newMean[i]._r;
mean[i]._g=newMean[i]._g;
mean[i]._b=newMean[i]._b;
mean[i]._m=newMean[i]._m;
mean[i]._n=newMean[i]._n;
}
}
//Comprobamos la convergencia
//Comprueba que cada clúster de puntos permanece igual
int chkConvrg(int *before_clusters,int *after_cluster,int num_points, float tol) {
int i;
tol = num_points*tol;
for(i=0;i<num_points;i++) {
if(abs(before_clusters[i]-after_cluster[i])>tol) {
//check = abs(before_clusters[i]-after_cluster[i]);
//printf("check = %d, after_cluster[%d]=%d, before_clusters[%d]=%d\n",check,i,after_cluster[i],i,before_clusters[i]);
return -1;
}
}
return 0;
}
int main(int argc, char* argv[]) {
//Variables CPU
int K;
int num_points;
int * before_clusters;
int i;
int job_done=0;
int x,y,iter=0;
Point* mean;
Point* points;
int * after_cluster;
float tol;
//Variables GPU
Point* points_d;
Point* mean_d;
int * after_cluster_d;
int * before_cluster_d;
hipEvent_t startinit, endinit, startmean, endmean, startcal, endcal, startindex, endindex;
hipEvent_t start1, end1;
float timeinit, timemean, timecal, timeindex;
float time1;
//float totTime = 0;
tol = atof(argv[3]);
//iterations = atof(argv[3]);
//printf("Ingrese tolerancia: ");
//scanf("%f",&tol);
printf("Tolerancia = %f \n",tol);
hipEventCreate(&start1);
hipEventCreate(&end1);
hipEventRecord(start1, 0);
//Leyendo archivo
FILE *ifp;
ifp=fopen(argv[1],"r");
readImageSize(ifp,&K,&x,&y);
K = atoi(argv[6]);
num_points = x*y;
int blockX=atoi(argv[4]);
int blockY=atoi(argv[5]);
//asignar memoria a la CPU
points=(Point*)malloc(sizeof(Point)*num_points);
readPoints(ifp,points,num_points);
fclose(ifp);
//printf("Entrada leida con exito \n");
before_clusters=(int*)malloc(sizeof(int)*num_points);
after_cluster=(int*)malloc(sizeof(int)*num_points);
mean=(Point*)malloc(sizeof(Point)*K);
//inicializando valores por defecto
initialize(mean,K, num_points, points);
IntClusterMem(before_clusters,num_points);
IntClusterMem(after_cluster,num_points);
CUDA_CALL(hipMalloc((void**) &after_cluster_d, sizeof(int)*num_points));
CUDA_CALL(hipMalloc((void**) &before_cluster_d, sizeof(int)*num_points));
CUDA_CALL(hipMalloc((void**) &points_d, sizeof(Point)*num_points));
CUDA_CALL(hipMalloc((void**) &mean_d, sizeof(Point)*K));
hipEventCreate(&startinit);
hipEventCreate(&endinit);
hipEventRecord(startinit, 0);
//copiar los puntos al device
CUDA_CALL(hipMemcpy(points_d, points, sizeof(Point)*num_points, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, hipMemcpyHostToDevice));
hipEventRecord(endinit, 0);
hipEventSynchronize(endinit);
hipEventElapsedTime(&timeinit, startinit, endinit);
int iter_max=0;
char *fcentroid;
if(K==10){
iter_max=4;
fcentroid="Centroid_10.txt";
}
else if(K==30){
iter_max=14;
fcentroid="Centroid_30.txt";
}
else if(K==50){
iter_max=63;
fcentroid="Centroid_50.txt";
}
else{
iter_max=87;
fcentroid="Centroid_100.txt";
}
while(1) {
hipEventCreate(&startmean);
hipEventCreate(&endmean);
hipEventRecord(startmean, 0);
//copiar los centroides iniciales al device
CUDA_CALL(hipMemcpy(mean_d, mean, sizeof(Point)*K, hipMemcpyHostToDevice));
hipEventRecord(endmean, 0);
hipEventSynchronize(endmean);
hipEventElapsedTime(&timemean, startmean, endmean);
//copia de memoria cuda
//CUDA_CALL(cudaMemcpy(after_cluster_d, after_cluster, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(before_cluster_d, before_clusters, sizeof(int)*num_points, cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(x_d, &x, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(y_d, &y, sizeof(int), cudaMemcpyHostToDevice));
//CUDA_CALL(cudaMemcpy(K_d, &K, sizeof(int), cudaMemcpyHostToDevice));
hipEventCreate(&startcal);
hipEventCreate(&endcal);
hipEventRecord(startcal, 0);
dim3 block(blockX, blockY);
dim3 grid((x+blockX-1)/blockX, (y+blockY-1)/blockY);
pointsCluster<<<grid,block>>>(after_cluster_d, points_d,mean_d,K,x,y);
hipDeviceSynchronize();
hipEventRecord(endcal, 0);
hipEventSynchronize(endcal);
hipEventElapsedTime(&timecal, startcal, endcal);
hipEventCreate(&startindex);
hipEventCreate(&endindex);
hipEventRecord(startindex, 0);
CUDA_CALL(hipMemcpy(after_cluster, after_cluster_d, sizeof(int)*num_points, hipMemcpyDeviceToHost));
hipEventRecord(endindex, 0);
hipEventSynchronize(endindex);
hipEventElapsedTime(&timeindex, startindex, endindex);
calcNewMean(points,after_cluster,mean,K,num_points);
//printf("Nuevos centroides son calculados!\n");
if(iter>iter_max) {
// printf("El algoritmo kmeans converge con = %d!\n",iter);
job_done=1;
}
else {
//printf("No converge!\n");
for(i=0;i<num_points;i++) {
//printf("1 after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
before_clusters[i]=after_cluster[i];
//printf("after_cluster[%d]=%d, before_clusters[%d]=%d\n",i,after_cluster[i],i,before_clusters[i]);
}
}
if(job_done==1)
break;
++iter;
}
//Salida en archivos
FILE* ofp=fopen(argv[2],"w");
FILE* ofpc=fopen(fcentroid,"w");
fprintf(ofp,"%d\n",K);
fprintf(ofp,"%d\n",x);
fprintf(ofp,"%d\n",y);
for(i=0;i<K;i++)
fprintf(ofpc,"%.0f,%.0f,%.0f,%.0f,%.0f\n",mean[i]._r,mean[i]._g,mean[i]._b,mean[i]._m,mean[i]._n);
for(i=0;i<num_points;i++)
fprintf(ofp,"%.0f,%.0f,%.0f,%.0f,%.0f,%d\n",points[i]._r,points[i]._g,points[i]._b,points[i]._m,points[i]._n,after_cluster[i]+1);
fclose(ofp);
fclose(ofpc);
hipEventRecord(end1, 0);
hipEventSynchronize(end1);
hipEventElapsedTime(&time1, start1, end1);
printf("Total Iteraciones = %d\n",iter-1);
printf("CUDA:Tiempo total transcurrido en la ejecucion. k= %d con tolerancia= %f en clusters : %f sec\n", K,tol,time1/1000);
//printf("Tiempo Total : %f\t sec\n",time1/1000);
CUDA_CALL(hipFree(after_cluster_d));
CUDA_CALL(hipFree(mean_d));
CUDA_CALL(hipFree(points_d));
free(before_clusters);
free(mean);
free(points);
free(after_cluster);
return 0;
} | .text
.file "kmean_cuda.hip"
.globl _Z13readImageSizeP8_IO_FILEPiS1_S1_ # -- Begin function _Z13readImageSizeP8_IO_FILEPiS1_S1_
.p2align 4, 0x90
.type _Z13readImageSizeP8_IO_FILEPiS1_S1_,@function
_Z13readImageSizeP8_IO_FILEPiS1_S1_: # @_Z13readImageSizeP8_IO_FILEPiS1_S1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r14
movl $.L.str, %esi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl (%r12), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z13readImageSizeP8_IO_FILEPiS1_S1_, .Lfunc_end0-_Z13readImageSizeP8_IO_FILEPiS1_S1_
.cfi_endproc
# -- End function
.globl _Z10readPointsP8_IO_FILEP5Pointi # -- Begin function _Z10readPointsP8_IO_FILEP5Pointi
.p2align 4, 0x90
.type _Z10readPointsP8_IO_FILEP5Pointi,@function
_Z10readPointsP8_IO_FILEP5Pointi: # @_Z10readPointsP8_IO_FILEP5Pointi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 8(%rbx), %rcx
leaq 16(%rbx), %r8
leaq 24(%rbx), %r9
leaq 32(%rbx), %rax
movq %rax, (%rsp)
movl $.L.str.1, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $40, %rbx
decq %r15
jne .LBB1_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10readPointsP8_IO_FILEP5Pointi, .Lfunc_end1-_Z10readPointsP8_IO_FILEP5Pointi
.cfi_endproc
# -- End function
.globl _Z10initializeP5PointiiS0_ # -- Begin function _Z10initializeP5PointiiS0_
.p2align 4, 0x90
.type _Z10initializeP5PointiiS0_,@function
_Z10initializeP5PointiiS0_: # @_Z10initializeP5PointiiS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
shlq $3, %rax
leaq (%rax,%rax,4), %rcx
movl $2, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
cltd
idivl %esi
cltq
leaq (%rax,%rax,4), %rax
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r14,%rdi)
movsd 8(%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 8(%r14,%rdi)
movsd 16(%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%r14,%rdi)
movsd 24(%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%r14,%rdi)
movsd 32(%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 32(%r14,%rdi)
incl %esi
addq $40, %rdi
cmpq %rdi, %rcx
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10initializeP5PointiiS0_, .Lfunc_end2-_Z10initializeP5PointiiS0_
.cfi_endproc
# -- End function
.globl _Z13IntClusterMemPii # -- Begin function _Z13IntClusterMemPii
.p2align 4, 0x90
.type _Z13IntClusterMemPii,@function
_Z13IntClusterMemPii: # @_Z13IntClusterMemPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %edx
shlq $2, %rdx
movl $255, %esi
jmp memset@PLT # TAILCALL
.LBB3_1: # %._crit_edge
retq
.Lfunc_end3:
.size _Z13IntClusterMemPii, .Lfunc_end3-_Z13IntClusterMemPii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__pointsClusterPiP5PointS1_iii # -- Begin function _Z28__device_stub__pointsClusterPiP5PointS1_iii
.p2align 4, 0x90
.type _Z28__device_stub__pointsClusterPiP5PointS1_iii,@function
_Z28__device_stub__pointsClusterPiP5PointS1_iii: # @_Z28__device_stub__pointsClusterPiP5PointS1_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13pointsClusterPiP5PointS1_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z28__device_stub__pointsClusterPiP5PointS1_iii, .Lfunc_end4-_Z28__device_stub__pointsClusterPiP5PointS1_iii
.cfi_endproc
# -- End function
.globl _Z11calcNewMeanP5PointPiS0_ii # -- Begin function _Z11calcNewMeanP5PointPiS0_ii
.p2align 4, 0x90
.type _Z11calcNewMeanP5PointPiS0_ii,@function
_Z11calcNewMeanP5PointPiS0_ii: # @_Z11calcNewMeanP5PointPiS0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 8(%rsp) # 4-byte Spill
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movslq %ecx, %r15
movq %r15, 16(%rsp) # 8-byte Spill
leaq (,%r15,8), %rax
leaq (%rax,%rax,4), %rdi
callq malloc
movq %rax, %r14
leaq (,%r15,4), %rdi
callq malloc
movq %rax, %r15
movl %ebp, 12(%rsp) # 4-byte Spill
movl %ebp, %ebp
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB5_2
# %bb.1: # %.lr.ph.preheader
leaq (,%rbp,4), %rdx
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
leaq (,%rbp,8), %rax
leaq (%rax,%rax,4), %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB5_2: # %.preheader108
movl 8(%rsp), %eax # 4-byte Reload
testl %eax, %eax
jle .LBB5_5
# %bb.3: # %.lr.ph111.preheader
movl %eax, %eax
addq $32, %r13
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_4: # %.lr.ph111
# =>This Inner Loop Header: Depth=1
movslq (%r12,%rcx,4), %rdx
incl (%r15,%rdx,4)
movsd -32(%r13), %xmm0 # xmm0 = mem[0],zero
leaq (%rdx,%rdx,4), %rdx
addsd (%r14,%rdx,8), %xmm0
movsd %xmm0, (%r14,%rdx,8)
movsd -24(%r13), %xmm0 # xmm0 = mem[0],zero
addsd 8(%r14,%rdx,8), %xmm0
movsd %xmm0, 8(%r14,%rdx,8)
movsd -16(%r13), %xmm0 # xmm0 = mem[0],zero
addsd 16(%r14,%rdx,8), %xmm0
movsd %xmm0, 16(%r14,%rdx,8)
movsd -8(%r13), %xmm0 # xmm0 = mem[0],zero
addsd 24(%r14,%rdx,8), %xmm0
movsd %xmm0, 24(%r14,%rdx,8)
movsd (%r13), %xmm0 # xmm0 = mem[0],zero
addsd 32(%r14,%rdx,8), %xmm0
movsd %xmm0, 32(%r14,%rdx,8)
incq %rcx
addq $40, %r13
cmpq %rcx, %rax
jne .LBB5_4
.LBB5_5: # %.preheader107
movl 12(%rsp), %esi # 4-byte Reload
testl %esi, %esi
jle .LBB5_9
# %bb.6: # %.lr.ph113.preheader
xorl %eax, %eax
xorpd %xmm0, %xmm0
movq %r14, %rcx
jmp .LBB5_7
.p2align 4, 0x90
.LBB5_13: # in Loop: Header=BB5_7 Depth=1
movupd %xmm0, 16(%rcx)
movupd %xmm0, (%rcx)
movq $0, 32(%rcx)
.LBB5_14: # in Loop: Header=BB5_7 Depth=1
incq %rax
addq $40, %rcx
cmpq %rax, %rbp
je .LBB5_9
.LBB5_7: # %.lr.ph113
# =>This Inner Loop Header: Depth=1
movl (%r15,%rax,4), %edx
testl %edx, %edx
je .LBB5_13
# %bb.8: # in Loop: Header=BB5_7 Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %edx, %xmm1
movsd (%rcx), %xmm2 # xmm2 = mem[0],zero
movsd 8(%rcx), %xmm3 # xmm3 = mem[0],zero
divsd %xmm1, %xmm2
movsd %xmm2, (%rcx)
divsd %xmm1, %xmm3
movsd %xmm3, 8(%rcx)
movsd 16(%rcx), %xmm2 # xmm2 = mem[0],zero
divsd %xmm1, %xmm2
movsd %xmm2, 16(%rcx)
movsd 24(%rcx), %xmm2 # xmm2 = mem[0],zero
divsd %xmm1, %xmm2
movsd %xmm2, 24(%rcx)
movsd 32(%rcx), %xmm2 # xmm2 = mem[0],zero
divsd %xmm1, %xmm2
movsd %xmm2, 32(%rcx)
jmp .LBB5_14
.LBB5_9: # %.preheader
testl %esi, %esi
jle .LBB5_12
# %bb.10: # %.lr.ph115.preheader
shlq $3, %rbp
leaq (,%rbp,4), %rax
addq %rbp, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_11: # %.lr.ph115
# =>This Inner Loop Header: Depth=1
movsd (%r14,%rcx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rbx,%rcx)
movsd 8(%r14,%rcx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 8(%rbx,%rcx)
movsd 16(%r14,%rcx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rbx,%rcx)
movsd 24(%r14,%rcx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%rbx,%rcx)
movsd 32(%r14,%rcx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 32(%rbx,%rcx)
addq $40, %rcx
cmpq %rcx, %rax
jne .LBB5_11
.LBB5_12: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11calcNewMeanP5PointPiS0_ii, .Lfunc_end5-_Z11calcNewMeanP5PointPiS0_ii
.cfi_endproc
# -- End function
.globl _Z9chkConvrgPiS_if # -- Begin function _Z9chkConvrgPiS_if
.p2align 4, 0x90
.type _Z9chkConvrgPiS_if,@function
_Z9chkConvrgPiS_if: # @_Z9chkConvrgPiS_if
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB6_5
# %bb.1: # %.lr.ph.preheader
cvtsi2ss %edx, %xmm1
mulss %xmm0, %xmm1
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdi,%rcx,4), %edx
subl (%rsi,%rcx,4), %edx
movl %edx, %r8d
negl %r8d
cmovsl %edx, %r8d
xorps %xmm0, %xmm0
cvtsi2ss %r8d, %xmm0
ucomiss %xmm1, %xmm0
ja .LBB6_6
# %bb.3: # in Loop: Header=BB6_2 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB6_2
.LBB6_5:
xorl %eax, %eax
retq
.LBB6_6:
movl $-1, %eax
retq
.Lfunc_end6:
.size _Z9chkConvrgPiS_if, .Lfunc_end6-_Z9chkConvrgPiS_if
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movq 24(%rsi), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movsd %xmm0, 208(%rsp) # 8-byte Spill
movb $1, %al
callq printf
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rbp), %rdi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
movq %rsp, %rdx
movl $.L.str, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl (%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdx
movl $.L.str, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rdx
movl $.L.str, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 48(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%rsp)
movl 4(%rsp), %ebx
imull 8(%rsp), %ebx
movq 32(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 48(%rsp) # 8-byte Spill
movq 40(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 40(%rsp) # 8-byte Spill
movl %ebx, 16(%rsp) # 4-byte Spill
movslq %ebx, %r15
leaq (,%r15,8), %rax
leaq (%rax,%rax,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movq %r15, %r13
testl %r15d, %r15d
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader.i
movl 16(%rsp), %r12d # 4-byte Reload
movq 32(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB7_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 8(%r15), %rcx
leaq 16(%r15), %r8
leaq 24(%r15), %r9
leaq 32(%r15), %r10
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
pushq %r10
.cfi_adjust_cfa_offset 8
callq __isoc23_fscanf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $40, %r15
decq %r12
jne .LBB7_2
.LBB7_3: # %_Z10readPointsP8_IO_FILEP5Pointi.exit
movq %r14, %rdi
callq fclose
movq %r13, %rdi
shlq $2, %rdi
movq %rdi, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r13
movslq (%rsp), %r14
leaq (,%r14,8), %rax
leaq (%rax,%rax,4), %rdi
callq malloc
movq %rax, %r15
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testq %r14, %r14
movq 32(%rsp), %r12 # 8-byte Reload
movl 16(%rsp), %r8d # 4-byte Reload
jle .LBB7_6
# %bb.4: # %.lr.ph.preheader.i120
movl %r14d, %eax
shlq $3, %rax
leaq (%rax,%rax,4), %rcx
movl $2, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB7_5: # %.lr.ph.i122
# =>This Inner Loop Header: Depth=1
movl %r8d, %eax
cltd
idivl %esi
cltq
leaq (%rax,%rax,4), %rax
movsd (%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r15,%rdi)
movsd 8(%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 8(%r15,%rdi)
movsd 16(%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%r15,%rdi)
movsd 24(%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%r15,%rdi)
movsd 32(%r12,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 32(%r15,%rdi)
incl %esi
addq $40, %rdi
cmpq %rdi, %rcx
jne .LBB7_5
.LBB7_6: # %_Z10initializeP5PointiiS0_.exit
testl %r8d, %r8d
jle .LBB7_8
# %bb.7: # %.lr.ph.preheader.i126
movl %r8d, %edx
shlq $2, %rdx
movq %r13, %rdi
movl $255, %esi
callq memset@PLT
.LBB7_8: # %_Z13IntClusterMemPii.exit128
leaq 64(%rsp), %rdi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.11:
leaq 352(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_12
# %bb.13:
leaq 128(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_14
# %bb.15:
movslq (%rsp), %rax
shlq $3, %rax
leaq (%rax,%rax,4), %rsi
leaq 120(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB7_16
# %bb.17:
leaq 192(%rsp), %rdi
callq hipEventCreate
leaq 112(%rsp), %rdi
callq hipEventCreate
movq 192(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 128(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_18
# %bb.19:
movq %rbp, 200(%rsp) # 8-byte Spill
movq 64(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_20
# %bb.21:
movq 112(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq 112(%rsp), %rdi
callq hipEventSynchronize
movq 192(%rsp), %rsi
movq 112(%rsp), %rdx
leaq 300(%rsp), %rdi
callq hipEventElapsedTime
movl (%rsp), %eax
cmpl $10, %eax
movq %r13, 72(%rsp) # 8-byte Spill
je .LBB7_22
# %bb.23:
cmpl $50, %eax
je .LBB7_26
# %bb.24:
cmpl $30, %eax
jne .LBB7_27
# %bb.25:
movl $14, 12(%rsp) # 4-byte Folded Spill
movl $.L.str.8, %eax
jmp .LBB7_28
.LBB7_26:
movl $63, 12(%rsp) # 4-byte Folded Spill
movl $.L.str.9, %eax
jmp .LBB7_28
.LBB7_22:
movl $4, 12(%rsp) # 4-byte Folded Spill
movl $.L.str.7, %eax
jmp .LBB7_28
.LBB7_27:
movl $87, 12(%rsp) # 4-byte Folded Spill
movl $.L.str.10, %eax
.LBB7_28:
movq %rax, 24(%rsp) # 8-byte Spill
movq 40(%rsp), %rdx # 8-byte Reload
movq %rdx, %rax
shlq $32, %rax
movq 48(%rsp), %rcx # 8-byte Reload
movl %ecx, %ebx
orq %rax, %rbx
leal -1(%rcx), %eax
movl %eax, 144(%rsp) # 4-byte Spill
leal -1(%rdx), %eax
movl %eax, 140(%rsp) # 4-byte Spill
xorl %r14d, %r14d
movq 72(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB7_29: # =>This Inner Loop Header: Depth=1
leaq 184(%rsp), %rdi
callq hipEventCreate
leaq 104(%rsp), %rdi
callq hipEventCreate
movq 184(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 120(%rsp), %rdi
movslq (%rsp), %rax
shlq $3, %rax
leaq (%rax,%rax,4), %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_30
# %bb.31: # in Loop: Header=BB7_29 Depth=1
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rdi
callq hipEventSynchronize
movq 184(%rsp), %rsi
movq 104(%rsp), %rdx
leaq 296(%rsp), %rdi
callq hipEventElapsedTime
leaq 176(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 176(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 8(%rsp), %eax
addl 144(%rsp), %eax # 4-byte Folded Reload
cltd
idivl 48(%rsp) # 4-byte Folded Reload
movl %eax, %edi
movl 4(%rsp), %eax
addl 140(%rsp), %eax # 4-byte Folded Reload
cltd
idivl 40(%rsp) # 4-byte Folded Reload
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_33
# %bb.32: # in Loop: Header=BB7_29 Depth=1
movq 64(%rsp), %rax
movq 128(%rsp), %rcx
movq 120(%rsp), %rdx
movl (%rsp), %esi
movl 8(%rsp), %edi
movl 4(%rsp), %r8d
movq %rax, 280(%rsp)
movq %rcx, 272(%rsp)
movq %rdx, 264(%rsp)
movl %esi, 156(%rsp)
movl %edi, 152(%rsp)
movl %r8d, 148(%rsp)
leaq 280(%rsp), %rax
movq %rax, 304(%rsp)
leaq 272(%rsp), %rax
movq %rax, 312(%rsp)
leaq 264(%rsp), %rax
movq %rax, 320(%rsp)
leaq 156(%rsp), %rax
movq %rax, 328(%rsp)
leaq 152(%rsp), %rax
movq %rax, 336(%rsp)
leaq 148(%rsp), %rax
movq %rax, 344(%rsp)
leaq 248(%rsp), %rdi
leaq 232(%rsp), %rsi
leaq 224(%rsp), %rdx
leaq 216(%rsp), %rcx
callq __hipPopCallConfiguration
movq 248(%rsp), %rsi
movl 256(%rsp), %edx
movq 232(%rsp), %rcx
movl 240(%rsp), %r8d
movl $_Z13pointsClusterPiP5PointS1_iii, %edi
leaq 304(%rsp), %r9
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_33: # in Loop: Header=BB7_29 Depth=1
callq hipDeviceSynchronize
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movq 176(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 292(%rsp), %rdi
callq hipEventElapsedTime
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rsi
movq %r13, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_34
# %bb.35: # %.loopexit
# in Loop: Header=BB7_29 Depth=1
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 88(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 288(%rsp), %rdi
callq hipEventElapsedTime
movl (%rsp), %ecx
movq %r12, %rdi
movq %r13, %rsi
movq %r15, %rdx
movl 16(%rsp), %r8d # 4-byte Reload
callq _Z11calcNewMeanP5PointPiS0_ii
cmpl 12(%rsp), %ebp # 4-byte Folded Reload
movl $1, %eax
cmoval %eax, %r14d
incl %ebp
cmpl $1, %r14d
jne .LBB7_29
# %bb.36:
movq 200(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
movl $.L.str.11, %esi
callq fopen
movq %rax, %rbx
movl $.L.str.11, %esi
movq 24(%rsp), %rdi # 8-byte Reload
callq fopen
movq %rax, %r13
movl (%rsp), %edx
movl $.L.str, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
movl 8(%rsp), %edx
movl $.L.str, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
movl 4(%rsp), %edx
movl $.L.str, %esi
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, (%rsp)
jle .LBB7_39
# %bb.37: # %.lr.ph.preheader
movq %r15, %rbx
addq $32, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_38: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd -32(%rbx), %xmm0 # xmm0 = mem[0],zero
movsd -24(%rbx), %xmm1 # xmm1 = mem[0],zero
movsd -16(%rbx), %xmm2 # xmm2 = mem[0],zero
movsd -8(%rbx), %xmm3 # xmm3 = mem[0],zero
movsd (%rbx), %xmm4 # xmm4 = mem[0],zero
movl $.L.str.12, %esi
movq %r13, %rdi
movb $5, %al
callq fprintf
incq %r12
movslq (%rsp), %rax
addq $40, %rbx
cmpq %rax, %r12
jl .LBB7_38
.LBB7_39: # %.preheader
movq %r13, 56(%rsp) # 8-byte Spill
movq %r15, 40(%rsp) # 8-byte Spill
movl 16(%rsp), %eax # 4-byte Reload
testl %eax, %eax
movq 72(%rsp), %r13 # 8-byte Reload
movq 48(%rsp), %r15 # 8-byte Reload
jle .LBB7_42
# %bb.40: # %.lr.ph134.preheader
movl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movq 32(%rsp), %rbx # 8-byte Reload
addq $32, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_41: # %.lr.ph134
# =>This Inner Loop Header: Depth=1
movsd -32(%rbx), %xmm0 # xmm0 = mem[0],zero
movsd -24(%rbx), %xmm1 # xmm1 = mem[0],zero
movsd -16(%rbx), %xmm2 # xmm2 = mem[0],zero
movsd -8(%rbx), %xmm3 # xmm3 = mem[0],zero
movsd (%rbx), %xmm4 # xmm4 = mem[0],zero
movl (%r13,%r12,4), %edx
incl %edx
movl $.L.str.13, %esi
movq %r15, %rdi
movb $5, %al
callq fprintf
incq %r12
addq $40, %rbx
cmpq %r12, 16(%rsp) # 8-byte Folded Reload
jne .LBB7_41
.LBB7_42: # %._crit_edge
xorl %ebx, %ebx
cmpl $1, %r14d
setne %bl
movq %r15, %rdi
callq fclose
movq 56(%rsp), %rdi # 8-byte Reload
callq fclose
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rsi
movq 80(%rsp), %rdx
leaq 304(%rsp), %rdi
callq hipEventElapsedTime
leal (%rbx,%rbp), %esi
addl $-2, %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl (%rsp), %esi
movss 304(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI7_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str.15, %edi
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_43
# %bb.44:
movq 120(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 32(%rsp), %rbx # 8-byte Reload
movq 72(%rsp), %r14 # 8-byte Reload
movq 40(%rsp), %r15 # 8-byte Reload
jne .LBB7_45
# %bb.46:
movq 128(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_47
# %bb.48:
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_34:
.cfi_def_cfa_offset 416
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $302, %edx # imm = 0x12E
jmp .LBB7_10
.LBB7_30:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $273, %edx # imm = 0x111
.LBB7_10:
xorl %eax, %eax
callq printf
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB7_9:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $230, %edx
jmp .LBB7_10
.LBB7_12:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $231, %edx
jmp .LBB7_10
.LBB7_14:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $232, %edx
jmp .LBB7_10
.LBB7_16:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $233, %edx
jmp .LBB7_10
.LBB7_18:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $240, %edx
jmp .LBB7_10
.LBB7_20:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $241, %edx
jmp .LBB7_10
.LBB7_43:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $351, %edx # imm = 0x15F
jmp .LBB7_10
.LBB7_45:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $352, %edx # imm = 0x160
jmp .LBB7_10
.LBB7_47:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $353, %edx # imm = 0x161
jmp .LBB7_10
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pointsClusterPiP5PointS1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf,%lf,%lf,%lf,%lf"
.size .L.str.1, 20
.type _Z13pointsClusterPiP5PointS1_iii,@object # @_Z13pointsClusterPiP5PointS1_iii
.section .rodata,"a",@progbits
.globl _Z13pointsClusterPiP5PointS1_iii
.p2align 3, 0x0
_Z13pointsClusterPiP5PointS1_iii:
.quad _Z28__device_stub__pointsClusterPiP5PointS1_iii
.size _Z13pointsClusterPiP5PointS1_iii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Tolerancia = %f \n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA error at %s:%d\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dbellidor/Comp_Molecular/master/Paper/CUDA/kmean_cuda.hip"
.size .L.str.5, 115
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " %s\n"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Centroid_10.txt"
.size .L.str.7, 16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Centroid_30.txt"
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Centroid_50.txt"
.size .L.str.9, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Centroid_100.txt"
.size .L.str.10, 17
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "w"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "%.0f,%.0f,%.0f,%.0f,%.0f\n"
.size .L.str.12, 26
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%.0f,%.0f,%.0f,%.0f,%.0f,%d\n"
.size .L.str.13, 29
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Total Iteraciones = %d\n"
.size .L.str.14, 24
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CUDA:Tiempo total transcurrido en la ejecucion. k= %d con tolerancia= %f en clusters : %f sec\n"
.size .L.str.15, 95
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13pointsClusterPiP5PointS1_iii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__pointsClusterPiP5PointS1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13pointsClusterPiP5PointS1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <cstdio>
using namespace std;
__global__ void matrixColour (float *a, float *b, int n){
int j= blockDim.x * blockIdx.x + threadIdx.x;
printf("Block = %d ; Thread = %d \n",blockIdx.x+1, threadIdx.x+1);
// if(j<n){
// for (int i=0; i<n; i++){
//// printf("Block = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, j+1,i+1,b[i]);
// if (a[j*n+i]==1){
// if (b[j]==b[i]){
// b[j]=-1;
// break;
// }
// }
// }
// }
int *colour = new int[n];
memset(colour, 0, n*sizeof(int));
if (j<n){
for (int i=0; i<n; i++){
//printf("Thread = %d ; i = %d ; %f\n",j+1,i+1,b[i]);
printf("Block = %d ; Thread = %d First For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
if (a[j*n+i]==1 && b[i]!=-1){
colour[(int)b[i]]=1;
}
// if (i==j){
// //atomicAdd(&b[i],1.0f);
// b[i]+=1.0f;
// }
}
for (int i=0; i<n; i++){
if (colour[i]==0){
printf("Block = %d ; Thread = %d Second For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
atomicAdd(&b[j],(float)i-b[j]);
break;
}
}
// for (int i=0; i<n; i++){
// printf("Third Block = %d ; ThreadId = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, threadIdx.x+1, j+1,i+1,b[i]);
// }
}
// printf("I am thread no: %d from blocknumber: %d\n", threadIdx.x, blockIdx.x);
//b[j] = j+1;
}
int main(){
int noNodes = 64;
int n = noNodes*noNodes;
size_t size = n * sizeof(float);
size_t sizeColouring = noNodes * sizeof(float);
float *h_matrix = new float[n];
float *h_colouring = new float[noNodes];
float *h_colouring1 = new float[noNodes];
int k=100;
for (int i=0; i<noNodes; i++){
h_colouring[i]=-1;
h_colouring1[i]=-1;
for (int j=0; j<noNodes; j++){
if (i==j){
h_matrix[noNodes*i+j]=0;
}
else{
h_matrix[noNodes*i+j]=rand()%2;
}
}
}
// for (int i=0; i<noNodes; i++){
//
// for (int j=0; j<noNodes; j++){
//
// cout<<h_matrix[noNodes*i+j]<<" ";
// }
//
// cout<<endl;
//
// }
float *d_matrix = NULL;
cudaMalloc((void **)&d_matrix, size);
float *d_colouring = NULL;
cudaMalloc((void **)&d_colouring, sizeColouring);
cudaMemcpy(d_matrix, h_matrix, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_colouring, h_colouring, sizeColouring, cudaMemcpyHostToDevice);
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// Launch the Vector Add CUDA Kernel
int threadsPerBlock = 32;
int blocksPerGrid = (noNodes + threadsPerBlock -1)/threadsPerBlock;
cout<<"Blocks "<<threadsPerBlock<<" "<<blocksPerGrid<<endl;
matrixColour<<<blocksPerGrid, threadsPerBlock>>>(d_matrix, d_colouring, noNodes);
cudaMemcpy(h_colouring, d_colouring, sizeColouring, cudaMemcpyDeviceToHost);
for (int i=0; i<noNodes; i++){
if (h_colouring[i]!=-1)
cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
}
bool colour[noNodes];
memset(colour, 0, noNodes*sizeof(bool));
for (int i=0; i<noNodes; i++){
if (h_colouring[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring[j] >= 0)
colour[(int)h_colouring[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
for (int i=0; i<noNodes; i++){
if (h_colouring1[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring1[j] >= 0)
colour[(int)h_colouring1[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring1[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
//
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
//
cudaFree(d_matrix);
cudaFree(d_colouring);
free(h_colouring);
free(h_matrix);
cudaDeviceReset();
return 0;
} | .file "tmpxft_00074b1e_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12matrixColourPfS_iPfS_i
.type _Z35__device_stub__Z12matrixColourPfS_iPfS_i, @function
_Z35__device_stub__Z12matrixColourPfS_iPfS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixColourPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z12matrixColourPfS_iPfS_i, .-_Z35__device_stub__Z12matrixColourPfS_iPfS_i
.globl _Z12matrixColourPfS_i
.type _Z12matrixColourPfS_i, @function
_Z12matrixColourPfS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12matrixColourPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12matrixColourPfS_i, .-_Z12matrixColourPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Blocks "
.LC3:
.string " "
.LC4:
.string "Back Home i = "
.LC5:
.string " ; "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $16384, %edi
call _Znam@PLT
movq %rax, %r14
movl $256, %edi
call _Znam@PLT
movq %rax, %r15
movl $256, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %r13d
movl $64, %r12d
movl $0, %ebp
jmp .L15
.L63:
movslq %ebx, %rax
movl $0x00000000, (%r14,%rax,4)
.L13:
addl $1, %ebx
cmpl %r12d, %ebx
je .L62
.L14:
leal (%rbx,%r13), %eax
cmpl %ebp, %eax
je .L63
call rand@PLT
movslq %ebx, %rcx
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r14,%rcx,4)
jmp .L13
.L62:
addq $1, %rbp
addl $64, %r12d
subl $64, %r13d
cmpq $64, %rbp
je .L64
.L15:
movl $0xbf800000, (%r15,%rbp,4)
movq 8(%rsp), %rax
movl $0xbf800000, (%rax,%rbp,4)
movl %ebp, %ebx
sall $6, %ebx
jmp .L14
.L64:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $32, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L16:
movl $2, %ecx
movl $256, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $1, %ebx
leaq _ZSt4cout(%rip), %r13
jmp .L23
.L65:
movl $64, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z12matrixColourPfS_iPfS_i
jmp .L16
.L68:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L69:
movzbl 67(%r12), %esi
.L22:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L17:
addq $1, %rbx
cmpq $65, %rbx
je .L67
.L23:
movss .LC0(%rip), %xmm7
ucomiss -4(%r15,%rbx,4), %xmm7
jp .L45
je .L17
.L45:
movl $14, %edx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd -4(%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L68
cmpb $0, 56(%r12)
jne .L69
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L67:
pxor %xmm0, %xmm0
movups %xmm0, 64(%rsp)
movups %xmm0, 80(%rsp)
movups %xmm0, 96(%rsp)
movups %xmm0, 112(%rsp)
movq %r14, %rdx
movq %r14, %rcx
movl $0, %edi
movss .LC0(%rip), %xmm6
movaps %xmm6, %xmm5
movss .LC6(%rip), %xmm1
movaps %xmm1, %xmm2
pxor %xmm3, %xmm3
leaq 64(%rsp), %r8
movdqa %xmm0, %xmm4
jmp .L33
.L71:
cvttss2sil %xmm0, %esi
movslq %esi, %rsi
movb $1, 64(%rsp,%rsi)
.L26:
addq $4, %rax
cmpq $256, %rax
je .L70
.L29:
ucomiss (%rcx,%rax), %xmm1
jp .L26
ucomiss (%rcx,%rax), %xmm2
jne .L26
movss (%r15,%rax), %xmm0
comiss %xmm3, %xmm0
jnb .L71
jmp .L26
.L70:
movl $0, %eax
.L32:
cmpb $0, (%rax,%r8)
je .L72
addq $1, %rax
cmpq $64, %rax
jne .L32
jmp .L31
.L72:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rdi,4)
.L31:
movups %xmm4, (%r8)
movups %xmm4, 16(%r8)
movups %xmm4, 32(%r8)
movups %xmm4, 48(%r8)
.L24:
addq $1, %rdi
addq $256, %rcx
cmpq $64, %rdi
je .L73
.L33:
ucomiss (%r15,%rdi,4), %xmm6
jp .L24
ucomiss (%r15,%rdi,4), %xmm5
jne .L24
movl $0, %eax
jmp .L29
.L73:
movl $0, %esi
movss .LC0(%rip), %xmm6
movaps %xmm6, %xmm5
movss .LC6(%rip), %xmm1
movaps %xmm1, %xmm2
pxor %xmm3, %xmm3
leaq 64(%rsp), %rdi
pxor %xmm4, %xmm4
jmp .L43
.L36:
addq $4, %rax
cmpq $256, %rax
je .L74
.L39:
ucomiss (%rdx,%rax), %xmm1
jp .L36
ucomiss (%rdx,%rax), %xmm2
jne .L36
movq 8(%rsp), %rcx
movss (%rcx,%rax), %xmm0
comiss %xmm3, %xmm0
jb .L36
cvttss2sil %xmm0, %ecx
movslq %ecx, %rcx
movb $1, 64(%rsp,%rcx)
jmp .L36
.L74:
movl $0, %eax
.L42:
cmpb $0, (%rax,%rdi)
je .L75
addq $1, %rax
cmpq $64, %rax
jne .L42
jmp .L41
.L75:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rsi,4)
.L41:
movups %xmm4, (%rdi)
movups %xmm4, 16(%rdi)
movups %xmm4, 32(%rdi)
movups %xmm4, 48(%rdi)
.L34:
addq $1, %rsi
addq $256, %rdx
cmpq $64, %rsi
je .L76
.L43:
movq 8(%rsp), %rax
ucomiss (%rax,%rsi,4), %xmm6
jp .L34
ucomiss (%rax,%rsi,4), %xmm5
jne .L34
movl $0, %eax
jmp .L39
.L76:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L77
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12matrixColourPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixColourPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1082130432
.align 4
.LC6:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <cstdio>
using namespace std;
__global__ void matrixColour (float *a, float *b, int n){
int j= blockDim.x * blockIdx.x + threadIdx.x;
printf("Block = %d ; Thread = %d \n",blockIdx.x+1, threadIdx.x+1);
// if(j<n){
// for (int i=0; i<n; i++){
//// printf("Block = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, j+1,i+1,b[i]);
// if (a[j*n+i]==1){
// if (b[j]==b[i]){
// b[j]=-1;
// break;
// }
// }
// }
// }
int *colour = new int[n];
memset(colour, 0, n*sizeof(int));
if (j<n){
for (int i=0; i<n; i++){
//printf("Thread = %d ; i = %d ; %f\n",j+1,i+1,b[i]);
printf("Block = %d ; Thread = %d First For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
if (a[j*n+i]==1 && b[i]!=-1){
colour[(int)b[i]]=1;
}
// if (i==j){
// //atomicAdd(&b[i],1.0f);
// b[i]+=1.0f;
// }
}
for (int i=0; i<n; i++){
if (colour[i]==0){
printf("Block = %d ; Thread = %d Second For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
atomicAdd(&b[j],(float)i-b[j]);
break;
}
}
// for (int i=0; i<n; i++){
// printf("Third Block = %d ; ThreadId = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, threadIdx.x+1, j+1,i+1,b[i]);
// }
}
// printf("I am thread no: %d from blocknumber: %d\n", threadIdx.x, blockIdx.x);
//b[j] = j+1;
}
int main(){
int noNodes = 64;
int n = noNodes*noNodes;
size_t size = n * sizeof(float);
size_t sizeColouring = noNodes * sizeof(float);
float *h_matrix = new float[n];
float *h_colouring = new float[noNodes];
float *h_colouring1 = new float[noNodes];
int k=100;
for (int i=0; i<noNodes; i++){
h_colouring[i]=-1;
h_colouring1[i]=-1;
for (int j=0; j<noNodes; j++){
if (i==j){
h_matrix[noNodes*i+j]=0;
}
else{
h_matrix[noNodes*i+j]=rand()%2;
}
}
}
// for (int i=0; i<noNodes; i++){
//
// for (int j=0; j<noNodes; j++){
//
// cout<<h_matrix[noNodes*i+j]<<" ";
// }
//
// cout<<endl;
//
// }
float *d_matrix = NULL;
cudaMalloc((void **)&d_matrix, size);
float *d_colouring = NULL;
cudaMalloc((void **)&d_colouring, sizeColouring);
cudaMemcpy(d_matrix, h_matrix, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_colouring, h_colouring, sizeColouring, cudaMemcpyHostToDevice);
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// Launch the Vector Add CUDA Kernel
int threadsPerBlock = 32;
int blocksPerGrid = (noNodes + threadsPerBlock -1)/threadsPerBlock;
cout<<"Blocks "<<threadsPerBlock<<" "<<blocksPerGrid<<endl;
matrixColour<<<blocksPerGrid, threadsPerBlock>>>(d_matrix, d_colouring, noNodes);
cudaMemcpy(h_colouring, d_colouring, sizeColouring, cudaMemcpyDeviceToHost);
for (int i=0; i<noNodes; i++){
if (h_colouring[i]!=-1)
cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
}
bool colour[noNodes];
memset(colour, 0, noNodes*sizeof(bool));
for (int i=0; i<noNodes; i++){
if (h_colouring[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring[j] >= 0)
colour[(int)h_colouring[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
for (int i=0; i<noNodes; i++){
if (h_colouring1[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring1[j] >= 0)
colour[(int)h_colouring1[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring1[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
//
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
//
cudaFree(d_matrix);
cudaFree(d_colouring);
free(h_colouring);
free(h_matrix);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstdio>
using namespace std;
__global__ void matrixColour (float *a, float *b, int n){
int j= blockDim.x * blockIdx.x + threadIdx.x;
printf("Block = %d ; Thread = %d \n",blockIdx.x+1, threadIdx.x+1);
// if(j<n){
// for (int i=0; i<n; i++){
//// printf("Block = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, j+1,i+1,b[i]);
// if (a[j*n+i]==1){
// if (b[j]==b[i]){
// b[j]=-1;
// break;
// }
// }
// }
// }
int *colour = new int[n];
memset(colour, 0, n*sizeof(int));
if (j<n){
for (int i=0; i<n; i++){
//printf("Thread = %d ; i = %d ; %f\n",j+1,i+1,b[i]);
printf("Block = %d ; Thread = %d First For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
if (a[j*n+i]==1 && b[i]!=-1){
colour[(int)b[i]]=1;
}
// if (i==j){
// //atomicAdd(&b[i],1.0f);
// b[i]+=1.0f;
// }
}
for (int i=0; i<n; i++){
if (colour[i]==0){
printf("Block = %d ; Thread = %d Second For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
atomicAdd(&b[j],(float)i-b[j]);
break;
}
}
// for (int i=0; i<n; i++){
// printf("Third Block = %d ; ThreadId = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, threadIdx.x+1, j+1,i+1,b[i]);
// }
}
// printf("I am thread no: %d from blocknumber: %d\n", threadIdx.x, blockIdx.x);
//b[j] = j+1;
}
int main(){
int noNodes = 64;
int n = noNodes*noNodes;
size_t size = n * sizeof(float);
size_t sizeColouring = noNodes * sizeof(float);
float *h_matrix = new float[n];
float *h_colouring = new float[noNodes];
float *h_colouring1 = new float[noNodes];
int k=100;
for (int i=0; i<noNodes; i++){
h_colouring[i]=-1;
h_colouring1[i]=-1;
for (int j=0; j<noNodes; j++){
if (i==j){
h_matrix[noNodes*i+j]=0;
}
else{
h_matrix[noNodes*i+j]=rand()%2;
}
}
}
// for (int i=0; i<noNodes; i++){
//
// for (int j=0; j<noNodes; j++){
//
// cout<<h_matrix[noNodes*i+j]<<" ";
// }
//
// cout<<endl;
//
// }
float *d_matrix = NULL;
hipMalloc((void **)&d_matrix, size);
float *d_colouring = NULL;
hipMalloc((void **)&d_colouring, sizeColouring);
hipMemcpy(d_matrix, h_matrix, size, hipMemcpyHostToDevice);
hipMemcpy(d_colouring, h_colouring, sizeColouring, hipMemcpyHostToDevice);
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// Launch the Vector Add CUDA Kernel
int threadsPerBlock = 32;
int blocksPerGrid = (noNodes + threadsPerBlock -1)/threadsPerBlock;
cout<<"Blocks "<<threadsPerBlock<<" "<<blocksPerGrid<<endl;
matrixColour<<<blocksPerGrid, threadsPerBlock>>>(d_matrix, d_colouring, noNodes);
hipMemcpy(h_colouring, d_colouring, sizeColouring, hipMemcpyDeviceToHost);
for (int i=0; i<noNodes; i++){
if (h_colouring[i]!=-1)
cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
}
bool colour[noNodes];
memset(colour, 0, noNodes*sizeof(bool));
for (int i=0; i<noNodes; i++){
if (h_colouring[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring[j] >= 0)
colour[(int)h_colouring[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
for (int i=0; i<noNodes; i++){
if (h_colouring1[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring1[j] >= 0)
colour[(int)h_colouring1[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring1[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
//
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
//
hipFree(d_matrix);
hipFree(d_colouring);
free(h_colouring);
free(h_matrix);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstdio>
using namespace std;
__global__ void matrixColour (float *a, float *b, int n){
int j= blockDim.x * blockIdx.x + threadIdx.x;
printf("Block = %d ; Thread = %d \n",blockIdx.x+1, threadIdx.x+1);
// if(j<n){
// for (int i=0; i<n; i++){
//// printf("Block = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, j+1,i+1,b[i]);
// if (a[j*n+i]==1){
// if (b[j]==b[i]){
// b[j]=-1;
// break;
// }
// }
// }
// }
int *colour = new int[n];
memset(colour, 0, n*sizeof(int));
if (j<n){
for (int i=0; i<n; i++){
//printf("Thread = %d ; i = %d ; %f\n",j+1,i+1,b[i]);
printf("Block = %d ; Thread = %d First For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
if (a[j*n+i]==1 && b[i]!=-1){
colour[(int)b[i]]=1;
}
// if (i==j){
// //atomicAdd(&b[i],1.0f);
// b[i]+=1.0f;
// }
}
for (int i=0; i<n; i++){
if (colour[i]==0){
printf("Block = %d ; Thread = %d Second For i = %d\n",blockIdx.x+1, threadIdx.x+1, i+1);
atomicAdd(&b[j],(float)i-b[j]);
break;
}
}
// for (int i=0; i<n; i++){
// printf("Third Block = %d ; ThreadId = %d ; Thread = %d ; i = %d ; %f\n",blockIdx.x+1, threadIdx.x+1, j+1,i+1,b[i]);
// }
}
// printf("I am thread no: %d from blocknumber: %d\n", threadIdx.x, blockIdx.x);
//b[j] = j+1;
}
int main(){
int noNodes = 64;
int n = noNodes*noNodes;
size_t size = n * sizeof(float);
size_t sizeColouring = noNodes * sizeof(float);
float *h_matrix = new float[n];
float *h_colouring = new float[noNodes];
float *h_colouring1 = new float[noNodes];
int k=100;
for (int i=0; i<noNodes; i++){
h_colouring[i]=-1;
h_colouring1[i]=-1;
for (int j=0; j<noNodes; j++){
if (i==j){
h_matrix[noNodes*i+j]=0;
}
else{
h_matrix[noNodes*i+j]=rand()%2;
}
}
}
// for (int i=0; i<noNodes; i++){
//
// for (int j=0; j<noNodes; j++){
//
// cout<<h_matrix[noNodes*i+j]<<" ";
// }
//
// cout<<endl;
//
// }
float *d_matrix = NULL;
hipMalloc((void **)&d_matrix, size);
float *d_colouring = NULL;
hipMalloc((void **)&d_colouring, sizeColouring);
hipMemcpy(d_matrix, h_matrix, size, hipMemcpyHostToDevice);
hipMemcpy(d_colouring, h_colouring, sizeColouring, hipMemcpyHostToDevice);
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// Launch the Vector Add CUDA Kernel
int threadsPerBlock = 32;
int blocksPerGrid = (noNodes + threadsPerBlock -1)/threadsPerBlock;
cout<<"Blocks "<<threadsPerBlock<<" "<<blocksPerGrid<<endl;
matrixColour<<<blocksPerGrid, threadsPerBlock>>>(d_matrix, d_colouring, noNodes);
hipMemcpy(h_colouring, d_colouring, sizeColouring, hipMemcpyDeviceToHost);
for (int i=0; i<noNodes; i++){
if (h_colouring[i]!=-1)
cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
}
bool colour[noNodes];
memset(colour, 0, noNodes*sizeof(bool));
for (int i=0; i<noNodes; i++){
if (h_colouring[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring[j] >= 0)
colour[(int)h_colouring[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
for (int i=0; i<noNodes; i++){
if (h_colouring1[i]==-1){
for (int j=0; j<noNodes; j++){
if (h_matrix[i*noNodes+j]==1){
if (h_colouring1[j] >= 0)
colour[(int)h_colouring1[j]]=true;
}
}
for (int j=0; j<noNodes; j++){
if (colour[j]==false){
h_colouring1[i]=j;
break;
}
}
memset(colour, 0, noNodes*sizeof(bool));
}
}
// for (int i=0; i<noNodes; i++){
//
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring[i]<<endl;
// }
// for (int i=0; i<noNodes; i++){
// cout<<"Back Home i = "<<i+1<<" ; "<<h_colouring1[i]<<endl;
// }
//
hipFree(d_matrix);
hipFree(d_colouring);
free(h_colouring);
free(h_matrix);
hipDeviceReset();
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__matrixColourPfS_i # -- Begin function _Z27__device_stub__matrixColourPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__matrixColourPfS_i,@function
_Z27__device_stub__matrixColourPfS_i: # @_Z27__device_stub__matrixColourPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixColourPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixColourPfS_i, .Lfunc_end0-_Z27__device_stub__matrixColourPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xbf800000 # float -1
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %r13
movl $256, %edi # imm = 0x100
callq _Znam
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
movq %r13, -72(%rbp) # 8-byte Spill
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $256, %r13 # imm = 0x100
cmpq $64, %r12
je .LBB1_6
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $-1082130432, (%r14,%r12,4) # imm = 0xBF800000
movl $-1082130432, (%r15,%r12,4) # imm = 0xBF800000
xorl %ebx, %ebx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $64, %rbx
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cmpq %rbx, %r12
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
jmp .LBB1_4
.LBB1_6:
movq $0, -56(%rbp)
leaq -56(%rbp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq $0, -48(%rbp)
leaq -48(%rbp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq -56(%rbp), %rdi
movl $16384, %edx # imm = 0x4000
movq -72(%rbp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq -48(%rbp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $32, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl $2, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_47
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_9
# %bb.8:
movzbl 67(%r12), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq -56(%rbp), %rax
movq -48(%rbp), %rcx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movl $64, -60(%rbp)
leaq -136(%rbp), %rax
movq %rax, -160(%rbp)
leaq -128(%rbp), %rax
movq %rax, -152(%rbp)
leaq -60(%rbp), %rax
movq %rax, -144(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -160(%rbp), %r9
movl $_Z12matrixColourPfS_i, %edi
pushq -80(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_12:
movq -48(%rbp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_13 Depth=1
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit120
# in Loop: Header=BB1_13 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.LBB1_19: # in Loop: Header=BB1_13 Depth=1
incq %r13
cmpq $64, %r13
je .LBB1_20
.LBB1_13: # =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm4, %xmm0
jne .LBB1_14
jnp .LBB1_19
.LBB1_14: # in Loop: Header=BB1_13 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leal 1(%r13), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_47
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i117
# in Loop: Header=BB1_13 Depth=1
cmpb $0, 56(%r12)
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_13 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_18
.LBB1_20:
movq %rsp, %r12
movq %rsp, %rcx
leaq -64(%rcx), %rax
movq %rax, %rsp
xorps %xmm1, %xmm1
movaps %xmm1, -16(%rcx)
movaps %xmm1, -32(%rcx)
movaps %xmm1, -48(%rcx)
movaps %xmm1, -64(%rcx)
xorl %ecx, %ecx
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
movq -72(%rbp), %rbx # 8-byte Reload
movq %rbx, %rdx
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_21 Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
movss %xmm3, (%r14,%rcx,4)
.LBB1_31: # %.loopexit127
# in Loop: Header=BB1_21 Depth=1
movaps %xmm1, 48(%rax)
movaps %xmm1, 32(%rax)
movaps %xmm1, 16(%rax)
movaps %xmm1, (%rax)
.LBB1_32: # in Loop: Header=BB1_21 Depth=1
incq %rcx
addq $256, %rdx # imm = 0x100
cmpq $64, %rcx
je .LBB1_33
.LBB1_21: # =>This Loop Header: Depth=1
# Child Loop BB1_23 Depth 2
# Child Loop BB1_28 Depth 2
movss (%r14,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm4, %xmm3
jne .LBB1_32
jp .LBB1_32
# %bb.22: # %.preheader128
# in Loop: Header=BB1_21 Depth=1
xorl %esi, %esi
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_23 Depth=2
incq %rsi
cmpq $64, %rsi
je .LBB1_27
.LBB1_23: # Parent Loop BB1_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm3
jne .LBB1_26
jp .LBB1_26
# %bb.24: # in Loop: Header=BB1_23 Depth=2
movss (%r14,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm3
jb .LBB1_26
# %bb.25: # in Loop: Header=BB1_23 Depth=2
cvttss2si %xmm3, %edi
movslq %edi, %rdi
movb $1, (%rax,%rdi)
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_27: # %.preheader126.preheader
# in Loop: Header=BB1_21 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_28: # %.preheader126
# Parent Loop BB1_21 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rax,%rsi)
je .LBB1_29
# %bb.30: # in Loop: Header=BB1_28 Depth=2
incq %rsi
cmpq $64, %rsi
jne .LBB1_28
jmp .LBB1_31
.LBB1_33: # %.preheader125.preheader
xorl %ecx, %ecx
xorps %xmm1, %xmm1
xorps %xmm2, %xmm2
movq %rbx, %rdx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_42: # in Loop: Header=BB1_34 Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
movss %xmm3, (%r15,%rcx,4)
.LBB1_44: # %.loopexit
# in Loop: Header=BB1_34 Depth=1
movaps %xmm2, 48(%rax)
movaps %xmm2, 32(%rax)
movaps %xmm2, 16(%rax)
movaps %xmm2, (%rax)
.LBB1_45: # in Loop: Header=BB1_34 Depth=1
incq %rcx
addq $256, %rdx # imm = 0x100
cmpq $64, %rcx
je .LBB1_46
.LBB1_34: # %.preheader125
# =>This Loop Header: Depth=1
# Child Loop BB1_36 Depth 2
# Child Loop BB1_41 Depth 2
movss (%r15,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm4, %xmm3
jne .LBB1_45
jp .LBB1_45
# %bb.35: # %.preheader124
# in Loop: Header=BB1_34 Depth=1
xorl %esi, %esi
jmp .LBB1_36
.p2align 4, 0x90
.LBB1_39: # in Loop: Header=BB1_36 Depth=2
incq %rsi
cmpq $64, %rsi
je .LBB1_40
.LBB1_36: # Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm3
jne .LBB1_39
jp .LBB1_39
# %bb.37: # in Loop: Header=BB1_36 Depth=2
movss (%r15,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm3
jb .LBB1_39
# %bb.38: # in Loop: Header=BB1_36 Depth=2
cvttss2si %xmm3, %edi
movslq %edi, %rdi
movb $1, (%rax,%rdi)
jmp .LBB1_39
.p2align 4, 0x90
.LBB1_40: # %.preheader.preheader
# in Loop: Header=BB1_34 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_41: # %.preheader
# Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rax,%rsi)
je .LBB1_42
# %bb.43: # in Loop: Header=BB1_41 Depth=2
incq %rsi
cmpq $64, %rsi
jne .LBB1_41
jmp .LBB1_44
.LBB1_46:
movq -56(%rbp), %rdi
callq hipFree
movq -48(%rbp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
callq hipDeviceReset
movq %r12, %rsp
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_47:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixColourPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixColourPfS_i,@object # @_Z12matrixColourPfS_i
.section .rodata,"a",@progbits
.globl _Z12matrixColourPfS_i
.p2align 3, 0x0
_Z12matrixColourPfS_i:
.quad _Z27__device_stub__matrixColourPfS_i
.size _Z12matrixColourPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Blocks "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Back Home i = "
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matrixColourPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixColourPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixColourPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074b1e_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12matrixColourPfS_iPfS_i
.type _Z35__device_stub__Z12matrixColourPfS_iPfS_i, @function
_Z35__device_stub__Z12matrixColourPfS_iPfS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixColourPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z12matrixColourPfS_iPfS_i, .-_Z35__device_stub__Z12matrixColourPfS_iPfS_i
.globl _Z12matrixColourPfS_i
.type _Z12matrixColourPfS_i, @function
_Z12matrixColourPfS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12matrixColourPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12matrixColourPfS_i, .-_Z12matrixColourPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Blocks "
.LC3:
.string " "
.LC4:
.string "Back Home i = "
.LC5:
.string " ; "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $16384, %edi
call _Znam@PLT
movq %rax, %r14
movl $256, %edi
call _Znam@PLT
movq %rax, %r15
movl $256, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %r13d
movl $64, %r12d
movl $0, %ebp
jmp .L15
.L63:
movslq %ebx, %rax
movl $0x00000000, (%r14,%rax,4)
.L13:
addl $1, %ebx
cmpl %r12d, %ebx
je .L62
.L14:
leal (%rbx,%r13), %eax
cmpl %ebp, %eax
je .L63
call rand@PLT
movslq %ebx, %rcx
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r14,%rcx,4)
jmp .L13
.L62:
addq $1, %rbp
addl $64, %r12d
subl $64, %r13d
cmpq $64, %rbp
je .L64
.L15:
movl $0xbf800000, (%r15,%rbp,4)
movq 8(%rsp), %rax
movl $0xbf800000, (%rax,%rbp,4)
movl %ebp, %ebx
sall $6, %ebx
jmp .L14
.L64:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $32, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L16:
movl $2, %ecx
movl $256, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $1, %ebx
leaq _ZSt4cout(%rip), %r13
jmp .L23
.L65:
movl $64, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z12matrixColourPfS_iPfS_i
jmp .L16
.L68:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L69:
movzbl 67(%r12), %esi
.L22:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L17:
addq $1, %rbx
cmpq $65, %rbx
je .L67
.L23:
movss .LC0(%rip), %xmm7
ucomiss -4(%r15,%rbx,4), %xmm7
jp .L45
je .L17
.L45:
movl $14, %edx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd -4(%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L68
cmpb $0, 56(%r12)
jne .L69
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L67:
pxor %xmm0, %xmm0
movups %xmm0, 64(%rsp)
movups %xmm0, 80(%rsp)
movups %xmm0, 96(%rsp)
movups %xmm0, 112(%rsp)
movq %r14, %rdx
movq %r14, %rcx
movl $0, %edi
movss .LC0(%rip), %xmm6
movaps %xmm6, %xmm5
movss .LC6(%rip), %xmm1
movaps %xmm1, %xmm2
pxor %xmm3, %xmm3
leaq 64(%rsp), %r8
movdqa %xmm0, %xmm4
jmp .L33
.L71:
cvttss2sil %xmm0, %esi
movslq %esi, %rsi
movb $1, 64(%rsp,%rsi)
.L26:
addq $4, %rax
cmpq $256, %rax
je .L70
.L29:
ucomiss (%rcx,%rax), %xmm1
jp .L26
ucomiss (%rcx,%rax), %xmm2
jne .L26
movss (%r15,%rax), %xmm0
comiss %xmm3, %xmm0
jnb .L71
jmp .L26
.L70:
movl $0, %eax
.L32:
cmpb $0, (%rax,%r8)
je .L72
addq $1, %rax
cmpq $64, %rax
jne .L32
jmp .L31
.L72:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rdi,4)
.L31:
movups %xmm4, (%r8)
movups %xmm4, 16(%r8)
movups %xmm4, 32(%r8)
movups %xmm4, 48(%r8)
.L24:
addq $1, %rdi
addq $256, %rcx
cmpq $64, %rdi
je .L73
.L33:
ucomiss (%r15,%rdi,4), %xmm6
jp .L24
ucomiss (%r15,%rdi,4), %xmm5
jne .L24
movl $0, %eax
jmp .L29
.L73:
movl $0, %esi
movss .LC0(%rip), %xmm6
movaps %xmm6, %xmm5
movss .LC6(%rip), %xmm1
movaps %xmm1, %xmm2
pxor %xmm3, %xmm3
leaq 64(%rsp), %rdi
pxor %xmm4, %xmm4
jmp .L43
.L36:
addq $4, %rax
cmpq $256, %rax
je .L74
.L39:
ucomiss (%rdx,%rax), %xmm1
jp .L36
ucomiss (%rdx,%rax), %xmm2
jne .L36
movq 8(%rsp), %rcx
movss (%rcx,%rax), %xmm0
comiss %xmm3, %xmm0
jb .L36
cvttss2sil %xmm0, %ecx
movslq %ecx, %rcx
movb $1, 64(%rsp,%rcx)
jmp .L36
.L74:
movl $0, %eax
.L42:
cmpb $0, (%rax,%rdi)
je .L75
addq $1, %rax
cmpq $64, %rax
jne .L42
jmp .L41
.L75:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rsi,4)
.L41:
movups %xmm4, (%rdi)
movups %xmm4, 16(%rdi)
movups %xmm4, 32(%rdi)
movups %xmm4, 48(%rdi)
.L34:
addq $1, %rsi
addq $256, %rdx
cmpq $64, %rsi
je .L76
.L43:
movq 8(%rsp), %rax
ucomiss (%rax,%rsi,4), %xmm6
jp .L34
ucomiss (%rax,%rsi,4), %xmm5
jne .L34
movl $0, %eax
jmp .L39
.L76:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L77
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12matrixColourPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixColourPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1082130432
.align 4
.LC6:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__matrixColourPfS_i # -- Begin function _Z27__device_stub__matrixColourPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__matrixColourPfS_i,@function
_Z27__device_stub__matrixColourPfS_i: # @_Z27__device_stub__matrixColourPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixColourPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixColourPfS_i, .Lfunc_end0-_Z27__device_stub__matrixColourPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xbf800000 # float -1
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $16384, %edi # imm = 0x4000
callq _Znam
movq %rax, %r13
movl $256, %edi # imm = 0x100
callq _Znam
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
movq %r13, -72(%rbp) # 8-byte Spill
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $256, %r13 # imm = 0x100
cmpq $64, %r12
je .LBB1_6
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $-1082130432, (%r14,%r12,4) # imm = 0xBF800000
movl $-1082130432, (%r15,%r12,4) # imm = 0xBF800000
xorl %ebx, %ebx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $64, %rbx
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cmpq %rbx, %r12
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
jmp .LBB1_4
.LBB1_6:
movq $0, -56(%rbp)
leaq -56(%rbp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movq $0, -48(%rbp)
leaq -48(%rbp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq -56(%rbp), %rdi
movl $16384, %edx # imm = 0x4000
movq -72(%rbp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq -48(%rbp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $32, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
movl $2, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_47
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_9
# %bb.8:
movzbl 67(%r12), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq -56(%rbp), %rax
movq -48(%rbp), %rcx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movl $64, -60(%rbp)
leaq -136(%rbp), %rax
movq %rax, -160(%rbp)
leaq -128(%rbp), %rax
movq %rax, -152(%rbp)
leaq -60(%rbp), %rax
movq %rax, -144(%rbp)
leaq -120(%rbp), %rdi
leaq -104(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -120(%rbp), %rsi
movl -112(%rbp), %edx
movq -104(%rbp), %rcx
movl -96(%rbp), %r8d
leaq -160(%rbp), %r9
movl $_Z12matrixColourPfS_i, %edi
pushq -80(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_12:
movq -48(%rbp), %rsi
movl $256, %edx # imm = 0x100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_13 Depth=1
movq %r12, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit120
# in Loop: Header=BB1_13 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movss .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
.LBB1_19: # in Loop: Header=BB1_13 Depth=1
incq %r13
cmpq $64, %r13
je .LBB1_20
.LBB1_13: # =>This Inner Loop Header: Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm4, %xmm0
jne .LBB1_14
jnp .LBB1_19
.LBB1_14: # in Loop: Header=BB1_13 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leal 1(%r13), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_47
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i117
# in Loop: Header=BB1_13 Depth=1
cmpb $0, 56(%r12)
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_13 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_18
.LBB1_20:
movq %rsp, %r12
movq %rsp, %rcx
leaq -64(%rcx), %rax
movq %rax, %rsp
xorps %xmm1, %xmm1
movaps %xmm1, -16(%rcx)
movaps %xmm1, -32(%rcx)
movaps %xmm1, -48(%rcx)
movaps %xmm1, -64(%rcx)
xorl %ecx, %ecx
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
movq -72(%rbp), %rbx # 8-byte Reload
movq %rbx, %rdx
jmp .LBB1_21
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_21 Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
movss %xmm3, (%r14,%rcx,4)
.LBB1_31: # %.loopexit127
# in Loop: Header=BB1_21 Depth=1
movaps %xmm1, 48(%rax)
movaps %xmm1, 32(%rax)
movaps %xmm1, 16(%rax)
movaps %xmm1, (%rax)
.LBB1_32: # in Loop: Header=BB1_21 Depth=1
incq %rcx
addq $256, %rdx # imm = 0x100
cmpq $64, %rcx
je .LBB1_33
.LBB1_21: # =>This Loop Header: Depth=1
# Child Loop BB1_23 Depth 2
# Child Loop BB1_28 Depth 2
movss (%r14,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm4, %xmm3
jne .LBB1_32
jp .LBB1_32
# %bb.22: # %.preheader128
# in Loop: Header=BB1_21 Depth=1
xorl %esi, %esi
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_23 Depth=2
incq %rsi
cmpq $64, %rsi
je .LBB1_27
.LBB1_23: # Parent Loop BB1_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm3
jne .LBB1_26
jp .LBB1_26
# %bb.24: # in Loop: Header=BB1_23 Depth=2
movss (%r14,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm3
jb .LBB1_26
# %bb.25: # in Loop: Header=BB1_23 Depth=2
cvttss2si %xmm3, %edi
movslq %edi, %rdi
movb $1, (%rax,%rdi)
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_27: # %.preheader126.preheader
# in Loop: Header=BB1_21 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_28: # %.preheader126
# Parent Loop BB1_21 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rax,%rsi)
je .LBB1_29
# %bb.30: # in Loop: Header=BB1_28 Depth=2
incq %rsi
cmpq $64, %rsi
jne .LBB1_28
jmp .LBB1_31
.LBB1_33: # %.preheader125.preheader
xorl %ecx, %ecx
xorps %xmm1, %xmm1
xorps %xmm2, %xmm2
movq %rbx, %rdx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_42: # in Loop: Header=BB1_34 Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
movss %xmm3, (%r15,%rcx,4)
.LBB1_44: # %.loopexit
# in Loop: Header=BB1_34 Depth=1
movaps %xmm2, 48(%rax)
movaps %xmm2, 32(%rax)
movaps %xmm2, 16(%rax)
movaps %xmm2, (%rax)
.LBB1_45: # in Loop: Header=BB1_34 Depth=1
incq %rcx
addq $256, %rdx # imm = 0x100
cmpq $64, %rcx
je .LBB1_46
.LBB1_34: # %.preheader125
# =>This Loop Header: Depth=1
# Child Loop BB1_36 Depth 2
# Child Loop BB1_41 Depth 2
movss (%r15,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm4, %xmm3
jne .LBB1_45
jp .LBB1_45
# %bb.35: # %.preheader124
# in Loop: Header=BB1_34 Depth=1
xorl %esi, %esi
jmp .LBB1_36
.p2align 4, 0x90
.LBB1_39: # in Loop: Header=BB1_36 Depth=2
incq %rsi
cmpq $64, %rsi
je .LBB1_40
.LBB1_36: # Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm3
jne .LBB1_39
jp .LBB1_39
# %bb.37: # in Loop: Header=BB1_36 Depth=2
movss (%r15,%rsi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm3
jb .LBB1_39
# %bb.38: # in Loop: Header=BB1_36 Depth=2
cvttss2si %xmm3, %edi
movslq %edi, %rdi
movb $1, (%rax,%rdi)
jmp .LBB1_39
.p2align 4, 0x90
.LBB1_40: # %.preheader.preheader
# in Loop: Header=BB1_34 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_41: # %.preheader
# Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rax,%rsi)
je .LBB1_42
# %bb.43: # in Loop: Header=BB1_41 Depth=2
incq %rsi
cmpq $64, %rsi
jne .LBB1_41
jmp .LBB1_44
.LBB1_46:
movq -56(%rbp), %rdi
callq hipFree
movq -48(%rbp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
callq hipDeviceReset
movq %r12, %rsp
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_47:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixColourPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixColourPfS_i,@object # @_Z12matrixColourPfS_i
.section .rodata,"a",@progbits
.globl _Z12matrixColourPfS_i
.p2align 3, 0x0
_Z12matrixColourPfS_i:
.quad _Z27__device_stub__matrixColourPfS_i
.size _Z12matrixColourPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Blocks "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Back Home i = "
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matrixColourPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixColourPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixColourPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
/*// Created by sergio on 13/02/19.
//
#include <iostream>
#include <stdint.h> // Para medir el clock
#include <cstdlib> // std
#include <iomanip> // Formateo de datos
#include <string>
#define CWIDTHLEFT 40
#define CWIDTHRIGHT 30
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
int main(){
int devCount = 1;
if (devCount == 0)
{
std::cout << "No se detecto el modulo cuda cargado";
exit (-1);
}
for (int i = 0; i < devCount; i++)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties (&devProp, i);
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << std::setfill ('*') << " Info de la placa cuda "
<< i << " ";
std::cout.unsetf (std::ios::right);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHRIGHT - 2) << std::setfill ('*') << "(todo en bytes) ";
std::cout << std::endl;
std::cout.unsetf (std::ios::left);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHLEFT) << std::setfill (' ') << "Nombre:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.name << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria Global:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalGlobalMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Memoria shared por bloque (SMM): ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.sharedMemPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Registros por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.regsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Wrap size: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.warpSize << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por SMM: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerMultiProcessor
<< std::endl;
std::cout.unsetf (std::ios::right);
//Dimeciones maximas por bloque
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por bloque:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsDim[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
//Dimeciones maximas por grid
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por grid:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxGridSize[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
std::cout << std::setw (CWIDTHLEFT) << "Clock rate: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.clockRate << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria constante: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalConstMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Soporta copia y ejecucion concurrente: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << (devProp.deviceOverlap ? "Sep" : "No")
<< std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Multiprocesadores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.multiProcessorCount << std::endl;
std::cout.unsetf (std::ios::right);
// Calculo de cuda cores
int mp = devProp.multiProcessorCount;
int cores;
switch (devProp.major)
{
case 2: // Fermi
if (devProp.minor == 1)
cores = mp * 48;
else
cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if (devProp.minor == 1)
cores = mp * 128;
else if (devProp.minor == 0)
cores = mp * 64;
else
std::cout << " desconocido ";
break;
default:
std::cout << " desconocido ";
break;
}
std::cout << std::setw (CWIDTHLEFT) << "Cuda cores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << cores << std::endl;
std::cout.unsetf (std::ios::right);
}
}
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
/*// Created by sergio on 13/02/19.
//
#include <iostream>
#include <stdint.h> // Para medir el clock
#include <cstdlib> // std
#include <iomanip> // Formateo de datos
#include <string>
#define CWIDTHLEFT 40
#define CWIDTHRIGHT 30
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
int main(){
int devCount = 1;
if (devCount == 0)
{
std::cout << "No se detecto el modulo cuda cargado";
exit (-1);
}
for (int i = 0; i < devCount; i++)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties (&devProp, i);
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << std::setfill ('*') << " Info de la placa cuda "
<< i << " ";
std::cout.unsetf (std::ios::right);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHRIGHT - 2) << std::setfill ('*') << "(todo en bytes) ";
std::cout << std::endl;
std::cout.unsetf (std::ios::left);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHLEFT) << std::setfill (' ') << "Nombre:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.name << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria Global:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalGlobalMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Memoria shared por bloque (SMM): ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.sharedMemPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Registros por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.regsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Wrap size: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.warpSize << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por SMM: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerMultiProcessor
<< std::endl;
std::cout.unsetf (std::ios::right);
//Dimeciones maximas por bloque
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por bloque:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsDim[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
//Dimeciones maximas por grid
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por grid:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxGridSize[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
std::cout << std::setw (CWIDTHLEFT) << "Clock rate: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.clockRate << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria constante: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalConstMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Soporta copia y ejecucion concurrente: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << (devProp.deviceOverlap ? "Sep" : "No")
<< std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Multiprocesadores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.multiProcessorCount << std::endl;
std::cout.unsetf (std::ios::right);
// Calculo de cuda cores
int mp = devProp.multiProcessorCount;
int cores;
switch (devProp.major)
{
case 2: // Fermi
if (devProp.minor == 1)
cores = mp * 48;
else
cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if (devProp.minor == 1)
cores = mp * 128;
else if (devProp.minor == 0)
cores = mp * 64;
else
std::cout << " desconocido ";
break;
default:
std::cout << " desconocido ";
break;
}
std::cout << std::setw (CWIDTHLEFT) << "Cuda cores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << cores << std::endl;
std::cout.unsetf (std::ios::right);
}
}
*/ | .file "tmpxft_000b1223_00000000-6_cudainfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
/*// Created by sergio on 13/02/19.
//
#include <iostream>
#include <stdint.h> // Para medir el clock
#include <cstdlib> // std
#include <iomanip> // Formateo de datos
#include <string>
#define CWIDTHLEFT 40
#define CWIDTHRIGHT 30
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
int main(){
int devCount = 1;
if (devCount == 0)
{
std::cout << "No se detecto el modulo cuda cargado";
exit (-1);
}
for (int i = 0; i < devCount; i++)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties (&devProp, i);
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << std::setfill ('*') << " Info de la placa cuda "
<< i << " ";
std::cout.unsetf (std::ios::right);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHRIGHT - 2) << std::setfill ('*') << "(todo en bytes) ";
std::cout << std::endl;
std::cout.unsetf (std::ios::left);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHLEFT) << std::setfill (' ') << "Nombre:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.name << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria Global:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalGlobalMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Memoria shared por bloque (SMM): ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.sharedMemPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Registros por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.regsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Wrap size: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.warpSize << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por SMM: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerMultiProcessor
<< std::endl;
std::cout.unsetf (std::ios::right);
//Dimeciones maximas por bloque
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por bloque:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsDim[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
//Dimeciones maximas por grid
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por grid:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxGridSize[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
std::cout << std::setw (CWIDTHLEFT) << "Clock rate: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.clockRate << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria constante: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalConstMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Soporta copia y ejecucion concurrente: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << (devProp.deviceOverlap ? "Sep" : "No")
<< std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Multiprocesadores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.multiProcessorCount << std::endl;
std::cout.unsetf (std::ios::right);
// Calculo de cuda cores
int mp = devProp.multiProcessorCount;
int cores;
switch (devProp.major)
{
case 2: // Fermi
if (devProp.minor == 1)
cores = mp * 48;
else
cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if (devProp.minor == 1)
cores = mp * 128;
else if (devProp.minor == 0)
cores = mp * 64;
else
std::cout << " desconocido ";
break;
default:
std::cout << " desconocido ";
break;
}
std::cout << std::setw (CWIDTHLEFT) << "Cuda cores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << cores << std::endl;
std::cout.unsetf (std::ios::right);
}
}
*/ | #include <hip/hip_runtime.h>
//
/*// Created by sergio on 13/02/19.
//
#include <iostream>
#include <stdint.h> // Para medir el clock
#include <cstdlib> // std
#include <iomanip> // Formateo de datos
#include <string>
#define CWIDTHLEFT 40
#define CWIDTHRIGHT 30
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
int main(){
int devCount = 1;
if (devCount == 0)
{
std::cout << "No se detecto el modulo cuda cargado";
exit (-1);
}
for (int i = 0; i < devCount; i++)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties (&devProp, i);
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << std::setfill ('*') << " Info de la placa cuda "
<< i << " ";
std::cout.unsetf (std::ios::right);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHRIGHT - 2) << std::setfill ('*') << "(todo en bytes) ";
std::cout << std::endl;
std::cout.unsetf (std::ios::left);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHLEFT) << std::setfill (' ') << "Nombre:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.name << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria Global:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalGlobalMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Memoria shared por bloque (SMM): ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.sharedMemPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Registros por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.regsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Wrap size: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.warpSize << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por SMM: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerMultiProcessor
<< std::endl;
std::cout.unsetf (std::ios::right);
//Dimeciones maximas por bloque
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por bloque:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsDim[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
//Dimeciones maximas por grid
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por grid:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxGridSize[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
std::cout << std::setw (CWIDTHLEFT) << "Clock rate: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.clockRate << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria constante: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalConstMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Soporta copia y ejecucion concurrente: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << (devProp.deviceOverlap ? "Sep" : "No")
<< std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Multiprocesadores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.multiProcessorCount << std::endl;
std::cout.unsetf (std::ios::right);
// Calculo de cuda cores
int mp = devProp.multiProcessorCount;
int cores;
switch (devProp.major)
{
case 2: // Fermi
if (devProp.minor == 1)
cores = mp * 48;
else
cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if (devProp.minor == 1)
cores = mp * 128;
else if (devProp.minor == 0)
cores = mp * 64;
else
std::cout << " desconocido ";
break;
default:
std::cout << " desconocido ";
break;
}
std::cout << std::setw (CWIDTHLEFT) << "Cuda cores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << cores << std::endl;
std::cout.unsetf (std::ios::right);
}
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//
/*// Created by sergio on 13/02/19.
//
#include <iostream>
#include <stdint.h> // Para medir el clock
#include <cstdlib> // std
#include <iomanip> // Formateo de datos
#include <string>
#define CWIDTHLEFT 40
#define CWIDTHRIGHT 30
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
int main(){
int devCount = 1;
if (devCount == 0)
{
std::cout << "No se detecto el modulo cuda cargado";
exit (-1);
}
for (int i = 0; i < devCount; i++)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties (&devProp, i);
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << std::setfill ('*') << " Info de la placa cuda "
<< i << " ";
std::cout.unsetf (std::ios::right);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHRIGHT - 2) << std::setfill ('*') << "(todo en bytes) ";
std::cout << std::endl;
std::cout.unsetf (std::ios::left);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHLEFT) << std::setfill (' ') << "Nombre:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.name << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria Global:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalGlobalMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Memoria shared por bloque (SMM): ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.sharedMemPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Registros por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.regsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Wrap size: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.warpSize << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por SMM: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerMultiProcessor
<< std::endl;
std::cout.unsetf (std::ios::right);
//Dimeciones maximas por bloque
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por bloque:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsDim[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
//Dimeciones maximas por grid
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por grid:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxGridSize[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
std::cout << std::setw (CWIDTHLEFT) << "Clock rate: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.clockRate << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria constante: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalConstMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Soporta copia y ejecucion concurrente: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << (devProp.deviceOverlap ? "Sep" : "No")
<< std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Multiprocesadores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.multiProcessorCount << std::endl;
std::cout.unsetf (std::ios::right);
// Calculo de cuda cores
int mp = devProp.multiProcessorCount;
int cores;
switch (devProp.major)
{
case 2: // Fermi
if (devProp.minor == 1)
cores = mp * 48;
else
cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if (devProp.minor == 1)
cores = mp * 128;
else if (devProp.minor == 0)
cores = mp * 64;
else
std::cout << " desconocido ";
break;
default:
std::cout << " desconocido ";
break;
}
std::cout << std::setw (CWIDTHLEFT) << "Cuda cores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << cores << std::endl;
std::cout.unsetf (std::ios::right);
}
}
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//
/*// Created by sergio on 13/02/19.
//
#include <iostream>
#include <stdint.h> // Para medir el clock
#include <cstdlib> // std
#include <iomanip> // Formateo de datos
#include <string>
#define CWIDTHLEFT 40
#define CWIDTHRIGHT 30
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <device_functions.h>
int main(){
int devCount = 1;
if (devCount == 0)
{
std::cout << "No se detecto el modulo cuda cargado";
exit (-1);
}
for (int i = 0; i < devCount; i++)
{
cudaDeviceProp devProp;
cudaGetDeviceProperties (&devProp, i);
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << std::setfill ('*') << " Info de la placa cuda "
<< i << " ";
std::cout.unsetf (std::ios::right);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHRIGHT - 2) << std::setfill ('*') << "(todo en bytes) ";
std::cout << std::endl;
std::cout.unsetf (std::ios::left);
std::cout.setf (std::ios::left);
std::cout << std::setw (CWIDTHLEFT) << std::setfill (' ') << "Nombre:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.name << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria Global:";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalGlobalMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Memoria shared por bloque (SMM): ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.sharedMemPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Registros por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.regsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Wrap size: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.warpSize << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por bloque: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerBlock << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Max threads por SMM: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsPerMultiProcessor
<< std::endl;
std::cout.unsetf (std::ios::right);
//Dimeciones maximas por bloque
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por bloque:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxThreadsDim[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
//Dimeciones maximas por grid
for (int j = 0; j < 3; ++j)
{
// c++11
std::string sstr = "Dimecion maxima " + std::to_string (j) + " por grid:";
std::cout << std::setw (CWIDTHLEFT) << sstr;
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.maxGridSize[j] << std::endl;
std::cout.unsetf (std::ios::right);
}
std::cout << std::setw (CWIDTHLEFT) << "Clock rate: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.clockRate << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Total Memoria constante: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.totalConstMem << std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Soporta copia y ejecucion concurrente: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << (devProp.deviceOverlap ? "Sep" : "No")
<< std::endl;
std::cout.unsetf (std::ios::right);
std::cout << std::setw (CWIDTHLEFT) << "Multiprocesadores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << devProp.multiProcessorCount << std::endl;
std::cout.unsetf (std::ios::right);
// Calculo de cuda cores
int mp = devProp.multiProcessorCount;
int cores;
switch (devProp.major)
{
case 2: // Fermi
if (devProp.minor == 1)
cores = mp * 48;
else
cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if (devProp.minor == 1)
cores = mp * 128;
else if (devProp.minor == 0)
cores = mp * 64;
else
std::cout << " desconocido ";
break;
default:
std::cout << " desconocido ";
break;
}
std::cout << std::setw (CWIDTHLEFT) << "Cuda cores: ";
std::cout.setf (std::ios::right);
std::cout << std::setw (CWIDTHRIGHT) << cores << std::endl;
std::cout.unsetf (std::ios::right);
}
}
*/ | .text
.file "cudainfo.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b1223_00000000-6_cudainfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudainfo.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include<iostream>
using namespace std;
#include <device_launch_parameters.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int id = threadIdx.x;
if (id < N)
{
c[id] = b[id] + a[id];
}
}
int main(void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a, sizeof(int) * N);
cudaMalloc((void**)&dev_b, sizeof(int) * N);
cudaMalloc((void**)&dev_c, sizeof(int) * N);
for (int i = 0; i < N; i++)
{
a[i] = -i;
b[i] = i * i;
}
cudaMemcpy(dev_a, a, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(int) * N, cudaMemcpyHostToDevice);
//Invoke device, N within <<<>>> defines N threads are allocated to run in parallel within one block
add <<<1, N>>> (dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
cout << "Element at " << i << " is: " << c[i] << endl;
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include<iostream>
using namespace std;
#include <device_launch_parameters.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int id = threadIdx.x;
if (id < N)
{
c[id] = b[id] + a[id];
}
}
int main(void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a, sizeof(int) * N);
cudaMalloc((void**)&dev_b, sizeof(int) * N);
cudaMalloc((void**)&dev_c, sizeof(int) * N);
for (int i = 0; i < N; i++)
{
a[i] = -i;
b[i] = i * i;
}
cudaMemcpy(dev_a, a, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(int) * N, cudaMemcpyHostToDevice);
//Invoke device, N within <<<>>> defines N threads are allocated to run in parallel within one block
add <<<1, N>>> (dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
cout << "Element at " << i << " is: " << c[i] << endl;
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
} | .file "tmpxft_000f189e_00000000-6_parallel_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Element at "
.LC1:
.string " is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movl $0, 48(%rsp)
movl $0, 80(%rsp)
movl $-1, 52(%rsp)
movl $1, 84(%rsp)
movl $-2, 56(%rsp)
movl $4, 88(%rsp)
movl $-3, 60(%rsp)
movl $9, 92(%rsp)
movl $-4, 64(%rsp)
movl $16, 96(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L17
.L21:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $5, %rbp
je .L23
.L17:
movl $11, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $5, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 112(%rsp,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L24
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
jmp .L16
.L23:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include<iostream>
using namespace std;
#include <device_launch_parameters.h>
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int id = threadIdx.x;
if (id < N)
{
c[id] = b[id] + a[id];
}
}
int main(void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a, sizeof(int) * N);
cudaMalloc((void**)&dev_b, sizeof(int) * N);
cudaMalloc((void**)&dev_c, sizeof(int) * N);
for (int i = 0; i < N; i++)
{
a[i] = -i;
b[i] = i * i;
}
cudaMemcpy(dev_a, a, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(int) * N, cudaMemcpyHostToDevice);
//Invoke device, N within <<<>>> defines N threads are allocated to run in parallel within one block
add <<<1, N>>> (dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
cout << "Element at " << i << " is: " << c[i] << endl;
}
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int id = threadIdx.x;
if (id < N)
{
c[id] = b[id] + a[id];
}
}
int main(void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a, sizeof(int) * N);
hipMalloc((void**)&dev_b, sizeof(int) * N);
hipMalloc((void**)&dev_c, sizeof(int) * N);
for (int i = 0; i < N; i++)
{
a[i] = -i;
b[i] = i * i;
}
hipMemcpy(dev_a, a, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(int) * N, hipMemcpyHostToDevice);
//Invoke device, N within <<<>>> defines N threads are allocated to run in parallel within one block
add <<<1, N>>> (dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
cout << "Element at " << i << " is: " << c[i] << endl;
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int id = threadIdx.x;
if (id < N)
{
c[id] = b[id] + a[id];
}
}
int main(void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a, sizeof(int) * N);
hipMalloc((void**)&dev_b, sizeof(int) * N);
hipMalloc((void**)&dev_c, sizeof(int) * N);
for (int i = 0; i < N; i++)
{
a[i] = -i;
b[i] = i * i;
}
hipMemcpy(dev_a, a, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(int) * N, hipMemcpyHostToDevice);
//Invoke device, N within <<<>>> defines N threads are allocated to run in parallel within one block
add <<<1, N>>> (dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
cout << "Element at " << i << " is: " << c[i] << endl;
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 5, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
#define N 5
__global__ void add(int* a, int* b, int* c)
{
int id = threadIdx.x;
if (id < N)
{
c[id] = b[id] + a[id];
}
}
int main(void) {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a, sizeof(int) * N);
hipMalloc((void**)&dev_b, sizeof(int) * N);
hipMalloc((void**)&dev_c, sizeof(int) * N);
for (int i = 0; i < N; i++)
{
a[i] = -i;
b[i] = i * i;
}
hipMemcpy(dev_a, a, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(int) * N, hipMemcpyHostToDevice);
//Invoke device, N within <<<>>> defines N threads are allocated to run in parallel within one block
add <<<1, N>>> (dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
cout << "Element at " << i << " is: " << c[i] << endl;
}
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
} | .text
.file "parallel_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $224, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 160(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $5, %rcx
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $5, %rbx
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 128(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r14)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_9
.LBB1_10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $224, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Element at "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " is: "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 5, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f189e_00000000-6_parallel_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Element at "
.LC1:
.string " is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movl $0, 48(%rsp)
movl $0, 80(%rsp)
movl $-1, 52(%rsp)
movl $1, 84(%rsp)
movl $-2, 56(%rsp)
movl $4, 88(%rsp)
movl $-3, 60(%rsp)
movl $9, 92(%rsp)
movl $-4, 64(%rsp)
movl $16, 96(%rsp)
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L17
.L21:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $5, %rbp
je .L23
.L17:
movl $11, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $5, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 112(%rsp,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L24
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
jmp .L16
.L23:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $224, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 160(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $5, %rcx
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq $5, %rbx
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 128(%rsp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r14)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_9
.LBB1_10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $224, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Element at "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " is: "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <time.h>
#include <cuda.h>
#include <stdio.h>
#define STOP 0
#define START 1
#define BLOCKSIZE 256
extern "C" void chrono (int kind, float *time);
__global__ void kconvol (float *gpu_a, float *gpu_b, int n) {
int i, j, l;
// TO DO : evaluate the global 1D index l of the current thread,
// using blockDim, blockIdx and threadIdx.
l = blockDim.x*blockIdx.x+threadIdx.x;
// TO DO : evaluate global indeces of thread (i,j) from the index l
j = l/n;
i = l%n;
if ((i >= n) || (j >= n)) return;
if ((i == 0) || (j == 0) || (i == n-1) || (j == n-1)) {
gpu_b[l] = gpu_a[l]; // edges are untouched
}
else
// TO DO : fill up the MISSING indices below
gpu_b[l]=(1./5.)*(gpu_a[l-n] + gpu_a[l-1] + gpu_a[l] + gpu_a[l+1]+ gpu_a[l+n]);
}
extern "C" void gpu_convol (float *a, float *b, int n) {
float *gpu_a;
float *gpu_b;
cudaError_t err;
float time;
err = cudaMalloc (&gpu_a, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_a: %s\n", cudaGetErrorString (err));
exit (1);
}
err = cudaMalloc (&gpu_b, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_b: %s\n", cudaGetErrorString (err));
exit (1);
}
cudaMemcpy (gpu_a, a, n*n*sizeof(float), cudaMemcpyHostToDevice);
// NOTE : the chronometer below does not contemplate overhead of memory allocation and
// memory transfer.
chrono (START, &time);
// TO DO : the number of blocks is missing below in the kernel invocation
kconvol <<<n*n/BLOCKSIZE+1,BLOCKSIZE>>> (gpu_a, gpu_b, n);
err=cudaDeviceSynchronize ();
chrono (STOP, &time);
printf ("Convolution took %f sec. on GPU\n", time);
cudaMemcpy (b, gpu_b, n*n*sizeof(float), cudaMemcpyDeviceToHost);
if (err != 0) {
printf ("%s\n", cudaGetErrorString (err));
exit (1);
}
cudaFree (gpu_a);
cudaFree (gpu_b);
} | code for sm_80
Function : _Z7kconvolPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fe200078e0204 */
/*0110*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fc800078e3cff */
/*0120*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe40003f44070 */
/*0130*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f06270 */
/*0140*/ LOP3.LUT R4, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff047a12 */
/* 0x000fd200078e33ff */
/*0150*/ @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a07 */
/*0160*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fc80007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc60003f25270 */
/*01a0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fca00078e0a03 */
/*01b0*/ SEL R5, R4, R3, !P1 ; /* 0x0000000304057207 */
/* 0x000fc80004800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06270 */
/*01d0*/ ISETP.GT.OR P0, PT, RZ, c[0x0][0x170], P0 ; /* 0x00005c00ff007a0c */
/* 0x000fda0000704670 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0200*/ IMAD.IADD R3, R2, 0x1, -R7 ; /* 0x0000000102037824 */
/* 0x000fe200078e0a07 */
/*0210*/ ISETP.GT.U32.AND P0, PT, R7, R2.reuse, PT ; /* 0x000000020700720c */
/* 0x080fe20003f04070 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x000fe200078e00ff */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0250*/ SEL R3, R3, R2, !P0 ; /* 0x0000000203037207 */
/* 0x000fe40004000000 */
/*0260*/ IADD3 R2, R9, -0x1, RZ ; /* 0xffffffff09027810 */
/* 0x000fca0007ffe0ff */
/*0270*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*0280*/ SEL R3, R4, R3, !P1 ; /* 0x0000000304037207 */
/* 0x000fc80004800000 */
/*0290*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05270 */
/*02a0*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fc80004702670 */
/*02b0*/ ISETP.EQ.OR P0, PT, R3, R2, P0 ; /* 0x000000020300720c */
/* 0x000fc80000702670 */
/*02c0*/ ISETP.EQ.OR P0, PT, R5, R2, P0 ; /* 0x000000020500720c */
/* 0x000fe20000702670 */
/*02d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*02e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0207 */
/*02f0*/ @P0 BRA 0x410 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R6, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000067a10 */
/* 0x000fe20007ffe0ff */
/*0310*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea8000c1e1900 */
/*0320*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0330*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ee6000c1e1900 */
/*0340*/ IMAD.WIDE R8, R9, 0x4, R4 ; /* 0x0000000409087825 */
/* 0x000fe200078e0204 */
/*0350*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000f28000c1e1900 */
/*0360*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*0370*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f62000c1e1900 */
/*0380*/ FADD R0, R0, R7 ; /* 0x0000000700007221 */
/* 0x008fc80000000000 */
/*0390*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x004fc80000000000 */
/*03a0*/ FADD R0, R0, R13 ; /* 0x0000000d00007221 */
/* 0x010fc80000000000 */
/*03b0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x020fc80000000000 */
/*03c0*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x000e240000201800 */
/*03d0*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*03e0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*03f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x001fe2000c101904 */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0420*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <time.h>
#include <cuda.h>
#include <stdio.h>
#define STOP 0
#define START 1
#define BLOCKSIZE 256
extern "C" void chrono (int kind, float *time);
__global__ void kconvol (float *gpu_a, float *gpu_b, int n) {
int i, j, l;
// TO DO : evaluate the global 1D index l of the current thread,
// using blockDim, blockIdx and threadIdx.
l = blockDim.x*blockIdx.x+threadIdx.x;
// TO DO : evaluate global indeces of thread (i,j) from the index l
j = l/n;
i = l%n;
if ((i >= n) || (j >= n)) return;
if ((i == 0) || (j == 0) || (i == n-1) || (j == n-1)) {
gpu_b[l] = gpu_a[l]; // edges are untouched
}
else
// TO DO : fill up the MISSING indices below
gpu_b[l]=(1./5.)*(gpu_a[l-n] + gpu_a[l-1] + gpu_a[l] + gpu_a[l+1]+ gpu_a[l+n]);
}
extern "C" void gpu_convol (float *a, float *b, int n) {
float *gpu_a;
float *gpu_b;
cudaError_t err;
float time;
err = cudaMalloc (&gpu_a, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_a: %s\n", cudaGetErrorString (err));
exit (1);
}
err = cudaMalloc (&gpu_b, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_b: %s\n", cudaGetErrorString (err));
exit (1);
}
cudaMemcpy (gpu_a, a, n*n*sizeof(float), cudaMemcpyHostToDevice);
// NOTE : the chronometer below does not contemplate overhead of memory allocation and
// memory transfer.
chrono (START, &time);
// TO DO : the number of blocks is missing below in the kernel invocation
kconvol <<<n*n/BLOCKSIZE+1,BLOCKSIZE>>> (gpu_a, gpu_b, n);
err=cudaDeviceSynchronize ();
chrono (STOP, &time);
printf ("Convolution took %f sec. on GPU\n", time);
cudaMemcpy (b, gpu_b, n*n*sizeof(float), cudaMemcpyDeviceToHost);
if (err != 0) {
printf ("%s\n", cudaGetErrorString (err));
exit (1);
}
cudaFree (gpu_a);
cudaFree (gpu_b);
} | .file "tmpxft_000d8ed6_00000000-6_convol.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7kconvolPfS_iPfS_i
.type _Z29__device_stub__Z7kconvolPfS_iPfS_i, @function
_Z29__device_stub__Z7kconvolPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kconvolPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7kconvolPfS_iPfS_i, .-_Z29__device_stub__Z7kconvolPfS_iPfS_i
.globl _Z7kconvolPfS_i
.type _Z7kconvolPfS_i, @function
_Z7kconvolPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kconvolPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7kconvolPfS_i, .-_Z7kconvolPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating gpu_a: %s\n"
.LC1:
.string "Error allocating gpu_b: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Convolution took %f sec. on GPU\n"
.section .rodata.str1.1
.LC3:
.string "%s\n"
.text
.globl gpu_convol
.type gpu_convol, @function
gpu_convol:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edx, %r13d
imull %edx, %r13d
movslq %r13d, %rbx
salq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L18
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %edi
call chrono@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
leal 255(%r13), %eax
testl %r13d, %r13d
cmovns %r13d, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L14:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
leaq 12(%rsp), %rsi
movl $0, %edi
call chrono@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebp, %ebp
jne .L21
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z7kconvolPfS_iPfS_i
jmp .L14
.L21:
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size gpu_convol, .-gpu_convol
.section .rodata.str1.1
.LC4:
.string "_Z7kconvolPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kconvolPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <time.h>
#include <cuda.h>
#include <stdio.h>
#define STOP 0
#define START 1
#define BLOCKSIZE 256
extern "C" void chrono (int kind, float *time);
__global__ void kconvol (float *gpu_a, float *gpu_b, int n) {
int i, j, l;
// TO DO : evaluate the global 1D index l of the current thread,
// using blockDim, blockIdx and threadIdx.
l = blockDim.x*blockIdx.x+threadIdx.x;
// TO DO : evaluate global indeces of thread (i,j) from the index l
j = l/n;
i = l%n;
if ((i >= n) || (j >= n)) return;
if ((i == 0) || (j == 0) || (i == n-1) || (j == n-1)) {
gpu_b[l] = gpu_a[l]; // edges are untouched
}
else
// TO DO : fill up the MISSING indices below
gpu_b[l]=(1./5.)*(gpu_a[l-n] + gpu_a[l-1] + gpu_a[l] + gpu_a[l+1]+ gpu_a[l+n]);
}
extern "C" void gpu_convol (float *a, float *b, int n) {
float *gpu_a;
float *gpu_b;
cudaError_t err;
float time;
err = cudaMalloc (&gpu_a, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_a: %s\n", cudaGetErrorString (err));
exit (1);
}
err = cudaMalloc (&gpu_b, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_b: %s\n", cudaGetErrorString (err));
exit (1);
}
cudaMemcpy (gpu_a, a, n*n*sizeof(float), cudaMemcpyHostToDevice);
// NOTE : the chronometer below does not contemplate overhead of memory allocation and
// memory transfer.
chrono (START, &time);
// TO DO : the number of blocks is missing below in the kernel invocation
kconvol <<<n*n/BLOCKSIZE+1,BLOCKSIZE>>> (gpu_a, gpu_b, n);
err=cudaDeviceSynchronize ();
chrono (STOP, &time);
printf ("Convolution took %f sec. on GPU\n", time);
cudaMemcpy (b, gpu_b, n*n*sizeof(float), cudaMemcpyDeviceToHost);
if (err != 0) {
printf ("%s\n", cudaGetErrorString (err));
exit (1);
}
cudaFree (gpu_a);
cudaFree (gpu_b);
} | #include <time.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define STOP 0
#define START 1
#define BLOCKSIZE 256
extern "C" void chrono (int kind, float *time);
__global__ void kconvol (float *gpu_a, float *gpu_b, int n) {
int i, j, l;
// TO DO : evaluate the global 1D index l of the current thread,
// using blockDim, blockIdx and threadIdx.
l = blockDim.x*blockIdx.x+threadIdx.x;
// TO DO : evaluate global indeces of thread (i,j) from the index l
j = l/n;
i = l%n;
if ((i >= n) || (j >= n)) return;
if ((i == 0) || (j == 0) || (i == n-1) || (j == n-1)) {
gpu_b[l] = gpu_a[l]; // edges are untouched
}
else
// TO DO : fill up the MISSING indices below
gpu_b[l]=(1./5.)*(gpu_a[l-n] + gpu_a[l-1] + gpu_a[l] + gpu_a[l+1]+ gpu_a[l+n]);
}
extern "C" void gpu_convol (float *a, float *b, int n) {
float *gpu_a;
float *gpu_b;
hipError_t err;
float time;
err = hipMalloc (&gpu_a, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_a: %s\n", hipGetErrorString (err));
exit (1);
}
err = hipMalloc (&gpu_b, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_b: %s\n", hipGetErrorString (err));
exit (1);
}
hipMemcpy (gpu_a, a, n*n*sizeof(float), hipMemcpyHostToDevice);
// NOTE : the chronometer below does not contemplate overhead of memory allocation and
// memory transfer.
chrono (START, &time);
// TO DO : the number of blocks is missing below in the kernel invocation
kconvol <<<n*n/BLOCKSIZE+1,BLOCKSIZE>>> (gpu_a, gpu_b, n);
err=hipDeviceSynchronize ();
chrono (STOP, &time);
printf ("Convolution took %f sec. on GPU\n", time);
hipMemcpy (b, gpu_b, n*n*sizeof(float), hipMemcpyDeviceToHost);
if (err != 0) {
printf ("%s\n", hipGetErrorString (err));
exit (1);
}
hipFree (gpu_a);
hipFree (gpu_b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <time.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define STOP 0
#define START 1
#define BLOCKSIZE 256
extern "C" void chrono (int kind, float *time);
__global__ void kconvol (float *gpu_a, float *gpu_b, int n) {
int i, j, l;
// TO DO : evaluate the global 1D index l of the current thread,
// using blockDim, blockIdx and threadIdx.
l = blockDim.x*blockIdx.x+threadIdx.x;
// TO DO : evaluate global indeces of thread (i,j) from the index l
j = l/n;
i = l%n;
if ((i >= n) || (j >= n)) return;
if ((i == 0) || (j == 0) || (i == n-1) || (j == n-1)) {
gpu_b[l] = gpu_a[l]; // edges are untouched
}
else
// TO DO : fill up the MISSING indices below
gpu_b[l]=(1./5.)*(gpu_a[l-n] + gpu_a[l-1] + gpu_a[l] + gpu_a[l+1]+ gpu_a[l+n]);
}
extern "C" void gpu_convol (float *a, float *b, int n) {
float *gpu_a;
float *gpu_b;
hipError_t err;
float time;
err = hipMalloc (&gpu_a, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_a: %s\n", hipGetErrorString (err));
exit (1);
}
err = hipMalloc (&gpu_b, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_b: %s\n", hipGetErrorString (err));
exit (1);
}
hipMemcpy (gpu_a, a, n*n*sizeof(float), hipMemcpyHostToDevice);
// NOTE : the chronometer below does not contemplate overhead of memory allocation and
// memory transfer.
chrono (START, &time);
// TO DO : the number of blocks is missing below in the kernel invocation
kconvol <<<n*n/BLOCKSIZE+1,BLOCKSIZE>>> (gpu_a, gpu_b, n);
err=hipDeviceSynchronize ();
chrono (STOP, &time);
printf ("Convolution took %f sec. on GPU\n", time);
hipMemcpy (b, gpu_b, n*n*sizeof(float), hipMemcpyDeviceToHost);
if (err != 0) {
printf ("%s\n", hipGetErrorString (err));
exit (1);
}
hipFree (gpu_a);
hipFree (gpu_b);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kconvolPfS_i
.globl _Z7kconvolPfS_i
.p2align 8
.type _Z7kconvolPfS_i,@function
_Z7kconvolPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s5, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s5
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_max_i32_e32 v0, -1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v0, v2, s3
s_load_b64 s[4:5], s[0:1], 0x0
v_cmp_eq_u32_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s2, vcc_lo
s_xor_b32 s2, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB0_5
s_add_i32 s2, s3, -1
s_mov_b32 s8, -1
v_cmp_ne_u32_e32 vcc_lo, s2, v3
v_cmp_ne_u32_e64 s2, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, s2, vcc_lo
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v3, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, 0x3fc99999
s_mov_b32 s8, 0x9999999a
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off
global_load_b32 v7, v[8:9], off offset:-4
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v7 :: v_dual_add_nc_u32 v5, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 2, v[5:6]
global_load_b64 v[5:6], v[8:9], off
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[3:4], v0
v_mul_f64 v[3:4], v[3:4], s[8:9]
s_xor_b32 s8, exec_lo, -1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[3:4]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s6, exec_lo
s_and_b32 s3, s8, exec_lo
s_or_b32 s6, s2, s3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kconvolPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kconvolPfS_i, .Lfunc_end0-_Z7kconvolPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kconvolPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kconvolPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <time.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define STOP 0
#define START 1
#define BLOCKSIZE 256
extern "C" void chrono (int kind, float *time);
__global__ void kconvol (float *gpu_a, float *gpu_b, int n) {
int i, j, l;
// TO DO : evaluate the global 1D index l of the current thread,
// using blockDim, blockIdx and threadIdx.
l = blockDim.x*blockIdx.x+threadIdx.x;
// TO DO : evaluate global indeces of thread (i,j) from the index l
j = l/n;
i = l%n;
if ((i >= n) || (j >= n)) return;
if ((i == 0) || (j == 0) || (i == n-1) || (j == n-1)) {
gpu_b[l] = gpu_a[l]; // edges are untouched
}
else
// TO DO : fill up the MISSING indices below
gpu_b[l]=(1./5.)*(gpu_a[l-n] + gpu_a[l-1] + gpu_a[l] + gpu_a[l+1]+ gpu_a[l+n]);
}
extern "C" void gpu_convol (float *a, float *b, int n) {
float *gpu_a;
float *gpu_b;
hipError_t err;
float time;
err = hipMalloc (&gpu_a, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_a: %s\n", hipGetErrorString (err));
exit (1);
}
err = hipMalloc (&gpu_b, n*n*sizeof(float));
if (err != 0) {
printf ("Error allocating gpu_b: %s\n", hipGetErrorString (err));
exit (1);
}
hipMemcpy (gpu_a, a, n*n*sizeof(float), hipMemcpyHostToDevice);
// NOTE : the chronometer below does not contemplate overhead of memory allocation and
// memory transfer.
chrono (START, &time);
// TO DO : the number of blocks is missing below in the kernel invocation
kconvol <<<n*n/BLOCKSIZE+1,BLOCKSIZE>>> (gpu_a, gpu_b, n);
err=hipDeviceSynchronize ();
chrono (STOP, &time);
printf ("Convolution took %f sec. on GPU\n", time);
hipMemcpy (b, gpu_b, n*n*sizeof(float), hipMemcpyDeviceToHost);
if (err != 0) {
printf ("%s\n", hipGetErrorString (err));
exit (1);
}
hipFree (gpu_a);
hipFree (gpu_b);
} | .text
.file "convol.hip"
.globl _Z22__device_stub__kconvolPfS_i # -- Begin function _Z22__device_stub__kconvolPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kconvolPfS_i,@function
_Z22__device_stub__kconvolPfS_i: # @_Z22__device_stub__kconvolPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kconvolPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kconvolPfS_i, .Lfunc_end0-_Z22__device_stub__kconvolPfS_i
.cfi_endproc
# -- End function
.globl gpu_convol # -- Begin function gpu_convol
.p2align 4, 0x90
.type gpu_convol,@function
gpu_convol: # @gpu_convol
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
movl %edx, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 4(%rsp), %rsi
movl $1, %edi
callq chrono
shrl $8, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%r12), %rdi
incq %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kconvolPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
movl %eax, %ebp
leaq 4(%rsp), %rsi
xorl %edi, %edi
callq chrono
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebp, %ebp
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
.LBB1_2:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_9:
movl %ebp, %edi
callq hipGetErrorString
movq %rax, %rdi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size gpu_convol, .Lfunc_end1-gpu_convol
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kconvolPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kconvolPfS_i,@object # @_Z7kconvolPfS_i
.section .rodata,"a",@progbits
.globl _Z7kconvolPfS_i
.p2align 3, 0x0
_Z7kconvolPfS_i:
.quad _Z22__device_stub__kconvolPfS_i
.size _Z7kconvolPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating gpu_a: %s\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating gpu_b: %s\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Convolution took %f sec. on GPU\n"
.size .L.str.2, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kconvolPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kconvolPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kconvolPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kconvolPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fe200078e0204 */
/*0110*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fc800078e3cff */
/*0120*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe40003f44070 */
/*0130*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f06270 */
/*0140*/ LOP3.LUT R4, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff047a12 */
/* 0x000fd200078e33ff */
/*0150*/ @!P2 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a07 */
/*0160*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fc80007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc60003f25270 */
/*01a0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fca00078e0a03 */
/*01b0*/ SEL R5, R4, R3, !P1 ; /* 0x0000000304057207 */
/* 0x000fc80004800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06270 */
/*01d0*/ ISETP.GT.OR P0, PT, RZ, c[0x0][0x170], P0 ; /* 0x00005c00ff007a0c */
/* 0x000fda0000704670 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0200*/ IMAD.IADD R3, R2, 0x1, -R7 ; /* 0x0000000102037824 */
/* 0x000fe200078e0a07 */
/*0210*/ ISETP.GT.U32.AND P0, PT, R7, R2.reuse, PT ; /* 0x000000020700720c */
/* 0x080fe20003f04070 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x000fe200078e00ff */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0240*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0250*/ SEL R3, R3, R2, !P0 ; /* 0x0000000203037207 */
/* 0x000fe40004000000 */
/*0260*/ IADD3 R2, R9, -0x1, RZ ; /* 0xffffffff09027810 */
/* 0x000fca0007ffe0ff */
/*0270*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*0280*/ SEL R3, R4, R3, !P1 ; /* 0x0000000304037207 */
/* 0x000fc80004800000 */
/*0290*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05270 */
/*02a0*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fc80004702670 */
/*02b0*/ ISETP.EQ.OR P0, PT, R3, R2, P0 ; /* 0x000000020300720c */
/* 0x000fc80000702670 */
/*02c0*/ ISETP.EQ.OR P0, PT, R5, R2, P0 ; /* 0x000000020500720c */
/* 0x000fe20000702670 */
/*02d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*02e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0207 */
/*02f0*/ @P0 BRA 0x410 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R6, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000067a10 */
/* 0x000fe20007ffe0ff */
/*0310*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea8000c1e1900 */
/*0320*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0330*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ee6000c1e1900 */
/*0340*/ IMAD.WIDE R8, R9, 0x4, R4 ; /* 0x0000000409087825 */
/* 0x000fe200078e0204 */
/*0350*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000f28000c1e1900 */
/*0360*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*0370*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f62000c1e1900 */
/*0380*/ FADD R0, R0, R7 ; /* 0x0000000700007221 */
/* 0x008fc80000000000 */
/*0390*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x004fc80000000000 */
/*03a0*/ FADD R0, R0, R13 ; /* 0x0000000d00007221 */
/* 0x010fc80000000000 */
/*03b0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x020fc80000000000 */
/*03c0*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x000e240000201800 */
/*03d0*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*03e0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*03f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x001fe2000c101904 */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0420*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kconvolPfS_i
.globl _Z7kconvolPfS_i
.p2align 8
.type _Z7kconvolPfS_i,@function
_Z7kconvolPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s5, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s5
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_max_i32_e32 v0, -1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v0, v2, s3
s_load_b64 s[4:5], s[0:1], 0x0
v_cmp_eq_u32_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s2, vcc_lo
s_xor_b32 s2, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB0_5
s_add_i32 s2, s3, -1
s_mov_b32 s8, -1
v_cmp_ne_u32_e32 vcc_lo, s2, v3
v_cmp_ne_u32_e64 s2, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, s2, vcc_lo
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v3, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, 0x3fc99999
s_mov_b32 s8, 0x9999999a
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[3:4], off
global_load_b32 v7, v[8:9], off offset:-4
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v7 :: v_dual_add_nc_u32 v5, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 2, v[5:6]
global_load_b64 v[5:6], v[8:9], off
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[3:4], v0
v_mul_f64 v[3:4], v[3:4], s[8:9]
s_xor_b32 s8, exec_lo, -1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[3:4]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s6, exec_lo
s_and_b32 s3, s8, exec_lo
s_or_b32 s6, s2, s3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s2, s6
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kconvolPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kconvolPfS_i, .Lfunc_end0-_Z7kconvolPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kconvolPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kconvolPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d8ed6_00000000-6_convol.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7kconvolPfS_iPfS_i
.type _Z29__device_stub__Z7kconvolPfS_iPfS_i, @function
_Z29__device_stub__Z7kconvolPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7kconvolPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7kconvolPfS_iPfS_i, .-_Z29__device_stub__Z7kconvolPfS_iPfS_i
.globl _Z7kconvolPfS_i
.type _Z7kconvolPfS_i, @function
_Z7kconvolPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7kconvolPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7kconvolPfS_i, .-_Z7kconvolPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating gpu_a: %s\n"
.LC1:
.string "Error allocating gpu_b: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Convolution took %f sec. on GPU\n"
.section .rodata.str1.1
.LC3:
.string "%s\n"
.text
.globl gpu_convol
.type gpu_convol, @function
gpu_convol:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r12
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edx, %r13d
imull %edx, %r13d
movslq %r13d, %rbx
salq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L18
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L19
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %edi
call chrono@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
leal 255(%r13), %eax
testl %r13d, %r13d
cmovns %r13d, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L14:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
leaq 12(%rsp), %rsi
movl $0, %edi
call chrono@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebp, %ebp
jne .L21
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
movl %ebp, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z7kconvolPfS_iPfS_i
jmp .L14
.L21:
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size gpu_convol, .-gpu_convol
.section .rodata.str1.1
.LC4:
.string "_Z7kconvolPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kconvolPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convol.hip"
.globl _Z22__device_stub__kconvolPfS_i # -- Begin function _Z22__device_stub__kconvolPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__kconvolPfS_i,@function
_Z22__device_stub__kconvolPfS_i: # @_Z22__device_stub__kconvolPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7kconvolPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__kconvolPfS_i, .Lfunc_end0-_Z22__device_stub__kconvolPfS_i
.cfi_endproc
# -- End function
.globl gpu_convol # -- Begin function gpu_convol
.p2align 4, 0x90
.type gpu_convol,@function
gpu_convol: # @gpu_convol
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
movl %edx, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 4(%rsp), %rsi
movl $1, %edi
callq chrono
shrl $8, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%r12), %rdi
incq %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kconvolPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
movl %eax, %ebp
leaq 4(%rsp), %rsi
xorl %edi, %edi
callq chrono
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %ebp, %ebp
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
jmp .LBB1_2
.LBB1_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
.LBB1_2:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_9:
movl %ebp, %edi
callq hipGetErrorString
movq %rax, %rdi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size gpu_convol, .Lfunc_end1-gpu_convol
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kconvolPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kconvolPfS_i,@object # @_Z7kconvolPfS_i
.section .rodata,"a",@progbits
.globl _Z7kconvolPfS_i
.p2align 3, 0x0
_Z7kconvolPfS_i:
.quad _Z22__device_stub__kconvolPfS_i
.size _Z7kconvolPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating gpu_a: %s\n"
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating gpu_b: %s\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Convolution took %f sec. on GPU\n"
.size .L.str.2, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kconvolPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kconvolPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kconvolPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void warp_kernel(float* out, const float* in, const int* index,const float* weights,const int npixels,const int nchannels){
int pixel = blockIdx.x * blockDim.x + threadIdx.x;
int channel = blockIdx.y * blockDim.y + threadIdx.y;
if( channel >= nchannels||pixel >= npixels)
return;
out[nchannels*pixel+channel]=in[nchannels*index[4*pixel]+channel]*weights[4*pixel]
+in[nchannels*index[4*pixel+1]+channel]*weights[4*pixel+1]
+in[nchannels*index[4*pixel+2]+channel]*weights[4*pixel+2]
+in[nchannels*index[4*pixel+3]+channel]*weights[4*pixel+3];
} | code for sm_80
Function : _Z11warp_kernelPfPKfPKiS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x180], P0 ; /* 0x0000600005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.L.U32 R3, R5, 0x2, RZ ; /* 0x0000000205037819 */
/* 0x000fe200000006ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R6, R3, R0, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fca00078e0200 */
/*00e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000404060b7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R13, [R6.64+0x8] ; /* 0x00000804060d7981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000f62000c1e1900 */
/*0120*/ IMAD.WIDE R2, R3, R0, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0200 */
/*0130*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000f62000c1e1900 */
/*0160*/ IMAD R11, R11, c[0x0][0x184], R4.reuse ; /* 0x000061000b0b7a24 */
/* 0x104fe400078e0204 */
/*0170*/ IMAD R9, R9, c[0x0][0x184], R4 ; /* 0x0000610009097a24 */
/* 0x008fc400078e0204 */
/*0180*/ IMAD.WIDE R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc800078e0200 */
/*0190*/ IMAD R13, R13, c[0x0][0x184], R4.reuse ; /* 0x000061000d0d7a24 */
/* 0x110fe400078e0204 */
/*01a0*/ IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0200 */
/*01b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea6000c1e1900 */
/*01c0*/ IMAD.WIDE R12, R13, R0, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe400078e0200 */
/*01d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee4000c1e1900 */
/*01e0*/ IMAD R7, R17, c[0x0][0x184], R4 ; /* 0x0000610011077a24 */
/* 0x020fc400078e0204 */
/*01f0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*0200*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe400078e0200 */
/*0210*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD R5, R5, c[0x0][0x184], R4 ; /* 0x0000610005057a24 */
/* 0x000fc800078e0204 */
/*0240*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0200 */
/*0250*/ FMUL R10, R15, R10 ; /* 0x0000000a0f0a7220 */
/* 0x004fc80000400000 */
/*0260*/ FFMA R10, R14, R9, R10 ; /* 0x000000090e0a7223 */
/* 0x008fc8000000000a */
/*0270*/ FFMA R10, R17, R12, R10 ; /* 0x0000000c110a7223 */
/* 0x010fc8000000000a */
/*0280*/ FFMA R19, R19, R6, R10 ; /* 0x0000000613137223 */
/* 0x020fca000000000a */
/*0290*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void warp_kernel(float* out, const float* in, const int* index,const float* weights,const int npixels,const int nchannels){
int pixel = blockIdx.x * blockDim.x + threadIdx.x;
int channel = blockIdx.y * blockDim.y + threadIdx.y;
if( channel >= nchannels||pixel >= npixels)
return;
out[nchannels*pixel+channel]=in[nchannels*index[4*pixel]+channel]*weights[4*pixel]
+in[nchannels*index[4*pixel+1]+channel]*weights[4*pixel+1]
+in[nchannels*index[4*pixel+2]+channel]*weights[4*pixel+2]
+in[nchannels*index[4*pixel+3]+channel]*weights[4*pixel+3];
} | .file "tmpxft_000b4f0d_00000000-6_warp_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii
.type _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii, @function
_Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11warp_kernelPfPKfPKiS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii, .-_Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii
.globl _Z11warp_kernelPfPKfPKiS1_ii
.type _Z11warp_kernelPfPKfPKiS1_ii, @function
_Z11warp_kernelPfPKfPKiS1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11warp_kernelPfPKfPKiS1_ii, .-_Z11warp_kernelPfPKfPKiS1_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11warp_kernelPfPKfPKiS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11warp_kernelPfPKfPKiS1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void warp_kernel(float* out, const float* in, const int* index,const float* weights,const int npixels,const int nchannels){
int pixel = blockIdx.x * blockDim.x + threadIdx.x;
int channel = blockIdx.y * blockDim.y + threadIdx.y;
if( channel >= nchannels||pixel >= npixels)
return;
out[nchannels*pixel+channel]=in[nchannels*index[4*pixel]+channel]*weights[4*pixel]
+in[nchannels*index[4*pixel+1]+channel]*weights[4*pixel+1]
+in[nchannels*index[4*pixel+2]+channel]*weights[4*pixel+2]
+in[nchannels*index[4*pixel+3]+channel]*weights[4*pixel+3];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void warp_kernel(float* out, const float* in, const int* index,const float* weights,const int npixels,const int nchannels){
int pixel = blockIdx.x * blockDim.x + threadIdx.x;
int channel = blockIdx.y * blockDim.y + threadIdx.y;
if( channel >= nchannels||pixel >= npixels)
return;
out[nchannels*pixel+channel]=in[nchannels*index[4*pixel]+channel]*weights[4*pixel]
+in[nchannels*index[4*pixel+1]+channel]*weights[4*pixel+1]
+in[nchannels*index[4*pixel+2]+channel]*weights[4*pixel+2]
+in[nchannels*index[4*pixel+3]+channel]*weights[4*pixel+3];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void warp_kernel(float* out, const float* in, const int* index,const float* weights,const int npixels,const int nchannels){
int pixel = blockIdx.x * blockDim.x + threadIdx.x;
int channel = blockIdx.y * blockDim.y + threadIdx.y;
if( channel >= nchannels||pixel >= npixels)
return;
out[nchannels*pixel+channel]=in[nchannels*index[4*pixel]+channel]*weights[4*pixel]
+in[nchannels*index[4*pixel+1]+channel]*weights[4*pixel+1]
+in[nchannels*index[4*pixel+2]+channel]*weights[4*pixel+2]
+in[nchannels*index[4*pixel+3]+channel]*weights[4*pixel+3];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11warp_kernelPfPKfPKiS1_ii
.globl _Z11warp_kernelPfPKfPKiS1_ii
.p2align 8
.type _Z11warp_kernelPfPKfPKiS1_ii,@function
_Z11warp_kernelPfPKfPKiS1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s9, v0
v_cmp_gt_i32_e64 s2, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_or_b32_e32 v6, 2, v2
v_or_b32_e32 v8, 3, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v14, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v7, vcc_lo
global_load_b32 v16, v[10:11], off
v_add_co_u32 v10, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
s_clause 0x2
global_load_b32 v17, v[12:13], off
global_load_b32 v18, v[14:15], off
global_load_b32 v19, v[10:11], off
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_waitcnt vmcnt(3)
v_mad_u64_u32 v[10:11], null, v16, s9, v[0:1]
s_waitcnt vmcnt(2)
v_mad_u64_u32 v[12:13], null, v17, s9, v[0:1]
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[14:15], null, v18, s9, v[0:1]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[16:17], null, v19, s9, v[0:1]
s_clause 0x1
global_load_b32 v18, v[2:3], off
global_load_b32 v19, v[4:5], off
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[12:13]
v_lshlrev_b64 v[4:5], 2, v[10:11]
global_load_b32 v12, v[6:7], off
v_lshlrev_b64 v[6:7], 2, v[14:15]
v_lshlrev_b64 v[10:11], 2, v[16:17]
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v13, v[2:3], off
v_add_co_u32 v2, vcc_lo, s2, v6
global_load_b32 v6, v[4:5], off
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v11, vcc_lo
global_load_b32 v7, v[2:3], off
global_load_b32 v8, v[8:9], off
global_load_b32 v4, v[4:5], off
v_mad_u64_u32 v[2:3], null, v1, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(4)
v_mul_f32_e32 v5, v13, v19
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v18
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v5, v7, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v8
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11warp_kernelPfPKfPKiS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11warp_kernelPfPKfPKiS1_ii, .Lfunc_end0-_Z11warp_kernelPfPKfPKiS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11warp_kernelPfPKfPKiS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11warp_kernelPfPKfPKiS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void warp_kernel(float* out, const float* in, const int* index,const float* weights,const int npixels,const int nchannels){
int pixel = blockIdx.x * blockDim.x + threadIdx.x;
int channel = blockIdx.y * blockDim.y + threadIdx.y;
if( channel >= nchannels||pixel >= npixels)
return;
out[nchannels*pixel+channel]=in[nchannels*index[4*pixel]+channel]*weights[4*pixel]
+in[nchannels*index[4*pixel+1]+channel]*weights[4*pixel+1]
+in[nchannels*index[4*pixel+2]+channel]*weights[4*pixel+2]
+in[nchannels*index[4*pixel+3]+channel]*weights[4*pixel+3];
} | .text
.file "warp_kernel.hip"
.globl _Z26__device_stub__warp_kernelPfPKfPKiS1_ii # -- Begin function _Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.p2align 4, 0x90
.type _Z26__device_stub__warp_kernelPfPKfPKiS1_ii,@function
_Z26__device_stub__warp_kernelPfPKfPKiS1_ii: # @_Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11warp_kernelPfPKfPKiS1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__warp_kernelPfPKfPKiS1_ii, .Lfunc_end0-_Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11warp_kernelPfPKfPKiS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11warp_kernelPfPKfPKiS1_ii,@object # @_Z11warp_kernelPfPKfPKiS1_ii
.section .rodata,"a",@progbits
.globl _Z11warp_kernelPfPKfPKiS1_ii
.p2align 3, 0x0
_Z11warp_kernelPfPKfPKiS1_ii:
.quad _Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.size _Z11warp_kernelPfPKfPKiS1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11warp_kernelPfPKfPKiS1_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11warp_kernelPfPKfPKiS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11warp_kernelPfPKfPKiS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x180], P0 ; /* 0x0000600005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00b0*/ SHF.L.U32 R3, R5, 0x2, RZ ; /* 0x0000000205037819 */
/* 0x000fe200000006ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R6, R3, R0, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fca00078e0200 */
/*00e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000404060b7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R13, [R6.64+0x8] ; /* 0x00000804060d7981 */
/* 0x000f28000c1e1900 */
/*0110*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x000f62000c1e1900 */
/*0120*/ IMAD.WIDE R2, R3, R0, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fca00078e0200 */
/*0130*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000f68000c1e1900 */
/*0140*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000f68000c1e1900 */
/*0150*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000f62000c1e1900 */
/*0160*/ IMAD R11, R11, c[0x0][0x184], R4.reuse ; /* 0x000061000b0b7a24 */
/* 0x104fe400078e0204 */
/*0170*/ IMAD R9, R9, c[0x0][0x184], R4 ; /* 0x0000610009097a24 */
/* 0x008fc400078e0204 */
/*0180*/ IMAD.WIDE R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc800078e0200 */
/*0190*/ IMAD R13, R13, c[0x0][0x184], R4.reuse ; /* 0x000061000d0d7a24 */
/* 0x110fe400078e0204 */
/*01a0*/ IMAD.WIDE R8, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x080fe200078e0200 */
/*01b0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea6000c1e1900 */
/*01c0*/ IMAD.WIDE R12, R13, R0, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe400078e0200 */
/*01d0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee4000c1e1900 */
/*01e0*/ IMAD R7, R17, c[0x0][0x184], R4 ; /* 0x0000610011077a24 */
/* 0x020fc400078e0204 */
/*01f0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f24000c1e1900 */
/*0200*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe400078e0200 */
/*0210*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD R5, R5, c[0x0][0x184], R4 ; /* 0x0000610005057a24 */
/* 0x000fc800078e0204 */
/*0240*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0200 */
/*0250*/ FMUL R10, R15, R10 ; /* 0x0000000a0f0a7220 */
/* 0x004fc80000400000 */
/*0260*/ FFMA R10, R14, R9, R10 ; /* 0x000000090e0a7223 */
/* 0x008fc8000000000a */
/*0270*/ FFMA R10, R17, R12, R10 ; /* 0x0000000c110a7223 */
/* 0x010fc8000000000a */
/*0280*/ FFMA R19, R19, R6, R10 ; /* 0x0000000613137223 */
/* 0x020fca000000000a */
/*0290*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11warp_kernelPfPKfPKiS1_ii
.globl _Z11warp_kernelPfPKfPKiS1_ii
.p2align 8
.type _Z11warp_kernelPfPKfPKiS1_ii,@function
_Z11warp_kernelPfPKfPKiS1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s9, v0
v_cmp_gt_i32_e64 s2, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
v_or_b32_e32 v6, 2, v2
v_or_b32_e32 v8, 3, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v14, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v7, vcc_lo
global_load_b32 v16, v[10:11], off
v_add_co_u32 v10, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
s_clause 0x2
global_load_b32 v17, v[12:13], off
global_load_b32 v18, v[14:15], off
global_load_b32 v19, v[10:11], off
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_waitcnt vmcnt(3)
v_mad_u64_u32 v[10:11], null, v16, s9, v[0:1]
s_waitcnt vmcnt(2)
v_mad_u64_u32 v[12:13], null, v17, s9, v[0:1]
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[14:15], null, v18, s9, v[0:1]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[16:17], null, v19, s9, v[0:1]
s_clause 0x1
global_load_b32 v18, v[2:3], off
global_load_b32 v19, v[4:5], off
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[12:13]
v_lshlrev_b64 v[4:5], 2, v[10:11]
global_load_b32 v12, v[6:7], off
v_lshlrev_b64 v[6:7], 2, v[14:15]
v_lshlrev_b64 v[10:11], 2, v[16:17]
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v13, v[2:3], off
v_add_co_u32 v2, vcc_lo, s2, v6
global_load_b32 v6, v[4:5], off
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v11, vcc_lo
global_load_b32 v7, v[2:3], off
global_load_b32 v8, v[8:9], off
global_load_b32 v4, v[4:5], off
v_mad_u64_u32 v[2:3], null, v1, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(4)
v_mul_f32_e32 v5, v13, v19
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v18
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v5, v7, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v8
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11warp_kernelPfPKfPKiS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11warp_kernelPfPKfPKiS1_ii, .Lfunc_end0-_Z11warp_kernelPfPKfPKiS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11warp_kernelPfPKfPKiS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11warp_kernelPfPKfPKiS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b4f0d_00000000-6_warp_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii
.type _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii, @function
_Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11warp_kernelPfPKfPKiS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii, .-_Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii
.globl _Z11warp_kernelPfPKfPKiS1_ii
.type _Z11warp_kernelPfPKfPKiS1_ii, @function
_Z11warp_kernelPfPKfPKiS1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z11warp_kernelPfPKfPKiS1_iiPfPKfPKiS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11warp_kernelPfPKfPKiS1_ii, .-_Z11warp_kernelPfPKfPKiS1_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11warp_kernelPfPKfPKiS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11warp_kernelPfPKfPKiS1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "warp_kernel.hip"
.globl _Z26__device_stub__warp_kernelPfPKfPKiS1_ii # -- Begin function _Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.p2align 4, 0x90
.type _Z26__device_stub__warp_kernelPfPKfPKiS1_ii,@function
_Z26__device_stub__warp_kernelPfPKfPKiS1_ii: # @_Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11warp_kernelPfPKfPKiS1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__warp_kernelPfPKfPKiS1_ii, .Lfunc_end0-_Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11warp_kernelPfPKfPKiS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11warp_kernelPfPKfPKiS1_ii,@object # @_Z11warp_kernelPfPKfPKiS1_ii
.section .rodata,"a",@progbits
.globl _Z11warp_kernelPfPKfPKiS1_ii
.p2align 3, 0x0
_Z11warp_kernelPfPKfPKiS1_ii:
.quad _Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.size _Z11warp_kernelPfPKfPKiS1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11warp_kernelPfPKfPKiS1_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__warp_kernelPfPKfPKiS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11warp_kernelPfPKfPKiS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand.h>
#include <curand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Plot_kernel(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * blockDim.x * gridDim.x;
unsigned char* f_r, *f_g, *f_b;
f_r = (unsigned char*)((char*)R_input + y*i_size);
f_g = (unsigned char*)((char*)G_input + y*i_size);
f_b = (unsigned char*)((char*)B_input + y*i_size);
ptr[offset].x = f_r[x];
ptr[offset].y = f_g[x];
ptr[offset].z = f_b[x];
ptr[offset].w = 255;
}
__device__ int log2(int N)
{
int k = N, i = 0;
while(k)
{
k >>= 1;
i++;
}
return i - 1;
}
__device__ int reverse(int N, int n)
{
int p = 0;
for(int j = 1; j <= log2(N); j++)
{
if(n & (1 << (log2(N) - j)))
p |= 1 << (j - 1);
}
return p;
}
__device__ void ordina_x(float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,int row, int col, int x)
{
int N = row, a;
for(int i = 0; i < N; i++)
{
a = reverse((int)N, i);
real_d_out[i*col + x] = complex_r[a*col + x];
imagi_d_out[i*col + x] = complex_i[a*col + x];}
for(int j = 0; j < N; j++)
{
complex_r[j*col + x] = real_d_out[j*col + x];
complex_i[j*col + x] = imagi_d_out[j*col + x];}
}
__device__ void ordina_y(float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,int row, int col, int y)
{
int N = row, a;
for(int i = 0; i < N; i++)
{
a = reverse((int)N, i);
real_d_out[y*col + i] = complex_r[y*col + a];
imagi_d_out[y*col + i] = complex_i[y*col + a];
}
for(int j = 0; j < N; j++)
{
complex_r[y*col + j] = real_d_out[y*col + j];
complex_i[y*col + j] = imagi_d_out[y*col + j];
}
}
__device__ void Func_FFT_X(float *complex_r, float *complex_i,int row, int col, int x)
{
int n = 1, N = row;
int a = N/2;
float temp_real, temp_imagi;
float t_r, t_i, a_r, a_i;
for(int j = 0; j < log2(N); j++)
{
for (int i = 0; i < N; i++)
{
if(!(i & n))
{
temp_real = complex_r[x + (i * col)];
temp_imagi = complex_i[x + (i * col)];
a_r = cos((-2) * ((i * a) % (n * a)) * PI / N);
a_i = sin((-2) * ((i * a) % (n * a)) * PI / N);
t_r = (a_r*complex_r[x + (i + n)*col]) - (a_i*complex_i[x + (i + n)*col]);
t_i = (a_i*complex_r[x + (i + n)*col]) + (a_r*complex_i[x + (i + n)*col]);
complex_r[x + (i * col)] += t_r;
complex_i[x + (i * col)] += t_i;
complex_r[x + (i + n)*col] = temp_real - t_r;
complex_i[x + (i + n)*col] = temp_imagi - t_i;
}
}
n *= 2;
a = a/2;
}
}
__device__ void Func_FFT_Y(float *complex_r, float *complex_i,int row, int col, int y)
{
int n = 1, N = col;
int a = N/2;
float temp_real, temp_imagi;
float t_r, t_i, a_r, a_i;
for(int j = 0; j < log2(N); j++)
{
for (int i = 0; i < N; i++)
{
if(!(i & n))
{
temp_real = complex_r[i + (y * col)];
temp_imagi = complex_i[i + (y * col)];
a_r = cos(-2 * ((i * a) % (n * a)) * PI/ N);
a_i = sin(-2 * ((i * a) % (n * a)) * PI/ N);
t_r = (a_r*complex_r[(i + n) + y*col]) - (a_i*complex_i[(i + n) + y*col]);
t_i = (a_i*complex_r[(i + n) + y*col]) + (a_r*complex_i[(i + n) + y*col]);
complex_r[i + (y * col)] += t_r;
complex_i[i + (y * col)] += t_i;
complex_r[(i + n) + y*col] = temp_real - t_r;
complex_i[(i + n) + y*col] = temp_imagi - t_i;
}
}
n *= 2;
a = a/2;
}
}
__global__ void FFT_X(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned long colF, unsigned long rowF )
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
float temp;
if(x < col)
{
for (int i = 0; i < row; i++)
{
complex_r[x + (i * colF)] = 0.2989 * R_input[x + (i * i_size)] + 0.587 * G_input[x + (i * i_size)] + 0.1140 * B_input[x + (i * i_size)];
complex_i[x + (i * colF)] = 0;
}
for (int i = row; i < rowF; i++)
{
complex_r[x + (i * colF)] = 0;
complex_i[x + (i * colF)] = 0;
}
}
else
{
for (int i = 0; i < rowF; i++)
{
complex_r[x + (i * colF)] = 0;
complex_i[x + (i * colF)] = 0;
}
}
ordina_x(complex_r, complex_i, real_d_out, imagi_d_out, rowF, colF, x);
Func_FFT_X(complex_r, complex_i, rowF, colF, x);
for (int i = 0; i < rowF/2; i++)
{
temp = complex_r[x + (i * colF)];
complex_r[x + (i * colF)] = complex_r[x + ((i + rowF/2) * colF)];
complex_r[x + ((i + rowF/2) * colF)] = temp;
temp = complex_i[x + (i * colF)];
complex_i[x + (i * colF)] = complex_i[x + ((i + rowF/2) * colF)];
complex_i[x + ((i + rowF/2) * colF)] = temp;
}
}
__global__ void FFT_Y(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned long colF, unsigned long rowF )
{
int y = threadIdx.x + (blockIdx.x * blockDim.x);
float temp;
ordina_y(complex_r, complex_i, real_d_out, imagi_d_out, rowF, colF, y);
Func_FFT_Y(complex_r, complex_i, rowF, colF, y);
for (int i = 0; i < colF/2; i++)
{
temp = complex_r[i + (y * colF)];
complex_r[i + (y * colF)] = complex_r[(i + colF/2) + (y * colF)];
complex_r[(i + colF/2) + (y * colF)] = temp;
temp = complex_i[i + (y * colF)];
complex_i[i + (y * colF)] = complex_i[(i + colF/2) + (y * colF)];
complex_i[(i + colF/2) + (y * colF)] = temp;
}
unsigned char v;
int a = (colF/2) - (col/2);
int temp_b = (rowF/2) - (row/2);
if( y >= temp_b)
for (int i = a; i < (colF/2) + (col/2); i++)
{
v = (unsigned char)(20*log10(sqrt((complex_r[i + (y * colF)]*complex_r[i + (y * colF)]) + (complex_i[i + (y * colF)]*complex_i[i + (y * colF)]))));
r_dataC[(i - a ) + (y - temp_b) * i_size] = v;
g_dataC[(i - a) + (y - temp_b) * i_size] = v;
b_dataC[(i - a) + (y - temp_b) * i_size] = v;
}
}
__global__ void erosion(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,float *mask, unsigned int dim, int m)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c = 0;
unsigned char color;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++)
{
ximg = x + i;
for (int j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
c += (R_input[offset2]*mask[k]);
k++;
}
}
if(c < m) color = 0;
else color = 255;
r_dataC[offset] = color;
g_dataC[offset] = color;
b_dataC[offset] = color;
}
__global__ void histogramGray(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned int *hist)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset];
G_input[offset] = R_input[offset];
B_input[offset] = R_input[offset];
atomicAdd( &(hist[R_input[offset]]), 1);
}
__global__ void binary(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,int um)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
unsigned char c;
if (R_input[offset] > um) c = 255;
else c = 0;
R_input[offset] = c;
G_input[offset] = c;
B_input[offset] = c;
}
__global__ void Copy(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *R_output, unsigned char *G_output,unsigned char *B_output)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned int dim)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++)
{
ximg = x + i;
for (j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
{
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;
}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i])
{
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i])
{
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i])
{
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;
}
if(n%2 == 1)
{
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}
else
{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,float *mask, unsigned int dim)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++)
{
ximg = x + i;
for (int j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
{
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];
}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Get_Histogram(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned int *hist_r,unsigned int *hist_g,unsigned int *hist_b)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
atomicAdd( &(hist_r[R_input[offset]]), 1);
atomicAdd( &(hist_g[G_input[offset]]), 1);
atomicAdd( &(hist_b[B_input[offset]]), 1);
}
__global__ void Equalization_GPU(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataE, unsigned char *g_dataE,unsigned char *b_dataE,unsigned int *hist_r,unsigned int *hist_g,unsigned int *hist_b)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
r_dataE[offset] = hist_r[R_input[offset]];
g_dataE[offset] = hist_g[G_input[offset]];
b_dataE[offset] = hist_b[B_input[offset]];
}
__global__ void Rotation_op(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size, float a,unsigned long col, unsigned long row)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * blockDim.x * gridDim.x;
x = x - (blockDim.x * gridDim.x / 2);
y = y - (blockDim.y * gridDim.y / 2);
unsigned char* f_r, *f_g, *f_b;
int ximg = (x*cos(a) + y*sin(a)) + (col/2), yimg = (y*cos(a) - x*sin(a)) + (row/2);
if (ximg < col && yimg < row)
{
f_r = (unsigned char*)((char*)R_input + yimg*i_size);
f_g = (unsigned char*)((char*)G_input + yimg*i_size);
f_b = (unsigned char*)((char*)B_input + yimg*i_size);
ptr[offset].x = f_r[ximg];
ptr[offset].y = f_g[ximg];
ptr[offset].z = f_b[ximg];
ptr[offset].w = 255;
}
else
{
ptr[offset].x = 0;
ptr[offset].y = 0;
ptr[offset].z = 0;
ptr[offset].w = 255;
}
}
__global__ void Scaling_op(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input,unsigned char *R_output, unsigned char *G_output,unsigned char *B_output,size_t i_size, size_t pitch2, float s,unsigned long col, unsigned long row)
{
float x = threadIdx.x + (blockIdx.x * blockDim.x);
float y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * pitch2;
x = x - (DIM / 2);
y = y - (DIM / 2);
unsigned char* f_r, *f_g, *f_b;
x /= s; y /= s;
int ximg = x + (col/2), yimg = y + (row/2);
if (ximg < (col - 1) && yimg < (row - 1))
{
f_r = (unsigned char*)((char*)R_input + yimg*i_size);
f_g = (unsigned char*)((char*)G_input + yimg*i_size);
f_b = (unsigned char*)((char*)B_input + yimg*i_size);
float cx = x - floor(x);
float cy = y - floor(y);
float R1 = f_r[ximg]*(1 - cx) + f_r[ximg + 1]*(cx);
float R2 = f_r[ximg + i_size]*(1 - cx) + f_r[ximg + 1 + i_size]*(cx);
R_output[offset] = R1*(1 - cy) + R2*(cy);
R1 = f_g[ximg]*(1 - cx) + f_g[ximg + 1]*(cx);
R2 = f_g[ximg + i_size]*(1 - cx) + f_g[ximg + 1 + i_size]*(cx);
G_output[offset] = R1*(1 - cy) + R2*(cy);
R1 = f_b[ximg]*(1 - cx) + f_b[ximg + 1]*(cx);
R2 = f_b[ximg + i_size]*(1 - cx) + f_b[ximg + 1 + i_size]*(cx);
B_output[offset] = R1*(1 - cy) + R2*(cy);
}
else
{
R_output[offset] = 0;
G_output[offset] = 0;
B_output[offset] = 0;
}
}
__global__ void PPnoise(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size, int noiseP, int seed)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
curandState_t state;
curand_init(seed, x, y, &state);
unsigned char noise = (unsigned char)(curand(&state) % 100);
if(curand(&state) % 100 < noiseP)
{
noise = 255 * (noise % 2);
R_input[offset] = noise;
G_input[offset] = noise;
B_input[offset] = noise;
}
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Plot_kernel(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * blockDim.x * gridDim.x;
unsigned char* f_r, *f_g, *f_b;
f_r = (unsigned char*)((char*)R_input + y*i_size);
f_g = (unsigned char*)((char*)G_input + y*i_size);
f_b = (unsigned char*)((char*)B_input + y*i_size);
ptr[offset].x = f_r[x];
ptr[offset].y = f_g[x];
ptr[offset].z = f_b[x];
ptr[offset].w = 255;
}
__device__ int log2(int N)
{
int k = N, i = 0;
while(k)
{
k >>= 1;
i++;
}
return i - 1;
}
__device__ int reverse(int N, int n)
{
int p = 0;
for(int j = 1; j <= log2(N); j++)
{
if(n & (1 << (log2(N) - j)))
p |= 1 << (j - 1);
}
return p;
}
__device__ void ordina_x(float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,int row, int col, int x)
{
int N = row, a;
for(int i = 0; i < N; i++)
{
a = reverse((int)N, i);
real_d_out[i*col + x] = complex_r[a*col + x];
imagi_d_out[i*col + x] = complex_i[a*col + x];}
for(int j = 0; j < N; j++)
{
complex_r[j*col + x] = real_d_out[j*col + x];
complex_i[j*col + x] = imagi_d_out[j*col + x];}
}
__device__ void ordina_y(float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,int row, int col, int y)
{
int N = row, a;
for(int i = 0; i < N; i++)
{
a = reverse((int)N, i);
real_d_out[y*col + i] = complex_r[y*col + a];
imagi_d_out[y*col + i] = complex_i[y*col + a];
}
for(int j = 0; j < N; j++)
{
complex_r[y*col + j] = real_d_out[y*col + j];
complex_i[y*col + j] = imagi_d_out[y*col + j];
}
}
__device__ void Func_FFT_X(float *complex_r, float *complex_i,int row, int col, int x)
{
int n = 1, N = row;
int a = N/2;
float temp_real, temp_imagi;
float t_r, t_i, a_r, a_i;
for(int j = 0; j < log2(N); j++)
{
for (int i = 0; i < N; i++)
{
if(!(i & n))
{
temp_real = complex_r[x + (i * col)];
temp_imagi = complex_i[x + (i * col)];
a_r = cos((-2) * ((i * a) % (n * a)) * PI / N);
a_i = sin((-2) * ((i * a) % (n * a)) * PI / N);
t_r = (a_r*complex_r[x + (i + n)*col]) - (a_i*complex_i[x + (i + n)*col]);
t_i = (a_i*complex_r[x + (i + n)*col]) + (a_r*complex_i[x + (i + n)*col]);
complex_r[x + (i * col)] += t_r;
complex_i[x + (i * col)] += t_i;
complex_r[x + (i + n)*col] = temp_real - t_r;
complex_i[x + (i + n)*col] = temp_imagi - t_i;
}
}
n *= 2;
a = a/2;
}
}
__device__ void Func_FFT_Y(float *complex_r, float *complex_i,int row, int col, int y)
{
int n = 1, N = col;
int a = N/2;
float temp_real, temp_imagi;
float t_r, t_i, a_r, a_i;
for(int j = 0; j < log2(N); j++)
{
for (int i = 0; i < N; i++)
{
if(!(i & n))
{
temp_real = complex_r[i + (y * col)];
temp_imagi = complex_i[i + (y * col)];
a_r = cos(-2 * ((i * a) % (n * a)) * PI/ N);
a_i = sin(-2 * ((i * a) % (n * a)) * PI/ N);
t_r = (a_r*complex_r[(i + n) + y*col]) - (a_i*complex_i[(i + n) + y*col]);
t_i = (a_i*complex_r[(i + n) + y*col]) + (a_r*complex_i[(i + n) + y*col]);
complex_r[i + (y * col)] += t_r;
complex_i[i + (y * col)] += t_i;
complex_r[(i + n) + y*col] = temp_real - t_r;
complex_i[(i + n) + y*col] = temp_imagi - t_i;
}
}
n *= 2;
a = a/2;
}
}
__global__ void FFT_X(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned long colF, unsigned long rowF )
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
float temp;
if(x < col)
{
for (int i = 0; i < row; i++)
{
complex_r[x + (i * colF)] = 0.2989 * R_input[x + (i * i_size)] + 0.587 * G_input[x + (i * i_size)] + 0.1140 * B_input[x + (i * i_size)];
complex_i[x + (i * colF)] = 0;
}
for (int i = row; i < rowF; i++)
{
complex_r[x + (i * colF)] = 0;
complex_i[x + (i * colF)] = 0;
}
}
else
{
for (int i = 0; i < rowF; i++)
{
complex_r[x + (i * colF)] = 0;
complex_i[x + (i * colF)] = 0;
}
}
ordina_x(complex_r, complex_i, real_d_out, imagi_d_out, rowF, colF, x);
Func_FFT_X(complex_r, complex_i, rowF, colF, x);
for (int i = 0; i < rowF/2; i++)
{
temp = complex_r[x + (i * colF)];
complex_r[x + (i * colF)] = complex_r[x + ((i + rowF/2) * colF)];
complex_r[x + ((i + rowF/2) * colF)] = temp;
temp = complex_i[x + (i * colF)];
complex_i[x + (i * colF)] = complex_i[x + ((i + rowF/2) * colF)];
complex_i[x + ((i + rowF/2) * colF)] = temp;
}
}
__global__ void FFT_Y(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned long colF, unsigned long rowF )
{
int y = threadIdx.x + (blockIdx.x * blockDim.x);
float temp;
ordina_y(complex_r, complex_i, real_d_out, imagi_d_out, rowF, colF, y);
Func_FFT_Y(complex_r, complex_i, rowF, colF, y);
for (int i = 0; i < colF/2; i++)
{
temp = complex_r[i + (y * colF)];
complex_r[i + (y * colF)] = complex_r[(i + colF/2) + (y * colF)];
complex_r[(i + colF/2) + (y * colF)] = temp;
temp = complex_i[i + (y * colF)];
complex_i[i + (y * colF)] = complex_i[(i + colF/2) + (y * colF)];
complex_i[(i + colF/2) + (y * colF)] = temp;
}
unsigned char v;
int a = (colF/2) - (col/2);
int temp_b = (rowF/2) - (row/2);
if( y >= temp_b)
for (int i = a; i < (colF/2) + (col/2); i++)
{
v = (unsigned char)(20*log10(sqrt((complex_r[i + (y * colF)]*complex_r[i + (y * colF)]) + (complex_i[i + (y * colF)]*complex_i[i + (y * colF)]))));
r_dataC[(i - a ) + (y - temp_b) * i_size] = v;
g_dataC[(i - a) + (y - temp_b) * i_size] = v;
b_dataC[(i - a) + (y - temp_b) * i_size] = v;
}
}
__global__ void erosion(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,float *mask, unsigned int dim, int m)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c = 0;
unsigned char color;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++)
{
ximg = x + i;
for (int j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
c += (R_input[offset2]*mask[k]);
k++;
}
}
if(c < m) color = 0;
else color = 255;
r_dataC[offset] = color;
g_dataC[offset] = color;
b_dataC[offset] = color;
}
__global__ void histogramGray(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned int *hist)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset];
G_input[offset] = R_input[offset];
B_input[offset] = R_input[offset];
atomicAdd( &(hist[R_input[offset]]), 1);
}
__global__ void binary(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,int um)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
unsigned char c;
if (R_input[offset] > um) c = 255;
else c = 0;
R_input[offset] = c;
G_input[offset] = c;
B_input[offset] = c;
}
__global__ void Copy(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *R_output, unsigned char *G_output,unsigned char *B_output)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned int dim)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++)
{
ximg = x + i;
for (j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
{
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;
}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i])
{
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i])
{
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i])
{
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;
}
if(n%2 == 1)
{
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}
else
{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,float *mask, unsigned int dim)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++)
{
ximg = x + i;
for (int j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
{
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];
}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Get_Histogram(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned int *hist_r,unsigned int *hist_g,unsigned int *hist_b)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
atomicAdd( &(hist_r[R_input[offset]]), 1);
atomicAdd( &(hist_g[G_input[offset]]), 1);
atomicAdd( &(hist_b[B_input[offset]]), 1);
}
__global__ void Equalization_GPU(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataE, unsigned char *g_dataE,unsigned char *b_dataE,unsigned int *hist_r,unsigned int *hist_g,unsigned int *hist_b)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
r_dataE[offset] = hist_r[R_input[offset]];
g_dataE[offset] = hist_g[G_input[offset]];
b_dataE[offset] = hist_b[B_input[offset]];
}
__global__ void Rotation_op(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size, float a,unsigned long col, unsigned long row)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * blockDim.x * gridDim.x;
x = x - (blockDim.x * gridDim.x / 2);
y = y - (blockDim.y * gridDim.y / 2);
unsigned char* f_r, *f_g, *f_b;
int ximg = (x*cos(a) + y*sin(a)) + (col/2), yimg = (y*cos(a) - x*sin(a)) + (row/2);
if (ximg < col && yimg < row)
{
f_r = (unsigned char*)((char*)R_input + yimg*i_size);
f_g = (unsigned char*)((char*)G_input + yimg*i_size);
f_b = (unsigned char*)((char*)B_input + yimg*i_size);
ptr[offset].x = f_r[ximg];
ptr[offset].y = f_g[ximg];
ptr[offset].z = f_b[ximg];
ptr[offset].w = 255;
}
else
{
ptr[offset].x = 0;
ptr[offset].y = 0;
ptr[offset].z = 0;
ptr[offset].w = 255;
}
}
__global__ void Scaling_op(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input,unsigned char *R_output, unsigned char *G_output,unsigned char *B_output,size_t i_size, size_t pitch2, float s,unsigned long col, unsigned long row)
{
float x = threadIdx.x + (blockIdx.x * blockDim.x);
float y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * pitch2;
x = x - (DIM / 2);
y = y - (DIM / 2);
unsigned char* f_r, *f_g, *f_b;
x /= s; y /= s;
int ximg = x + (col/2), yimg = y + (row/2);
if (ximg < (col - 1) && yimg < (row - 1))
{
f_r = (unsigned char*)((char*)R_input + yimg*i_size);
f_g = (unsigned char*)((char*)G_input + yimg*i_size);
f_b = (unsigned char*)((char*)B_input + yimg*i_size);
float cx = x - floor(x);
float cy = y - floor(y);
float R1 = f_r[ximg]*(1 - cx) + f_r[ximg + 1]*(cx);
float R2 = f_r[ximg + i_size]*(1 - cx) + f_r[ximg + 1 + i_size]*(cx);
R_output[offset] = R1*(1 - cy) + R2*(cy);
R1 = f_g[ximg]*(1 - cx) + f_g[ximg + 1]*(cx);
R2 = f_g[ximg + i_size]*(1 - cx) + f_g[ximg + 1 + i_size]*(cx);
G_output[offset] = R1*(1 - cy) + R2*(cy);
R1 = f_b[ximg]*(1 - cx) + f_b[ximg + 1]*(cx);
R2 = f_b[ximg + i_size]*(1 - cx) + f_b[ximg + 1 + i_size]*(cx);
B_output[offset] = R1*(1 - cy) + R2*(cy);
}
else
{
R_output[offset] = 0;
G_output[offset] = 0;
B_output[offset] = 0;
}
}
__global__ void PPnoise(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size, int noiseP, int seed)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
hiprandState_t state;
hiprand_init(seed, x, y, &state);
unsigned char noise = (unsigned char)(hiprand(&state) % 100);
if(hiprand(&state) % 100 < noiseP)
{
noise = 255 * (noise % 2);
R_input[offset] = noise;
G_input[offset] = noise;
B_input[offset] = noise;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void Plot_kernel(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * blockDim.x * gridDim.x;
unsigned char* f_r, *f_g, *f_b;
f_r = (unsigned char*)((char*)R_input + y*i_size);
f_g = (unsigned char*)((char*)G_input + y*i_size);
f_b = (unsigned char*)((char*)B_input + y*i_size);
ptr[offset].x = f_r[x];
ptr[offset].y = f_g[x];
ptr[offset].z = f_b[x];
ptr[offset].w = 255;
}
__device__ int log2(int N)
{
int k = N, i = 0;
while(k)
{
k >>= 1;
i++;
}
return i - 1;
}
__device__ int reverse(int N, int n)
{
int p = 0;
for(int j = 1; j <= log2(N); j++)
{
if(n & (1 << (log2(N) - j)))
p |= 1 << (j - 1);
}
return p;
}
__device__ void ordina_x(float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,int row, int col, int x)
{
int N = row, a;
for(int i = 0; i < N; i++)
{
a = reverse((int)N, i);
real_d_out[i*col + x] = complex_r[a*col + x];
imagi_d_out[i*col + x] = complex_i[a*col + x];}
for(int j = 0; j < N; j++)
{
complex_r[j*col + x] = real_d_out[j*col + x];
complex_i[j*col + x] = imagi_d_out[j*col + x];}
}
__device__ void ordina_y(float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,int row, int col, int y)
{
int N = row, a;
for(int i = 0; i < N; i++)
{
a = reverse((int)N, i);
real_d_out[y*col + i] = complex_r[y*col + a];
imagi_d_out[y*col + i] = complex_i[y*col + a];
}
for(int j = 0; j < N; j++)
{
complex_r[y*col + j] = real_d_out[y*col + j];
complex_i[y*col + j] = imagi_d_out[y*col + j];
}
}
__device__ void Func_FFT_X(float *complex_r, float *complex_i,int row, int col, int x)
{
int n = 1, N = row;
int a = N/2;
float temp_real, temp_imagi;
float t_r, t_i, a_r, a_i;
for(int j = 0; j < log2(N); j++)
{
for (int i = 0; i < N; i++)
{
if(!(i & n))
{
temp_real = complex_r[x + (i * col)];
temp_imagi = complex_i[x + (i * col)];
a_r = cos((-2) * ((i * a) % (n * a)) * PI / N);
a_i = sin((-2) * ((i * a) % (n * a)) * PI / N);
t_r = (a_r*complex_r[x + (i + n)*col]) - (a_i*complex_i[x + (i + n)*col]);
t_i = (a_i*complex_r[x + (i + n)*col]) + (a_r*complex_i[x + (i + n)*col]);
complex_r[x + (i * col)] += t_r;
complex_i[x + (i * col)] += t_i;
complex_r[x + (i + n)*col] = temp_real - t_r;
complex_i[x + (i + n)*col] = temp_imagi - t_i;
}
}
n *= 2;
a = a/2;
}
}
__device__ void Func_FFT_Y(float *complex_r, float *complex_i,int row, int col, int y)
{
int n = 1, N = col;
int a = N/2;
float temp_real, temp_imagi;
float t_r, t_i, a_r, a_i;
for(int j = 0; j < log2(N); j++)
{
for (int i = 0; i < N; i++)
{
if(!(i & n))
{
temp_real = complex_r[i + (y * col)];
temp_imagi = complex_i[i + (y * col)];
a_r = cos(-2 * ((i * a) % (n * a)) * PI/ N);
a_i = sin(-2 * ((i * a) % (n * a)) * PI/ N);
t_r = (a_r*complex_r[(i + n) + y*col]) - (a_i*complex_i[(i + n) + y*col]);
t_i = (a_i*complex_r[(i + n) + y*col]) + (a_r*complex_i[(i + n) + y*col]);
complex_r[i + (y * col)] += t_r;
complex_i[i + (y * col)] += t_i;
complex_r[(i + n) + y*col] = temp_real - t_r;
complex_i[(i + n) + y*col] = temp_imagi - t_i;
}
}
n *= 2;
a = a/2;
}
}
__global__ void FFT_X(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned long colF, unsigned long rowF )
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
float temp;
if(x < col)
{
for (int i = 0; i < row; i++)
{
complex_r[x + (i * colF)] = 0.2989 * R_input[x + (i * i_size)] + 0.587 * G_input[x + (i * i_size)] + 0.1140 * B_input[x + (i * i_size)];
complex_i[x + (i * colF)] = 0;
}
for (int i = row; i < rowF; i++)
{
complex_r[x + (i * colF)] = 0;
complex_i[x + (i * colF)] = 0;
}
}
else
{
for (int i = 0; i < rowF; i++)
{
complex_r[x + (i * colF)] = 0;
complex_i[x + (i * colF)] = 0;
}
}
ordina_x(complex_r, complex_i, real_d_out, imagi_d_out, rowF, colF, x);
Func_FFT_X(complex_r, complex_i, rowF, colF, x);
for (int i = 0; i < rowF/2; i++)
{
temp = complex_r[x + (i * colF)];
complex_r[x + (i * colF)] = complex_r[x + ((i + rowF/2) * colF)];
complex_r[x + ((i + rowF/2) * colF)] = temp;
temp = complex_i[x + (i * colF)];
complex_i[x + (i * colF)] = complex_i[x + ((i + rowF/2) * colF)];
complex_i[x + ((i + rowF/2) * colF)] = temp;
}
}
__global__ void FFT_Y(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,float *complex_r, float *complex_i,float *real_d_out, float *imagi_d_out,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned long colF, unsigned long rowF )
{
int y = threadIdx.x + (blockIdx.x * blockDim.x);
float temp;
ordina_y(complex_r, complex_i, real_d_out, imagi_d_out, rowF, colF, y);
Func_FFT_Y(complex_r, complex_i, rowF, colF, y);
for (int i = 0; i < colF/2; i++)
{
temp = complex_r[i + (y * colF)];
complex_r[i + (y * colF)] = complex_r[(i + colF/2) + (y * colF)];
complex_r[(i + colF/2) + (y * colF)] = temp;
temp = complex_i[i + (y * colF)];
complex_i[i + (y * colF)] = complex_i[(i + colF/2) + (y * colF)];
complex_i[(i + colF/2) + (y * colF)] = temp;
}
unsigned char v;
int a = (colF/2) - (col/2);
int temp_b = (rowF/2) - (row/2);
if( y >= temp_b)
for (int i = a; i < (colF/2) + (col/2); i++)
{
v = (unsigned char)(20*log10(sqrt((complex_r[i + (y * colF)]*complex_r[i + (y * colF)]) + (complex_i[i + (y * colF)]*complex_i[i + (y * colF)]))));
r_dataC[(i - a ) + (y - temp_b) * i_size] = v;
g_dataC[(i - a) + (y - temp_b) * i_size] = v;
b_dataC[(i - a) + (y - temp_b) * i_size] = v;
}
}
__global__ void erosion(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,float *mask, unsigned int dim, int m)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c = 0;
unsigned char color;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++)
{
ximg = x + i;
for (int j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
c += (R_input[offset2]*mask[k]);
k++;
}
}
if(c < m) color = 0;
else color = 255;
r_dataC[offset] = color;
g_dataC[offset] = color;
b_dataC[offset] = color;
}
__global__ void histogramGray(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned int *hist)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset];
G_input[offset] = R_input[offset];
B_input[offset] = R_input[offset];
atomicAdd( &(hist[R_input[offset]]), 1);
}
__global__ void binary(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,int um)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
unsigned char c;
if (R_input[offset] > um) c = 255;
else c = 0;
R_input[offset] = c;
G_input[offset] = c;
B_input[offset] = c;
}
__global__ void Copy(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *R_output, unsigned char *G_output,unsigned char *B_output)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
R_output[offset] = R_input[offset];
G_output[offset] = G_input[offset];
B_output[offset] = B_input[offset];
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,unsigned int dim)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++)
{
ximg = x + i;
for (j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
{
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;
}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i])
{
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i])
{
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i])
{
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;
}
if(n%2 == 1)
{
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}
else
{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataC, unsigned char *g_dataC,unsigned char *b_dataC, unsigned long col, unsigned long row,float *mask, unsigned int dim)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++)
{
ximg = x + i;
for (int j = ini; j <= end; j++)
{
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
{
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];
}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Get_Histogram(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned int *hist_r,unsigned int *hist_g,unsigned int *hist_b)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
atomicAdd( &(hist_r[R_input[offset]]), 1);
atomicAdd( &(hist_g[G_input[offset]]), 1);
atomicAdd( &(hist_b[B_input[offset]]), 1);
}
__global__ void Equalization_GPU(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size,unsigned char *r_dataE, unsigned char *g_dataE,unsigned char *b_dataE,unsigned int *hist_r,unsigned int *hist_g,unsigned int *hist_b)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
r_dataE[offset] = hist_r[R_input[offset]];
g_dataE[offset] = hist_g[G_input[offset]];
b_dataE[offset] = hist_b[B_input[offset]];
}
__global__ void Rotation_op(uchar4 *ptr, unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size, float a,unsigned long col, unsigned long row)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * blockDim.x * gridDim.x;
x = x - (blockDim.x * gridDim.x / 2);
y = y - (blockDim.y * gridDim.y / 2);
unsigned char* f_r, *f_g, *f_b;
int ximg = (x*cos(a) + y*sin(a)) + (col/2), yimg = (y*cos(a) - x*sin(a)) + (row/2);
if (ximg < col && yimg < row)
{
f_r = (unsigned char*)((char*)R_input + yimg*i_size);
f_g = (unsigned char*)((char*)G_input + yimg*i_size);
f_b = (unsigned char*)((char*)B_input + yimg*i_size);
ptr[offset].x = f_r[ximg];
ptr[offset].y = f_g[ximg];
ptr[offset].z = f_b[ximg];
ptr[offset].w = 255;
}
else
{
ptr[offset].x = 0;
ptr[offset].y = 0;
ptr[offset].z = 0;
ptr[offset].w = 255;
}
}
__global__ void Scaling_op(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input,unsigned char *R_output, unsigned char *G_output,unsigned char *B_output,size_t i_size, size_t pitch2, float s,unsigned long col, unsigned long row)
{
float x = threadIdx.x + (blockIdx.x * blockDim.x);
float y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * pitch2;
x = x - (DIM / 2);
y = y - (DIM / 2);
unsigned char* f_r, *f_g, *f_b;
x /= s; y /= s;
int ximg = x + (col/2), yimg = y + (row/2);
if (ximg < (col - 1) && yimg < (row - 1))
{
f_r = (unsigned char*)((char*)R_input + yimg*i_size);
f_g = (unsigned char*)((char*)G_input + yimg*i_size);
f_b = (unsigned char*)((char*)B_input + yimg*i_size);
float cx = x - floor(x);
float cy = y - floor(y);
float R1 = f_r[ximg]*(1 - cx) + f_r[ximg + 1]*(cx);
float R2 = f_r[ximg + i_size]*(1 - cx) + f_r[ximg + 1 + i_size]*(cx);
R_output[offset] = R1*(1 - cy) + R2*(cy);
R1 = f_g[ximg]*(1 - cx) + f_g[ximg + 1]*(cx);
R2 = f_g[ximg + i_size]*(1 - cx) + f_g[ximg + 1 + i_size]*(cx);
G_output[offset] = R1*(1 - cy) + R2*(cy);
R1 = f_b[ximg]*(1 - cx) + f_b[ximg + 1]*(cx);
R2 = f_b[ximg + i_size]*(1 - cx) + f_b[ximg + 1 + i_size]*(cx);
B_output[offset] = R1*(1 - cy) + R2*(cy);
}
else
{
R_output[offset] = 0;
G_output[offset] = 0;
B_output[offset] = 0;
}
}
__global__ void PPnoise(unsigned char *R_input, unsigned char *G_input,unsigned char *B_input, size_t i_size, int noiseP, int seed)
{
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
hiprandState_t state;
hiprand_init(seed, x, y, &state);
unsigned char noise = (unsigned char)(hiprand(&state) % 100);
if(hiprand(&state) % 100 < noiseP)
{
noise = 255 * (noise % 2);
R_input[offset] = noise;
G_input[offset] = noise;
B_input[offset] = noise;
}
} | .text
.file "functions.hip"
.globl _Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m # -- Begin function _Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.p2align 4, 0x90
.type _Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m,@function
_Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m: # @_Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m, .Lfunc_end0-_Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.cfi_endproc
# -- End function
.globl _Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm # -- Begin function _Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.p2align 4, 0x90
.type _Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm,@function
_Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm: # @_Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end1:
.size _Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm, .Lfunc_end1-_Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.cfi_endproc
# -- End function
.globl _Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm # -- Begin function _Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.p2align 4, 0x90
.type _Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm,@function
_Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm: # @_Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end2:
.size _Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm, .Lfunc_end2-_Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.cfi_endproc
# -- End function
.globl _Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji # -- Begin function _Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji
.p2align 4, 0x90
.type _Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji,@function
_Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji: # @_Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7erosionPhS_S_mS_S_S_mmPfji, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end3:
.size _Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji, .Lfunc_end3-_Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji
.cfi_endproc
# -- End function
.globl _Z28__device_stub__histogramGrayPhS_S_mPj # -- Begin function _Z28__device_stub__histogramGrayPhS_S_mPj
.p2align 4, 0x90
.type _Z28__device_stub__histogramGrayPhS_S_mPj,@function
_Z28__device_stub__histogramGrayPhS_S_mPj: # @_Z28__device_stub__histogramGrayPhS_S_mPj
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13histogramGrayPhS_S_mPj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end4:
.size _Z28__device_stub__histogramGrayPhS_S_mPj, .Lfunc_end4-_Z28__device_stub__histogramGrayPhS_S_mPj
.cfi_endproc
# -- End function
.globl _Z21__device_stub__binaryPhS_S_mi # -- Begin function _Z21__device_stub__binaryPhS_S_mi
.p2align 4, 0x90
.type _Z21__device_stub__binaryPhS_S_mi,@function
_Z21__device_stub__binaryPhS_S_mi: # @_Z21__device_stub__binaryPhS_S_mi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6binaryPhS_S_mi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end5:
.size _Z21__device_stub__binaryPhS_S_mi, .Lfunc_end5-_Z21__device_stub__binaryPhS_S_mi
.cfi_endproc
# -- End function
.globl _Z19__device_stub__CopyPhS_S_mS_S_S_ # -- Begin function _Z19__device_stub__CopyPhS_S_mS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__CopyPhS_S_mS_S_S_,@function
_Z19__device_stub__CopyPhS_S_mS_S_S_: # @_Z19__device_stub__CopyPhS_S_mS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4CopyPhS_S_mS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size _Z19__device_stub__CopyPhS_S_mS_S_S_, .Lfunc_end6-_Z19__device_stub__CopyPhS_S_mS_S_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj # -- Begin function _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.p2align 4, 0x90
.type _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj,@function
_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj: # @_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13median_filterPhS_S_mS_S_S_mmj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end7:
.size _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj, .Lfunc_end7-_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.cfi_endproc
# -- End function
.globl _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj # -- Begin function _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.p2align 4, 0x90
.type _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj,@function
_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj: # @_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end8:
.size _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj, .Lfunc_end8-_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.cfi_endproc
# -- End function
.globl _Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_ # -- Begin function _Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_
.p2align 4, 0x90
.type _Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_,@function
_Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_: # @_Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Get_HistogramPhS_S_mPjS0_S0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size _Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_, .Lfunc_end9-_Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_ # -- Begin function _Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.p2align 4, 0x90
.type _Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_,@function
_Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_: # @_Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end10:
.size _Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_, .Lfunc_end10-_Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm # -- Begin function _Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.p2align 4, 0x90
.type _Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm,@function
_Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm: # @_Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %r9, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 192(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end11:
.size _Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, .Lfunc_end11-_Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm # -- Begin function _Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm
.p2align 4, 0x90
.type _Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm,@function
_Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm: # @_Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 232(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10Scaling_opPhS_S_S_S_S_mmfmm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end12:
.size _Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm, .Lfunc_end12-_Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm
.cfi_endproc
# -- End function
.globl _Z22__device_stub__PPnoisePhS_S_mii # -- Begin function _Z22__device_stub__PPnoisePhS_S_mii
.p2align 4, 0x90
.type _Z22__device_stub__PPnoisePhS_S_mii,@function
_Z22__device_stub__PPnoisePhS_S_mii: # @_Z22__device_stub__PPnoisePhS_S_mii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7PPnoisePhS_S_mii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end13:
.size _Z22__device_stub__PPnoisePhS_S_mii, .Lfunc_end13-_Z22__device_stub__PPnoisePhS_S_mii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7erosionPhS_S_mS_S_S_mmPfji, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13histogramGrayPhS_S_mPj, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6binaryPhS_S_mi, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4CopyPhS_S_mS_S_S_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13median_filterPhS_S_mS_S_S_mmj, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Get_HistogramPhS_S_mPjS0_S0_, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Scaling_opPhS_S_S_S_S_mmfmm, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7PPnoisePhS_S_mii, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m,@object # @_Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.section .rodata,"a",@progbits
.globl _Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.p2align 3, 0x0
_Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m:
.quad _Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.size _Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m, 8
.type _Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm,@object # @_Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.globl _Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.p2align 3, 0x0
_Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm:
.quad _Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.size _Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm, 8
.type _Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm,@object # @_Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.globl _Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.p2align 3, 0x0
_Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm:
.quad _Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.size _Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm, 8
.type _Z7erosionPhS_S_mS_S_S_mmPfji,@object # @_Z7erosionPhS_S_mS_S_S_mmPfji
.globl _Z7erosionPhS_S_mS_S_S_mmPfji
.p2align 3, 0x0
_Z7erosionPhS_S_mS_S_S_mmPfji:
.quad _Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji
.size _Z7erosionPhS_S_mS_S_S_mmPfji, 8
.type _Z13histogramGrayPhS_S_mPj,@object # @_Z13histogramGrayPhS_S_mPj
.globl _Z13histogramGrayPhS_S_mPj
.p2align 3, 0x0
_Z13histogramGrayPhS_S_mPj:
.quad _Z28__device_stub__histogramGrayPhS_S_mPj
.size _Z13histogramGrayPhS_S_mPj, 8
.type _Z6binaryPhS_S_mi,@object # @_Z6binaryPhS_S_mi
.globl _Z6binaryPhS_S_mi
.p2align 3, 0x0
_Z6binaryPhS_S_mi:
.quad _Z21__device_stub__binaryPhS_S_mi
.size _Z6binaryPhS_S_mi, 8
.type _Z4CopyPhS_S_mS_S_S_,@object # @_Z4CopyPhS_S_mS_S_S_
.globl _Z4CopyPhS_S_mS_S_S_
.p2align 3, 0x0
_Z4CopyPhS_S_mS_S_S_:
.quad _Z19__device_stub__CopyPhS_S_mS_S_S_
.size _Z4CopyPhS_S_mS_S_S_, 8
.type _Z13median_filterPhS_S_mS_S_S_mmj,@object # @_Z13median_filterPhS_S_mS_S_S_mmj
.globl _Z13median_filterPhS_S_mS_S_S_mmj
.p2align 3, 0x0
_Z13median_filterPhS_S_mS_S_S_mmj:
.quad _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.size _Z13median_filterPhS_S_mS_S_S_mmj, 8
.type _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj,@object # @_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.globl _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.p2align 3, 0x0
_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj:
.quad _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.size _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, 8
.type _Z13Get_HistogramPhS_S_mPjS0_S0_,@object # @_Z13Get_HistogramPhS_S_mPjS0_S0_
.globl _Z13Get_HistogramPhS_S_mPjS0_S0_
.p2align 3, 0x0
_Z13Get_HistogramPhS_S_mPjS0_S0_:
.quad _Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_
.size _Z13Get_HistogramPhS_S_mPjS0_S0_, 8
.type _Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_,@object # @_Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.globl _Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.p2align 3, 0x0
_Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_:
.quad _Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.size _Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_, 8
.type _Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm,@object # @_Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.globl _Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.p2align 3, 0x0
_Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm:
.quad _Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.size _Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm, 8
.type _Z10Scaling_opPhS_S_S_S_S_mmfmm,@object # @_Z10Scaling_opPhS_S_S_S_S_mmfmm
.globl _Z10Scaling_opPhS_S_S_S_S_mmfmm
.p2align 3, 0x0
_Z10Scaling_opPhS_S_S_S_S_mmfmm:
.quad _Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm
.size _Z10Scaling_opPhS_S_S_S_S_mmfmm, 8
.type _Z7PPnoisePhS_S_mii,@object # @_Z7PPnoisePhS_S_mii
.globl _Z7PPnoisePhS_S_mii
.p2align 3, 0x0
_Z7PPnoisePhS_S_mii:
.quad _Z22__device_stub__PPnoisePhS_S_mii
.size _Z7PPnoisePhS_S_mii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m"
.size .L__unnamed_1, 50
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm"
.size .L__unnamed_2, 37
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm"
.size .L__unnamed_3, 37
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z7erosionPhS_S_mS_S_S_mmPfji"
.size .L__unnamed_4, 30
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z13histogramGrayPhS_S_mPj"
.size .L__unnamed_5, 27
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z6binaryPhS_S_mi"
.size .L__unnamed_6, 18
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z4CopyPhS_S_mS_S_S_"
.size .L__unnamed_7, 21
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z13median_filterPhS_S_mS_S_S_mmj"
.size .L__unnamed_8, 34
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj"
.size .L__unnamed_9, 43
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z13Get_HistogramPhS_S_mPjS0_S0_"
.size .L__unnamed_10, 33
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_"
.size .L__unnamed_11, 42
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "_Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm"
.size .L__unnamed_12, 53
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "_Z10Scaling_opPhS_S_S_S_S_mmfmm"
.size .L__unnamed_13, 32
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "_Z7PPnoisePhS_S_mii"
.size .L__unnamed_14, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.addrsig_sym _Z20__device_stub__FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.addrsig_sym _Z20__device_stub__FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.addrsig_sym _Z22__device_stub__erosionPhS_S_mS_S_S_mmPfji
.addrsig_sym _Z28__device_stub__histogramGrayPhS_S_mPj
.addrsig_sym _Z21__device_stub__binaryPhS_S_mi
.addrsig_sym _Z19__device_stub__CopyPhS_S_mS_S_S_
.addrsig_sym _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.addrsig_sym _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.addrsig_sym _Z28__device_stub__Get_HistogramPhS_S_mPjS0_S0_
.addrsig_sym _Z31__device_stub__Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.addrsig_sym _Z26__device_stub__Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.addrsig_sym _Z25__device_stub__Scaling_opPhS_S_S_S_S_mmfmm
.addrsig_sym _Z22__device_stub__PPnoisePhS_S_mii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Plot_kernelP15HIP_vector_typeIhLj4EEPhS2_S2_m
.addrsig_sym _Z5FFT_XPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.addrsig_sym _Z5FFT_YPhS_S_mPfS0_S0_S0_S_S_S_mmmm
.addrsig_sym _Z7erosionPhS_S_mS_S_S_mmPfji
.addrsig_sym _Z13histogramGrayPhS_S_mPj
.addrsig_sym _Z6binaryPhS_S_mi
.addrsig_sym _Z4CopyPhS_S_mS_S_S_
.addrsig_sym _Z13median_filterPhS_S_mS_S_S_mmj
.addrsig_sym _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.addrsig_sym _Z13Get_HistogramPhS_S_mPjS0_S0_
.addrsig_sym _Z16Equalization_GPUPhS_S_mS_S_S_PjS0_S0_
.addrsig_sym _Z11Rotation_opP15HIP_vector_typeIhLj4EEPhS2_S2_mfmm
.addrsig_sym _Z10Scaling_opPhS_S_S_S_S_mmfmm
.addrsig_sym _Z7PPnoisePhS_S_mii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
struct list_elem {
int key;
list_elem *next;
};
template <typename T>
void alloc_bytes(T &ptr, size_t num_bytes){
cudaMallocManaged(&ptr, num_bytes);
}
__host__ __device__
void print_element(list_elem *list, int ele_num){
list_elem *elem = list;
for (int i = 0; i < ele_num; i++)
elem = elem->next;
printf("key = %d\n", elem->key);
}
__global__ void gpu_print_element(list_elem *list, int ele_num){
print_element(list, ele_num);
}
const int num_elem = 5;
const int ele = 3;
int main(){
list_elem *list_base, *list;
alloc_bytes(list_base, sizeof(list_elem));
list = list_base;
for (int i = 0; i < num_elem; i++){
list->key = i;
alloc_bytes(list->next, sizeof(list_elem));
list = list->next;}
print_element(list_base, ele);
gpu_print_element<<<1,1>>>(list_base, ele);
cudaDeviceSynchronize();
cudaCheckErrors("cuda error!");
} | code for sm_80
Function : _Z17gpu_print_elementP9list_elemi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fcc00008e06ff */
/*0090*/ @!P0 BRA 0x430 ; /* 0x0000039000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R0, R4.reuse, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*00d0*/ @!P0 BRA 0x3d0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R0, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004007a10 */
/* 0x000fc80007ffe1ff */
/*00f0*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 BRA 0x360 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*0120*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0130*/ @!P1 BRA 0x280 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0150*/ LD.E.64 R2, [R2.64+0x8] ; /* 0x0000080402027980 */
/* 0x020ea8000c101b00 */
/*0160*/ LD.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087980 */
/* 0x004ea8000c101b00 */
/*0170*/ LD.E.64 R8, [R8.64+0x8] ; /* 0x0000080408087980 */
/* 0x004ea8000c101b00 */
/*0180*/ LD.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7980 */
/* 0x004ea8000c101b00 */
/*0190*/ LD.E.64 R10, [R10.64+0x8] ; /* 0x000008040a0a7980 */
/* 0x004ea8000c101b00 */
/*01a0*/ LD.E.64 R12, [R10.64+0x8] ; /* 0x000008040a0c7980 */
/* 0x004ea8000c101b00 */
/*01b0*/ LD.E.64 R12, [R12.64+0x8] ; /* 0x000008040c0c7980 */
/* 0x004ea8000c101b00 */
/*01c0*/ LD.E.64 R14, [R12.64+0x8] ; /* 0x000008040c0e7980 */
/* 0x004ea8000c101b00 */
/*01d0*/ LD.E.64 R14, [R14.64+0x8] ; /* 0x000008040e0e7980 */
/* 0x004ea8000c101b00 */
/*01e0*/ LD.E.64 R16, [R14.64+0x8] ; /* 0x000008040e107980 */
/* 0x004ea8000c101b00 */
/*01f0*/ LD.E.64 R16, [R16.64+0x8] ; /* 0x0000080410107980 */
/* 0x004ea8000c101b00 */
/*0200*/ LD.E.64 R18, [R16.64+0x8] ; /* 0x0000080410127980 */
/* 0x004ea8000c101b00 */
/*0210*/ LD.E.64 R18, [R18.64+0x8] ; /* 0x0000080412127980 */
/* 0x004ea8000c101b00 */
/*0220*/ LD.E.64 R20, [R18.64+0x8] ; /* 0x0000080412147980 */
/* 0x005ea2000c101b00 */
/*0230*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fc80007ffe0ff */
/*0240*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f24270 */
/*0250*/ LD.E.64 R20, [R20.64+0x8] ; /* 0x0000080414147980 */
/* 0x004ea8000c101b00 */
/*0260*/ LD.E.64 R2, [R20.64+0x8] ; /* 0x0000080414027980 */
/* 0x004170000c101b00 */
/*0270*/ @P1 BRA 0x150 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0280*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f24270 */
/*0290*/ @!P1 BRA 0x340 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*02a0*/ LD.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087980 */
/* 0x020ea8000c101b00 */
/*02b0*/ LD.E.64 R8, [R8.64+0x8] ; /* 0x0000080408087980 */
/* 0x004ea8000c101b00 */
/*02c0*/ LD.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7980 */
/* 0x004ea8000c101b00 */
/*02d0*/ LD.E.64 R10, [R10.64+0x8] ; /* 0x000008040a0a7980 */
/* 0x004ea8000c101b00 */
/*02e0*/ LD.E.64 R12, [R10.64+0x8] ; /* 0x000008040a0c7980 */
/* 0x004ea8000c101b00 */
/*02f0*/ LD.E.64 R12, [R12.64+0x8] ; /* 0x000008040c0c7980 */
/* 0x004ea8000c101b00 */
/*0300*/ LD.E.64 R14, [R12.64+0x8] ; /* 0x000008040c0e7980 */
/* 0x004ea2000c101b00 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0320*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe20007ffe0ff */
/*0330*/ LD.E.64 R2, [R14.64+0x8] ; /* 0x000008040e027980 */
/* 0x004368000c101b00 */
/*0340*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0350*/ @!P0 BRA 0x3d0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0360*/ LD.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087980 */
/* 0x020ea8000c101b00 */
/*0370*/ LD.E.64 R8, [R8.64+0x8] ; /* 0x0000080408087980 */
/* 0x004ea2000c101b00 */
/*0380*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*03a0*/ LD.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7980 */
/* 0x004ea8000c101b00 */
/*03b0*/ LD.E.64 R2, [R10.64+0x8] ; /* 0x000008040a027980 */
/* 0x004570000c101b00 */
/*03c0*/ @P0 BRA 0x360 ; /* 0xffffff9000000947 */
/* 0x027fea000383ffff */
/*03d0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0400*/ LD.E.64 R2, [R2.64+0x8] ; /* 0x0000080402027980 */
/* 0x020f66000c101b00 */
/*0410*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0420*/ @P0 BRA 0x3f0 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0430*/ LD.E R2, [R2.64] ; /* 0x0000000402027980 */
/* 0x020ea2000c101900 */
/*0440*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0470*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0007220000000a00 */
/*0480*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0047ea0000100800 */
/*0490*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x018fe40000000000 */
/*04a0*/ MOV R11, 0x510 ; /* 0x00000510000b7802 */
/* 0x000fe40000000f00 */
/*04b0*/ MOV R20, 0x490 ; /* 0x0000049000147802 */
/* 0x001fe40000000f00 */
/*04c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*04d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*04e0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*04f0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0500*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
struct list_elem {
int key;
list_elem *next;
};
template <typename T>
void alloc_bytes(T &ptr, size_t num_bytes){
cudaMallocManaged(&ptr, num_bytes);
}
__host__ __device__
void print_element(list_elem *list, int ele_num){
list_elem *elem = list;
for (int i = 0; i < ele_num; i++)
elem = elem->next;
printf("key = %d\n", elem->key);
}
__global__ void gpu_print_element(list_elem *list, int ele_num){
print_element(list, ele_num);
}
const int num_elem = 5;
const int ele = 3;
int main(){
list_elem *list_base, *list;
alloc_bytes(list_base, sizeof(list_elem));
list = list_base;
for (int i = 0; i < num_elem; i++){
list->key = i;
alloc_bytes(list->next, sizeof(list_elem));
list = list->next;}
print_element(list_base, ele);
gpu_print_element<<<1,1>>>(list_base, ele);
cudaDeviceSynchronize();
cudaCheckErrors("cuda error!");
} | .file "tmpxft_001ac8ec_00000000-6_linked_list_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "key = %d\n"
.text
.globl _Z13print_elementP9list_elemi
.type _Z13print_elementP9list_elemi, @function
_Z13print_elementP9list_elemi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %esi, %esi
jle .L4
movl $0, %eax
.L5:
movq 8(%rdi), %rdi
addl $1, %eax
cmpl %eax, %esi
jne .L5
.L4:
movl (%rdi), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13print_elementP9list_elemi, .-_Z13print_elementP9list_elemi
.globl _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
.type _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi, @function
_Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17gpu_print_elementP9list_elemi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi, .-_Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
.globl _Z17gpu_print_elementP9list_elemi
.type _Z17gpu_print_elementP9list_elemi, @function
_Z17gpu_print_elementP9list_elemi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z17gpu_print_elementP9list_elemi, .-_Z17gpu_print_elementP9list_elemi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mlwong/cuda-training-series/master/exercises/hw6/linked_list_solution.cu"
.section .rodata.str1.1
.LC2:
.string "cuda error!"
.section .rodata.str1.8
.align 8
.LC3:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC4:
.string "*** FAILED - ABORTING\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rbp
movl $0, %ebx
.L17:
movl %ebx, 0(%rbp)
leaq 8(%rbp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 8(%rbp), %rbp
addl $1, %ebx
cmpl $5, %ebx
jne .L17
movl $3, %esi
movq 8(%rsp), %rdi
call _Z13print_elementP9list_elemi
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $3, %esi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
jmp .L18
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $53
.cfi_def_cfa_offset 96
leaq .LC1(%rip), %r9
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z17gpu_print_elementP9list_elemi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17gpu_print_elementP9list_elemi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
struct list_elem {
int key;
list_elem *next;
};
template <typename T>
void alloc_bytes(T &ptr, size_t num_bytes){
cudaMallocManaged(&ptr, num_bytes);
}
__host__ __device__
void print_element(list_elem *list, int ele_num){
list_elem *elem = list;
for (int i = 0; i < ele_num; i++)
elem = elem->next;
printf("key = %d\n", elem->key);
}
__global__ void gpu_print_element(list_elem *list, int ele_num){
print_element(list, ele_num);
}
const int num_elem = 5;
const int ele = 3;
int main(){
list_elem *list_base, *list;
alloc_bytes(list_base, sizeof(list_elem));
list = list_base;
for (int i = 0; i < num_elem; i++){
list->key = i;
alloc_bytes(list->next, sizeof(list_elem));
list = list->next;}
print_element(list_base, ele);
gpu_print_element<<<1,1>>>(list_base, ele);
cudaDeviceSynchronize();
cudaCheckErrors("cuda error!");
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
struct list_elem {
int key;
list_elem *next;
};
template <typename T>
void alloc_bytes(T &ptr, size_t num_bytes){
hipMallocManaged(&ptr, num_bytes);
}
__host__ __device__
void print_element(list_elem *list, int ele_num){
list_elem *elem = list;
for (int i = 0; i < ele_num; i++)
elem = elem->next;
printf("key = %d\n", elem->key);
}
__global__ void gpu_print_element(list_elem *list, int ele_num){
print_element(list, ele_num);
}
const int num_elem = 5;
const int ele = 3;
int main(){
list_elem *list_base, *list;
alloc_bytes(list_base, sizeof(list_elem));
list = list_base;
for (int i = 0; i < num_elem; i++){
list->key = i;
alloc_bytes(list->next, sizeof(list_elem));
list = list->next;}
print_element(list_base, ele);
gpu_print_element<<<1,1>>>(list_base, ele);
hipDeviceSynchronize();
cudaCheckErrors("cuda error!");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
// error checking macro
#define cudaCheckErrors(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
struct list_elem {
int key;
list_elem *next;
};
template <typename T>
void alloc_bytes(T &ptr, size_t num_bytes){
hipMallocManaged(&ptr, num_bytes);
}
__host__ __device__
void print_element(list_elem *list, int ele_num){
list_elem *elem = list;
for (int i = 0; i < ele_num; i++)
elem = elem->next;
printf("key = %d\n", elem->key);
}
__global__ void gpu_print_element(list_elem *list, int ele_num){
print_element(list, ele_num);
}
const int num_elem = 5;
const int ele = 3;
int main(){
list_elem *list_base, *list;
alloc_bytes(list_base, sizeof(list_elem));
list = list_base;
for (int i = 0; i < num_elem; i++){
list->key = i;
alloc_bytes(list->next, sizeof(list_elem));
list = list->next;}
print_element(list_base, ele);
gpu_print_element<<<1,1>>>(list_base, ele);
hipDeviceSynchronize();
cudaCheckErrors("cuda error!");
} | .text
.file "linked_list_solution.hip"
.globl _Z13print_elementP9list_elemi # -- Begin function _Z13print_elementP9list_elemi
.p2align 4, 0x90
.type _Z13print_elementP9list_elemi,@function
_Z13print_elementP9list_elemi: # @_Z13print_elementP9list_elemi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_2
.p2align 4, 0x90
.LBB0_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 8(%rdi), %rdi
decl %esi
jne .LBB0_1
.LBB0_2: # %._crit_edge
movl (%rdi), %esi
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z13print_elementP9list_elemi, .Lfunc_end0-_Z13print_elementP9list_elemi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__gpu_print_elementP9list_elemi # -- Begin function _Z32__device_stub__gpu_print_elementP9list_elemi
.p2align 4, 0x90
.type _Z32__device_stub__gpu_print_elementP9list_elemi,@function
_Z32__device_stub__gpu_print_elementP9list_elemi: # @_Z32__device_stub__gpu_print_elementP9list_elemi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17gpu_print_elementP9list_elemi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z32__device_stub__gpu_print_elementP9list_elemi, .Lfunc_end1-_Z32__device_stub__gpu_print_elementP9list_elemi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rbx
movl $16, %esi
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rbx
movl %ebp, (%rbx)
addq $8, %rbx
movl $16, %esi
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
incl %ebp
cmpl $5, %ebp
jne .LBB2_1
# %bb.2:
movl $3, %ecx
movq 16(%rsp), %rax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq 8(%rax), %rax
decl %ecx
jne .LBB2_3
# %bb.4: # %_Z13print_elementP9list_elemi.exit
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $3, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17gpu_print_elementP9list_elemi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.7:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $55, %r9d
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_print_elementP9list_elemi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "key = %d\n"
.size .L.str, 10
.type _Z17gpu_print_elementP9list_elemi,@object # @_Z17gpu_print_elementP9list_elemi
.section .rodata,"a",@progbits
.globl _Z17gpu_print_elementP9list_elemi
.p2align 3, 0x0
_Z17gpu_print_elementP9list_elemi:
.quad _Z32__device_stub__gpu_print_elementP9list_elemi
.size _Z17gpu_print_elementP9list_elemi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cuda error!"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mlwong/cuda-training-series/master/exercises/hw6/linked_list_solution.hip"
.size .L.str.3, 131
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.4, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17gpu_print_elementP9list_elemi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gpu_print_elementP9list_elemi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17gpu_print_elementP9list_elemi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ac8ec_00000000-6_linked_list_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "key = %d\n"
.text
.globl _Z13print_elementP9list_elemi
.type _Z13print_elementP9list_elemi, @function
_Z13print_elementP9list_elemi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %esi, %esi
jle .L4
movl $0, %eax
.L5:
movq 8(%rdi), %rdi
addl $1, %eax
cmpl %eax, %esi
jne .L5
.L4:
movl (%rdi), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13print_elementP9list_elemi, .-_Z13print_elementP9list_elemi
.globl _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
.type _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi, @function
_Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17gpu_print_elementP9list_elemi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi, .-_Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
.globl _Z17gpu_print_elementP9list_elemi
.type _Z17gpu_print_elementP9list_elemi, @function
_Z17gpu_print_elementP9list_elemi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z17gpu_print_elementP9list_elemi, .-_Z17gpu_print_elementP9list_elemi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mlwong/cuda-training-series/master/exercises/hw6/linked_list_solution.cu"
.section .rodata.str1.1
.LC2:
.string "cuda error!"
.section .rodata.str1.8
.align 8
.LC3:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC4:
.string "*** FAILED - ABORTING\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rbp
movl $0, %ebx
.L17:
movl %ebx, 0(%rbp)
leaq 8(%rbp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 8(%rbp), %rbp
addl $1, %ebx
cmpl $5, %ebx
jne .L17
movl $3, %esi
movq 8(%rsp), %rdi
call _Z13print_elementP9list_elemi
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $3, %esi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z17gpu_print_elementP9list_elemiP9list_elemi
jmp .L18
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $53
.cfi_def_cfa_offset 96
leaq .LC1(%rip), %r9
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 80
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z17gpu_print_elementP9list_elemi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17gpu_print_elementP9list_elemi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "linked_list_solution.hip"
.globl _Z13print_elementP9list_elemi # -- Begin function _Z13print_elementP9list_elemi
.p2align 4, 0x90
.type _Z13print_elementP9list_elemi,@function
_Z13print_elementP9list_elemi: # @_Z13print_elementP9list_elemi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_2
.p2align 4, 0x90
.LBB0_1: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 8(%rdi), %rdi
decl %esi
jne .LBB0_1
.LBB0_2: # %._crit_edge
movl (%rdi), %esi
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z13print_elementP9list_elemi, .Lfunc_end0-_Z13print_elementP9list_elemi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__gpu_print_elementP9list_elemi # -- Begin function _Z32__device_stub__gpu_print_elementP9list_elemi
.p2align 4, 0x90
.type _Z32__device_stub__gpu_print_elementP9list_elemi,@function
_Z32__device_stub__gpu_print_elementP9list_elemi: # @_Z32__device_stub__gpu_print_elementP9list_elemi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17gpu_print_elementP9list_elemi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z32__device_stub__gpu_print_elementP9list_elemi, .Lfunc_end1-_Z32__device_stub__gpu_print_elementP9list_elemi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rbx
movl $16, %esi
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rbx
movl %ebp, (%rbx)
addq $8, %rbx
movl $16, %esi
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
incl %ebp
cmpl $5, %ebp
jne .LBB2_1
# %bb.2:
movl $3, %ecx
movq 16(%rsp), %rax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq 8(%rax), %rax
decl %ecx
jne .LBB2_3
# %bb.4: # %_Z13print_elementP9list_elemi.exit
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl $3, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17gpu_print_elementP9list_elemi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.7:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $55, %r9d
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_print_elementP9list_elemi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "key = %d\n"
.size .L.str, 10
.type _Z17gpu_print_elementP9list_elemi,@object # @_Z17gpu_print_elementP9list_elemi
.section .rodata,"a",@progbits
.globl _Z17gpu_print_elementP9list_elemi
.p2align 3, 0x0
_Z17gpu_print_elementP9list_elemi:
.quad _Z32__device_stub__gpu_print_elementP9list_elemi
.size _Z17gpu_print_elementP9list_elemi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cuda error!"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mlwong/cuda-training-series/master/exercises/hw6/linked_list_solution.hip"
.size .L.str.3, 131
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.4, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17gpu_print_elementP9list_elemi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gpu_print_elementP9list_elemi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17gpu_print_elementP9list_elemi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
void __global__ kernel_matrix_sum(int *A, int *B, int *C, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
int idx = iy + ny * ix;
if((ix < nx) && (iy < ny)) C[idx] = A[idx] + B[idx];
} | code for sm_80
Function : _Z17kernel_matrix_sumPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
void __global__ kernel_matrix_sum(int *A, int *B, int *C, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
int idx = iy + ny * ix;
if((ix < nx) && (iy < ny)) C[idx] = A[idx] + B[idx];
} | .file "tmpxft_0001b96b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii
.type _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii, @function
_Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kernel_matrix_sumPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii, .-_Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii
.globl _Z17kernel_matrix_sumPiS_S_ii
.type _Z17kernel_matrix_sumPiS_S_ii, @function
_Z17kernel_matrix_sumPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z17kernel_matrix_sumPiS_S_ii, .-_Z17kernel_matrix_sumPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kernel_matrix_sumPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_matrix_sumPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
void __global__ kernel_matrix_sum(int *A, int *B, int *C, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
int idx = iy + ny * ix;
if((ix < nx) && (iy < ny)) C[idx] = A[idx] + B[idx];
} | #include <hip/hip_runtime.h>
#include <stdio.h>
void __global__ kernel_matrix_sum(int *A, int *B, int *C, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
int idx = iy + ny * ix;
if((ix < nx) && (iy < ny)) C[idx] = A[idx] + B[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void __global__ kernel_matrix_sum(int *A, int *B, int *C, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
int idx = iy + ny * ix;
if((ix < nx) && (iy < ny)) C[idx] = A[idx] + B[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kernel_matrix_sumPiS_S_ii
.globl _Z17kernel_matrix_sumPiS_S_ii
.p2align 8
.type _Z17kernel_matrix_sumPiS_S_ii,@function
_Z17kernel_matrix_sumPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_matrix_sumPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kernel_matrix_sumPiS_S_ii, .Lfunc_end0-_Z17kernel_matrix_sumPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_matrix_sumPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_matrix_sumPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void __global__ kernel_matrix_sum(int *A, int *B, int *C, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
int idx = iy + ny * ix;
if((ix < nx) && (iy < ny)) C[idx] = A[idx] + B[idx];
} | .text
.file "kernel.hip"
.globl _Z32__device_stub__kernel_matrix_sumPiS_S_ii # -- Begin function _Z32__device_stub__kernel_matrix_sumPiS_S_ii
.p2align 4, 0x90
.type _Z32__device_stub__kernel_matrix_sumPiS_S_ii,@function
_Z32__device_stub__kernel_matrix_sumPiS_S_ii: # @_Z32__device_stub__kernel_matrix_sumPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kernel_matrix_sumPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__kernel_matrix_sumPiS_S_ii, .Lfunc_end0-_Z32__device_stub__kernel_matrix_sumPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_matrix_sumPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kernel_matrix_sumPiS_S_ii,@object # @_Z17kernel_matrix_sumPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z17kernel_matrix_sumPiS_S_ii
.p2align 3, 0x0
_Z17kernel_matrix_sumPiS_S_ii:
.quad _Z32__device_stub__kernel_matrix_sumPiS_S_ii
.size _Z17kernel_matrix_sumPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kernel_matrix_sumPiS_S_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kernel_matrix_sumPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kernel_matrix_sumPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17kernel_matrix_sumPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kernel_matrix_sumPiS_S_ii
.globl _Z17kernel_matrix_sumPiS_S_ii
.p2align 8
.type _Z17kernel_matrix_sumPiS_S_ii,@function
_Z17kernel_matrix_sumPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_matrix_sumPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kernel_matrix_sumPiS_S_ii, .Lfunc_end0-_Z17kernel_matrix_sumPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_matrix_sumPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_matrix_sumPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b96b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii
.type _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii, @function
_Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17kernel_matrix_sumPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii, .-_Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii
.globl _Z17kernel_matrix_sumPiS_S_ii
.type _Z17kernel_matrix_sumPiS_S_ii, @function
_Z17kernel_matrix_sumPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17kernel_matrix_sumPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z17kernel_matrix_sumPiS_S_ii, .-_Z17kernel_matrix_sumPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kernel_matrix_sumPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_matrix_sumPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z32__device_stub__kernel_matrix_sumPiS_S_ii # -- Begin function _Z32__device_stub__kernel_matrix_sumPiS_S_ii
.p2align 4, 0x90
.type _Z32__device_stub__kernel_matrix_sumPiS_S_ii,@function
_Z32__device_stub__kernel_matrix_sumPiS_S_ii: # @_Z32__device_stub__kernel_matrix_sumPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17kernel_matrix_sumPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__kernel_matrix_sumPiS_S_ii, .Lfunc_end0-_Z32__device_stub__kernel_matrix_sumPiS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_matrix_sumPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kernel_matrix_sumPiS_S_ii,@object # @_Z17kernel_matrix_sumPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z17kernel_matrix_sumPiS_S_ii
.p2align 3, 0x0
_Z17kernel_matrix_sumPiS_S_ii:
.quad _Z32__device_stub__kernel_matrix_sumPiS_S_ii
.size _Z17kernel_matrix_sumPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kernel_matrix_sumPiS_S_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kernel_matrix_sumPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kernel_matrix_sumPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void VectorAdd(int* A, int* B, int* C, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx > N )
return;
C[idx] = A[idx] + B[idx];
}
void GenerateData(int* data, int N)
{
for(int i = 0; i< N; ++i)
(*(data+i)) = i;
}
void VectorAddOnDevice(int N)
{
int* HA = (int*)malloc(sizeof(int) * N);
int* HB = (int*)malloc(sizeof(int) * N);
int* HC = (int*)malloc(sizeof(int) * N);
GenerateData(HA, N);
GenerateData(HB, N);
int nBytes = N * sizeof(int);
int* DA;
int* DB;
int* DC;
cudaMalloc((int**)&DA, nBytes);
cudaMalloc((int**)&DB, nBytes);
cudaMalloc((int**)&DC, nBytes);
cudaMemcpy(DA, HA,nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(DB, HB,nBytes, cudaMemcpyHostToDevice);
dim3 block(32);
dim3 grid((N + block.x -1) / block.x);
VectorAdd<<<grid, block>>>(DA, DB,DC,N);
cudaMemcpy(HC, DC, nBytes, cudaMemcpyDeviceToHost);
for(int i = 0; i < N;++i)
printf("%d ", HC[i]);
printf("\n");
cudaFree(DA);
cudaFree(DB);
cudaFree(DC);
free(HA);
free(HB);
free(HC);
} | code for sm_80
Function : _Z9VectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void VectorAdd(int* A, int* B, int* C, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx > N )
return;
C[idx] = A[idx] + B[idx];
}
void GenerateData(int* data, int N)
{
for(int i = 0; i< N; ++i)
(*(data+i)) = i;
}
void VectorAddOnDevice(int N)
{
int* HA = (int*)malloc(sizeof(int) * N);
int* HB = (int*)malloc(sizeof(int) * N);
int* HC = (int*)malloc(sizeof(int) * N);
GenerateData(HA, N);
GenerateData(HB, N);
int nBytes = N * sizeof(int);
int* DA;
int* DB;
int* DC;
cudaMalloc((int**)&DA, nBytes);
cudaMalloc((int**)&DB, nBytes);
cudaMalloc((int**)&DC, nBytes);
cudaMemcpy(DA, HA,nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(DB, HB,nBytes, cudaMemcpyHostToDevice);
dim3 block(32);
dim3 grid((N + block.x -1) / block.x);
VectorAdd<<<grid, block>>>(DA, DB,DC,N);
cudaMemcpy(HC, DC, nBytes, cudaMemcpyDeviceToHost);
for(int i = 0; i < N;++i)
printf("%d ", HC[i]);
printf("\n");
cudaFree(DA);
cudaFree(DB);
cudaFree(DC);
free(HA);
free(HB);
free(HC);
} | .file "tmpxft_0012e0ad_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12GenerateDataPii
.type _Z12GenerateDataPii, @function
_Z12GenerateDataPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12GenerateDataPii, .-_Z12GenerateDataPii
.globl _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.globl _Z9VectorAddPiS_S_i
.type _Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z17VectorAddOnDevicei
.type _Z17VectorAddOnDevicei, @function
_Z17VectorAddOnDevicei:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %esi
movq %r14, %rdi
call _Z12GenerateDataPii
movl %ebx, %esi
movq %r13, %rdi
call _Z12GenerateDataPii
leal 0(,%rbx,4), %r15d
movslq %r15d, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
leal 31(%rbx), %eax
shrl $5, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L17
movq %r12, %rbx
addq %r12, %rbp
leaq .LC0(%rip), %r15
.L18:
movl (%rbx), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
.L17:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z17VectorAddOnDevicei, .-_Z17VectorAddOnDevicei
.section .rodata.str1.1
.LC2:
.string "_Z9VectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void VectorAdd(int* A, int* B, int* C, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx > N )
return;
C[idx] = A[idx] + B[idx];
}
void GenerateData(int* data, int N)
{
for(int i = 0; i< N; ++i)
(*(data+i)) = i;
}
void VectorAddOnDevice(int N)
{
int* HA = (int*)malloc(sizeof(int) * N);
int* HB = (int*)malloc(sizeof(int) * N);
int* HC = (int*)malloc(sizeof(int) * N);
GenerateData(HA, N);
GenerateData(HB, N);
int nBytes = N * sizeof(int);
int* DA;
int* DB;
int* DC;
cudaMalloc((int**)&DA, nBytes);
cudaMalloc((int**)&DB, nBytes);
cudaMalloc((int**)&DC, nBytes);
cudaMemcpy(DA, HA,nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(DB, HB,nBytes, cudaMemcpyHostToDevice);
dim3 block(32);
dim3 grid((N + block.x -1) / block.x);
VectorAdd<<<grid, block>>>(DA, DB,DC,N);
cudaMemcpy(HC, DC, nBytes, cudaMemcpyDeviceToHost);
for(int i = 0; i < N;++i)
printf("%d ", HC[i]);
printf("\n");
cudaFree(DA);
cudaFree(DB);
cudaFree(DC);
free(HA);
free(HB);
free(HC);
} | #include <hip/hip_runtime.h>
void VectorAddOnDevice(int N = 1024);
void GenerateData(int* data, int N); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void VectorAddOnDevice(int N = 1024);
void GenerateData(int* data, int N); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void VectorAddOnDevice(int N = 1024);
void GenerateData(int* data, int N); | .text
.file "vectorAdd.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9VectorAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012e0ad_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12GenerateDataPii
.type _Z12GenerateDataPii, @function
_Z12GenerateDataPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12GenerateDataPii, .-_Z12GenerateDataPii
.globl _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.globl _Z9VectorAddPiS_S_i
.type _Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z17VectorAddOnDevicei
.type _Z17VectorAddOnDevicei, @function
_Z17VectorAddOnDevicei:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %esi
movq %r14, %rdi
call _Z12GenerateDataPii
movl %ebx, %esi
movq %r13, %rdi
call _Z12GenerateDataPii
leal 0(,%rbx,4), %r15d
movslq %r15d, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
leal 31(%rbx), %eax
shrl $5, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L17
movq %r12, %rbx
addq %r12, %rbp
leaq .LC0(%rip), %r15
.L18:
movl (%rbx), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
.L17:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z17VectorAddOnDevicei, .-_Z17VectorAddOnDevicei
.section .rodata.str1.1
.LC2:
.string "_Z9VectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <iterator>
#include <algorithm>
#include <assert.h>
#include <cstdlib>
//#include <time.h>
using namespace std;
int vertex_num;
int edge_num;
string fn;
float const PAGERANK_COEFFICIENT = 0.85f;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "Error: %s\nFile %s, line %d\n", cudaGetErrorString(code), file, line);
exit(code);
}
}
__host__
void Graphpreproc(
string const filename,
vector<int> &vertex_begin,
int* edge)
{
ifstream in_f;
vector<int> t;
vector<int>::iterator itr;
int count = 0;
int e = 0;
in_f.open(filename.c_str(), ios::in);
string line;
char delim[3] = " \t"; //In most benchmarks, the delimiter is usually the space character or the tab character.
char* pch;
// Read the input graph line-by-line.
while( !in_f.eof()) {
getline(in_f, line);
if( line[0] < '0' || line[0] > '9' ) // Skipping any line blank or starting with a character rather than a number.
continue;
char cstrLine[256];
strcpy( cstrLine, line.c_str() );
pch = strtok(cstrLine, delim);
if( pch != NULL )
t.push_back(atoi(pch));
else
continue;
pch = strtok( NULL, delim );
if( pch != NULL )
edge[e++] = atoi(pch);
else
continue;
}
itr = t.begin();
vertex_begin.push_back(0);
for (int i = 0; i < vertex_num - 1; i++){
while ((itr != t.end()) && (*itr == i)){
count++;
itr++;
}
count += vertex_begin.at(i);
vertex_begin.push_back(count);
count = 0;
}
vertex_begin.push_back(edge_num);
}
__host__
void greedy_ord(
int* edge,
int* trans)
{
bool* vis = new bool[vertex_num];
memset(vis, false, sizeof(bool)*vertex_num);
int curr_pos = 0;
for(int e = 0; e < edge_num; e++){
if(!vis[edge[e]]){
vis[edge[e]] = true;
trans[edge[e]] = curr_pos;
edge[e] = curr_pos++;
}
else
edge[e] = trans[edge[e]];
}
}
/*__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[vertex_begin[i] + 32*j + tid%degree]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}*/
__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
const int* const edge,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[edge[vertex_begin[i] + 32*j + tid%degree]]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}
int main(int argc, const char * argv[])
{
if(argc < 4){
cout << "parameter should be three!";
return 0;
}
fn = argv[1];
vertex_num = atoi(argv[2]);
edge_num = atoi(argv[3]);
vector<int> vertex_begin;
vertex_begin.reserve(vertex_num + 1);
int* edge = new int[edge_num];
Graphpreproc(fn, vertex_begin, edge);
int* trans = new int[vertex_num];
greedy_ord(edge, trans);
int * dev_vertex_begin;
int * dev_edge;
float * dev_values;
float * dev_tmp;
size_t memSize_R = (vertex_num + 1) * sizeof(int);
size_t memSize_C = edge_num * sizeof(int);
gpuErrchk(cudaMalloc(&dev_vertex_begin, memSize_R));
gpuErrchk(cudaMemcpy(dev_vertex_begin, vertex_begin.data(), memSize_R, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&dev_edge, memSize_C));
gpuErrchk(cudaMemcpy(dev_edge, edge, memSize_C, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&dev_values, memSize_C));
gpuErrchk(cudaMemset(dev_values, 0.0, memSize_C));
gpuErrchk(cudaMalloc(&dev_tmp, memSize_R));
gpuErrchk(cudaMemset(dev_tmp, 0.0, memSize_R));
int bn = 256;
int tn = 128;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
kernel_vertex<<<tn,bn>>>(
vertex_num,
dev_vertex_begin,
dev_edge,
dev_values,
dev_tmp);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float time;
cudaEventElapsedTime(&time,start,stop);
printf("time is %f\n",time);
gpuErrchk(cudaFree(dev_values));
gpuErrchk(cudaFree(dev_edge));
gpuErrchk(cudaFree(dev_vertex_begin));
gpuErrchk(cudaFree(dev_tmp));
delete []edge;
delete []trans;
return 0;
} | code for sm_80
Function : _Z13kernel_vertexiPKiS0_PfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fe200078e02ff */
/*0040*/ SHF.R.U32.HI R3, RZ, 0x5, R2 ; /* 0x00000005ff037819 */
/* 0x002fc80000011602 */
/*0050*/ LEA.HI R6, R0, R3, RZ, 0x1b ; /* 0x0000000300067211 */
/* 0x000fc800078fd8ff */
/*0060*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*0090*/ LOP3.LUT R0, R2, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02007812 */
/* 0x000fe200078ec0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a24 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x002fc800078e00ff */
/*00d0*/ IMAD.WIDE R2, R6, R13, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e020d */
/*00e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ea2000c1e1900 */
/*0100*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0110*/ BSSY B0, 0x990 ; /* 0x0000087000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.IADD R9, R4, 0x1, -R9 ; /* 0x0000000104097824 */
/* 0x004fca00078e0a09 */
/*0130*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 BRA 0x980 ; /* 0x0000083000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GE.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe20003f06270 */
/*0160*/ BSSY B1, 0x7c0 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0170*/ SHF.R.S32.HI R11, RZ, 0x1f, R6 ; /* 0x0000001fff0b7819 */
/* 0x000fd60000011406 */
/*0180*/ @P0 BRA 0x7b0 ; /* 0x0000062000000947 */
/* 0x000fea0003800000 */
/*0190*/ IABS R15, R9.reuse ; /* 0x00000009000f7213 */
/* 0x080fe20000000000 */
/*01a0*/ BSSY B2, 0x5e0 ; /* 0x0000043000027945 */
/* 0x000fe20003800000 */
/*01b0*/ IABS R12, R9 ; /* 0x00000009000c7213 */
/* 0x000fe20000000000 */
/*01c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*01d0*/ I2F.RP R8, R15 ; /* 0x0000000f00087306 */
/* 0x000e220000209400 */
/*01e0*/ ISETP.GE.U32.AND P3, PT, R9.reuse, 0x60, PT ; /* 0x000000600900780c */
/* 0x040fe40003f66070 */
/*01f0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f26270 */
/*0200*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f45270 */
/*0210*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R4, R8, 0xffffffe, RZ ; /* 0x0ffffffe08047810 */
/* 0x001fe20007ffe0ff */
/*0230*/ IMAD.MOV R8, RZ, RZ, -R12 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0a0c */
/*0240*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0260*/ IMAD.MOV R10, RZ, RZ, -R5 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a05 */
/*0270*/ IMAD R17, R10, R15, RZ ; /* 0x0000000f0a117224 */
/* 0x000fe200078e02ff */
/*0280*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fc60000000000 */
/*0290*/ IMAD.HI.U32 R5, R5, R17, R4 ; /* 0x0000001105057227 */
/* 0x000fe200078e0004 */
/*02a0*/ LEA R4, P4, R6, c[0x0][0x180], 0x2 ; /* 0x0000600006047a11 */
/* 0x000fca00078810ff */
/*02b0*/ IMAD.HI.U32 R5, R5, R10, RZ ; /* 0x0000000a05057227 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD R10, R5, R8, R10 ; /* 0x00000008050a7224 */
/* 0x000fe200078e020a */
/*02d0*/ LEA.HI R8, R9, 0x1, RZ, 0x1b ; /* 0x0000000109087811 */
/* 0x000fe400078fd8ff */
/*02e0*/ LEA.HI.X R5, R6, c[0x0][0x184], R11, 0x2, P4 ; /* 0x0000610006057a11 */
/* 0x000fe400020f140b */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R15, R10, PT ; /* 0x0000000a0f00720c */
/* 0x000fe40003f04070 */
/*0300*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fd600078ec0ff */
/*0310*/ @!P0 IMAD.IADD R10, R10, 0x1, -R15 ; /* 0x000000010a0a8824 */
/* 0x000fca00078e0a0f */
/*0320*/ ISETP.GT.U32.AND P0, PT, R15, R10, PT ; /* 0x0000000a0f00720c */
/* 0x000fda0003f04070 */
/*0330*/ @!P0 IMAD.IADD R10, R10, 0x1, -R15 ; /* 0x000000010a0a8824 */
/* 0x000fe200078e0a0f */
/*0340*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f05270 */
/*0350*/ @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0a0a */
/*0360*/ @!P2 LOP3.LUT R10, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff0aa212 */
/* 0x000fe200078e33ff */
/*0370*/ @!P3 BRA 0x5d0 ; /* 0x000002500000b947 */
/* 0x000fea0003800000 */
/*0380*/ LEA.HI R15, R9, -R8, RZ, 0x1b ; /* 0x80000008090f7211 */
/* 0x000fe200078fd8ff */
/*0390*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*03a0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*03b0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ IMAD.IADD R16, R17, 0x1, R12 ; /* 0x0000000111107824 */
/* 0x004fc800078e020c */
/*03d0*/ IMAD.WIDE R16, R16, R13, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fcc00078e020d */
/*03e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IMAD.WIDE R18, R16, R13, c[0x0][0x178] ; /* 0x00005e0010127625 */
/* 0x005fcc00078e020d */
/*0400*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea2000c1e1900 */
/*0410*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0420*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R19 ; /* 0x000000130400798e */
/* 0x0041e8000c10e784 */
/*0430*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ea4000c1e1900 */
/*0440*/ IADD3 R20, R12, 0x20, R21 ; /* 0x000000200c147810 */
/* 0x004fca0007ffe015 */
/*0450*/ IMAD.WIDE R20, R20, R13, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fcc00078e020d */
/*0460*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD.WIDE R22, R20, R13, c[0x0][0x178] ; /* 0x00005e0014167625 */
/* 0x004fcc00078e020d */
/*0480*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ea8000c1e1900 */
/*0490*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R23 ; /* 0x000000170400798e */
/* 0x0043e8000c10e784 */
/*04a0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea4000c1e1900 */
/*04b0*/ IADD3 R16, R12, 0x40, R17 ; /* 0x000000400c107810 */
/* 0x004fca0007ffe011 */
/*04c0*/ IMAD.WIDE R16, R16, R13, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fcc00078e020d */
/*04d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000e24000c1e1900 */
/*04e0*/ IMAD.WIDE R18, R16, R13, c[0x0][0x178] ; /* 0x00005e0010127625 */
/* 0x001fcc00078e020d */
/*04f0*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea8000c1e1900 */
/*0500*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R19 ; /* 0x000000130400798e */
/* 0x0041e8000c10e784 */
/*0510*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IADD3 R20, R12, 0x60, R21 ; /* 0x000000600c147810 */
/* 0x004fca0007ffe015 */
/*0530*/ IMAD.WIDE R20, R20, R13, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fcc00078e020d */
/*0540*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000e62000c1e1900 */
/*0550*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.NE.AND P1, PT, R15, -0x1, PT ; /* 0xffffffff0f00780c */
/* 0x000fe20003f25270 */
/*0570*/ IMAD.WIDE R22, R20, R13, c[0x0][0x178] ; /* 0x00005e0014167625 */
/* 0x002fcc00078e020d */
/*0580*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R12, R12, 0x80, RZ ; /* 0x000000800c0c7810 */
/* 0x000fe20007ffe0ff */
/*05b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R23 ; /* 0x000000170400798e */
/* 0x0041e4000c10e784 */
/*05c0*/ @P1 BRA 0x3b0 ; /* 0xfffffde000001947 */
/* 0x000fea000383ffff */
/*05d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05e0*/ @!P0 BRA 0x7b0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*0600*/ IMAD R15, R14, 0x20, R15 ; /* 0x000000200e0f7824 */
/* 0x004fc800078e020f */
/*0610*/ IMAD.IADD R16, R10, 0x1, R15 ; /* 0x000000010a107824 */
/* 0x000fc800078e020f */
/*0620*/ IMAD.WIDE R16, R16, R13, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fcc00078e020d */
/*0630*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f05270 */
/*0650*/ IMAD.WIDE R18, R16, R13, c[0x0][0x178] ; /* 0x00005e0010127625 */
/* 0x005fcc00078e020d */
/*0660*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea8000c1e1900 */
/*0670*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R19 ; /* 0x000000130400798e */
/* 0x0041e4000c10e784 */
/*0680*/ @!P0 BRA 0x7b0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ IMAD R15, R14, 0x20, R15 ; /* 0x000000200e0f7824 */
/* 0x004fca00078e020f */
/*06b0*/ IADD3 R16, R15, 0x20, R10 ; /* 0x000000200f107810 */
/* 0x000fca0007ffe00a */
/*06c0*/ IMAD.WIDE R16, R16, R13, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fcc00078e020d */
/*06d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f05270 */
/*06f0*/ IMAD.WIDE R18, R16, R13, c[0x0][0x178] ; /* 0x00005e0010127625 */
/* 0x005fcc00078e020d */
/*0700*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea8000c1e1900 */
/*0710*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R19 ; /* 0x000000130400798e */
/* 0x0041e4000c10e784 */
/*0720*/ @!P0 BRA 0x7b0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0740*/ IMAD R15, R14, 0x20, R3 ; /* 0x000000200e0f7824 */
/* 0x004fca00078e0203 */
/*0750*/ IADD3 R14, R15, 0x40, R10 ; /* 0x000000400f0e7810 */
/* 0x000fca0007ffe00a */
/*0760*/ IMAD.WIDE R14, R14, R13, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x000fca00078e020d */
/*0770*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ IMAD.WIDE R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x004fcc00078e020d */
/*0790*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R13 ; /* 0x0000000d0400798e */
/* 0x0043e4000c10e784 */
/*07b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07d0*/ @P0 BRA 0x980 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD.SHL.U32 R2, R6.reuse, 0x4, RZ ; /* 0x0000000406027824 */
/* 0x040fe200078e00ff */
/*07f0*/ SHF.L.U64.HI R11, R6, 0x2, R11 ; /* 0x00000002060b7819 */
/* 0x000fc8000001020b */
/*0800*/ IADD3 R4, P0, R2, c[0x0][0x180], RZ ; /* 0x0000600002047a10 */
/* 0x003fc80007f1e0ff */
/*0810*/ IADD3.X R5, R11, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000b057a10 */
/* 0x000fca00007fe4ff */
/*0820*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x000ea2000c1e1900 */
/*0830*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x000e220000201400 */
/*0840*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3f59999a ; /* 0x3f59999aff0a7424 */
/* 0x000fe200078e00ff */
/*0850*/ BSSY B1, 0x950 ; /* 0x000000f000017945 */
/* 0x000fec0003800000 */
/*0860*/ MUFU.RCP R8, R12 ; /* 0x0000000c00087308 */
/* 0x001e220000001000 */
/*0870*/ FFMA R3, R3, R10, 1 ; /* 0x3f80000003037423 */
/* 0x004fc8000000000a */
/*0880*/ FADD R13, R3, -0.85000002384185791016 ; /* 0xbf59999a030d7421 */
/* 0x000fe40000000000 */
/*0890*/ FFMA R3, -R12, R8, 1 ; /* 0x3f8000000c037423 */
/* 0x001fe40000000108 */
/*08a0*/ FCHK P0, R13, R12 ; /* 0x0000000c0d007302 */
/* 0x000e220000000000 */
/*08b0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0003e2000c101904 */
/*08c0*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fc80000000008 */
/*08d0*/ FFMA R8, R13, R3, RZ ; /* 0x000000030d087223 */
/* 0x000fc800000000ff */
/*08e0*/ FFMA R10, -R12, R8, R13 ; /* 0x000000080c0a7223 */
/* 0x000fc8000000010d */
/*08f0*/ FFMA R9, R3, R10, R8 ; /* 0x0000000a03097223 */
/* 0x000fe20000000008 */
/*0900*/ @!P0 BRA 0x940 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0910*/ MOV R4, 0x930 ; /* 0x0000093000047802 */
/* 0x002fe40000000f00 */
/*0920*/ CALL.REL.NOINC 0x9d0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0930*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0003 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*0950*/ IADD3 R2, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc80007f1e0ff */
/*0960*/ IADD3.X R3, R11, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000b037a10 */
/* 0x000fca00007fe4ff */
/*0970*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0980*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0990*/ LEA.HI R6, R7, R6, RZ, 0x1b ; /* 0x0000000607067211 */
/* 0x000fc800078fd8ff */
/*09a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*09b0*/ @!P0 BRA 0xc0 ; /* 0xfffff70000008947 */
/* 0x000fea000383ffff */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ SHF.R.U32.HI R8, RZ, 0x17, R12 ; /* 0x00000017ff087819 */
/* 0x000fe2000001160c */
/*09e0*/ BSSY B2, 0x1040 ; /* 0x0000065000027945 */
/* 0x000fe20003800000 */
/*09f0*/ SHF.R.U32.HI R3, RZ, 0x17, R13.reuse ; /* 0x00000017ff037819 */
/* 0x100fe2000001160d */
/*0a00*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0a10*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fe400078ec0ff */
/*0a20*/ LOP3.LUT R15, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030f7812 */
/* 0x000fe400078ec0ff */
/*0a30*/ IADD3 R16, R8, -0x1, RZ ; /* 0xffffffff08107810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R14, R15, -0x1, RZ ; /* 0xffffffff0f0e7810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; /* 0x000000fd1000780c */
/* 0x000fc80003f04070 */
/*0a60*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*0a70*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff058224 */
/* 0x000fe200078e00ff */
/*0a80*/ @!P0 BRA 0xc20 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0a90*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe20003f1c200 */
/*0aa0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0ab0*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe20003f3c200 */
/*0ac0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e000c */
/*0ad0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0ae0*/ @P0 BRA 0x1020 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0af0*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c809 */
/*0b00*/ @!P0 BRA 0x1000 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b10*/ FSETP.NEU.FTZ.AND P1, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f3d200 */
/*0b20*/ FSETP.NEU.FTZ.AND P2, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f5d200 */
/*0b30*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0b40*/ @!P2 BRA !P1, 0x1000 ; /* 0x000004b00000a947 */
/* 0x000fea0004800000 */
/*0b50*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0b60*/ PLOP3.LUT P1, PT, P2, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0001722572 */
/*0b70*/ @P1 BRA 0xfe0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b80*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0b90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0ba0*/ @P0 BRA 0xfb0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*0bc0*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f26270 */
/*0bd0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*0be0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x40 ; /* 0xffffffc0ff058424 */
/* 0x000fe400078e00ff */
/*0bf0*/ @!P0 FFMA R9, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003098823 */
/* 0x000fe400000000ff */
/*0c00*/ @!P1 FFMA R12, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a0c9823 */
/* 0x000fe200000000ff */
/*0c10*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ LEA R3, R8, 0xc0800000, 0x17 ; /* 0xc080000008037811 */
/* 0x000fe200078eb8ff */
/*0c30*/ BSSY B3, 0xfa0 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0c40*/ IADD3 R10, R15, -0x7f, RZ ; /* 0xffffff810f0a7810 */
/* 0x000fc60007ffe0ff */
/*0c50*/ IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0a03 */
/*0c60*/ IMAD R9, R10.reuse, -0x800000, R9 ; /* 0xff8000000a097824 */
/* 0x040fe200078e0209 */
/*0c70*/ IADD3 R10, R10, 0x7f, -R8 ; /* 0x0000007f0a0a7810 */
/* 0x000fe20007ffe808 */
/*0c80*/ MUFU.RCP R3, R12 ; /* 0x0000000c00037308 */
/* 0x000e220000001000 */
/*0c90*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fc60000010100 */
/*0ca0*/ IMAD.IADD R10, R10, 0x1, R5 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0205 */
/*0cb0*/ FFMA R16, R3, R14, 1 ; /* 0x3f80000003107423 */
/* 0x001fc8000000000e */
/*0cc0*/ FFMA R18, R3, R16, R3 ; /* 0x0000001003127223 */
/* 0x000fc80000000003 */
/*0cd0*/ FFMA R3, R9, R18, RZ ; /* 0x0000001209037223 */
/* 0x000fc800000000ff */
/*0ce0*/ FFMA R16, R14, R3, R9 ; /* 0x000000030e107223 */
/* 0x000fc80000000009 */
/*0cf0*/ FFMA R13, R18, R16, R3 ; /* 0x00000010120d7223 */
/* 0x000fc80000000003 */
/*0d00*/ FFMA R14, R14, R13, R9 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000009 */
/*0d10*/ FFMA R3, R18, R14, R13 ; /* 0x0000000e12037223 */
/* 0x000fca000000000d */
/*0d20*/ SHF.R.U32.HI R8, RZ, 0x17, R3 ; /* 0x00000017ff087819 */
/* 0x000fc80000011603 */
/*0d30*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*0d40*/ IMAD.IADD R12, R8, 0x1, R10 ; /* 0x00000001080c7824 */
/* 0x000fca00078e020a */
/*0d50*/ IADD3 R5, R12, -0x1, RZ ; /* 0xffffffff0c057810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0d70*/ @!P0 BRA 0xf80 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d80*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0d90*/ @P0 BRA 0xf50 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0da0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0db0*/ @P0 BRA 0xf90 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0dc0*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*0dd0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0de0*/ @!P0 BRA 0xf90 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0df0*/ FFMA.RZ R5, R18, R14.reuse, R13.reuse ; /* 0x0000000e12057223 */
/* 0x180fe2000000c00d */
/*0e00*/ IADD3 R10, R12, 0x20, RZ ; /* 0x000000200c0a7810 */
/* 0x000fe20007ffe0ff */
/*0e10*/ FFMA.RM R8, R18, R14.reuse, R13.reuse ; /* 0x0000000e12087223 */
/* 0x180fe2000000400d */
/*0e20*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f45270 */
/*0e30*/ LOP3.LUT R9, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05097812 */
/* 0x000fe200078ec0ff */
/*0e40*/ FFMA.RP R5, R18, R14, R13 ; /* 0x0000000e12057223 */
/* 0x000fe2000000800d */
/*0e50*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0e60*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0c */
/*0e70*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0e80*/ FSETP.NEU.FTZ.AND P0, PT, R5, R8, PT ; /* 0x000000080500720b */
/* 0x000fc40003f1d000 */
/*0e90*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0ea0*/ SEL R8, R12, RZ, P2 ; /* 0x000000ff0c087207 */
/* 0x000fe40001000000 */
/*0eb0*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0ec0*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0ed0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0ee0*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0ef0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0f00*/ LOP3.LUT R5, R5, 0x1, R10, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef80a */
/*0f10*/ LOP3.LUT R5, R5, R8, RZ, 0xc0, !PT ; /* 0x0000000805057212 */
/* 0x000fca00078ec0ff */
/*0f20*/ IMAD.IADD R10, R10, 0x1, R5 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0205 */
/*0f30*/ LOP3.LUT R3, R10, R3, RZ, 0xfc, !PT ; /* 0x000000030a037212 */
/* 0x000fe200078efcff */
/*0f40*/ BRA 0xf90 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f50*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0f60*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0f70*/ BRA 0xf90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f80*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe400078e0203 */
/*0f90*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0fa0*/ BRA 0x1030 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ LOP3.LUT R3, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c037812 */
/* 0x000fc800078e4809 */
/*0fc0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0fd0*/ BRA 0x1030 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0fe0*/ LOP3.LUT R3, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c037812 */
/* 0x000fe200078e4809 */
/*0ff0*/ BRA 0x1030 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1000*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*1010*/ BRA 0x1030 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1020*/ FADD.FTZ R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x000fe40000010000 */
/*1030*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1040*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1050*/ RET.REL.NODEC R4 0x0 ; /* 0xffffefa004007950 */
/* 0x000fea0003c3ffff */
/*1060*/ BRA 0x1060; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <iterator>
#include <algorithm>
#include <assert.h>
#include <cstdlib>
//#include <time.h>
using namespace std;
int vertex_num;
int edge_num;
string fn;
float const PAGERANK_COEFFICIENT = 0.85f;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "Error: %s\nFile %s, line %d\n", cudaGetErrorString(code), file, line);
exit(code);
}
}
__host__
void Graphpreproc(
string const filename,
vector<int> &vertex_begin,
int* edge)
{
ifstream in_f;
vector<int> t;
vector<int>::iterator itr;
int count = 0;
int e = 0;
in_f.open(filename.c_str(), ios::in);
string line;
char delim[3] = " \t"; //In most benchmarks, the delimiter is usually the space character or the tab character.
char* pch;
// Read the input graph line-by-line.
while( !in_f.eof()) {
getline(in_f, line);
if( line[0] < '0' || line[0] > '9' ) // Skipping any line blank or starting with a character rather than a number.
continue;
char cstrLine[256];
strcpy( cstrLine, line.c_str() );
pch = strtok(cstrLine, delim);
if( pch != NULL )
t.push_back(atoi(pch));
else
continue;
pch = strtok( NULL, delim );
if( pch != NULL )
edge[e++] = atoi(pch);
else
continue;
}
itr = t.begin();
vertex_begin.push_back(0);
for (int i = 0; i < vertex_num - 1; i++){
while ((itr != t.end()) && (*itr == i)){
count++;
itr++;
}
count += vertex_begin.at(i);
vertex_begin.push_back(count);
count = 0;
}
vertex_begin.push_back(edge_num);
}
__host__
void greedy_ord(
int* edge,
int* trans)
{
bool* vis = new bool[vertex_num];
memset(vis, false, sizeof(bool)*vertex_num);
int curr_pos = 0;
for(int e = 0; e < edge_num; e++){
if(!vis[edge[e]]){
vis[edge[e]] = true;
trans[edge[e]] = curr_pos;
edge[e] = curr_pos++;
}
else
edge[e] = trans[edge[e]];
}
}
/*__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[vertex_begin[i] + 32*j + tid%degree]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}*/
__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
const int* const edge,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[edge[vertex_begin[i] + 32*j + tid%degree]]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}
int main(int argc, const char * argv[])
{
if(argc < 4){
cout << "parameter should be three!";
return 0;
}
fn = argv[1];
vertex_num = atoi(argv[2]);
edge_num = atoi(argv[3]);
vector<int> vertex_begin;
vertex_begin.reserve(vertex_num + 1);
int* edge = new int[edge_num];
Graphpreproc(fn, vertex_begin, edge);
int* trans = new int[vertex_num];
greedy_ord(edge, trans);
int * dev_vertex_begin;
int * dev_edge;
float * dev_values;
float * dev_tmp;
size_t memSize_R = (vertex_num + 1) * sizeof(int);
size_t memSize_C = edge_num * sizeof(int);
gpuErrchk(cudaMalloc(&dev_vertex_begin, memSize_R));
gpuErrchk(cudaMemcpy(dev_vertex_begin, vertex_begin.data(), memSize_R, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&dev_edge, memSize_C));
gpuErrchk(cudaMemcpy(dev_edge, edge, memSize_C, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&dev_values, memSize_C));
gpuErrchk(cudaMemset(dev_values, 0.0, memSize_C));
gpuErrchk(cudaMalloc(&dev_tmp, memSize_R));
gpuErrchk(cudaMemset(dev_tmp, 0.0, memSize_R));
int bn = 256;
int tn = 128;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
kernel_vertex<<<tn,bn>>>(
vertex_num,
dev_vertex_begin,
dev_edge,
dev_values,
dev_tmp);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float time;
cudaEventElapsedTime(&time,start,stop);
printf("time is %f\n",time);
gpuErrchk(cudaFree(dev_values));
gpuErrchk(cudaFree(dev_edge));
gpuErrchk(cudaFree(dev_vertex_begin));
gpuErrchk(cudaFree(dev_tmp));
delete []edge;
delete []trans;
return 0;
} | .file "tmpxft_001001d1_00000000-6_pr_warp_ord.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4916:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4916:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %s\nFile %s, line %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4897:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
movl %edx, %r12d
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %rbp, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4897:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z10greedy_ordPiS_
.type _Z10greedy_ordPiS_, @function
_Z10greedy_ordPiS_:
.LFB4912:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movslq vertex_num(%rip), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbp
movslq vertex_num(%rip), %rdx
movq %r13, %rcx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
cmpl $0, edge_num(%rip)
jle .L9
movl $0, %eax
movl $0, %esi
jmp .L13
.L11:
movl (%r12,%rdx,4), %edx
.L12:
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpl %eax, edge_num(%rip)
jle .L9
.L13:
movslq (%rbx,%rax,4), %rdx
leaq 0(%rbp,%rdx), %rcx
cmpb $0, (%rcx)
jne .L11
movb $1, (%rcx)
movl %esi, (%r12,%rdx,4)
movl %esi, %edx
leal 1(%rsi), %esi
jmp .L12
.L9:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4912:
.size _Z10greedy_ordPiS_, .-_Z10greedy_ordPiS_
.globl _Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_
.type _Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_, @function
_Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_:
.LFB4938:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13kernel_vertexiPKiS0_PfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4938:
.size _Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_, .-_Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_
.globl _Z13kernel_vertexiPKiS0_PfS1_
.type _Z13kernel_vertexiPKiS0_PfS1_, @function
_Z13kernel_vertexiPKiS0_PfS1_:
.LFB4939:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4939:
.size _Z13kernel_vertexiPKiS0_PfS1_, .-_Z13kernel_vertexiPKiS0_PfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13kernel_vertexiPKiS0_PfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4941:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_vertexiPKiS0_PfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4941:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5277:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L29
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L29:
ret
.cfi_endproc
.LFE5277:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB5487:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L49
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L35
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L36
jmp .L43
.L49:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L50:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L38
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L42
.L35:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L43:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L36:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L50
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L40
.L38:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L40:
addq %rbp, %r15
testq %r13, %r13
je .L41
movq 16(%rbx), %rsi
subq %r13, %rsi
.L42:
movq %r13, %rdi
call _ZdlPvm@PLT
.L41:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5487:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB5597:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L68
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L54
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L55
jmp .L62
.L68:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L69:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L57
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L61
.L54:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L62:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L55:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L69
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L59
.L57:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L59:
addq %rbp, %r15
testq %r13, %r13
je .L60
movq 16(%rbx), %rsi
subq %r13, %rsi
.L61:
movq %r13, %rdi
call _ZdlPvm@PLT
.L60:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5597:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .text._ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_
.type _ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_, @function
_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_:
.LFB5479:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
je .L71
movl (%rsi), %edx
movl %edx, (%rax)
addq $4, 8(%rdi)
.L72:
movq 8(%rbx), %rax
subq $4, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movq %rsi, %rdx
movq %rax, %rsi
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L72
.cfi_endproc
.LFE5479:
.size _ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_, .-_ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)"
.text
.globl _Z12GraphpreprocNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorIiSaIiEEPi
.type _Z12GraphpreprocNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorIiSaIiEEPi, @function
_Z12GraphpreprocNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorIiSaIiEEPi:
.LFB4898:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4898
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $904, %rsp
.cfi_def_cfa_offset 960
movq %rdi, %rbx
movq %rsi, %r13
movq %rdx, %r15
movq %fs:40, %rax
movq %rax, 888(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rbp
leaq 352(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 352(%rsp)
movq $0, 568(%rsp)
movb $0, 576(%rsp)
movb $0, 577(%rsp)
movq $0, 584(%rsp)
movq $0, 592(%rsp)
movq $0, 600(%rsp)
movq $0, 608(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r14
movq %r14, 96(%rsp)
movq -24(%r14), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdi
movq %rdi, 96(%rsp,%rax)
movq $0, 104(%rsp)
movq 96(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 96(%rsp)
leaq 40(%rax), %rax
movq %rax, 352(%rsp)
leaq 112(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 112(%rsp), %rsi
leaq 352(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L124
.L116:
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L77:
movq %r14, 96(%rsp)
movq -24(%r14), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdi
movq %rdi, 96(%rsp,%rax)
movq $0, 104(%rsp)
.L78:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 352(%rsp)
leaq 352(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 888(%rsp), %rax
subq %fs:40, %rax
je .L79
call __stack_chk_fail@PLT
.L115:
endbr64
movq %rax, %rbx
jmp .L77
.L114:
endbr64
movq %rax, %rbx
jmp .L78
.L79:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L124:
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl $0, 24(%rsp)
movq (%rbx), %rsi
leaq 112(%rsp), %rdi
movl $8, %edx
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L125
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq 96(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L81
.L125:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq 96(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE4:
.L81:
leaq 80(%rsp), %rax
movq %rax, 64(%rsp)
movq $0, 72(%rsp)
movb $0, 80(%rsp)
movw $2336, 621(%rsp)
movb $0, 623(%rsp)
movl 384(%rsp), %r12d
andl $2, %r12d
jne .L82
leaq 64(%rsp), %rbp
jmp .L89
.L128:
movq 888(%rsp), %rax
subq %fs:40, %rax
jne .L126
.LEHB5:
call _ZSt16__throw_bad_castv@PLT
.L113:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L108:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 888(%rsp), %rax
subq %fs:40, %rax
je .L109
call __stack_chk_fail@PLT
.L126:
call __stack_chk_fail@PLT
.L85:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L86
.L129:
movq 64(%rsp), %rsi
movzbl (%rsi), %eax
subl $48, %eax
cmpb $9, %al
jbe .L127
.L88:
testb $2, 384(%rsp)
jne .L82
.L89:
movq 96(%rsp), %rax
movq -24(%rax), %rax
movq 336(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L128
cmpb $0, 56(%rbx)
je .L85
movzbl 67(%rbx), %edx
.L86:
movsbl %dl, %edx
leaq 96(%rsp), %rdi
movq %rbp, %rsi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L129
.L127:
leaq 624(%rsp), %rbx
movl $256, %edx
movq %rbx, %rdi
call __strcpy_chk@PLT
leaq 621(%rsp), %rsi
movq %rbx, %rdi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
je .L88
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 28(%rsp)
leaq 28(%rsp), %rsi
leaq 32(%rsp), %rdi
call _ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_
leaq 621(%rsp), %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
je .L88
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rdx
movslq %r12d, %rax
movl %edx, (%r15,%rax,4)
leal 1(%r12), %r12d
jmp .L88
.L82:
movq 32(%rsp), %r15
movl $0, 28(%rsp)
leaq 28(%rsp), %rsi
movq %r13, %rdi
call _ZNSt6vectorIiSaIiEE12emplace_backIJiEEERiDpOT_
.LEHE5:
movq %r15, %rbp
movl $0, %ebx
movl $1, %r12d
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
cmpl $1, vertex_num(%rip)
jg .L90
.L91:
movq 8(%r13), %rsi
cmpq 16(%r13), %rsi
je .L101
movl edge_num(%rip), %eax
movl %eax, (%rsi)
addq $4, 8(%r13)
.L102:
movq 64(%rsp), %rdi
leaq 80(%rsp), %rax
cmpq %rax, %rdi
je .L103
movq 80(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L103:
testq %r15, %r15
je .L104
movq 48(%rsp), %rsi
subq %r15, %rsi
movq %r15, %rdi
call _ZdlPvm@PLT
.L104:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 96(%rsp)
leaq 40(%rax), %rax
movq %rax, 352(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rdi
.LEHB6:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE6:
jmp .L106
.L131:
testb %sil, %sil
je .L97
movl %edx, 24(%rsp)
.L97:
movq 8(%r13), %rsi
movq 0(%r13), %rcx
movq %rsi, %rdx
subq %rcx, %rdx
sarq $2, %rdx
cmpq %rdx, %rbx
jnb .L130
movl 24(%rsp), %eax
addl (%rcx,%rbx,4), %eax
movl %eax, 24(%rsp)
cmpq 16(%r13), %rsi
je .L98
movl %eax, (%rsi)
addq $4, 8(%r13)
.L99:
movl $0, 24(%rsp)
addq $1, %rbx
movl vertex_num(%rip), %eax
subl $1, %eax
cmpl %ebx, %eax
jle .L91
.L90:
movq 40(%rsp), %rcx
cmpq %rbp, %rcx
je .L97
movl 24(%rsp), %edx
movq %rbp, %rax
movl $0, %esi
.L96:
movq %rax, %rbp
cmpl %ebx, (%rax)
jne .L131
addl $1, %edx
addq $4, %rax
movl %r12d, %esi
cmpq %rax, %rcx
jne .L96
movl %edx, 24(%rsp)
movq %rcx, %rbp
jmp .L97
.L130:
movq 888(%rsp), %rax
subq %fs:40, %rax
jne .L132
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
.LEHB7:
call _ZSt24__throw_out_of_range_fmtPKcz@PLT
.L132:
call __stack_chk_fail@PLT
.L98:
movq 8(%rsp), %rdx
movq %r13, %rdi
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L99
.L101:
leaq edge_num(%rip), %rdx
movq %r13, %rdi
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJRKiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.LEHE7:
jmp .L102
.L117:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L106:
leaq 216(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 112(%rsp)
leaq 168(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, 96(%rsp)
movq -24(%r14), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdi
movq %rdi, 96(%rsp,%rax)
movq $0, 104(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 352(%rsp)
leaq 352(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 888(%rsp), %rax
subq %fs:40, %rax
jne .L133
addq $904, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L108
.L109:
movq %rbx, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.LEHE8:
.L133:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4898:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4898:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4898-.LLSDATTD4898
.LLSDATTD4898:
.byte 0x1
.uleb128 .LLSDACSE4898-.LLSDACSB4898
.LLSDACSB4898:
.uleb128 .LEHB0-.LFB4898
.uleb128 .LEHE0-.LEHB0
.uleb128 .L114-.LFB4898
.uleb128 0
.uleb128 .LEHB1-.LFB4898
.uleb128 .LEHE1-.LEHB1
.uleb128 .L115-.LFB4898
.uleb128 0
.uleb128 .LEHB2-.LFB4898
.uleb128 .LEHE2-.LEHB2
.uleb128 .L116-.LFB4898
.uleb128 0
.uleb128 .LEHB3-.LFB4898
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4898
.uleb128 .LEHE4-.LEHB4
.uleb128 .L112-.LFB4898
.uleb128 0
.uleb128 .LEHB5-.LFB4898
.uleb128 .LEHE5-.LEHB5
.uleb128 .L113-.LFB4898
.uleb128 0
.uleb128 .LEHB6-.LFB4898
.uleb128 .LEHE6-.LEHB6
.uleb128 .L117-.LFB4898
.uleb128 0x1
.uleb128 .LEHB7-.LFB4898
.uleb128 .LEHE7-.LEHB7
.uleb128 .L113-.LFB4898
.uleb128 0
.uleb128 .LEHB8-.LFB4898
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE4898:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4898:
.text
.size _Z12GraphpreprocNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorIiSaIiEEPi, .-_Z12GraphpreprocNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorIiSaIiEEPi
.section .rodata.str1.1
.LC4:
.string "parameter should be three!"
.LC5:
.string "vector::reserve"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/HinPeng/SCC_on_GPU/master/pr_warp_ord.cu"
.section .rodata.str1.1
.LC7:
.string "time is %f\n"
.text
.globl main
.type main, @function
main:
.LFB4913:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4913
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L157
movq %rsi, %rbx
movq 8(%rsi), %rsi
leaq _Z2fnB5cxx11(%rip), %rdi
.LEHB9:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
.LEHE9:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, vertex_num(%rip)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, edge_num(%rip)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl vertex_num(%rip), %eax
addl $1, %eax
cltq
movabsq $2305843009213693951, %rdx
cmpq %rax, %rdx
jb .L158
testq %rax, %rax
je .L139
leaq 0(,%rax,4), %rbx
movq %rbx, %rdi
.LEHB10:
call _Znwm@PLT
.LEHE10:
jmp .L159
.L157:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB11:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE11:
jmp .L136
.L158:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L160
leaq .LC5(%rip), %rdi
.LEHB12:
call _ZSt20__throw_length_errorPKc@PLT
.L151:
endbr64
movq %rax, %rbx
jmp .L148
.L160:
call __stack_chk_fail@PLT
.L159:
movq %rax, 80(%rsp)
movq %rax, 88(%rsp)
addq %rbx, %rax
movq %rax, 96(%rsp)
.L139:
movslq edge_num(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L140
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
leaq 112(%rsp), %rdi
leaq _Z2fnB5cxx11(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1ERKS4_@PLT
jmp .L161
.L140:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L142
call __stack_chk_fail@PLT
.L142:
call __cxa_throw_bad_array_new_length@PLT
.LEHE12:
.L161:
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdi
movq %r12, %rdx
.LEHB13:
call _Z12GraphpreprocNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERSt6vectorIiSaIiEEPi
.LEHE13:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movslq vertex_num(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L143
salq $2, %rdi
.LEHB14:
call _Znam@PLT
movq %rax, %r13
movq %rax, %rsi
movq %r12, %rdi
call _Z10greedy_ordPiS_
jmp .L162
.L143:
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L145
call __stack_chk_fail@PLT
.L145:
call __cxa_throw_bad_array_new_length@PLT
.L162:
movl vertex_num(%rip), %eax
leal 1(%rax), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movslq edge_num(%rip), %rbp
salq $2, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $183, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $184, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $186, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $187, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $189, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rbp, %rdx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
movl $1, %ecx
movl $190, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $192, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rbx, %rdx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
movl $1, %ecx
movl $193, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $128, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L146
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl vertex_num(%rip), %edi
call _Z43__device_stub__Z13kernel_vertexiPKiS0_PfS1_iPKiS0_PfS1_
.L146:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $218, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $219, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $220, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $221, %edx
leaq .LC6(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
.LEHE14:
movq %r12, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L136:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L163
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L152:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L148:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L149
call __stack_chk_fail@PLT
.L149:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L163:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4913:
.section .gcc_except_table
.LLSDA4913:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4913-.LLSDACSB4913
.LLSDACSB4913:
.uleb128 .LEHB9-.LFB4913
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB4913
.uleb128 .LEHE10-.LEHB10
.uleb128 .L151-.LFB4913
.uleb128 0
.uleb128 .LEHB11-.LFB4913
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.uleb128 .LEHB12-.LFB4913
.uleb128 .LEHE12-.LEHB12
.uleb128 .L151-.LFB4913
.uleb128 0
.uleb128 .LEHB13-.LFB4913
.uleb128 .LEHE13-.LEHB13
.uleb128 .L152-.LFB4913
.uleb128 0
.uleb128 .LEHB14-.LFB4913
.uleb128 .LEHE14-.LEHB14
.uleb128 .L151-.LFB4913
.uleb128 0
.uleb128 .LEHB15-.LFB4913
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.LLSDACSE4913:
.text
.size main, .-main
.type _GLOBAL__sub_I_vertex_num, @function
_GLOBAL__sub_I_vertex_num:
.LFB5714:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16+_Z2fnB5cxx11(%rip), %rax
movq %rax, _Z2fnB5cxx11(%rip)
movq $0, 8+_Z2fnB5cxx11(%rip)
movb $0, 16+_Z2fnB5cxx11(%rip)
leaq __dso_handle(%rip), %rdx
leaq -16(%rax), %rsi
movq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED1Ev@GOTPCREL(%rip), %rdi
call __cxa_atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5714:
.size _GLOBAL__sub_I_vertex_num, .-_GLOBAL__sub_I_vertex_num
.section .init_array
.align 8
.quad _GLOBAL__sub_I_vertex_num
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl _Z2fnB5cxx11
.bss
.align 32
.type _Z2fnB5cxx11, @object
.size _Z2fnB5cxx11, 32
_Z2fnB5cxx11:
.zero 32
.globl edge_num
.align 4
.type edge_num, @object
.size edge_num, 4
edge_num:
.zero 4
.globl vertex_num
.align 4
.type vertex_num, @object
.size vertex_num, 4
vertex_num:
.zero 4
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <iterator>
#include <algorithm>
#include <assert.h>
#include <cstdlib>
//#include <time.h>
using namespace std;
int vertex_num;
int edge_num;
string fn;
float const PAGERANK_COEFFICIENT = 0.85f;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "Error: %s\nFile %s, line %d\n", cudaGetErrorString(code), file, line);
exit(code);
}
}
__host__
void Graphpreproc(
string const filename,
vector<int> &vertex_begin,
int* edge)
{
ifstream in_f;
vector<int> t;
vector<int>::iterator itr;
int count = 0;
int e = 0;
in_f.open(filename.c_str(), ios::in);
string line;
char delim[3] = " \t"; //In most benchmarks, the delimiter is usually the space character or the tab character.
char* pch;
// Read the input graph line-by-line.
while( !in_f.eof()) {
getline(in_f, line);
if( line[0] < '0' || line[0] > '9' ) // Skipping any line blank or starting with a character rather than a number.
continue;
char cstrLine[256];
strcpy( cstrLine, line.c_str() );
pch = strtok(cstrLine, delim);
if( pch != NULL )
t.push_back(atoi(pch));
else
continue;
pch = strtok( NULL, delim );
if( pch != NULL )
edge[e++] = atoi(pch);
else
continue;
}
itr = t.begin();
vertex_begin.push_back(0);
for (int i = 0; i < vertex_num - 1; i++){
while ((itr != t.end()) && (*itr == i)){
count++;
itr++;
}
count += vertex_begin.at(i);
vertex_begin.push_back(count);
count = 0;
}
vertex_begin.push_back(edge_num);
}
__host__
void greedy_ord(
int* edge,
int* trans)
{
bool* vis = new bool[vertex_num];
memset(vis, false, sizeof(bool)*vertex_num);
int curr_pos = 0;
for(int e = 0; e < edge_num; e++){
if(!vis[edge[e]]){
vis[edge[e]] = true;
trans[edge[e]] = curr_pos;
edge[e] = curr_pos++;
}
else
edge[e] = trans[edge[e]];
}
}
/*__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[vertex_begin[i] + 32*j + tid%degree]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}*/
__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
const int* const edge,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[edge[vertex_begin[i] + 32*j + tid%degree]]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}
int main(int argc, const char * argv[])
{
if(argc < 4){
cout << "parameter should be three!";
return 0;
}
fn = argv[1];
vertex_num = atoi(argv[2]);
edge_num = atoi(argv[3]);
vector<int> vertex_begin;
vertex_begin.reserve(vertex_num + 1);
int* edge = new int[edge_num];
Graphpreproc(fn, vertex_begin, edge);
int* trans = new int[vertex_num];
greedy_ord(edge, trans);
int * dev_vertex_begin;
int * dev_edge;
float * dev_values;
float * dev_tmp;
size_t memSize_R = (vertex_num + 1) * sizeof(int);
size_t memSize_C = edge_num * sizeof(int);
gpuErrchk(cudaMalloc(&dev_vertex_begin, memSize_R));
gpuErrchk(cudaMemcpy(dev_vertex_begin, vertex_begin.data(), memSize_R, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&dev_edge, memSize_C));
gpuErrchk(cudaMemcpy(dev_edge, edge, memSize_C, cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc(&dev_values, memSize_C));
gpuErrchk(cudaMemset(dev_values, 0.0, memSize_C));
gpuErrchk(cudaMalloc(&dev_tmp, memSize_R));
gpuErrchk(cudaMemset(dev_tmp, 0.0, memSize_R));
int bn = 256;
int tn = 128;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
kernel_vertex<<<tn,bn>>>(
vertex_num,
dev_vertex_begin,
dev_edge,
dev_values,
dev_tmp);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float time;
cudaEventElapsedTime(&time,start,stop);
printf("time is %f\n",time);
gpuErrchk(cudaFree(dev_values));
gpuErrchk(cudaFree(dev_edge));
gpuErrchk(cudaFree(dev_vertex_begin));
gpuErrchk(cudaFree(dev_tmp));
delete []edge;
delete []trans;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <iterator>
#include <algorithm>
#include <assert.h>
#include <cstdlib>
//#include <time.h>
using namespace std;
int vertex_num;
int edge_num;
string fn;
float const PAGERANK_COEFFICIENT = 0.85f;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "Error: %s\nFile %s, line %d\n", hipGetErrorString(code), file, line);
exit(code);
}
}
__host__
void Graphpreproc(
string const filename,
vector<int> &vertex_begin,
int* edge)
{
ifstream in_f;
vector<int> t;
vector<int>::iterator itr;
int count = 0;
int e = 0;
in_f.open(filename.c_str(), ios::in);
string line;
char delim[3] = " \t"; //In most benchmarks, the delimiter is usually the space character or the tab character.
char* pch;
// Read the input graph line-by-line.
while( !in_f.eof()) {
getline(in_f, line);
if( line[0] < '0' || line[0] > '9' ) // Skipping any line blank or starting with a character rather than a number.
continue;
char cstrLine[256];
strcpy( cstrLine, line.c_str() );
pch = strtok(cstrLine, delim);
if( pch != NULL )
t.push_back(atoi(pch));
else
continue;
pch = strtok( NULL, delim );
if( pch != NULL )
edge[e++] = atoi(pch);
else
continue;
}
itr = t.begin();
vertex_begin.push_back(0);
for (int i = 0; i < vertex_num - 1; i++){
while ((itr != t.end()) && (*itr == i)){
count++;
itr++;
}
count += vertex_begin.at(i);
vertex_begin.push_back(count);
count = 0;
}
vertex_begin.push_back(edge_num);
}
__host__
void greedy_ord(
int* edge,
int* trans)
{
bool* vis = new bool[vertex_num];
memset(vis, false, sizeof(bool)*vertex_num);
int curr_pos = 0;
for(int e = 0; e < edge_num; e++){
if(!vis[edge[e]]){
vis[edge[e]] = true;
trans[edge[e]] = curr_pos;
edge[e] = curr_pos++;
}
else
edge[e] = trans[edge[e]];
}
}
/*__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[vertex_begin[i] + 32*j + tid%degree]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}*/
__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
const int* const edge,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[edge[vertex_begin[i] + 32*j + tid%degree]]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}
int main(int argc, const char * argv[])
{
if(argc < 4){
cout << "parameter should be three!";
return 0;
}
fn = argv[1];
vertex_num = atoi(argv[2]);
edge_num = atoi(argv[3]);
vector<int> vertex_begin;
vertex_begin.reserve(vertex_num + 1);
int* edge = new int[edge_num];
Graphpreproc(fn, vertex_begin, edge);
int* trans = new int[vertex_num];
greedy_ord(edge, trans);
int * dev_vertex_begin;
int * dev_edge;
float * dev_values;
float * dev_tmp;
size_t memSize_R = (vertex_num + 1) * sizeof(int);
size_t memSize_C = edge_num * sizeof(int);
gpuErrchk(hipMalloc(&dev_vertex_begin, memSize_R));
gpuErrchk(hipMemcpy(dev_vertex_begin, vertex_begin.data(), memSize_R, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&dev_edge, memSize_C));
gpuErrchk(hipMemcpy(dev_edge, edge, memSize_C, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&dev_values, memSize_C));
gpuErrchk(hipMemset(dev_values, 0.0, memSize_C));
gpuErrchk(hipMalloc(&dev_tmp, memSize_R));
gpuErrchk(hipMemset(dev_tmp, 0.0, memSize_R));
int bn = 256;
int tn = 128;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
kernel_vertex<<<tn,bn>>>(
vertex_num,
dev_vertex_begin,
dev_edge,
dev_values,
dev_tmp);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float time;
hipEventElapsedTime(&time,start,stop);
printf("time is %f\n",time);
gpuErrchk(hipFree(dev_values));
gpuErrchk(hipFree(dev_edge));
gpuErrchk(hipFree(dev_vertex_begin));
gpuErrchk(hipFree(dev_tmp));
delete []edge;
delete []trans;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <iterator>
#include <algorithm>
#include <assert.h>
#include <cstdlib>
//#include <time.h>
using namespace std;
int vertex_num;
int edge_num;
string fn;
float const PAGERANK_COEFFICIENT = 0.85f;
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "Error: %s\nFile %s, line %d\n", hipGetErrorString(code), file, line);
exit(code);
}
}
__host__
void Graphpreproc(
string const filename,
vector<int> &vertex_begin,
int* edge)
{
ifstream in_f;
vector<int> t;
vector<int>::iterator itr;
int count = 0;
int e = 0;
in_f.open(filename.c_str(), ios::in);
string line;
char delim[3] = " \t"; //In most benchmarks, the delimiter is usually the space character or the tab character.
char* pch;
// Read the input graph line-by-line.
while( !in_f.eof()) {
getline(in_f, line);
if( line[0] < '0' || line[0] > '9' ) // Skipping any line blank or starting with a character rather than a number.
continue;
char cstrLine[256];
strcpy( cstrLine, line.c_str() );
pch = strtok(cstrLine, delim);
if( pch != NULL )
t.push_back(atoi(pch));
else
continue;
pch = strtok( NULL, delim );
if( pch != NULL )
edge[e++] = atoi(pch);
else
continue;
}
itr = t.begin();
vertex_begin.push_back(0);
for (int i = 0; i < vertex_num - 1; i++){
while ((itr != t.end()) && (*itr == i)){
count++;
itr++;
}
count += vertex_begin.at(i);
vertex_begin.push_back(count);
count = 0;
}
vertex_begin.push_back(edge_num);
}
__host__
void greedy_ord(
int* edge,
int* trans)
{
bool* vis = new bool[vertex_num];
memset(vis, false, sizeof(bool)*vertex_num);
int curr_pos = 0;
for(int e = 0; e < edge_num; e++){
if(!vis[edge[e]]){
vis[edge[e]] = true;
trans[edge[e]] = curr_pos;
edge[e] = curr_pos++;
}
else
edge[e] = trans[edge[e]];
}
}
/*__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[vertex_begin[i] + 32*j + tid%degree]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}*/
__global__ void kernel_vertex(
int const vertex_num,
const int* const vertex_begin,
const int* const edge,
float* const values,
float* const tmp)
{
int n = blockDim.x * gridDim.x/32; //total warp number
int tid = threadIdx.x % 32;
int wid = blockIdx.x * blockDim.x/32 + threadIdx.x/32;
for(int i = wid; i < vertex_num; i += n){
int degree = vertex_begin[i + 1] - vertex_begin[i];
if(degree > 0){
int loop_num = degree / 32;
if(tid < degree){
for(int j = 0; j <= loop_num; j++)
atomicAdd(&tmp[i], values[edge[vertex_begin[i] + 32*j + tid%degree]]);
}
if(tid == 0){
tmp[i] = PAGERANK_COEFFICIENT * tmp[i] + 1.0f - PAGERANK_COEFFICIENT;
values[i] = tmp[i] / degree;
}
}
}
}
int main(int argc, const char * argv[])
{
if(argc < 4){
cout << "parameter should be three!";
return 0;
}
fn = argv[1];
vertex_num = atoi(argv[2]);
edge_num = atoi(argv[3]);
vector<int> vertex_begin;
vertex_begin.reserve(vertex_num + 1);
int* edge = new int[edge_num];
Graphpreproc(fn, vertex_begin, edge);
int* trans = new int[vertex_num];
greedy_ord(edge, trans);
int * dev_vertex_begin;
int * dev_edge;
float * dev_values;
float * dev_tmp;
size_t memSize_R = (vertex_num + 1) * sizeof(int);
size_t memSize_C = edge_num * sizeof(int);
gpuErrchk(hipMalloc(&dev_vertex_begin, memSize_R));
gpuErrchk(hipMemcpy(dev_vertex_begin, vertex_begin.data(), memSize_R, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&dev_edge, memSize_C));
gpuErrchk(hipMemcpy(dev_edge, edge, memSize_C, hipMemcpyHostToDevice));
gpuErrchk(hipMalloc(&dev_values, memSize_C));
gpuErrchk(hipMemset(dev_values, 0.0, memSize_C));
gpuErrchk(hipMalloc(&dev_tmp, memSize_R));
gpuErrchk(hipMemset(dev_tmp, 0.0, memSize_R));
int bn = 256;
int tn = 128;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
kernel_vertex<<<tn,bn>>>(
vertex_num,
dev_vertex_begin,
dev_edge,
dev_values,
dev_tmp);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float time;
hipEventElapsedTime(&time,start,stop);
printf("time is %f\n",time);
gpuErrchk(hipFree(dev_values));
gpuErrchk(hipFree(dev_edge));
gpuErrchk(hipFree(dev_vertex_begin));
gpuErrchk(hipFree(dev_tmp));
delete []edge;
delete []trans;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_vertexiPKiS0_PfS1_
.globl _Z13kernel_vertexiPKiS0_PfS1_
.p2align 8
.type _Z13kernel_vertexiPKiS0_PfS1_,@function
_Z13kernel_vertexiPKiS0_PfS1_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
v_lshrrev_b32_e32 v1, 5, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s13
s_lshr_b32 s4, s15, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s4, v1
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_11
s_load_b32 s2, s[2:3], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
v_and_b32_e32 v0, 31, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e64 s0, 0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_lshr_b32 s1, s2, 5
s_mov_b32 s2, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_11
.LBB0_3:
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[7:8], v[5:6], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v11
s_cbranch_execz .LBB0_2
s_mov_b32 s13, exec_lo
v_cmpx_lt_i32_e64 v0, v11
s_cbranch_execz .LBB0_9
v_cvt_f32_u32_e32 v7, v11
v_sub_nc_u32_e32 v8, 0, v11
v_lshrrev_b32_e32 v12, 5, v11
s_mov_b32 s14, 0
s_mov_b32 s15, 0
v_rcp_iflag_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x4f7ffffe, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v7, v7
v_mul_lo_u32 v8, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v8, v7, v8
v_add_nc_u32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v7, v0, v7
v_mul_lo_u32 v7, v7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v0, v7
v_sub_nc_u32_e32 v8, v7, v11
v_cmp_ge_u32_e32 vcc_lo, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v7, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v4, vcc_lo
v_sub_nc_u32_e32 v10, v9, v11
v_cmp_ge_u32_e32 vcc_lo, v9, v11
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v13, v9, v10, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_6:
global_load_b32 v9, v[5:6], off
s_lshl_b32 s16, s15, 5
s_waitcnt vmcnt(0)
v_add3_u32 v9, v9, s16, v13
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_b32 v14, v[9:10], off
global_load_b32 v10, v[7:8], off
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v10, v14
global_atomic_cmpswap_b32 v9, v[7:8], v[9:10], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v9, v10
v_mov_b32_e32 v10, v9
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s16
v_cmp_eq_u32_e32 vcc_lo, s15, v12
s_add_i32 s15, s15, 1
s_or_b32 s14, vcc_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
v_cvt_f32_i32_e32 v8, v11
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_fma_f32 v7, v7, 0x3f59999a, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, 0xbf59999a, v7
v_div_scale_f32 v9, null, v8, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v12, vcc_lo, v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v12, v10
v_fma_f32 v13, -v9, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v13, v10
v_fma_f32 v9, -v9, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v9, v9, v10, v11
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_div_fixup_f32 v8, v9, v8, v7
global_store_b32 v[5:6], v7, off
global_store_b32 v[3:4], v8, off
s_branch .LBB0_2
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_vertexiPKiS0_PfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_vertexiPKiS0_PfS1_, .Lfunc_end0-_Z13kernel_vertexiPKiS0_PfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_vertexiPKiS0_PfS1_
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z13kernel_vertexiPKiS0_PfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <algorithm>
#include <chrono>
__global__ void add(float *x, float *y, float *z, int size)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < size; i += stride)
{
z[i] = x[i] + y[i];
}
}
cudaError_t cuda_add(float *x, float *y, float *z, int size);
int main()
{
const int N = 1 << 20;
float *x = new float[N];
float *y = new float[N];
float *z = new float[N];
std::fill_n(x, N, 1.0f);
std::fill_n(y, N, 2.0f);
cudaError_t cudaStatus = cuda_add(x, y, z, N);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "add_cuda failed!");
return 1;
}
float max_err = 0.0f;
for (int i = 0; i < N; i++)
{
max_err = std::fmax(max_err, std::fabs(z[i]-3.0f));
}
std::cout << "Max error: " << max_err << std::endl;
delete[] x;
delete[] y;
delete[] z;
}
cudaError_t cuda_add(float *x, float *y, float *z, int size)
{
float *dev_x = 0;
float *dev_y = 0;
float *dev_z = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_x, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_y, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
cudaFree(dev_y);
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_z, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(dev_x, x, size * sizeof(float), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(dev_y, y, size * sizeof(float), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
auto start = std::chrono::high_resolution_clock::now();
add<<<1, 1>>>(dev_x, dev_y, dev_z, size);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "kernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << " microseconds" << std::endl;
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(z, dev_z, size * sizeof(float), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
} | code for sm_80
Function : _Z3addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*0200*/ IMAD.WIDE R2, R0, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020b */
/*0210*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e020b */
/*0220*/ IMAD.WIDE R6, R0, R11, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e020b */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0240*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0002a2000c1e1900 */
/*0250*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.WIDE R4, R11, c[0x0][0x0], R4 ; /* 0x000000000b047a25 */
/* 0x001fc800078e0204 */
/*0290*/ IMAD.WIDE R6, R11, c[0x0][0x0], R6 ; /* 0x000000000b067a25 */
/* 0x002fc800078e0206 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*02b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*02c0*/ IMAD.WIDE R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a25 */
/* 0x001fe200078e0202 */
/*02d0*/ @P0 BRA 0x230 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*0310*/ IMAD.WIDE R6, R0, R3, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0203 */
/*0320*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x0c0fe200078e0203 */
/*0330*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R8, R0, R3, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fc800078e0203 */
/*0360*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0370*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*0380*/ IMAD.WIDE R10, R3, c[0x0][0x0], R4 ; /* 0x00000000030a7a25 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R3, c[0x0][0x0], R8 ; /* 0x00000000030e7a25 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R6, R3, c[0x0][0x0], R12 ; /* 0x0000000003067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R4, R3, c[0x0][0x0], R10 ; /* 0x0000000003047a25 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R16, R3, c[0x0][0x0], R14 ; /* 0x0000000003107a25 */
/* 0x000fc800078e020e */
/*0440*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a25 */
/* 0x001fc800078e0204 */
/*0460*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*0470*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*04b0*/ IMAD.WIDE R2, R3, c[0x0][0x0], R16 ; /* 0x0000000003027a25 */
/* 0x000fe200078e0210 */
/*04c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc40000000f00 */
/*04d0*/ LEA R0, R7, R0, 0x1 ; /* 0x0000000007007211 */
/* 0x000fc800078e08ff */
/*04e0*/ LEA R0, R5, R0, 0x1 ; /* 0x0000000005007211 */
/* 0x000fc800078e08ff */
/*04f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0500*/ FADD R11, R12, R9 ; /* 0x000000090c0b7221 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003ee000c101904 */
/*0520*/ @!P0 BRA 0x300 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <algorithm>
#include <chrono>
__global__ void add(float *x, float *y, float *z, int size)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < size; i += stride)
{
z[i] = x[i] + y[i];
}
}
cudaError_t cuda_add(float *x, float *y, float *z, int size);
int main()
{
const int N = 1 << 20;
float *x = new float[N];
float *y = new float[N];
float *z = new float[N];
std::fill_n(x, N, 1.0f);
std::fill_n(y, N, 2.0f);
cudaError_t cudaStatus = cuda_add(x, y, z, N);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "add_cuda failed!");
return 1;
}
float max_err = 0.0f;
for (int i = 0; i < N; i++)
{
max_err = std::fmax(max_err, std::fabs(z[i]-3.0f));
}
std::cout << "Max error: " << max_err << std::endl;
delete[] x;
delete[] y;
delete[] z;
}
cudaError_t cuda_add(float *x, float *y, float *z, int size)
{
float *dev_x = 0;
float *dev_y = 0;
float *dev_z = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_x, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_y, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
cudaFree(dev_y);
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_z, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(dev_x, x, size * sizeof(float), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(dev_y, y, size * sizeof(float), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
auto start = std::chrono::high_resolution_clock::now();
add<<<1, 1>>>(dev_x, dev_y, dev_z, size);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "kernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << " microseconds" << std::endl;
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(z, dev_z, size * sizeof(float), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
} | .file "tmpxft_00018742_00000000-6_cuda_example1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB4051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4051:
.size _Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB4052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4052:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "kernel launch failed: %s\n"
.LC4:
.string " microseconds"
.section .rodata.str1.8
.align 8
.LC5:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z8cuda_addPfS_S_i
.type _Z8cuda_addPfS_S_i, @function
_Z8cuda_addPfS_S_i:
.LFB4023:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L29
movslq %ebp, %r15
salq $2, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L36
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbp
movl $13, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L37
cmpb $0, 56(%r12)
je .L23
movzbl 67(%r12), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
testl %ebx, %ebx
jne .L38
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L29:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L31:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L32:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L33:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L34:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L35:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
jmp .L19
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L37:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L23:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L38:
movl %ebx, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L39:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4023:
.size _Z8cuda_addPfS_S_i, .-_Z8cuda_addPfS_S_i
.section .rodata.str1.1
.LC9:
.string "add_cuda failed!"
.LC12:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB4022:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r14
leaq 4194304(%r13), %rdx
movq %r13, %rax
movss .LC7(%rip), %xmm0
.L43:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L43
leaq 4194304(%r12), %rdx
movq %r12, %rax
movss .LC8(%rip), %xmm0
.L44:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L44
movl $1048576, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z8cuda_addPfS_S_i
testl %eax, %eax
jne .L52
movq %r14, %rbx
leaq 4194304(%r14), %rbp
movl $0x00000000, 12(%rsp)
.L47:
movss (%rbx), %xmm0
subss .LC10(%rip), %xmm0
andps .LC11(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movl $0, %eax
.L42:
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L42
.cfi_endproc
.LFE4022:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z3addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353216
.align 4
.LC8:
.long 1073741824
.align 4
.LC10:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <algorithm>
#include <chrono>
__global__ void add(float *x, float *y, float *z, int size)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < size; i += stride)
{
z[i] = x[i] + y[i];
}
}
cudaError_t cuda_add(float *x, float *y, float *z, int size);
int main()
{
const int N = 1 << 20;
float *x = new float[N];
float *y = new float[N];
float *z = new float[N];
std::fill_n(x, N, 1.0f);
std::fill_n(y, N, 2.0f);
cudaError_t cudaStatus = cuda_add(x, y, z, N);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "add_cuda failed!");
return 1;
}
float max_err = 0.0f;
for (int i = 0; i < N; i++)
{
max_err = std::fmax(max_err, std::fabs(z[i]-3.0f));
}
std::cout << "Max error: " << max_err << std::endl;
delete[] x;
delete[] y;
delete[] z;
}
cudaError_t cuda_add(float *x, float *y, float *z, int size)
{
float *dev_x = 0;
float *dev_y = 0;
float *dev_z = 0;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_x, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_y, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
cudaFree(dev_y);
return cudaStatus;
}
cudaStatus = cudaMalloc((void**)&dev_z, size * sizeof(float));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(dev_x, x, size * sizeof(float), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(dev_y, y, size * sizeof(float), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
auto start = std::chrono::high_resolution_clock::now();
add<<<1, 1>>>(dev_x, dev_y, dev_z, size);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "kernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << " microseconds" << std::endl;
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaStatus = cudaMemcpy(z, dev_z, size * sizeof(float), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed!");
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
}
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
return cudaStatus;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <chrono>
__global__ void add(float *x, float *y, float *z, int size)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < size; i += stride)
{
z[i] = x[i] + y[i];
}
}
hipError_t cuda_add(float *x, float *y, float *z, int size);
int main()
{
const int N = 1 << 20;
float *x = new float[N];
float *y = new float[N];
float *z = new float[N];
std::fill_n(x, N, 1.0f);
std::fill_n(y, N, 2.0f);
hipError_t cudaStatus = cuda_add(x, y, z, N);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "add_cuda failed!");
return 1;
}
float max_err = 0.0f;
for (int i = 0; i < N; i++)
{
max_err = std::fmax(max_err, std::fabs(z[i]-3.0f));
}
std::cout << "Max error: " << max_err << std::endl;
delete[] x;
delete[] y;
delete[] z;
}
hipError_t cuda_add(float *x, float *y, float *z, int size)
{
float *dev_x = 0;
float *dev_y = 0;
float *dev_z = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_x, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_y, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
hipFree(dev_y);
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_z, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(dev_x, x, size * sizeof(float), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(dev_y, y, size * sizeof(float), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
auto start = std::chrono::high_resolution_clock::now();
add<<<1, 1>>>(dev_x, dev_y, dev_z, size);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "kernel launch failed: %s\n", hipGetErrorString(cudaStatus));
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << " microseconds" << std::endl;
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(z, dev_z, size * sizeof(float), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <chrono>
__global__ void add(float *x, float *y, float *z, int size)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < size; i += stride)
{
z[i] = x[i] + y[i];
}
}
hipError_t cuda_add(float *x, float *y, float *z, int size);
int main()
{
const int N = 1 << 20;
float *x = new float[N];
float *y = new float[N];
float *z = new float[N];
std::fill_n(x, N, 1.0f);
std::fill_n(y, N, 2.0f);
hipError_t cudaStatus = cuda_add(x, y, z, N);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "add_cuda failed!");
return 1;
}
float max_err = 0.0f;
for (int i = 0; i < N; i++)
{
max_err = std::fmax(max_err, std::fabs(z[i]-3.0f));
}
std::cout << "Max error: " << max_err << std::endl;
delete[] x;
delete[] y;
delete[] z;
}
hipError_t cuda_add(float *x, float *y, float *z, int size)
{
float *dev_x = 0;
float *dev_y = 0;
float *dev_z = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_x, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_y, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
hipFree(dev_y);
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_z, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(dev_x, x, size * sizeof(float), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(dev_y, y, size * sizeof(float), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
auto start = std::chrono::high_resolution_clock::now();
add<<<1, 1>>>(dev_x, dev_y, dev_z, size);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "kernel launch failed: %s\n", hipGetErrorString(cudaStatus));
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << " microseconds" << std::endl;
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(z, dev_z, size * sizeof(float), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_i
.globl _Z3addPfS_S_i
.p2align 8
.type _Z3addPfS_S_i,@function
_Z3addPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
s_lshl_b32 s10, s1, 2
s_mov_b32 s11, s9
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v7, v5
v_cmp_le_i32_e64 s0, s8, v0
global_store_b32 v[3:4], v5, off
s_or_b32 s11, s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_i, .Lfunc_end0-_Z3addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <chrono>
__global__ void add(float *x, float *y, float *z, int size)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = index; i < size; i += stride)
{
z[i] = x[i] + y[i];
}
}
hipError_t cuda_add(float *x, float *y, float *z, int size);
int main()
{
const int N = 1 << 20;
float *x = new float[N];
float *y = new float[N];
float *z = new float[N];
std::fill_n(x, N, 1.0f);
std::fill_n(y, N, 2.0f);
hipError_t cudaStatus = cuda_add(x, y, z, N);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "add_cuda failed!");
return 1;
}
float max_err = 0.0f;
for (int i = 0; i < N; i++)
{
max_err = std::fmax(max_err, std::fabs(z[i]-3.0f));
}
std::cout << "Max error: " << max_err << std::endl;
delete[] x;
delete[] y;
delete[] z;
}
hipError_t cuda_add(float *x, float *y, float *z, int size)
{
float *dev_x = 0;
float *dev_y = 0;
float *dev_z = 0;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_x, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_y, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
hipFree(dev_y);
return cudaStatus;
}
cudaStatus = hipMalloc((void**)&dev_z, size * sizeof(float));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(dev_x, x, size * sizeof(float), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(dev_y, y, size * sizeof(float), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
auto start = std::chrono::high_resolution_clock::now();
add<<<1, 1>>>(dev_x, dev_y, dev_z, size);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "kernel launch failed: %s\n", hipGetErrorString(cudaStatus));
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipDeviceSynchronize();
auto stop = std::chrono::high_resolution_clock::now();
auto duration = std::chrono::duration_cast<std::chrono::microseconds>(stop - start);
std::cout << duration.count() << " microseconds" << std::endl;
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
cudaStatus = hipMemcpy(z, dev_z, size * sizeof(float), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed!");
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
}
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
return cudaStatus;
} | .text
.file "cuda_example1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPfS_S_i # -- Begin function _Z18__device_stub__addPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i: # @_Z18__device_stub__addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_i, .Lfunc_end0-_Z18__device_stub__addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $4, %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB1_1
# %bb.2: # %.lr.ph.i.i.i.i17.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i.i.i.i17
# =>This Inner Loop Header: Depth=1
movl $1073741824, (%r14,%rax) # imm = 0x40000000
addq $4, %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB1_3
# %bb.4: # %_ZSt6fill_nIPfifET_S1_T0_RKT1_.exit20
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1048576, %ecx # imm = 0x100000
callq _Z8cuda_addPfS_S_i
testl %eax, %eax
jne .LBB1_12
# %bb.5: # %.preheader.preheader
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_6: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_6
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, (%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps (%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_10
# %bb.9:
movzbl 67(%r12), %ecx
jmp .LBB1_11
.LBB1_10:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB1_13:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_13
.LBB1_14:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z8cuda_addPfS_S_i # -- Begin function _Z8cuda_addPfS_S_i
.p2align 4, 0x90
.type _Z8cuda_addPfS_S_i,@function
_Z8cuda_addPfS_S_i: # @_Z8cuda_addPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_1
# %bb.2:
movslq %ebp, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.5:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.10:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.12:
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.13:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17:
callq hipDeviceSynchronize
movl %eax, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r15, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.6, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB2_27
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_20
# %bb.19:
movzbl 67(%r12), %eax
jmp .LBB2_21
.LBB2_20:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %ebp, %ebp
jne .LBB2_22
# %bb.24:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.25:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB2_26
.LBB2_11:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
jmp .LBB2_9
.LBB2_1:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $63, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movl %ebx, %eax
jmp .LBB2_26
.LBB2_3:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movq 8(%rsp), %rdi
jmp .LBB2_4
.LBB2_6:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
jmp .LBB2_4
.LBB2_8:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
.LBB2_9:
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
.LBB2_4:
callq hipFree
movl %ebx, %eax
jmp .LBB2_26
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_23
.LBB2_22:
movl %ebp, %edx
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
.LBB2_23:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl %ebp, %eax
.LBB2_26:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z8cuda_addPfS_S_i, .Lfunc_end2-_Z8cuda_addPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_i,@object # @_Z3addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_i
.p2align 3, 0x0
_Z3addPfS_S_i:
.quad _Z18__device_stub__addPfS_S_i
.size _Z3addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "add_cuda failed!"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.2, 64
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc failed!"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy failed!"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "kernel launch failed: %s\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " microseconds"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.7, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2f0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fc60000000f00 */
/*0200*/ IMAD.WIDE R2, R0, R11, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e020b */
/*0210*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e020b */
/*0220*/ IMAD.WIDE R6, R0, R11, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e020b */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0240*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0002a2000c1e1900 */
/*0250*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.WIDE R4, R11, c[0x0][0x0], R4 ; /* 0x000000000b047a25 */
/* 0x001fc800078e0204 */
/*0290*/ IMAD.WIDE R6, R11, c[0x0][0x0], R6 ; /* 0x000000000b067a25 */
/* 0x002fc800078e0206 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*02b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*02c0*/ IMAD.WIDE R2, R11, c[0x0][0x0], R2 ; /* 0x000000000b027a25 */
/* 0x001fe200078e0202 */
/*02d0*/ @P0 BRA 0x230 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*0310*/ IMAD.WIDE R6, R0, R3, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0203 */
/*0320*/ IMAD.WIDE R4, R0.reuse, R3.reuse, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x0c0fe200078e0203 */
/*0330*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R8, R0, R3, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fc800078e0203 */
/*0360*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0370*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*0380*/ IMAD.WIDE R10, R3, c[0x0][0x0], R4 ; /* 0x00000000030a7a25 */
/* 0x000fc600078e0204 */
/*0390*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R3, c[0x0][0x0], R8 ; /* 0x00000000030e7a25 */
/* 0x000fc800078e0208 */
/*03d0*/ IMAD.WIDE R6, R3, c[0x0][0x0], R12 ; /* 0x0000000003067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R4, R3, c[0x0][0x0], R10 ; /* 0x0000000003047a25 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R16, R3, c[0x0][0x0], R14 ; /* 0x0000000003107a25 */
/* 0x000fc800078e020e */
/*0440*/ IMAD.WIDE R12, R3, c[0x0][0x0], R6 ; /* 0x00000000030c7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a25 */
/* 0x001fc800078e0204 */
/*0460*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*0470*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*04b0*/ IMAD.WIDE R2, R3, c[0x0][0x0], R16 ; /* 0x0000000003027a25 */
/* 0x000fe200078e0210 */
/*04c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fc40000000f00 */
/*04d0*/ LEA R0, R7, R0, 0x1 ; /* 0x0000000007007211 */
/* 0x000fc800078e08ff */
/*04e0*/ LEA R0, R5, R0, 0x1 ; /* 0x0000000005007211 */
/* 0x000fc800078e08ff */
/*04f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0500*/ FADD R11, R12, R9 ; /* 0x000000090c0b7221 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003ee000c101904 */
/*0520*/ @!P0 BRA 0x300 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_i
.globl _Z3addPfS_S_i
.p2align 8
.type _Z3addPfS_S_i,@function
_Z3addPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
s_lshl_b32 s10, s1, 2
s_mov_b32 s11, s9
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v7, v5
v_cmp_le_i32_e64 s0, s8, v0
global_store_b32 v[3:4], v5, off
s_or_b32 s11, s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_i, .Lfunc_end0-_Z3addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00018742_00000000-6_cuda_example1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB4051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4051:
.size _Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB4052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4052:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "kernel launch failed: %s\n"
.LC4:
.string " microseconds"
.section .rodata.str1.8
.align 8
.LC5:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z8cuda_addPfS_S_i
.type _Z8cuda_addPfS_S_i, @function
_Z8cuda_addPfS_S_i:
.LFB4023:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L29
movslq %ebp, %r15
salq $2, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L33
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L34
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L36
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbp
movl $13, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L37
cmpb $0, 56(%r12)
je .L23
movzbl 67(%r12), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
testl %ebx, %ebx
jne .L38
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L39
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L29:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L31:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L32:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L33:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L34:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L35:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
jmp .L19
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L37:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L23:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L38:
movl %ebx, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L39:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4023:
.size _Z8cuda_addPfS_S_i, .-_Z8cuda_addPfS_S_i
.section .rodata.str1.1
.LC9:
.string "add_cuda failed!"
.LC12:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB4022:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r14
leaq 4194304(%r13), %rdx
movq %r13, %rax
movss .LC7(%rip), %xmm0
.L43:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L43
leaq 4194304(%r12), %rdx
movq %r12, %rax
movss .LC8(%rip), %xmm0
.L44:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L44
movl $1048576, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z8cuda_addPfS_S_i
testl %eax, %eax
jne .L52
movq %r14, %rbx
leaq 4194304(%r14), %rbp
movl $0x00000000, 12(%rsp)
.L47:
movss (%rbx), %xmm0
subss .LC10(%rip), %xmm0
andps .LC11(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movl $0, %eax
.L42:
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L42
.cfi_endproc
.LFE4022:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z3addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353216
.align 4
.LC8:
.long 1073741824
.align 4
.LC10:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_example1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPfS_S_i # -- Begin function _Z18__device_stub__addPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i: # @_Z18__device_stub__addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_i, .Lfunc_end0-_Z18__device_stub__addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $4, %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB1_1
# %bb.2: # %.lr.ph.i.i.i.i17.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i.i.i.i17
# =>This Inner Loop Header: Depth=1
movl $1073741824, (%r14,%rax) # imm = 0x40000000
addq $4, %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB1_3
# %bb.4: # %_ZSt6fill_nIPfifET_S1_T0_RKT1_.exit20
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1048576, %ecx # imm = 0x100000
callq _Z8cuda_addPfS_S_i
testl %eax, %eax
jne .LBB1_12
# %bb.5: # %.preheader.preheader
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_6: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_6
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, (%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps (%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_14
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_10
# %bb.9:
movzbl 67(%r12), %ecx
jmp .LBB1_11
.LBB1_10:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB1_13:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_13
.LBB1_14:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z8cuda_addPfS_S_i # -- Begin function _Z8cuda_addPfS_S_i
.p2align 4, 0x90
.type _Z8cuda_addPfS_S_i,@function
_Z8cuda_addPfS_S_i: # @_Z8cuda_addPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_1
# %bb.2:
movslq %ebp, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.5:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.10:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.12:
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.13:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17:
callq hipDeviceSynchronize
movl %eax, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r15, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r15
movl $.L.str.6, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB2_27
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_20
# %bb.19:
movzbl 67(%r12), %eax
jmp .LBB2_21
.LBB2_20:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %ebp, %ebp
jne .LBB2_22
# %bb.24:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.25:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB2_26
.LBB2_11:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
jmp .LBB2_9
.LBB2_1:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $63, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movl %ebx, %eax
jmp .LBB2_26
.LBB2_3:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movq 8(%rsp), %rdi
jmp .LBB2_4
.LBB2_6:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
jmp .LBB2_4
.LBB2_8:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
.LBB2_9:
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
callq fwrite@PLT
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
.LBB2_4:
callq hipFree
movl %ebx, %eax
jmp .LBB2_26
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_23
.LBB2_22:
movl %ebp, %edx
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
.LBB2_23:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl %ebp, %eax
.LBB2_26:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z8cuda_addPfS_S_i, .Lfunc_end2-_Z8cuda_addPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_i,@object # @_Z3addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_i
.p2align 3, 0x0
_Z3addPfS_S_i:
.quad _Z18__device_stub__addPfS_S_i
.size _Z3addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "add_cuda failed!"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.2, 64
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc failed!"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy failed!"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "kernel launch failed: %s\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " microseconds"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.7, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
CS 4402 Distributed and Parallel Systems
Assignment 2 Question 1: N thread blocks and N threads per thread block
Sarah Whelan 250778849
TO RUN: nvcc q1_swhela2.cu -o q1_swhela2
./q1_swhela2
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
int modBy = 103; // common prime num used for modding coefficient values during generation, multiplication, and addition
void genPolynomials(int *polyA, int *polyB, int size);
void multPolynomialsSerial(int *polyA, int *polyB, int polySize, int *product, int productSize);
__global__ void multPolynomialsParallel(int *polyA, int *polyB, int *product, int polySize, int modBy);
__global__ void sumProductsParallel(int prodSize, int threadsPerBlock, int *summedProduct, int *products, int numBlocks, int modBy);
void checkCUDAError(const char* msg);
int main() {
srand(time(NULL));
int numTerms;
// get user desired input on length of polynomials
printf("Specify the number of terms in the polynomial by specifying the exponent on base 2, UP TO 10, e.g. enter '3' if you want 2^3 terms (AKA 8 terms) per polynomial: ");
scanf("%d", &numTerms);
printf("\nYou entered '%d'.\n", numTerms);
if (numTerms > 10) {
printf("Invalid entry. The maximum number of terms is 2^10. Please enter a term less than or equal to 10 next time.");
return 1;
}
// then bitshift by input value to determine actual value of numTerms
numTerms = 1 << numTerms;
printf("Number of terms per polynomial = %d, hence each polynomial will have degree = %d.\n\n", numTerms, numTerms-1);
// use numTerms as the number of blocks per thread and the number of blocks
int threadsPerBlock = numTerms;
int blocks = numTerms;
// instantiate and allocate host memory blocks to store each polynomial of size numTerms
int *host_polyA, *host_polyB;
host_polyA = (int *) malloc(numTerms * sizeof(int));
host_polyB = (int *) malloc(numTerms * sizeof(int));
// generate random polynomials of size numTerms
printf("Generating polynomials...\n\n");
genPolynomials(host_polyA, host_polyB, numTerms);
printf("polyA:\n");
for (int i = 0; i < numTerms; i++) {
printf("%dx^%d ", host_polyA[i], i);
if (i != numTerms-1) {
printf("+ ");
}
}
printf("\n\npolyB:\n");
for (int i = 0; i < numTerms; i++) {
printf("%dx^%d ", host_polyB[i], i);
if (i != numTerms-1) {
printf("+ ");
}
}
printf("\n\n");
// determine degree of product
int degreeOfProduct = (numTerms - 1) * 2; // e.g. degree(polyA, polyB) = 3 then x^3 * x^3 = x^6 and degree = numTerms - 1
// allocate blocks of memory on the host for storing the product with size degreeOfProduct + 1 (serial)
// and numTerms*numTerms for the intermediary parallel product, as well asthe final parallel product
// two different allocations in order to verify results at the end!
int *host_product_serial, *host_product_parallel, *host_final_product;
host_product_serial = (int *) malloc((degreeOfProduct+1) * sizeof(int)); // sum of products is intrinsic
host_product_parallel = (int *) malloc(numTerms * numTerms * sizeof(int)); // because of n threads in each n thread blocks
host_final_product = (int *) malloc((degreeOfProduct+1) * sizeof(int)); // final product from parallel version once summed
// ensure all vals in host_product_parallel are 0 (this is done within the serial version so we don't need to worry about that one)
for (int i = 0; i < numTerms*numTerms; i++) {
host_product_parallel[i] = 0;
}
// ensure all vals in host_final_product are 0
for (int i = 0; i < degreeOfProduct+1; i++) {
host_final_product[i] = 0;
}
// initialize and allocate memory on the devices for storing dev_polyA, dev_polyB, and dev_product
int *dev_polyA, *dev_polyB, *dev_product;
cudaMalloc( (void **) &dev_polyA, numTerms * sizeof(int));
cudaMalloc( (void **) &dev_polyB, numTerms * sizeof(int));
cudaMalloc( (void **) &dev_product, numTerms * numTerms * sizeof(int));
// copy polynomials: host -> device (dest, src, size, direction)
cudaMemcpy(dev_polyA, host_polyA, numTerms * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_polyB, host_polyB, numTerms * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_product, host_product_parallel, numTerms * numTerms * sizeof(int), cudaMemcpyHostToDevice);
// setup kernel params & launch
dim3 dimGrid(blocks);
dim3 dimBlock(threadsPerBlock);
multPolynomialsParallel<<<dimGrid, dimBlock>>>(dev_polyA, dev_polyB, dev_product, numTerms, modBy);
cudaThreadSynchronize(); // wait for ALL threads from all blocks to complete
checkCUDAError("kernel invocation");
// copy dev_product back into host_product_parallel (dest, src, size, direction)
cudaMemcpy(host_product_parallel, dev_product, numTerms * numTerms * sizeof(int), cudaMemcpyDeviceToHost);
/* ~~~ now we need to deal with the summation of intermediary products ~~~ */
// allocate device mem for final product
int *dev_final;
cudaMalloc( (void **) &dev_final, (degreeOfProduct+1) * sizeof(int));
// copy zero'd host_final_product to dev_final and host_product_parallel to dev_product
// (dest, src, size, direction)
cudaMemcpy(dev_final, host_final_product, (degreeOfProduct+1) * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_product, host_product_parallel, numTerms * numTerms * sizeof(int), cudaMemcpyHostToDevice);
// parameters are (int prodSize, int threadsPerBlock, int *summedProduct, int *products, int numBlocks, int modBy)
sumProductsParallel<<<dimGrid, dimBlock>>>(degreeOfProduct+1, threadsPerBlock, dev_final, dev_product, blocks, modBy);
cudaThreadSynchronize(); // wait for ALL threads from all blocks to complete
checkCUDAError("kernel invocation");
// copy summation of products back to host (dest, src, size, direction)
cudaMemcpy(host_final_product, dev_final, (degreeOfProduct+1) * sizeof(int), cudaMemcpyDeviceToHost);
// multiply polynomials in serial and write to host_product_serial for verification
multPolynomialsSerial(host_polyA, host_polyB, numTerms, host_product_serial, degreeOfProduct+1);
printf("Serial result:\n");
for (int i = 0; i < degreeOfProduct+1; i++) {
printf("%dx^%d ", host_product_serial[i], i);
if (i != degreeOfProduct) {
printf("+ ");
}
}
printf("\n\nParallel result:\n");
for (int i = 0; i < degreeOfProduct+1; i++) {
printf("%dx^%d ", host_final_product[i], i);
if (i != degreeOfProduct) {
printf("+ ");
}
}
printf("\n\n");
bool allRight = 1;
for (int i = 0; i < degreeOfProduct+1; i++) {
if (host_product_serial[i] == host_final_product[i]) {
continue;
} else {
printf("Coefficients at degree %d are not equivalent: serial!=parallel (%d!=%d)\n", i, host_product_serial[i], host_final_product[i]);
allRight = 0;
}
}
if (allRight) {
printf("Verification successful. The serial and parallel polynomial multiplications produced the same result!\n\n");
} else {
printf("Looks like there were some discrepancies. Verification failed.\n\n");
}
// free host and device memory
free(host_polyA);
free(host_polyB);
free(host_product_serial);
free(host_product_parallel);
free(host_final_product);
cudaFree(dev_polyA);
cudaFree(dev_polyB);
cudaFree(dev_product);
cudaFree(dev_final);
return 0;
}
// genPolynomials takes two polynomials and their size (number of terms per polynomial),
// and generates random coefficients for each term mod p
void genPolynomials(int *polyA, int *polyB, int size) {
// coefficient generation using rand mod p where p = 103
for (int i = 0; i < size; i++) {
polyA[i] = rand() % modBy;
if (polyA[i] == 0) { // we don't want any zeros!!!
polyA[i] = 1;
}
polyB[i] = rand() % modBy;
if (polyB[i] == 0) {
polyB[i] = 1;
}
}
}
// multPolynomialsSerial takes two polynomials and their size, in addition to a memory block to place
// the sum of products into, as well as the size of the product polynomial
void multPolynomialsSerial(int *polyA, int *polyB, int polySize, int *product, int productSize) {
int degreeOfTerms;
// ensure all coefficients of product are 0
for (int i = 0; i < productSize; i++) {
product[i] = 0;
}
// calculate sum of products
for (int a = 0; a < polySize; a++) { // iterate through terms in A
for (int b = 0; b < polySize; b++) { // for each term in A, iterate through all terms in B
// add degrees (indices) to determine which index this product belongs to in the product array block
degreeOfTerms = a + b;
// add product of terms to previous sum and mod by 103
product[degreeOfTerms] = (product[degreeOfTerms] + polyA[a] * polyB[b]) % modBy;
}
}
}
// multPolynomialsParallel determines the intermediary products of the polynomial multiplication problem
__global__ void multPolynomialsParallel(int *polyA, int *polyB, int *product, int polySize, int modBy) {
int a = blockIdx.x; // all threads in the same block will access the same polyA element
int b = threadIdx.x; // but all threads will access individual polyB elements
int myIndex = blockDim.x * blockIdx.x + threadIdx.x; // where to write this thread's product
product[myIndex] = (polyA[a] * polyB[b]) % modBy;
}
// sumProductsParallel uses prodSize threads, each thread corresponding to a degree, to sum common terms and determine the actual product of polyA and polyB
__global__ void sumProductsParallel(int prodSize, int threadsPerBlock, int *summedProduct, int *products, int numBlocks, int modBy) {
int responsibleFor = blockIdx.x * blockDim.x + threadIdx.x; // used to check which threads are going to be active during this step
if (responsibleFor < prodSize) { // e.g. 1 < 7 so thread 1 is going to be in charge of summing the x^1 terms, threads >= prodSize will be inactive for remainder
for (int blockNum = 0; blockNum < numBlocks; blockNum++) { // loop through blocks
for (int indexInBlock = 0; indexInBlock < threadsPerBlock; indexInBlock++) { // loop through each index per block
int degreeOfElement = blockNum + indexInBlock; // the degree related to the coefficient stored at each products[] index is equal to the block number + the relative index in the block
if (indexInBlock == 0 && degreeOfElement > responsibleFor) {
return; // this thread is done summing its common terms
}
else if (degreeOfElement == responsibleFor) { // if this thread is responsible for the degree we just calculated
int spotInProducts = blockNum * blockDim.x + indexInBlock; // get its actual index in products[]
summedProduct[responsibleFor] = (summedProduct[responsibleFor] + products[spotInProducts]) % modBy; // and write that value into the final summedProduct[our degree]
}
}
}
}
}
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if(cudaSuccess != err)
{
fprintf(stderr, "CUDA error: %s: %s.\n", msg, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z19sumProductsParalleliiPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], !P0 ; /* 0x0000580000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff027624 */
/* 0x000fca00078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0203 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x001fc800078e00ff */
/*0100*/ IMAD.IADD R7, R5.reuse, 0x1, R4 ; /* 0x0000000105077824 */
/* 0x040fe200078e0204 */
/*0110*/ ISETP.EQ.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f22270 */
/*0120*/ ISETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f04270 */
/*0130*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x001fea0000800000 */
/*0140*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f05270 */
/*0150*/ BSSY B0, 0x340 ; /* 0x000001e000007945 */
/* 0x000fd80003800000 */
/*0160*/ @P0 BRA 0x330 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0180*/ IMAD R6, R4, c[0x0][0x0], R5 ; /* 0x0000000004067a24 */
/* 0x000fe200078e0205 */
/*0190*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000eb0000c1e1900 */
/*01a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*01b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IABS R13, c[0x0][0x17c] ; /* 0x00005f00000d7a13 */
/* 0x000fc80000000000 */
/*01d0*/ I2F.RP R10, R13 ; /* 0x0000000d000a7306 */
/* 0x000e300000209400 */
/*01e0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x001e240000001000 */
/*01f0*/ IADD3 R8, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a087810 */
/* 0x001fcc0007ffe0ff */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0210*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x001fe20000000f00 */
/*0220*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a09 */
/*0230*/ IMAD R15, R12, R13, RZ ; /* 0x0000000d0c0f7224 */
/* 0x000fc800078e02ff */
/*0240*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fc800078e0008 */
/*0250*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x004fca00078e020b */
/*0260*/ IABS R6, R11 ; /* 0x0000000b00067213 */
/* 0x000fca0000000000 */
/*0270*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0290*/ IMAD R6, R13, R9, R6 ; /* 0x000000090d067224 */
/* 0x000fca00078e0206 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R13, R6, PT ; /* 0x000000060d00720c */
/* 0x000fe40003f04070 */
/*02b0*/ ISETP.GE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f46270 */
/*02c0*/ @!P0 IMAD.IADD R6, R6, 0x1, -R13 ; /* 0x0000000106068824 */
/* 0x000fca00078e0a0d */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R13, R6, PT ; /* 0x000000060d00720c */
/* 0x000fe40003f24070 */
/*02e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fd60003f05270 */
/*02f0*/ @!P1 IADD3 R6, R6, -R13, RZ ; /* 0x8000000d06069210 */
/* 0x000fca0007ffe0ff */
/*0300*/ @!P2 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06a224 */
/* 0x000fe200078e0a06 */
/*0310*/ @!P0 LOP3.LUT R6, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff068a12 */
/* 0x000fca00078e33ff */
/*0320*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0001e4000c101904 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fda0003f06270 */
/*0360*/ @!P0 BRA 0x100 ; /* 0xfffffd9000008947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0390*/ @!P0 BRA 0xf0 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23multPolynomialsParallelPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e6e0000002100 */
/*0050*/ IMAD.WIDE R2, R9, R11, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fc800078e020b */
/*0060*/ IMAD.WIDE R4, R10, R11, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x002fe400078e020b */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0080*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IABS R13, c[0x0][0x17c] ; /* 0x00005f00000d7a13 */
/* 0x000fc80000000000 */
/*00a0*/ I2F.RP R8, R13 ; /* 0x0000000d00087306 */
/* 0x000e700000209400 */
/*00b0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*00c0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002e4000021f000 */
/*00e0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x002fe200000001ff */
/*00f0*/ IMAD.MOV R12, RZ, RZ, -R7 ; /* 0x000000ffff0c7224 */
/* 0x008fc800078e0a07 */
/*0100*/ IMAD R3, R12, R13, RZ ; /* 0x0000000d0c037224 */
/* 0x001fca00078e02ff */
/*0110*/ IMAD.HI.U32 R7, R7, R3, R6 ; /* 0x0000000307077227 */
/* 0x000fc800078e0006 */
/*0120*/ IMAD R0, R2, R5, RZ ; /* 0x0000000502007224 */
/* 0x004fca00078e02ff */
/*0130*/ IABS R2, R0 ; /* 0x0000000000027213 */
/* 0x000fe40000000000 */
/*0140*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f46270 */
/*0150*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a07 */
/*0170*/ IMAD R2, R13, R7, R2 ; /* 0x000000070d027224 */
/* 0x000fca00078e0202 */
/*0180*/ ISETP.GT.U32.AND P0, PT, R13, R2, PT ; /* 0x000000020d00720c */
/* 0x000fda0003f04070 */
/*0190*/ @!P0 IADD3 R2, R2, -R13, RZ ; /* 0x8000000d02028210 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R13, R2, PT ; /* 0x000000020d00720c */
/* 0x000fda0003f24070 */
/*01c0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R13 ; /* 0x0000000102029824 */
/* 0x000fca00078e0a0d */
/*01d0*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD R2, R9, c[0x0][0x0], R10 ; /* 0x0000000009027a24 */
/* 0x000fc800078e020a */
/*01f0*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*0200*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff058a12 */
/* 0x000fe200078e33ff */
/*0210*/ IMAD.WIDE R2, R2, R11, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e020b */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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