system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void VecAdd(float* A, float *B, float *C)
{
int idx = threadIdx.x;
C[idx] = A[idx] + B[idx];
} | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void VecAdd(float* A, float *B, float *C)
{
int idx = threadIdx.x;
C[idx] = A[idx] + B[idx];
} | .file "tmpxft_000b661b_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void VecAdd(float* A, float *B, float *C)
{
int idx = threadIdx.x;
C[idx] = A[idx] + B[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(float* A, float *B, float *C)
{
int idx = threadIdx.x;
C[idx] = A[idx] + B[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(float* A, float *B, float *C)
{
int idx = threadIdx.x;
C[idx] = A[idx] + B[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(float* A, float *B, float *C)
{
int idx = threadIdx.x;
C[idx] = A[idx] + B[idx];
} | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b661b_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Version 20180131-01: added version number.
#include <iostream>
#include <iomanip>
void SelectDevice () {
int nDevices;
int selectedDevice = 0;
cudaGetDeviceCount(&nDevices);
if (nDevices == 1) {
cudaSetDevice(selectedDevice);
} else {
std::cout << "\n=============================================\n";
std::cout << "|| ||";
std::cout << "\n|| There are " << nDevices << " CUDA compatible devices. ||\n";
std::cout << "|| ||\n";
for (int i = 0; i < nDevices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
std::cout << "||=========================================||\n";
std::cout << "|| ||\n";
std::cout << "|| Device Number: " << std::setw(25) << std::left << i <<"||\n";
std::cout << "|| Device name: " << std::setw(25) << std::left << prop.name << "||\n";
std::cout << "|| Memory Clock Rate (MHz): " << std::setw(13) << std::left << prop.memoryClockRate/1000 << "||\n";
std::cout << "|| Memory Bus Width (bits): " << std::setw(13) << std::left << prop.memoryBusWidth << "||\n";
std::cout << "|| Peak Memory Bandwidth (GB/s): " << std::setw(7) << std::left << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << " ||\n";
std::cout << "|| ||\n";
}
std::cout << "=============================================\n";
std::cout << "\nPlease enter a Device Number: ";
std::cin >> selectedDevice;
cudaSetDevice(selectedDevice);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Version 20180131-01: added version number.
#include <iostream>
#include <iomanip>
void SelectDevice () {
int nDevices;
int selectedDevice = 0;
cudaGetDeviceCount(&nDevices);
if (nDevices == 1) {
cudaSetDevice(selectedDevice);
} else {
std::cout << "\n=============================================\n";
std::cout << "|| ||";
std::cout << "\n|| There are " << nDevices << " CUDA compatible devices. ||\n";
std::cout << "|| ||\n";
for (int i = 0; i < nDevices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
std::cout << "||=========================================||\n";
std::cout << "|| ||\n";
std::cout << "|| Device Number: " << std::setw(25) << std::left << i <<"||\n";
std::cout << "|| Device name: " << std::setw(25) << std::left << prop.name << "||\n";
std::cout << "|| Memory Clock Rate (MHz): " << std::setw(13) << std::left << prop.memoryClockRate/1000 << "||\n";
std::cout << "|| Memory Bus Width (bits): " << std::setw(13) << std::left << prop.memoryBusWidth << "||\n";
std::cout << "|| Peak Memory Bandwidth (GB/s): " << std::setw(7) << std::left << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << " ||\n";
std::cout << "|| ||\n";
}
std::cout << "=============================================\n";
std::cout << "\nPlease enter a Device Number: ";
std::cin >> selectedDevice;
cudaSetDevice(selectedDevice);
}
} | .file "tmpxft_001af012_00000000-6_select_GPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n=============================================\n"
.align 8
.LC1:
.string "|| ||"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n|| There are "
.section .rodata.str1.8
.align 8
.LC3:
.string " CUDA compatible devices. ||\n"
.align 8
.LC4:
.string "|| ||\n"
.align 8
.LC5:
.string "||=========================================||\n"
.section .rodata.str1.1
.LC6:
.string "|| Device Number: "
.LC7:
.string "||\n"
.LC8:
.string "|| Device name: "
.section .rodata.str1.8
.align 8
.LC9:
.string "|| Memory Clock Rate (MHz): "
.align 8
.LC10:
.string "|| Memory Bus Width (bits): "
.align 8
.LC11:
.string "|| Peak Memory Bandwidth (GB/s): "
.section .rodata.str1.1
.LC13:
.string " ||\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "=============================================\n"
.align 8
.LC15:
.string "\nPlease enter a Device Number: "
.text
.globl _Z12SelectDevicev
.type _Z12SelectDevicev, @function
_Z12SelectDevicev:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $1, 8(%rsp)
je .L11
movl $47, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $45, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $14, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $32, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $46, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $0, 8(%rsp)
jle .L6
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC4(%rip), %r12
.L7:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $46, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $46, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $18, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $25, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC7(%rip), %r14
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $18, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $25, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $3, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $30, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $13, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movl 624(%rsp), %eax
movslq %eax, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %eax
subl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $30, %edx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $13, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movl 628(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $7, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
pxor %xmm0, %xmm0
cvtsi2sdl 624(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 628(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC12(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $4, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $46, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jg .L7
.L6:
movl $46, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $31, %edx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 12(%rsp), %edi
call cudaSetDevice@PLT
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl 12(%rsp), %edi
call cudaSetDevice@PLT
jmp .L3
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z12SelectDevicev, .-_Z12SelectDevicev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Version 20180131-01: added version number.
#include <iostream>
#include <iomanip>
void SelectDevice () {
int nDevices;
int selectedDevice = 0;
cudaGetDeviceCount(&nDevices);
if (nDevices == 1) {
cudaSetDevice(selectedDevice);
} else {
std::cout << "\n=============================================\n";
std::cout << "|| ||";
std::cout << "\n|| There are " << nDevices << " CUDA compatible devices. ||\n";
std::cout << "|| ||\n";
for (int i = 0; i < nDevices; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
std::cout << "||=========================================||\n";
std::cout << "|| ||\n";
std::cout << "|| Device Number: " << std::setw(25) << std::left << i <<"||\n";
std::cout << "|| Device name: " << std::setw(25) << std::left << prop.name << "||\n";
std::cout << "|| Memory Clock Rate (MHz): " << std::setw(13) << std::left << prop.memoryClockRate/1000 << "||\n";
std::cout << "|| Memory Bus Width (bits): " << std::setw(13) << std::left << prop.memoryBusWidth << "||\n";
std::cout << "|| Peak Memory Bandwidth (GB/s): " << std::setw(7) << std::left << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << " ||\n";
std::cout << "|| ||\n";
}
std::cout << "=============================================\n";
std::cout << "\nPlease enter a Device Number: ";
std::cin >> selectedDevice;
cudaSetDevice(selectedDevice);
}
} | // Version 20180131-01: added version number.
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
void SelectDevice () {
int nDevices;
int selectedDevice = 0;
hipGetDeviceCount(&nDevices);
if (nDevices == 1) {
hipSetDevice(selectedDevice);
} else {
std::cout << "\n=============================================\n";
std::cout << "|| ||";
std::cout << "\n|| There are " << nDevices << " CUDA compatible devices. ||\n";
std::cout << "|| ||\n";
for (int i = 0; i < nDevices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
std::cout << "||=========================================||\n";
std::cout << "|| ||\n";
std::cout << "|| Device Number: " << std::setw(25) << std::left << i <<"||\n";
std::cout << "|| Device name: " << std::setw(25) << std::left << prop.name << "||\n";
std::cout << "|| Memory Clock Rate (MHz): " << std::setw(13) << std::left << prop.memoryClockRate/1000 << "||\n";
std::cout << "|| Memory Bus Width (bits): " << std::setw(13) << std::left << prop.memoryBusWidth << "||\n";
std::cout << "|| Peak Memory Bandwidth (GB/s): " << std::setw(7) << std::left << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << " ||\n";
std::cout << "|| ||\n";
}
std::cout << "=============================================\n";
std::cout << "\nPlease enter a Device Number: ";
std::cin >> selectedDevice;
hipSetDevice(selectedDevice);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Version 20180131-01: added version number.
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
void SelectDevice () {
int nDevices;
int selectedDevice = 0;
hipGetDeviceCount(&nDevices);
if (nDevices == 1) {
hipSetDevice(selectedDevice);
} else {
std::cout << "\n=============================================\n";
std::cout << "|| ||";
std::cout << "\n|| There are " << nDevices << " CUDA compatible devices. ||\n";
std::cout << "|| ||\n";
for (int i = 0; i < nDevices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
std::cout << "||=========================================||\n";
std::cout << "|| ||\n";
std::cout << "|| Device Number: " << std::setw(25) << std::left << i <<"||\n";
std::cout << "|| Device name: " << std::setw(25) << std::left << prop.name << "||\n";
std::cout << "|| Memory Clock Rate (MHz): " << std::setw(13) << std::left << prop.memoryClockRate/1000 << "||\n";
std::cout << "|| Memory Bus Width (bits): " << std::setw(13) << std::left << prop.memoryBusWidth << "||\n";
std::cout << "|| Peak Memory Bandwidth (GB/s): " << std::setw(7) << std::left << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << " ||\n";
std::cout << "|| ||\n";
}
std::cout << "=============================================\n";
std::cout << "\nPlease enter a Device Number: ";
std::cin >> selectedDevice;
hipSetDevice(selectedDevice);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Version 20180131-01: added version number.
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
void SelectDevice () {
int nDevices;
int selectedDevice = 0;
hipGetDeviceCount(&nDevices);
if (nDevices == 1) {
hipSetDevice(selectedDevice);
} else {
std::cout << "\n=============================================\n";
std::cout << "|| ||";
std::cout << "\n|| There are " << nDevices << " CUDA compatible devices. ||\n";
std::cout << "|| ||\n";
for (int i = 0; i < nDevices; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
std::cout << "||=========================================||\n";
std::cout << "|| ||\n";
std::cout << "|| Device Number: " << std::setw(25) << std::left << i <<"||\n";
std::cout << "|| Device name: " << std::setw(25) << std::left << prop.name << "||\n";
std::cout << "|| Memory Clock Rate (MHz): " << std::setw(13) << std::left << prop.memoryClockRate/1000 << "||\n";
std::cout << "|| Memory Bus Width (bits): " << std::setw(13) << std::left << prop.memoryBusWidth << "||\n";
std::cout << "|| Peak Memory Bandwidth (GB/s): " << std::setw(7) << std::left << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << " ||\n";
std::cout << "|| ||\n";
}
std::cout << "=============================================\n";
std::cout << "\nPlease enter a Device Number: ";
std::cin >> selectedDevice;
hipSetDevice(selectedDevice);
}
} | .text
.file "select_GPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12SelectDevicev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z12SelectDevicev
.p2align 4, 0x90
.type _Z12SelectDevicev,@function
_Z12SelectDevicev: # @_Z12SelectDevicev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
cmpl $1, 8(%rsp)
je .LBB0_5
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $32, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 8(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
movl $-177, %ebp
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $25, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $25, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $13, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movslq 624(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $13, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movl 628(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $7, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
cvtsi2sdl 624(%rsp), %xmm1
movl %ecx, _ZSt4cout+24(%rax)
addsd %xmm1, %xmm1
movl 628(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
cmpl 8(%rsp), %ebx
jl .LBB0_3
.LBB0_4: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
.LBB0_5:
movl 12(%rsp), %edi
callq hipSetDevice
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12SelectDevicev, .Lfunc_end0-_Z12SelectDevicev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n=============================================\n"
.size .L.str, 48
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "|| ||"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n|| There are "
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " CUDA compatible devices. ||\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "|| ||\n"
.size .L.str.4, 47
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "||=========================================||\n"
.size .L.str.5, 47
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "|| Device Number: "
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "||\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "|| Device name: "
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "|| Memory Clock Rate (MHz): "
.size .L.str.9, 31
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "|| Memory Bus Width (bits): "
.size .L.str.10, 31
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "|| Peak Memory Bandwidth (GB/s): "
.size .L.str.11, 36
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " ||\n"
.size .L.str.12, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "=============================================\n"
.size .L.str.13, 47
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\nPlease enter a Device Number: "
.size .L.str.14, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001af012_00000000-6_select_GPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n=============================================\n"
.align 8
.LC1:
.string "|| ||"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n|| There are "
.section .rodata.str1.8
.align 8
.LC3:
.string " CUDA compatible devices. ||\n"
.align 8
.LC4:
.string "|| ||\n"
.align 8
.LC5:
.string "||=========================================||\n"
.section .rodata.str1.1
.LC6:
.string "|| Device Number: "
.LC7:
.string "||\n"
.LC8:
.string "|| Device name: "
.section .rodata.str1.8
.align 8
.LC9:
.string "|| Memory Clock Rate (MHz): "
.align 8
.LC10:
.string "|| Memory Bus Width (bits): "
.align 8
.LC11:
.string "|| Peak Memory Bandwidth (GB/s): "
.section .rodata.str1.1
.LC13:
.string " ||\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "=============================================\n"
.align 8
.LC15:
.string "\nPlease enter a Device Number: "
.text
.globl _Z12SelectDevicev
.type _Z12SelectDevicev, @function
_Z12SelectDevicev:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $1, 8(%rsp)
je .L11
movl $47, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $45, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $14, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 8(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $32, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $46, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $0, 8(%rsp)
jle .L6
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC4(%rip), %r12
.L7:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $46, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $46, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $18, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $25, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC7(%rip), %r14
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $18, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $25, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $3, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $30, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $13, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movl 624(%rsp), %eax
movslq %eax, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %eax
subl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $30, %edx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $13, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
movl 628(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $35, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rdx
movq $7, 16(%rbx,%rdx)
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andb $79, %al
orl $32, %eax
movl %eax, 24(%rdx)
pxor %xmm0, %xmm0
cvtsi2sdl 624(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 628(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC12(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $4, %edx
leaq .LC13(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $46, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jg .L7
.L6:
movl $46, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $31, %edx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 12(%rsp), %edi
call cudaSetDevice@PLT
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl 12(%rsp), %edi
call cudaSetDevice@PLT
jmp .L3
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size _Z12SelectDevicev, .-_Z12SelectDevicev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "select_GPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12SelectDevicev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z12SelectDevicev
.p2align 4, 0x90
.type _Z12SelectDevicev,@function
_Z12SelectDevicev: # @_Z12SelectDevicev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
cmpl $1, 8(%rsp)
je .LBB0_5
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $32, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 8(%rsp)
jle .LBB0_4
# %bb.2: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
movl $-177, %ebp
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $25, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $25, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $13, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movslq 624(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $13, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
movl %ecx, _ZSt4cout+24(%rax)
movl 628(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movq $7, _ZSt4cout+16(%rcx)
movq -24(%rax), %rax
movl _ZSt4cout+24(%rax), %ecx
andl %ebp, %ecx
orl $32, %ecx
cvtsi2sdl 624(%rsp), %xmm1
movl %ecx, _ZSt4cout+24(%rax)
addsd %xmm1, %xmm1
movl 628(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
cmpl 8(%rsp), %ebx
jl .LBB0_3
.LBB0_4: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
.LBB0_5:
movl 12(%rsp), %edi
callq hipSetDevice
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12SelectDevicev, .Lfunc_end0-_Z12SelectDevicev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n=============================================\n"
.size .L.str, 48
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "|| ||"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n|| There are "
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " CUDA compatible devices. ||\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "|| ||\n"
.size .L.str.4, 47
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "||=========================================||\n"
.size .L.str.5, 47
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "|| Device Number: "
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "||\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "|| Device name: "
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "|| Memory Clock Rate (MHz): "
.size .L.str.9, 31
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "|| Memory Bus Width (bits): "
.size .L.str.10, 31
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "|| Peak Memory Bandwidth (GB/s): "
.size .L.str.11, 36
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " ||\n"
.size .L.str.12, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "=============================================\n"
.size .L.str.13, 47
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\nPlease enter a Device Number: "
.size .L.str.14, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define NUM_THREADS 511
#define ITERATIONS 100000
using namespace std;
__global__ void kernel_map(int *values, int *next_values)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < NUM_THREADS)
{
next_values[tid] = values[tid] + 1;
}
} | code for sm_80
Function : _Z10kernel_mapPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x1fe, PT ; /* 0x000001fe0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define NUM_THREADS 511
#define ITERATIONS 100000
using namespace std;
__global__ void kernel_map(int *values, int *next_values)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < NUM_THREADS)
{
next_values[tid] = values[tid] + 1;
}
} | .file "tmpxft_00115b1a_00000000-6_kernel_map.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10kernel_mapPiS_PiS_
.type _Z32__device_stub__Z10kernel_mapPiS_PiS_, @function
_Z32__device_stub__Z10kernel_mapPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_mapPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10kernel_mapPiS_PiS_, .-_Z32__device_stub__Z10kernel_mapPiS_PiS_
.globl _Z10kernel_mapPiS_
.type _Z10kernel_mapPiS_, @function
_Z10kernel_mapPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10kernel_mapPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_mapPiS_, .-_Z10kernel_mapPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_mapPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_mapPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define NUM_THREADS 511
#define ITERATIONS 100000
using namespace std;
__global__ void kernel_map(int *values, int *next_values)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < NUM_THREADS)
{
next_values[tid] = values[tid] + 1;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREADS 511
#define ITERATIONS 100000
using namespace std;
__global__ void kernel_map(int *values, int *next_values)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < NUM_THREADS)
{
next_values[tid] = values[tid] + 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREADS 511
#define ITERATIONS 100000
using namespace std;
__global__ void kernel_map(int *values, int *next_values)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < NUM_THREADS)
{
next_values[tid] = values[tid] + 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_mapPiS_
.globl _Z10kernel_mapPiS_
.p2align 8
.type _Z10kernel_mapPiS_,@function
_Z10kernel_mapPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1ff, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_mapPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_mapPiS_, .Lfunc_end0-_Z10kernel_mapPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_mapPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_mapPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREADS 511
#define ITERATIONS 100000
using namespace std;
__global__ void kernel_map(int *values, int *next_values)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < NUM_THREADS)
{
next_values[tid] = values[tid] + 1;
}
} | .text
.file "kernel_map.hip"
.globl _Z25__device_stub__kernel_mapPiS_ # -- Begin function _Z25__device_stub__kernel_mapPiS_
.p2align 4, 0x90
.type _Z25__device_stub__kernel_mapPiS_,@function
_Z25__device_stub__kernel_mapPiS_: # @_Z25__device_stub__kernel_mapPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_mapPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_mapPiS_, .Lfunc_end0-_Z25__device_stub__kernel_mapPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_mapPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_mapPiS_,@object # @_Z10kernel_mapPiS_
.section .rodata,"a",@progbits
.globl _Z10kernel_mapPiS_
.p2align 3, 0x0
_Z10kernel_mapPiS_:
.quad _Z25__device_stub__kernel_mapPiS_
.size _Z10kernel_mapPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_mapPiS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_mapPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_mapPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_mapPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x1fe, PT ; /* 0x000001fe0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ IADD3 R7, R2, 0x1, RZ ; /* 0x0000000102077810 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_mapPiS_
.globl _Z10kernel_mapPiS_
.p2align 8
.type _Z10kernel_mapPiS_,@function
_Z10kernel_mapPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1ff, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_mapPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_mapPiS_, .Lfunc_end0-_Z10kernel_mapPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_mapPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_mapPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00115b1a_00000000-6_kernel_map.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10kernel_mapPiS_PiS_
.type _Z32__device_stub__Z10kernel_mapPiS_PiS_, @function
_Z32__device_stub__Z10kernel_mapPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10kernel_mapPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10kernel_mapPiS_PiS_, .-_Z32__device_stub__Z10kernel_mapPiS_PiS_
.globl _Z10kernel_mapPiS_
.type _Z10kernel_mapPiS_, @function
_Z10kernel_mapPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10kernel_mapPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_mapPiS_, .-_Z10kernel_mapPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_mapPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_mapPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_map.hip"
.globl _Z25__device_stub__kernel_mapPiS_ # -- Begin function _Z25__device_stub__kernel_mapPiS_
.p2align 4, 0x90
.type _Z25__device_stub__kernel_mapPiS_,@function
_Z25__device_stub__kernel_mapPiS_: # @_Z25__device_stub__kernel_mapPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10kernel_mapPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_mapPiS_, .Lfunc_end0-_Z25__device_stub__kernel_mapPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_mapPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_mapPiS_,@object # @_Z10kernel_mapPiS_
.section .rodata,"a",@progbits
.globl _Z10kernel_mapPiS_
.p2align 3, 0x0
_Z10kernel_mapPiS_:
.quad _Z25__device_stub__kernel_mapPiS_
.size _Z10kernel_mapPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_mapPiS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_mapPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_mapPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <cuda.h>
#define TIME 500 //# of iterations
#define BLKSIZE 24
#define DEBUG(s) {printf("peek "); printf(s); printf("\n");}
//#define DEBUG(s)
typedef unsigned long long bint;
__global__ void simulate(float *src, float* des, bint dim){
__shared__ float add[TIME+1][BLKSIZE];
//x, y location of thread - to MEM space
bint x = threadIdx.x;
bint y = threadIdx.y + blockIdx.x*blockDim.y;
bint id = threadIdx.x*(dim-2) + threadIdx.y + blockIdx.x*blockDim.y;
float v = src[id]/4;
//initialize
if (x>0){
add[x][y] = 0;
}
__syncthreads();
//load each v to up, left, right, down positions
if (x < TIME)
add[x+1][y] = v;
if (x > 0)
add[x-1][y] = v;
if (y%BLKSIZE > 0) //has sth on left
add[x][y%BLKSIZE-1] = v;
else if (y > 0)
des[id-1] = v; //global
if (y%BLKSIZE < BLKSIZE-1) //has sth on right
add[x][y%BLKSIZE+1] = v;
else if (y < dim-3)
des[id+1] = v; //global
__syncthreads();
// GMT once for all
if ((x > 0) && (y < dim-2))
des[id] += add[x][y];
}
__global__ void assembly(float *d1, float *d2, float *m, bint dim){
__shared__ float tmp[TIME+1];
bint x = threadIdx.x;
bint y = threadIdx.y;
bint id1 = threadIdx.x*(dim-2) + threadIdx.y;
bint id2 = (threadIdx.x+1)*(dim-2) - threadIdx.y - 1; //upright box
tmp[x] = d2[x]; //global load to shared
__syncthreads();
// GMT
m[y] = tmp[y];
if (y < TIME){
d1[id1] += tmp[y+1];
d1[id2] += tmp[y+1];
d2[id1] += tmp[y+1];
d2[id2] += tmp[y+1];
m[dim-2-y] = tmp[y+1];
}
}
float * config(bint dim){
//allocate on host and initialize
float *bar1 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side with 150
float *bar2 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side all 80
bint p;
for (p=0; p < dim-2; p++){
bar1[p] = 80;
bar2[p] = 80;
if ((p>=10) && (p<=30)){
bar1[p] = 150;
}
}
//config kernel
dim3 blkdim;
blkdim.x = TIME+1;
blkdim.y = BLKSIZE;
bint griddim = ceil((double)(dim-2)/BLKSIZE);
//allocate on kernel
bint mem = (dim-2)*(TIME+1)*sizeof(float);
float *src1, *des1;
cudaMalloc((void **)&src1, mem);
cudaMalloc((void **)&des1, mem);
cudaMemcpy(src1, bar1, mem, cudaMemcpyHostToDevice);
cudaMemcpy(des1, bar1, mem, cudaMemcpyHostToDevice);
float *src2, *des2;
cudaMalloc((void **)&src2, mem);
cudaMalloc((void **)&des2, mem);
cudaMemcpy(src2, bar2, mem, cudaMemcpyHostToDevice);
cudaMemcpy(des2, bar2, mem, cudaMemcpyHostToDevice);
DEBUG("loaded")
free(bar1);
free(bar2);
//launch
bint i;
for (i=0; i<TIME; i++){
if (i%2==0){
simulate<<<griddim, blkdim>>>(src1, des1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}else{
simulate<<<griddim, blkdim>>>(des1, src1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}}
// clean up
float *d1, *d2;
if (TIME%2==0){ //result in src
cudaFree(des1);
cudaFree(des2);
d1 = src1;
d2 = src2;
}
else{
cudaFree(src1);
cudaFree(src2);
d1 = des1;
d2 = des2;
}
DEBUG("simulated")
//assembly
float *mid;
cudaMalloc((void **)&mid, dim*sizeof(float)); //result for middle lines
dim3 blk;
blk.x = TIME+1;
blk.y = (TIME%32==0) ? TIME : TIME+32-TIME%32; //first 32n >= TIME
assembly<<<1, blk>>>(d1, d2, mid, dim);
DEBUG("assemblied")
/*
//cpu assembly
float *m = (float *)malloc(dim*dim*sizeof(float));
bint unit = (dim-2)*sizeof(float);
for (i=0; i<TIME+1; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d1[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d1);
//done line 0 to TIME
float *middlelines = (float *)malloc(dim*sizeof(float));
cudaMemcpy(middlelines, mid, dim*sizeof(float), cudaMemcpyDeviceToHost);
for (i=TIME+1; i<dim-1-TIME; i++){
middlelines[i] = 0; //no temperature for the middle region
}
middlelines[dim-1] = 80;
for (i=TIME+1; i<dim-1-TIME; i++){
memcpy(&m[i*dim], middlelines, dim*sizeof(float));
}
cudaFree(mid);
//done for TIME+1...dim-TIME-1
for (i=dim-1-TIME; i<dim; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d2[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d2);
//done dim-TIME-1...dim-1
return m;
*/
cudaFree(d1);
cudaFree(d2);
cudaFree(mid);
return NULL;
}
float avg(float *m, bint dim){
bint size = dim*dim;
float sum = 0;
bint i;
for (i=0; i<size; i++){
sum += m[i];
//if (i % dim==0)
// printf("\n");
//printf("%f ", m[i]);
}
//printf("\n");
return sum/size;
}
int main(int argc, char *argv[]){
//getDeviceProp();
if (argc < 2){
printf("Please indicate matrix size.\n");
exit(0);
}
bint n = atoi(argv[1]);
float *x = config(n+1);
if (x != NULL){
float mean = avg(x, n+1);
printf("peek mean: %f\n", mean);
free(x);
}
return 0;
} | code for sm_80
Function : _Z8assemblyPfS_S_y
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R11, R4, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x001fcc00078e0004 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0070*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0x1f3, PT ; /* 0x000001f30000780c */
/* 0x041fe20003f04070 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0004 */
/*0090*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x001fe200078e00ff */
/*00f0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fc400078e00ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0120*/ IADD3 R5, P0, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R2, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02027810 */
/* 0x000fe400007fe4ff */
/*0140*/ IMAD.WIDE.U32 R8, R11, R5, R6 ; /* 0x000000050b087225 */
/* 0x000fc800078e0006 */
/*0150*/ IMAD R3, R2, R11, RZ ; /* 0x0000000b02037224 */
/* 0x000fe400078e02ff */
/*0160*/ IMAD.SHL.U32 R10, R8, 0x4, RZ ; /* 0x00000004080a7824 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fc600078e0203 */
/*0180*/ IADD3 R6, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a067a10 */
/* 0x000fe40007f1e0ff */
/*0190*/ SHF.L.U64.HI R14, R8, 0x2, R3 ; /* 0x00000002080e7819 */
/* 0x000fe40000010203 */
/*01a0*/ LDS R3, [R0.X4+0x4] ; /* 0x0000040000037984 */
/* 0x000e240000004800 */
/*01b0*/ IADD3.X R7, R14, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000e077a10 */
/* 0x000fca00007fe4ff */
/*01c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000e22000c1e1900 */
/*01d0*/ LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff087212 */
/* 0x000fe200078e33ff */
/*01e0*/ IMAD.MOV.U32 R9, RZ, RZ, -0x1 ; /* 0xffffffffff097424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fca0007ffe0ff */
/*0200*/ IMAD.WIDE.U32 R8, R11, R5, R8 ; /* 0x000000050b087225 */
/* 0x000fc800078e0008 */
/*0210*/ IMAD R13, R2, R11, RZ ; /* 0x0000000b020d7224 */
/* 0x000fe400078e02ff */
/*0220*/ IMAD.SHL.U32 R12, R8, 0x4, RZ ; /* 0x00000004080c7824 */
/* 0x000fc600078e00ff */
/*0230*/ IADD3 R13, R9, R13, RZ ; /* 0x0000000d090d7210 */
/* 0x000fc80007ffe0ff */
/*0240*/ SHF.L.U64.HI R13, R8, 0x2, R13 ; /* 0x00000002080d7819 */
/* 0x000fe4000001020d */
/*0250*/ IADD3 R8, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c087a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R9, R13, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000d097a10 */
/* 0x000fe200007fe4ff */
/*0270*/ FADD R15, R4, R3 ; /* 0x00000003040f7221 */
/* 0x001fca0000000000 */
/*0280*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R10, P0, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0a7a10 */
/* 0x000fc80007f1e0ff */
/*02b0*/ IADD3.X R11, R14, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000e0b7a10 */
/* 0x000fe200007fe4ff */
/*02c0*/ FADD R17, R3, R4 ; /* 0x0000000403117221 */
/* 0x004fca0000000000 */
/*02d0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x000fe8000c101904 */
/*02e0*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IADD3 R12, P0, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0300*/ IADD3.X R13, R13, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000d0d7a10 */
/* 0x000fe200007fe4ff */
/*0310*/ FADD R19, R3, R4 ; /* 0x0000000403137221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x000fe8000c101904 */
/*0330*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x001ea2000c1e1900 */
/*0340*/ IADD3 R0, P0, -R0, R5, RZ ; /* 0x0000000500007210 */
/* 0x000fc80007f1e1ff */
/*0350*/ IADD3.X R5, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02057810 */
/* 0x000fe400007fe4ff */
/*0360*/ LEA R4, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000047a11 */
/* 0x000fc800078010ff */
/*0370*/ LEA.HI.X R5, R0, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d0000057a11 */
/* 0x000fe200000f1405 */
/*0380*/ FADD R7, R3, R6 ; /* 0x0000000603077221 */
/* 0x004fca0000000000 */
/*0390*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8simulatePfS_y
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0030*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ ULDC.64 UR10, c[0x0][0x170] ; /* 0x00005c00000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002100 */
/*0060*/ UIADD3 UR8, UP0, UR10, -0x2, URZ ; /* 0xfffffffe0a087890 */
/* 0x000fe4000ff1e03f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ UIADD3.X UR9, UR11, -0x1, URZ, UP0, !UPT ; /* 0xffffffff0b097890 */
/* 0x000fc400087fe43f */
/*0090*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc8000f8e023f */
/*00a0*/ IMAD R11, R9, UR9, RZ ; /* 0x00000009090b7c24 */
/* 0x004fe4000f8e02ff */
/*00b0*/ IADD3 R2, P0, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x002fca000ff1e0ff */
/*00c0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fc800000e06ff */
/*00d0*/ IMAD.WIDE.U32 R2, R9, UR8, R2 ; /* 0x0000000809027c25 */
/* 0x000fc8000f8e0002 */
/*00e0*/ IMAD.IADD R11, R3, 0x1, R11 ; /* 0x00000001030b7824 */
/* 0x000fe400078e020b */
/*00f0*/ IMAD.SHL.U32 R10, R2, 0x4, RZ ; /* 0x00000004020a7824 */
/* 0x000fc600078e00ff */
/*0100*/ SHF.L.U64.HI R11, R2, 0x2, R11 ; /* 0x00000002020b7819 */
/* 0x000fe4000001020b */
/*0110*/ IADD3 R4, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a047a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R5, R11, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000b057a10 */
/* 0x000fca00007fe4ff */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe0ff */
/*0150*/ BSSY B0, 0x2c0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f45270 */
/*0170*/ ISETP.GT.U32.AND P1, PT, R9, 0x1f3, PT ; /* 0x000001f30900780c */
/* 0x000fe20003f24070 */
/*0180*/ IMAD.WIDE.U32 R2, R0, -0x55555555, RZ ; /* 0xaaaaaaab00027825 */
/* 0x000fca00078e00ff */
/*0190*/ SHF.R.U32.HI R3, RZ, 0x4, R3 ; /* 0x00000004ff037819 */
/* 0x000fca0000011603 */
/*01a0*/ IMAD R8, R3, -0x18, R0 ; /* 0xffffffe803087824 */
/* 0x000fe400078e0200 */
/*01b0*/ IMAD R3, R9, 0x60, RZ ; /* 0x0000006009037824 */
/* 0x000fc600078e02ff */
/*01c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*01d0*/ IMAD R6, R0, 0x4, R3 ; /* 0x0000000400067824 */
/* 0x000fca00078e0203 */
/*01e0*/ @P2 STS [R6], RZ ; /* 0x000000ff06002388 */
/* 0x0001e80000000800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ FMUL R7, R4, 0.25 ; /* 0x3e80000004077820 */
/* 0x004fe40000400000 */
/*0210*/ IMAD R4, R8, 0x4, R3 ; /* 0x0000000408047824 */
/* 0x000fc600078e0203 */
/*0220*/ @!P1 STS [R6+0x60], R7 ; /* 0x0000600706009388 */
/* 0x0001e20000000800 */
/*0230*/ ISETP.GE.U32.AND P1, PT, R8, 0x17, PT ; /* 0x000000170800780c */
/* 0x000fc60003f26070 */
/*0240*/ @P2 STS [R6+-0x60], R7 ; /* 0xffffa00706002388 */
/* 0x0001e20000000800 */
/*0250*/ IADD3 R2, P2, R10, c[0x0][0x168], RZ ; /* 0x00005a000a027a10 */
/* 0x000fc60007f5e0ff */
/*0260*/ @P0 STS [R4+-0x4], R7 ; /* 0xfffffc0704000388 */
/* 0x0001e20000000800 */
/*0270*/ IADD3.X R3, R11, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b000b037a10 */
/* 0x000fe200017fe4ff */
/*0280*/ @P0 BRA 0x2b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*02a0*/ @P0 STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702000986 */
/* 0x0003e4000c101906 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ BSSY B0, 0x380 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02d0*/ @!P1 BRA 0x360 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*02e0*/ UIADD3 UR4, UP0, UR10, -0x3, URZ ; /* 0xfffffffd0a047890 */
/* 0x000fc8000ff1e03f */
/*02f0*/ UIADD3.X UR5, UR11, -0x1, URZ, UP0, !UPT ; /* 0xffffffff0b057890 */
/* 0x000fe400087fe43f */
/*0300*/ ISETP.LT.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf01070 */
/*0310*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x001fca000f8e00ff */
/*0320*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f04100 */
/*0330*/ @!P0 BRA 0x370 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0340*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c101906 */
/*0350*/ BRA 0x370 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0360*/ STS [R4+0x4], R7 ; /* 0x0000040704007388 */
/* 0x0005e40000000800 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.LT.U32.AND P0, PT, R0, UR8, PT ; /* 0x0000000800007c0c */
/* 0x000fe2000bf01070 */
/*03a0*/ IMAD.U32 R0, RZ, RZ, UR9 ; /* 0x00000009ff007e24 */
/* 0x000fca000f8e00ff */
/*03b0*/ ISETP.GT.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80003f04100 */
/*03c0*/ ISETP.EQ.OR P0, PT, R9, RZ, !P0 ; /* 0x000000ff0900720c */
/* 0x000fda0004702670 */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x001ee40000000800 */
/*0400*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x008fca0000000000 */
/*0410*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <cuda.h>
#define TIME 500 //# of iterations
#define BLKSIZE 24
#define DEBUG(s) {printf("peek "); printf(s); printf("\n");}
//#define DEBUG(s)
typedef unsigned long long bint;
__global__ void simulate(float *src, float* des, bint dim){
__shared__ float add[TIME+1][BLKSIZE];
//x, y location of thread - to MEM space
bint x = threadIdx.x;
bint y = threadIdx.y + blockIdx.x*blockDim.y;
bint id = threadIdx.x*(dim-2) + threadIdx.y + blockIdx.x*blockDim.y;
float v = src[id]/4;
//initialize
if (x>0){
add[x][y] = 0;
}
__syncthreads();
//load each v to up, left, right, down positions
if (x < TIME)
add[x+1][y] = v;
if (x > 0)
add[x-1][y] = v;
if (y%BLKSIZE > 0) //has sth on left
add[x][y%BLKSIZE-1] = v;
else if (y > 0)
des[id-1] = v; //global
if (y%BLKSIZE < BLKSIZE-1) //has sth on right
add[x][y%BLKSIZE+1] = v;
else if (y < dim-3)
des[id+1] = v; //global
__syncthreads();
// GMT once for all
if ((x > 0) && (y < dim-2))
des[id] += add[x][y];
}
__global__ void assembly(float *d1, float *d2, float *m, bint dim){
__shared__ float tmp[TIME+1];
bint x = threadIdx.x;
bint y = threadIdx.y;
bint id1 = threadIdx.x*(dim-2) + threadIdx.y;
bint id2 = (threadIdx.x+1)*(dim-2) - threadIdx.y - 1; //upright box
tmp[x] = d2[x]; //global load to shared
__syncthreads();
// GMT
m[y] = tmp[y];
if (y < TIME){
d1[id1] += tmp[y+1];
d1[id2] += tmp[y+1];
d2[id1] += tmp[y+1];
d2[id2] += tmp[y+1];
m[dim-2-y] = tmp[y+1];
}
}
float * config(bint dim){
//allocate on host and initialize
float *bar1 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side with 150
float *bar2 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side all 80
bint p;
for (p=0; p < dim-2; p++){
bar1[p] = 80;
bar2[p] = 80;
if ((p>=10) && (p<=30)){
bar1[p] = 150;
}
}
//config kernel
dim3 blkdim;
blkdim.x = TIME+1;
blkdim.y = BLKSIZE;
bint griddim = ceil((double)(dim-2)/BLKSIZE);
//allocate on kernel
bint mem = (dim-2)*(TIME+1)*sizeof(float);
float *src1, *des1;
cudaMalloc((void **)&src1, mem);
cudaMalloc((void **)&des1, mem);
cudaMemcpy(src1, bar1, mem, cudaMemcpyHostToDevice);
cudaMemcpy(des1, bar1, mem, cudaMemcpyHostToDevice);
float *src2, *des2;
cudaMalloc((void **)&src2, mem);
cudaMalloc((void **)&des2, mem);
cudaMemcpy(src2, bar2, mem, cudaMemcpyHostToDevice);
cudaMemcpy(des2, bar2, mem, cudaMemcpyHostToDevice);
DEBUG("loaded")
free(bar1);
free(bar2);
//launch
bint i;
for (i=0; i<TIME; i++){
if (i%2==0){
simulate<<<griddim, blkdim>>>(src1, des1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}else{
simulate<<<griddim, blkdim>>>(des1, src1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}}
// clean up
float *d1, *d2;
if (TIME%2==0){ //result in src
cudaFree(des1);
cudaFree(des2);
d1 = src1;
d2 = src2;
}
else{
cudaFree(src1);
cudaFree(src2);
d1 = des1;
d2 = des2;
}
DEBUG("simulated")
//assembly
float *mid;
cudaMalloc((void **)&mid, dim*sizeof(float)); //result for middle lines
dim3 blk;
blk.x = TIME+1;
blk.y = (TIME%32==0) ? TIME : TIME+32-TIME%32; //first 32n >= TIME
assembly<<<1, blk>>>(d1, d2, mid, dim);
DEBUG("assemblied")
/*
//cpu assembly
float *m = (float *)malloc(dim*dim*sizeof(float));
bint unit = (dim-2)*sizeof(float);
for (i=0; i<TIME+1; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d1[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d1);
//done line 0 to TIME
float *middlelines = (float *)malloc(dim*sizeof(float));
cudaMemcpy(middlelines, mid, dim*sizeof(float), cudaMemcpyDeviceToHost);
for (i=TIME+1; i<dim-1-TIME; i++){
middlelines[i] = 0; //no temperature for the middle region
}
middlelines[dim-1] = 80;
for (i=TIME+1; i<dim-1-TIME; i++){
memcpy(&m[i*dim], middlelines, dim*sizeof(float));
}
cudaFree(mid);
//done for TIME+1...dim-TIME-1
for (i=dim-1-TIME; i<dim; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d2[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d2);
//done dim-TIME-1...dim-1
return m;
*/
cudaFree(d1);
cudaFree(d2);
cudaFree(mid);
return NULL;
}
float avg(float *m, bint dim){
bint size = dim*dim;
float sum = 0;
bint i;
for (i=0; i<size; i++){
sum += m[i];
//if (i % dim==0)
// printf("\n");
//printf("%f ", m[i]);
}
//printf("\n");
return sum/size;
}
int main(int argc, char *argv[]){
//getDeviceProp();
if (argc < 2){
printf("Please indicate matrix size.\n");
exit(0);
}
bint n = atoi(argv[1]);
float *x = config(n+1);
if (x != NULL){
float mean = avg(x, n+1);
printf("peek mean: %f\n", mean);
free(x);
}
return 0;
} | .file "tmpxft_000bed7f_00000000-6_cuda-optimized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3avgPfy
.type _Z3avgPfy, @function
_Z3avgPfy:
.LFB2058:
.cfi_startproc
endbr64
imulq %rsi, %rsi
testq %rsi, %rsi
je .L8
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
pxor %xmm0, %xmm0
.L5:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L4:
testq %rsi, %rsi
js .L6
pxor %xmm1, %xmm1
cvtsi2ssq %rsi, %xmm1
.L7:
divss %xmm1, %xmm0
ret
.L8:
pxor %xmm0, %xmm0
jmp .L4
.L6:
movq %rsi, %rax
shrq %rax
andl $1, %esi
orq %rsi, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z3avgPfy, .-_Z3avgPfy
.globl _Z30__device_stub__Z8simulatePfS_yPfS_y
.type _Z30__device_stub__Z8simulatePfS_yPfS_y, @function
_Z30__device_stub__Z8simulatePfS_yPfS_y:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8simulatePfS_y(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z8simulatePfS_yPfS_y, .-_Z30__device_stub__Z8simulatePfS_yPfS_y
.globl _Z8simulatePfS_y
.type _Z8simulatePfS_y, @function
_Z8simulatePfS_y:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8simulatePfS_yPfS_y
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8simulatePfS_y, .-_Z8simulatePfS_y
.globl _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
.type _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y, @function
_Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8assemblyPfS_S_y(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y, .-_Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
.globl _Z8assemblyPfS_S_y
.type _Z8assemblyPfS_S_y, @function
_Z8assemblyPfS_S_y:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8assemblyPfS_S_y, .-_Z8assemblyPfS_S_y
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "peek "
.LC9:
.string "loaded"
.LC10:
.string "\n"
.LC11:
.string "simulated"
.LC12:
.string "assemblied"
.text
.globl _Z6configy
.type _Z6configy, @function
_Z6configy:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
imulq $501, %rdi, %rbx
subq $1002, %rbx
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %rbx
movq %r12, %rcx
subq $2, %rcx
je .L27
leaq -12(%r12), %rdx
movq $-10, %rax
movss .LC1(%rip), %xmm2
movaps %xmm2, %xmm1
jmp .L29
.L28:
movss %xmm0, 40(%r13,%rax,4)
addq $1, %rax
cmpq %rax, %rdx
je .L27
.L29:
movss %xmm2, 40(%rbx,%rax,4)
movaps %xmm1, %xmm0
cmpq $20, %rax
ja .L28
movss .LC2(%rip), %xmm0
jmp .L28
.L27:
movl $1, 60(%rsp)
movl $501, 52(%rsp)
movl $24, 56(%rsp)
testq %rcx, %rcx
js .L30
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
.L31:
divsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC13(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC4(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L32
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L32:
comisd .LC7(%rip), %xmm1
jnb .L33
cvttsd2siq %xmm1, %rbp
.L34:
imulq $2004, %r12, %r14
subq $4008, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %ebx
jmp .L41
.L30:
movq %rcx, %rax
shrq %rax
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L31
.L33:
subsd .LC7(%rip), %xmm1
cvttsd2siq %xmm1, %rbp
btcq $63, %rbp
jmp .L34
.L51:
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L36
.L35:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L39:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L38:
addq $1, %rbx
cmpq $500, %rbx
je .L50
.L41:
testb $1, %bl
jne .L35
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L36:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L38
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L38
.L48:
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L39
.L49:
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L38
.L50:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rbp
movq 24(%rsp), %rbx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%r12,4), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl $501, 64(%rsp)
movl $512, 68(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L42:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %r12, %rcx
movq 40(%rsp), %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
jmp .L42
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6configy, .-_Z6configy
.section .rodata.str1.1
.LC14:
.string "Please indicate matrix size.\n"
.LC15:
.string "peek mean: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $1, %edi
jle .L58
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
addq $1, %rbx
movq %rbx, %rdi
call _Z6configy
movq %rax, %rbp
testq %rax, %rax
je .L56
movq %rbx, %rsi
movq %rax, %rdi
call _Z3avgPfy
cvtss2sd %xmm0, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
.L56:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z8assemblyPfS_S_y"
.LC17:
.string "_Z8simulatePfS_y"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8assemblyPfS_S_y(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z8simulatePfS_y(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1117782016
.align 4
.LC2:
.long 1125515264
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1077411840
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long 0
.long 1138753536
.align 8
.LC13:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <cuda.h>
#define TIME 500 //# of iterations
#define BLKSIZE 24
#define DEBUG(s) {printf("peek "); printf(s); printf("\n");}
//#define DEBUG(s)
typedef unsigned long long bint;
__global__ void simulate(float *src, float* des, bint dim){
__shared__ float add[TIME+1][BLKSIZE];
//x, y location of thread - to MEM space
bint x = threadIdx.x;
bint y = threadIdx.y + blockIdx.x*blockDim.y;
bint id = threadIdx.x*(dim-2) + threadIdx.y + blockIdx.x*blockDim.y;
float v = src[id]/4;
//initialize
if (x>0){
add[x][y] = 0;
}
__syncthreads();
//load each v to up, left, right, down positions
if (x < TIME)
add[x+1][y] = v;
if (x > 0)
add[x-1][y] = v;
if (y%BLKSIZE > 0) //has sth on left
add[x][y%BLKSIZE-1] = v;
else if (y > 0)
des[id-1] = v; //global
if (y%BLKSIZE < BLKSIZE-1) //has sth on right
add[x][y%BLKSIZE+1] = v;
else if (y < dim-3)
des[id+1] = v; //global
__syncthreads();
// GMT once for all
if ((x > 0) && (y < dim-2))
des[id] += add[x][y];
}
__global__ void assembly(float *d1, float *d2, float *m, bint dim){
__shared__ float tmp[TIME+1];
bint x = threadIdx.x;
bint y = threadIdx.y;
bint id1 = threadIdx.x*(dim-2) + threadIdx.y;
bint id2 = (threadIdx.x+1)*(dim-2) - threadIdx.y - 1; //upright box
tmp[x] = d2[x]; //global load to shared
__syncthreads();
// GMT
m[y] = tmp[y];
if (y < TIME){
d1[id1] += tmp[y+1];
d1[id2] += tmp[y+1];
d2[id1] += tmp[y+1];
d2[id2] += tmp[y+1];
m[dim-2-y] = tmp[y+1];
}
}
float * config(bint dim){
//allocate on host and initialize
float *bar1 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side with 150
float *bar2 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side all 80
bint p;
for (p=0; p < dim-2; p++){
bar1[p] = 80;
bar2[p] = 80;
if ((p>=10) && (p<=30)){
bar1[p] = 150;
}
}
//config kernel
dim3 blkdim;
blkdim.x = TIME+1;
blkdim.y = BLKSIZE;
bint griddim = ceil((double)(dim-2)/BLKSIZE);
//allocate on kernel
bint mem = (dim-2)*(TIME+1)*sizeof(float);
float *src1, *des1;
cudaMalloc((void **)&src1, mem);
cudaMalloc((void **)&des1, mem);
cudaMemcpy(src1, bar1, mem, cudaMemcpyHostToDevice);
cudaMemcpy(des1, bar1, mem, cudaMemcpyHostToDevice);
float *src2, *des2;
cudaMalloc((void **)&src2, mem);
cudaMalloc((void **)&des2, mem);
cudaMemcpy(src2, bar2, mem, cudaMemcpyHostToDevice);
cudaMemcpy(des2, bar2, mem, cudaMemcpyHostToDevice);
DEBUG("loaded")
free(bar1);
free(bar2);
//launch
bint i;
for (i=0; i<TIME; i++){
if (i%2==0){
simulate<<<griddim, blkdim>>>(src1, des1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}else{
simulate<<<griddim, blkdim>>>(des1, src1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}}
// clean up
float *d1, *d2;
if (TIME%2==0){ //result in src
cudaFree(des1);
cudaFree(des2);
d1 = src1;
d2 = src2;
}
else{
cudaFree(src1);
cudaFree(src2);
d1 = des1;
d2 = des2;
}
DEBUG("simulated")
//assembly
float *mid;
cudaMalloc((void **)&mid, dim*sizeof(float)); //result for middle lines
dim3 blk;
blk.x = TIME+1;
blk.y = (TIME%32==0) ? TIME : TIME+32-TIME%32; //first 32n >= TIME
assembly<<<1, blk>>>(d1, d2, mid, dim);
DEBUG("assemblied")
/*
//cpu assembly
float *m = (float *)malloc(dim*dim*sizeof(float));
bint unit = (dim-2)*sizeof(float);
for (i=0; i<TIME+1; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d1[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d1);
//done line 0 to TIME
float *middlelines = (float *)malloc(dim*sizeof(float));
cudaMemcpy(middlelines, mid, dim*sizeof(float), cudaMemcpyDeviceToHost);
for (i=TIME+1; i<dim-1-TIME; i++){
middlelines[i] = 0; //no temperature for the middle region
}
middlelines[dim-1] = 80;
for (i=TIME+1; i<dim-1-TIME; i++){
memcpy(&m[i*dim], middlelines, dim*sizeof(float));
}
cudaFree(mid);
//done for TIME+1...dim-TIME-1
for (i=dim-1-TIME; i<dim; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d2[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d2);
//done dim-TIME-1...dim-1
return m;
*/
cudaFree(d1);
cudaFree(d2);
cudaFree(mid);
return NULL;
}
float avg(float *m, bint dim){
bint size = dim*dim;
float sum = 0;
bint i;
for (i=0; i<size; i++){
sum += m[i];
//if (i % dim==0)
// printf("\n");
//printf("%f ", m[i]);
}
//printf("\n");
return sum/size;
}
int main(int argc, char *argv[]){
//getDeviceProp();
if (argc < 2){
printf("Please indicate matrix size.\n");
exit(0);
}
bint n = atoi(argv[1]);
float *x = config(n+1);
if (x != NULL){
float mean = avg(x, n+1);
printf("peek mean: %f\n", mean);
free(x);
}
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define TIME 500 //# of iterations
#define BLKSIZE 24
#define DEBUG(s) {printf("peek "); printf(s); printf("\n");}
//#define DEBUG(s)
typedef unsigned long long bint;
__global__ void simulate(float *src, float* des, bint dim){
__shared__ float add[TIME+1][BLKSIZE];
//x, y location of thread - to MEM space
bint x = threadIdx.x;
bint y = threadIdx.y + blockIdx.x*blockDim.y;
bint id = threadIdx.x*(dim-2) + threadIdx.y + blockIdx.x*blockDim.y;
float v = src[id]/4;
//initialize
if (x>0){
add[x][y] = 0;
}
__syncthreads();
//load each v to up, left, right, down positions
if (x < TIME)
add[x+1][y] = v;
if (x > 0)
add[x-1][y] = v;
if (y%BLKSIZE > 0) //has sth on left
add[x][y%BLKSIZE-1] = v;
else if (y > 0)
des[id-1] = v; //global
if (y%BLKSIZE < BLKSIZE-1) //has sth on right
add[x][y%BLKSIZE+1] = v;
else if (y < dim-3)
des[id+1] = v; //global
__syncthreads();
// GMT once for all
if ((x > 0) && (y < dim-2))
des[id] += add[x][y];
}
__global__ void assembly(float *d1, float *d2, float *m, bint dim){
__shared__ float tmp[TIME+1];
bint x = threadIdx.x;
bint y = threadIdx.y;
bint id1 = threadIdx.x*(dim-2) + threadIdx.y;
bint id2 = (threadIdx.x+1)*(dim-2) - threadIdx.y - 1; //upright box
tmp[x] = d2[x]; //global load to shared
__syncthreads();
// GMT
m[y] = tmp[y];
if (y < TIME){
d1[id1] += tmp[y+1];
d1[id2] += tmp[y+1];
d2[id1] += tmp[y+1];
d2[id2] += tmp[y+1];
m[dim-2-y] = tmp[y+1];
}
}
float * config(bint dim){
//allocate on host and initialize
float *bar1 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side with 150
float *bar2 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side all 80
bint p;
for (p=0; p < dim-2; p++){
bar1[p] = 80;
bar2[p] = 80;
if ((p>=10) && (p<=30)){
bar1[p] = 150;
}
}
//config kernel
dim3 blkdim;
blkdim.x = TIME+1;
blkdim.y = BLKSIZE;
bint griddim = ceil((double)(dim-2)/BLKSIZE);
//allocate on kernel
bint mem = (dim-2)*(TIME+1)*sizeof(float);
float *src1, *des1;
hipMalloc((void **)&src1, mem);
hipMalloc((void **)&des1, mem);
hipMemcpy(src1, bar1, mem, hipMemcpyHostToDevice);
hipMemcpy(des1, bar1, mem, hipMemcpyHostToDevice);
float *src2, *des2;
hipMalloc((void **)&src2, mem);
hipMalloc((void **)&des2, mem);
hipMemcpy(src2, bar2, mem, hipMemcpyHostToDevice);
hipMemcpy(des2, bar2, mem, hipMemcpyHostToDevice);
DEBUG("loaded")
free(bar1);
free(bar2);
//launch
bint i;
for (i=0; i<TIME; i++){
if (i%2==0){
simulate<<<griddim, blkdim>>>(src1, des1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}else{
simulate<<<griddim, blkdim>>>(des1, src1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}}
// clean up
float *d1, *d2;
if (TIME%2==0){ //result in src
hipFree(des1);
hipFree(des2);
d1 = src1;
d2 = src2;
}
else{
hipFree(src1);
hipFree(src2);
d1 = des1;
d2 = des2;
}
DEBUG("simulated")
//assembly
float *mid;
hipMalloc((void **)&mid, dim*sizeof(float)); //result for middle lines
dim3 blk;
blk.x = TIME+1;
blk.y = (TIME%32==0) ? TIME : TIME+32-TIME%32; //first 32n >= TIME
assembly<<<1, blk>>>(d1, d2, mid, dim);
DEBUG("assemblied")
/*
//cpu assembly
float *m = (float *)malloc(dim*dim*sizeof(float));
bint unit = (dim-2)*sizeof(float);
for (i=0; i<TIME+1; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d1[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d1);
//done line 0 to TIME
float *middlelines = (float *)malloc(dim*sizeof(float));
cudaMemcpy(middlelines, mid, dim*sizeof(float), cudaMemcpyDeviceToHost);
for (i=TIME+1; i<dim-1-TIME; i++){
middlelines[i] = 0; //no temperature for the middle region
}
middlelines[dim-1] = 80;
for (i=TIME+1; i<dim-1-TIME; i++){
memcpy(&m[i*dim], middlelines, dim*sizeof(float));
}
cudaFree(mid);
//done for TIME+1...dim-TIME-1
for (i=dim-1-TIME; i<dim; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d2[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d2);
//done dim-TIME-1...dim-1
return m;
*/
hipFree(d1);
hipFree(d2);
hipFree(mid);
return NULL;
}
float avg(float *m, bint dim){
bint size = dim*dim;
float sum = 0;
bint i;
for (i=0; i<size; i++){
sum += m[i];
//if (i % dim==0)
// printf("\n");
//printf("%f ", m[i]);
}
//printf("\n");
return sum/size;
}
int main(int argc, char *argv[]){
//getDeviceProp();
if (argc < 2){
printf("Please indicate matrix size.\n");
exit(0);
}
bint n = atoi(argv[1]);
float *x = config(n+1);
if (x != NULL){
float mean = avg(x, n+1);
printf("peek mean: %f\n", mean);
free(x);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define TIME 500 //# of iterations
#define BLKSIZE 24
#define DEBUG(s) {printf("peek "); printf(s); printf("\n");}
//#define DEBUG(s)
typedef unsigned long long bint;
__global__ void simulate(float *src, float* des, bint dim){
__shared__ float add[TIME+1][BLKSIZE];
//x, y location of thread - to MEM space
bint x = threadIdx.x;
bint y = threadIdx.y + blockIdx.x*blockDim.y;
bint id = threadIdx.x*(dim-2) + threadIdx.y + blockIdx.x*blockDim.y;
float v = src[id]/4;
//initialize
if (x>0){
add[x][y] = 0;
}
__syncthreads();
//load each v to up, left, right, down positions
if (x < TIME)
add[x+1][y] = v;
if (x > 0)
add[x-1][y] = v;
if (y%BLKSIZE > 0) //has sth on left
add[x][y%BLKSIZE-1] = v;
else if (y > 0)
des[id-1] = v; //global
if (y%BLKSIZE < BLKSIZE-1) //has sth on right
add[x][y%BLKSIZE+1] = v;
else if (y < dim-3)
des[id+1] = v; //global
__syncthreads();
// GMT once for all
if ((x > 0) && (y < dim-2))
des[id] += add[x][y];
}
__global__ void assembly(float *d1, float *d2, float *m, bint dim){
__shared__ float tmp[TIME+1];
bint x = threadIdx.x;
bint y = threadIdx.y;
bint id1 = threadIdx.x*(dim-2) + threadIdx.y;
bint id2 = (threadIdx.x+1)*(dim-2) - threadIdx.y - 1; //upright box
tmp[x] = d2[x]; //global load to shared
__syncthreads();
// GMT
m[y] = tmp[y];
if (y < TIME){
d1[id1] += tmp[y+1];
d1[id2] += tmp[y+1];
d2[id1] += tmp[y+1];
d2[id2] += tmp[y+1];
m[dim-2-y] = tmp[y+1];
}
}
float * config(bint dim){
//allocate on host and initialize
float *bar1 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side with 150
float *bar2 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side all 80
bint p;
for (p=0; p < dim-2; p++){
bar1[p] = 80;
bar2[p] = 80;
if ((p>=10) && (p<=30)){
bar1[p] = 150;
}
}
//config kernel
dim3 blkdim;
blkdim.x = TIME+1;
blkdim.y = BLKSIZE;
bint griddim = ceil((double)(dim-2)/BLKSIZE);
//allocate on kernel
bint mem = (dim-2)*(TIME+1)*sizeof(float);
float *src1, *des1;
hipMalloc((void **)&src1, mem);
hipMalloc((void **)&des1, mem);
hipMemcpy(src1, bar1, mem, hipMemcpyHostToDevice);
hipMemcpy(des1, bar1, mem, hipMemcpyHostToDevice);
float *src2, *des2;
hipMalloc((void **)&src2, mem);
hipMalloc((void **)&des2, mem);
hipMemcpy(src2, bar2, mem, hipMemcpyHostToDevice);
hipMemcpy(des2, bar2, mem, hipMemcpyHostToDevice);
DEBUG("loaded")
free(bar1);
free(bar2);
//launch
bint i;
for (i=0; i<TIME; i++){
if (i%2==0){
simulate<<<griddim, blkdim>>>(src1, des1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}else{
simulate<<<griddim, blkdim>>>(des1, src1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}}
// clean up
float *d1, *d2;
if (TIME%2==0){ //result in src
hipFree(des1);
hipFree(des2);
d1 = src1;
d2 = src2;
}
else{
hipFree(src1);
hipFree(src2);
d1 = des1;
d2 = des2;
}
DEBUG("simulated")
//assembly
float *mid;
hipMalloc((void **)&mid, dim*sizeof(float)); //result for middle lines
dim3 blk;
blk.x = TIME+1;
blk.y = (TIME%32==0) ? TIME : TIME+32-TIME%32; //first 32n >= TIME
assembly<<<1, blk>>>(d1, d2, mid, dim);
DEBUG("assemblied")
/*
//cpu assembly
float *m = (float *)malloc(dim*dim*sizeof(float));
bint unit = (dim-2)*sizeof(float);
for (i=0; i<TIME+1; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d1[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d1);
//done line 0 to TIME
float *middlelines = (float *)malloc(dim*sizeof(float));
cudaMemcpy(middlelines, mid, dim*sizeof(float), cudaMemcpyDeviceToHost);
for (i=TIME+1; i<dim-1-TIME; i++){
middlelines[i] = 0; //no temperature for the middle region
}
middlelines[dim-1] = 80;
for (i=TIME+1; i<dim-1-TIME; i++){
memcpy(&m[i*dim], middlelines, dim*sizeof(float));
}
cudaFree(mid);
//done for TIME+1...dim-TIME-1
for (i=dim-1-TIME; i<dim; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d2[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d2);
//done dim-TIME-1...dim-1
return m;
*/
hipFree(d1);
hipFree(d2);
hipFree(mid);
return NULL;
}
float avg(float *m, bint dim){
bint size = dim*dim;
float sum = 0;
bint i;
for (i=0; i<size; i++){
sum += m[i];
//if (i % dim==0)
// printf("\n");
//printf("%f ", m[i]);
}
//printf("\n");
return sum/size;
}
int main(int argc, char *argv[]){
//getDeviceProp();
if (argc < 2){
printf("Please indicate matrix size.\n");
exit(0);
}
bint n = atoi(argv[1]);
float *x = config(n+1);
if (x != NULL){
float mean = avg(x, n+1);
printf("peek mean: %f\n", mean);
free(x);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8simulatePfS_y
.globl _Z8simulatePfS_y
.p2align 8
.type _Z8simulatePfS_y,@function
_Z8simulatePfS_y:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v6, 0x3ff, v0
v_bfe_u32 v7, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v8, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s2, 16
s_add_u32 s4, s6, -2
s_addc_u32 s5, s7, -1
v_mad_u64_u32 v[2:3], null, s4, v6, v[7:8]
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s15, s15, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v0, v3
v_add_co_u32 v2, vcc_lo, v2, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s5, v6, v[0:1]
v_mov_b32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v0, vcc_lo
v_add_nc_u32_e32 v0, s15, v7
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v6
global_load_b32 v4, v[4:5], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v5, 2, v0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u32_u24 v5, v6, 0x60, v5
ds_store_b32 v5, v7
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, 0x3e800000, v4
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x1f4, v6
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v4, v6, 0x60, v4
ds_store_b32 v4, v7 offset:96
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_mul_u32_u24_e32 v4, 0x60, v6
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v4, v5, 0xffffffa0
ds_store_b32 v4, v7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_mul_hi_u32 v4, v0, 0xaaaaaaa
s_load_b64 s[2:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, 24
v_sub_nc_u32_e32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, 24, v4
v_cmp_lt_u32_e64 s0, 23, v4
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, 24, v4
v_cmp_lt_u32_e64 s0, 23, v4
v_cndmask_b32_e64 v4, v4, v5, s0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 0, v4
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v8, 2, v4
v_mul_u32_u24_e32 v9, 0x60, v6
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v8, v8, v9, -4
ds_store_b32 v8, v7
.LBB0_8:
s_and_not1_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_12
s_mov_b32 s8, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s2, v8
v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
global_store_b32 v[8:9], v7, off offset:-4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s1, exec_lo
v_cmpx_lt_u64_e32 22, v[4:5]
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_16
s_add_u32 s6, s6, -3
s_addc_u32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s0, s[6:7], v[0:1]
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_15
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
global_store_b32 v[4:5], v7, off offset:4
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_16:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_18
v_mul_u32_u24_e32 v5, 0x60, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, v5
ds_store_b32 v4, v7 offset:4
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u64_e64 s0, s[4:5], v[0:1]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_20
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u32_u24 v0, v6, 0x60, v0
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
ds_load_b32 v0, v0
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
global_store_b32 v[1:2], v0, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8simulatePfS_y
.amdhsa_group_segment_fixed_size 48096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8simulatePfS_y, .Lfunc_end0-_Z8simulatePfS_y
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8assemblyPfS_S_y
.globl _Z8assemblyPfS_S_y
.p2align 8
.type _Z8assemblyPfS_S_y,@function
_Z8assemblyPfS_S_y:
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v1, 2, v2
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v4, v3, s[6:7]
v_cmpx_gt_u32_e32 0x1f4, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v12, 1, v2
v_not_b32_e32 v8, v1
v_not_b32_e32 v7, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, -2
s_addc_u32 s3, s3, -1
v_mad_u64_u32 v[3:4], null, s2, v2, v[0:1]
v_mad_u64_u32 v[9:10], null, s2, v12, v[7:8]
v_lshlrev_b32_e32 v7, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s3, v2, v[4:5]
v_mov_b32_e32 v2, v10
ds_load_b32 v13, v7 offset:4
v_mov_b32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
v_mad_u64_u32 v[7:8], null, s3, v12, v[2:3]
global_load_b32 v11, v[5:6], off
v_mov_b32_e32 v10, v7
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v8, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v13, v11
global_store_b32 v[5:6], v2, off
global_load_b32 v2, v[9:10], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v13, v2
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[9:10], v5, off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v13, v4
v_add_co_u32 v4, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v8, vcc_lo
global_store_b32 v[2:3], v6, off
v_sub_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[4:5], off
v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v13, v2
global_store_b32 v[4:5], v2, off
global_store_b32 v[0:1], v13, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8assemblyPfS_S_y
.amdhsa_group_segment_fixed_size 2004
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8assemblyPfS_S_y, .Lfunc_end1-_Z8assemblyPfS_S_y
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 48096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8simulatePfS_y
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8simulatePfS_y.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 2004
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8assemblyPfS_S_y
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8assemblyPfS_S_y.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define TIME 500 //# of iterations
#define BLKSIZE 24
#define DEBUG(s) {printf("peek "); printf(s); printf("\n");}
//#define DEBUG(s)
typedef unsigned long long bint;
__global__ void simulate(float *src, float* des, bint dim){
__shared__ float add[TIME+1][BLKSIZE];
//x, y location of thread - to MEM space
bint x = threadIdx.x;
bint y = threadIdx.y + blockIdx.x*blockDim.y;
bint id = threadIdx.x*(dim-2) + threadIdx.y + blockIdx.x*blockDim.y;
float v = src[id]/4;
//initialize
if (x>0){
add[x][y] = 0;
}
__syncthreads();
//load each v to up, left, right, down positions
if (x < TIME)
add[x+1][y] = v;
if (x > 0)
add[x-1][y] = v;
if (y%BLKSIZE > 0) //has sth on left
add[x][y%BLKSIZE-1] = v;
else if (y > 0)
des[id-1] = v; //global
if (y%BLKSIZE < BLKSIZE-1) //has sth on right
add[x][y%BLKSIZE+1] = v;
else if (y < dim-3)
des[id+1] = v; //global
__syncthreads();
// GMT once for all
if ((x > 0) && (y < dim-2))
des[id] += add[x][y];
}
__global__ void assembly(float *d1, float *d2, float *m, bint dim){
__shared__ float tmp[TIME+1];
bint x = threadIdx.x;
bint y = threadIdx.y;
bint id1 = threadIdx.x*(dim-2) + threadIdx.y;
bint id2 = (threadIdx.x+1)*(dim-2) - threadIdx.y - 1; //upright box
tmp[x] = d2[x]; //global load to shared
__syncthreads();
// GMT
m[y] = tmp[y];
if (y < TIME){
d1[id1] += tmp[y+1];
d1[id2] += tmp[y+1];
d2[id1] += tmp[y+1];
d2[id2] += tmp[y+1];
m[dim-2-y] = tmp[y+1];
}
}
float * config(bint dim){
//allocate on host and initialize
float *bar1 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side with 150
float *bar2 = (float *)calloc((dim-2)*(TIME+1), sizeof(float)); //side all 80
bint p;
for (p=0; p < dim-2; p++){
bar1[p] = 80;
bar2[p] = 80;
if ((p>=10) && (p<=30)){
bar1[p] = 150;
}
}
//config kernel
dim3 blkdim;
blkdim.x = TIME+1;
blkdim.y = BLKSIZE;
bint griddim = ceil((double)(dim-2)/BLKSIZE);
//allocate on kernel
bint mem = (dim-2)*(TIME+1)*sizeof(float);
float *src1, *des1;
hipMalloc((void **)&src1, mem);
hipMalloc((void **)&des1, mem);
hipMemcpy(src1, bar1, mem, hipMemcpyHostToDevice);
hipMemcpy(des1, bar1, mem, hipMemcpyHostToDevice);
float *src2, *des2;
hipMalloc((void **)&src2, mem);
hipMalloc((void **)&des2, mem);
hipMemcpy(src2, bar2, mem, hipMemcpyHostToDevice);
hipMemcpy(des2, bar2, mem, hipMemcpyHostToDevice);
DEBUG("loaded")
free(bar1);
free(bar2);
//launch
bint i;
for (i=0; i<TIME; i++){
if (i%2==0){
simulate<<<griddim, blkdim>>>(src1, des1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}else{
simulate<<<griddim, blkdim>>>(des1, src1, dim);
simulate<<<griddim, blkdim>>>(src2, des2, dim);
}}
// clean up
float *d1, *d2;
if (TIME%2==0){ //result in src
hipFree(des1);
hipFree(des2);
d1 = src1;
d2 = src2;
}
else{
hipFree(src1);
hipFree(src2);
d1 = des1;
d2 = des2;
}
DEBUG("simulated")
//assembly
float *mid;
hipMalloc((void **)&mid, dim*sizeof(float)); //result for middle lines
dim3 blk;
blk.x = TIME+1;
blk.y = (TIME%32==0) ? TIME : TIME+32-TIME%32; //first 32n >= TIME
assembly<<<1, blk>>>(d1, d2, mid, dim);
DEBUG("assemblied")
/*
//cpu assembly
float *m = (float *)malloc(dim*dim*sizeof(float));
bint unit = (dim-2)*sizeof(float);
for (i=0; i<TIME+1; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d1[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d1);
//done line 0 to TIME
float *middlelines = (float *)malloc(dim*sizeof(float));
cudaMemcpy(middlelines, mid, dim*sizeof(float), cudaMemcpyDeviceToHost);
for (i=TIME+1; i<dim-1-TIME; i++){
middlelines[i] = 0; //no temperature for the middle region
}
middlelines[dim-1] = 80;
for (i=TIME+1; i<dim-1-TIME; i++){
memcpy(&m[i*dim], middlelines, dim*sizeof(float));
}
cudaFree(mid);
//done for TIME+1...dim-TIME-1
for (i=dim-1-TIME; i<dim; i++){
m[i*dim] = 80;
cudaMemcpy(&m[i*dim+1], &d2[i*(dim-2)], unit, cudaMemcpyDeviceToHost);
m[(i+1)*dim-1] = 80;
}
cudaFree(d2);
//done dim-TIME-1...dim-1
return m;
*/
hipFree(d1);
hipFree(d2);
hipFree(mid);
return NULL;
}
float avg(float *m, bint dim){
bint size = dim*dim;
float sum = 0;
bint i;
for (i=0; i<size; i++){
sum += m[i];
//if (i % dim==0)
// printf("\n");
//printf("%f ", m[i]);
}
//printf("\n");
return sum/size;
}
int main(int argc, char *argv[]){
//getDeviceProp();
if (argc < 2){
printf("Please indicate matrix size.\n");
exit(0);
}
bint n = atoi(argv[1]);
float *x = config(n+1);
if (x != NULL){
float mean = avg(x, n+1);
printf("peek mean: %f\n", mean);
free(x);
}
return 0;
} | .text
.file "cuda-optimized.hip"
.globl _Z23__device_stub__simulatePfS_y # -- Begin function _Z23__device_stub__simulatePfS_y
.p2align 4, 0x90
.type _Z23__device_stub__simulatePfS_y,@function
_Z23__device_stub__simulatePfS_y: # @_Z23__device_stub__simulatePfS_y
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8simulatePfS_y, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__simulatePfS_y, .Lfunc_end0-_Z23__device_stub__simulatePfS_y
.cfi_endproc
# -- End function
.globl _Z23__device_stub__assemblyPfS_S_y # -- Begin function _Z23__device_stub__assemblyPfS_S_y
.p2align 4, 0x90
.type _Z23__device_stub__assemblyPfS_S_y,@function
_Z23__device_stub__assemblyPfS_S_y: # @_Z23__device_stub__assemblyPfS_S_y
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8assemblyPfS_S_y, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__assemblyPfS_S_y, .Lfunc_end1-_Z23__device_stub__assemblyPfS_S_y
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6configy
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x4038000000000000 # double 24
.LCPI2_3:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl _Z6configy
.p2align 4, 0x90
.type _Z6configy,@function
_Z6configy: # @_Z6configy
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
leaq -2(%rdi), %rbp
imulq $501, %rbp, %r15 # imm = 0x1F5
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r13
testq %rbp, %rbp
je .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl $2, %eax
subq %rbx, %rax
movq $-10, %rcx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
leaq (%rax,%rcx), %rdx
incq %rdx
incq %rcx
cmpq $-10, %rdx
je .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1117782016, 40(%r14,%rcx,4) # imm = 0x42A00000
movl $1117782016, 40(%r13,%rcx,4) # imm = 0x42A00000
cmpq $20, %rcx
ja .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl $1125515264, 40(%r14,%rcx,4) # imm = 0x43160000
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movabsq $103079215605, %r15 # imm = 0x18000001F5
movq %rbp, %xmm1
punpckldq .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI2_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12
movq %r12, %rax
subsd .LCPI2_3(%rip), %xmm0
cvttsd2si %xmm0, %rcx
sarq $63, %rax
andl %eax, %ecx
orl %ecx, %r12d
imulq $2004, %rbp, %rbp # imm = 0x7D4
leaq 104(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 96(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 88(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %ebp, %ebp
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
leaq 72(%rsp), %r13
leaq 112(%rsp), %r14
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_6 Depth=1
incq %rbp
cmpq $500, %rbp # imm = 0x1F4
je .LBB2_15
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
testb $1, %bpl
jne .LBB2_9
# %bb.7: # in Loop: Header=BB2_6 Depth=1
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.8: # in Loop: Header=BB2_6 Depth=1
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_6 Depth=1
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.10: # in Loop: Header=BB2_6 Depth=1
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
.LBB2_11: # in Loop: Header=BB2_6 Depth=1
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z8simulatePfS_y, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12: # in Loop: Header=BB2_6 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_6 Depth=1
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z8simulatePfS_y, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_14
.LBB2_15:
movq 96(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 104(%rsp), %r15
movq 88(%rsp), %r14
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
leaq (,%rbx,4), %rsi
leaq 152(%rsp), %rdi
callq hipMalloc
movabsq $4294967296, %rdi # imm = 0x100000000
incq %rdi
movabsq $2199023256053, %rdx # imm = 0x200000001F5
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movq 152(%rsp), %rax
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rax, 48(%rsp)
movq %rbx, 40(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8assemblyPfS_S_y, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_17:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6configy, .Lfunc_end2-_Z6configy
.cfi_endproc
# -- End function
.globl _Z3avgPfy # -- Begin function _Z3avgPfy
.p2align 4, 0x90
.type _Z3avgPfy,@function
_Z3avgPfy: # @_Z3avgPfy
.cfi_startproc
# %bb.0:
imulq %rsi, %rsi
xorps %xmm0, %xmm0
testq %rsi, %rsi
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq %rax, %rsi
jne .LBB3_2
.LBB3_3: # %._crit_edge
testq %rsi, %rsi
js .LBB3_4
# %bb.5: # %._crit_edge
cvtsi2ss %rsi, %xmm1
divss %xmm1, %xmm0
retq
.LBB3_4:
movq %rsi, %rax
shrq %rax
andl $1, %esi
orq %rax, %rsi
cvtsi2ss %rsi, %xmm1
addss %xmm1, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end3:
.size _Z3avgPfy, .Lfunc_end3-_Z3avgPfy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $1, %edi
jle .LBB4_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rdi
incq %rdi
callq _Z6configy
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8simulatePfS_y, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8assemblyPfS_S_y, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8simulatePfS_y,@object # @_Z8simulatePfS_y
.section .rodata,"a",@progbits
.globl _Z8simulatePfS_y
.p2align 3, 0x0
_Z8simulatePfS_y:
.quad _Z23__device_stub__simulatePfS_y
.size _Z8simulatePfS_y, 8
.type _Z8assemblyPfS_S_y,@object # @_Z8assemblyPfS_S_y
.globl _Z8assemblyPfS_S_y
.p2align 3, 0x0
_Z8assemblyPfS_S_y:
.quad _Z23__device_stub__assemblyPfS_S_y
.size _Z8assemblyPfS_S_y, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "peek "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "loaded"
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "simulated"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "assemblied"
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8simulatePfS_y"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8assemblyPfS_S_y"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please indicate matrix size."
.size .Lstr, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__simulatePfS_y
.addrsig_sym _Z23__device_stub__assemblyPfS_S_y
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8simulatePfS_y
.addrsig_sym _Z8assemblyPfS_S_y
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8assemblyPfS_S_y
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R11, R4, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x001fcc00078e0004 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0070*/ ISETP.GT.U32.AND P0, PT, R0.reuse, 0x1f3, PT ; /* 0x000001f30000780c */
/* 0x041fe20003f04070 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0004 */
/*0090*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e2000c101904 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x001fe200078e00ff */
/*00f0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fc400078e00ff */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0120*/ IADD3 R5, P0, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R2, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02027810 */
/* 0x000fe400007fe4ff */
/*0140*/ IMAD.WIDE.U32 R8, R11, R5, R6 ; /* 0x000000050b087225 */
/* 0x000fc800078e0006 */
/*0150*/ IMAD R3, R2, R11, RZ ; /* 0x0000000b02037224 */
/* 0x000fe400078e02ff */
/*0160*/ IMAD.SHL.U32 R10, R8, 0x4, RZ ; /* 0x00000004080a7824 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.IADD R3, R9, 0x1, R3 ; /* 0x0000000109037824 */
/* 0x000fc600078e0203 */
/*0180*/ IADD3 R6, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a067a10 */
/* 0x000fe40007f1e0ff */
/*0190*/ SHF.L.U64.HI R14, R8, 0x2, R3 ; /* 0x00000002080e7819 */
/* 0x000fe40000010203 */
/*01a0*/ LDS R3, [R0.X4+0x4] ; /* 0x0000040000037984 */
/* 0x000e240000004800 */
/*01b0*/ IADD3.X R7, R14, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000e077a10 */
/* 0x000fca00007fe4ff */
/*01c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000e22000c1e1900 */
/*01d0*/ LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff087212 */
/* 0x000fe200078e33ff */
/*01e0*/ IMAD.MOV.U32 R9, RZ, RZ, -0x1 ; /* 0xffffffffff097424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fca0007ffe0ff */
/*0200*/ IMAD.WIDE.U32 R8, R11, R5, R8 ; /* 0x000000050b087225 */
/* 0x000fc800078e0008 */
/*0210*/ IMAD R13, R2, R11, RZ ; /* 0x0000000b020d7224 */
/* 0x000fe400078e02ff */
/*0220*/ IMAD.SHL.U32 R12, R8, 0x4, RZ ; /* 0x00000004080c7824 */
/* 0x000fc600078e00ff */
/*0230*/ IADD3 R13, R9, R13, RZ ; /* 0x0000000d090d7210 */
/* 0x000fc80007ffe0ff */
/*0240*/ SHF.L.U64.HI R13, R8, 0x2, R13 ; /* 0x00000002080d7819 */
/* 0x000fe4000001020d */
/*0250*/ IADD3 R8, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c087a10 */
/* 0x000fc80007f1e0ff */
/*0260*/ IADD3.X R9, R13, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000d097a10 */
/* 0x000fe200007fe4ff */
/*0270*/ FADD R15, R4, R3 ; /* 0x00000003040f7221 */
/* 0x001fca0000000000 */
/*0280*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R10, P0, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0a7a10 */
/* 0x000fc80007f1e0ff */
/*02b0*/ IADD3.X R11, R14, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000e0b7a10 */
/* 0x000fe200007fe4ff */
/*02c0*/ FADD R17, R3, R4 ; /* 0x0000000403117221 */
/* 0x004fca0000000000 */
/*02d0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x000fe8000c101904 */
/*02e0*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IADD3 R12, P0, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0300*/ IADD3.X R13, R13, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000d0d7a10 */
/* 0x000fe200007fe4ff */
/*0310*/ FADD R19, R3, R4 ; /* 0x0000000403137221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x000fe8000c101904 */
/*0330*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x001ea2000c1e1900 */
/*0340*/ IADD3 R0, P0, -R0, R5, RZ ; /* 0x0000000500007210 */
/* 0x000fc80007f1e1ff */
/*0350*/ IADD3.X R5, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02057810 */
/* 0x000fe400007fe4ff */
/*0360*/ LEA R4, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000047a11 */
/* 0x000fc800078010ff */
/*0370*/ LEA.HI.X R5, R0, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d0000057a11 */
/* 0x000fe200000f1405 */
/*0380*/ FADD R7, R3, R6 ; /* 0x0000000603077221 */
/* 0x004fca0000000000 */
/*0390*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8simulatePfS_y
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0030*/ ULDC UR5, c[0x0][0x4] ; /* 0x0000010000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ ULDC.64 UR10, c[0x0][0x170] ; /* 0x00005c00000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ea20000002100 */
/*0060*/ UIADD3 UR8, UP0, UR10, -0x2, URZ ; /* 0xfffffffe0a087890 */
/* 0x000fe4000ff1e03f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ UIADD3.X UR9, UR11, -0x1, URZ, UP0, !UPT ; /* 0xffffffff0b097890 */
/* 0x000fc400087fe43f */
/*0090*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc8000f8e023f */
/*00a0*/ IMAD R11, R9, UR9, RZ ; /* 0x00000009090b7c24 */
/* 0x004fe4000f8e02ff */
/*00b0*/ IADD3 R2, P0, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x002fca000ff1e0ff */
/*00c0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fc800000e06ff */
/*00d0*/ IMAD.WIDE.U32 R2, R9, UR8, R2 ; /* 0x0000000809027c25 */
/* 0x000fc8000f8e0002 */
/*00e0*/ IMAD.IADD R11, R3, 0x1, R11 ; /* 0x00000001030b7824 */
/* 0x000fe400078e020b */
/*00f0*/ IMAD.SHL.U32 R10, R2, 0x4, RZ ; /* 0x00000004020a7824 */
/* 0x000fc600078e00ff */
/*0100*/ SHF.L.U64.HI R11, R2, 0x2, R11 ; /* 0x00000002020b7819 */
/* 0x000fe4000001020b */
/*0110*/ IADD3 R4, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a047a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R5, R11, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000b057a10 */
/* 0x000fca00007fe4ff */
/*0130*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe0ff */
/*0150*/ BSSY B0, 0x2c0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f45270 */
/*0170*/ ISETP.GT.U32.AND P1, PT, R9, 0x1f3, PT ; /* 0x000001f30900780c */
/* 0x000fe20003f24070 */
/*0180*/ IMAD.WIDE.U32 R2, R0, -0x55555555, RZ ; /* 0xaaaaaaab00027825 */
/* 0x000fca00078e00ff */
/*0190*/ SHF.R.U32.HI R3, RZ, 0x4, R3 ; /* 0x00000004ff037819 */
/* 0x000fca0000011603 */
/*01a0*/ IMAD R8, R3, -0x18, R0 ; /* 0xffffffe803087824 */
/* 0x000fe400078e0200 */
/*01b0*/ IMAD R3, R9, 0x60, RZ ; /* 0x0000006009037824 */
/* 0x000fc600078e02ff */
/*01c0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*01d0*/ IMAD R6, R0, 0x4, R3 ; /* 0x0000000400067824 */
/* 0x000fca00078e0203 */
/*01e0*/ @P2 STS [R6], RZ ; /* 0x000000ff06002388 */
/* 0x0001e80000000800 */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ FMUL R7, R4, 0.25 ; /* 0x3e80000004077820 */
/* 0x004fe40000400000 */
/*0210*/ IMAD R4, R8, 0x4, R3 ; /* 0x0000000408047824 */
/* 0x000fc600078e0203 */
/*0220*/ @!P1 STS [R6+0x60], R7 ; /* 0x0000600706009388 */
/* 0x0001e20000000800 */
/*0230*/ ISETP.GE.U32.AND P1, PT, R8, 0x17, PT ; /* 0x000000170800780c */
/* 0x000fc60003f26070 */
/*0240*/ @P2 STS [R6+-0x60], R7 ; /* 0xffffa00706002388 */
/* 0x0001e20000000800 */
/*0250*/ IADD3 R2, P2, R10, c[0x0][0x168], RZ ; /* 0x00005a000a027a10 */
/* 0x000fc60007f5e0ff */
/*0260*/ @P0 STS [R4+-0x4], R7 ; /* 0xfffffc0704000388 */
/* 0x0001e20000000800 */
/*0270*/ IADD3.X R3, R11, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b000b037a10 */
/* 0x000fe200017fe4ff */
/*0280*/ @P0 BRA 0x2b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*02a0*/ @P0 STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702000986 */
/* 0x0003e4000c101906 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ BSSY B0, 0x380 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02d0*/ @!P1 BRA 0x360 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*02e0*/ UIADD3 UR4, UP0, UR10, -0x3, URZ ; /* 0xfffffffd0a047890 */
/* 0x000fc8000ff1e03f */
/*02f0*/ UIADD3.X UR5, UR11, -0x1, URZ, UP0, !UPT ; /* 0xffffffff0b057890 */
/* 0x000fe400087fe43f */
/*0300*/ ISETP.LT.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf01070 */
/*0310*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x001fca000f8e00ff */
/*0320*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0003f04100 */
/*0330*/ @!P0 BRA 0x370 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0340*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c101906 */
/*0350*/ BRA 0x370 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0360*/ STS [R4+0x4], R7 ; /* 0x0000040704007388 */
/* 0x0005e40000000800 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0390*/ ISETP.LT.U32.AND P0, PT, R0, UR8, PT ; /* 0x0000000800007c0c */
/* 0x000fe2000bf01070 */
/*03a0*/ IMAD.U32 R0, RZ, RZ, UR9 ; /* 0x00000009ff007e24 */
/* 0x000fca000f8e00ff */
/*03b0*/ ISETP.GT.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80003f04100 */
/*03c0*/ ISETP.EQ.OR P0, PT, R9, RZ, !P0 ; /* 0x000000ff0900720c */
/* 0x000fda0004702670 */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x001ee40000000800 */
/*0400*/ FADD R5, R6, R5 ; /* 0x0000000506057221 */
/* 0x008fca0000000000 */
/*0410*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8simulatePfS_y
.globl _Z8simulatePfS_y
.p2align 8
.type _Z8simulatePfS_y,@function
_Z8simulatePfS_y:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v6, 0x3ff, v0
v_bfe_u32 v7, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v8, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s2, 16
s_add_u32 s4, s6, -2
s_addc_u32 s5, s7, -1
v_mad_u64_u32 v[2:3], null, s4, v6, v[7:8]
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s15, s15, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v0, v3
v_add_co_u32 v2, vcc_lo, v2, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s5, v6, v[0:1]
v_mov_b32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v0, vcc_lo
v_add_nc_u32_e32 v0, s15, v7
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v6
global_load_b32 v4, v[4:5], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v5, 2, v0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2)
v_mad_u32_u24 v5, v6, 0x60, v5
ds_store_b32 v5, v7
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, 0x3e800000, v4
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x1f4, v6
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v4, v6, 0x60, v4
ds_store_b32 v4, v7 offset:96
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_mul_u32_u24_e32 v4, 0x60, v6
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v4, v5, 0xffffffa0
ds_store_b32 v4, v7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_mul_hi_u32 v4, v0, 0xaaaaaaa
s_load_b64 s[2:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, 24
v_sub_nc_u32_e32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, 24, v4
v_cmp_lt_u32_e64 s0, 23, v4
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, 24, v4
v_cmp_lt_u32_e64 s0, 23, v4
v_cndmask_b32_e64 v4, v4, v5, s0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 0, v4
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v8, 2, v4
v_mul_u32_u24_e32 v9, 0x60, v6
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v8, v8, v9, -4
ds_store_b32 v8, v7
.LBB0_8:
s_and_not1_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_12
s_mov_b32 s8, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s2, v8
v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
global_store_b32 v[8:9], v7, off offset:-4
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s1, exec_lo
v_cmpx_lt_u64_e32 22, v[4:5]
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_16
s_add_u32 s6, s6, -3
s_addc_u32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s0, s[6:7], v[0:1]
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_15
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
global_store_b32 v[4:5], v7, off offset:4
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_16:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_18
v_mul_u32_u24_e32 v5, 0x60, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, v5
ds_store_b32 v4, v7 offset:4
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_gt_u64_e64 s0, s[4:5], v[0:1]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_20
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u32_u24 v0, v6, 0x60, v0
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
ds_load_b32 v0, v0
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v3
global_store_b32 v[1:2], v0, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8simulatePfS_y
.amdhsa_group_segment_fixed_size 48096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8simulatePfS_y, .Lfunc_end0-_Z8simulatePfS_y
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8assemblyPfS_S_y
.globl _Z8assemblyPfS_S_y
.p2align 8
.type _Z8assemblyPfS_S_y,@function
_Z8assemblyPfS_S_y:
s_load_b128 s[4:7], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v1, 2, v2
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v4, v3, s[6:7]
v_cmpx_gt_u32_e32 0x1f4, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
v_add_nc_u32_e32 v12, 1, v2
v_not_b32_e32 v8, v1
v_not_b32_e32 v7, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, -2
s_addc_u32 s3, s3, -1
v_mad_u64_u32 v[3:4], null, s2, v2, v[0:1]
v_mad_u64_u32 v[9:10], null, s2, v12, v[7:8]
v_lshlrev_b32_e32 v7, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, s3, v2, v[4:5]
v_mov_b32_e32 v2, v10
ds_load_b32 v13, v7 offset:4
v_mov_b32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
v_mad_u64_u32 v[7:8], null, s3, v12, v[2:3]
global_load_b32 v11, v[5:6], off
v_mov_b32_e32 v10, v7
v_lshlrev_b64 v[7:8], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v8, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v13, v11
global_store_b32 v[5:6], v2, off
global_load_b32 v2, v[9:10], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v13, v2
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
global_store_b32 v[9:10], v5, off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v13, v4
v_add_co_u32 v4, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v8, vcc_lo
global_store_b32 v[2:3], v6, off
v_sub_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[4:5], off
v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v13, v2
global_store_b32 v[4:5], v2, off
global_store_b32 v[0:1], v13, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8assemblyPfS_S_y
.amdhsa_group_segment_fixed_size 2004
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8assemblyPfS_S_y, .Lfunc_end1-_Z8assemblyPfS_S_y
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 48096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8simulatePfS_y
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8simulatePfS_y.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 2004
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8assemblyPfS_S_y
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8assemblyPfS_S_y.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bed7f_00000000-6_cuda-optimized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3avgPfy
.type _Z3avgPfy, @function
_Z3avgPfy:
.LFB2058:
.cfi_startproc
endbr64
imulq %rsi, %rsi
testq %rsi, %rsi
je .L8
movq %rdi, %rax
leaq (%rdi,%rsi,4), %rdx
pxor %xmm0, %xmm0
.L5:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L4:
testq %rsi, %rsi
js .L6
pxor %xmm1, %xmm1
cvtsi2ssq %rsi, %xmm1
.L7:
divss %xmm1, %xmm0
ret
.L8:
pxor %xmm0, %xmm0
jmp .L4
.L6:
movq %rsi, %rax
shrq %rax
andl $1, %esi
orq %rsi, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z3avgPfy, .-_Z3avgPfy
.globl _Z30__device_stub__Z8simulatePfS_yPfS_y
.type _Z30__device_stub__Z8simulatePfS_yPfS_y, @function
_Z30__device_stub__Z8simulatePfS_yPfS_y:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8simulatePfS_y(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z8simulatePfS_yPfS_y, .-_Z30__device_stub__Z8simulatePfS_yPfS_y
.globl _Z8simulatePfS_y
.type _Z8simulatePfS_y, @function
_Z8simulatePfS_y:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8simulatePfS_yPfS_y
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8simulatePfS_y, .-_Z8simulatePfS_y
.globl _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
.type _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y, @function
_Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8assemblyPfS_S_y(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y, .-_Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
.globl _Z8assemblyPfS_S_y
.type _Z8assemblyPfS_S_y, @function
_Z8assemblyPfS_S_y:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8assemblyPfS_S_y, .-_Z8assemblyPfS_S_y
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "peek "
.LC9:
.string "loaded"
.LC10:
.string "\n"
.LC11:
.string "simulated"
.LC12:
.string "assemblied"
.text
.globl _Z6configy
.type _Z6configy, @function
_Z6configy:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
imulq $501, %rdi, %rbx
subq $1002, %rbx
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %rbx
movq %r12, %rcx
subq $2, %rcx
je .L27
leaq -12(%r12), %rdx
movq $-10, %rax
movss .LC1(%rip), %xmm2
movaps %xmm2, %xmm1
jmp .L29
.L28:
movss %xmm0, 40(%r13,%rax,4)
addq $1, %rax
cmpq %rax, %rdx
je .L27
.L29:
movss %xmm2, 40(%rbx,%rax,4)
movaps %xmm1, %xmm0
cmpq $20, %rax
ja .L28
movss .LC2(%rip), %xmm0
jmp .L28
.L27:
movl $1, 60(%rsp)
movl $501, 52(%rsp)
movl $24, 56(%rsp)
testq %rcx, %rcx
js .L30
pxor %xmm0, %xmm0
cvtsi2sdq %rcx, %xmm0
.L31:
divsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC13(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC4(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L32
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L32:
comisd .LC7(%rip), %xmm1
jnb .L33
cvttsd2siq %xmm1, %rbp
.L34:
imulq $2004, %r12, %r14
subq $4008, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %ebx
jmp .L41
.L30:
movq %rcx, %rax
shrq %rax
andl $1, %ecx
orq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L31
.L33:
subsd .LC7(%rip), %xmm1
cvttsd2siq %xmm1, %rbp
btcq $63, %rbp
jmp .L34
.L51:
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L36
.L35:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L39:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L38:
addq $1, %rbx
cmpq $500, %rbx
je .L50
.L41:
testb $1, %bl
jne .L35
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L36:
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 60(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L38
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L38
.L48:
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L39
.L49:
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z8simulatePfS_yPfS_y
jmp .L38
.L50:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rbp
movq 24(%rsp), %rbx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%r12,4), %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl $501, 64(%rsp)
movl $512, 68(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L42:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %r12, %rcx
movq 40(%rsp), %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z32__device_stub__Z8assemblyPfS_S_yPfS_S_y
jmp .L42
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6configy, .-_Z6configy
.section .rodata.str1.1
.LC14:
.string "Please indicate matrix size.\n"
.LC15:
.string "peek mean: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $1, %edi
jle .L58
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
addq $1, %rbx
movq %rbx, %rdi
call _Z6configy
movq %rax, %rbp
testq %rax, %rax
je .L56
movq %rbx, %rsi
movq %rax, %rdi
call _Z3avgPfy
cvtss2sd %xmm0, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
.L56:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z8assemblyPfS_S_y"
.LC17:
.string "_Z8simulatePfS_y"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z8assemblyPfS_S_y(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z8simulatePfS_y(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1117782016
.align 4
.LC2:
.long 1125515264
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1077411840
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long 0
.long 1138753536
.align 8
.LC13:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-optimized.hip"
.globl _Z23__device_stub__simulatePfS_y # -- Begin function _Z23__device_stub__simulatePfS_y
.p2align 4, 0x90
.type _Z23__device_stub__simulatePfS_y,@function
_Z23__device_stub__simulatePfS_y: # @_Z23__device_stub__simulatePfS_y
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8simulatePfS_y, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__simulatePfS_y, .Lfunc_end0-_Z23__device_stub__simulatePfS_y
.cfi_endproc
# -- End function
.globl _Z23__device_stub__assemblyPfS_S_y # -- Begin function _Z23__device_stub__assemblyPfS_S_y
.p2align 4, 0x90
.type _Z23__device_stub__assemblyPfS_S_y,@function
_Z23__device_stub__assemblyPfS_S_y: # @_Z23__device_stub__assemblyPfS_S_y
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8assemblyPfS_S_y, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__assemblyPfS_S_y, .Lfunc_end1-_Z23__device_stub__assemblyPfS_S_y
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6configy
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x4038000000000000 # double 24
.LCPI2_3:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl _Z6configy
.p2align 4, 0x90
.type _Z6configy,@function
_Z6configy: # @_Z6configy
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
leaq -2(%rdi), %rbp
imulq $501, %rbp, %r15 # imm = 0x1F5
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r14
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, %r13
testq %rbp, %rbp
je .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl $2, %eax
subq %rbx, %rax
movq $-10, %rcx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
leaq (%rax,%rcx), %rdx
incq %rdx
incq %rcx
cmpq $-10, %rdx
je .LBB2_5
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1117782016, 40(%r14,%rcx,4) # imm = 0x42A00000
movl $1117782016, 40(%r13,%rcx,4) # imm = 0x42A00000
cmpq $20, %rcx
ja .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movl $1125515264, 40(%r14,%rcx,4) # imm = 0x43160000
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movabsq $103079215605, %r15 # imm = 0x18000001F5
movq %rbp, %xmm1
punpckldq .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI2_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %r12
movq %r12, %rax
subsd .LCPI2_3(%rip), %xmm0
cvttsd2si %xmm0, %rcx
sarq $63, %rax
andl %eax, %ecx
orl %ecx, %r12d
imulq $2004, %rbp, %rbp # imm = 0x7D4
leaq 104(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 96(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 88(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 88(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %ebp, %ebp
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
leaq 72(%rsp), %r13
leaq 112(%rsp), %r14
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_6 Depth=1
incq %rbp
cmpq $500, %rbp # imm = 0x1F4
je .LBB2_15
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
testb $1, %bpl
jne .LBB2_9
# %bb.7: # in Loop: Header=BB2_6 Depth=1
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.8: # in Loop: Header=BB2_6 Depth=1
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_6 Depth=1
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.10: # in Loop: Header=BB2_6 Depth=1
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
.LBB2_11: # in Loop: Header=BB2_6 Depth=1
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z8simulatePfS_y, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12: # in Loop: Header=BB2_6 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_6 Depth=1
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z8simulatePfS_y, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_14
.LBB2_15:
movq 96(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 104(%rsp), %r15
movq 88(%rsp), %r14
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
leaq (,%rbx,4), %rsi
leaq 152(%rsp), %rdi
callq hipMalloc
movabsq $4294967296, %rdi # imm = 0x100000000
incq %rdi
movabsq $2199023256053, %rdx # imm = 0x200000001F5
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movq 152(%rsp), %rax
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rax, 48(%rsp)
movq %rbx, 40(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8assemblyPfS_S_y, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_17:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq 152(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6configy, .Lfunc_end2-_Z6configy
.cfi_endproc
# -- End function
.globl _Z3avgPfy # -- Begin function _Z3avgPfy
.p2align 4, 0x90
.type _Z3avgPfy,@function
_Z3avgPfy: # @_Z3avgPfy
.cfi_startproc
# %bb.0:
imulq %rsi, %rsi
xorps %xmm0, %xmm0
testq %rsi, %rsi
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdi,%rax,4), %xmm0
incq %rax
cmpq %rax, %rsi
jne .LBB3_2
.LBB3_3: # %._crit_edge
testq %rsi, %rsi
js .LBB3_4
# %bb.5: # %._crit_edge
cvtsi2ss %rsi, %xmm1
divss %xmm1, %xmm0
retq
.LBB3_4:
movq %rsi, %rax
shrq %rax
andl $1, %esi
orq %rax, %rsi
cvtsi2ss %rsi, %xmm1
addss %xmm1, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end3:
.size _Z3avgPfy, .Lfunc_end3-_Z3avgPfy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $1, %edi
jle .LBB4_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rdi
incq %rdi
callq _Z6configy
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8simulatePfS_y, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8assemblyPfS_S_y, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8simulatePfS_y,@object # @_Z8simulatePfS_y
.section .rodata,"a",@progbits
.globl _Z8simulatePfS_y
.p2align 3, 0x0
_Z8simulatePfS_y:
.quad _Z23__device_stub__simulatePfS_y
.size _Z8simulatePfS_y, 8
.type _Z8assemblyPfS_S_y,@object # @_Z8assemblyPfS_S_y
.globl _Z8assemblyPfS_S_y
.p2align 3, 0x0
_Z8assemblyPfS_S_y:
.quad _Z23__device_stub__assemblyPfS_S_y
.size _Z8assemblyPfS_S_y, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "peek "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "loaded"
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "simulated"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "assemblied"
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8simulatePfS_y"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8assemblyPfS_S_y"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please indicate matrix size."
.size .Lstr, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__simulatePfS_y
.addrsig_sym _Z23__device_stub__assemblyPfS_S_y
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8simulatePfS_y
.addrsig_sym _Z8assemblyPfS_S_y
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computeCost(const double *Params, const float *uproj, const float *mu, const float *W, const int *ioff, const bool *iW, float *cmax){
int tid, bid, Nspikes, Nfeatures, NfeatW, Nthreads, k;
float xsum = 0.0f, Ci, lam;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
NfeatW = (int) Params[4];
Nthreads = blockDim.x;
lam = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
while(tid<Nspikes){
if (iW[tid + bid*Nspikes]){
xsum = 0.0f;
for (k=0;k<Nfeatures;k++)
xsum += uproj[k + Nfeatures * tid] * W[k + ioff[tid] + NfeatW * bid];
Ci = max(0.0f, xsum) + lam/mu[bid];
cmax[tid + bid*Nspikes] = Ci * Ci / (1.0f + lam/(mu[bid] * mu[bid])) - lam;
}
tid+= Nthreads;
}
} | .file "tmpxft_001288ba_00000000-6_computeCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf
.type _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf, @function
_Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11computeCostPKdPKfS2_S2_PKiPKbPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf, .-_Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf
.globl _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.type _Z11computeCostPKdPKfS2_S2_PKiPKbPf, @function
_Z11computeCostPKdPKfS2_S2_PKiPKbPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11computeCostPKdPKfS2_S2_PKiPKbPf, .-_Z11computeCostPKdPKfS2_S2_PKiPKbPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11computeCostPKdPKfS2_S2_PKiPKbPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11computeCostPKdPKfS2_S2_PKiPKbPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computeCost(const double *Params, const float *uproj, const float *mu, const float *W, const int *ioff, const bool *iW, float *cmax){
int tid, bid, Nspikes, Nfeatures, NfeatW, Nthreads, k;
float xsum = 0.0f, Ci, lam;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
NfeatW = (int) Params[4];
Nthreads = blockDim.x;
lam = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
while(tid<Nspikes){
if (iW[tid + bid*Nspikes]){
xsum = 0.0f;
for (k=0;k<Nfeatures;k++)
xsum += uproj[k + Nfeatures * tid] * W[k + ioff[tid] + NfeatW * bid];
Ci = max(0.0f, xsum) + lam/mu[bid];
cmax[tid + bid*Nspikes] = Ci * Ci / (1.0f + lam/(mu[bid] * mu[bid])) - lam;
}
tid+= Nthreads;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeCost(const double *Params, const float *uproj, const float *mu, const float *W, const int *ioff, const bool *iW, float *cmax){
int tid, bid, Nspikes, Nfeatures, NfeatW, Nthreads, k;
float xsum = 0.0f, Ci, lam;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
NfeatW = (int) Params[4];
Nthreads = blockDim.x;
lam = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
while(tid<Nspikes){
if (iW[tid + bid*Nspikes]){
xsum = 0.0f;
for (k=0;k<Nfeatures;k++)
xsum += uproj[k + Nfeatures * tid] * W[k + ioff[tid] + NfeatW * bid];
Ci = max(0.0f, xsum) + lam/mu[bid];
cmax[tid + bid*Nspikes] = Ci * Ci / (1.0f + lam/(mu[bid] * mu[bid])) - lam;
}
tid+= Nthreads;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeCost(const double *Params, const float *uproj, const float *mu, const float *W, const int *ioff, const bool *iW, float *cmax){
int tid, bid, Nspikes, Nfeatures, NfeatW, Nthreads, k;
float xsum = 0.0f, Ci, lam;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
NfeatW = (int) Params[4];
Nthreads = blockDim.x;
lam = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
while(tid<Nspikes){
if (iW[tid + bid*Nspikes]){
xsum = 0.0f;
for (k=0;k<Nfeatures;k++)
xsum += uproj[k + Nfeatures * tid] * W[k + ioff[tid] + NfeatW * bid];
Ci = max(0.0f, xsum) + lam/mu[bid];
cmax[tid + bid*Nspikes] = Ci * Ci / (1.0f + lam/(mu[bid] * mu[bid])) - lam;
}
tid+= Nthreads;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.globl _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.p2align 8
.type _Z11computeCostPKdPKfS2_S2_PKiPKbPf,@function
_Z11computeCostPKdPKfS2_S2_PKiPKbPf:
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v10, s[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v0, v10
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b128 s[8:11], s[4:5], 0x20
s_load_b64 s[4:5], s[4:5], 0x8
s_mov_b32 s2, s15
v_mov_b32_e32 v16, 0
v_mul_lo_u32 v13, s2, v10
s_ashr_i32 s3, s2, 31
s_mov_b32 s17, 0
s_lshl_b64 s[18:19], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[8:9]
v_cvt_i32_f64_e32 v11, s[4:5]
v_cvt_f32_f64_e32 v12, s[10:11]
s_clause 0x2
s_load_b32 s16, s[0:1], 0x44
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b128 s[12:15], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s16, 0xffff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v14, s2, v1
v_mul_lo_u32 v2, v0, v11
v_mul_lo_u32 v15, v11, s16
v_cmp_lt_i32_e64 s0, 0, v11
s_add_u32 s2, s6, s18
s_addc_u32 s3, s7, s19
s_branch .LBB0_5
.LBB0_2:
v_mov_b32_e32 v1, 0
.LBB0_3:
global_load_b32 v3, v16, s[2:3]
v_max_f32_e32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_max_f32_e32 v1, 0, v1
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v3, v3, v12
v_div_scale_f32 v19, vcc_lo, v12, v3, v12
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v3, v3 :: v_dual_fmac_f32 v8, v18, v8
v_div_scale_f32 v9, null, v7, v7, v12
v_div_scale_f32 v21, s1, v12, v7, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v17, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v9, v17, 1.0
v_dual_mul_f32 v20, v19, v8 :: v_dual_fmac_f32 v17, v18, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v18, -v6, v20, v19
v_mul_f32_e32 v22, v21, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v20, v18, v8
v_fma_f32 v18, -v9, v22, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v20, v19
v_div_fmas_f32 v6, v6, v8, v20
s_mov_b32 vcc_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v6, v3, v12
v_dual_fmac_f32 v22, v18, v17 :: v_dual_add_f32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v9, v22, v21
v_mul_f32_e32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v8, v17, v22
v_div_fixup_f32 v3, v6, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_div_scale_f32 v6, null, v3, v3, v1
v_div_scale_f32 v9, vcc_lo, v1, v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v17, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v17, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
v_div_fixup_f32 v1, v6, v3, v1
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v1, v1, v12
v_add_co_u32 v3, vcc_lo, s14, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
global_store_b32 v[3:4], v1, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v0, s16, v0
v_add_nc_u32_e32 v2, v2, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v10
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_9
.LBB0_5:
v_add_nc_u32_e32 v4, v0, v13
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v6, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
global_load_u8 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v1
s_cbranch_execz .LBB0_4
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v3
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v7, vcc_lo
global_load_b32 v8, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, v14, v8
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_mov_b32_e32 v3, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.p2align 6
.LBB0_8:
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -1, v3
v_lshlrev_b64 v[17:18], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s1, 0, v3
v_add_co_u32 v17, vcc_lo, s8, v17
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
global_load_b32 v9, v[6:7], off
global_load_b32 v17, v[17:18], off
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_nc_u32_e32 v8, 1, v8
s_and_b32 vcc_lo, exec_lo, s1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v9, v17
s_cbranch_vccnz .LBB0_8
s_branch .LBB0_3
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11computeCostPKdPKfS2_S2_PKiPKbPf, .Lfunc_end0-_Z11computeCostPKdPKfS2_S2_PKiPKbPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z11computeCostPKdPKfS2_S2_PKiPKbPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeCost(const double *Params, const float *uproj, const float *mu, const float *W, const int *ioff, const bool *iW, float *cmax){
int tid, bid, Nspikes, Nfeatures, NfeatW, Nthreads, k;
float xsum = 0.0f, Ci, lam;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
NfeatW = (int) Params[4];
Nthreads = blockDim.x;
lam = (float) Params[5];
tid = threadIdx.x;
bid = blockIdx.x;
while(tid<Nspikes){
if (iW[tid + bid*Nspikes]){
xsum = 0.0f;
for (k=0;k<Nfeatures;k++)
xsum += uproj[k + Nfeatures * tid] * W[k + ioff[tid] + NfeatW * bid];
Ci = max(0.0f, xsum) + lam/mu[bid];
cmax[tid + bid*Nspikes] = Ci * Ci / (1.0f + lam/(mu[bid] * mu[bid])) - lam;
}
tid+= Nthreads;
}
} | .text
.file "computeCost.hip"
.globl _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf # -- Begin function _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.p2align 4, 0x90
.type _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf,@function
_Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf: # @_Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11computeCostPKdPKfS2_S2_PKiPKbPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf, .Lfunc_end0-_Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11computeCostPKdPKfS2_S2_PKiPKbPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11computeCostPKdPKfS2_S2_PKiPKbPf,@object # @_Z11computeCostPKdPKfS2_S2_PKiPKbPf
.section .rodata,"a",@progbits
.globl _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.p2align 3, 0x0
_Z11computeCostPKdPKfS2_S2_PKiPKbPf:
.quad _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.size _Z11computeCostPKdPKfS2_S2_PKiPKbPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11computeCostPKdPKfS2_S2_PKiPKbPf"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001288ba_00000000-6_computeCost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf
.type _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf, @function
_Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11computeCostPKdPKfS2_S2_PKiPKbPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf, .-_Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf
.globl _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.type _Z11computeCostPKdPKfS2_S2_PKiPKbPf, @function
_Z11computeCostPKdPKfS2_S2_PKiPKbPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z11computeCostPKdPKfS2_S2_PKiPKbPfPKdPKfS2_S2_PKiPKbPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11computeCostPKdPKfS2_S2_PKiPKbPf, .-_Z11computeCostPKdPKfS2_S2_PKiPKbPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11computeCostPKdPKfS2_S2_PKiPKbPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11computeCostPKdPKfS2_S2_PKiPKbPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computeCost.hip"
.globl _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf # -- Begin function _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.p2align 4, 0x90
.type _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf,@function
_Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf: # @_Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11computeCostPKdPKfS2_S2_PKiPKbPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf, .Lfunc_end0-_Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11computeCostPKdPKfS2_S2_PKiPKbPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11computeCostPKdPKfS2_S2_PKiPKbPf,@object # @_Z11computeCostPKdPKfS2_S2_PKiPKbPf
.section .rodata,"a",@progbits
.globl _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.p2align 3, 0x0
_Z11computeCostPKdPKfS2_S2_PKiPKbPf:
.quad _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.size _Z11computeCostPKdPKfS2_S2_PKiPKbPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11computeCostPKdPKfS2_S2_PKiPKbPf"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__computeCostPKdPKfS2_S2_PKiPKbPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11computeCostPKdPKfS2_S2_PKiPKbPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include "Queue.cuh"
Queue** createQueue(int width, int height){
Queue** queue=(Queue**)calloc(1, sizeof(Queue*));
*queue=(Queue*)calloc(1, sizeof(Queue));
(*queue)->width=width;
(*queue)->height=height;
(*queue)->entries=0;
(*queue)->queue=(int**)calloc(height, sizeof(int*));
for(int entry=0; entry<height; entry++){
(*queue)->queue[entry]=(int*)calloc(width, sizeof(int));
}
return queue;
}
void copyValuesBetweenQueues(Queue** queue1, Queue** queue2){
for(int entry=0; entry<(*queue1)->height; entry++){
for(int value=0; value<(*queue1)->width; value++){
(*queue2)->queue[entry][value]=(*queue1)->queue[entry][value];
}
}
(*queue2)->entries=(*queue1)->entries;
}
void freeQueue(Queue** queue){
for(int entry=0; entry<(*queue)->height; entry++){
free((*queue)->queue[entry]);
}
free((*queue)->queue);
free(*queue);
free(queue);
}
void extendQueue(Queue** queue, int newWidth, int newHeight){
Queue** queueHolder=createQueue(newWidth, newHeight);
copyValuesBetweenQueues(queue, queueHolder);
*queue=*queueHolder;
free(queueHolder);
}
void freeEntryFromQueue(int* entry){
free(entry);
}
int isEmpty(Queue** queue){
return (*queue)->entries==0;
}
void insertToQueue(Queue** queue, int* entry){
if((*queue)->entries==(*queue)->height){
extendQueue(queue, (*queue)->width, (*queue)->height*2);
}
for(int value=0; value<(*queue)->width; value++){
(*queue)->queue[(*queue)->entries][value]=entry[value];
}
(*queue)->entries++;
freeEntryFromQueue(entry);
}
int* peekFromQueue(Queue** queue, int entryNum){
return (*queue)->queue[entryNum];
}
int* popFromQueue(Queue** queue, int entryNum){
int* returnedEntry=(int*)calloc((*queue)->width, sizeof(int));
for(int value=0; value<(*queue)->width; value++){
returnedEntry[value]=(*queue)->queue[entryNum][value];
}
(*queue)->entries--;
for(int entry=entryNum; entry<(*queue)->entries; entry++){
for(int value=0; value<(*queue)->width; value++){
(*queue)->queue[entry][value]=(*queue)->queue[entry+1][value];
}
}
return returnedEntry;
}
int* popRandomEntryFromQueue(Queue** queue){
int entry=(int)((((double)rand())/(RAND_MAX+1))*(*queue)->entries);
return popFromQueue(queue, entry);
}
void printQueueData(Queue** queue){
printf("Width %d, Height %d, entries %d\n", (*queue)->width, (*queue)->height, (*queue)->entries);
for(int entry=0; entry<(*queue)->height; entry++){
printf("Entry %d \t", entry);
for(int value=0; value<(*queue)->width; value++){
printf("%d ", (*queue)->queue[entry][value]);
}
printf("\n");
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "Queue.cuh"
Queue** createQueue(int width, int height){
Queue** queue=(Queue**)calloc(1, sizeof(Queue*));
*queue=(Queue*)calloc(1, sizeof(Queue));
(*queue)->width=width;
(*queue)->height=height;
(*queue)->entries=0;
(*queue)->queue=(int**)calloc(height, sizeof(int*));
for(int entry=0; entry<height; entry++){
(*queue)->queue[entry]=(int*)calloc(width, sizeof(int));
}
return queue;
}
void copyValuesBetweenQueues(Queue** queue1, Queue** queue2){
for(int entry=0; entry<(*queue1)->height; entry++){
for(int value=0; value<(*queue1)->width; value++){
(*queue2)->queue[entry][value]=(*queue1)->queue[entry][value];
}
}
(*queue2)->entries=(*queue1)->entries;
}
void freeQueue(Queue** queue){
for(int entry=0; entry<(*queue)->height; entry++){
free((*queue)->queue[entry]);
}
free((*queue)->queue);
free(*queue);
free(queue);
}
void extendQueue(Queue** queue, int newWidth, int newHeight){
Queue** queueHolder=createQueue(newWidth, newHeight);
copyValuesBetweenQueues(queue, queueHolder);
*queue=*queueHolder;
free(queueHolder);
}
void freeEntryFromQueue(int* entry){
free(entry);
}
int isEmpty(Queue** queue){
return (*queue)->entries==0;
}
void insertToQueue(Queue** queue, int* entry){
if((*queue)->entries==(*queue)->height){
extendQueue(queue, (*queue)->width, (*queue)->height*2);
}
for(int value=0; value<(*queue)->width; value++){
(*queue)->queue[(*queue)->entries][value]=entry[value];
}
(*queue)->entries++;
freeEntryFromQueue(entry);
}
int* peekFromQueue(Queue** queue, int entryNum){
return (*queue)->queue[entryNum];
}
int* popFromQueue(Queue** queue, int entryNum){
int* returnedEntry=(int*)calloc((*queue)->width, sizeof(int));
for(int value=0; value<(*queue)->width; value++){
returnedEntry[value]=(*queue)->queue[entryNum][value];
}
(*queue)->entries--;
for(int entry=entryNum; entry<(*queue)->entries; entry++){
for(int value=0; value<(*queue)->width; value++){
(*queue)->queue[entry][value]=(*queue)->queue[entry+1][value];
}
}
return returnedEntry;
}
int* popRandomEntryFromQueue(Queue** queue){
int entry=(int)((((double)rand())/(RAND_MAX+1))*(*queue)->entries);
return popFromQueue(queue, entry);
}
void printQueueData(Queue** queue){
printf("Width %d, Height %d, entries %d\n", (*queue)->width, (*queue)->height, (*queue)->entries);
for(int entry=0; entry<(*queue)->height; entry++){
printf("Entry %d \t", entry);
for(int value=0; value<(*queue)->width; value++){
printf("%d ", (*queue)->queue[entry][value]);
}
printf("\n");
}
} | .file "tmpxft_000a7c1d_00000000-6_Queue.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11createQueueii
.type _Z11createQueueii, @function
_Z11createQueueii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebp
movl %esi, %r12d
movl $8, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r13
movl $24, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %rbx
movq %rax, 0(%r13)
movl %ebp, 4(%rax)
movl %r12d, (%rax)
movl $0, 16(%rax)
movslq %r12d, %r14
movl $8, %esi
movq %r14, %rdi
call calloc@PLT
movq %rax, 8(%rbx)
testl %r12d, %r12d
jle .L3
movq %rax, %rbx
leaq (%rax,%r14,8), %r12
movslq %ebp, %rbp
.L5:
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L5
.L3:
movq %r13, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11createQueueii, .-_Z11createQueueii
.globl _Z23copyValuesBetweenQueuesPP1qS1_
.type _Z23copyValuesBetweenQueuesPP1qS1_, @function
_Z23copyValuesBetweenQueuesPP1qS1_:
.LFB2058:
.cfi_startproc
endbr64
movq (%rdi), %rax
movl $0, %r9d
cmpl $0, (%rax)
jg .L9
.L10:
movq (%rsi), %rdx
movl 16(%rax), %eax
movl %eax, 16(%rdx)
ret
.L11:
movq 8(%rdx), %rdx
movq (%rdx,%rcx), %rdx
movl (%rdx,%rax,4), %r8d
movq (%rsi), %rdx
movq 8(%rdx), %rdx
movq (%rdx,%rcx), %rdx
movl %r8d, (%rdx,%rax,4)
movq (%rdi), %rdx
addq $1, %rax
cmpl %eax, 4(%rdx)
jg .L11
.L13:
movq (%rdi), %rax
addq $1, %r9
cmpl %r9d, (%rax)
jle .L10
.L9:
movq (%rdi), %rdx
leaq 0(,%r9,8), %rcx
movl $0, %eax
cmpl $0, 4(%rdx)
jg .L11
jmp .L13
.cfi_endproc
.LFE2058:
.size _Z23copyValuesBetweenQueuesPP1qS1_, .-_Z23copyValuesBetweenQueuesPP1qS1_
.globl _Z9freeQueuePP1q
.type _Z9freeQueuePP1q, @function
_Z9freeQueuePP1q:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq (%rdi), %rax
cmpl $0, (%rax)
jle .L19
movl $0, %ebx
.L20:
movq 8(%rax), %rax
movq (%rax,%rbx,8), %rdi
call free@PLT
movq 0(%rbp), %rax
addq $1, %rbx
cmpl %ebx, (%rax)
jg .L20
.L19:
movq 8(%rax), %rdi
call free@PLT
movq 0(%rbp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z9freeQueuePP1q, .-_Z9freeQueuePP1q
.globl _Z11extendQueuePP1qii
.type _Z11extendQueuePP1qii, @function
_Z11extendQueuePP1qii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl %esi, %edi
movl %edx, %esi
call _Z11createQueueii
movq %rax, %rbx
movq %rax, %rsi
movq %rbp, %rdi
call _Z23copyValuesBetweenQueuesPP1qS1_
movq (%rbx), %rax
movq %rax, 0(%rbp)
movq %rbx, %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z11extendQueuePP1qii, .-_Z11extendQueuePP1qii
.globl _Z18freeEntryFromQueuePi
.type _Z18freeEntryFromQueuePi, @function
_Z18freeEntryFromQueuePi:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z18freeEntryFromQueuePi, .-_Z18freeEntryFromQueuePi
.globl _Z7isEmptyPP1q
.type _Z7isEmptyPP1q, @function
_Z7isEmptyPP1q:
.LFB2062:
.cfi_startproc
endbr64
movq (%rdi), %rax
cmpl $0, 16(%rax)
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z7isEmptyPP1q, .-_Z7isEmptyPP1q
.globl _Z13insertToQueuePP1qPi
.type _Z13insertToQueuePP1qPi, @function
_Z13insertToQueuePP1qPi:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movq (%rdi), %rax
movl (%rax), %edx
cmpl %edx, 16(%rax)
je .L34
.L29:
movq (%rbx), %rdx
cmpl $0, 4(%rdx)
jle .L30
movl $0, %eax
.L31:
movl 0(%rbp,%rax,4), %ecx
movslq 16(%rdx), %rsi
movq 8(%rdx), %rdx
movq (%rdx,%rsi,8), %rdx
movl %ecx, (%rdx,%rax,4)
movq (%rbx), %rdx
addq $1, %rax
cmpl %eax, 4(%rdx)
jg .L31
.L30:
addl $1, 16(%rdx)
movq %rbp, %rdi
call free@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
addl %edx, %edx
movl 4(%rax), %esi
call _Z11extendQueuePP1qii
jmp .L29
.cfi_endproc
.LFE2063:
.size _Z13insertToQueuePP1qPi, .-_Z13insertToQueuePP1qPi
.globl _Z13peekFromQueuePP1qi
.type _Z13peekFromQueuePP1qi, @function
_Z13peekFromQueuePP1qi:
.LFB2064:
.cfi_startproc
endbr64
movq (%rdi), %rax
movslq %esi, %rsi
movq 8(%rax), %rax
movq (%rax,%rsi,8), %rax
ret
.cfi_endproc
.LFE2064:
.size _Z13peekFromQueuePP1qi, .-_Z13peekFromQueuePP1qi
.globl _Z12popFromQueuePP1qi
.type _Z12popFromQueuePP1qi, @function
_Z12popFromQueuePP1qi:
.LFB2065:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %esi, %ebp
movq (%rdi), %r12
movl 4(%r12), %r13d
movslq %r13d, %rdi
movl $4, %esi
call calloc@PLT
movq %rax, %r8
testl %r13d, %r13d
jle .L37
movslq %ebp, %rcx
salq $3, %rcx
movl $0, %eax
.L38:
movq 8(%r12), %rdx
movq (%rdx,%rcx), %rdx
movl (%rdx,%rax,4), %edx
movl %edx, (%r8,%rax,4)
addq $1, %rax
cmpl %eax, 4(%r12)
jg .L38
.L37:
subl $1, 16(%r12)
movq (%rbx), %rax
cmpl 16(%rax), %ebp
jge .L36
movslq %ebp, %rax
leaq 8(,%rax,8), %rsi
jmp .L40
.L41:
movq 8(%rdx), %rdx
movq (%rdx,%rsi), %rcx
movl (%rcx,%rax,4), %ecx
movq (%rdx,%rdi), %rdx
movl %ecx, (%rdx,%rax,4)
movq (%rbx), %rdx
addq $1, %rax
cmpl %eax, 4(%rdx)
jg .L41
.L43:
addl $1, %ebp
addq $8, %rsi
movq (%rbx), %rax
cmpl %ebp, 16(%rax)
jle .L36
.L40:
movq (%rbx), %rdx
leaq -8(%rsi), %rdi
movl $0, %eax
cmpl $0, 4(%rdx)
jg .L41
jmp .L43
.L36:
movq %r8, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z12popFromQueuePP1qi, .-_Z12popFromQueuePP1qi
.globl _Z23popRandomEntryFromQueuePP1q
.type _Z23popRandomEntryFromQueuePP1q, @function
_Z23popRandomEntryFromQueuePP1q:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call rand@PLT
movq (%rbx), %rdx
pxor %xmm0, %xmm0
cvtsi2sdl 16(%rdx), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd .LC0(%rip), %xmm1
mulsd %xmm1, %xmm0
cvttsd2sil %xmm0, %esi
movq %rbx, %rdi
call _Z12popFromQueuePP1qi
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z23popRandomEntryFromQueuePP1q, .-_Z23popRandomEntryFromQueuePP1q
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Width %d, Height %d, entries %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Entry %d \t"
.LC3:
.string "%d "
.LC4:
.string "\n"
.text
.globl _Z14printQueueDataPP1q
.type _Z14printQueueDataPP1q, @function
_Z14printQueueDataPP1q:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq (%rdi), %rax
movl (%rax), %ecx
movl 4(%rax), %edx
movl 16(%rax), %r8d
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 0(%rbp), %rax
cmpl $0, (%rax)
jle .L50
movl $0, %r14d
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r13
.L54:
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 0(%rbp), %rax
cmpl $0, 4(%rax)
jle .L52
leaq 0(,%r14,8), %r12
movl $0, %ebx
.L53:
movq 8(%rax), %rax
movq (%rax,%r12), %rax
movl (%rax,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 0(%rbp), %rax
addq $1, %rbx
cmpl %ebx, 4(%rax)
jg .L53
.L52:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
movq 0(%rbp), %rax
cmpl %r14d, (%rax)
jg .L54
.L50:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _Z14printQueueDataPP1q, .-_Z14printQueueDataPP1q
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1107296256
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "Queue.cuh"
Queue** createQueue(int width, int height){
Queue** queue=(Queue**)calloc(1, sizeof(Queue*));
*queue=(Queue*)calloc(1, sizeof(Queue));
(*queue)->width=width;
(*queue)->height=height;
(*queue)->entries=0;
(*queue)->queue=(int**)calloc(height, sizeof(int*));
for(int entry=0; entry<height; entry++){
(*queue)->queue[entry]=(int*)calloc(width, sizeof(int));
}
return queue;
}
void copyValuesBetweenQueues(Queue** queue1, Queue** queue2){
for(int entry=0; entry<(*queue1)->height; entry++){
for(int value=0; value<(*queue1)->width; value++){
(*queue2)->queue[entry][value]=(*queue1)->queue[entry][value];
}
}
(*queue2)->entries=(*queue1)->entries;
}
void freeQueue(Queue** queue){
for(int entry=0; entry<(*queue)->height; entry++){
free((*queue)->queue[entry]);
}
free((*queue)->queue);
free(*queue);
free(queue);
}
void extendQueue(Queue** queue, int newWidth, int newHeight){
Queue** queueHolder=createQueue(newWidth, newHeight);
copyValuesBetweenQueues(queue, queueHolder);
*queue=*queueHolder;
free(queueHolder);
}
void freeEntryFromQueue(int* entry){
free(entry);
}
int isEmpty(Queue** queue){
return (*queue)->entries==0;
}
void insertToQueue(Queue** queue, int* entry){
if((*queue)->entries==(*queue)->height){
extendQueue(queue, (*queue)->width, (*queue)->height*2);
}
for(int value=0; value<(*queue)->width; value++){
(*queue)->queue[(*queue)->entries][value]=entry[value];
}
(*queue)->entries++;
freeEntryFromQueue(entry);
}
int* peekFromQueue(Queue** queue, int entryNum){
return (*queue)->queue[entryNum];
}
int* popFromQueue(Queue** queue, int entryNum){
int* returnedEntry=(int*)calloc((*queue)->width, sizeof(int));
for(int value=0; value<(*queue)->width; value++){
returnedEntry[value]=(*queue)->queue[entryNum][value];
}
(*queue)->entries--;
for(int entry=entryNum; entry<(*queue)->entries; entry++){
for(int value=0; value<(*queue)->width; value++){
(*queue)->queue[entry][value]=(*queue)->queue[entry+1][value];
}
}
return returnedEntry;
}
int* popRandomEntryFromQueue(Queue** queue){
int entry=(int)((((double)rand())/(RAND_MAX+1))*(*queue)->entries);
return popFromQueue(queue, entry);
}
void printQueueData(Queue** queue){
printf("Width %d, Height %d, entries %d\n", (*queue)->width, (*queue)->height, (*queue)->entries);
for(int entry=0; entry<(*queue)->height; entry++){
printf("Entry %d \t", entry);
for(int value=0; value<(*queue)->width; value++){
printf("%d ", (*queue)->queue[entry][value]);
}
printf("\n");
}
} | #ifndef QUEUE_CUH
#define QUEUE_CUH
typedef struct q{
int height;
int width;
int** queue;
int entries;
}Queue;
Queue** createQueue(int width, int height);
void freeQueue(Queue** queue);
void freeEntryFromQueue(int* entry);
int isEmpty(Queue** queue);
void insertToQueue(Queue** queue, int* entry);
int* peekFromQueue(Queue** queue, int entryNum);
int* popFromQueue(Queue** queue, int entryNum);
int* popRandomEntryFromQueue(Queue** queue);
void printQueueData(Queue** queue);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef QUEUE_CUH
#define QUEUE_CUH
typedef struct q{
int height;
int width;
int** queue;
int entries;
}Queue;
Queue** createQueue(int width, int height);
void freeQueue(Queue** queue);
void freeEntryFromQueue(int* entry);
int isEmpty(Queue** queue);
void insertToQueue(Queue** queue, int* entry);
int* peekFromQueue(Queue** queue, int entryNum);
int* popFromQueue(Queue** queue, int entryNum);
int* popRandomEntryFromQueue(Queue** queue);
void printQueueData(Queue** queue);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef QUEUE_CUH
#define QUEUE_CUH
typedef struct q{
int height;
int width;
int** queue;
int entries;
}Queue;
Queue** createQueue(int width, int height);
void freeQueue(Queue** queue);
void freeEntryFromQueue(int* entry);
int isEmpty(Queue** queue);
void insertToQueue(Queue** queue, int* entry);
int* peekFromQueue(Queue** queue, int entryNum);
int* popFromQueue(Queue** queue, int entryNum);
int* popRandomEntryFromQueue(Queue** queue);
void printQueueData(Queue** queue);
#endif | .text
.file "Queue.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a7c1d_00000000-6_Queue.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11createQueueii
.type _Z11createQueueii, @function
_Z11createQueueii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebp
movl %esi, %r12d
movl $8, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r13
movl $24, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %rbx
movq %rax, 0(%r13)
movl %ebp, 4(%rax)
movl %r12d, (%rax)
movl $0, 16(%rax)
movslq %r12d, %r14
movl $8, %esi
movq %r14, %rdi
call calloc@PLT
movq %rax, 8(%rbx)
testl %r12d, %r12d
jle .L3
movq %rax, %rbx
leaq (%rax,%r14,8), %r12
movslq %ebp, %rbp
.L5:
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L5
.L3:
movq %r13, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11createQueueii, .-_Z11createQueueii
.globl _Z23copyValuesBetweenQueuesPP1qS1_
.type _Z23copyValuesBetweenQueuesPP1qS1_, @function
_Z23copyValuesBetweenQueuesPP1qS1_:
.LFB2058:
.cfi_startproc
endbr64
movq (%rdi), %rax
movl $0, %r9d
cmpl $0, (%rax)
jg .L9
.L10:
movq (%rsi), %rdx
movl 16(%rax), %eax
movl %eax, 16(%rdx)
ret
.L11:
movq 8(%rdx), %rdx
movq (%rdx,%rcx), %rdx
movl (%rdx,%rax,4), %r8d
movq (%rsi), %rdx
movq 8(%rdx), %rdx
movq (%rdx,%rcx), %rdx
movl %r8d, (%rdx,%rax,4)
movq (%rdi), %rdx
addq $1, %rax
cmpl %eax, 4(%rdx)
jg .L11
.L13:
movq (%rdi), %rax
addq $1, %r9
cmpl %r9d, (%rax)
jle .L10
.L9:
movq (%rdi), %rdx
leaq 0(,%r9,8), %rcx
movl $0, %eax
cmpl $0, 4(%rdx)
jg .L11
jmp .L13
.cfi_endproc
.LFE2058:
.size _Z23copyValuesBetweenQueuesPP1qS1_, .-_Z23copyValuesBetweenQueuesPP1qS1_
.globl _Z9freeQueuePP1q
.type _Z9freeQueuePP1q, @function
_Z9freeQueuePP1q:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq (%rdi), %rax
cmpl $0, (%rax)
jle .L19
movl $0, %ebx
.L20:
movq 8(%rax), %rax
movq (%rax,%rbx,8), %rdi
call free@PLT
movq 0(%rbp), %rax
addq $1, %rbx
cmpl %ebx, (%rax)
jg .L20
.L19:
movq 8(%rax), %rdi
call free@PLT
movq 0(%rbp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z9freeQueuePP1q, .-_Z9freeQueuePP1q
.globl _Z11extendQueuePP1qii
.type _Z11extendQueuePP1qii, @function
_Z11extendQueuePP1qii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl %esi, %edi
movl %edx, %esi
call _Z11createQueueii
movq %rax, %rbx
movq %rax, %rsi
movq %rbp, %rdi
call _Z23copyValuesBetweenQueuesPP1qS1_
movq (%rbx), %rax
movq %rax, 0(%rbp)
movq %rbx, %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z11extendQueuePP1qii, .-_Z11extendQueuePP1qii
.globl _Z18freeEntryFromQueuePi
.type _Z18freeEntryFromQueuePi, @function
_Z18freeEntryFromQueuePi:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z18freeEntryFromQueuePi, .-_Z18freeEntryFromQueuePi
.globl _Z7isEmptyPP1q
.type _Z7isEmptyPP1q, @function
_Z7isEmptyPP1q:
.LFB2062:
.cfi_startproc
endbr64
movq (%rdi), %rax
cmpl $0, 16(%rax)
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z7isEmptyPP1q, .-_Z7isEmptyPP1q
.globl _Z13insertToQueuePP1qPi
.type _Z13insertToQueuePP1qPi, @function
_Z13insertToQueuePP1qPi:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movq (%rdi), %rax
movl (%rax), %edx
cmpl %edx, 16(%rax)
je .L34
.L29:
movq (%rbx), %rdx
cmpl $0, 4(%rdx)
jle .L30
movl $0, %eax
.L31:
movl 0(%rbp,%rax,4), %ecx
movslq 16(%rdx), %rsi
movq 8(%rdx), %rdx
movq (%rdx,%rsi,8), %rdx
movl %ecx, (%rdx,%rax,4)
movq (%rbx), %rdx
addq $1, %rax
cmpl %eax, 4(%rdx)
jg .L31
.L30:
addl $1, 16(%rdx)
movq %rbp, %rdi
call free@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
addl %edx, %edx
movl 4(%rax), %esi
call _Z11extendQueuePP1qii
jmp .L29
.cfi_endproc
.LFE2063:
.size _Z13insertToQueuePP1qPi, .-_Z13insertToQueuePP1qPi
.globl _Z13peekFromQueuePP1qi
.type _Z13peekFromQueuePP1qi, @function
_Z13peekFromQueuePP1qi:
.LFB2064:
.cfi_startproc
endbr64
movq (%rdi), %rax
movslq %esi, %rsi
movq 8(%rax), %rax
movq (%rax,%rsi,8), %rax
ret
.cfi_endproc
.LFE2064:
.size _Z13peekFromQueuePP1qi, .-_Z13peekFromQueuePP1qi
.globl _Z12popFromQueuePP1qi
.type _Z12popFromQueuePP1qi, @function
_Z12popFromQueuePP1qi:
.LFB2065:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl %esi, %ebp
movq (%rdi), %r12
movl 4(%r12), %r13d
movslq %r13d, %rdi
movl $4, %esi
call calloc@PLT
movq %rax, %r8
testl %r13d, %r13d
jle .L37
movslq %ebp, %rcx
salq $3, %rcx
movl $0, %eax
.L38:
movq 8(%r12), %rdx
movq (%rdx,%rcx), %rdx
movl (%rdx,%rax,4), %edx
movl %edx, (%r8,%rax,4)
addq $1, %rax
cmpl %eax, 4(%r12)
jg .L38
.L37:
subl $1, 16(%r12)
movq (%rbx), %rax
cmpl 16(%rax), %ebp
jge .L36
movslq %ebp, %rax
leaq 8(,%rax,8), %rsi
jmp .L40
.L41:
movq 8(%rdx), %rdx
movq (%rdx,%rsi), %rcx
movl (%rcx,%rax,4), %ecx
movq (%rdx,%rdi), %rdx
movl %ecx, (%rdx,%rax,4)
movq (%rbx), %rdx
addq $1, %rax
cmpl %eax, 4(%rdx)
jg .L41
.L43:
addl $1, %ebp
addq $8, %rsi
movq (%rbx), %rax
cmpl %ebp, 16(%rax)
jle .L36
.L40:
movq (%rbx), %rdx
leaq -8(%rsi), %rdi
movl $0, %eax
cmpl $0, 4(%rdx)
jg .L41
jmp .L43
.L36:
movq %r8, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z12popFromQueuePP1qi, .-_Z12popFromQueuePP1qi
.globl _Z23popRandomEntryFromQueuePP1q
.type _Z23popRandomEntryFromQueuePP1q, @function
_Z23popRandomEntryFromQueuePP1q:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call rand@PLT
movq (%rbx), %rdx
pxor %xmm0, %xmm0
cvtsi2sdl 16(%rdx), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd .LC0(%rip), %xmm1
mulsd %xmm1, %xmm0
cvttsd2sil %xmm0, %esi
movq %rbx, %rdi
call _Z12popFromQueuePP1qi
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z23popRandomEntryFromQueuePP1q, .-_Z23popRandomEntryFromQueuePP1q
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Width %d, Height %d, entries %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Entry %d \t"
.LC3:
.string "%d "
.LC4:
.string "\n"
.text
.globl _Z14printQueueDataPP1q
.type _Z14printQueueDataPP1q, @function
_Z14printQueueDataPP1q:
.LFB2067:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq (%rdi), %rax
movl (%rax), %ecx
movl 4(%rax), %edx
movl 16(%rax), %r8d
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 0(%rbp), %rax
cmpl $0, (%rax)
jle .L50
movl $0, %r14d
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r13
.L54:
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 0(%rbp), %rax
cmpl $0, 4(%rax)
jle .L52
leaq 0(,%r14,8), %r12
movl $0, %ebx
.L53:
movq 8(%rax), %rax
movq (%rax,%r12), %rax
movl (%rax,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 0(%rbp), %rax
addq $1, %rbx
cmpl %ebx, 4(%rax)
jg .L53
.L52:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
movq 0(%rbp), %rax
cmpl %r14d, (%rax)
jg .L54
.L50:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _Z14printQueueDataPP1q, .-_Z14printQueueDataPP1q
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1107296256
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Queue.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Program to add 2 matrics of size M * N in CUDA C++
Using grid of one block
Block contains M*N threads arranged in M rows and N columns
*/
#include<iostream>
#include "cuda.h"
#include "cuda_runtime.h"
#define M 2
#define N 9
__global__ void matAdd(int* a, int* b, int* c)
{
int idx = threadIdx.x * blockDim.y + threadIdx.y;
c[idx] = a[idx] + b[idx];
}
__host__ void print_matrix(int* matrix)
{
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
std::cout<<matrix[i*N+j]<<' ';
}
std::cout<<"\n";
}
std::cout<<"\n";
}
int main()
{
int size = M * N * sizeof(int);
int* a = new int[size];
int* b = new int[size];
int* c = new int[size];
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
a[i*N + j] = i; //Fill your own values here
b[i*N + j] = j; //Fill your own values here
}
}
std::cout<<"MATRIX A =\n";
print_matrix(a);
std::cout<<"MATRIX B =\n";
print_matrix(b);
/* Setting up variables on device. i.e. GPU */
int *d_a, *d_b, *d_c;
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
/* Copy data from host to device */
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
/*
Kernel Launch
Grid contains 1 block
Each block has M*N threads arranged in M*N rectangle
Hence index of vector is
idx = threadIdx.x * blockDim.y + threadIdx.y;
*/
dim3 blockSize(M, N);
matAdd<<<1, blockSize>>>(d_a, d_b, d_c);
cudaDeviceSynchronize();
/* Copy result from GPU device to host */
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
/* Print result */
std::cout<<"A + B =\n";
print_matrix(c);
std::cout<<'\n';
/* Cleanup device and host memory */
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
delete a;
delete b;
delete c;
return 0;
} | code for sm_80
Function : _Z6matAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Program to add 2 matrics of size M * N in CUDA C++
Using grid of one block
Block contains M*N threads arranged in M rows and N columns
*/
#include<iostream>
#include "cuda.h"
#include "cuda_runtime.h"
#define M 2
#define N 9
__global__ void matAdd(int* a, int* b, int* c)
{
int idx = threadIdx.x * blockDim.y + threadIdx.y;
c[idx] = a[idx] + b[idx];
}
__host__ void print_matrix(int* matrix)
{
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
std::cout<<matrix[i*N+j]<<' ';
}
std::cout<<"\n";
}
std::cout<<"\n";
}
int main()
{
int size = M * N * sizeof(int);
int* a = new int[size];
int* b = new int[size];
int* c = new int[size];
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
a[i*N + j] = i; //Fill your own values here
b[i*N + j] = j; //Fill your own values here
}
}
std::cout<<"MATRIX A =\n";
print_matrix(a);
std::cout<<"MATRIX B =\n";
print_matrix(b);
/* Setting up variables on device. i.e. GPU */
int *d_a, *d_b, *d_c;
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
/* Copy data from host to device */
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
/*
Kernel Launch
Grid contains 1 block
Each block has M*N threads arranged in M*N rectangle
Hence index of vector is
idx = threadIdx.x * blockDim.y + threadIdx.y;
*/
dim3 blockSize(M, N);
matAdd<<<1, blockSize>>>(d_a, d_b, d_c);
cudaDeviceSynchronize();
/* Copy result from GPU device to host */
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
/* Print result */
std::cout<<"A + B =\n";
print_matrix(c);
std::cout<<'\n';
/* Cleanup device and host memory */
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
delete a;
delete b;
delete c;
return 0;
} | .file "tmpxft_00131fd4_00000000-6_matAdd2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl _Z12print_matrixPi
.type _Z12print_matrixPi, @function
_Z12print_matrixPi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 36(%rdi), %rbp
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq 7(%rsp), %r13
leaq .LC0(%rip), %r15
jmp .L4
.L5:
movl $32, %esi
call _ZNSo3putEc@PLT
.L6:
addq $4, %rbx
cmpq %rbp, %rbx
je .L12
.L7:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L5
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L6
.L12:
movl $1, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $36, %rbp
addl $9, %r14d
cmpl $18, %r14d
je .L8
.L4:
leaq -36(%rbp), %rbx
jmp .L7
.L8:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z12print_matrixPi, .-_Z12print_matrixPi
.globl _Z29__device_stub__Z6matAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6matAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6matAddPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z6matAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6matAddPiS_S_PiS_S_
.globl _Z6matAddPiS_S_
.type _Z6matAddPiS_S_, @function
_Z6matAddPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6matAddPiS_S_, .-_Z6matAddPiS_S_
.section .rodata.str1.1
.LC1:
.string "MATRIX A =\n"
.LC2:
.string "MATRIX B =\n"
.LC3:
.string "A + B =\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $288, %edi
call _Znam@PLT
movq %rax, %rbp
movl $288, %edi
call _Znam@PLT
movq %rax, %rbx
movl $288, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L23:
movl $0, 0(%rbp,%rax,4)
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $9, %rax
jne .L23
movl $0, %eax
.L24:
movl $1, 36(%rbp,%rax,4)
movl %eax, 36(%rbx,%rax,4)
addq $1, %rax
cmpq $9, %rax
jne .L24
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rdi
call _Z12print_matrixPi
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbx, %rdi
call _Z12print_matrixPi
leaq 8(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $72, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $72, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 32(%rsp)
movl $9, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $72, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r12, %rdi
call _Z12print_matrixPi
movl $10, %esi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6matAddPiS_S_PiS_S_
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6matAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Program to add 2 matrics of size M * N in CUDA C++
Using grid of one block
Block contains M*N threads arranged in M rows and N columns
*/
#include<iostream>
#include "cuda.h"
#include "cuda_runtime.h"
#define M 2
#define N 9
__global__ void matAdd(int* a, int* b, int* c)
{
int idx = threadIdx.x * blockDim.y + threadIdx.y;
c[idx] = a[idx] + b[idx];
}
__host__ void print_matrix(int* matrix)
{
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
std::cout<<matrix[i*N+j]<<' ';
}
std::cout<<"\n";
}
std::cout<<"\n";
}
int main()
{
int size = M * N * sizeof(int);
int* a = new int[size];
int* b = new int[size];
int* c = new int[size];
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
a[i*N + j] = i; //Fill your own values here
b[i*N + j] = j; //Fill your own values here
}
}
std::cout<<"MATRIX A =\n";
print_matrix(a);
std::cout<<"MATRIX B =\n";
print_matrix(b);
/* Setting up variables on device. i.e. GPU */
int *d_a, *d_b, *d_c;
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
/* Copy data from host to device */
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
/*
Kernel Launch
Grid contains 1 block
Each block has M*N threads arranged in M*N rectangle
Hence index of vector is
idx = threadIdx.x * blockDim.y + threadIdx.y;
*/
dim3 blockSize(M, N);
matAdd<<<1, blockSize>>>(d_a, d_b, d_c);
cudaDeviceSynchronize();
/* Copy result from GPU device to host */
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
/* Print result */
std::cout<<"A + B =\n";
print_matrix(c);
std::cout<<'\n';
/* Cleanup device and host memory */
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
delete a;
delete b;
delete c;
return 0;
} | /*
Program to add 2 matrics of size M * N in CUDA C++
Using grid of one block
Block contains M*N threads arranged in M rows and N columns
*/
#include<iostream>
#include "hip/hip_runtime.h"
#define M 2
#define N 9
__global__ void matAdd(int* a, int* b, int* c)
{
int idx = threadIdx.x * blockDim.y + threadIdx.y;
c[idx] = a[idx] + b[idx];
}
__host__ void print_matrix(int* matrix)
{
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
std::cout<<matrix[i*N+j]<<' ';
}
std::cout<<"\n";
}
std::cout<<"\n";
}
int main()
{
int size = M * N * sizeof(int);
int* a = new int[size];
int* b = new int[size];
int* c = new int[size];
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
a[i*N + j] = i; //Fill your own values here
b[i*N + j] = j; //Fill your own values here
}
}
std::cout<<"MATRIX A =\n";
print_matrix(a);
std::cout<<"MATRIX B =\n";
print_matrix(b);
/* Setting up variables on device. i.e. GPU */
int *d_a, *d_b, *d_c;
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
/* Copy data from host to device */
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
/*
Kernel Launch
Grid contains 1 block
Each block has M*N threads arranged in M*N rectangle
Hence index of vector is
idx = threadIdx.x * blockDim.y + threadIdx.y;
*/
dim3 blockSize(M, N);
matAdd<<<1, blockSize>>>(d_a, d_b, d_c);
hipDeviceSynchronize();
/* Copy result from GPU device to host */
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
/* Print result */
std::cout<<"A + B =\n";
print_matrix(c);
std::cout<<'\n';
/* Cleanup device and host memory */
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
delete a;
delete b;
delete c;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Program to add 2 matrics of size M * N in CUDA C++
Using grid of one block
Block contains M*N threads arranged in M rows and N columns
*/
#include<iostream>
#include "hip/hip_runtime.h"
#define M 2
#define N 9
__global__ void matAdd(int* a, int* b, int* c)
{
int idx = threadIdx.x * blockDim.y + threadIdx.y;
c[idx] = a[idx] + b[idx];
}
__host__ void print_matrix(int* matrix)
{
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
std::cout<<matrix[i*N+j]<<' ';
}
std::cout<<"\n";
}
std::cout<<"\n";
}
int main()
{
int size = M * N * sizeof(int);
int* a = new int[size];
int* b = new int[size];
int* c = new int[size];
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
a[i*N + j] = i; //Fill your own values here
b[i*N + j] = j; //Fill your own values here
}
}
std::cout<<"MATRIX A =\n";
print_matrix(a);
std::cout<<"MATRIX B =\n";
print_matrix(b);
/* Setting up variables on device. i.e. GPU */
int *d_a, *d_b, *d_c;
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
/* Copy data from host to device */
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
/*
Kernel Launch
Grid contains 1 block
Each block has M*N threads arranged in M*N rectangle
Hence index of vector is
idx = threadIdx.x * blockDim.y + threadIdx.y;
*/
dim3 blockSize(M, N);
matAdd<<<1, blockSize>>>(d_a, d_b, d_c);
hipDeviceSynchronize();
/* Copy result from GPU device to host */
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
/* Print result */
std::cout<<"A + B =\n";
print_matrix(c);
std::cout<<'\n';
/* Cleanup device and host memory */
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
delete a;
delete b;
delete c;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matAddPiS_S_
.globl _Z6matAddPiS_S_
.p2align 8
.type _Z6matAddPiS_S_,@function
_Z6matAddPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, s2, v1
v_add_lshl_u32 v0, v1, v0, 2
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matAddPiS_S_, .Lfunc_end0-_Z6matAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6matAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Program to add 2 matrics of size M * N in CUDA C++
Using grid of one block
Block contains M*N threads arranged in M rows and N columns
*/
#include<iostream>
#include "hip/hip_runtime.h"
#define M 2
#define N 9
__global__ void matAdd(int* a, int* b, int* c)
{
int idx = threadIdx.x * blockDim.y + threadIdx.y;
c[idx] = a[idx] + b[idx];
}
__host__ void print_matrix(int* matrix)
{
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
std::cout<<matrix[i*N+j]<<' ';
}
std::cout<<"\n";
}
std::cout<<"\n";
}
int main()
{
int size = M * N * sizeof(int);
int* a = new int[size];
int* b = new int[size];
int* c = new int[size];
for(int i=0; i<M; ++i)
{
for(int j=0; j<N; ++j)
{
a[i*N + j] = i; //Fill your own values here
b[i*N + j] = j; //Fill your own values here
}
}
std::cout<<"MATRIX A =\n";
print_matrix(a);
std::cout<<"MATRIX B =\n";
print_matrix(b);
/* Setting up variables on device. i.e. GPU */
int *d_a, *d_b, *d_c;
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
/* Copy data from host to device */
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
/*
Kernel Launch
Grid contains 1 block
Each block has M*N threads arranged in M*N rectangle
Hence index of vector is
idx = threadIdx.x * blockDim.y + threadIdx.y;
*/
dim3 blockSize(M, N);
matAdd<<<1, blockSize>>>(d_a, d_b, d_c);
hipDeviceSynchronize();
/* Copy result from GPU device to host */
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
/* Print result */
std::cout<<"A + B =\n";
print_matrix(c);
std::cout<<'\n';
/* Cleanup device and host memory */
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
delete a;
delete b;
delete c;
return 0;
} | .text
.file "matAdd2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matAddPiS_S_ # -- Begin function _Z21__device_stub__matAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__matAddPiS_S_,@function
_Z21__device_stub__matAddPiS_S_: # @_Z21__device_stub__matAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__matAddPiS_S_, .Lfunc_end0-_Z21__device_stub__matAddPiS_S_
.cfi_endproc
# -- End function
.globl _Z12print_matrixPi # -- Begin function _Z12print_matrixPi
.p2align 4, 0x90
.type _Z12print_matrixPi,@function
_Z12print_matrixPi: # @_Z12print_matrixPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
leaq 7(%rsp), %r14
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 1(%r15), %rax
addq $36, %rbx
testq %r15, %r15
movq %rax, %r15
jne .LBB1_5
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_2 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB1_7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_2 Depth=2
incq %r12
cmpq $9, %r12
je .LBB1_4
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_6
# %bb.3: # in Loop: Header=BB1_2 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_7
.LBB1_5:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_matrixPi, .Lfunc_end1-_Z12print_matrixPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $288, %edi # imm = 0x120
callq _Znam
movq %rax, %rbx
movl $288, %edi # imm = 0x120
callq _Znam
movq %rax, %r14
movl $288, %edi # imm = 0x120
callq _Znam
movq %rax, %r15
xorl %ecx, %ecx
movq %rbx, %rax
movq %r14, %rdx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, (%rax,%rsi,4)
movl %esi, (%rdx,%rsi,4)
incq %rsi
cmpq $9, %rsi
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
leaq 1(%rcx), %rsi
addq $36, %rdx
addq $36, %rax
testq %rcx, %rcx
movq %rsi, %rcx
je .LBB2_1
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq _Z12print_matrixPi
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq _Z12print_matrixPi
leaq 24(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $72, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $72, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $72, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $38654705666, %rdx # imm = 0x900000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6matAddPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $72, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq _Z12print_matrixPi
movb $10, 32(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB2_8
# %bb.7:
leaq 32(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_9
.LBB2_8:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB2_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matAddPiS_S_,@object # @_Z6matAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6matAddPiS_S_
.p2align 3, 0x0
_Z6matAddPiS_S_:
.quad _Z21__device_stub__matAddPiS_S_
.size _Z6matAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "MATRIX A =\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "MATRIX B =\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "A + B =\n"
.size .L.str.3, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matAddPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matAddPiS_S_
.globl _Z6matAddPiS_S_
.p2align 8
.type _Z6matAddPiS_S_,@function
_Z6matAddPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, s2, v1
v_add_lshl_u32 v0, v1, v0, 2
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matAddPiS_S_, .Lfunc_end0-_Z6matAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6matAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00131fd4_00000000-6_matAdd2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl _Z12print_matrixPi
.type _Z12print_matrixPi, @function
_Z12print_matrixPi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 36(%rdi), %rbp
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq 7(%rsp), %r13
leaq .LC0(%rip), %r15
jmp .L4
.L5:
movl $32, %esi
call _ZNSo3putEc@PLT
.L6:
addq $4, %rbx
cmpq %rbp, %rbx
je .L12
.L7:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L5
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L6
.L12:
movl $1, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $36, %rbp
addl $9, %r14d
cmpl $18, %r14d
je .L8
.L4:
leaq -36(%rbp), %rbx
jmp .L7
.L8:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z12print_matrixPi, .-_Z12print_matrixPi
.globl _Z29__device_stub__Z6matAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6matAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6matAddPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z6matAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6matAddPiS_S_PiS_S_
.globl _Z6matAddPiS_S_
.type _Z6matAddPiS_S_, @function
_Z6matAddPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6matAddPiS_S_, .-_Z6matAddPiS_S_
.section .rodata.str1.1
.LC1:
.string "MATRIX A =\n"
.LC2:
.string "MATRIX B =\n"
.LC3:
.string "A + B =\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $288, %edi
call _Znam@PLT
movq %rax, %rbp
movl $288, %edi
call _Znam@PLT
movq %rax, %rbx
movl $288, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L23:
movl $0, 0(%rbp,%rax,4)
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $9, %rax
jne .L23
movl $0, %eax
.L24:
movl $1, 36(%rbp,%rax,4)
movl %eax, 36(%rbx,%rax,4)
addq $1, %rax
cmpq $9, %rax
jne .L24
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rdi
call _Z12print_matrixPi
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbx, %rdi
call _Z12print_matrixPi
leaq 8(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $72, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $72, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 32(%rsp)
movl $9, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $72, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r12, %rdi
call _Z12print_matrixPi
movl $10, %esi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6matAddPiS_S_PiS_S_
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6matAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matAdd2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matAddPiS_S_ # -- Begin function _Z21__device_stub__matAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__matAddPiS_S_,@function
_Z21__device_stub__matAddPiS_S_: # @_Z21__device_stub__matAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__matAddPiS_S_, .Lfunc_end0-_Z21__device_stub__matAddPiS_S_
.cfi_endproc
# -- End function
.globl _Z12print_matrixPi # -- Begin function _Z12print_matrixPi
.p2align 4, 0x90
.type _Z12print_matrixPi,@function
_Z12print_matrixPi: # @_Z12print_matrixPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
leaq 7(%rsp), %r14
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 1(%r15), %rax
addq $36, %rbx
testq %r15, %r15
movq %rax, %r15
jne .LBB1_5
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_2 Depth=2
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB1_7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_2 Depth=2
incq %r12
cmpq $9, %r12
je .LBB1_4
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_6
# %bb.3: # in Loop: Header=BB1_2 Depth=2
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_7
.LBB1_5:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_matrixPi, .Lfunc_end1-_Z12print_matrixPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $288, %edi # imm = 0x120
callq _Znam
movq %rax, %rbx
movl $288, %edi # imm = 0x120
callq _Znam
movq %rax, %r14
movl $288, %edi # imm = 0x120
callq _Znam
movq %rax, %r15
xorl %ecx, %ecx
movq %rbx, %rax
movq %r14, %rdx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, (%rax,%rsi,4)
movl %esi, (%rdx,%rsi,4)
incq %rsi
cmpq $9, %rsi
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
leaq 1(%rcx), %rsi
addq $36, %rdx
addq $36, %rax
testq %rcx, %rcx
movq %rsi, %rcx
je .LBB2_1
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq _Z12print_matrixPi
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq _Z12print_matrixPi
leaq 24(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $72, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $72, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $72, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $38654705666, %rdx # imm = 0x900000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6matAddPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $72, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq _Z12print_matrixPi
movb $10, 32(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB2_8
# %bb.7:
leaq 32(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB2_9
.LBB2_8:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB2_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matAddPiS_S_,@object # @_Z6matAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6matAddPiS_S_
.p2align 3, 0x0
_Z6matAddPiS_S_:
.quad _Z21__device_stub__matAddPiS_S_
.size _Z6matAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "MATRIX A =\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "MATRIX B =\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "A + B =\n"
.size .L.str.3, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matAddPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#define N 160
#define THREADS 16
__global__ void sum(float *A, float *B, float *result_d)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
result_d[i] = A[i] * B[i];
__shared__ float sresult[THREADS];
sresult[threadIdx.x] = result_d[i];
for(unsigned int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x < s){
sresult[threadIdx.x] += sresult[threadIdx.x+s];
__syncthreads();
}
}
if(threadIdx.x == 0){
result_d[blockIdx.x] = sresult[threadIdx.x];
}
}
int main()
{
float A[N], B[N], tresult, *result;
float *A_d, *B_d, *result_d;
int i;
dim3 dimBlock(THREADS);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x);
for(i=0; i<N; i++){
A[i] = i * 2;
B[i] = N - i;
}
cudaMalloc((void **) &A_d, sizeof(float)*N);
cudaMalloc((void **) &B_d, sizeof(float)*N);
cudaMalloc((void **) &result_d, sizeof(float)*dimGrid.x);
cudaMemcpy(A_d, A, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B, sizeof(float)*N, cudaMemcpyHostToDevice);
sum<<<dimGrid, dimBlock>>>(A_d, B_d, result_d);
result = (float*)malloc(sizeof(float)*dimGrid.x);
cudaMemcpy(result, result_d, sizeof(float)*dimGrid.x, cudaMemcpyDeviceToHost);
tresult = 0.0;
for(i=0; i<dimGrid.x; i++){
tresult += result[i];
}
printf("GPU dotprod : %f\n", tresult);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(result_d);
free(result);
} | code for sm_80
Function : _Z3sumPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R8, c[0x0][0x0], R10 ; /* 0x0000000008067a24 */
/* 0x001fca00078e020a */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00f0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101906 */
/*0110*/ STS [R10.X4], R9 ; /* 0x000000090a007388 */
/* 0x0001e60000004800 */
/*0120*/ @!P1 BRA 0x220 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0130*/ BSSY B0, 0x220 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0140*/ SHF.L.U32 R0, R10, 0x2, RZ ; /* 0x000000020a007819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f26070 */
/*0170*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0180*/ @!P1 LDS R4, [R10.X4] ; /* 0x000000000a049984 */
/* 0x000fe20000004800 */
/*0190*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*01a0*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe40003800000 */
/*01b0*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e640000000800 */
/*01c0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x002fca0000000000 */
/*01d0*/ @!P1 STS [R10.X4], R4 ; /* 0x000000040a009388 */
/* 0x0003e80000004800 */
/*01e0*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0200*/ @P1 BRA 0x160 ; /* 0xffffff5000001947 */
/* 0x002fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x170] ; /* 0x00005c0008027625 */
/* 0x000fca00078e0003 */
/*0260*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define N 160
#define THREADS 16
__global__ void sum(float *A, float *B, float *result_d)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
result_d[i] = A[i] * B[i];
__shared__ float sresult[THREADS];
sresult[threadIdx.x] = result_d[i];
for(unsigned int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x < s){
sresult[threadIdx.x] += sresult[threadIdx.x+s];
__syncthreads();
}
}
if(threadIdx.x == 0){
result_d[blockIdx.x] = sresult[threadIdx.x];
}
}
int main()
{
float A[N], B[N], tresult, *result;
float *A_d, *B_d, *result_d;
int i;
dim3 dimBlock(THREADS);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x);
for(i=0; i<N; i++){
A[i] = i * 2;
B[i] = N - i;
}
cudaMalloc((void **) &A_d, sizeof(float)*N);
cudaMalloc((void **) &B_d, sizeof(float)*N);
cudaMalloc((void **) &result_d, sizeof(float)*dimGrid.x);
cudaMemcpy(A_d, A, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B, sizeof(float)*N, cudaMemcpyHostToDevice);
sum<<<dimGrid, dimBlock>>>(A_d, B_d, result_d);
result = (float*)malloc(sizeof(float)*dimGrid.x);
cudaMemcpy(result, result_d, sizeof(float)*dimGrid.x, cudaMemcpyDeviceToHost);
tresult = 0.0;
for(i=0; i<dimGrid.x; i++){
tresult += result[i];
}
printf("GPU dotprod : %f\n", tresult);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(result_d);
free(result);
} | .file "tmpxft_0016bda3_00000000-6_CUDA_homework2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3sumPfS_S_PfS_S_
.type _Z26__device_stub__Z3sumPfS_S_PfS_S_, @function
_Z26__device_stub__Z3sumPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3sumPfS_S_PfS_S_, .-_Z26__device_stub__Z3sumPfS_S_PfS_S_
.globl _Z3sumPfS_S_
.type _Z3sumPfS_S_, @function
_Z3sumPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3sumPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3sumPfS_S_, .-_Z3sumPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU dotprod : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1344, %rsp
.cfi_def_cfa_offset 1360
movq %fs:40, %rax
movq %rax, 1336(%rsp)
xorl %eax, %eax
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $160, %ecx
.L12:
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 688(%rsp,%rax,4)
addq $1, %rax
cmpq $160, %rax
jne .L12
movq %rsp, %rdi
movl $640, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $640, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 688(%rsp), %rsi
movl $1, %ecx
movl $640, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $16, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 40(%rbx), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 1336(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3sumPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3sumPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define N 160
#define THREADS 16
__global__ void sum(float *A, float *B, float *result_d)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
result_d[i] = A[i] * B[i];
__shared__ float sresult[THREADS];
sresult[threadIdx.x] = result_d[i];
for(unsigned int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x < s){
sresult[threadIdx.x] += sresult[threadIdx.x+s];
__syncthreads();
}
}
if(threadIdx.x == 0){
result_d[blockIdx.x] = sresult[threadIdx.x];
}
}
int main()
{
float A[N], B[N], tresult, *result;
float *A_d, *B_d, *result_d;
int i;
dim3 dimBlock(THREADS);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x);
for(i=0; i<N; i++){
A[i] = i * 2;
B[i] = N - i;
}
cudaMalloc((void **) &A_d, sizeof(float)*N);
cudaMalloc((void **) &B_d, sizeof(float)*N);
cudaMalloc((void **) &result_d, sizeof(float)*dimGrid.x);
cudaMemcpy(A_d, A, sizeof(float)*N, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B, sizeof(float)*N, cudaMemcpyHostToDevice);
sum<<<dimGrid, dimBlock>>>(A_d, B_d, result_d);
result = (float*)malloc(sizeof(float)*dimGrid.x);
cudaMemcpy(result, result_d, sizeof(float)*dimGrid.x, cudaMemcpyDeviceToHost);
tresult = 0.0;
for(i=0; i<dimGrid.x; i++){
tresult += result[i];
}
printf("GPU dotprod : %f\n", tresult);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(result_d);
free(result);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N 160
#define THREADS 16
__global__ void sum(float *A, float *B, float *result_d)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
result_d[i] = A[i] * B[i];
__shared__ float sresult[THREADS];
sresult[threadIdx.x] = result_d[i];
for(unsigned int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x < s){
sresult[threadIdx.x] += sresult[threadIdx.x+s];
__syncthreads();
}
}
if(threadIdx.x == 0){
result_d[blockIdx.x] = sresult[threadIdx.x];
}
}
int main()
{
float A[N], B[N], tresult, *result;
float *A_d, *B_d, *result_d;
int i;
dim3 dimBlock(THREADS);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x);
for(i=0; i<N; i++){
A[i] = i * 2;
B[i] = N - i;
}
hipMalloc((void **) &A_d, sizeof(float)*N);
hipMalloc((void **) &B_d, sizeof(float)*N);
hipMalloc((void **) &result_d, sizeof(float)*dimGrid.x);
hipMemcpy(A_d, A, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemcpy(B_d, B, sizeof(float)*N, hipMemcpyHostToDevice);
sum<<<dimGrid, dimBlock>>>(A_d, B_d, result_d);
result = (float*)malloc(sizeof(float)*dimGrid.x);
hipMemcpy(result, result_d, sizeof(float)*dimGrid.x, hipMemcpyDeviceToHost);
tresult = 0.0;
for(i=0; i<dimGrid.x; i++){
tresult += result[i];
}
printf("GPU dotprod : %f\n", tresult);
hipFree(A_d);
hipFree(B_d);
hipFree(result_d);
free(result);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N 160
#define THREADS 16
__global__ void sum(float *A, float *B, float *result_d)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
result_d[i] = A[i] * B[i];
__shared__ float sresult[THREADS];
sresult[threadIdx.x] = result_d[i];
for(unsigned int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x < s){
sresult[threadIdx.x] += sresult[threadIdx.x+s];
__syncthreads();
}
}
if(threadIdx.x == 0){
result_d[blockIdx.x] = sresult[threadIdx.x];
}
}
int main()
{
float A[N], B[N], tresult, *result;
float *A_d, *B_d, *result_d;
int i;
dim3 dimBlock(THREADS);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x);
for(i=0; i<N; i++){
A[i] = i * 2;
B[i] = N - i;
}
hipMalloc((void **) &A_d, sizeof(float)*N);
hipMalloc((void **) &B_d, sizeof(float)*N);
hipMalloc((void **) &result_d, sizeof(float)*dimGrid.x);
hipMemcpy(A_d, A, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemcpy(B_d, B, sizeof(float)*N, hipMemcpyHostToDevice);
sum<<<dimGrid, dimBlock>>>(A_d, B_d, result_d);
result = (float*)malloc(sizeof(float)*dimGrid.x);
hipMemcpy(result, result_d, sizeof(float)*dimGrid.x, hipMemcpyDeviceToHost);
tresult = 0.0;
for(i=0; i<dimGrid.x; i++){
tresult += result[i];
}
printf("GPU dotprod : %f\n", tresult);
hipFree(A_d);
hipFree(B_d);
hipFree(result_d);
free(result);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPfS_S_
.globl _Z3sumPfS_S_
.p2align 8
.type _Z3sumPfS_S_,@function
_Z3sumPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v7, v5 :: v_dual_lshlrev_b32 v1, 2, v0
global_store_b32 v[3:4], v2, off
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_5
.LBB0_1:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
ds_load_b32 v0, v1
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_1
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPfS_S_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPfS_S_, .Lfunc_end0-_Z3sumPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N 160
#define THREADS 16
__global__ void sum(float *A, float *B, float *result_d)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
result_d[i] = A[i] * B[i];
__shared__ float sresult[THREADS];
sresult[threadIdx.x] = result_d[i];
for(unsigned int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x < s){
sresult[threadIdx.x] += sresult[threadIdx.x+s];
__syncthreads();
}
}
if(threadIdx.x == 0){
result_d[blockIdx.x] = sresult[threadIdx.x];
}
}
int main()
{
float A[N], B[N], tresult, *result;
float *A_d, *B_d, *result_d;
int i;
dim3 dimBlock(THREADS);
dim3 dimGrid((N+dimBlock.x-1)/dimBlock.x);
for(i=0; i<N; i++){
A[i] = i * 2;
B[i] = N - i;
}
hipMalloc((void **) &A_d, sizeof(float)*N);
hipMalloc((void **) &B_d, sizeof(float)*N);
hipMalloc((void **) &result_d, sizeof(float)*dimGrid.x);
hipMemcpy(A_d, A, sizeof(float)*N, hipMemcpyHostToDevice);
hipMemcpy(B_d, B, sizeof(float)*N, hipMemcpyHostToDevice);
sum<<<dimGrid, dimBlock>>>(A_d, B_d, result_d);
result = (float*)malloc(sizeof(float)*dimGrid.x);
hipMemcpy(result, result_d, sizeof(float)*dimGrid.x, hipMemcpyDeviceToHost);
tresult = 0.0;
for(i=0; i<dimGrid.x; i++){
tresult += result[i];
}
printf("GPU dotprod : %f\n", tresult);
hipFree(A_d);
hipFree(B_d);
hipFree(result_d);
free(result);
} | .text
.file "CUDA_homework2.hip"
.globl _Z18__device_stub__sumPfS_S_ # -- Begin function _Z18__device_stub__sumPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__sumPfS_S_,@function
_Z18__device_stub__sumPfS_S_: # @_Z18__device_stub__sumPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPfS_S_, .Lfunc_end0-_Z18__device_stub__sumPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1408, %rsp # imm = 0x580
.cfi_def_cfa_offset 1424
.cfi_offset %rbx, -16
movl $160, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, 768(%rsp,%rcx,2)
movss %xmm1, 128(%rsp,%rcx,2)
addq $2, %rcx
decq %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
leaq 8(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 768(%rsp), %rsi
movl $640, %edx # imm = 0x280
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $640, %edx # imm = 0x280
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sumPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $40, %edi
callq malloc
movq %rax, %rbx
movq (%rsp), %rsi
movl $40, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $10, %rax
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $1408, %rsp # imm = 0x580
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPfS_S_,@object # @_Z3sumPfS_S_
.section .rodata,"a",@progbits
.globl _Z3sumPfS_S_
.p2align 3, 0x0
_Z3sumPfS_S_:
.quad _Z18__device_stub__sumPfS_S_
.size _Z3sumPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU dotprod : %f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R8, c[0x0][0x0], R10 ; /* 0x0000000008067a24 */
/* 0x001fca00078e020a */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00f0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101906 */
/*0110*/ STS [R10.X4], R9 ; /* 0x000000090a007388 */
/* 0x0001e60000004800 */
/*0120*/ @!P1 BRA 0x220 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0130*/ BSSY B0, 0x220 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0140*/ SHF.L.U32 R0, R10, 0x2, RZ ; /* 0x000000020a007819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f26070 */
/*0170*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0180*/ @!P1 LDS R4, [R10.X4] ; /* 0x000000000a049984 */
/* 0x000fe20000004800 */
/*0190*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*01a0*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe40003800000 */
/*01b0*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e640000000800 */
/*01c0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x002fca0000000000 */
/*01d0*/ @!P1 STS [R10.X4], R4 ; /* 0x000000040a009388 */
/* 0x0003e80000004800 */
/*01e0*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0200*/ @P1 BRA 0x160 ; /* 0xffffff5000001947 */
/* 0x002fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x170] ; /* 0x00005c0008027625 */
/* 0x000fca00078e0003 */
/*0260*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPfS_S_
.globl _Z3sumPfS_S_
.p2align 8
.type _Z3sumPfS_S_,@function
_Z3sumPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v7, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v7, v5 :: v_dual_lshlrev_b32 v1, 2, v0
global_store_b32 v[3:4], v2, off
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_5
.LBB0_1:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
ds_load_b32 v0, v1
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_1
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_branch .LBB0_4
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPfS_S_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPfS_S_, .Lfunc_end0-_Z3sumPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016bda3_00000000-6_CUDA_homework2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3sumPfS_S_PfS_S_
.type _Z26__device_stub__Z3sumPfS_S_PfS_S_, @function
_Z26__device_stub__Z3sumPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3sumPfS_S_PfS_S_, .-_Z26__device_stub__Z3sumPfS_S_PfS_S_
.globl _Z3sumPfS_S_
.type _Z3sumPfS_S_, @function
_Z3sumPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3sumPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3sumPfS_S_, .-_Z3sumPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU dotprod : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1344, %rsp
.cfi_def_cfa_offset 1360
movq %fs:40, %rax
movq %rax, 1336(%rsp)
xorl %eax, %eax
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $160, %ecx
.L12:
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 688(%rsp,%rax,4)
addq $1, %rax
cmpq $160, %rax
jne .L12
movq %rsp, %rdi
movl $640, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $640, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $640, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 688(%rsp), %rsi
movl $1, %ecx
movl $640, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $16, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 40(%rbx), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 1336(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3sumPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3sumPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_homework2.hip"
.globl _Z18__device_stub__sumPfS_S_ # -- Begin function _Z18__device_stub__sumPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__sumPfS_S_,@function
_Z18__device_stub__sumPfS_S_: # @_Z18__device_stub__sumPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPfS_S_, .Lfunc_end0-_Z18__device_stub__sumPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1408, %rsp # imm = 0x580
.cfi_def_cfa_offset 1424
.cfi_offset %rbx, -16
movl $160, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, 768(%rsp,%rcx,2)
movss %xmm1, 128(%rsp,%rcx,2)
addq $2, %rcx
decq %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
leaq 8(%rsp), %rdi
movl $640, %esi # imm = 0x280
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 768(%rsp), %rsi
movl $640, %edx # imm = 0x280
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $640, %edx # imm = 0x280
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sumPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $40, %edi
callq malloc
movq %rax, %rbx
movq (%rsp), %rsi
movl $40, %edx
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $10, %rax
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $1408, %rsp # imm = 0x580
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPfS_S_,@object # @_Z3sumPfS_S_
.section .rodata,"a",@progbits
.globl _Z3sumPfS_S_
.p2align 3, 0x0
_Z3sumPfS_S_:
.quad _Z18__device_stub__sumPfS_S_
.size _Z3sumPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU dotprod : %f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void gfill(const int n, const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
c[i] = a[0];
}
}
} | code for sm_80
Function : gfill
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fcc0000000f00 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*00c0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void gfill(const int n, const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
c[i] = a[0];
}
}
} | .file "tmpxft_0002cd54_00000000-6_gfill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5gfilliPKdPdiPKdPd
.type _Z28__device_stub__Z5gfilliPKdPdiPKdPd, @function
_Z28__device_stub__Z5gfilliPKdPdiPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gfill(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5gfilliPKdPdiPKdPd, .-_Z28__device_stub__Z5gfilliPKdPdiPKdPd
.globl gfill
.type gfill, @function
gfill:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5gfilliPKdPdiPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gfill, .-gfill
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gfill"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gfill(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void gfill(const int n, const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
c[i] = a[0];
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gfill(const int n, const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
c[i] = a[0];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gfill(const int n, const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
c[i] = a[0];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gfill
.globl gfill
.p2align 8
.type gfill,@function
gfill:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_load_b64 s[0:1], s[0:1], 0x0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gfill
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gfill, .Lfunc_end0-gfill
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gfill
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gfill.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void gfill(const int n, const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
c[i] = a[0];
}
}
} | .text
.file "gfill.hip"
.globl __device_stub__gfill # -- Begin function __device_stub__gfill
.p2align 4, 0x90
.type __device_stub__gfill,@function
__device_stub__gfill: # @__device_stub__gfill
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gfill, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__gfill, .Lfunc_end0-__device_stub__gfill
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gfill, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gfill,@object # @gfill
.section .rodata,"a",@progbits
.globl gfill
.p2align 3, 0x0
gfill:
.quad __device_stub__gfill
.size gfill, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gfill"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gfill
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gfill
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : gfill
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fcc0000000f00 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*00c0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gfill
.globl gfill
.p2align 8
.type gfill,@function
gfill:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_load_b64 s[0:1], s[0:1], 0x0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gfill
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gfill, .Lfunc_end0-gfill
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gfill
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gfill.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002cd54_00000000-6_gfill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5gfilliPKdPdiPKdPd
.type _Z28__device_stub__Z5gfilliPKdPdiPKdPd, @function
_Z28__device_stub__Z5gfilliPKdPdiPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gfill(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5gfilliPKdPdiPKdPd, .-_Z28__device_stub__Z5gfilliPKdPdiPKdPd
.globl gfill
.type gfill, @function
gfill:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5gfilliPKdPdiPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gfill, .-gfill
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gfill"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gfill(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gfill.hip"
.globl __device_stub__gfill # -- Begin function __device_stub__gfill
.p2align 4, 0x90
.type __device_stub__gfill,@function
__device_stub__gfill: # @__device_stub__gfill
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gfill, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__gfill, .Lfunc_end0-__device_stub__gfill
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gfill, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gfill,@object # @gfill
.section .rodata,"a",@progbits
.globl gfill
.p2align 3, 0x0
gfill:
.quad __device_stub__gfill
.size gfill, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gfill"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gfill
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gfill
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void colorInvalids_kernel(uchar4 *out_image, const float *in_image, int width, int height) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
if (x < width && y < height) {
int ind = __mul24(y, width) + x;
uchar4 temp = out_image[ind];
float value = in_image[ind];
if (!isfinite(value)) { // color
temp.x *= 0.5f;
temp.y *= 0.5f;
}
out_image[ind] = temp;
}
} | code for sm_80
Function : _Z20colorInvalids_kernelP6uchar4PKfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff027624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea40000002100 */
/*0060*/ SHF.L.U32 R2, R2, 0x8, RZ ; /* 0x0000000802027819 */
/* 0x000fe200000006ff */
/*0070*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000ee20000002500 */
/*0080*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fe400078e00ff */
/*0090*/ SHF.R.S32.HI R2, RZ, 0x8, R2 ; /* 0x00000008ff027819 */
/* 0x000fc60000011402 */
/*00a0*/ SHF.R.S32.HI R0, RZ, 0x8, R0 ; /* 0x00000008ff007819 */
/* 0x000fe20000011400 */
/*00b0*/ USHF.L.U32 UR5, UR5, 0x8, URZ ; /* 0x0000000805057899 */
/* 0x001fc8000800063f */
/*00c0*/ USHF.R.S32.HI UR5, URZ, 0x8, UR5 ; /* 0x000000083f057899 */
/* 0x000fe40008011405 */
/*00d0*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x008fc8000800063f */
/*00e0*/ IMAD R2, R2, UR5, R5 ; /* 0x0000000502027c24 */
/* 0x002fe2000f8e0205 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fc80008011404 */
/*0100*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe40003f06270 */
/*0110*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x004fca000f8e0203 */
/*0120*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0150*/ IMAD.SHL.U32 R2, R2, 0x100, RZ ; /* 0x0000010002027824 */
/* 0x000fe200078e00ff */
/*0160*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x000fc8000800063f */
/*0170*/ SHF.R.S32.HI R3, RZ, 0x8, R2 ; /* 0x00000008ff037819 */
/* 0x000fe20000011402 */
/*0180*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fe20008011404 */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fca00000001ff */
/*01a0*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0200 */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*01c0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0202 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*01f0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1900 */
/*0200*/ FSETP.GEU.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x004fe40003f0e200 */
/*0210*/ PRMT R6, R10.reuse, 0x7770, RZ ; /* 0x000077700a067816 */
/* 0x048fe400000000ff */
/*0220*/ PRMT R7, R10.reuse, 0x7771, RZ ; /* 0x000077710a077816 */
/* 0x040fe400000000ff */
/*0230*/ PRMT R4, R10, 0x7773, RZ ; /* 0x000077730a047816 */
/* 0x000fce00000000ff */
/*0240*/ @P0 I2F.U16 R0, R6 ; /* 0x0000000600000306 */
/* 0x000e300000101000 */
/*0250*/ @P0 I2F.U16 R9, R7 ; /* 0x0000000700090306 */
/* 0x000e620000101000 */
/*0260*/ @P0 FMUL R8, R0, 0.5 ; /* 0x3f00000000080820 */
/* 0x001fe20000400000 */
/*0270*/ PRMT R0, R10, 0x7772, RZ ; /* 0x000077720a007816 */
/* 0x000fcc00000000ff */
/*0280*/ @P0 F2I.U32.TRUNC.NTZ R6, R8 ; /* 0x0000000800060305 */
/* 0x000fe2000020f000 */
/*0290*/ @P0 FMUL R9, R9, 0.5 ; /* 0x3f00000009090820 */
/* 0x002fce0000400000 */
/*02a0*/ @P0 F2I.U32.TRUNC.NTZ R7, R9 ; /* 0x0000000900070305 */
/* 0x000e24000020f000 */
/*02b0*/ PRMT R5, R7, 0x7604, R6 ; /* 0x0000760407057816 */
/* 0x001fc80000000006 */
/*02c0*/ PRMT R5, R0, 0x7054, R5 ; /* 0x0000705400057816 */
/* 0x000fc80000000005 */
/*02d0*/ PRMT R5, R4, 0x654, R5 ; /* 0x0000065404057816 */
/* 0x000fca0000000005 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void colorInvalids_kernel(uchar4 *out_image, const float *in_image, int width, int height) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
if (x < width && y < height) {
int ind = __mul24(y, width) + x;
uchar4 temp = out_image[ind];
float value = in_image[ind];
if (!isfinite(value)) { // color
temp.x *= 0.5f;
temp.y *= 0.5f;
}
out_image[ind] = temp;
}
} | .file "tmpxft_001afc9f_00000000-6_colorInvalids_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii
.type _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii, @function
_Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20colorInvalids_kernelP6uchar4PKfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii, .-_Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii
.globl _Z20colorInvalids_kernelP6uchar4PKfii
.type _Z20colorInvalids_kernelP6uchar4PKfii, @function
_Z20colorInvalids_kernelP6uchar4PKfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20colorInvalids_kernelP6uchar4PKfii, .-_Z20colorInvalids_kernelP6uchar4PKfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20colorInvalids_kernelP6uchar4PKfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20colorInvalids_kernelP6uchar4PKfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void colorInvalids_kernel(uchar4 *out_image, const float *in_image, int width, int height) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
if (x < width && y < height) {
int ind = __mul24(y, width) + x;
uchar4 temp = out_image[ind];
float value = in_image[ind];
if (!isfinite(value)) { // color
temp.x *= 0.5f;
temp.y *= 0.5f;
}
out_image[ind] = temp;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void colorInvalids_kernel(uchar4 *out_image, const float *in_image, int width, int height) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
if (x < width && y < height) {
int ind = __mul24(y, width) + x;
uchar4 temp = out_image[ind];
float value = in_image[ind];
if (!isfinite(value)) { // color
temp.x *= 0.5f;
temp.y *= 0.5f;
}
out_image[ind] = temp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void colorInvalids_kernel(uchar4 *out_image, const float *in_image, int width, int height) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
if (x < width && y < height) {
int ind = __mul24(y, width) + x;
uchar4 temp = out_image[ind];
float value = in_image[ind];
if (!isfinite(value)) { // color
temp.x *= 0.5f;
temp.y *= 0.5f;
}
out_image[ind] = temp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.globl _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.p2align 8
.type _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii,@function
_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_bfe_i32 s3, s14, 0x180000
s_bfe_i32 s6, s15, 0x180000
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s3, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s6, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_i32_i24 v0, v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v2, v[0:1], off offset:1
s_waitcnt vmcnt(2)
v_cmpx_nlg_f32_e64 0x7f800000, |v4|
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v3
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v3, 0.5, v3 :: v_dual_mul_f32 v2, 0.5, v2
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2)
v_cvt_i32_f32_e32 v2, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(1)
global_store_b8 v[0:1], v3, off
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off offset:1
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, .Lfunc_end0-_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void colorInvalids_kernel(uchar4 *out_image, const float *in_image, int width, int height) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
if (x < width && y < height) {
int ind = __mul24(y, width) + x;
uchar4 temp = out_image[ind];
float value = in_image[ind];
if (!isfinite(value)) { // color
temp.x *= 0.5f;
temp.y *= 0.5f;
}
out_image[ind] = temp;
}
} | .text
.file "colorInvalids_kernel.hip"
.globl _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii # -- Begin function _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.p2align 4, 0x90
.type _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii,@function
_Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii: # @_Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, .Lfunc_end0-_Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii,@object # @_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.section .rodata,"a",@progbits
.globl _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.p2align 3, 0x0
_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii:
.quad _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.size _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20colorInvalids_kernelP6uchar4PKfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff027624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea40000002100 */
/*0060*/ SHF.L.U32 R2, R2, 0x8, RZ ; /* 0x0000000802027819 */
/* 0x000fe200000006ff */
/*0070*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000ee20000002500 */
/*0080*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fe400078e00ff */
/*0090*/ SHF.R.S32.HI R2, RZ, 0x8, R2 ; /* 0x00000008ff027819 */
/* 0x000fc60000011402 */
/*00a0*/ SHF.R.S32.HI R0, RZ, 0x8, R0 ; /* 0x00000008ff007819 */
/* 0x000fe20000011400 */
/*00b0*/ USHF.L.U32 UR5, UR5, 0x8, URZ ; /* 0x0000000805057899 */
/* 0x001fc8000800063f */
/*00c0*/ USHF.R.S32.HI UR5, URZ, 0x8, UR5 ; /* 0x000000083f057899 */
/* 0x000fe40008011405 */
/*00d0*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x008fc8000800063f */
/*00e0*/ IMAD R2, R2, UR5, R5 ; /* 0x0000000502027c24 */
/* 0x002fe2000f8e0205 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fc80008011404 */
/*0100*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe40003f06270 */
/*0110*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x004fca000f8e0203 */
/*0120*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0150*/ IMAD.SHL.U32 R2, R2, 0x100, RZ ; /* 0x0000010002027824 */
/* 0x000fe200078e00ff */
/*0160*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x000fc8000800063f */
/*0170*/ SHF.R.S32.HI R3, RZ, 0x8, R2 ; /* 0x00000008ff037819 */
/* 0x000fe20000011402 */
/*0180*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fe20008011404 */
/*0190*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fca00000001ff */
/*01a0*/ IMAD R3, R3, UR4, R0 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0200 */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*01c0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fcc00078e0202 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*01f0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1900 */
/*0200*/ FSETP.GEU.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x004fe40003f0e200 */
/*0210*/ PRMT R6, R10.reuse, 0x7770, RZ ; /* 0x000077700a067816 */
/* 0x048fe400000000ff */
/*0220*/ PRMT R7, R10.reuse, 0x7771, RZ ; /* 0x000077710a077816 */
/* 0x040fe400000000ff */
/*0230*/ PRMT R4, R10, 0x7773, RZ ; /* 0x000077730a047816 */
/* 0x000fce00000000ff */
/*0240*/ @P0 I2F.U16 R0, R6 ; /* 0x0000000600000306 */
/* 0x000e300000101000 */
/*0250*/ @P0 I2F.U16 R9, R7 ; /* 0x0000000700090306 */
/* 0x000e620000101000 */
/*0260*/ @P0 FMUL R8, R0, 0.5 ; /* 0x3f00000000080820 */
/* 0x001fe20000400000 */
/*0270*/ PRMT R0, R10, 0x7772, RZ ; /* 0x000077720a007816 */
/* 0x000fcc00000000ff */
/*0280*/ @P0 F2I.U32.TRUNC.NTZ R6, R8 ; /* 0x0000000800060305 */
/* 0x000fe2000020f000 */
/*0290*/ @P0 FMUL R9, R9, 0.5 ; /* 0x3f00000009090820 */
/* 0x002fce0000400000 */
/*02a0*/ @P0 F2I.U32.TRUNC.NTZ R7, R9 ; /* 0x0000000900070305 */
/* 0x000e24000020f000 */
/*02b0*/ PRMT R5, R7, 0x7604, R6 ; /* 0x0000760407057816 */
/* 0x001fc80000000006 */
/*02c0*/ PRMT R5, R0, 0x7054, R5 ; /* 0x0000705400057816 */
/* 0x000fc80000000005 */
/*02d0*/ PRMT R5, R4, 0x654, R5 ; /* 0x0000065404057816 */
/* 0x000fca0000000005 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.globl _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.p2align 8
.type _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii,@function
_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_bfe_i32 s3, s14, 0x180000
s_bfe_i32 s6, s15, 0x180000
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s3, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s6, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_i32_i24 v0, v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
global_load_u8 v3, v[0:1], off
global_load_u8 v2, v[0:1], off offset:1
s_waitcnt vmcnt(2)
v_cmpx_nlg_f32_e64 0x7f800000, |v4|
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v3, v3
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v3, 0.5, v3 :: v_dual_mul_f32 v2, 0.5, v2
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2)
v_cvt_i32_f32_e32 v2, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(1)
global_store_b8 v[0:1], v3, off
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off offset:1
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, .Lfunc_end0-_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001afc9f_00000000-6_colorInvalids_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii
.type _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii, @function
_Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20colorInvalids_kernelP6uchar4PKfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii, .-_Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii
.globl _Z20colorInvalids_kernelP6uchar4PKfii
.type _Z20colorInvalids_kernelP6uchar4PKfii, @function
_Z20colorInvalids_kernelP6uchar4PKfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20colorInvalids_kernelP6uchar4PKfiiP6uchar4PKfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20colorInvalids_kernelP6uchar4PKfii, .-_Z20colorInvalids_kernelP6uchar4PKfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20colorInvalids_kernelP6uchar4PKfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20colorInvalids_kernelP6uchar4PKfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "colorInvalids_kernel.hip"
.globl _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii # -- Begin function _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.p2align 4, 0x90
.type _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii,@function
_Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii: # @_Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, .Lfunc_end0-_Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii,@object # @_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.section .rodata,"a",@progbits
.globl _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.p2align 3, 0x0
_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii:
.quad _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.size _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20colorInvalids_kernelP15HIP_vector_typeIhLj4EEPKfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define SIZE 1000
#define NUM_BIN 16
__global__ void histogram_shared_memory(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int offset = blockDim.x * gridDim.x;
__shared__ int cache[256];
cache[threadIdx.x] = 0;
__syncthreads();
while (tid < SIZE)
{
atomicAdd(&(cache[device_a[tid]]), 1);
tid += offset;
}
__syncthreads();
atomicAdd(&(device_b[threadIdx.x]), cache[threadIdx.x]);
}
int main(int argc, char **argv)
{
// generate the input array on the host.
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
//host_a[i] = bit_reverse(i, log2(SIZE));
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int i = 0; i < NUM_BIN; ++i)
{
host_b[i] = 0;
}
// declare GPU memory pointers
int *device_a, *device_b;
// allocate GPU memory
cudaMalloc((void **)&device_a, SIZE * sizeof(int));
cudaMalloc((void **)&device_b, NUM_BIN * sizeof(int));
// transfer the arrays to the GPU
cudaMemcpy(device_a, host_a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, NUM_BIN * sizeof(int), cudaMemcpyHostToDevice);
// launch the kernel
histogram_shared_memory <<<SIZE / 256, 256 >>> (device_b, device_a);
// copy back the result from GPU
cudaMemcpy(host_b, device_b, NUM_BIN * sizeof(int), cudaMemcpyDeviceToHost);
printf("Histogram using 16 bin is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
// free GPU memory allocation
cudaFree(device_a);
cudaFree(device_b);
return 0;
} | code for sm_80
Function : _Z23histogram_shared_memoryPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0207 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x3e8, PT ; /* 0x000003e80000780c */
/* 0x000fe20003f06270 */
/*0100*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0110*/ @!P0 BRA 0x90 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0120*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x001fca0000000f00 */
/*0150*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0002 */
/*0160*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define SIZE 1000
#define NUM_BIN 16
__global__ void histogram_shared_memory(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int offset = blockDim.x * gridDim.x;
__shared__ int cache[256];
cache[threadIdx.x] = 0;
__syncthreads();
while (tid < SIZE)
{
atomicAdd(&(cache[device_a[tid]]), 1);
tid += offset;
}
__syncthreads();
atomicAdd(&(device_b[threadIdx.x]), cache[threadIdx.x]);
}
int main(int argc, char **argv)
{
// generate the input array on the host.
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
//host_a[i] = bit_reverse(i, log2(SIZE));
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int i = 0; i < NUM_BIN; ++i)
{
host_b[i] = 0;
}
// declare GPU memory pointers
int *device_a, *device_b;
// allocate GPU memory
cudaMalloc((void **)&device_a, SIZE * sizeof(int));
cudaMalloc((void **)&device_b, NUM_BIN * sizeof(int));
// transfer the arrays to the GPU
cudaMemcpy(device_a, host_a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, NUM_BIN * sizeof(int), cudaMemcpyHostToDevice);
// launch the kernel
histogram_shared_memory <<<SIZE / 256, 256 >>> (device_b, device_a);
// copy back the result from GPU
cudaMemcpy(host_b, device_b, NUM_BIN * sizeof(int), cudaMemcpyDeviceToHost);
printf("Histogram using 16 bin is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
// free GPU memory allocation
cudaFree(device_a);
cudaFree(device_b);
return 0;
} | .file "tmpxft_001178cb_00000000-6_4_06_histogram_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
.type _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_, @function
_Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23histogram_shared_memoryPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_, .-_Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
.globl _Z23histogram_shared_memoryPiS_
.type _Z23histogram_shared_memoryPiS_, @function
_Z23histogram_shared_memoryPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z23histogram_shared_memoryPiS_, .-_Z23histogram_shared_memoryPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Histogram using 16 bin is: \n"
.LC1:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $40, %rsp
.cfi_def_cfa_offset 4160
movq %fs:40, %rax
movq %rax, 4120(%rsp)
xorl %eax, %eax
.L12:
movl %eax, %ecx
sarl $31, %ecx
shrl $28, %ecx
leal (%rcx,%rax), %edx
andl $15, %edx
subl %ecx, %edx
movl %edx, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 48(%rsp), %rax
leaq 112(%rsp), %rdx
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4120(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $4136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z23histogram_shared_memoryPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z23histogram_shared_memoryPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#define SIZE 1000
#define NUM_BIN 16
__global__ void histogram_shared_memory(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int offset = blockDim.x * gridDim.x;
__shared__ int cache[256];
cache[threadIdx.x] = 0;
__syncthreads();
while (tid < SIZE)
{
atomicAdd(&(cache[device_a[tid]]), 1);
tid += offset;
}
__syncthreads();
atomicAdd(&(device_b[threadIdx.x]), cache[threadIdx.x]);
}
int main(int argc, char **argv)
{
// generate the input array on the host.
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
//host_a[i] = bit_reverse(i, log2(SIZE));
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int i = 0; i < NUM_BIN; ++i)
{
host_b[i] = 0;
}
// declare GPU memory pointers
int *device_a, *device_b;
// allocate GPU memory
cudaMalloc((void **)&device_a, SIZE * sizeof(int));
cudaMalloc((void **)&device_b, NUM_BIN * sizeof(int));
// transfer the arrays to the GPU
cudaMemcpy(device_a, host_a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, host_b, NUM_BIN * sizeof(int), cudaMemcpyHostToDevice);
// launch the kernel
histogram_shared_memory <<<SIZE / 256, 256 >>> (device_b, device_a);
// copy back the result from GPU
cudaMemcpy(host_b, device_b, NUM_BIN * sizeof(int), cudaMemcpyDeviceToHost);
printf("Histogram using 16 bin is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
// free GPU memory allocation
cudaFree(device_a);
cudaFree(device_b);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIZE 1000
#define NUM_BIN 16
__global__ void histogram_shared_memory(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int offset = blockDim.x * gridDim.x;
__shared__ int cache[256];
cache[threadIdx.x] = 0;
__syncthreads();
while (tid < SIZE)
{
atomicAdd(&(cache[device_a[tid]]), 1);
tid += offset;
}
__syncthreads();
atomicAdd(&(device_b[threadIdx.x]), cache[threadIdx.x]);
}
int main(int argc, char **argv)
{
// generate the input array on the host.
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
//host_a[i] = bit_reverse(i, log2(SIZE));
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int i = 0; i < NUM_BIN; ++i)
{
host_b[i] = 0;
}
// declare GPU memory pointers
int *device_a, *device_b;
// allocate GPU memory
hipMalloc((void **)&device_a, SIZE * sizeof(int));
hipMalloc((void **)&device_b, NUM_BIN * sizeof(int));
// transfer the arrays to the GPU
hipMemcpy(device_a, host_a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, NUM_BIN * sizeof(int), hipMemcpyHostToDevice);
// launch the kernel
histogram_shared_memory <<<SIZE / 256, 256 >>> (device_b, device_a);
// copy back the result from GPU
hipMemcpy(host_b, device_b, NUM_BIN * sizeof(int), hipMemcpyDeviceToHost);
printf("Histogram using 16 bin is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
// free GPU memory allocation
hipFree(device_a);
hipFree(device_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIZE 1000
#define NUM_BIN 16
__global__ void histogram_shared_memory(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int offset = blockDim.x * gridDim.x;
__shared__ int cache[256];
cache[threadIdx.x] = 0;
__syncthreads();
while (tid < SIZE)
{
atomicAdd(&(cache[device_a[tid]]), 1);
tid += offset;
}
__syncthreads();
atomicAdd(&(device_b[threadIdx.x]), cache[threadIdx.x]);
}
int main(int argc, char **argv)
{
// generate the input array on the host.
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
//host_a[i] = bit_reverse(i, log2(SIZE));
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int i = 0; i < NUM_BIN; ++i)
{
host_b[i] = 0;
}
// declare GPU memory pointers
int *device_a, *device_b;
// allocate GPU memory
hipMalloc((void **)&device_a, SIZE * sizeof(int));
hipMalloc((void **)&device_b, NUM_BIN * sizeof(int));
// transfer the arrays to the GPU
hipMemcpy(device_a, host_a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, NUM_BIN * sizeof(int), hipMemcpyHostToDevice);
// launch the kernel
histogram_shared_memory <<<SIZE / 256, 256 >>> (device_b, device_a);
// copy back the result from GPU
hipMemcpy(host_b, device_b, NUM_BIN * sizeof(int), hipMemcpyDeviceToHost);
printf("Histogram using 16 bin is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
// free GPU memory allocation
hipFree(device_a);
hipFree(device_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23histogram_shared_memoryPiS_
.globl _Z23histogram_shared_memoryPiS_
.p2align 8
.type _Z23histogram_shared_memoryPiS_,@function
_Z23histogram_shared_memoryPiS_:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v4, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 0
s_lshl_b64 s[6:7], s[4:5], 2
.LBB0_2:
global_load_b32 v6, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v6, 2, v6
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v4
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23histogram_shared_memoryPiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23histogram_shared_memoryPiS_, .Lfunc_end0-_Z23histogram_shared_memoryPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23histogram_shared_memoryPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23histogram_shared_memoryPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define SIZE 1000
#define NUM_BIN 16
__global__ void histogram_shared_memory(int *device_b, int *device_a)
{
int tid = threadIdx.x + blockDim.x * blockIdx.x;
int offset = blockDim.x * gridDim.x;
__shared__ int cache[256];
cache[threadIdx.x] = 0;
__syncthreads();
while (tid < SIZE)
{
atomicAdd(&(cache[device_a[tid]]), 1);
tid += offset;
}
__syncthreads();
atomicAdd(&(device_b[threadIdx.x]), cache[threadIdx.x]);
}
int main(int argc, char **argv)
{
// generate the input array on the host.
int host_a[SIZE];
for (int i = 0; i < SIZE; ++i)
{
//host_a[i] = bit_reverse(i, log2(SIZE));
host_a[i] = i % NUM_BIN;
}
int host_b[NUM_BIN];
for (int i = 0; i < NUM_BIN; ++i)
{
host_b[i] = 0;
}
// declare GPU memory pointers
int *device_a, *device_b;
// allocate GPU memory
hipMalloc((void **)&device_a, SIZE * sizeof(int));
hipMalloc((void **)&device_b, NUM_BIN * sizeof(int));
// transfer the arrays to the GPU
hipMemcpy(device_a, host_a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(device_b, host_b, NUM_BIN * sizeof(int), hipMemcpyHostToDevice);
// launch the kernel
histogram_shared_memory <<<SIZE / 256, 256 >>> (device_b, device_a);
// copy back the result from GPU
hipMemcpy(host_b, device_b, NUM_BIN * sizeof(int), hipMemcpyDeviceToHost);
printf("Histogram using 16 bin is: \n");
for (int i = 0; i < NUM_BIN; ++i)
{
printf("bin %d: count %d\n", i, host_b[i]);
}
// free GPU memory allocation
hipFree(device_a);
hipFree(device_b);
return 0;
} | .text
.file "4_06_histogram_shared_memory.hip"
.globl _Z38__device_stub__histogram_shared_memoryPiS_ # -- Begin function _Z38__device_stub__histogram_shared_memoryPiS_
.p2align 4, 0x90
.type _Z38__device_stub__histogram_shared_memoryPiS_,@function
_Z38__device_stub__histogram_shared_memoryPiS_: # @_Z38__device_stub__histogram_shared_memoryPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23histogram_shared_memoryPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z38__device_stub__histogram_shared_memoryPiS_, .Lfunc_end0-_Z38__device_stub__histogram_shared_memoryPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $15, %ecx
movl %ecx, 160(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
xorps %xmm0, %xmm0
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 253(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23histogram_shared_memoryPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23histogram_shared_memoryPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23histogram_shared_memoryPiS_,@object # @_Z23histogram_shared_memoryPiS_
.section .rodata,"a",@progbits
.globl _Z23histogram_shared_memoryPiS_
.p2align 3, 0x0
_Z23histogram_shared_memoryPiS_:
.quad _Z38__device_stub__histogram_shared_memoryPiS_
.size _Z23histogram_shared_memoryPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "bin %d: count %d\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23histogram_shared_memoryPiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Histogram using 16 bin is: "
.size .Lstr, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__histogram_shared_memoryPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23histogram_shared_memoryPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23histogram_shared_memoryPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0207 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0070*/ ISETP.GT.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fda0003f04270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x3e8, PT ; /* 0x000003e80000780c */
/* 0x000fe20003f06270 */
/*0100*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0110*/ @!P0 BRA 0x90 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0120*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x001fca0000000f00 */
/*0150*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0002 */
/*0160*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23histogram_shared_memoryPiS_
.globl _Z23histogram_shared_memoryPiS_
.p2align 8
.type _Z23histogram_shared_memoryPiS_,@function
_Z23histogram_shared_memoryPiS_:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v4, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 0x3e8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 0
s_lshl_b64 s[6:7], s[4:5], 2
.LBB0_2:
global_load_b32 v6, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
v_cmp_lt_i32_e32 vcc_lo, 0x3e7, v1
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v6, 2, v6
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v4
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23histogram_shared_memoryPiS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23histogram_shared_memoryPiS_, .Lfunc_end0-_Z23histogram_shared_memoryPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23histogram_shared_memoryPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23histogram_shared_memoryPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001178cb_00000000-6_4_06_histogram_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
.type _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_, @function
_Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23histogram_shared_memoryPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_, .-_Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
.globl _Z23histogram_shared_memoryPiS_
.type _Z23histogram_shared_memoryPiS_, @function
_Z23histogram_shared_memoryPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z23histogram_shared_memoryPiS_, .-_Z23histogram_shared_memoryPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Histogram using 16 bin is: \n"
.LC1:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $40, %rsp
.cfi_def_cfa_offset 4160
movq %fs:40, %rax
movq %rax, 4120(%rsp)
xorl %eax, %eax
.L12:
movl %eax, %ecx
sarl $31, %ecx
shrl $28, %ecx
leal (%rcx,%rax), %edx
andl $15, %edx
subl %ecx, %edx
movl %edx, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 48(%rsp), %rax
leaq 112(%rsp), %rdx
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L15:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4120(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $4136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z45__device_stub__Z23histogram_shared_memoryPiS_PiS_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z23histogram_shared_memoryPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z23histogram_shared_memoryPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "4_06_histogram_shared_memory.hip"
.globl _Z38__device_stub__histogram_shared_memoryPiS_ # -- Begin function _Z38__device_stub__histogram_shared_memoryPiS_
.p2align 4, 0x90
.type _Z38__device_stub__histogram_shared_memoryPiS_,@function
_Z38__device_stub__histogram_shared_memoryPiS_: # @_Z38__device_stub__histogram_shared_memoryPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23histogram_shared_memoryPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z38__device_stub__histogram_shared_memoryPiS_, .Lfunc_end0-_Z38__device_stub__histogram_shared_memoryPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $15, %ecx
movl %ecx, 160(%rsp,%rax,4)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
xorps %xmm0, %xmm0
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 253(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23histogram_shared_memoryPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23histogram_shared_memoryPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23histogram_shared_memoryPiS_,@object # @_Z23histogram_shared_memoryPiS_
.section .rodata,"a",@progbits
.globl _Z23histogram_shared_memoryPiS_
.p2align 3, 0x0
_Z23histogram_shared_memoryPiS_:
.quad _Z38__device_stub__histogram_shared_memoryPiS_
.size _Z23histogram_shared_memoryPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "bin %d: count %d\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23histogram_shared_memoryPiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Histogram using 16 bin is: "
.size .Lstr, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__histogram_shared_memoryPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23histogram_shared_memoryPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* JCudaVec - Vector operations for JCuda
* http://www.jcuda.org
*
* Copyright (c) 2013-2015 Marco Hutter - http://www.jcuda.org
*/
extern "C"
//=== Vector arithmetic ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar arithmetic ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector comparison ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar comparison ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector math (one argument) =============================================
// Calculate the arc cosine of the input argument.
extern "C"
// Calculate the nonnegative arc hyperbolic cosine of the input argument.
extern "C"
// Calculate the arc sine of the input argument.
extern "C"
// Calculate the arc hyperbolic sine of the input argument.
extern "C"
// Calculate the arc tangent of the input argument.
extern "C"
// Calculate the arc hyperbolic tangent of the input argument.
extern "C"
// Calculate the cube root of the input argument.
extern "C"
// Calculate ceiling of the input argument.
extern "C"
// Calculate the cosine of the input argument.
extern "C"
// Calculate the hyperbolic cosine of the input argument.
extern "C"
// Calculate the cosine of the input argument × p .
extern "C"
// Calculate the complementary error function of the input argument.
extern "C"
// Calculate the inverse complementary error function of the input argument.
extern "C"
// Calculate the scaled complementary error function of the input argument.
extern "C"
// Calculate the error function of the input argument.
extern "C"
// Calculate the inverse error function of the input argument.
extern "C"
// Calculate the base 10 exponential of the input argument.
extern "C"
// Calculate the base 2 exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument, minus 1.
extern "C"
// Calculate the absolute value of its argument.
extern "C"
// Calculate the largest integer less than or equal to x.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 1 for the input argument.
extern "C"
// Calculate the natural logarithm of the absolute value of the gamma function of the input argument.
extern "C"
// Calculate the base 10 logarithm of the input argument.
extern "C"
// Calculate the value of l o g e ( 1 + x ) .
extern "C"
// Calculate the base 2 logarithm of the input argument.
extern "C"
// Calculate the floating point representation of the exponent of the input argument.
extern "C"
// Calculate the natural logarithm of the input argument.
extern "C"
// Calculate the standard normal cumulative distribution function.
extern "C"
// Calculate the inverse of the standard normal cumulative distribution function.
extern "C"
// Calculate reciprocal cube root function.
extern "C"
// Round input to nearest integer value in floating-point.
extern "C"
// Round to nearest integer value in floating-point.
extern "C"
// Calculate the reciprocal of the square root of the input argument.
extern "C"
// Calculate the sine of the input argument.
extern "C"
// Calculate the hyperbolic sine of the input argument.
extern "C"
// Calculate the sine of the input argument × p .
extern "C"
// Calculate the square root of the input argument.
extern "C"
// Calculate the tangent of the input argument.
extern "C"
// Calculate the hyperbolic tangent of the input argument.
extern "C"
// Calculate the gamma function of the input argument.
extern "C"
// Truncate input argument to the integral part.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 1 for the input argument.
extern "C"
//=== Vector math (two arguments) ============================================
// Create value with given magnitude, copying sign of second value.
extern "C"
// Compute the positive difference between x and y.
extern "C"
// Divide two floating point values.
extern "C"
// Determine the maximum numeric value of the arguments.
extern "C"
// Determine the minimum numeric value of the arguments.
extern "C"
// Calculate the floating-point remainder of x / y.
extern "C"
// Calculate the square root of the sum of squares of two arguments.
extern "C"
// Return next representable single-precision floating-point value afer argument.
extern "C"
// Calculate the value of first argument to the power of second argument.
extern "C"
// Compute single-precision floating-point remainder.
extern "C"
__global__ void vec_log1pf (size_t n, float *result, float *x)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < n)
{
result[id] = log1pf(x[id]);
}
} | code for sm_80
Function : vec_log1pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ SHF.L.U32 R8, R0.reuse, 0x2, RZ ; /* 0x0000000200087819 */
/* 0x040fe200000006ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.L.U64.HI R9, R0, 0x2, R3 ; /* 0x0000000200097819 */
/* 0x000fe40000010203 */
/*00b0*/ IADD3 R2, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R3, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009037a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x0000a2000c1e1900 */
/*00e0*/ HFMA2.MMA R7, -RZ, RZ, 1.625, 0 ; /* 0x3e800000ff077435 */
/* 0x000fe200000001ff */
/*00f0*/ MOV R11, 0x3d39bf78 ; /* 0x3d39bf78000b7802 */
/* 0x000fe20000000f00 */
/*0100*/ BSSY B0, 0x2f0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0110*/ IADD3 R2, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008027a10 */
/* 0x001fc80007f3e0ff */
/*0120*/ IADD3.X R3, R9, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009037a10 */
/* 0x000fe20000ffe4ff */
/*0130*/ FADD.RZ R4, R0.reuse, 1 ; /* 0x3f80000000047421 */
/* 0x044fe2000000c000 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, 0x7f800000, PT ; /* 0x7f8000000000780c */
/* 0x000fc80003f06070 */
/*0150*/ IADD3 R4, R4, -0x3f400000, RZ ; /* 0xc0c0000004047810 */
/* 0x000fc80007ffe0ff */
/*0160*/ LOP3.LUT R5, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004057812 */
/* 0x000fc800078ec0ff */
/*0170*/ IADD3 R6, -R5, 0x40800000, RZ ; /* 0x4080000005067810 */
/* 0x000fe20007ffe1ff */
/*0180*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe400078e0a05 */
/*0190*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e240000201400 */
/*01a0*/ FFMA R7, R6, R7, -1 ; /* 0xbf80000006077423 */
/* 0x000fc80000000007 */
/*01b0*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x000fc80000000000 */
/*01c0*/ FFMA R7, R4, -R11, 0.10546888411045074463 ; /* 0x3dd8001204077423 */
/* 0x000fc8000000080b */
/*01d0*/ FFMA R7, R4, R7, -0.13229703903198242188 ; /* 0xbe0778e004077423 */
/* 0x000fc80000000007 */
/*01e0*/ FFMA R7, R4, R7, 0.14491446316242218018 ; /* 0x3e14647504077423 */
/* 0x000fc80000000007 */
/*01f0*/ FFMA R7, R4, R7, -0.16641564667224884033 ; /* 0xbe2a68dd04077423 */
/* 0x000fc80000000007 */
/*0200*/ FFMA R7, R4, R7, 0.19988867640495300293 ; /* 0x3e4caf9e04077423 */
/* 0x000fc80000000007 */
/*0210*/ FFMA R7, R4, R7, -0.25000196695327758789 ; /* 0xbe80004204077423 */
/* 0x000fc80000000007 */
/*0220*/ FFMA R7, R4, R7, 0.33333510160446166992 ; /* 0x3eaaaae604077423 */
/* 0x000fc80000000007 */
/*0230*/ FFMA R7, R4, R7, -0.5 ; /* 0xbf00000004077423 */
/* 0x000fc80000000007 */
/*0240*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x000fc80000400000 */
/*0250*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fe40000000004 */
/*0260*/ FMUL R4, R5, 1.1920928955078125e-07 ; /* 0x3400000005047820 */
/* 0x001fc80000400000 */
/*0270*/ FFMA R7, R4, 0.69314718246459960938, R7 ; /* 0x3f31721804077823 */
/* 0x000fe20000000007 */
/*0280*/ @!P0 BRA 0x2e0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GE.AND P0, PT, R0.reuse, -0x407fffff, PT ; /* 0xbf8000010000780c */
/* 0x040fe40003f06270 */
/*02a0*/ FSETP.NEU.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fd60003f2d000 */
/*02b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, 0x7f800000 ; /* 0x7f800000ff050424 */
/* 0x000fc800078e00ff */
/*02c0*/ @P0 FFMA R7, R0, R5, +INF ; /* 0x7f80000000070423 */
/* 0x000fca0000000005 */
/*02d0*/ FSEL R7, R7, -RZ, P1 ; /* 0x800000ff07077208 */
/* 0x000fe40000800000 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* JCudaVec - Vector operations for JCuda
* http://www.jcuda.org
*
* Copyright (c) 2013-2015 Marco Hutter - http://www.jcuda.org
*/
extern "C"
//=== Vector arithmetic ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar arithmetic ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector comparison ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar comparison ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector math (one argument) =============================================
// Calculate the arc cosine of the input argument.
extern "C"
// Calculate the nonnegative arc hyperbolic cosine of the input argument.
extern "C"
// Calculate the arc sine of the input argument.
extern "C"
// Calculate the arc hyperbolic sine of the input argument.
extern "C"
// Calculate the arc tangent of the input argument.
extern "C"
// Calculate the arc hyperbolic tangent of the input argument.
extern "C"
// Calculate the cube root of the input argument.
extern "C"
// Calculate ceiling of the input argument.
extern "C"
// Calculate the cosine of the input argument.
extern "C"
// Calculate the hyperbolic cosine of the input argument.
extern "C"
// Calculate the cosine of the input argument × p .
extern "C"
// Calculate the complementary error function of the input argument.
extern "C"
// Calculate the inverse complementary error function of the input argument.
extern "C"
// Calculate the scaled complementary error function of the input argument.
extern "C"
// Calculate the error function of the input argument.
extern "C"
// Calculate the inverse error function of the input argument.
extern "C"
// Calculate the base 10 exponential of the input argument.
extern "C"
// Calculate the base 2 exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument, minus 1.
extern "C"
// Calculate the absolute value of its argument.
extern "C"
// Calculate the largest integer less than or equal to x.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 1 for the input argument.
extern "C"
// Calculate the natural logarithm of the absolute value of the gamma function of the input argument.
extern "C"
// Calculate the base 10 logarithm of the input argument.
extern "C"
// Calculate the value of l o g e ( 1 + x ) .
extern "C"
// Calculate the base 2 logarithm of the input argument.
extern "C"
// Calculate the floating point representation of the exponent of the input argument.
extern "C"
// Calculate the natural logarithm of the input argument.
extern "C"
// Calculate the standard normal cumulative distribution function.
extern "C"
// Calculate the inverse of the standard normal cumulative distribution function.
extern "C"
// Calculate reciprocal cube root function.
extern "C"
// Round input to nearest integer value in floating-point.
extern "C"
// Round to nearest integer value in floating-point.
extern "C"
// Calculate the reciprocal of the square root of the input argument.
extern "C"
// Calculate the sine of the input argument.
extern "C"
// Calculate the hyperbolic sine of the input argument.
extern "C"
// Calculate the sine of the input argument × p .
extern "C"
// Calculate the square root of the input argument.
extern "C"
// Calculate the tangent of the input argument.
extern "C"
// Calculate the hyperbolic tangent of the input argument.
extern "C"
// Calculate the gamma function of the input argument.
extern "C"
// Truncate input argument to the integral part.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 1 for the input argument.
extern "C"
//=== Vector math (two arguments) ============================================
// Create value with given magnitude, copying sign of second value.
extern "C"
// Compute the positive difference between x and y.
extern "C"
// Divide two floating point values.
extern "C"
// Determine the maximum numeric value of the arguments.
extern "C"
// Determine the minimum numeric value of the arguments.
extern "C"
// Calculate the floating-point remainder of x / y.
extern "C"
// Calculate the square root of the sum of squares of two arguments.
extern "C"
// Return next representable single-precision floating-point value afer argument.
extern "C"
// Calculate the value of first argument to the power of second argument.
extern "C"
// Compute single-precision floating-point remainder.
extern "C"
__global__ void vec_log1pf (size_t n, float *result, float *x)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < n)
{
result[id] = log1pf(x[id]);
}
} | .file "tmpxft_00081b5c_00000000-6_vec_log1pf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_
.type _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_, @function
_Z33__device_stub__Z10vec_log1pfmPfS_mPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vec_log1pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_, .-_Z33__device_stub__Z10vec_log1pfmPfS_mPfS_
.globl vec_log1pf
.type vec_log1pf, @function
vec_log1pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vec_log1pf, .-vec_log1pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vec_log1pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vec_log1pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* JCudaVec - Vector operations for JCuda
* http://www.jcuda.org
*
* Copyright (c) 2013-2015 Marco Hutter - http://www.jcuda.org
*/
extern "C"
//=== Vector arithmetic ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar arithmetic ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector comparison ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar comparison ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector math (one argument) =============================================
// Calculate the arc cosine of the input argument.
extern "C"
// Calculate the nonnegative arc hyperbolic cosine of the input argument.
extern "C"
// Calculate the arc sine of the input argument.
extern "C"
// Calculate the arc hyperbolic sine of the input argument.
extern "C"
// Calculate the arc tangent of the input argument.
extern "C"
// Calculate the arc hyperbolic tangent of the input argument.
extern "C"
// Calculate the cube root of the input argument.
extern "C"
// Calculate ceiling of the input argument.
extern "C"
// Calculate the cosine of the input argument.
extern "C"
// Calculate the hyperbolic cosine of the input argument.
extern "C"
// Calculate the cosine of the input argument × p .
extern "C"
// Calculate the complementary error function of the input argument.
extern "C"
// Calculate the inverse complementary error function of the input argument.
extern "C"
// Calculate the scaled complementary error function of the input argument.
extern "C"
// Calculate the error function of the input argument.
extern "C"
// Calculate the inverse error function of the input argument.
extern "C"
// Calculate the base 10 exponential of the input argument.
extern "C"
// Calculate the base 2 exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument, minus 1.
extern "C"
// Calculate the absolute value of its argument.
extern "C"
// Calculate the largest integer less than or equal to x.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 1 for the input argument.
extern "C"
// Calculate the natural logarithm of the absolute value of the gamma function of the input argument.
extern "C"
// Calculate the base 10 logarithm of the input argument.
extern "C"
// Calculate the value of l o g e ( 1 + x ) .
extern "C"
// Calculate the base 2 logarithm of the input argument.
extern "C"
// Calculate the floating point representation of the exponent of the input argument.
extern "C"
// Calculate the natural logarithm of the input argument.
extern "C"
// Calculate the standard normal cumulative distribution function.
extern "C"
// Calculate the inverse of the standard normal cumulative distribution function.
extern "C"
// Calculate reciprocal cube root function.
extern "C"
// Round input to nearest integer value in floating-point.
extern "C"
// Round to nearest integer value in floating-point.
extern "C"
// Calculate the reciprocal of the square root of the input argument.
extern "C"
// Calculate the sine of the input argument.
extern "C"
// Calculate the hyperbolic sine of the input argument.
extern "C"
// Calculate the sine of the input argument × p .
extern "C"
// Calculate the square root of the input argument.
extern "C"
// Calculate the tangent of the input argument.
extern "C"
// Calculate the hyperbolic tangent of the input argument.
extern "C"
// Calculate the gamma function of the input argument.
extern "C"
// Truncate input argument to the integral part.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 1 for the input argument.
extern "C"
//=== Vector math (two arguments) ============================================
// Create value with given magnitude, copying sign of second value.
extern "C"
// Compute the positive difference between x and y.
extern "C"
// Divide two floating point values.
extern "C"
// Determine the maximum numeric value of the arguments.
extern "C"
// Determine the minimum numeric value of the arguments.
extern "C"
// Calculate the floating-point remainder of x / y.
extern "C"
// Calculate the square root of the sum of squares of two arguments.
extern "C"
// Return next representable single-precision floating-point value afer argument.
extern "C"
// Calculate the value of first argument to the power of second argument.
extern "C"
// Compute single-precision floating-point remainder.
extern "C"
__global__ void vec_log1pf (size_t n, float *result, float *x)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < n)
{
result[id] = log1pf(x[id]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* JCudaVec - Vector operations for JCuda
* http://www.jcuda.org
*
* Copyright (c) 2013-2015 Marco Hutter - http://www.jcuda.org
*/
extern "C"
//=== Vector arithmetic ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar arithmetic ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector comparison ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar comparison ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector math (one argument) =============================================
// Calculate the arc cosine of the input argument.
extern "C"
// Calculate the nonnegative arc hyperbolic cosine of the input argument.
extern "C"
// Calculate the arc sine of the input argument.
extern "C"
// Calculate the arc hyperbolic sine of the input argument.
extern "C"
// Calculate the arc tangent of the input argument.
extern "C"
// Calculate the arc hyperbolic tangent of the input argument.
extern "C"
// Calculate the cube root of the input argument.
extern "C"
// Calculate ceiling of the input argument.
extern "C"
// Calculate the cosine of the input argument.
extern "C"
// Calculate the hyperbolic cosine of the input argument.
extern "C"
// Calculate the cosine of the input argument × p .
extern "C"
// Calculate the complementary error function of the input argument.
extern "C"
// Calculate the inverse complementary error function of the input argument.
extern "C"
// Calculate the scaled complementary error function of the input argument.
extern "C"
// Calculate the error function of the input argument.
extern "C"
// Calculate the inverse error function of the input argument.
extern "C"
// Calculate the base 10 exponential of the input argument.
extern "C"
// Calculate the base 2 exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument, minus 1.
extern "C"
// Calculate the absolute value of its argument.
extern "C"
// Calculate the largest integer less than or equal to x.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 1 for the input argument.
extern "C"
// Calculate the natural logarithm of the absolute value of the gamma function of the input argument.
extern "C"
// Calculate the base 10 logarithm of the input argument.
extern "C"
// Calculate the value of l o g e ( 1 + x ) .
extern "C"
// Calculate the base 2 logarithm of the input argument.
extern "C"
// Calculate the floating point representation of the exponent of the input argument.
extern "C"
// Calculate the natural logarithm of the input argument.
extern "C"
// Calculate the standard normal cumulative distribution function.
extern "C"
// Calculate the inverse of the standard normal cumulative distribution function.
extern "C"
// Calculate reciprocal cube root function.
extern "C"
// Round input to nearest integer value in floating-point.
extern "C"
// Round to nearest integer value in floating-point.
extern "C"
// Calculate the reciprocal of the square root of the input argument.
extern "C"
// Calculate the sine of the input argument.
extern "C"
// Calculate the hyperbolic sine of the input argument.
extern "C"
// Calculate the sine of the input argument × p .
extern "C"
// Calculate the square root of the input argument.
extern "C"
// Calculate the tangent of the input argument.
extern "C"
// Calculate the hyperbolic tangent of the input argument.
extern "C"
// Calculate the gamma function of the input argument.
extern "C"
// Truncate input argument to the integral part.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 1 for the input argument.
extern "C"
//=== Vector math (two arguments) ============================================
// Create value with given magnitude, copying sign of second value.
extern "C"
// Compute the positive difference between x and y.
extern "C"
// Divide two floating point values.
extern "C"
// Determine the maximum numeric value of the arguments.
extern "C"
// Determine the minimum numeric value of the arguments.
extern "C"
// Calculate the floating-point remainder of x / y.
extern "C"
// Calculate the square root of the sum of squares of two arguments.
extern "C"
// Return next representable single-precision floating-point value afer argument.
extern "C"
// Calculate the value of first argument to the power of second argument.
extern "C"
// Compute single-precision floating-point remainder.
extern "C"
__global__ void vec_log1pf (size_t n, float *result, float *x)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < n)
{
result[id] = log1pf(x[id]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* JCudaVec - Vector operations for JCuda
* http://www.jcuda.org
*
* Copyright (c) 2013-2015 Marco Hutter - http://www.jcuda.org
*/
extern "C"
//=== Vector arithmetic ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar arithmetic ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector comparison ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar comparison ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector math (one argument) =============================================
// Calculate the arc cosine of the input argument.
extern "C"
// Calculate the nonnegative arc hyperbolic cosine of the input argument.
extern "C"
// Calculate the arc sine of the input argument.
extern "C"
// Calculate the arc hyperbolic sine of the input argument.
extern "C"
// Calculate the arc tangent of the input argument.
extern "C"
// Calculate the arc hyperbolic tangent of the input argument.
extern "C"
// Calculate the cube root of the input argument.
extern "C"
// Calculate ceiling of the input argument.
extern "C"
// Calculate the cosine of the input argument.
extern "C"
// Calculate the hyperbolic cosine of the input argument.
extern "C"
// Calculate the cosine of the input argument × p .
extern "C"
// Calculate the complementary error function of the input argument.
extern "C"
// Calculate the inverse complementary error function of the input argument.
extern "C"
// Calculate the scaled complementary error function of the input argument.
extern "C"
// Calculate the error function of the input argument.
extern "C"
// Calculate the inverse error function of the input argument.
extern "C"
// Calculate the base 10 exponential of the input argument.
extern "C"
// Calculate the base 2 exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument, minus 1.
extern "C"
// Calculate the absolute value of its argument.
extern "C"
// Calculate the largest integer less than or equal to x.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 1 for the input argument.
extern "C"
// Calculate the natural logarithm of the absolute value of the gamma function of the input argument.
extern "C"
// Calculate the base 10 logarithm of the input argument.
extern "C"
// Calculate the value of l o g e ( 1 + x ) .
extern "C"
// Calculate the base 2 logarithm of the input argument.
extern "C"
// Calculate the floating point representation of the exponent of the input argument.
extern "C"
// Calculate the natural logarithm of the input argument.
extern "C"
// Calculate the standard normal cumulative distribution function.
extern "C"
// Calculate the inverse of the standard normal cumulative distribution function.
extern "C"
// Calculate reciprocal cube root function.
extern "C"
// Round input to nearest integer value in floating-point.
extern "C"
// Round to nearest integer value in floating-point.
extern "C"
// Calculate the reciprocal of the square root of the input argument.
extern "C"
// Calculate the sine of the input argument.
extern "C"
// Calculate the hyperbolic sine of the input argument.
extern "C"
// Calculate the sine of the input argument × p .
extern "C"
// Calculate the square root of the input argument.
extern "C"
// Calculate the tangent of the input argument.
extern "C"
// Calculate the hyperbolic tangent of the input argument.
extern "C"
// Calculate the gamma function of the input argument.
extern "C"
// Truncate input argument to the integral part.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 1 for the input argument.
extern "C"
//=== Vector math (two arguments) ============================================
// Create value with given magnitude, copying sign of second value.
extern "C"
// Compute the positive difference between x and y.
extern "C"
// Divide two floating point values.
extern "C"
// Determine the maximum numeric value of the arguments.
extern "C"
// Determine the minimum numeric value of the arguments.
extern "C"
// Calculate the floating-point remainder of x / y.
extern "C"
// Calculate the square root of the sum of squares of two arguments.
extern "C"
// Return next representable single-precision floating-point value afer argument.
extern "C"
// Calculate the value of first argument to the power of second argument.
extern "C"
// Compute single-precision floating-point remainder.
extern "C"
__global__ void vec_log1pf (size_t n, float *result, float *x)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < n)
{
result[id] = log1pf(x[id]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vec_log1pf
.globl vec_log1pf
.p2align 8
.type vec_log1pf,@function
vec_log1pf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, 0x3e9b6dac
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v4, v3
v_frexp_exp_i32_f32_e32 v5, v3
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
v_add_f32_e32 v5, -1.0, v3
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
v_sub_nc_u32_e32 v6, 0, v4
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v5, v3
v_ldexp_f32 v3, v3, v6
v_sub_f32_e32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, 1.0, v7
v_add_f32_e32 v8, 1.0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v7, -1.0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ldexp_f32 v5, v5, v6
v_add_f32_e32 v6, -1.0, v3
v_sub_f32_e32 v7, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 1.0, v6
v_add_f32_e32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v9
v_add_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v5, v3
v_rcp_f32_e32 v5, v9
v_sub_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v10, v6, v3 :: v_dual_sub_f32 v7, v7, v8
v_sub_f32_e32 v6, v10, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v6 :: v_dual_mul_f32 v12, v9, v11
v_fma_f32 v8, v11, v9, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v11, v7
v_add_f32_e32 v13, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v14, v10, v13
v_sub_f32_e32 v6, v13, v12
v_sub_f32_e32 v10, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v8
v_sub_f32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v10
v_add_f32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v14, v3
v_mul_f32_e32 v8, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v13, v14, v6 :: v_dual_mul_f32 v10, v9, v8
v_fma_f32 v9, v8, v9, -v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v7
v_add_f32_e32 v7, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v6, v7
v_sub_f32_e32 v10, v7, v10
v_dual_add_f32 v3, v3, v13 :: v_dual_sub_f32 v6, v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_add_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v11, v8 :: v_dual_sub_f32 v7, v10, v9
v_add_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v6, v11
v_add_f32_e32 v3, v12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v8, v7
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v3
v_add_f32_e32 v5, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v5, v5
v_fmaak_f32 v8, s2, v7, 0x3ecc95a3
v_mul_f32_e32 v9, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmaak_f32 v7, v7, v8, 0x3f2aaada
v_ldexp_f32 v8, v5, 1
v_sub_f32_e32 v5, v5, v6
v_mul_f32_e32 v7, v9, v7
v_mul_f32_e32 v9, 0x3f317218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v5 :: v_dual_add_f32 v6, v8, v7
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v6, v8
v_fma_f32 v8, v4, 0x3f317218, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v7, v5 :: v_dual_fmamk_f32 v4, v4, 0xb102e308, v8
v_add_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v9, v4
v_add_f32_e32 v7, v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v5, v9
v_add_f32_e32 v8, v5, v7
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v9
v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v8, v10
v_dual_sub_f32 v6, v7, v10 :: v_dual_add_f32 v7, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v11
v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v7, v5
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v8, v5
v_sub_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v9, v8
v_dual_add_f32 v3, v3, v4 :: v_dual_sub_f32 v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, -1.0, v2
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, -1.0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0xff800000, v3, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x33800000, |v2|
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vec_log1pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vec_log1pf, .Lfunc_end0-vec_log1pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vec_log1pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vec_log1pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* JCudaVec - Vector operations for JCuda
* http://www.jcuda.org
*
* Copyright (c) 2013-2015 Marco Hutter - http://www.jcuda.org
*/
extern "C"
//=== Vector arithmetic ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar arithmetic ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector comparison ======================================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector-and-scalar comparison ===========================================
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
extern "C"
//=== Vector math (one argument) =============================================
// Calculate the arc cosine of the input argument.
extern "C"
// Calculate the nonnegative arc hyperbolic cosine of the input argument.
extern "C"
// Calculate the arc sine of the input argument.
extern "C"
// Calculate the arc hyperbolic sine of the input argument.
extern "C"
// Calculate the arc tangent of the input argument.
extern "C"
// Calculate the arc hyperbolic tangent of the input argument.
extern "C"
// Calculate the cube root of the input argument.
extern "C"
// Calculate ceiling of the input argument.
extern "C"
// Calculate the cosine of the input argument.
extern "C"
// Calculate the hyperbolic cosine of the input argument.
extern "C"
// Calculate the cosine of the input argument × p .
extern "C"
// Calculate the complementary error function of the input argument.
extern "C"
// Calculate the inverse complementary error function of the input argument.
extern "C"
// Calculate the scaled complementary error function of the input argument.
extern "C"
// Calculate the error function of the input argument.
extern "C"
// Calculate the inverse error function of the input argument.
extern "C"
// Calculate the base 10 exponential of the input argument.
extern "C"
// Calculate the base 2 exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument.
extern "C"
// Calculate the base e exponential of the input argument, minus 1.
extern "C"
// Calculate the absolute value of its argument.
extern "C"
// Calculate the largest integer less than or equal to x.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the first kind of order 1 for the input argument.
extern "C"
// Calculate the natural logarithm of the absolute value of the gamma function of the input argument.
extern "C"
// Calculate the base 10 logarithm of the input argument.
extern "C"
// Calculate the value of l o g e ( 1 + x ) .
extern "C"
// Calculate the base 2 logarithm of the input argument.
extern "C"
// Calculate the floating point representation of the exponent of the input argument.
extern "C"
// Calculate the natural logarithm of the input argument.
extern "C"
// Calculate the standard normal cumulative distribution function.
extern "C"
// Calculate the inverse of the standard normal cumulative distribution function.
extern "C"
// Calculate reciprocal cube root function.
extern "C"
// Round input to nearest integer value in floating-point.
extern "C"
// Round to nearest integer value in floating-point.
extern "C"
// Calculate the reciprocal of the square root of the input argument.
extern "C"
// Calculate the sine of the input argument.
extern "C"
// Calculate the hyperbolic sine of the input argument.
extern "C"
// Calculate the sine of the input argument × p .
extern "C"
// Calculate the square root of the input argument.
extern "C"
// Calculate the tangent of the input argument.
extern "C"
// Calculate the hyperbolic tangent of the input argument.
extern "C"
// Calculate the gamma function of the input argument.
extern "C"
// Truncate input argument to the integral part.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 0 for the input argument.
extern "C"
// Calculate the value of the Bessel function of the second kind of order 1 for the input argument.
extern "C"
//=== Vector math (two arguments) ============================================
// Create value with given magnitude, copying sign of second value.
extern "C"
// Compute the positive difference between x and y.
extern "C"
// Divide two floating point values.
extern "C"
// Determine the maximum numeric value of the arguments.
extern "C"
// Determine the minimum numeric value of the arguments.
extern "C"
// Calculate the floating-point remainder of x / y.
extern "C"
// Calculate the square root of the sum of squares of two arguments.
extern "C"
// Return next representable single-precision floating-point value afer argument.
extern "C"
// Calculate the value of first argument to the power of second argument.
extern "C"
// Compute single-precision floating-point remainder.
extern "C"
__global__ void vec_log1pf (size_t n, float *result, float *x)
{
int id = threadIdx.x + blockIdx.x * blockDim.x;
if (id < n)
{
result[id] = log1pf(x[id]);
}
} | .text
.file "vec_log1pf.hip"
.globl __device_stub__vec_log1pf # -- Begin function __device_stub__vec_log1pf
.p2align 4, 0x90
.type __device_stub__vec_log1pf,@function
__device_stub__vec_log1pf: # @__device_stub__vec_log1pf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $vec_log1pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__vec_log1pf, .Lfunc_end0-__device_stub__vec_log1pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vec_log1pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type vec_log1pf,@object # @vec_log1pf
.section .rodata,"a",@progbits
.globl vec_log1pf
.p2align 3, 0x0
vec_log1pf:
.quad __device_stub__vec_log1pf
.size vec_log1pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vec_log1pf"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vec_log1pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vec_log1pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : vec_log1pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ SHF.L.U32 R8, R0.reuse, 0x2, RZ ; /* 0x0000000200087819 */
/* 0x040fe200000006ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.L.U64.HI R9, R0, 0x2, R3 ; /* 0x0000000200097819 */
/* 0x000fe40000010203 */
/*00b0*/ IADD3 R2, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R3, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009037a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x0000a2000c1e1900 */
/*00e0*/ HFMA2.MMA R7, -RZ, RZ, 1.625, 0 ; /* 0x3e800000ff077435 */
/* 0x000fe200000001ff */
/*00f0*/ MOV R11, 0x3d39bf78 ; /* 0x3d39bf78000b7802 */
/* 0x000fe20000000f00 */
/*0100*/ BSSY B0, 0x2f0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0110*/ IADD3 R2, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008027a10 */
/* 0x001fc80007f3e0ff */
/*0120*/ IADD3.X R3, R9, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0009037a10 */
/* 0x000fe20000ffe4ff */
/*0130*/ FADD.RZ R4, R0.reuse, 1 ; /* 0x3f80000000047421 */
/* 0x044fe2000000c000 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, 0x7f800000, PT ; /* 0x7f8000000000780c */
/* 0x000fc80003f06070 */
/*0150*/ IADD3 R4, R4, -0x3f400000, RZ ; /* 0xc0c0000004047810 */
/* 0x000fc80007ffe0ff */
/*0160*/ LOP3.LUT R5, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004057812 */
/* 0x000fc800078ec0ff */
/*0170*/ IADD3 R6, -R5, 0x40800000, RZ ; /* 0x4080000005067810 */
/* 0x000fe20007ffe1ff */
/*0180*/ IMAD.IADD R4, R0, 0x1, -R5 ; /* 0x0000000100047824 */
/* 0x000fe400078e0a05 */
/*0190*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e240000201400 */
/*01a0*/ FFMA R7, R6, R7, -1 ; /* 0xbf80000006077423 */
/* 0x000fc80000000007 */
/*01b0*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x000fc80000000000 */
/*01c0*/ FFMA R7, R4, -R11, 0.10546888411045074463 ; /* 0x3dd8001204077423 */
/* 0x000fc8000000080b */
/*01d0*/ FFMA R7, R4, R7, -0.13229703903198242188 ; /* 0xbe0778e004077423 */
/* 0x000fc80000000007 */
/*01e0*/ FFMA R7, R4, R7, 0.14491446316242218018 ; /* 0x3e14647504077423 */
/* 0x000fc80000000007 */
/*01f0*/ FFMA R7, R4, R7, -0.16641564667224884033 ; /* 0xbe2a68dd04077423 */
/* 0x000fc80000000007 */
/*0200*/ FFMA R7, R4, R7, 0.19988867640495300293 ; /* 0x3e4caf9e04077423 */
/* 0x000fc80000000007 */
/*0210*/ FFMA R7, R4, R7, -0.25000196695327758789 ; /* 0xbe80004204077423 */
/* 0x000fc80000000007 */
/*0220*/ FFMA R7, R4, R7, 0.33333510160446166992 ; /* 0x3eaaaae604077423 */
/* 0x000fc80000000007 */
/*0230*/ FFMA R7, R4, R7, -0.5 ; /* 0xbf00000004077423 */
/* 0x000fc80000000007 */
/*0240*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x000fc80000400000 */
/*0250*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fe40000000004 */
/*0260*/ FMUL R4, R5, 1.1920928955078125e-07 ; /* 0x3400000005047820 */
/* 0x001fc80000400000 */
/*0270*/ FFMA R7, R4, 0.69314718246459960938, R7 ; /* 0x3f31721804077823 */
/* 0x000fe20000000007 */
/*0280*/ @!P0 BRA 0x2e0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GE.AND P0, PT, R0.reuse, -0x407fffff, PT ; /* 0xbf8000010000780c */
/* 0x040fe40003f06270 */
/*02a0*/ FSETP.NEU.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fd60003f2d000 */
/*02b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, 0x7f800000 ; /* 0x7f800000ff050424 */
/* 0x000fc800078e00ff */
/*02c0*/ @P0 FFMA R7, R0, R5, +INF ; /* 0x7f80000000070423 */
/* 0x000fca0000000005 */
/*02d0*/ FSEL R7, R7, -RZ, P1 ; /* 0x800000ff07077208 */
/* 0x000fe40000800000 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vec_log1pf
.globl vec_log1pf
.p2align 8
.type vec_log1pf,@function
vec_log1pf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, 0x3e9b6dac
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v4, v3
v_frexp_exp_i32_f32_e32 v5, v3
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
v_add_f32_e32 v5, -1.0, v3
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
v_sub_nc_u32_e32 v6, 0, v4
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v5, v3
v_ldexp_f32 v3, v3, v6
v_sub_f32_e32 v5, v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, 1.0, v7
v_add_f32_e32 v8, 1.0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v7, -1.0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ldexp_f32 v5, v5, v6
v_add_f32_e32 v6, -1.0, v3
v_sub_f32_e32 v7, v3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 1.0, v6
v_add_f32_e32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v9
v_add_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v5, v3
v_rcp_f32_e32 v5, v9
v_sub_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v10, v6, v3 :: v_dual_sub_f32 v7, v7, v8
v_sub_f32_e32 v6, v10, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v6 :: v_dual_mul_f32 v12, v9, v11
v_fma_f32 v8, v11, v9, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v11, v7
v_add_f32_e32 v13, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v14, v10, v13
v_sub_f32_e32 v6, v13, v12
v_sub_f32_e32 v10, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v8
v_sub_f32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v10
v_add_f32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v14, v3
v_mul_f32_e32 v8, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v13, v14, v6 :: v_dual_mul_f32 v10, v9, v8
v_fma_f32 v9, v8, v9, -v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v7
v_add_f32_e32 v7, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v6, v7
v_sub_f32_e32 v10, v7, v10
v_dual_add_f32 v3, v3, v13 :: v_dual_sub_f32 v6, v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_add_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v11, v8 :: v_dual_sub_f32 v7, v10, v9
v_add_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v6, v11
v_add_f32_e32 v3, v12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v8, v7
v_mul_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v7, v3
v_add_f32_e32 v5, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v5, v5
v_fmaak_f32 v8, s2, v7, 0x3ecc95a3
v_mul_f32_e32 v9, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmaak_f32 v7, v7, v8, 0x3f2aaada
v_ldexp_f32 v8, v5, 1
v_sub_f32_e32 v5, v5, v6
v_mul_f32_e32 v7, v9, v7
v_mul_f32_e32 v9, 0x3f317218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v3, v5 :: v_dual_add_f32 v6, v8, v7
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v6, v8
v_fma_f32 v8, v4, 0x3f317218, -v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v7, v5 :: v_dual_fmamk_f32 v4, v4, 0xb102e308, v8
v_add_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v9, v4
v_add_f32_e32 v7, v6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v5, v9
v_add_f32_e32 v8, v5, v7
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v9
v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v8, v10
v_dual_sub_f32 v6, v7, v10 :: v_dual_add_f32 v7, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v11
v_dual_add_f32 v5, v6, v5 :: v_dual_sub_f32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v7, v5
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v8, v5
v_sub_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v9, v8
v_dual_add_f32 v3, v3, v4 :: v_dual_sub_f32 v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
v_add_f32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, -1.0, v2
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, -1.0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0xff800000, v3, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x33800000, |v2|
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vec_log1pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vec_log1pf, .Lfunc_end0-vec_log1pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vec_log1pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vec_log1pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00081b5c_00000000-6_vec_log1pf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_
.type _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_, @function
_Z33__device_stub__Z10vec_log1pfmPfS_mPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vec_log1pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_, .-_Z33__device_stub__Z10vec_log1pfmPfS_mPfS_
.globl vec_log1pf
.type vec_log1pf, @function
vec_log1pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10vec_log1pfmPfS_mPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vec_log1pf, .-vec_log1pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vec_log1pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vec_log1pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_log1pf.hip"
.globl __device_stub__vec_log1pf # -- Begin function __device_stub__vec_log1pf
.p2align 4, 0x90
.type __device_stub__vec_log1pf,@function
__device_stub__vec_log1pf: # @__device_stub__vec_log1pf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $vec_log1pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__vec_log1pf, .Lfunc_end0-__device_stub__vec_log1pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vec_log1pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type vec_log1pf,@object # @vec_log1pf
.section .rodata,"a",@progbits
.globl vec_log1pf
.p2align 3, 0x0
vec_log1pf:
.quad __device_stub__vec_log1pf
.size vec_log1pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vec_log1pf"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vec_log1pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vec_log1pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
//some of the materials here was reused or based on NERSC/OLCF cuda training-series (https://github.com/olcf/cuda-training-series)
#define cudaCheck(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
#define DATA_SIZE 1024*1024*32
void result_check(float *A, float *B, float *C);
// kernel
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size);
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size);
int main(){
float *A_h, *B_h, *C_h; // host pointers
float *A_d, *B_d, *C_d;// device pointers
A_h = new float[DATA_SIZE]; // allocating host arrays
B_h = new float[DATA_SIZE];
C_h = new float[DATA_SIZE];
for (int i = 0; i < DATA_SIZE; i++){ // initializing host vectors
A_h[i] = rand()/(float)RAND_MAX;
B_h[i] = rand()/(float)RAND_MAX;
C_h[i] = 0;
}
cudaMalloc(&A_d, DATA_SIZE*sizeof(float)); //allocate memory for device vectors
cudaMalloc(&B_d, DATA_SIZE*sizeof(float));
cudaMalloc(&C_d, DATA_SIZE*sizeof(float));
cudaCheck("Error in cudaMallocs"); //check if any errors during memory allocation on device
// copy host vectors to device
cudaMemcpy(A_d, A_h, DATA_SIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, DATA_SIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaCheck("host to device copy error");
int blocks = 4; // to set number of blocks
int threads = 256; // to set number of threads per block
// set memory stride size
//*************************************************************************************///
//*********** uncomment the below kernel for studying launch configurations ***********///
//*************************************************************************************///
vector_add_kernel<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE);
//*************************************************************************************///
//*********** uncomment the below two lines to study memory caching and coalescing ***********///
//*************************************************************************************///
// int mem_stride = 8;
// vector_add_kernel_memory<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE, mem_stride);
cudaCheck("kernel launch error");
// copy result vector from device to host
cudaMemcpy(C_h, C_d, DATA_SIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaCheck("device to host copy error or kernel launch failure");
result_check(A_h, B_h, C_h);
return 0;
} // end main
void result_check(float *A, float *B, float *C){
int errors = 0;
for(int i = 0; i < DATA_SIZE; i++){
if(A[i] + B[i] != C[i]){
errors++;
}
}
if(errors == 0){
std::cout<<"\tCorrectness Test Passed\n";
}else{
std::cout<<"\tCorrectness Test Failed\n";
}
}
// kernel for launch configurations
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
for(int i = idx; i < size; i+=total_threads)
C[i] = A[i] + B[i];
}
// kernel for stuyding effect of caching
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
int strides_per_thread = size/(total_threads*stride_size);
for(int j = 0; j < strides_per_thread; j++){
int stride_begin = stride_size * idx + j * stride_size * total_threads;
int stride_end = stride_size + stride_begin;
for(int i = stride_begin; i < stride_end; i++ ){
C[i] = A[i] + B[i];
}
}
} | .file "tmpxft_001a8055_00000000-6_vec_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\tCorrectness Test Passed\n"
.LC1:
.string "\tCorrectness Test Failed\n"
.text
.globl _Z12result_checkPfS_S_
.type _Z12result_checkPfS_S_, @function
_Z12result_checkPfS_S_:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %eax
movl $0, %ecx
jmp .L6
.L9:
addl $1, %ecx
.L4:
addq $4, %rax
cmpq $134217728, %rax
je .L12
.L6:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L9
je .L4
jmp .L9
.L12:
testl %ecx, %ecx
jne .L7
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl $25, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L3
.cfi_endproc
.LFE3670:
.size _Z12result_checkPfS_S_, .-_Z12result_checkPfS_S_
.globl _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
.type _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi, @function
_Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17vector_add_kernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi, .-_Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
.globl _Z17vector_add_kernelPKfS0_Pfi
.type _Z17vector_add_kernelPKfS0_Pfi, @function
_Z17vector_add_kernelPKfS0_Pfi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z17vector_add_kernelPKfS0_Pfi, .-_Z17vector_add_kernelPKfS0_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mgawan/nersc_cuda_tutorial/master/Session-2/vec_add.cu"
.section .rodata.str1.1
.LC5:
.string "Error in cudaMallocs"
.section .rodata.str1.8
.align 8
.LC6:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC7:
.string "*** FAILED - ABORTING\n"
.LC8:
.string "host to device copy error"
.LC9:
.string "kernel launch error"
.section .rodata.str1.8
.align 8
.LC10:
.string "device to host copy error or kernel launch failure"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $134217728, %edi
call _Znam@PLT
movq %rax, %rbp
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r12
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %ebx
.L22:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
movl $0x00000000, 0(%r13,%rbx)
addq $4, %rbx
cmpq $134217728, %rbx
jne .L22
leaq 8(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
movl $1, %ecx
movl $134217728, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $134217728, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L34
movl $2, %ecx
movl $134217728, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z12result_checkPfS_S_
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $45
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $49
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl $33554432, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
jmp .L25
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $67
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC9(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $70
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC10(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii
.type _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii, @function
_Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24vector_add_kernel_memoryPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii, .-_Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii
.globl _Z24vector_add_kernel_memoryPKfS0_Pfii
.type _Z24vector_add_kernel_memoryPKfS0_Pfii, @function
_Z24vector_add_kernel_memoryPKfS0_Pfii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z24vector_add_kernel_memoryPKfS0_Pfii, .-_Z24vector_add_kernel_memoryPKfS0_Pfii
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z24vector_add_kernel_memoryPKfS0_Pfii"
.align 8
.LC12:
.string "_Z17vector_add_kernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z24vector_add_kernel_memoryPKfS0_Pfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z17vector_add_kernelPKfS0_Pfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
//some of the materials here was reused or based on NERSC/OLCF cuda training-series (https://github.com/olcf/cuda-training-series)
#define cudaCheck(msg) \
do { \
cudaError_t __err = cudaGetLastError(); \
if (__err != cudaSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, cudaGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
#define DATA_SIZE 1024*1024*32
void result_check(float *A, float *B, float *C);
// kernel
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size);
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size);
int main(){
float *A_h, *B_h, *C_h; // host pointers
float *A_d, *B_d, *C_d;// device pointers
A_h = new float[DATA_SIZE]; // allocating host arrays
B_h = new float[DATA_SIZE];
C_h = new float[DATA_SIZE];
for (int i = 0; i < DATA_SIZE; i++){ // initializing host vectors
A_h[i] = rand()/(float)RAND_MAX;
B_h[i] = rand()/(float)RAND_MAX;
C_h[i] = 0;
}
cudaMalloc(&A_d, DATA_SIZE*sizeof(float)); //allocate memory for device vectors
cudaMalloc(&B_d, DATA_SIZE*sizeof(float));
cudaMalloc(&C_d, DATA_SIZE*sizeof(float));
cudaCheck("Error in cudaMallocs"); //check if any errors during memory allocation on device
// copy host vectors to device
cudaMemcpy(A_d, A_h, DATA_SIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, DATA_SIZE*sizeof(float), cudaMemcpyHostToDevice);
cudaCheck("host to device copy error");
int blocks = 4; // to set number of blocks
int threads = 256; // to set number of threads per block
// set memory stride size
//*************************************************************************************///
//*********** uncomment the below kernel for studying launch configurations ***********///
//*************************************************************************************///
vector_add_kernel<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE);
//*************************************************************************************///
//*********** uncomment the below two lines to study memory caching and coalescing ***********///
//*************************************************************************************///
// int mem_stride = 8;
// vector_add_kernel_memory<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE, mem_stride);
cudaCheck("kernel launch error");
// copy result vector from device to host
cudaMemcpy(C_h, C_d, DATA_SIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaCheck("device to host copy error or kernel launch failure");
result_check(A_h, B_h, C_h);
return 0;
} // end main
void result_check(float *A, float *B, float *C){
int errors = 0;
for(int i = 0; i < DATA_SIZE; i++){
if(A[i] + B[i] != C[i]){
errors++;
}
}
if(errors == 0){
std::cout<<"\tCorrectness Test Passed\n";
}else{
std::cout<<"\tCorrectness Test Failed\n";
}
}
// kernel for launch configurations
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
for(int i = idx; i < size; i+=total_threads)
C[i] = A[i] + B[i];
}
// kernel for stuyding effect of caching
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
int strides_per_thread = size/(total_threads*stride_size);
for(int j = 0; j < strides_per_thread; j++){
int stride_begin = stride_size * idx + j * stride_size * total_threads;
int stride_end = stride_size + stride_begin;
for(int i = stride_begin; i < stride_end; i++ ){
C[i] = A[i] + B[i];
}
}
} | #include <hip/hip_runtime.h>
#include <iostream>
//some of the materials here was reused or based on NERSC/OLCF cuda training-series (https://github.com/olcf/cuda-training-series)
#define cudaCheck(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
#define DATA_SIZE 1024*1024*32
void result_check(float *A, float *B, float *C);
// kernel
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size);
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size);
int main(){
float *A_h, *B_h, *C_h; // host pointers
float *A_d, *B_d, *C_d;// device pointers
A_h = new float[DATA_SIZE]; // allocating host arrays
B_h = new float[DATA_SIZE];
C_h = new float[DATA_SIZE];
for (int i = 0; i < DATA_SIZE; i++){ // initializing host vectors
A_h[i] = rand()/(float)RAND_MAX;
B_h[i] = rand()/(float)RAND_MAX;
C_h[i] = 0;
}
hipMalloc(&A_d, DATA_SIZE*sizeof(float)); //allocate memory for device vectors
hipMalloc(&B_d, DATA_SIZE*sizeof(float));
hipMalloc(&C_d, DATA_SIZE*sizeof(float));
cudaCheck("Error in cudaMallocs"); //check if any errors during memory allocation on device
// copy host vectors to device
hipMemcpy(A_d, A_h, DATA_SIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, DATA_SIZE*sizeof(float), hipMemcpyHostToDevice);
cudaCheck("host to device copy error");
int blocks = 4; // to set number of blocks
int threads = 256; // to set number of threads per block
// set memory stride size
//*************************************************************************************///
//*********** uncomment the below kernel for studying launch configurations ***********///
//*************************************************************************************///
vector_add_kernel<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE);
//*************************************************************************************///
//*********** uncomment the below two lines to study memory caching and coalescing ***********///
//*************************************************************************************///
// int mem_stride = 8;
// vector_add_kernel_memory<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE, mem_stride);
cudaCheck("kernel launch error");
// copy result vector from device to host
hipMemcpy(C_h, C_d, DATA_SIZE*sizeof(float), hipMemcpyDeviceToHost);
cudaCheck("device to host copy error or kernel launch failure");
result_check(A_h, B_h, C_h);
return 0;
} // end main
void result_check(float *A, float *B, float *C){
int errors = 0;
for(int i = 0; i < DATA_SIZE; i++){
if(A[i] + B[i] != C[i]){
errors++;
}
}
if(errors == 0){
std::cout<<"\tCorrectness Test Passed\n";
}else{
std::cout<<"\tCorrectness Test Failed\n";
}
}
// kernel for launch configurations
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
for(int i = idx; i < size; i+=total_threads)
C[i] = A[i] + B[i];
}
// kernel for stuyding effect of caching
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
int strides_per_thread = size/(total_threads*stride_size);
for(int j = 0; j < strides_per_thread; j++){
int stride_begin = stride_size * idx + j * stride_size * total_threads;
int stride_end = stride_size + stride_begin;
for(int i = stride_begin; i < stride_end; i++ ){
C[i] = A[i] + B[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
//some of the materials here was reused or based on NERSC/OLCF cuda training-series (https://github.com/olcf/cuda-training-series)
#define cudaCheck(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
#define DATA_SIZE 1024*1024*32
void result_check(float *A, float *B, float *C);
// kernel
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size);
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size);
int main(){
float *A_h, *B_h, *C_h; // host pointers
float *A_d, *B_d, *C_d;// device pointers
A_h = new float[DATA_SIZE]; // allocating host arrays
B_h = new float[DATA_SIZE];
C_h = new float[DATA_SIZE];
for (int i = 0; i < DATA_SIZE; i++){ // initializing host vectors
A_h[i] = rand()/(float)RAND_MAX;
B_h[i] = rand()/(float)RAND_MAX;
C_h[i] = 0;
}
hipMalloc(&A_d, DATA_SIZE*sizeof(float)); //allocate memory for device vectors
hipMalloc(&B_d, DATA_SIZE*sizeof(float));
hipMalloc(&C_d, DATA_SIZE*sizeof(float));
cudaCheck("Error in cudaMallocs"); //check if any errors during memory allocation on device
// copy host vectors to device
hipMemcpy(A_d, A_h, DATA_SIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, DATA_SIZE*sizeof(float), hipMemcpyHostToDevice);
cudaCheck("host to device copy error");
int blocks = 4; // to set number of blocks
int threads = 256; // to set number of threads per block
// set memory stride size
//*************************************************************************************///
//*********** uncomment the below kernel for studying launch configurations ***********///
//*************************************************************************************///
vector_add_kernel<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE);
//*************************************************************************************///
//*********** uncomment the below two lines to study memory caching and coalescing ***********///
//*************************************************************************************///
// int mem_stride = 8;
// vector_add_kernel_memory<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE, mem_stride);
cudaCheck("kernel launch error");
// copy result vector from device to host
hipMemcpy(C_h, C_d, DATA_SIZE*sizeof(float), hipMemcpyDeviceToHost);
cudaCheck("device to host copy error or kernel launch failure");
result_check(A_h, B_h, C_h);
return 0;
} // end main
void result_check(float *A, float *B, float *C){
int errors = 0;
for(int i = 0; i < DATA_SIZE; i++){
if(A[i] + B[i] != C[i]){
errors++;
}
}
if(errors == 0){
std::cout<<"\tCorrectness Test Passed\n";
}else{
std::cout<<"\tCorrectness Test Failed\n";
}
}
// kernel for launch configurations
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
for(int i = idx; i < size; i+=total_threads)
C[i] = A[i] + B[i];
}
// kernel for stuyding effect of caching
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
int strides_per_thread = size/(total_threads*stride_size);
for(int j = 0; j < strides_per_thread; j++){
int stride_begin = stride_size * idx + j * stride_size * total_threads;
int stride_end = stride_size + stride_begin;
for(int i = stride_begin; i < stride_end; i++ ){
C[i] = A[i] + B[i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17vector_add_kernelPKfS0_Pfi
.globl _Z17vector_add_kernelPKfS0_Pfi
.p2align 8
.type _Z17vector_add_kernelPKfS0_Pfi,@function
_Z17vector_add_kernelPKfS0_Pfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17vector_add_kernelPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17vector_add_kernelPKfS0_Pfi, .Lfunc_end0-_Z17vector_add_kernelPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24vector_add_kernel_memoryPKfS0_Pfii
.globl _Z24vector_add_kernel_memoryPKfS0_Pfii
.p2align 8
.type _Z24vector_add_kernel_memoryPKfS0_Pfii,@function
_Z24vector_add_kernel_memoryPKfS0_Pfii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s10, s10, s13
s_ashr_i32 s8, s2, 31
s_mul_i32 s11, s10, s3
s_add_i32 s2, s2, s8
s_ashr_i32 s4, s11, 31
s_xor_b32 s2, s2, s8
s_add_i32 s5, s11, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s5, s5, s4
s_xor_b32 s4, s8, s4
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s7, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s7, s6
s_mul_hi_u32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_mul_hi_u32 s6, s2, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s6, s5
s_sub_i32 s2, s2, s7
s_add_i32 s7, s6, 1
s_sub_i32 s8, s2, s5
s_cmp_ge_u32 s2, s5
s_cselect_b32 s6, s7, s6
s_cselect_b32 s2, s8, s2
s_add_i32 s7, s6, 1
s_cmp_ge_u32 s2, s5
s_cselect_b32 s2, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s4
s_sub_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_cmp_gt_i32 s3, 0
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, s3, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s11, v2
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s12, s2
s_cbranch_scc1 .LBB1_7
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB1_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mad_u64_u32 v[4:5], null, s12, s10, v[1:2]
s_mov_b32 s13, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v4, s3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
v_add_nc_u32_e32 v9, s3, v0
.p2align 6
.LBB1_5:
global_load_b32 v10, v[3:4], off
global_load_b32 v11, v[5:6], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_nc_u32_e32 v0, 1, v0
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_ge_i32_e32 vcc_lo, v0, v9
s_or_b32 s13, vcc_lo, s13
s_waitcnt vmcnt(0)
v_add_f32_e32 v10, v10, v11
global_store_b32 v[7:8], v10, off
v_add_co_u32 v7, s0, v7, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_5
s_or_b32 exec_lo, exec_lo, s13
s_branch .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24vector_add_kernel_memoryPKfS0_Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z24vector_add_kernel_memoryPKfS0_Pfii, .Lfunc_end1-_Z24vector_add_kernel_memoryPKfS0_Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17vector_add_kernelPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17vector_add_kernelPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24vector_add_kernel_memoryPKfS0_Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24vector_add_kernel_memoryPKfS0_Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
//some of the materials here was reused or based on NERSC/OLCF cuda training-series (https://github.com/olcf/cuda-training-series)
#define cudaCheck(msg) \
do { \
hipError_t __err = hipGetLastError(); \
if (__err != hipSuccess) { \
fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
msg, hipGetErrorString(__err), \
__FILE__, __LINE__); \
fprintf(stderr, "*** FAILED - ABORTING\n"); \
exit(1); \
} \
} while (0)
#define DATA_SIZE 1024*1024*32
void result_check(float *A, float *B, float *C);
// kernel
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size);
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size);
int main(){
float *A_h, *B_h, *C_h; // host pointers
float *A_d, *B_d, *C_d;// device pointers
A_h = new float[DATA_SIZE]; // allocating host arrays
B_h = new float[DATA_SIZE];
C_h = new float[DATA_SIZE];
for (int i = 0; i < DATA_SIZE; i++){ // initializing host vectors
A_h[i] = rand()/(float)RAND_MAX;
B_h[i] = rand()/(float)RAND_MAX;
C_h[i] = 0;
}
hipMalloc(&A_d, DATA_SIZE*sizeof(float)); //allocate memory for device vectors
hipMalloc(&B_d, DATA_SIZE*sizeof(float));
hipMalloc(&C_d, DATA_SIZE*sizeof(float));
cudaCheck("Error in cudaMallocs"); //check if any errors during memory allocation on device
// copy host vectors to device
hipMemcpy(A_d, A_h, DATA_SIZE*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, DATA_SIZE*sizeof(float), hipMemcpyHostToDevice);
cudaCheck("host to device copy error");
int blocks = 4; // to set number of blocks
int threads = 256; // to set number of threads per block
// set memory stride size
//*************************************************************************************///
//*********** uncomment the below kernel for studying launch configurations ***********///
//*************************************************************************************///
vector_add_kernel<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE);
//*************************************************************************************///
//*********** uncomment the below two lines to study memory caching and coalescing ***********///
//*************************************************************************************///
// int mem_stride = 8;
// vector_add_kernel_memory<<<blocks, threads>>>(A_d, B_d, C_d, DATA_SIZE, mem_stride);
cudaCheck("kernel launch error");
// copy result vector from device to host
hipMemcpy(C_h, C_d, DATA_SIZE*sizeof(float), hipMemcpyDeviceToHost);
cudaCheck("device to host copy error or kernel launch failure");
result_check(A_h, B_h, C_h);
return 0;
} // end main
void result_check(float *A, float *B, float *C){
int errors = 0;
for(int i = 0; i < DATA_SIZE; i++){
if(A[i] + B[i] != C[i]){
errors++;
}
}
if(errors == 0){
std::cout<<"\tCorrectness Test Passed\n";
}else{
std::cout<<"\tCorrectness Test Failed\n";
}
}
// kernel for launch configurations
__global__
void vector_add_kernel(const float *A, const float *B, float *C, int size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
for(int i = idx; i < size; i+=total_threads)
C[i] = A[i] + B[i];
}
// kernel for stuyding effect of caching
__global__
void vector_add_kernel_memory(const float *A, const float *B, float *C, int size, int stride_size){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int total_threads = gridDim.x*blockDim.x;
int strides_per_thread = size/(total_threads*stride_size);
for(int j = 0; j < strides_per_thread; j++){
int stride_begin = stride_size * idx + j * stride_size * total_threads;
int stride_end = stride_size + stride_begin;
for(int i = stride_begin; i < stride_end; i++ ){
C[i] = A[i] + B[i];
}
}
} | .text
.file "vec_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %rbx
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r14
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $33554432, %r12 # imm = 0x2000000
jne .LBB0_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_3
# %bb.5:
movq 32(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB0_6
# %bb.7:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $33554432, 12(%rsp) # imm = 0x2000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17vector_add_kernelPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB0_10
# %bb.11:
movq 16(%rsp), %rsi
movl $134217728, %edx # imm = 0x8000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB0_15
# %bb.12: # %.preheader.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_13: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
cmpneqss (%r15,%rax,4), %xmm0
movd %xmm0, %edx
subl %edx, %ecx
incq %rax
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB0_13
# %bb.14: # %_Z12result_checkPfS_S_.exit
testl %ecx, %ecx
movl $.L.str.7, %eax
movl $.L.str.8, %esi
cmoveq %rax, %rsi
movl $_ZSt4cout, %edi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $47, %r9d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $51, %r9d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.5, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $69, %r9d
jmp .LBB0_4
.LBB0_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $72, %r9d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z32__device_stub__vector_add_kernelPKfS0_Pfi # -- Begin function _Z32__device_stub__vector_add_kernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z32__device_stub__vector_add_kernelPKfS0_Pfi,@function
_Z32__device_stub__vector_add_kernelPKfS0_Pfi: # @_Z32__device_stub__vector_add_kernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17vector_add_kernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__vector_add_kernelPKfS0_Pfi, .Lfunc_end1-_Z32__device_stub__vector_add_kernelPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z12result_checkPfS_S_ # -- Begin function _Z12result_checkPfS_S_
.p2align 4, 0x90
.type _Z12result_checkPfS_S_,@function
_Z12result_checkPfS_S_: # @_Z12result_checkPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
cmpneqss (%rdx,%rax,4), %xmm0
movd %xmm0, %r8d
subl %r8d, %ecx
incq %rax
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB2_1
# %bb.2:
testl %ecx, %ecx
movl $.L.str.7, %eax
movl $.L.str.8, %esi
cmoveq %rax, %rsi
movl $_ZSt4cout, %edi
movl $25, %edx
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end2:
.size _Z12result_checkPfS_S_, .Lfunc_end2-_Z12result_checkPfS_S_
.cfi_endproc
# -- End function
.globl _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii # -- Begin function _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.p2align 4, 0x90
.type _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii,@function
_Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii: # @_Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24vector_add_kernel_memoryPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii, .Lfunc_end3-_Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17vector_add_kernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24vector_add_kernel_memoryPKfS0_Pfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error in cudaMallocs"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mgawan/nersc_cuda_tutorial/master/Session-2/vec_add.hip"
.size .L.str.2, 113
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "host to device copy error"
.size .L.str.4, 26
.type _Z17vector_add_kernelPKfS0_Pfi,@object # @_Z17vector_add_kernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z17vector_add_kernelPKfS0_Pfi
.p2align 3, 0x0
_Z17vector_add_kernelPKfS0_Pfi:
.quad _Z32__device_stub__vector_add_kernelPKfS0_Pfi
.size _Z17vector_add_kernelPKfS0_Pfi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "kernel launch error"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "device to host copy error or kernel launch failure"
.size .L.str.6, 51
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tCorrectness Test Passed\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tCorrectness Test Failed\n"
.size .L.str.8, 26
.type _Z24vector_add_kernel_memoryPKfS0_Pfii,@object # @_Z24vector_add_kernel_memoryPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z24vector_add_kernel_memoryPKfS0_Pfii
.p2align 3, 0x0
_Z24vector_add_kernel_memoryPKfS0_Pfii:
.quad _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.size _Z24vector_add_kernel_memoryPKfS0_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17vector_add_kernelPKfS0_Pfi"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24vector_add_kernel_memoryPKfS0_Pfii"
.size .L__unnamed_2, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__vector_add_kernelPKfS0_Pfi
.addrsig_sym _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17vector_add_kernelPKfS0_Pfi
.addrsig_sym _ZSt4cout
.addrsig_sym _Z24vector_add_kernel_memoryPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a8055_00000000-6_vec_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\tCorrectness Test Passed\n"
.LC1:
.string "\tCorrectness Test Failed\n"
.text
.globl _Z12result_checkPfS_S_
.type _Z12result_checkPfS_S_, @function
_Z12result_checkPfS_S_:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %eax
movl $0, %ecx
jmp .L6
.L9:
addl $1, %ecx
.L4:
addq $4, %rax
cmpq $134217728, %rax
je .L12
.L6:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L9
je .L4
jmp .L9
.L12:
testl %ecx, %ecx
jne .L7
movl $25, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl $25, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L3
.cfi_endproc
.LFE3670:
.size _Z12result_checkPfS_S_, .-_Z12result_checkPfS_S_
.globl _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
.type _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi, @function
_Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17vector_add_kernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi, .-_Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
.globl _Z17vector_add_kernelPKfS0_Pfi
.type _Z17vector_add_kernelPKfS0_Pfi, @function
_Z17vector_add_kernelPKfS0_Pfi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z17vector_add_kernelPKfS0_Pfi, .-_Z17vector_add_kernelPKfS0_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mgawan/nersc_cuda_tutorial/master/Session-2/vec_add.cu"
.section .rodata.str1.1
.LC5:
.string "Error in cudaMallocs"
.section .rodata.str1.8
.align 8
.LC6:
.string "Fatal error: %s (%s at %s:%d)\n"
.section .rodata.str1.1
.LC7:
.string "*** FAILED - ABORTING\n"
.LC8:
.string "host to device copy error"
.LC9:
.string "kernel launch error"
.section .rodata.str1.8
.align 8
.LC10:
.string "device to host copy error or kernel launch failure"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $134217728, %edi
call _Znam@PLT
movq %rax, %rbp
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r12
movl $134217728, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %ebx
.L22:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
movl $0x00000000, 0(%r13,%rbx)
addq $4, %rbx
cmpq $134217728, %rbx
jne .L22
leaq 8(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $134217728, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
movl $1, %ecx
movl $134217728, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $134217728, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L34
movl $2, %ecx
movl $134217728, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z12result_checkPfS_S_
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $45
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $49
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC8(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl $33554432, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z17vector_add_kernelPKfS0_PfiPKfS0_Pfi
jmp .L25
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $67
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC9(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq $70
.cfi_def_cfa_offset 128
leaq .LC4(%rip), %r9
leaq .LC10(%rip), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii
.type _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii, @function
_Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24vector_add_kernel_memoryPKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii, .-_Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii
.globl _Z24vector_add_kernel_memoryPKfS0_Pfii
.type _Z24vector_add_kernel_memoryPKfS0_Pfii, @function
_Z24vector_add_kernel_memoryPKfS0_Pfii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z24vector_add_kernel_memoryPKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z24vector_add_kernel_memoryPKfS0_Pfii, .-_Z24vector_add_kernel_memoryPKfS0_Pfii
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z24vector_add_kernel_memoryPKfS0_Pfii"
.align 8
.LC12:
.string "_Z17vector_add_kernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z24vector_add_kernel_memoryPKfS0_Pfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z17vector_add_kernelPKfS0_Pfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %rbx
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r14
movl $134217728, %edi # imm = 0x8000000
callq _Znam
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $33554432, %r12 # imm = 0x2000000
jne .LBB0_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $134217728, %esi # imm = 0x8000000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB0_3
# %bb.5:
movq 32(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $134217728, %edx # imm = 0x8000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB0_6
# %bb.7:
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_9
# %bb.8:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $33554432, 12(%rsp) # imm = 0x2000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17vector_add_kernelPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB0_10
# %bb.11:
movq 16(%rsp), %rsi
movl $134217728, %edx # imm = 0x8000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB0_15
# %bb.12: # %.preheader.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_13: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
cmpneqss (%r15,%rax,4), %xmm0
movd %xmm0, %edx
subl %edx, %ecx
incq %rax
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB0_13
# %bb.14: # %_Z12result_checkPfS_S_.exit
testl %ecx, %ecx
movl $.L.str.7, %eax
movl $.L.str.8, %esi
cmoveq %rax, %rsi
movl $_ZSt4cout, %edi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $47, %r9d
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $51, %r9d
jmp .LBB0_4
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.5, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $69, %r9d
jmp .LBB0_4
.LBB0_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rcx
movl $72, %r9d
.LBB0_4:
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z32__device_stub__vector_add_kernelPKfS0_Pfi # -- Begin function _Z32__device_stub__vector_add_kernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z32__device_stub__vector_add_kernelPKfS0_Pfi,@function
_Z32__device_stub__vector_add_kernelPKfS0_Pfi: # @_Z32__device_stub__vector_add_kernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17vector_add_kernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z32__device_stub__vector_add_kernelPKfS0_Pfi, .Lfunc_end1-_Z32__device_stub__vector_add_kernelPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z12result_checkPfS_S_ # -- Begin function _Z12result_checkPfS_S_
.p2align 4, 0x90
.type _Z12result_checkPfS_S_,@function
_Z12result_checkPfS_S_: # @_Z12result_checkPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
cmpneqss (%rdx,%rax,4), %xmm0
movd %xmm0, %r8d
subl %r8d, %ecx
incq %rax
cmpq $33554432, %rax # imm = 0x2000000
jne .LBB2_1
# %bb.2:
testl %ecx, %ecx
movl $.L.str.7, %eax
movl $.L.str.8, %esi
cmoveq %rax, %rsi
movl $_ZSt4cout, %edi
movl $25, %edx
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end2:
.size _Z12result_checkPfS_S_, .Lfunc_end2-_Z12result_checkPfS_S_
.cfi_endproc
# -- End function
.globl _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii # -- Begin function _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.p2align 4, 0x90
.type _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii,@function
_Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii: # @_Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24vector_add_kernel_memoryPKfS0_Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii, .Lfunc_end3-_Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17vector_add_kernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24vector_add_kernel_memoryPKfS0_Pfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fatal error: %s (%s at %s:%d)\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error in cudaMallocs"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mgawan/nersc_cuda_tutorial/master/Session-2/vec_add.hip"
.size .L.str.2, 113
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "*** FAILED - ABORTING\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "host to device copy error"
.size .L.str.4, 26
.type _Z17vector_add_kernelPKfS0_Pfi,@object # @_Z17vector_add_kernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z17vector_add_kernelPKfS0_Pfi
.p2align 3, 0x0
_Z17vector_add_kernelPKfS0_Pfi:
.quad _Z32__device_stub__vector_add_kernelPKfS0_Pfi
.size _Z17vector_add_kernelPKfS0_Pfi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "kernel launch error"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "device to host copy error or kernel launch failure"
.size .L.str.6, 51
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tCorrectness Test Passed\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tCorrectness Test Failed\n"
.size .L.str.8, 26
.type _Z24vector_add_kernel_memoryPKfS0_Pfii,@object # @_Z24vector_add_kernel_memoryPKfS0_Pfii
.section .rodata,"a",@progbits
.globl _Z24vector_add_kernel_memoryPKfS0_Pfii
.p2align 3, 0x0
_Z24vector_add_kernel_memoryPKfS0_Pfii:
.quad _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.size _Z24vector_add_kernel_memoryPKfS0_Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17vector_add_kernelPKfS0_Pfi"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24vector_add_kernel_memoryPKfS0_Pfii"
.size .L__unnamed_2, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__vector_add_kernelPKfS0_Pfi
.addrsig_sym _Z39__device_stub__vector_add_kernel_memoryPKfS0_Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17vector_add_kernelPKfS0_Pfi
.addrsig_sym _ZSt4cout
.addrsig_sym _Z24vector_add_kernel_memoryPKfS0_Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include <cuda.h>
inline __device__ void f() __attribute__((always_inline));
inline __device__ void f() {
}
inline __device__ void g() __attribute__((always_inline));
inline __device__ void g() {
f();
}
__global__ void k() {
g();
} | code for sm_80
Function : _Z1kv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include <cuda.h>
inline __device__ void f() __attribute__((always_inline));
inline __device__ void f() {
}
inline __device__ void g() __attribute__((always_inline));
inline __device__ void g() {
f();
}
__global__ void k() {
g();
} | .file "tmpxft_0018f91c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1kvv
.type _Z19__device_stub__Z1kvv, @function
_Z19__device_stub__Z1kvv:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1kv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z19__device_stub__Z1kvv, .-_Z19__device_stub__Z1kvv
.globl _Z1kv
.type _Z1kv, @function
_Z1kv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1kvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z1kv, .-_Z1kv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1kv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1kv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include <cuda.h>
inline __device__ void f() __attribute__((always_inline));
inline __device__ void f() {
}
inline __device__ void g() __attribute__((always_inline));
inline __device__ void g() {
f();
}
__global__ void k() {
g();
} | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include <hip/hip_runtime.h>
inline __device__ void f() __attribute__((always_inline));
inline __device__ void f() {
}
inline __device__ void g() __attribute__((always_inline));
inline __device__ void g() {
f();
}
__global__ void k() {
g();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include <hip/hip_runtime.h>
inline __device__ void f() __attribute__((always_inline));
inline __device__ void f() {
}
inline __device__ void g() __attribute__((always_inline));
inline __device__ void g() {
f();
}
__global__ void k() {
g();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1kv
.globl _Z1kv
.p2align 8
.type _Z1kv,@function
_Z1kv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1kv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1kv, .Lfunc_end0-_Z1kv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1kv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z1kv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include <hip/hip_runtime.h>
inline __device__ void f() __attribute__((always_inline));
inline __device__ void f() {
}
inline __device__ void g() __attribute__((always_inline));
inline __device__ void g() {
f();
}
__global__ void k() {
g();
} | .text
.file "main.hip"
.globl _Z16__device_stub__kv # -- Begin function _Z16__device_stub__kv
.p2align 4, 0x90
.type _Z16__device_stub__kv,@function
_Z16__device_stub__kv: # @_Z16__device_stub__kv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__kv, .Lfunc_end0-_Z16__device_stub__kv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1kv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1kv,@object # @_Z1kv
.section .rodata,"a",@progbits
.globl _Z1kv
.p2align 3, 0x0
_Z1kv:
.quad _Z16__device_stub__kv
.size _Z1kv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1kv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__kv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1kv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1kv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1kv
.globl _Z1kv
.p2align 8
.type _Z1kv,@function
_Z1kv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1kv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1kv, .Lfunc_end0-_Z1kv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1kv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z1kv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f91c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19__device_stub__Z1kvv
.type _Z19__device_stub__Z1kvv, @function
_Z19__device_stub__Z1kvv:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1kv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z19__device_stub__Z1kvv, .-_Z19__device_stub__Z1kvv
.globl _Z1kv
.type _Z1kv, @function
_Z1kv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1kvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z1kv, .-_Z1kv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1kv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1kv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z16__device_stub__kv # -- Begin function _Z16__device_stub__kv
.p2align 4, 0x90
.type _Z16__device_stub__kv,@function
_Z16__device_stub__kv: # @_Z16__device_stub__kv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__kv, .Lfunc_end0-_Z16__device_stub__kv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1kv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1kv,@object # @_Z1kv
.section .rodata,"a",@progbits
.globl _Z1kv
.p2align 3, 0x0
_Z1kv:
.quad _Z16__device_stub__kv
.size _Z1kv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1kv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__kv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1kv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void linearLayerBackprop(float* W, float* dZ, float *dA, int W_x_dim, int W_y_dim, int dZ_x_dim, int dZ_y_dim) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
// W is treated as transposed
int dA_x_dim = dZ_x_dim;
int dA_y_dim = W_x_dim;
float dA_value = 0.0f;
if (row < dA_y_dim && col < dA_x_dim) {
for (int i = 0; i < W_y_dim; i++) {
dA_value += W[i * W_x_dim + row] * dZ[i * dZ_x_dim + col];
}
dA[row * dA_x_dim + col] = dA_value;
}
} | code for sm_80
Function : _Z19linearLayerBackpropPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xcb0 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xbc0 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0170*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0180*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f04270 */
/*01a0*/ IMAD.WIDE R14, R0, R6, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x000fc800078e0206 */
/*01b0*/ IMAD.WIDE R16, R3, R6, c[0x0][0x160] ; /* 0x0000580003107625 */
/* 0x000fe400078e0206 */
/*01c0*/ @!P0 BRA 0xa40 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x750 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0230*/ IMAD.WIDE R22, R6, c[0x0][0x180], R14 ; /* 0x0000600006167a25 */
/* 0x000fc800078e020e */
/*0240*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e00061a7a25 */
/* 0x040fe200078e0210 */
/*0250*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000728000c1e1900 */
/*0260*/ LDG.E R24, [R26.64] ; /* 0x000000041a187981 */
/* 0x000b22000c1e1900 */
/*0270*/ IMAD.WIDE R22, R6, c[0x0][0x180], R22 ; /* 0x0000600006167a25 */
/* 0x008fc800078e0216 */
/*0280*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x178], R26 ; /* 0x00005e00061a7a25 */
/* 0x060fe200078e021a */
/*0290*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000766000c1e1900 */
/*02a0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x180], R22 ; /* 0x00006000060e7a25 */
/* 0x041fe200078e0216 */
/*02b0*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000166000c1e1900 */
/*02c0*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R26 ; /* 0x00005e00060c7a25 */
/* 0x040fe200078e021a */
/*02d0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x002368000c1e1900 */
/*02e0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD.WIDE R28, R6, c[0x0][0x178], R12 ; /* 0x00005e00061c7a25 */
/* 0x000fc800078e020c */
/*0300*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x180], R14 ; /* 0x00006000060e7a25 */
/* 0x042fe200078e020e */
/*0310*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x008762000c1e1900 */
/*0330*/ IMAD.WIDE R26, R6, c[0x0][0x180], R14 ; /* 0x00006000061a7a25 */
/* 0x001fc800078e020e */
/*0340*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x178], R28 ; /* 0x00005e00061c7a25 */
/* 0x042fe200078e021c */
/*0350*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x00016a000c1e1900 */
/*0360*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R28 ; /* 0x00005e00060c7a25 */
/* 0x040fe400078e021c */
/*0370*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000564000c1e1900 */
/*0380*/ IMAD.WIDE R26, R6, c[0x0][0x180], R26 ; /* 0x00006000061a7a25 */
/* 0x001fc400078e021a */
/*0390*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000362000c1e1900 */
/*03b0*/ IMAD.WIDE R14, R6, c[0x0][0x180], R26 ; /* 0x00006000060e7a25 */
/* 0x008fc800078e021a */
/*03c0*/ IMAD.WIDE R12, R6, c[0x0][0x178], R12 ; /* 0x00005e00060c7a25 */
/* 0x001fc800078e020c */
/*03d0*/ FFMA R29, R20, R9, R10 ; /* 0x00000009141d7223 */
/* 0x004fe4000000000a */
/*03e0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a8000c1e1900 */
/*03f0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0006a2000c1e1900 */
/*0400*/ IMAD.WIDE R20, R6, c[0x0][0x178], R12 ; /* 0x00005e0006147a25 */
/* 0x000fc800078e020c */
/*0410*/ FFMA R29, R11, R24, R29 ; /* 0x000000180b1d7223 */
/* 0x010fe4000000001d */
/*0420*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0008a2000c1e1900 */
/*0430*/ IMAD.WIDE R14, R6, c[0x0][0x180], R14 ; /* 0x00006000060e7a25 */
/* 0x008fca00078e020e */
/*0440*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0006a2000c1e1900 */
/*0450*/ IMAD.WIDE R26, R6, c[0x0][0x178], R20 ; /* 0x00005e00061a7a25 */
/* 0x002fc800078e0214 */
/*0460*/ FFMA R29, R19, R18, R29 ; /* 0x00000012131d7223 */
/* 0x020fe4000000001d */
/*0470*/ IMAD.WIDE R18, R6, c[0x0][0x180], R14 ; /* 0x0000600006127a25 */
/* 0x000fc800078e020e */
/*0480*/ FFMA R16, R16, R25, R29 ; /* 0x0000001910107223 */
/* 0x000fe4000000001d */
/*0490*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*04a0*/ IMAD.WIDE R12, R6, c[0x0][0x178], R26 ; /* 0x00005e00060c7a25 */
/* 0x001fc600078e021a */
/*04b0*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000162000c1e1900 */
/*04c0*/ IMAD.WIDE R18, R6, c[0x0][0x180], R18 ; /* 0x0000600006127a25 */
/* 0x002fc800078e0212 */
/*04d0*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fe20000000010 */
/*04e0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x001162000c1e1900 */
/*04f0*/ IMAD.WIDE R14, R6, c[0x0][0x178], R12 ; /* 0x00005e00060e7a25 */
/* 0x008fc600078e020c */
/*0500*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0004e2000c1e1900 */
/*0510*/ IMAD.WIDE R16, R6, c[0x0][0x180], R18 ; /* 0x0000600006107a25 */
/* 0x000fc600078e0212 */
/*0520*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x0002e2000c1e1900 */
/*0530*/ FFMA R28, R23, R28, R22 ; /* 0x0000001c171c7223 */
/* 0x000fe40000000016 */
/*0540*/ IMAD.WIDE R20, R6, c[0x0][0x178], R14 ; /* 0x00005e0006147a25 */
/* 0x010fc800078e020e */
/*0550*/ IMAD.WIDE R22, R6, c[0x0][0x180], R16 ; /* 0x0000600006167a25 */
/* 0x000fe400078e0210 */
/*0560*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0570*/ FFMA R8, R8, R7, R28 ; /* 0x0000000708087223 */
/* 0x000fe4000000001c */
/*0580*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R20 ; /* 0x00005e00060e7a25 */
/* 0x042fe200078e0214 */
/*0590*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x0002e6000c1e1900 */
/*05a0*/ IMAD.WIDE R18, R6, c[0x0][0x180], R22 ; /* 0x0000600006127a25 */
/* 0x001fe200078e0216 */
/*05b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee6000c1e1900 */
/*05c0*/ FFMA R13, R10, R9, R8 ; /* 0x000000090a0d7223 */
/* 0x004fc40000000008 */
/*05d0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*05e0*/ IMAD.WIDE R8, R6, c[0x0][0x178], R14 ; /* 0x00005e0006087a25 */
/* 0x000fc600078e020e */
/*05f0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0108a2000c1e1900 */
/*0610*/ IMAD.WIDE R18, R6, c[0x0][0x180], R18 ; /* 0x0000600006127a25 */
/* 0x001fca00078e0212 */
/*0620*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.WIDE R22, R6, c[0x0][0x180], R18 ; /* 0x0000600006167a25 */
/* 0x002fc800078e0212 */
/*0640*/ IMAD.WIDE R8, R6, c[0x0][0x178], R8 ; /* 0x00005e0006087a25 */
/* 0x010fc800078e0208 */
/*0650*/ FFMA R13, R11, R24, R13 ; /* 0x000000180b0d7223 */
/* 0x000fe4000000000d */
/*0660*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f28000c1e1900 */
/*0670*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000f22000c1e1900 */
/*0680*/ FFMA R13, R25, R26, R13 ; /* 0x0000001a190d7223 */
/* 0x020fe2000000000d */
/*0690*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*06a0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*06b0*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x008fc8000000000d */
/*06c0*/ FFMA R12, R16, R29, R12 ; /* 0x0000001d100c7223 */
/* 0x000fc8000000000c */
/*06d0*/ FFMA R7, R7, R20, R12 ; /* 0x0000001407077223 */
/* 0x000fe2000000000c */
/*06e0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ FFMA R7, R10, R15, R7 ; /* 0x0000000f0a077223 */
/* 0x004fe40000000007 */
/*0700*/ IMAD.WIDE R14, R6, c[0x0][0x180], R22 ; /* 0x00006000060e7a25 */
/* 0x000fc800078e0216 */
/*0710*/ FFMA R7, R28, R17, R7 ; /* 0x000000111c077223 */
/* 0x000fe40000000007 */
/*0720*/ IMAD.WIDE R16, R6, c[0x0][0x178], R8 ; /* 0x00005e0006107a25 */
/* 0x000fc800078e0208 */
/*0730*/ FFMA R10, R11, R24, R7 ; /* 0x000000180b0a7223 */
/* 0x010fe20000000007 */
/*0740*/ @P1 BRA 0x210 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0750*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0xa20 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0000a8000c1e1900 */
/*0780*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*0790*/ IMAD.WIDE R8, R6, c[0x0][0x178], R16 ; /* 0x00005e0006087a25 */
/* 0x000fc800078e0210 */
/*07a0*/ IMAD.WIDE R12, R6, c[0x0][0x180], R14 ; /* 0x00006000060c7a25 */
/* 0x000fc800078e020e */
/*07b0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R8 ; /* 0x00005e00060e7a25 */
/* 0x041fe200078e0208 */
/*07c0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0000e6000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x180], R12 ; /* 0x0000600006127a25 */
/* 0x040fe200078e020c */
/*07e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0008e6000c1e1900 */
/*07f0*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x178], R14 ; /* 0x00005e0006107a25 */
/* 0x042fe200078e020e */
/*0800*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000366000c1e1900 */
/*0810*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x180], R18 ; /* 0x0000600006147a25 */
/* 0x040fe200078e0212 */
/*0820*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000366000c1e1900 */
/*0830*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e00060c7a25 */
/* 0x041fe200078e0210 */
/*0840*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000166000c1e1900 */
/*0850*/ IMAD.WIDE R22, R6, c[0x0][0x180], R20 ; /* 0x0000600006167a25 */
/* 0x000fc400078e0214 */
/*0860*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000964000c1e1900 */
/*0870*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R12 ; /* 0x00005e00060e7a25 */
/* 0x042fe400078e020c */
/*0880*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000364000c1e1900 */
/*0890*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x180], R22 ; /* 0x0000600006107a25 */
/* 0x041fe400078e0216 */
/*08a0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x010128000c1e1900 */
/*08b0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x180], R16 ; /* 0x0000600006127a25 */
/* 0x040fe200078e0210 */
/*08c0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000326000c1e1900 */
/*08d0*/ IMAD.WIDE R12, R6, c[0x0][0x178], R14 ; /* 0x00005e00060c7a25 */
/* 0x001fc400078e020e */
/*08e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*08f0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x002122000c1e1900 */
/*0900*/ IMAD.WIDE R22, R6, c[0x0][0x178], R12 ; /* 0x00005e0006167a25 */
/* 0x000fc600078e020c */
/*0910*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*0920*/ IMAD.WIDE R18, R6, c[0x0][0x180], R18 ; /* 0x0000600006127a25 */
/* 0x001fc800078e0212 */
/*0930*/ FFMA R28, R27, R28, R10 ; /* 0x0000001c1b1c7223 */
/* 0x004fe4000000000a */
/*0940*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea8000c1e1900 */
/*0950*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0960*/ FFMA R7, R7, R8, R28 ; /* 0x0000000807077223 */
/* 0x008fc8000000001c */
/*0970*/ FFMA R7, R25, R26, R7 ; /* 0x0000001a19077223 */
/* 0x020fc80000000007 */
/*0980*/ FFMA R7, R21, R24, R7 ; /* 0x0000001815077223 */
/* 0x000fc80000000007 */
/*0990*/ FFMA R7, R11, R20, R7 ; /* 0x000000140b077223 */
/* 0x010fe20000000007 */
/*09a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09b0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*09c0*/ FFMA R7, R9, R14, R7 ; /* 0x0000000e09077223 */
/* 0x000fe20000000007 */
/*09d0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*09e0*/ IMAD.WIDE R14, R6, c[0x0][0x180], R18 ; /* 0x00006000060e7a25 */
/* 0x000fc800078e0212 */
/*09f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fe40000000007 */
/*0a00*/ IMAD.WIDE R16, R6, c[0x0][0x178], R22 ; /* 0x00005e0006107a25 */
/* 0x000fc800078e0216 */
/*0a10*/ FFMA R10, R10, R27, R7 ; /* 0x0000001b0a0a7223 */
/* 0x004fe40000000007 */
/*0a20*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0a30*/ @!P0 BRA 0xbc0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.WIDE R8, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e0006087a25 */
/* 0x040fe400078e0210 */
/*0a50*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x180], R14 ; /* 0x00006000060c7a25 */
/* 0x040fe400078e020e */
/*0a70*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000a4000c1e1900 */
/*0a80*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x178], R8 ; /* 0x00005e0006167a25 */
/* 0x040fe400078e0208 */
/*0a90*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0aa0*/ IMAD.WIDE R18, R6, c[0x0][0x180], R12 ; /* 0x0000600006127a25 */
/* 0x000fc400078e020c */
/*0ab0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0ac0*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x178], R22 ; /* 0x00005e0006147a25 */
/* 0x040fe400078e0216 */
/*0ad0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f24000c1e1900 */
/*0ae0*/ IMAD.WIDE R24, R6, c[0x0][0x180], R18 ; /* 0x0000600006187a25 */
/* 0x000fe400078e0212 */
/*0af0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000f68000c1e1900 */
/*0b10*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x001f62000c1e1900 */
/*0b20*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0b30*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0b40*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FFMA R15, R15, R16, R10 ; /* 0x000000100f0f7223 */
/* 0x004fc8000000000a */
/*0b60*/ FFMA R15, R12, R8, R15 ; /* 0x000000080c0f7223 */
/* 0x008fe4000000000f */
/*0b70*/ IMAD.WIDE R16, R6, c[0x0][0x178], R20 ; /* 0x00005e0006107a25 */
/* 0x000fc800078e0214 */
/*0b80*/ FFMA R7, R26, R7, R15 ; /* 0x000000071a077223 */
/* 0x010fc8000000000f */
/*0b90*/ FFMA R10, R14, R11, R7 ; /* 0x0000000b0e0a7223 */
/* 0x020fe40000000007 */
/*0ba0*/ IMAD.WIDE R14, R6, c[0x0][0x180], R24 ; /* 0x00006000060e7a25 */
/* 0x000fe200078e0218 */
/*0bb0*/ @P0 BRA 0xa40 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0bd0*/ @!P0 BRA 0xcb0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0be0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0bf0*/ IMAD R5, R4.reuse, c[0x0][0x180], R0 ; /* 0x0000600004057a24 */
/* 0x040fe400078e0200 */
/*0c00*/ IMAD R6, R4, c[0x0][0x178], R3 ; /* 0x00005e0004067a24 */
/* 0x000fce00078e0203 */
/*0c10*/ IMAD.WIDE R4, R5, R11, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e020b */
/*0c20*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0c30*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0c40*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0002a2000c1e1900 */
/*0c50*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c70*/ IMAD.WIDE R4, R11, c[0x0][0x180], R4 ; /* 0x000060000b047a25 */
/* 0x001fc800078e0204 */
/*0c80*/ IMAD.WIDE R6, R11, c[0x0][0x178], R6 ; /* 0x00005e000b067a25 */
/* 0x002fc800078e0206 */
/*0c90*/ FFMA R10, R9, R8, R10 ; /* 0x00000008090a7223 */
/* 0x004fc8000000000a */
/*0ca0*/ @P0 BRA 0xc30 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0cb0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0cc0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0cd0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0ce0*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0cf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d00*/ BRA 0xd00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void linearLayerBackprop(float* W, float* dZ, float *dA, int W_x_dim, int W_y_dim, int dZ_x_dim, int dZ_y_dim) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
// W is treated as transposed
int dA_x_dim = dZ_x_dim;
int dA_y_dim = W_x_dim;
float dA_value = 0.0f;
if (row < dA_y_dim && col < dA_x_dim) {
for (int i = 0; i < W_y_dim; i++) {
dA_value += W[i * W_x_dim + row] * dZ[i * dZ_x_dim + col];
}
dA[row * dA_x_dim + col] = dA_value;
}
} | .file "tmpxft_0016f41b_00000000-6_linearLayerBackprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii
.type _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii, @function
_Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19linearLayerBackpropPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii, .-_Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii
.globl _Z19linearLayerBackpropPfS_S_iiii
.type _Z19linearLayerBackpropPfS_S_iiii, @function
_Z19linearLayerBackpropPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19linearLayerBackpropPfS_S_iiii, .-_Z19linearLayerBackpropPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19linearLayerBackpropPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19linearLayerBackpropPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void linearLayerBackprop(float* W, float* dZ, float *dA, int W_x_dim, int W_y_dim, int dZ_x_dim, int dZ_y_dim) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
// W is treated as transposed
int dA_x_dim = dZ_x_dim;
int dA_y_dim = W_x_dim;
float dA_value = 0.0f;
if (row < dA_y_dim && col < dA_x_dim) {
for (int i = 0; i < W_y_dim; i++) {
dA_value += W[i * W_x_dim + row] * dZ[i * dZ_x_dim + col];
}
dA[row * dA_x_dim + col] = dA_value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void linearLayerBackprop(float* W, float* dZ, float *dA, int W_x_dim, int W_y_dim, int dZ_x_dim, int dZ_y_dim) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
// W is treated as transposed
int dA_x_dim = dZ_x_dim;
int dA_y_dim = W_x_dim;
float dA_value = 0.0f;
if (row < dA_y_dim && col < dA_x_dim) {
for (int i = 0; i < W_y_dim; i++) {
dA_value += W[i * W_x_dim + row] * dZ[i * dZ_x_dim + col];
}
dA[row * dA_x_dim + col] = dA_value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void linearLayerBackprop(float* W, float* dZ, float *dA, int W_x_dim, int W_y_dim, int dZ_x_dim, int dZ_y_dim) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
// W is treated as transposed
int dA_x_dim = dZ_x_dim;
int dA_y_dim = W_x_dim;
float dA_value = 0.0f;
if (row < dA_y_dim && col < dA_x_dim) {
for (int i = 0; i < W_y_dim; i++) {
dA_value += W[i * W_x_dim + row] * dZ[i * dZ_x_dim + col];
}
dA[row * dA_x_dim + col] = dA_value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19linearLayerBackpropPfS_S_iiii
.globl _Z19linearLayerBackpropPfS_S_iiii
.p2align 8
.type _Z19linearLayerBackpropPfS_S_iiii,@function
_Z19linearLayerBackpropPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
v_add_nc_u32_e32 v2, s8, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19linearLayerBackpropPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19linearLayerBackpropPfS_S_iiii, .Lfunc_end0-_Z19linearLayerBackpropPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19linearLayerBackpropPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19linearLayerBackpropPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void linearLayerBackprop(float* W, float* dZ, float *dA, int W_x_dim, int W_y_dim, int dZ_x_dim, int dZ_y_dim) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
// W is treated as transposed
int dA_x_dim = dZ_x_dim;
int dA_y_dim = W_x_dim;
float dA_value = 0.0f;
if (row < dA_y_dim && col < dA_x_dim) {
for (int i = 0; i < W_y_dim; i++) {
dA_value += W[i * W_x_dim + row] * dZ[i * dZ_x_dim + col];
}
dA[row * dA_x_dim + col] = dA_value;
}
} | .text
.file "linearLayerBackprop.hip"
.globl _Z34__device_stub__linearLayerBackpropPfS_S_iiii # -- Begin function _Z34__device_stub__linearLayerBackpropPfS_S_iiii
.p2align 4, 0x90
.type _Z34__device_stub__linearLayerBackpropPfS_S_iiii,@function
_Z34__device_stub__linearLayerBackpropPfS_S_iiii: # @_Z34__device_stub__linearLayerBackpropPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19linearLayerBackpropPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__linearLayerBackpropPfS_S_iiii, .Lfunc_end0-_Z34__device_stub__linearLayerBackpropPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19linearLayerBackpropPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19linearLayerBackpropPfS_S_iiii,@object # @_Z19linearLayerBackpropPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z19linearLayerBackpropPfS_S_iiii
.p2align 3, 0x0
_Z19linearLayerBackpropPfS_S_iiii:
.quad _Z34__device_stub__linearLayerBackpropPfS_S_iiii
.size _Z19linearLayerBackpropPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19linearLayerBackpropPfS_S_iiii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__linearLayerBackpropPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19linearLayerBackpropPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19linearLayerBackpropPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xcb0 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xbc0 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0170*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0180*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f04270 */
/*01a0*/ IMAD.WIDE R14, R0, R6, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x000fc800078e0206 */
/*01b0*/ IMAD.WIDE R16, R3, R6, c[0x0][0x160] ; /* 0x0000580003107625 */
/* 0x000fe400078e0206 */
/*01c0*/ @!P0 BRA 0xa40 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x750 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0230*/ IMAD.WIDE R22, R6, c[0x0][0x180], R14 ; /* 0x0000600006167a25 */
/* 0x000fc800078e020e */
/*0240*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e00061a7a25 */
/* 0x040fe200078e0210 */
/*0250*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000728000c1e1900 */
/*0260*/ LDG.E R24, [R26.64] ; /* 0x000000041a187981 */
/* 0x000b22000c1e1900 */
/*0270*/ IMAD.WIDE R22, R6, c[0x0][0x180], R22 ; /* 0x0000600006167a25 */
/* 0x008fc800078e0216 */
/*0280*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x178], R26 ; /* 0x00005e00061a7a25 */
/* 0x060fe200078e021a */
/*0290*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000766000c1e1900 */
/*02a0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x180], R22 ; /* 0x00006000060e7a25 */
/* 0x041fe200078e0216 */
/*02b0*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000166000c1e1900 */
/*02c0*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R26 ; /* 0x00005e00060c7a25 */
/* 0x040fe200078e021a */
/*02d0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x002368000c1e1900 */
/*02e0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD.WIDE R28, R6, c[0x0][0x178], R12 ; /* 0x00005e00061c7a25 */
/* 0x000fc800078e020c */
/*0300*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x180], R14 ; /* 0x00006000060e7a25 */
/* 0x042fe200078e020e */
/*0310*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x008762000c1e1900 */
/*0330*/ IMAD.WIDE R26, R6, c[0x0][0x180], R14 ; /* 0x00006000061a7a25 */
/* 0x001fc800078e020e */
/*0340*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x178], R28 ; /* 0x00005e00061c7a25 */
/* 0x042fe200078e021c */
/*0350*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x00016a000c1e1900 */
/*0360*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R28 ; /* 0x00005e00060c7a25 */
/* 0x040fe400078e021c */
/*0370*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000564000c1e1900 */
/*0380*/ IMAD.WIDE R26, R6, c[0x0][0x180], R26 ; /* 0x00006000061a7a25 */
/* 0x001fc400078e021a */
/*0390*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000168000c1e1900 */
/*03a0*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000362000c1e1900 */
/*03b0*/ IMAD.WIDE R14, R6, c[0x0][0x180], R26 ; /* 0x00006000060e7a25 */
/* 0x008fc800078e021a */
/*03c0*/ IMAD.WIDE R12, R6, c[0x0][0x178], R12 ; /* 0x00005e00060c7a25 */
/* 0x001fc800078e020c */
/*03d0*/ FFMA R29, R20, R9, R10 ; /* 0x00000009141d7223 */
/* 0x004fe4000000000a */
/*03e0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a8000c1e1900 */
/*03f0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0006a2000c1e1900 */
/*0400*/ IMAD.WIDE R20, R6, c[0x0][0x178], R12 ; /* 0x00005e0006147a25 */
/* 0x000fc800078e020c */
/*0410*/ FFMA R29, R11, R24, R29 ; /* 0x000000180b1d7223 */
/* 0x010fe4000000001d */
/*0420*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0008a2000c1e1900 */
/*0430*/ IMAD.WIDE R14, R6, c[0x0][0x180], R14 ; /* 0x00006000060e7a25 */
/* 0x008fca00078e020e */
/*0440*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0006a2000c1e1900 */
/*0450*/ IMAD.WIDE R26, R6, c[0x0][0x178], R20 ; /* 0x00005e00061a7a25 */
/* 0x002fc800078e0214 */
/*0460*/ FFMA R29, R19, R18, R29 ; /* 0x00000012131d7223 */
/* 0x020fe4000000001d */
/*0470*/ IMAD.WIDE R18, R6, c[0x0][0x180], R14 ; /* 0x0000600006127a25 */
/* 0x000fc800078e020e */
/*0480*/ FFMA R16, R16, R25, R29 ; /* 0x0000001910107223 */
/* 0x000fe4000000001d */
/*0490*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*04a0*/ IMAD.WIDE R12, R6, c[0x0][0x178], R26 ; /* 0x00005e00060c7a25 */
/* 0x001fc600078e021a */
/*04b0*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000162000c1e1900 */
/*04c0*/ IMAD.WIDE R18, R6, c[0x0][0x180], R18 ; /* 0x0000600006127a25 */
/* 0x002fc800078e0212 */
/*04d0*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fe20000000010 */
/*04e0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x001162000c1e1900 */
/*04f0*/ IMAD.WIDE R14, R6, c[0x0][0x178], R12 ; /* 0x00005e00060e7a25 */
/* 0x008fc600078e020c */
/*0500*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0004e2000c1e1900 */
/*0510*/ IMAD.WIDE R16, R6, c[0x0][0x180], R18 ; /* 0x0000600006107a25 */
/* 0x000fc600078e0212 */
/*0520*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x0002e2000c1e1900 */
/*0530*/ FFMA R28, R23, R28, R22 ; /* 0x0000001c171c7223 */
/* 0x000fe40000000016 */
/*0540*/ IMAD.WIDE R20, R6, c[0x0][0x178], R14 ; /* 0x00005e0006147a25 */
/* 0x010fc800078e020e */
/*0550*/ IMAD.WIDE R22, R6, c[0x0][0x180], R16 ; /* 0x0000600006167a25 */
/* 0x000fe400078e0210 */
/*0560*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0570*/ FFMA R8, R8, R7, R28 ; /* 0x0000000708087223 */
/* 0x000fe4000000001c */
/*0580*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R20 ; /* 0x00005e00060e7a25 */
/* 0x042fe200078e0214 */
/*0590*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x0002e6000c1e1900 */
/*05a0*/ IMAD.WIDE R18, R6, c[0x0][0x180], R22 ; /* 0x0000600006127a25 */
/* 0x001fe200078e0216 */
/*05b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee6000c1e1900 */
/*05c0*/ FFMA R13, R10, R9, R8 ; /* 0x000000090a0d7223 */
/* 0x004fc40000000008 */
/*05d0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*05e0*/ IMAD.WIDE R8, R6, c[0x0][0x178], R14 ; /* 0x00005e0006087a25 */
/* 0x000fc600078e020e */
/*05f0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0108a2000c1e1900 */
/*0610*/ IMAD.WIDE R18, R6, c[0x0][0x180], R18 ; /* 0x0000600006127a25 */
/* 0x001fca00078e0212 */
/*0620*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.WIDE R22, R6, c[0x0][0x180], R18 ; /* 0x0000600006167a25 */
/* 0x002fc800078e0212 */
/*0640*/ IMAD.WIDE R8, R6, c[0x0][0x178], R8 ; /* 0x00005e0006087a25 */
/* 0x010fc800078e0208 */
/*0650*/ FFMA R13, R11, R24, R13 ; /* 0x000000180b0d7223 */
/* 0x000fe4000000000d */
/*0660*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f28000c1e1900 */
/*0670*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000f22000c1e1900 */
/*0680*/ FFMA R13, R25, R26, R13 ; /* 0x0000001a190d7223 */
/* 0x020fe2000000000d */
/*0690*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*06a0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*06b0*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x008fc8000000000d */
/*06c0*/ FFMA R12, R16, R29, R12 ; /* 0x0000001d100c7223 */
/* 0x000fc8000000000c */
/*06d0*/ FFMA R7, R7, R20, R12 ; /* 0x0000001407077223 */
/* 0x000fe2000000000c */
/*06e0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ FFMA R7, R10, R15, R7 ; /* 0x0000000f0a077223 */
/* 0x004fe40000000007 */
/*0700*/ IMAD.WIDE R14, R6, c[0x0][0x180], R22 ; /* 0x00006000060e7a25 */
/* 0x000fc800078e0216 */
/*0710*/ FFMA R7, R28, R17, R7 ; /* 0x000000111c077223 */
/* 0x000fe40000000007 */
/*0720*/ IMAD.WIDE R16, R6, c[0x0][0x178], R8 ; /* 0x00005e0006107a25 */
/* 0x000fc800078e0208 */
/*0730*/ FFMA R10, R11, R24, R7 ; /* 0x000000180b0a7223 */
/* 0x010fe20000000007 */
/*0740*/ @P1 BRA 0x210 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0750*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0xa20 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0000a8000c1e1900 */
/*0780*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*0790*/ IMAD.WIDE R8, R6, c[0x0][0x178], R16 ; /* 0x00005e0006087a25 */
/* 0x000fc800078e0210 */
/*07a0*/ IMAD.WIDE R12, R6, c[0x0][0x180], R14 ; /* 0x00006000060c7a25 */
/* 0x000fc800078e020e */
/*07b0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R8 ; /* 0x00005e00060e7a25 */
/* 0x041fe200078e0208 */
/*07c0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0000e6000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x180], R12 ; /* 0x0000600006127a25 */
/* 0x040fe200078e020c */
/*07e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0008e6000c1e1900 */
/*07f0*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x178], R14 ; /* 0x00005e0006107a25 */
/* 0x042fe200078e020e */
/*0800*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000366000c1e1900 */
/*0810*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x180], R18 ; /* 0x0000600006147a25 */
/* 0x040fe200078e0212 */
/*0820*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000366000c1e1900 */
/*0830*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e00060c7a25 */
/* 0x041fe200078e0210 */
/*0840*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000166000c1e1900 */
/*0850*/ IMAD.WIDE R22, R6, c[0x0][0x180], R20 ; /* 0x0000600006167a25 */
/* 0x000fc400078e0214 */
/*0860*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000964000c1e1900 */
/*0870*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x178], R12 ; /* 0x00005e00060e7a25 */
/* 0x042fe400078e020c */
/*0880*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000364000c1e1900 */
/*0890*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x180], R22 ; /* 0x0000600006107a25 */
/* 0x041fe400078e0216 */
/*08a0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x010128000c1e1900 */
/*08b0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x180], R16 ; /* 0x0000600006127a25 */
/* 0x040fe200078e0210 */
/*08c0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000326000c1e1900 */
/*08d0*/ IMAD.WIDE R12, R6, c[0x0][0x178], R14 ; /* 0x00005e00060c7a25 */
/* 0x001fc400078e020e */
/*08e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*08f0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x002122000c1e1900 */
/*0900*/ IMAD.WIDE R22, R6, c[0x0][0x178], R12 ; /* 0x00005e0006167a25 */
/* 0x000fc600078e020c */
/*0910*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*0920*/ IMAD.WIDE R18, R6, c[0x0][0x180], R18 ; /* 0x0000600006127a25 */
/* 0x001fc800078e0212 */
/*0930*/ FFMA R28, R27, R28, R10 ; /* 0x0000001c1b1c7223 */
/* 0x004fe4000000000a */
/*0940*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea8000c1e1900 */
/*0950*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0960*/ FFMA R7, R7, R8, R28 ; /* 0x0000000807077223 */
/* 0x008fc8000000001c */
/*0970*/ FFMA R7, R25, R26, R7 ; /* 0x0000001a19077223 */
/* 0x020fc80000000007 */
/*0980*/ FFMA R7, R21, R24, R7 ; /* 0x0000001815077223 */
/* 0x000fc80000000007 */
/*0990*/ FFMA R7, R11, R20, R7 ; /* 0x000000140b077223 */
/* 0x010fe20000000007 */
/*09a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09b0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*09c0*/ FFMA R7, R9, R14, R7 ; /* 0x0000000e09077223 */
/* 0x000fe20000000007 */
/*09d0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*09e0*/ IMAD.WIDE R14, R6, c[0x0][0x180], R18 ; /* 0x00006000060e7a25 */
/* 0x000fc800078e0212 */
/*09f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fe40000000007 */
/*0a00*/ IMAD.WIDE R16, R6, c[0x0][0x178], R22 ; /* 0x00005e0006107a25 */
/* 0x000fc800078e0216 */
/*0a10*/ FFMA R10, R10, R27, R7 ; /* 0x0000001b0a0a7223 */
/* 0x004fe40000000007 */
/*0a20*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0a30*/ @!P0 BRA 0xbc0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.WIDE R8, R6.reuse, c[0x0][0x178], R16 ; /* 0x00005e0006087a25 */
/* 0x040fe400078e0210 */
/*0a50*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x180], R14 ; /* 0x00006000060c7a25 */
/* 0x040fe400078e020e */
/*0a70*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000a4000c1e1900 */
/*0a80*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x178], R8 ; /* 0x00005e0006167a25 */
/* 0x040fe400078e0208 */
/*0a90*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0aa0*/ IMAD.WIDE R18, R6, c[0x0][0x180], R12 ; /* 0x0000600006127a25 */
/* 0x000fc400078e020c */
/*0ab0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0ac0*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x178], R22 ; /* 0x00005e0006147a25 */
/* 0x040fe400078e0216 */
/*0ad0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f24000c1e1900 */
/*0ae0*/ IMAD.WIDE R24, R6, c[0x0][0x180], R18 ; /* 0x0000600006187a25 */
/* 0x000fe400078e0212 */
/*0af0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000f68000c1e1900 */
/*0b10*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x001f62000c1e1900 */
/*0b20*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0b30*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0b40*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FFMA R15, R15, R16, R10 ; /* 0x000000100f0f7223 */
/* 0x004fc8000000000a */
/*0b60*/ FFMA R15, R12, R8, R15 ; /* 0x000000080c0f7223 */
/* 0x008fe4000000000f */
/*0b70*/ IMAD.WIDE R16, R6, c[0x0][0x178], R20 ; /* 0x00005e0006107a25 */
/* 0x000fc800078e0214 */
/*0b80*/ FFMA R7, R26, R7, R15 ; /* 0x000000071a077223 */
/* 0x010fc8000000000f */
/*0b90*/ FFMA R10, R14, R11, R7 ; /* 0x0000000b0e0a7223 */
/* 0x020fe40000000007 */
/*0ba0*/ IMAD.WIDE R14, R6, c[0x0][0x180], R24 ; /* 0x00006000060e7a25 */
/* 0x000fe200078e0218 */
/*0bb0*/ @P0 BRA 0xa40 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0bd0*/ @!P0 BRA 0xcb0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0be0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0bf0*/ IMAD R5, R4.reuse, c[0x0][0x180], R0 ; /* 0x0000600004057a24 */
/* 0x040fe400078e0200 */
/*0c00*/ IMAD R6, R4, c[0x0][0x178], R3 ; /* 0x00005e0004067a24 */
/* 0x000fce00078e0203 */
/*0c10*/ IMAD.WIDE R4, R5, R11, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc800078e020b */
/*0c20*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0c30*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0c40*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0002a2000c1e1900 */
/*0c50*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c70*/ IMAD.WIDE R4, R11, c[0x0][0x180], R4 ; /* 0x000060000b047a25 */
/* 0x001fc800078e0204 */
/*0c80*/ IMAD.WIDE R6, R11, c[0x0][0x178], R6 ; /* 0x00005e000b067a25 */
/* 0x002fc800078e0206 */
/*0c90*/ FFMA R10, R9, R8, R10 ; /* 0x00000008090a7223 */
/* 0x004fc8000000000a */
/*0ca0*/ @P0 BRA 0xc30 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0cb0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0cc0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0cd0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0ce0*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0cf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d00*/ BRA 0xd00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19linearLayerBackpropPfS_S_iiii
.globl _Z19linearLayerBackpropPfS_S_iiii
.p2align 8
.type _Z19linearLayerBackpropPfS_S_iiii,@function
_Z19linearLayerBackpropPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
v_add_nc_u32_e32 v2, s8, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19linearLayerBackpropPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19linearLayerBackpropPfS_S_iiii, .Lfunc_end0-_Z19linearLayerBackpropPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19linearLayerBackpropPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19linearLayerBackpropPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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