system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016f41b_00000000-6_linearLayerBackprop.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii
.type _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii, @function
_Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19linearLayerBackpropPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii, .-_Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii
.globl _Z19linearLayerBackpropPfS_S_iiii
.type _Z19linearLayerBackpropPfS_S_iiii, @function
_Z19linearLayerBackpropPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z19linearLayerBackpropPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19linearLayerBackpropPfS_S_iiii, .-_Z19linearLayerBackpropPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19linearLayerBackpropPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19linearLayerBackpropPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "linearLayerBackprop.hip"
.globl _Z34__device_stub__linearLayerBackpropPfS_S_iiii # -- Begin function _Z34__device_stub__linearLayerBackpropPfS_S_iiii
.p2align 4, 0x90
.type _Z34__device_stub__linearLayerBackpropPfS_S_iiii,@function
_Z34__device_stub__linearLayerBackpropPfS_S_iiii: # @_Z34__device_stub__linearLayerBackpropPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19linearLayerBackpropPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__linearLayerBackpropPfS_S_iiii, .Lfunc_end0-_Z34__device_stub__linearLayerBackpropPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19linearLayerBackpropPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19linearLayerBackpropPfS_S_iiii,@object # @_Z19linearLayerBackpropPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z19linearLayerBackpropPfS_S_iiii
.p2align 3, 0x0
_Z19linearLayerBackpropPfS_S_iiii:
.quad _Z34__device_stub__linearLayerBackpropPfS_S_iiii
.size _Z19linearLayerBackpropPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19linearLayerBackpropPfS_S_iiii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__linearLayerBackpropPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19linearLayerBackpropPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "sigmoid-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SigmoidCrossEntropyGrad::SigmoidCrossEntropyGrad(Op* y, Op* logits)
: Op("sigmoid_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SigmoidCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t len = cy.out_shape.total();
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(len);
auto out_node = rt::Node::op_sigmoid_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
len,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "sigmoid-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SigmoidCrossEntropyGrad::SigmoidCrossEntropyGrad(Op* y, Op* logits)
: Op("sigmoid_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SigmoidCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t len = cy.out_shape.total();
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(len);
auto out_node = rt::Node::op_sigmoid_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
len,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .file "tmpxft_001589d3_00000000-6_sigmoid-cross-entropy-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops23SigmoidCrossEntropyGradD2Ev,"axG",@progbits,_ZN3ops23SigmoidCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SigmoidCrossEntropyGradD2Ev
.type _ZN3ops23SigmoidCrossEntropyGradD2Ev, @function
_ZN3ops23SigmoidCrossEntropyGradD2Ev:
.LFB5632:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5632:
.size _ZN3ops23SigmoidCrossEntropyGradD2Ev, .-_ZN3ops23SigmoidCrossEntropyGradD2Ev
.weak _ZN3ops23SigmoidCrossEntropyGradD1Ev
.set _ZN3ops23SigmoidCrossEntropyGradD1Ev,_ZN3ops23SigmoidCrossEntropyGradD2Ev
.section .text._ZN3ops23SigmoidCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SigmoidCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SigmoidCrossEntropyGradD0Ev
.type _ZN3ops23SigmoidCrossEntropyGradD0Ev, @function
_ZN3ops23SigmoidCrossEntropyGradD0Ev:
.LFB5634:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5634:
.size _ZN3ops23SigmoidCrossEntropyGradD0Ev, .-_ZN3ops23SigmoidCrossEntropyGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4982:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4982:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.type _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_, @function
_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, 16(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 32(%rsp)
movq %rbx, (%rax)
movq %r12, 8(%rax)
movq %rdx, 24(%rsp)
movq %rbx, %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
movq %rax, %rbx
leaq 80(%rsp), %rdi
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $26, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE1:
jmp .L47
.L43:
endbr64
movq %rax, %rbx
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L33
call _ZdlPvm@PLT
.L33:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L47:
movq %rax, 80(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 96(%rsp)
movabsq $6873734858571999603, %rsi
movabsq $7954869266282410595, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $8247338199294374767, %rsi
movabsq $7233188264842719343, %rdi
movq %rsi, 10(%rax)
movq %rdi, 18(%rax)
movq %rdx, 88(%rsp)
movq 80(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 16(%rsp), %rcx
leaq 80(%rsp), %rsi
leaq 48(%rsp), %r8
movq %rbx, %rdx
movq %rbp, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 96(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L35
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L35:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L36
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L36:
leaq 16+_ZTVN3ops23SigmoidCrossEntropyGradE(%rip), %rax
movq %rax, 0(%rbp)
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L38:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L33
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L43-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_, .-_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.globl _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_
.set _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_,_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5162:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L52
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L52:
ret
.cfi_endproc
.LFE5162:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.type _ZN3ops23SigmoidCrossEntropyGrad7compileEv, @function
_ZN3ops23SigmoidCrossEntropyGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %r13
leaq -80(%rbp), %rdi
movq %r14, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %r13, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L56
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L56:
leaq -80(%rbp), %rdi
movq %r14, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq %r13, %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE7:
movq %rax, -152(%rbp)
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L57
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L57:
leaq 64(%rbx), %rdi
.LEHB8:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %r15
movq 72(%rbx), %r12
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
subq 64(%rbx), %r12
je .L86
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L99
movq %r12, %rdi
call _Znwm@PLT
.LEHE8:
movq %rax, -160(%rbp)
.L58:
movq -160(%rbp), %rdi
movq %rdi, -144(%rbp)
movq %rdi, -136(%rbp)
addq %rdi, %r12
movq %r12, -128(%rbp)
movq 64(%rbx), %rsi
movq 72(%rbx), %r12
subq %rsi, %r12
cmpq $4, %r12
jle .L61
movq %r12, %rdx
call memmove@PLT
.L62:
movq -160(%rbp), %rax
addq %r12, %rax
movq %rax, -136(%rbp)
movq %r15, %rdi
.LEHB9:
call _Z12tensor_allocm@PLT
.LEHE9:
jmp .L100
.L99:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L101
.LEHB10:
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE10:
.L101:
call __stack_chk_fail@PLT
.L86:
movq $0, -160(%rbp)
jmp .L58
.L61:
jne .L62
movl (%rsi), %eax
movq -160(%rbp), %rcx
movl %eax, (%rcx)
jmp .L62
.L100:
movq %rax, -160(%rbp)
movq 56(%rbx), %r12
movq -152(%rbp), %rcx
movq 56(%rcx), %rsi
movq %rsi, -168(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB11:
call _Znwm@PLT
.LEHE11:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r12, (%rax)
movq -168(%rbp), %rsi
movq %rsi, 8(%rax)
movq %rdx, -72(%rbp)
movq -152(%rbp), %rcx
movq 88(%rcx), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r8
movq %r15, %rcx
movq -160(%rbp), %rdx
.LEHB12:
call _ZN2rt4Node29op_sigmoid_cross_entropy_gradEPKfS2_PfmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE12:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L66
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L66:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
jmp .L102
.L92:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L65:
movq -144(%rbp), %rdi
movq -128(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L83
call _ZdlPvm@PLT
.L83:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L102:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq -160(%rbp), %r15
movq %r15, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r15
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r14, %rsi
movq %r13, %rdi
.LEHB15:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE15:
jmp .L103
.L93:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L103:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L73
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L73:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L74
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L74:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L55
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L55:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L72:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L87:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L77
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
.LEHB16:
call _Unwind_Resume@PLT
.L88:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L79
call __stack_chk_fail@PLT
.L79:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L90:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L65
.L91:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L72
.L89:
endbr64
movq %rax, %rbx
jmp .L65
.L84:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE16:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L87-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L88-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L89-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L92-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L90-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 .L93-.LFB4617
.uleb128 0
.uleb128 .LEHB14-.LFB4617
.uleb128 .LEHE14-.LEHB14
.uleb128 .L94-.LFB4617
.uleb128 0
.uleb128 .LEHB15-.LFB4617
.uleb128 .LEHE15-.LEHB15
.uleb128 .L91-.LFB4617
.uleb128 0
.uleb128 .LEHB16-.LFB4617
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops23SigmoidCrossEntropyGrad7compileEv, .-_ZN3ops23SigmoidCrossEntropyGrad7compileEv
.weak _ZTSN3ops23SigmoidCrossEntropyGradE
.section .rodata._ZTSN3ops23SigmoidCrossEntropyGradE,"aG",@progbits,_ZTSN3ops23SigmoidCrossEntropyGradE,comdat
.align 32
.type _ZTSN3ops23SigmoidCrossEntropyGradE, @object
.size _ZTSN3ops23SigmoidCrossEntropyGradE, 32
_ZTSN3ops23SigmoidCrossEntropyGradE:
.string "N3ops23SigmoidCrossEntropyGradE"
.weak _ZTIN3ops23SigmoidCrossEntropyGradE
.section .data.rel.ro._ZTIN3ops23SigmoidCrossEntropyGradE,"awG",@progbits,_ZTIN3ops23SigmoidCrossEntropyGradE,comdat
.align 8
.type _ZTIN3ops23SigmoidCrossEntropyGradE, @object
.size _ZTIN3ops23SigmoidCrossEntropyGradE, 24
_ZTIN3ops23SigmoidCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SigmoidCrossEntropyGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops23SigmoidCrossEntropyGradE
.section .data.rel.ro._ZTVN3ops23SigmoidCrossEntropyGradE,"awG",@progbits,_ZTVN3ops23SigmoidCrossEntropyGradE,comdat
.align 8
.type _ZTVN3ops23SigmoidCrossEntropyGradE, @object
.size _ZTVN3ops23SigmoidCrossEntropyGradE, 48
_ZTVN3ops23SigmoidCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SigmoidCrossEntropyGradE
.quad _ZN3ops23SigmoidCrossEntropyGradD1Ev
.quad _ZN3ops23SigmoidCrossEntropyGradD0Ev
.quad _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "sigmoid-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SigmoidCrossEntropyGrad::SigmoidCrossEntropyGrad(Op* y, Op* logits)
: Op("sigmoid_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SigmoidCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t len = cy.out_shape.total();
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(len);
auto out_node = rt::Node::op_sigmoid_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
len,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | #include <hip/hip_runtime.h>
#include "sigmoid-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SigmoidCrossEntropyGrad::SigmoidCrossEntropyGrad(Op* y, Op* logits)
: Op("sigmoid_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SigmoidCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t len = cy.out_shape.total();
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(len);
auto out_node = rt::Node::op_sigmoid_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
len,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "sigmoid-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SigmoidCrossEntropyGrad::SigmoidCrossEntropyGrad(Op* y, Op* logits)
: Op("sigmoid_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SigmoidCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t len = cy.out_shape.total();
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(len);
auto out_node = rt::Node::op_sigmoid_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
len,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "sigmoid-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SigmoidCrossEntropyGrad::SigmoidCrossEntropyGrad(Op* y, Op* logits)
: Op("sigmoid_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SigmoidCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t len = cy.out_shape.total();
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(len);
auto out_node = rt::Node::op_sigmoid_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
len,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.file "sigmoid-cross-entropy-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_,@function
_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_: # @_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
movl $27, %edi
callq _Znwm
movq %rax, 32(%rsp)
movq $26, 48(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str+10(%rip), %xmm0
movups %xmm0, 10(%rax)
movq $26, 40(%rsp)
movb $0, 26(%rax)
.Ltmp0:
movq %r15, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r12, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
callq _ZdlPv
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops23SigmoidCrossEntropyGradE+16, (%rbx)
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
jmp .LBB0_14
.LBB0_10:
.Ltmp5:
movq %rax, %rbx
.LBB0_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_16
# %bb.15:
callq _ZdlPv
jmp .LBB0_16
.LBB0_11:
.Ltmp2:
movq %rax, %rbx
.LBB0_16: # %.body
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_18
# %bb.17: # %.critedge.i.i23
callq _ZdlPv
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops23SigmoidCrossEntropyGrad7compileEv,@function
_ZN3ops23SigmoidCrossEntropyGrad7compileEv: # @_ZN3ops23SigmoidCrossEntropyGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
callq _ZN3ops5Graph8instanceEv
movq %rax, %r13
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %r13, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r15
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %r13, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, %r12
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit38
movq %r15, %rdi
addq $64, %rdi
callq _ZNK3ops5Shape5totalEv
movl %eax, %ebp
movq 72(%r15), %rdi
movq 64(%r15), %rax
movq %rdi, %rbx
subq %rax, %rbx
sarq $2, %rbx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
subq %rax, %rdi
movq %r14, 144(%rsp) # 8-byte Spill
movq %r13, 136(%rsp) # 8-byte Spill
je .LBB1_9
# %bb.7:
movq %rbx, %rax
shrq $61, %rax
jne .LBB1_29
# %bb.8: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i.i
callq _Znwm
movq %rax, %r13
jmp .LBB1_10
.LBB1_9:
xorl %r13d, %r13d
.LBB1_10: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i.i
movslq %ebp, %rbp
movq %r13, 16(%rsp)
movq %r13, 24(%rsp)
leaq (,%rbx,4), %rax
addq %r13, %rax
movq %rax, 32(%rsp)
movq 64(%r15), %rsi
movq 72(%r15), %rbx
subq %rsi, %rbx
cmpq $5, %rbx
jl .LBB1_27
# %bb.11:
movq %r13, %rdi
movq %rbx, %rdx
callq memmove@PLT
.LBB1_12: # %_ZN3ops5ShapeC2ERKS0_.exit
addq %rbx, %r13
movq %r13, 24(%rsp)
.Ltmp15:
movq %rbp, %rdi
callq _Z12tensor_allocm
.Ltmp16:
# %bb.13:
movq %rax, %r13
movq 88(%r15), %rbx
movq 88(%r12), %r14
movq 56(%r15), %r15
movq 56(%r12), %r12
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp18:
movl $16, %edi
callq _Znwm
.Ltmp19:
# %bb.14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 112(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 128(%rsp)
movq %r15, (%rax)
movq %r12, 8(%rax)
movq %rcx, 120(%rsp)
.Ltmp21:
leaq 112(%rsp), %r8
movq %rbx, %rdi
movq %r14, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq _ZN2rt4Node29op_sigmoid_cross_entropy_gradEPKfS2_PfmRKSt6vectorIPS0_SaIS5_EE
.Ltmp22:
# %bb.15:
movq %rax, %r15
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_17
# %bb.16:
callq _ZdlPv
.LBB1_17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp24:
movl $8, %edi
callq _Znwm
.Ltmp25:
# %bb.18: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit45
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r15, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp27:
movl $8, %edi
callq _Znwm
.Ltmp28:
# %bb.19: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r13, (%rax)
movq %rcx, 56(%rsp)
.Ltmp30:
movq %r13, (%rsp)
leaq 80(%rsp), %rdx
leaq 48(%rsp), %rcx
leaq 16(%rsp), %r9
movq 136(%rsp), %rdi # 8-byte Reload
movq 144(%rsp), %rsi # 8-byte Reload
movq %r15, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp31:
# %bb.20:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_22
# %bb.21:
callq _ZdlPv
.LBB1_22: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit53
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_26
# %bb.25:
callq _ZdlPv
.LBB1_26: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 208
cmpq $4, %rbx
jne .LBB1_12
# %bb.28:
movl (%rsi), %eax
movl %eax, (%r13)
jmp .LBB1_12
.LBB1_29:
shrq $62, %rbx
je .LBB1_31
# %bb.30: # %.noexc.i.i.i
callq _ZSt28__throw_bad_array_new_lengthv
.LBB1_31: # %.noexc4.i.i.i
callq _ZSt17__throw_bad_allocv
.LBB1_32:
.Ltmp32:
jmp .LBB1_34
.LBB1_33:
.Ltmp29:
.LBB1_34:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_37
# %bb.35: # %.body47.sink.split
callq _ZdlPv
jmp .LBB1_37
.LBB1_36:
.Ltmp26:
movq %rax, %rbx
.LBB1_37: # %.body47
movq 80(%rsp), %rdi
jmp .LBB1_41
.LBB1_38:
.Ltmp23:
jmp .LBB1_40
.LBB1_39:
.Ltmp20:
.LBB1_40:
movq %rax, %rbx
movq 112(%rsp), %rdi
.LBB1_41: # %.body47
testq %rdi, %rdi
je .LBB1_47
# %bb.42:
callq _ZdlPv
jmp .LBB1_47
.LBB1_43:
.Ltmp17:
jmp .LBB1_46
.LBB1_44:
.Ltmp14:
jmp .LBB1_46
.LBB1_45:
.Ltmp11:
.LBB1_46: # %.body43
movq %rax, %rbx
.LBB1_47: # %.body43
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_49
# %bb.48:
callq _ZdlPv
.LBB1_49:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops23SigmoidCrossEntropyGrad7compileEv, .Lfunc_end1-_ZN3ops23SigmoidCrossEntropyGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin1 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops23SigmoidCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SigmoidCrossEntropyGradD0Ev,comdat
.weak _ZN3ops23SigmoidCrossEntropyGradD0Ev # -- Begin function _ZN3ops23SigmoidCrossEntropyGradD0Ev
.p2align 4, 0x90
.type _ZN3ops23SigmoidCrossEntropyGradD0Ev,@function
_ZN3ops23SigmoidCrossEntropyGradD0Ev: # @_ZN3ops23SigmoidCrossEntropyGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops23SigmoidCrossEntropyGradD0Ev, .Lfunc_end3-_ZN3ops23SigmoidCrossEntropyGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sigmoid_cross_entropy_grad"
.size .L.str, 27
.type _ZTVN3ops23SigmoidCrossEntropyGradE,@object # @_ZTVN3ops23SigmoidCrossEntropyGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops23SigmoidCrossEntropyGradE
.p2align 3, 0x0
_ZTVN3ops23SigmoidCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SigmoidCrossEntropyGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops23SigmoidCrossEntropyGradD0Ev
.quad _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops23SigmoidCrossEntropyGradE, 48
.type _ZTSN3ops23SigmoidCrossEntropyGradE,@object # @_ZTSN3ops23SigmoidCrossEntropyGradE
.globl _ZTSN3ops23SigmoidCrossEntropyGradE
_ZTSN3ops23SigmoidCrossEntropyGradE:
.asciz "N3ops23SigmoidCrossEntropyGradE"
.size _ZTSN3ops23SigmoidCrossEntropyGradE, 32
.type _ZTIN3ops23SigmoidCrossEntropyGradE,@object # @_ZTIN3ops23SigmoidCrossEntropyGradE
.globl _ZTIN3ops23SigmoidCrossEntropyGradE
.p2align 3, 0x0
_ZTIN3ops23SigmoidCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SigmoidCrossEntropyGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops23SigmoidCrossEntropyGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_
.type _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_,@function
.set _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_, _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops23SigmoidCrossEntropyGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops23SigmoidCrossEntropyGradE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001589d3_00000000-6_sigmoid-cross-entropy-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops23SigmoidCrossEntropyGradD2Ev,"axG",@progbits,_ZN3ops23SigmoidCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SigmoidCrossEntropyGradD2Ev
.type _ZN3ops23SigmoidCrossEntropyGradD2Ev, @function
_ZN3ops23SigmoidCrossEntropyGradD2Ev:
.LFB5632:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5632:
.size _ZN3ops23SigmoidCrossEntropyGradD2Ev, .-_ZN3ops23SigmoidCrossEntropyGradD2Ev
.weak _ZN3ops23SigmoidCrossEntropyGradD1Ev
.set _ZN3ops23SigmoidCrossEntropyGradD1Ev,_ZN3ops23SigmoidCrossEntropyGradD2Ev
.section .text._ZN3ops23SigmoidCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SigmoidCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SigmoidCrossEntropyGradD0Ev
.type _ZN3ops23SigmoidCrossEntropyGradD0Ev, @function
_ZN3ops23SigmoidCrossEntropyGradD0Ev:
.LFB5634:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5634:
.size _ZN3ops23SigmoidCrossEntropyGradD0Ev, .-_ZN3ops23SigmoidCrossEntropyGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4982:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4982:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.type _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_, @function
_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, 16(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 32(%rsp)
movq %rbx, (%rax)
movq %r12, 8(%rax)
movq %rdx, 24(%rsp)
movq %rbx, %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
movq %rax, %rbx
leaq 80(%rsp), %rdi
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $26, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE1:
jmp .L47
.L43:
endbr64
movq %rax, %rbx
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L33
call _ZdlPvm@PLT
.L33:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L47:
movq %rax, 80(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 96(%rsp)
movabsq $6873734858571999603, %rsi
movabsq $7954869266282410595, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $8247338199294374767, %rsi
movabsq $7233188264842719343, %rdi
movq %rsi, 10(%rax)
movq %rdi, 18(%rax)
movq %rdx, 88(%rsp)
movq 80(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 16(%rsp), %rcx
leaq 80(%rsp), %rsi
leaq 48(%rsp), %r8
movq %rbx, %rdx
movq %rbp, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 96(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L35
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L35:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L36
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L36:
leaq 16+_ZTVN3ops23SigmoidCrossEntropyGradE(%rip), %rax
movq %rax, 0(%rbp)
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L38:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L33
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L43-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_, .-_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.globl _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_
.set _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_,_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5162:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L52
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L52:
ret
.cfi_endproc
.LFE5162:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.type _ZN3ops23SigmoidCrossEntropyGrad7compileEv, @function
_ZN3ops23SigmoidCrossEntropyGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %r13
leaq -80(%rbp), %rdi
movq %r14, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %r13, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L56
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L56:
leaq -80(%rbp), %rdi
movq %r14, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq %r13, %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE7:
movq %rax, -152(%rbp)
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L57
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L57:
leaq 64(%rbx), %rdi
.LEHB8:
call _ZNK3ops5Shape5totalEv@PLT
movslq %eax, %r15
movq 72(%rbx), %r12
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
subq 64(%rbx), %r12
je .L86
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L99
movq %r12, %rdi
call _Znwm@PLT
.LEHE8:
movq %rax, -160(%rbp)
.L58:
movq -160(%rbp), %rdi
movq %rdi, -144(%rbp)
movq %rdi, -136(%rbp)
addq %rdi, %r12
movq %r12, -128(%rbp)
movq 64(%rbx), %rsi
movq 72(%rbx), %r12
subq %rsi, %r12
cmpq $4, %r12
jle .L61
movq %r12, %rdx
call memmove@PLT
.L62:
movq -160(%rbp), %rax
addq %r12, %rax
movq %rax, -136(%rbp)
movq %r15, %rdi
.LEHB9:
call _Z12tensor_allocm@PLT
.LEHE9:
jmp .L100
.L99:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L101
.LEHB10:
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE10:
.L101:
call __stack_chk_fail@PLT
.L86:
movq $0, -160(%rbp)
jmp .L58
.L61:
jne .L62
movl (%rsi), %eax
movq -160(%rbp), %rcx
movl %eax, (%rcx)
jmp .L62
.L100:
movq %rax, -160(%rbp)
movq 56(%rbx), %r12
movq -152(%rbp), %rcx
movq 56(%rcx), %rsi
movq %rsi, -168(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB11:
call _Znwm@PLT
.LEHE11:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r12, (%rax)
movq -168(%rbp), %rsi
movq %rsi, 8(%rax)
movq %rdx, -72(%rbp)
movq -152(%rbp), %rcx
movq 88(%rcx), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r8
movq %r15, %rcx
movq -160(%rbp), %rdx
.LEHB12:
call _ZN2rt4Node29op_sigmoid_cross_entropy_gradEPKfS2_PfmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE12:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L66
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L66:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
jmp .L102
.L92:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L65:
movq -144(%rbp), %rdi
movq -128(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L83
call _ZdlPvm@PLT
.L83:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L102:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq -160(%rbp), %r15
movq %r15, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r15
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r14, %rsi
movq %r13, %rdi
.LEHB15:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE15:
jmp .L103
.L93:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L103:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L73
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L73:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L74
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L74:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L55
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L55:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L72:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L87:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L77
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
.LEHB16:
call _Unwind_Resume@PLT
.L88:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L79
call __stack_chk_fail@PLT
.L79:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L90:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L65
.L91:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L72
.L89:
endbr64
movq %rax, %rbx
jmp .L65
.L84:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE16:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L87-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L88-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L89-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L92-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L90-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 .L93-.LFB4617
.uleb128 0
.uleb128 .LEHB14-.LFB4617
.uleb128 .LEHE14-.LEHB14
.uleb128 .L94-.LFB4617
.uleb128 0
.uleb128 .LEHB15-.LFB4617
.uleb128 .LEHE15-.LEHB15
.uleb128 .L91-.LFB4617
.uleb128 0
.uleb128 .LEHB16-.LFB4617
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops23SigmoidCrossEntropyGrad7compileEv, .-_ZN3ops23SigmoidCrossEntropyGrad7compileEv
.weak _ZTSN3ops23SigmoidCrossEntropyGradE
.section .rodata._ZTSN3ops23SigmoidCrossEntropyGradE,"aG",@progbits,_ZTSN3ops23SigmoidCrossEntropyGradE,comdat
.align 32
.type _ZTSN3ops23SigmoidCrossEntropyGradE, @object
.size _ZTSN3ops23SigmoidCrossEntropyGradE, 32
_ZTSN3ops23SigmoidCrossEntropyGradE:
.string "N3ops23SigmoidCrossEntropyGradE"
.weak _ZTIN3ops23SigmoidCrossEntropyGradE
.section .data.rel.ro._ZTIN3ops23SigmoidCrossEntropyGradE,"awG",@progbits,_ZTIN3ops23SigmoidCrossEntropyGradE,comdat
.align 8
.type _ZTIN3ops23SigmoidCrossEntropyGradE, @object
.size _ZTIN3ops23SigmoidCrossEntropyGradE, 24
_ZTIN3ops23SigmoidCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SigmoidCrossEntropyGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops23SigmoidCrossEntropyGradE
.section .data.rel.ro._ZTVN3ops23SigmoidCrossEntropyGradE,"awG",@progbits,_ZTVN3ops23SigmoidCrossEntropyGradE,comdat
.align 8
.type _ZTVN3ops23SigmoidCrossEntropyGradE, @object
.size _ZTVN3ops23SigmoidCrossEntropyGradE, 48
_ZTVN3ops23SigmoidCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SigmoidCrossEntropyGradE
.quad _ZN3ops23SigmoidCrossEntropyGradD1Ev
.quad _ZN3ops23SigmoidCrossEntropyGradD0Ev
.quad _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sigmoid-cross-entropy-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_,@function
_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_: # @_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
movl $27, %edi
callq _Znwm
movq %rax, 32(%rsp)
movq $26, 48(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str+10(%rip), %xmm0
movups %xmm0, 10(%rax)
movq $26, 40(%rsp)
movb $0, 26(%rax)
.Ltmp0:
movq %r15, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r12, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
callq _ZdlPv
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops23SigmoidCrossEntropyGradE+16, (%rbx)
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
jmp .LBB0_14
.LBB0_10:
.Ltmp5:
movq %rax, %rbx
.LBB0_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_16
# %bb.15:
callq _ZdlPv
jmp .LBB0_16
.LBB0_11:
.Ltmp2:
movq %rax, %rbx
.LBB0_16: # %.body
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_18
# %bb.17: # %.critedge.i.i23
callq _ZdlPv
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops23SigmoidCrossEntropyGrad7compileEv,@function
_ZN3ops23SigmoidCrossEntropyGrad7compileEv: # @_ZN3ops23SigmoidCrossEntropyGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
callq _ZN3ops5Graph8instanceEv
movq %rax, %r13
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %r13, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r15
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %r13, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, %r12
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit38
movq %r15, %rdi
addq $64, %rdi
callq _ZNK3ops5Shape5totalEv
movl %eax, %ebp
movq 72(%r15), %rdi
movq 64(%r15), %rax
movq %rdi, %rbx
subq %rax, %rbx
sarq $2, %rbx
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
subq %rax, %rdi
movq %r14, 144(%rsp) # 8-byte Spill
movq %r13, 136(%rsp) # 8-byte Spill
je .LBB1_9
# %bb.7:
movq %rbx, %rax
shrq $61, %rax
jne .LBB1_29
# %bb.8: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i.i
callq _Znwm
movq %rax, %r13
jmp .LBB1_10
.LBB1_9:
xorl %r13d, %r13d
.LBB1_10: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i.i
movslq %ebp, %rbp
movq %r13, 16(%rsp)
movq %r13, 24(%rsp)
leaq (,%rbx,4), %rax
addq %r13, %rax
movq %rax, 32(%rsp)
movq 64(%r15), %rsi
movq 72(%r15), %rbx
subq %rsi, %rbx
cmpq $5, %rbx
jl .LBB1_27
# %bb.11:
movq %r13, %rdi
movq %rbx, %rdx
callq memmove@PLT
.LBB1_12: # %_ZN3ops5ShapeC2ERKS0_.exit
addq %rbx, %r13
movq %r13, 24(%rsp)
.Ltmp15:
movq %rbp, %rdi
callq _Z12tensor_allocm
.Ltmp16:
# %bb.13:
movq %rax, %r13
movq 88(%r15), %rbx
movq 88(%r12), %r14
movq 56(%r15), %r15
movq 56(%r12), %r12
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp18:
movl $16, %edi
callq _Znwm
.Ltmp19:
# %bb.14: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 112(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 128(%rsp)
movq %r15, (%rax)
movq %r12, 8(%rax)
movq %rcx, 120(%rsp)
.Ltmp21:
leaq 112(%rsp), %r8
movq %rbx, %rdi
movq %r14, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq _ZN2rt4Node29op_sigmoid_cross_entropy_gradEPKfS2_PfmRKSt6vectorIPS0_SaIS5_EE
.Ltmp22:
# %bb.15:
movq %rax, %r15
movq 112(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_17
# %bb.16:
callq _ZdlPv
.LBB1_17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp24:
movl $8, %edi
callq _Znwm
.Ltmp25:
# %bb.18: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit45
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %r15, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp27:
movl $8, %edi
callq _Znwm
.Ltmp28:
# %bb.19: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r13, (%rax)
movq %rcx, 56(%rsp)
.Ltmp30:
movq %r13, (%rsp)
leaq 80(%rsp), %rdx
leaq 48(%rsp), %rcx
leaq 16(%rsp), %r9
movq 136(%rsp), %rdi # 8-byte Reload
movq 144(%rsp), %rsi # 8-byte Reload
movq %r15, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp31:
# %bb.20:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_22
# %bb.21:
callq _ZdlPv
.LBB1_22: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_24
# %bb.23:
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit53
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_26
# %bb.25:
callq _ZdlPv
.LBB1_26: # %_ZN3ops5ShapeD2Ev.exit
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 208
cmpq $4, %rbx
jne .LBB1_12
# %bb.28:
movl (%rsi), %eax
movl %eax, (%r13)
jmp .LBB1_12
.LBB1_29:
shrq $62, %rbx
je .LBB1_31
# %bb.30: # %.noexc.i.i.i
callq _ZSt28__throw_bad_array_new_lengthv
.LBB1_31: # %.noexc4.i.i.i
callq _ZSt17__throw_bad_allocv
.LBB1_32:
.Ltmp32:
jmp .LBB1_34
.LBB1_33:
.Ltmp29:
.LBB1_34:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_37
# %bb.35: # %.body47.sink.split
callq _ZdlPv
jmp .LBB1_37
.LBB1_36:
.Ltmp26:
movq %rax, %rbx
.LBB1_37: # %.body47
movq 80(%rsp), %rdi
jmp .LBB1_41
.LBB1_38:
.Ltmp23:
jmp .LBB1_40
.LBB1_39:
.Ltmp20:
.LBB1_40:
movq %rax, %rbx
movq 112(%rsp), %rdi
.LBB1_41: # %.body47
testq %rdi, %rdi
je .LBB1_47
# %bb.42:
callq _ZdlPv
jmp .LBB1_47
.LBB1_43:
.Ltmp17:
jmp .LBB1_46
.LBB1_44:
.Ltmp14:
jmp .LBB1_46
.LBB1_45:
.Ltmp11:
.LBB1_46: # %.body43
movq %rax, %rbx
.LBB1_47: # %.body43
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_49
# %bb.48:
callq _ZdlPv
.LBB1_49:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops23SigmoidCrossEntropyGrad7compileEv, .Lfunc_end1-_ZN3ops23SigmoidCrossEntropyGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin1 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops23SigmoidCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SigmoidCrossEntropyGradD0Ev,comdat
.weak _ZN3ops23SigmoidCrossEntropyGradD0Ev # -- Begin function _ZN3ops23SigmoidCrossEntropyGradD0Ev
.p2align 4, 0x90
.type _ZN3ops23SigmoidCrossEntropyGradD0Ev,@function
_ZN3ops23SigmoidCrossEntropyGradD0Ev: # @_ZN3ops23SigmoidCrossEntropyGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops23SigmoidCrossEntropyGradD0Ev, .Lfunc_end3-_ZN3ops23SigmoidCrossEntropyGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sigmoid_cross_entropy_grad"
.size .L.str, 27
.type _ZTVN3ops23SigmoidCrossEntropyGradE,@object # @_ZTVN3ops23SigmoidCrossEntropyGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops23SigmoidCrossEntropyGradE
.p2align 3, 0x0
_ZTVN3ops23SigmoidCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SigmoidCrossEntropyGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops23SigmoidCrossEntropyGradD0Ev
.quad _ZN3ops23SigmoidCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops23SigmoidCrossEntropyGradE, 48
.type _ZTSN3ops23SigmoidCrossEntropyGradE,@object # @_ZTSN3ops23SigmoidCrossEntropyGradE
.globl _ZTSN3ops23SigmoidCrossEntropyGradE
_ZTSN3ops23SigmoidCrossEntropyGradE:
.asciz "N3ops23SigmoidCrossEntropyGradE"
.size _ZTSN3ops23SigmoidCrossEntropyGradE, 32
.type _ZTIN3ops23SigmoidCrossEntropyGradE,@object # @_ZTIN3ops23SigmoidCrossEntropyGradE
.globl _ZTIN3ops23SigmoidCrossEntropyGradE
.p2align 3, 0x0
_ZTIN3ops23SigmoidCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SigmoidCrossEntropyGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops23SigmoidCrossEntropyGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_
.type _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_,@function
.set _ZN3ops23SigmoidCrossEntropyGradC1EPNS_2OpES2_, _ZN3ops23SigmoidCrossEntropyGradC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops23SigmoidCrossEntropyGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops23SigmoidCrossEntropyGradE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
array[index] = index;
}
int main(void) {
int num_elements = 256;
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int *)malloc(num_bytes);
// cudaMalloc a device array
cudaMalloc((void **)&device_array, num_bytes);
int block_size = 16;
int grid_size = num_elements / block_size;
kernel<<<grid_size, block_size>>>(device_array);
// download and inspect the result on the host:
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
// print out the result element by element
for (int i = 0; i < num_elements; ++i) {
printf("%3d ", host_array[i]);
if ((i + 1) % block_size == 0) printf("\n");
}
// deallocate memory
free(host_array);
cudaFree(device_array);
} | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
array[index] = index;
}
int main(void) {
int num_elements = 256;
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int *)malloc(num_bytes);
// cudaMalloc a device array
cudaMalloc((void **)&device_array, num_bytes);
int block_size = 16;
int grid_size = num_elements / block_size;
kernel<<<grid_size, block_size>>>(device_array);
// download and inspect the result on the host:
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
// print out the result element by element
for (int i = 0; i < num_elements; ++i) {
printf("%3d ", host_array[i]);
if ((i + 1) % block_size == 0) printf("\n");
}
// deallocate memory
free(host_array);
cudaFree(device_array);
} | .file "tmpxft_001773ad_00000000-6_one_dim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%3d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L14
.L18:
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L12
.L13:
addq $1, %rbx
cmpq $257, %rbx
je .L19
.L14:
movl -4(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $15, %bl
jne .L13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L19:
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
array[index] = index;
}
int main(void) {
int num_elements = 256;
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int *)malloc(num_bytes);
// cudaMalloc a device array
cudaMalloc((void **)&device_array, num_bytes);
int block_size = 16;
int grid_size = num_elements / block_size;
kernel<<<grid_size, block_size>>>(device_array);
// download and inspect the result on the host:
cudaMemcpy(host_array, device_array, num_bytes, cudaMemcpyDeviceToHost);
// print out the result element by element
for (int i = 0; i < num_elements; ++i) {
printf("%3d ", host_array[i]);
if ((i + 1) % block_size == 0) printf("\n");
}
// deallocate memory
free(host_array);
cudaFree(device_array);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
array[index] = index;
}
int main(void) {
int num_elements = 256;
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int *)malloc(num_bytes);
// cudaMalloc a device array
hipMalloc((void **)&device_array, num_bytes);
int block_size = 16;
int grid_size = num_elements / block_size;
kernel<<<grid_size, block_size>>>(device_array);
// download and inspect the result on the host:
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
// print out the result element by element
for (int i = 0; i < num_elements; ++i) {
printf("%3d ", host_array[i]);
if ((i + 1) % block_size == 0) printf("\n");
}
// deallocate memory
free(host_array);
hipFree(device_array);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
array[index] = index;
}
int main(void) {
int num_elements = 256;
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int *)malloc(num_bytes);
// cudaMalloc a device array
hipMalloc((void **)&device_array, num_bytes);
int block_size = 16;
int grid_size = num_elements / block_size;
kernel<<<grid_size, block_size>>>(device_array);
// download and inspect the result on the host:
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
// print out the result element by element
for (int i = 0; i < num_elements; ++i) {
printf("%3d ", host_array[i]);
if ((i + 1) % block_size == 0) printf("\n");
}
// deallocate memory
free(host_array);
hipFree(device_array);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(int *array) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
array[index] = index;
}
int main(void) {
int num_elements = 256;
int num_bytes = num_elements * sizeof(int);
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
// malloc a host array
host_array = (int *)malloc(num_bytes);
// cudaMalloc a device array
hipMalloc((void **)&device_array, num_bytes);
int block_size = 16;
int grid_size = num_elements / block_size;
kernel<<<grid_size, block_size>>>(device_array);
// download and inspect the result on the host:
hipMemcpy(host_array, device_array, num_bytes, hipMemcpyDeviceToHost);
// print out the result element by element
for (int i = 0; i < num_elements; ++i) {
printf("%3d ", host_array[i]);
if ((i + 1) % block_size == 0) printf("\n");
}
// deallocate memory
free(host_array);
hipFree(device_array);
} | .text
.file "one_dim.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %r14d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %r14
cmpq $257, %r14 # imm = 0x101
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $15, %r14b
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_5
.LBB1_6:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%3d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001773ad_00000000-6_one_dim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%3d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $2, %ecx
movl $1024, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L14
.L18:
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L12
.L13:
addq $1, %rbx
cmpq $257, %rbx
je .L19
.L14:
movl -4(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $15, %bl
jne .L13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L19:
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "one_dim.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %r14d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %r14
cmpq $257, %r14 # imm = 0x101
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $15, %r14b
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_5
.LBB1_6:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%3d "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* PARA CORRERLO:
* $ export LD_LIBRARY_PATH=/usr/local/cuda/lib
* $ export PATH=$PATH:/usr/local/cuda/bin
* $ nvcc -o matrixTrans matrixTrans.cu -O2 -lc -lm
* $ ./matrixTrans n
*/
/*
* UNSIGNED INT --> Tipo de dato para enteros, números sin punto decimal.
* Los enteros sin signo pueden ser tan grandes como 65535
* y tan pequeños como 0.
* Son almacenados como 16 bits de información.
*
* SIZE_T --> is an unsigned integer type guaranteed to support the longest
* object for the platform you use. It is also the result of the
* sizeof operator.sizeof returns the size of the type in bytes.
* So in your context of question in both cases you pass a
* size_t to malloc.
*/
#define NUMBER_THREADS 32
float elapsed_time_ms;
int gpudev = 1;
char *dev_mat_in, *dev_mat_out;
//---------------------------------------------------------------------------
__global__ void kernelTransposeMatrix(const char *mat_in, char *mat_out, unsigned int rows, unsigned int cols){
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idy = threadIdx.y + blockIdx.y * blockDim.y;
if (idx < cols && idy < rows) {
unsigned int pos = idy * cols + idx;
unsigned int trans_pos = idx * rows + idy;
mat_out[trans_pos] = mat_in[pos];
}
} | code for sm_80
Function : _Z21kernelTransposeMatrixPKcPcjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R3, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff037a10 */
/* 0x000fcc00007fe4ff */
/*00e0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fca00078e0205 */
/*0100*/ IADD3 R4, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, RZ, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00ff057a10 */
/* 0x000fca00007fe4ff */
/*0120*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101104 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* PARA CORRERLO:
* $ export LD_LIBRARY_PATH=/usr/local/cuda/lib
* $ export PATH=$PATH:/usr/local/cuda/bin
* $ nvcc -o matrixTrans matrixTrans.cu -O2 -lc -lm
* $ ./matrixTrans n
*/
/*
* UNSIGNED INT --> Tipo de dato para enteros, números sin punto decimal.
* Los enteros sin signo pueden ser tan grandes como 65535
* y tan pequeños como 0.
* Son almacenados como 16 bits de información.
*
* SIZE_T --> is an unsigned integer type guaranteed to support the longest
* object for the platform you use. It is also the result of the
* sizeof operator.sizeof returns the size of the type in bytes.
* So in your context of question in both cases you pass a
* size_t to malloc.
*/
#define NUMBER_THREADS 32
float elapsed_time_ms;
int gpudev = 1;
char *dev_mat_in, *dev_mat_out;
//---------------------------------------------------------------------------
__global__ void kernelTransposeMatrix(const char *mat_in, char *mat_out, unsigned int rows, unsigned int cols){
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idy = threadIdx.y + blockIdx.y * blockDim.y;
if (idx < cols && idy < rows) {
unsigned int pos = idy * cols + idx;
unsigned int trans_pos = idx * rows + idy;
mat_out[trans_pos] = mat_in[pos];
}
} | .file "tmpxft_0009a482_00000000-6_kernelTransposeMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj
.type _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj, @function
_Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernelTransposeMatrixPKcPcjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj, .-_Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj
.globl _Z21kernelTransposeMatrixPKcPcjj
.type _Z21kernelTransposeMatrixPKcPcjj, @function
_Z21kernelTransposeMatrixPKcPcjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21kernelTransposeMatrixPKcPcjj, .-_Z21kernelTransposeMatrixPKcPcjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21kernelTransposeMatrixPKcPcjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernelTransposeMatrixPKcPcjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_mat_out
.bss
.align 8
.type dev_mat_out, @object
.size dev_mat_out, 8
dev_mat_out:
.zero 8
.globl dev_mat_in
.align 8
.type dev_mat_in, @object
.size dev_mat_in, 8
dev_mat_in:
.zero 8
.globl gpudev
.data
.align 4
.type gpudev, @object
.size gpudev, 4
gpudev:
.long 1
.globl elapsed_time_ms
.bss
.align 4
.type elapsed_time_ms, @object
.size elapsed_time_ms, 4
elapsed_time_ms:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* PARA CORRERLO:
* $ export LD_LIBRARY_PATH=/usr/local/cuda/lib
* $ export PATH=$PATH:/usr/local/cuda/bin
* $ nvcc -o matrixTrans matrixTrans.cu -O2 -lc -lm
* $ ./matrixTrans n
*/
/*
* UNSIGNED INT --> Tipo de dato para enteros, números sin punto decimal.
* Los enteros sin signo pueden ser tan grandes como 65535
* y tan pequeños como 0.
* Son almacenados como 16 bits de información.
*
* SIZE_T --> is an unsigned integer type guaranteed to support the longest
* object for the platform you use. It is also the result of the
* sizeof operator.sizeof returns the size of the type in bytes.
* So in your context of question in both cases you pass a
* size_t to malloc.
*/
#define NUMBER_THREADS 32
float elapsed_time_ms;
int gpudev = 1;
char *dev_mat_in, *dev_mat_out;
//---------------------------------------------------------------------------
__global__ void kernelTransposeMatrix(const char *mat_in, char *mat_out, unsigned int rows, unsigned int cols){
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idy = threadIdx.y + blockIdx.y * blockDim.y;
if (idx < cols && idy < rows) {
unsigned int pos = idy * cols + idx;
unsigned int trans_pos = idx * rows + idy;
mat_out[trans_pos] = mat_in[pos];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* PARA CORRERLO:
* $ export LD_LIBRARY_PATH=/usr/local/cuda/lib
* $ export PATH=$PATH:/usr/local/cuda/bin
* $ nvcc -o matrixTrans matrixTrans.cu -O2 -lc -lm
* $ ./matrixTrans n
*/
/*
* UNSIGNED INT --> Tipo de dato para enteros, números sin punto decimal.
* Los enteros sin signo pueden ser tan grandes como 65535
* y tan pequeños como 0.
* Son almacenados como 16 bits de información.
*
* SIZE_T --> is an unsigned integer type guaranteed to support the longest
* object for the platform you use. It is also the result of the
* sizeof operator.sizeof returns the size of the type in bytes.
* So in your context of question in both cases you pass a
* size_t to malloc.
*/
#define NUMBER_THREADS 32
float elapsed_time_ms;
int gpudev = 1;
char *dev_mat_in, *dev_mat_out;
//---------------------------------------------------------------------------
__global__ void kernelTransposeMatrix(const char *mat_in, char *mat_out, unsigned int rows, unsigned int cols){
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idy = threadIdx.y + blockIdx.y * blockDim.y;
if (idx < cols && idy < rows) {
unsigned int pos = idy * cols + idx;
unsigned int trans_pos = idx * rows + idy;
mat_out[trans_pos] = mat_in[pos];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* PARA CORRERLO:
* $ export LD_LIBRARY_PATH=/usr/local/cuda/lib
* $ export PATH=$PATH:/usr/local/cuda/bin
* $ nvcc -o matrixTrans matrixTrans.cu -O2 -lc -lm
* $ ./matrixTrans n
*/
/*
* UNSIGNED INT --> Tipo de dato para enteros, números sin punto decimal.
* Los enteros sin signo pueden ser tan grandes como 65535
* y tan pequeños como 0.
* Son almacenados como 16 bits de información.
*
* SIZE_T --> is an unsigned integer type guaranteed to support the longest
* object for the platform you use. It is also the result of the
* sizeof operator.sizeof returns the size of the type in bytes.
* So in your context of question in both cases you pass a
* size_t to malloc.
*/
#define NUMBER_THREADS 32
float elapsed_time_ms;
int gpudev = 1;
char *dev_mat_in, *dev_mat_out;
//---------------------------------------------------------------------------
__global__ void kernelTransposeMatrix(const char *mat_in, char *mat_out, unsigned int rows, unsigned int cols){
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idy = threadIdx.y + blockIdx.y * blockDim.y;
if (idx < cols && idy < rows) {
unsigned int pos = idy * cols + idx;
unsigned int trans_pos = idx * rows + idy;
mat_out[trans_pos] = mat_in[pos];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21kernelTransposeMatrixPKcPcjj
.globl _Z21kernelTransposeMatrixPKcPcjj
.p2align 8
.type _Z21kernelTransposeMatrixPKcPcjj,@function
_Z21kernelTransposeMatrixPKcPcjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v2, s[0:1]
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_waitcnt vmcnt(0)
global_store_b8 v2, v4, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21kernelTransposeMatrixPKcPcjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21kernelTransposeMatrixPKcPcjj, .Lfunc_end0-_Z21kernelTransposeMatrixPKcPcjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21kernelTransposeMatrixPKcPcjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21kernelTransposeMatrixPKcPcjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* PARA CORRERLO:
* $ export LD_LIBRARY_PATH=/usr/local/cuda/lib
* $ export PATH=$PATH:/usr/local/cuda/bin
* $ nvcc -o matrixTrans matrixTrans.cu -O2 -lc -lm
* $ ./matrixTrans n
*/
/*
* UNSIGNED INT --> Tipo de dato para enteros, números sin punto decimal.
* Los enteros sin signo pueden ser tan grandes como 65535
* y tan pequeños como 0.
* Son almacenados como 16 bits de información.
*
* SIZE_T --> is an unsigned integer type guaranteed to support the longest
* object for the platform you use. It is also the result of the
* sizeof operator.sizeof returns the size of the type in bytes.
* So in your context of question in both cases you pass a
* size_t to malloc.
*/
#define NUMBER_THREADS 32
float elapsed_time_ms;
int gpudev = 1;
char *dev_mat_in, *dev_mat_out;
//---------------------------------------------------------------------------
__global__ void kernelTransposeMatrix(const char *mat_in, char *mat_out, unsigned int rows, unsigned int cols){
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int idy = threadIdx.y + blockIdx.y * blockDim.y;
if (idx < cols && idy < rows) {
unsigned int pos = idy * cols + idx;
unsigned int trans_pos = idx * rows + idy;
mat_out[trans_pos] = mat_in[pos];
}
} | .text
.file "kernelTransposeMatrix.hip"
.globl _Z36__device_stub__kernelTransposeMatrixPKcPcjj # -- Begin function _Z36__device_stub__kernelTransposeMatrixPKcPcjj
.p2align 4, 0x90
.type _Z36__device_stub__kernelTransposeMatrixPKcPcjj,@function
_Z36__device_stub__kernelTransposeMatrixPKcPcjj: # @_Z36__device_stub__kernelTransposeMatrixPKcPcjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernelTransposeMatrixPKcPcjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__kernelTransposeMatrixPKcPcjj, .Lfunc_end0-_Z36__device_stub__kernelTransposeMatrixPKcPcjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernelTransposeMatrixPKcPcjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type elapsed_time_ms,@object # @elapsed_time_ms
.bss
.globl elapsed_time_ms
.p2align 2, 0x0
elapsed_time_ms:
.long 0x00000000 # float 0
.size elapsed_time_ms, 4
.type gpudev,@object # @gpudev
.data
.globl gpudev
.p2align 2, 0x0
gpudev:
.long 1 # 0x1
.size gpudev, 4
.type dev_mat_in,@object # @dev_mat_in
.bss
.globl dev_mat_in
.p2align 3, 0x0
dev_mat_in:
.quad 0
.size dev_mat_in, 8
.type dev_mat_out,@object # @dev_mat_out
.globl dev_mat_out
.p2align 3, 0x0
dev_mat_out:
.quad 0
.size dev_mat_out, 8
.type _Z21kernelTransposeMatrixPKcPcjj,@object # @_Z21kernelTransposeMatrixPKcPcjj
.section .rodata,"a",@progbits
.globl _Z21kernelTransposeMatrixPKcPcjj
.p2align 3, 0x0
_Z21kernelTransposeMatrixPKcPcjj:
.quad _Z36__device_stub__kernelTransposeMatrixPKcPcjj
.size _Z21kernelTransposeMatrixPKcPcjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21kernelTransposeMatrixPKcPcjj"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__kernelTransposeMatrixPKcPcjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21kernelTransposeMatrixPKcPcjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21kernelTransposeMatrixPKcPcjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R3, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff037a10 */
/* 0x000fcc00007fe4ff */
/*00e0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fca00078e0205 */
/*0100*/ IADD3 R4, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, RZ, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00ff057a10 */
/* 0x000fca00007fe4ff */
/*0120*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101104 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21kernelTransposeMatrixPKcPcjj
.globl _Z21kernelTransposeMatrixPKcPcjj
.p2align 8
.type _Z21kernelTransposeMatrixPKcPcjj,@function
_Z21kernelTransposeMatrixPKcPcjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v2, s[0:1]
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_waitcnt vmcnt(0)
global_store_b8 v2, v4, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21kernelTransposeMatrixPKcPcjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21kernelTransposeMatrixPKcPcjj, .Lfunc_end0-_Z21kernelTransposeMatrixPKcPcjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21kernelTransposeMatrixPKcPcjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21kernelTransposeMatrixPKcPcjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009a482_00000000-6_kernelTransposeMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj
.type _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj, @function
_Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernelTransposeMatrixPKcPcjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj, .-_Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj
.globl _Z21kernelTransposeMatrixPKcPcjj
.type _Z21kernelTransposeMatrixPKcPcjj, @function
_Z21kernelTransposeMatrixPKcPcjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21kernelTransposeMatrixPKcPcjjPKcPcjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21kernelTransposeMatrixPKcPcjj, .-_Z21kernelTransposeMatrixPKcPcjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21kernelTransposeMatrixPKcPcjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernelTransposeMatrixPKcPcjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dev_mat_out
.bss
.align 8
.type dev_mat_out, @object
.size dev_mat_out, 8
dev_mat_out:
.zero 8
.globl dev_mat_in
.align 8
.type dev_mat_in, @object
.size dev_mat_in, 8
dev_mat_in:
.zero 8
.globl gpudev
.data
.align 4
.type gpudev, @object
.size gpudev, 4
gpudev:
.long 1
.globl elapsed_time_ms
.bss
.align 4
.type elapsed_time_ms, @object
.size elapsed_time_ms, 4
elapsed_time_ms:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelTransposeMatrix.hip"
.globl _Z36__device_stub__kernelTransposeMatrixPKcPcjj # -- Begin function _Z36__device_stub__kernelTransposeMatrixPKcPcjj
.p2align 4, 0x90
.type _Z36__device_stub__kernelTransposeMatrixPKcPcjj,@function
_Z36__device_stub__kernelTransposeMatrixPKcPcjj: # @_Z36__device_stub__kernelTransposeMatrixPKcPcjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernelTransposeMatrixPKcPcjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__kernelTransposeMatrixPKcPcjj, .Lfunc_end0-_Z36__device_stub__kernelTransposeMatrixPKcPcjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernelTransposeMatrixPKcPcjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type elapsed_time_ms,@object # @elapsed_time_ms
.bss
.globl elapsed_time_ms
.p2align 2, 0x0
elapsed_time_ms:
.long 0x00000000 # float 0
.size elapsed_time_ms, 4
.type gpudev,@object # @gpudev
.data
.globl gpudev
.p2align 2, 0x0
gpudev:
.long 1 # 0x1
.size gpudev, 4
.type dev_mat_in,@object # @dev_mat_in
.bss
.globl dev_mat_in
.p2align 3, 0x0
dev_mat_in:
.quad 0
.size dev_mat_in, 8
.type dev_mat_out,@object # @dev_mat_out
.globl dev_mat_out
.p2align 3, 0x0
dev_mat_out:
.quad 0
.size dev_mat_out, 8
.type _Z21kernelTransposeMatrixPKcPcjj,@object # @_Z21kernelTransposeMatrixPKcPcjj
.section .rodata,"a",@progbits
.globl _Z21kernelTransposeMatrixPKcPcjj
.p2align 3, 0x0
_Z21kernelTransposeMatrixPKcPcjj:
.quad _Z36__device_stub__kernelTransposeMatrixPKcPcjj
.size _Z21kernelTransposeMatrixPKcPcjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21kernelTransposeMatrixPKcPcjj"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__kernelTransposeMatrixPKcPcjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21kernelTransposeMatrixPKcPcjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ const char *STR = "HELLO WORLD!";
//__constant__ const char *STR = "HELLO WORLD!";
const char STR_LENGTH = 12;
__global__ void hello()
{
printf("%c\n", STR[threadIdx.x % STR_LENGTH]);
}
int main(void)
{
int num_threads = STR_LENGTH;
int num_blocks = 2;
dim3 dimBlock (16,16);
dim3 dimGrid(32,32);
hello<<<dimGrid,dimBlock>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fca0007ffe0ff */
/*0050*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0070*/ IMAD.WIDE.U32 R2, R9, -0x55555555, RZ ; /* 0xaaaaaaab09027825 */
/* 0x001fca00078e00ff */
/*0080*/ SHF.R.U32.HI R2, RZ, 0x3, R3 ; /* 0x00000003ff027819 */
/* 0x000fca0000011603 */
/*0090*/ IMAD R9, R2, -0xc, R9 ; /* 0xfffffff402097824 */
/* 0x000fca00078e0209 */
/*00a0*/ IADD3 R8, P0, R4, R9, RZ ; /* 0x0000000904087210 */
/* 0x004fca0007f1e0ff */
/*00b0*/ IMAD.X R9, RZ, RZ, R5, P0 ; /* 0x000000ffff097224 */
/* 0x000fca00000e0605 */
/*00c0*/ LD.E.S8 R0, [R8.64] ; /* 0x0000000408007980 */
/* 0x000ea2000c101300 */
/*00d0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fc600078e00ff */
/*0110*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0130*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0043ec0000100800 */
/*0140*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*0150*/ MOV R11, 0x1c0 ; /* 0x000001c0000b7802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01a0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01b0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ const char *STR = "HELLO WORLD!";
//__constant__ const char *STR = "HELLO WORLD!";
const char STR_LENGTH = 12;
__global__ void hello()
{
printf("%c\n", STR[threadIdx.x % STR_LENGTH]);
}
int main(void)
{
int num_threads = STR_LENGTH;
int num_blocks = 2;
dim3 dimBlock (16,16);
dim3 dimGrid(32,32);
hello<<<dimGrid,dimBlock>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00107328_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.LC1:
.string "STR"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3STR(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3STR
.comm _ZL3STR,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ const char *STR = "HELLO WORLD!";
//__constant__ const char *STR = "HELLO WORLD!";
const char STR_LENGTH = 12;
__global__ void hello()
{
printf("%c\n", STR[threadIdx.x % STR_LENGTH]);
}
int main(void)
{
int num_threads = STR_LENGTH;
int num_blocks = 2;
dim3 dimBlock (16,16);
dim3 dimGrid(32,32);
hello<<<dimGrid,dimBlock>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ const char *STR = "HELLO WORLD!";
//__constant__ const char *STR = "HELLO WORLD!";
const char STR_LENGTH = 12;
__global__ void hello()
{
printf("%c\n", STR[threadIdx.x % STR_LENGTH]);
}
int main(void)
{
int num_threads = STR_LENGTH;
int num_blocks = 2;
dim3 dimBlock (16,16);
dim3 dimGrid(32,32);
hello<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ const char *STR = "HELLO WORLD!";
//__constant__ const char *STR = "HELLO WORLD!";
const char STR_LENGTH = 12;
__global__ void hello()
{
printf("%c\n", STR[threadIdx.x % STR_LENGTH]);
}
int main(void)
{
int num_threads = STR_LENGTH;
int num_blocks = 2;
dim3 dimBlock (16,16);
dim3 dimGrid(32,32);
hello<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $137438953504, %rdi # imm = 0x2000000020
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $STR, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type STR,@object # @STR
.local STR
.comm STR,8,8
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "STR"
.size .L__unnamed_2, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym STR
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00107328_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.LC1:
.string "STR"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3STR(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3STR
.comm _ZL3STR,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $137438953504, %rdi # imm = 0x2000000020
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $STR, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type STR,@object # @STR
.local STR
.comm STR,8,8
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "STR"
.size .L__unnamed_2, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym STR
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static const int WORK_SIZE = 256;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ unsigned int bitreverse(unsigned int number) {
number = ((0xf0f0f0f0 & number) >> 4) | ((0x0f0f0f0f & number) << 4);
number = ((0xcccccccc & number) >> 2) | ((0x33333333 & number) << 2);
number = ((0xaaaaaaaa & number) >> 1) | ((0x55555555 & number) << 1);
return number;
}
/**
* CUDA kernel function that reverses the order of bits in each element of the array.
*/
__global__ void bitreverse(void *data) {
unsigned int *idata = (unsigned int*) data;
idata[threadIdx.x] = bitreverse(idata[threadIdx.x]);
}
__global__ void add(int *a, int *b, int *c)
{
//c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
#define THREADS_PER_BLOCK 1024
int main(int argc, char *argv[])
{
struct timeval t0;
struct timeval t1;
int N = atoi(argv[1]);
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int);
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// Setup input values
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
int i = 0;
for(i = 0; i < N; i++)
{
a[i] = i;//rand() % 100;
b[i] = i;//rand() % 100;
}
gettimeofday(&t0,0);
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
gettimeofday(&t1,0);
double time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
for(i = 0; i < N; i++)
{
printf("%d\n",c[i]);
}
printf("\nTime Spent GPU: %f\n\n",time_spent);
// Cleanup
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
// CPU Part
gettimeofday(&t0,0);
for(i = 0; i < N; i++)
{
c[i] = a[i]+b[i];
}
gettimeofday(&t1,0);
time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
printf("\nTime Spent CPU: %f\n\n",time_spent);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10bitreversePv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IMAD.SHL.U32 R4, R0.reuse, 0x10, RZ ; /* 0x0000001000047824 */
/* 0x044fe200078e00ff */
/*0070*/ LOP3.LUT R0, R0, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f000007812 */
/* 0x000fc800078ec0ff */
/*0080*/ LOP3.LUT R5, R4, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f004057812 */
/* 0x000fc800078ec0ff */
/*0090*/ LEA.HI R0, R0, R5, RZ, 0x1c ; /* 0x0000000500007211 */
/* 0x000fca00078fe0ff */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*00b0*/ LOP3.LUT R0, R0, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc00007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ LOP3.LUT R5, R4, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc04057812 */
/* 0x000fc800078ec0ff */
/*00d0*/ LEA.HI R0, R0, R5, RZ, 0x1e ; /* 0x0000000500007211 */
/* 0x000fca00078ff0ff */
/*00e0*/ IMAD.SHL.U32 R4, R0.reuse, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x040fe200078e00ff */
/*00f0*/ LOP3.LUT R0, R0, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa00007812 */
/* 0x000fc800078ec0ff */
/*0100*/ LOP3.LUT R5, R4, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa04057812 */
/* 0x000fc800078ec0ff */
/*0110*/ LEA.HI R5, R0, R5, RZ, 0x1f ; /* 0x0000000500057211 */
/* 0x000fca00078ff8ff */
/*0120*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static const int WORK_SIZE = 256;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ unsigned int bitreverse(unsigned int number) {
number = ((0xf0f0f0f0 & number) >> 4) | ((0x0f0f0f0f & number) << 4);
number = ((0xcccccccc & number) >> 2) | ((0x33333333 & number) << 2);
number = ((0xaaaaaaaa & number) >> 1) | ((0x55555555 & number) << 1);
return number;
}
/**
* CUDA kernel function that reverses the order of bits in each element of the array.
*/
__global__ void bitreverse(void *data) {
unsigned int *idata = (unsigned int*) data;
idata[threadIdx.x] = bitreverse(idata[threadIdx.x]);
}
__global__ void add(int *a, int *b, int *c)
{
//c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
#define THREADS_PER_BLOCK 1024
int main(int argc, char *argv[])
{
struct timeval t0;
struct timeval t1;
int N = atoi(argv[1]);
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int);
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// Setup input values
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
int i = 0;
for(i = 0; i < N; i++)
{
a[i] = i;//rand() % 100;
b[i] = i;//rand() % 100;
}
gettimeofday(&t0,0);
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
gettimeofday(&t1,0);
double time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
for(i = 0; i < N; i++)
{
printf("%d\n",c[i]);
}
printf("\nTime Spent GPU: %f\n\n",time_spent);
// Cleanup
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
// CPU Part
gettimeofday(&t0,0);
for(i = 0; i < N; i++)
{
c[i] = a[i]+b[i];
}
gettimeofday(&t1,0);
time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
printf("\nTime Spent CPU: %f\n\n",time_spent);
return 0;
} | .file "tmpxft_00119812_00000000-6_B01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10bitreversej
.type _Z10bitreversej, @function
_Z10bitreversej:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10bitreversej, .-_Z10bitreversej
.globl _Z30__device_stub__Z10bitreversePvPv
.type _Z30__device_stub__Z10bitreversePvPv, @function
_Z30__device_stub__Z10bitreversePvPv:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10bitreversePv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z10bitreversePvPv, .-_Z30__device_stub__Z10bitreversePvPv
.globl _Z10bitreversePv
.type _Z10bitreversePv, @function
_Z10bitreversePv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10bitreversePvPv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10bitreversePv, .-_Z10bitreversePv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.LC2:
.string "\nTime Spent GPU: %f\n\n"
.LC3:
.string "\nTime Spent CPU: %f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
leal 0(,%rax,4), %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testl %r14d, %r14d
jle .L22
leal -1(%r14), %ecx
movl $0, %eax
.L23:
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L23
.L22:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
leal 1023(%r14), %eax
testl %r14d, %r14d
cmovns %r14d, %eax
sarl $10, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L24:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
testl %r14d, %r14d
jle .L25
movq %r13, %rbx
leal -1(%r14), %r14d
leaq 4(%r13,%r14,4), %r15
.L26:
movl (%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L26
movsd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %eax
.L27:
movl (%r12,%rax,4), %edx
addl 0(%rbp,%rax,4), %edx
movl %edx, 0(%r13,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %r14, %rdx
jne .L27
.L28:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L24
.L25:
movsd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L28
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPiS_S_"
.LC5:
.string "_Z10bitreversePv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bitreversePv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static const int WORK_SIZE = 256;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ unsigned int bitreverse(unsigned int number) {
number = ((0xf0f0f0f0 & number) >> 4) | ((0x0f0f0f0f & number) << 4);
number = ((0xcccccccc & number) >> 2) | ((0x33333333 & number) << 2);
number = ((0xaaaaaaaa & number) >> 1) | ((0x55555555 & number) << 1);
return number;
}
/**
* CUDA kernel function that reverses the order of bits in each element of the array.
*/
__global__ void bitreverse(void *data) {
unsigned int *idata = (unsigned int*) data;
idata[threadIdx.x] = bitreverse(idata[threadIdx.x]);
}
__global__ void add(int *a, int *b, int *c)
{
//c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
#define THREADS_PER_BLOCK 1024
int main(int argc, char *argv[])
{
struct timeval t0;
struct timeval t1;
int N = atoi(argv[1]);
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int);
// Allocate space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// Setup input values
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
int i = 0;
for(i = 0; i < N; i++)
{
a[i] = i;//rand() % 100;
b[i] = i;//rand() % 100;
}
gettimeofday(&t0,0);
// Copy inputs to device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
// Copy result back to host
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
gettimeofday(&t1,0);
double time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
for(i = 0; i < N; i++)
{
printf("%d\n",c[i]);
}
printf("\nTime Spent GPU: %f\n\n",time_spent);
// Cleanup
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
// CPU Part
gettimeofday(&t0,0);
for(i = 0; i < N; i++)
{
c[i] = a[i]+b[i];
}
gettimeofday(&t1,0);
time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
printf("\nTime Spent CPU: %f\n\n",time_spent);
return 0;
} | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static const int WORK_SIZE = 256;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ unsigned int bitreverse(unsigned int number) {
number = ((0xf0f0f0f0 & number) >> 4) | ((0x0f0f0f0f & number) << 4);
number = ((0xcccccccc & number) >> 2) | ((0x33333333 & number) << 2);
number = ((0xaaaaaaaa & number) >> 1) | ((0x55555555 & number) << 1);
return number;
}
/**
* CUDA kernel function that reverses the order of bits in each element of the array.
*/
__global__ void bitreverse(void *data) {
unsigned int *idata = (unsigned int*) data;
idata[threadIdx.x] = bitreverse(idata[threadIdx.x]);
}
__global__ void add(int *a, int *b, int *c)
{
//c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
#define THREADS_PER_BLOCK 1024
int main(int argc, char *argv[])
{
struct timeval t0;
struct timeval t1;
int N = atoi(argv[1]);
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int);
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// Setup input values
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
int i = 0;
for(i = 0; i < N; i++)
{
a[i] = i;//rand() % 100;
b[i] = i;//rand() % 100;
}
gettimeofday(&t0,0);
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
gettimeofday(&t1,0);
double time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
for(i = 0; i < N; i++)
{
printf("%d\n",c[i]);
}
printf("\nTime Spent GPU: %f\n\n",time_spent);
// Cleanup
hipFree(d_a); hipFree(d_b); hipFree(d_c);
// CPU Part
gettimeofday(&t0,0);
for(i = 0; i < N; i++)
{
c[i] = a[i]+b[i];
}
gettimeofday(&t1,0);
time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
printf("\nTime Spent CPU: %f\n\n",time_spent);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static const int WORK_SIZE = 256;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ unsigned int bitreverse(unsigned int number) {
number = ((0xf0f0f0f0 & number) >> 4) | ((0x0f0f0f0f & number) << 4);
number = ((0xcccccccc & number) >> 2) | ((0x33333333 & number) << 2);
number = ((0xaaaaaaaa & number) >> 1) | ((0x55555555 & number) << 1);
return number;
}
/**
* CUDA kernel function that reverses the order of bits in each element of the array.
*/
__global__ void bitreverse(void *data) {
unsigned int *idata = (unsigned int*) data;
idata[threadIdx.x] = bitreverse(idata[threadIdx.x]);
}
__global__ void add(int *a, int *b, int *c)
{
//c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
#define THREADS_PER_BLOCK 1024
int main(int argc, char *argv[])
{
struct timeval t0;
struct timeval t1;
int N = atoi(argv[1]);
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int);
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// Setup input values
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
int i = 0;
for(i = 0; i < N; i++)
{
a[i] = i;//rand() % 100;
b[i] = i;//rand() % 100;
}
gettimeofday(&t0,0);
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
gettimeofday(&t1,0);
double time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
for(i = 0; i < N; i++)
{
printf("%d\n",c[i]);
}
printf("\nTime Spent GPU: %f\n\n",time_spent);
// Cleanup
hipFree(d_a); hipFree(d_b); hipFree(d_c);
// CPU Part
gettimeofday(&t0,0);
for(i = 0; i < N; i++)
{
c[i] = a[i]+b[i];
}
gettimeofday(&t1,0);
time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
printf("\nTime Spent CPU: %f\n\n",time_spent);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bitreversePv
.globl _Z10bitreversePv
.p2align 8
.type _Z10bitreversePv,@function
_Z10bitreversePv:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v2, 4, v1
v_lshlrev_b32_e32 v1, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0xf0f0f0f, v2, v1
v_lshrrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0x33333333, v2, v1
v_lshrrev_b32_e32 v2, 1, v1
v_lshlrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v1, 0x55555555, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bitreversePv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bitreversePv, .Lfunc_end0-_Z10bitreversePv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addPiS_S_, .Lfunc_end1-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bitreversePv
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10bitreversePv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
static const int WORK_SIZE = 256;
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ unsigned int bitreverse(unsigned int number) {
number = ((0xf0f0f0f0 & number) >> 4) | ((0x0f0f0f0f & number) << 4);
number = ((0xcccccccc & number) >> 2) | ((0x33333333 & number) << 2);
number = ((0xaaaaaaaa & number) >> 1) | ((0x55555555 & number) << 1);
return number;
}
/**
* CUDA kernel function that reverses the order of bits in each element of the array.
*/
__global__ void bitreverse(void *data) {
unsigned int *idata = (unsigned int*) data;
idata[threadIdx.x] = bitreverse(idata[threadIdx.x]);
}
__global__ void add(int *a, int *b, int *c)
{
//c[blockIdx.x] = a[blockIdx.x] + b[blockIdx.x];
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
#define THREADS_PER_BLOCK 1024
int main(int argc, char *argv[])
{
struct timeval t0;
struct timeval t1;
int N = atoi(argv[1]);
int *a, *b, *c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size = N * sizeof(int);
// Allocate space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// Setup input values
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
int i = 0;
for(i = 0; i < N; i++)
{
a[i] = i;//rand() % 100;
b[i] = i;//rand() % 100;
}
gettimeofday(&t0,0);
// Copy inputs to device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
// Copy result back to host
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
gettimeofday(&t1,0);
double time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
for(i = 0; i < N; i++)
{
printf("%d\n",c[i]);
}
printf("\nTime Spent GPU: %f\n\n",time_spent);
// Cleanup
hipFree(d_a); hipFree(d_b); hipFree(d_c);
// CPU Part
gettimeofday(&t0,0);
for(i = 0; i < N; i++)
{
c[i] = a[i]+b[i];
}
gettimeofday(&t1,0);
time_spent = (t1.tv_sec-t0.tv_sec) + (double)(t1.tv_usec-t0.tv_usec)/1000000;
printf("\nTime Spent CPU: %f\n\n",time_spent);
return 0;
} | .text
.file "B01.hip"
.globl _Z25__device_stub__bitreversePv # -- Begin function _Z25__device_stub__bitreversePv
.p2align 4, 0x90
.type _Z25__device_stub__bitreversePv,@function
_Z25__device_stub__bitreversePv: # @_Z25__device_stub__bitreversePv
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10bitreversePv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__bitreversePv, .Lfunc_end0-_Z25__device_stub__bitreversePv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end1-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leal (,%rax,4), %eax
movslq %eax, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%r14,%rcx,4)
movl %ecx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%rbx), %edi
testl %ebx, %ebx
cmovnsl %ebx, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 56(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 64(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB2_8
# %bb.6: # %.lr.ph48.preheader
movl %ebx, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_7: # %.lr.ph48
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r13
jne .LBB2_7
.LBB2_8: # %._crit_edge49
movl $.L.str.1, %edi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebx, %ebx
jle .LBB2_11
# %bb.9: # %.lr.ph52.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_10: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
movl (%r15,%rcx,4), %edx
addl (%r14,%rcx,4), %edx
movl %edx, (%r12,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_10
.LBB2_11: # %._crit_edge53
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 56(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 64(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bitreversePv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bitreversePv,@object # @_Z10bitreversePv
.section .rodata,"a",@progbits
.globl _Z10bitreversePv
.p2align 3, 0x0
_Z10bitreversePv:
.quad _Z25__device_stub__bitreversePv
.size _Z10bitreversePv, 8
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nTime Spent GPU: %f\n\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nTime Spent CPU: %f\n\n"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bitreversePv"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bitreversePv
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bitreversePv
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10bitreversePv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IMAD.SHL.U32 R4, R0.reuse, 0x10, RZ ; /* 0x0000001000047824 */
/* 0x044fe200078e00ff */
/*0070*/ LOP3.LUT R0, R0, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f000007812 */
/* 0x000fc800078ec0ff */
/*0080*/ LOP3.LUT R5, R4, 0xf0f0f0f0, RZ, 0xc0, !PT ; /* 0xf0f0f0f004057812 */
/* 0x000fc800078ec0ff */
/*0090*/ LEA.HI R0, R0, R5, RZ, 0x1c ; /* 0x0000000500007211 */
/* 0x000fca00078fe0ff */
/*00a0*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*00b0*/ LOP3.LUT R0, R0, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc00007812 */
/* 0x000fc800078ec0ff */
/*00c0*/ LOP3.LUT R5, R4, 0xcccccccc, RZ, 0xc0, !PT ; /* 0xcccccccc04057812 */
/* 0x000fc800078ec0ff */
/*00d0*/ LEA.HI R0, R0, R5, RZ, 0x1e ; /* 0x0000000500007211 */
/* 0x000fca00078ff0ff */
/*00e0*/ IMAD.SHL.U32 R4, R0.reuse, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x040fe200078e00ff */
/*00f0*/ LOP3.LUT R0, R0, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa00007812 */
/* 0x000fc800078ec0ff */
/*0100*/ LOP3.LUT R5, R4, 0xaaaaaaaa, RZ, 0xc0, !PT ; /* 0xaaaaaaaa04057812 */
/* 0x000fc800078ec0ff */
/*0110*/ LEA.HI R5, R0, R5, RZ, 0x1f ; /* 0x0000000500057211 */
/* 0x000fca00078ff8ff */
/*0120*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bitreversePv
.globl _Z10bitreversePv
.p2align 8
.type _Z10bitreversePv,@function
_Z10bitreversePv:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v2, 4, v1
v_lshlrev_b32_e32 v1, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0xf0f0f0f, v2, v1
v_lshrrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0x33333333, v2, v1
v_lshrrev_b32_e32 v2, 1, v1
v_lshlrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v1, 0x55555555, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bitreversePv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bitreversePv, .Lfunc_end0-_Z10bitreversePv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addPiS_S_, .Lfunc_end1-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bitreversePv
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10bitreversePv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00119812_00000000-6_B01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10bitreversej
.type _Z10bitreversej, @function
_Z10bitreversej:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10bitreversej, .-_Z10bitreversej
.globl _Z30__device_stub__Z10bitreversePvPv
.type _Z30__device_stub__Z10bitreversePvPv, @function
_Z30__device_stub__Z10bitreversePvPv:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10bitreversePv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z10bitreversePvPv, .-_Z30__device_stub__Z10bitreversePvPv
.globl _Z10bitreversePv
.type _Z10bitreversePv, @function
_Z10bitreversePv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10bitreversePvPv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10bitreversePv, .-_Z10bitreversePv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.LC2:
.string "\nTime Spent GPU: %f\n\n"
.LC3:
.string "\nTime Spent CPU: %f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
leal 0(,%rax,4), %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
testl %r14d, %r14d
jle .L22
leal -1(%r14), %ecx
movl $0, %eax
.L23:
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L23
.L22:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
leal 1023(%r14), %eax
testl %r14d, %r14d
cmovns %r14d, %eax
sarl $10, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L24:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
testl %r14d, %r14d
jle .L25
movq %r13, %rbx
leal -1(%r14), %r14d
leaq 4(%r13,%r14,4), %r15
.L26:
movl (%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L26
movsd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %eax
.L27:
movl (%r12,%rax,4), %edx
addl 0(%rbp,%rax,4), %edx
movl %edx, 0(%r13,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %r14, %rdx
jne .L27
.L28:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L24
.L25:
movsd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L28
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3addPiS_S_"
.LC5:
.string "_Z10bitreversePv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bitreversePv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "B01.hip"
.globl _Z25__device_stub__bitreversePv # -- Begin function _Z25__device_stub__bitreversePv
.p2align 4, 0x90
.type _Z25__device_stub__bitreversePv,@function
_Z25__device_stub__bitreversePv: # @_Z25__device_stub__bitreversePv
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10bitreversePv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__bitreversePv, .Lfunc_end0-_Z25__device_stub__bitreversePv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end1-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leal (,%rax,4), %eax
movslq %eax, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%r14,%rcx,4)
movl %ecx, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%rbx), %edi
testl %ebx, %ebx
cmovnsl %ebx, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 56(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 64(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB2_8
# %bb.6: # %.lr.ph48.preheader
movl %ebx, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_7: # %.lr.ph48
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbp,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r13
jne .LBB2_7
.LBB2_8: # %._crit_edge49
movl $.L.str.1, %edi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebx, %ebx
jle .LBB2_11
# %bb.9: # %.lr.ph52.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_10: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
movl (%r15,%rcx,4), %edx
addl (%r14,%rcx,4), %edx
movl %edx, (%r12,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_10
.LBB2_11: # %._crit_edge53
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 56(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 64(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bitreversePv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bitreversePv,@object # @_Z10bitreversePv
.section .rodata,"a",@progbits
.globl _Z10bitreversePv
.p2align 3, 0x0
_Z10bitreversePv:
.quad _Z25__device_stub__bitreversePv
.size _Z10bitreversePv, 8
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nTime Spent GPU: %f\n\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nTime Spent CPU: %f\n\n"
.size .L.str.2, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bitreversePv"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_2, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bitreversePv
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bitreversePv
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMult(int* m, int* n, int* p, int size)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum;
for (int i = 0;i < size;i++) {
p_sum += m[row * size + i] * n[col * size + i];
}
p[row * size + col] = p_sum;
} | code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fe200078e0203 */
/*00b0*/ @!P0 BRA 0xab0 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x960 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R9, R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0170*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0180*/ @!P0 BRA 0x7e0 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x580 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea6000c1e1900 */
/*0200*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*0210*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100404187981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140402137981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c04041a7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IMAD R15, R14, R15, R13 ; /* 0x0000000f0e0f7224 */
/* 0x004fc600078e020d */
/*0300*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c04020d7981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD R25, R16, R25, R15 ; /* 0x0000001910197224 */
/* 0x008fc600078e020f */
/*0330*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x010fc600078e0219 */
/*0360*/ LDG.E R17, [R2.64+0x24] ; /* 0x0000240402117981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000f22000c1e1900 */
/*0380*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0390*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R21, [R4.64+0x28] ; /* 0x0000280404157981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x000fc600078e0219 */
/*03c0*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R23, [R4.64+0x2c] ; /* 0x00002c0404177981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x000fc600078e0219 */
/*03f0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R19, [R4.64+0x30] ; /* 0x0000300404137981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0420*/ LDG.E R12, [R2.64+0x34] ; /* 0x00003404020c7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003404040b7981 */
/* 0x000f62000c1e1900 */
/*0440*/ IMAD R27, R14, R13, R25 ; /* 0x0000000d0e1b7224 */
/* 0x004fc600078e0219 */
/*0450*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0000a8000c1e1900 */
/*0460*/ LDG.E R13, [R4.64+0x38] ; /* 0x00003804040d7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R25, [R2.64+0x3c] ; /* 0x00003c0402197981 */
/* 0x0000a2000c1e1900 */
/*0480*/ IMAD R15, R16, R15, R27 ; /* 0x0000000f100f7224 */
/* 0x008fc800078e021b */
/*0490*/ IMAD R15, R18, R17, R15 ; /* 0x00000011120f7224 */
/* 0x010fe200078e020f */
/*04a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD R15, R21, R22, R15 ; /* 0x00000016150f7224 */
/* 0x020fe200078e020f */
/*04c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*04d0*/ IMAD R15, R23, R24, R15 ; /* 0x00000018170f7224 */
/* 0x000fe200078e020f */
/*04e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fc6000ff1e03f */
/*04f0*/ IMAD R15, R19, R20, R15 ; /* 0x00000014130f7224 */
/* 0x000fe200078e020f */
/*0500*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe20007f5e0ff */
/*0510*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0520*/ IMAD R11, R11, R12, R15 ; /* 0x0000000c0b0b7224 */
/* 0x000fe200078e020f */
/*0530*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0540*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R13, R13, R14, R11 ; /* 0x0000000e0d0d7224 */
/* 0x004fc800078e020b */
/*0560*/ IMAD R13, R26, R25, R13 ; /* 0x000000191a0d7224 */
/* 0x000fe200078e020d */
/*0570*/ @P1 BRA 0x1d0 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*0580*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x7c0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*05a0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*05b0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*05c0*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x0000a6000c1e1900 */
/*05d0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*05e0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x0000e8000c1e1900 */
/*05f0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R26, [R2.64+0x8] ; /* 0x00000804021a7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R27, [R4.64+0x8] ; /* 0x00000804041b7981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0690*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000168000c1e1900 */
/*06a0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R21, [R4.64+0x1c] ; /* 0x00001c0404157981 */
/* 0x000f68000c1e1900 */
/*06c0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000162000c1e1900 */
/*06d0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*06e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*06f0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fe20007f3e0ff */
/*0720*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc600087fe43f */
/*0730*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*0740*/ IMAD R22, R22, R23, R13 ; /* 0x0000001716167224 */
/* 0x004fc800078e020d */
/*0750*/ IMAD R22, R25, R24, R22 ; /* 0x0000001819167224 */
/* 0x008fc800078e0216 */
/*0760*/ IMAD R22, R27, R26, R22 ; /* 0x0000001a1b167224 */
/* 0x010fc800078e0216 */
/*0770*/ IMAD R18, R18, R19, R22 ; /* 0x0000001312127224 */
/* 0x020fc800078e0216 */
/*0780*/ IMAD R16, R16, R17, R18 ; /* 0x0000001110107224 */
/* 0x000fc800078e0212 */
/*0790*/ IMAD R14, R14, R15, R16 ; /* 0x0000000f0e0e7224 */
/* 0x000fc800078e0210 */
/*07a0*/ IMAD R11, R11, R12, R14 ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e020e */
/*07b0*/ IMAD R13, R21, R20, R11 ; /* 0x00000014150d7224 */
/* 0x000fe400078e020b */
/*07c0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*07d0*/ @!P0 BRA 0x960 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*07e0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*07f0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0810*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee4000c1e1900 */
/*0820*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0830*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000f28000c1e1900 */
/*0870*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000162000c1e1900 */
/*0890*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*08b0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*08c0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ IMAD R11, R12, R11, R13 ; /* 0x0000000b0c0b7224 */
/* 0x004fe200078e020d */
/*08f0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fc60007f3e0ff */
/*0900*/ IMAD R11, R14, R15, R11 ; /* 0x0000000f0e0b7224 */
/* 0x008fc800078e020b */
/*0910*/ IMAD R11, R16, R17, R11 ; /* 0x00000011100b7224 */
/* 0x010fe200078e020b */
/*0920*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x001fe20000000f00 */
/*0930*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0940*/ IMAD R13, R18, R19, R11 ; /* 0x00000013120d7224 */
/* 0x020fe200078e020b */
/*0950*/ @P0 BRA 0x7e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0960*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0970*/ @!P0 BRA 0xab0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0990*/ IMAD R2, R0, c[0x0][0x178], R10 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e020a */
/*09a0*/ IADD3 R4, R7, R10, RZ ; /* 0x0000000a07047210 */
/* 0x000fd00007ffe0ff */
/*09b0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*09c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*09e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*09f0*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x000fe40000000f00 */
/*0a00*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fc80000000f00 */
/*0a10*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0a20*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0a30*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f3e0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a60*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f5e0ff */
/*0a70*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fc600008e0603 */
/*0a80*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0a90*/ IMAD R13, R2, R4, R13 ; /* 0x00000004020d7224 */
/* 0x004fcc00078e020d */
/*0aa0*/ @P0 BRA 0x9f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fd20007ffe0ff */
/*0ad0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0ae0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMult(int* m, int* n, int* p, int size)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum;
for (int i = 0;i < size;i++) {
p_sum += m[row * size + i] * n[col * size + i];
}
p[row * size + col] = p_sum;
} | .file "tmpxft_0014cb54_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMult(int* m, int* n, int* p, int size)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum;
for (int i = 0;i < size;i++) {
p_sum += m[row * size + i] * n[col * size + i];
}
p[row * size + col] = p_sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMult(int* m, int* n, int* p, int size)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum;
for (int i = 0;i < size;i++) {
p_sum += m[row * size + i] * n[col * size + i];
}
p[row * size + col] = p_sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMult(int* m, int* n, int* p, int size)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum;
for (int i = 0;i < size;i++) {
p_sum += m[row * size + i] * n[col * size + i];
}
p[row * size + col] = p_sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
v_mul_lo_u32 v4, v0, s2
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v9, v[5:6], off
global_load_b32 v10, v[3:4], off
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v2, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMult(int* m, int* n, int* p, int size)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int p_sum;
for (int i = 0;i < size;i++) {
p_sum += m[row * size + i] * n[col * size + i];
}
p[row * size + col] = p_sum;
} | .text
.file "matrixMult.hip"
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fe200078e0203 */
/*00b0*/ @!P0 BRA 0xab0 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x960 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R9, R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0170*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0180*/ @!P0 BRA 0x7e0 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x580 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea6000c1e1900 */
/*0200*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*0210*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100404187981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140402137981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c04041a7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IMAD R15, R14, R15, R13 ; /* 0x0000000f0e0f7224 */
/* 0x004fc600078e020d */
/*0300*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c04020d7981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD R25, R16, R25, R15 ; /* 0x0000001910197224 */
/* 0x008fc600078e020f */
/*0330*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x010fc600078e0219 */
/*0360*/ LDG.E R17, [R2.64+0x24] ; /* 0x0000240402117981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000f22000c1e1900 */
/*0380*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0390*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R21, [R4.64+0x28] ; /* 0x0000280404157981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x000fc600078e0219 */
/*03c0*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R23, [R4.64+0x2c] ; /* 0x00002c0404177981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x000fc600078e0219 */
/*03f0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R19, [R4.64+0x30] ; /* 0x0000300404137981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0420*/ LDG.E R12, [R2.64+0x34] ; /* 0x00003404020c7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003404040b7981 */
/* 0x000f62000c1e1900 */
/*0440*/ IMAD R27, R14, R13, R25 ; /* 0x0000000d0e1b7224 */
/* 0x004fc600078e0219 */
/*0450*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0000a8000c1e1900 */
/*0460*/ LDG.E R13, [R4.64+0x38] ; /* 0x00003804040d7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R25, [R2.64+0x3c] ; /* 0x00003c0402197981 */
/* 0x0000a2000c1e1900 */
/*0480*/ IMAD R15, R16, R15, R27 ; /* 0x0000000f100f7224 */
/* 0x008fc800078e021b */
/*0490*/ IMAD R15, R18, R17, R15 ; /* 0x00000011120f7224 */
/* 0x010fe200078e020f */
/*04a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD R15, R21, R22, R15 ; /* 0x00000016150f7224 */
/* 0x020fe200078e020f */
/*04c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*04d0*/ IMAD R15, R23, R24, R15 ; /* 0x00000018170f7224 */
/* 0x000fe200078e020f */
/*04e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fc6000ff1e03f */
/*04f0*/ IMAD R15, R19, R20, R15 ; /* 0x00000014130f7224 */
/* 0x000fe200078e020f */
/*0500*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe20007f5e0ff */
/*0510*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0520*/ IMAD R11, R11, R12, R15 ; /* 0x0000000c0b0b7224 */
/* 0x000fe200078e020f */
/*0530*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0540*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R13, R13, R14, R11 ; /* 0x0000000e0d0d7224 */
/* 0x004fc800078e020b */
/*0560*/ IMAD R13, R26, R25, R13 ; /* 0x000000191a0d7224 */
/* 0x000fe200078e020d */
/*0570*/ @P1 BRA 0x1d0 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*0580*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x7c0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*05a0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*05b0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*05c0*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x0000a6000c1e1900 */
/*05d0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*05e0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x0000e8000c1e1900 */
/*05f0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R26, [R2.64+0x8] ; /* 0x00000804021a7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R27, [R4.64+0x8] ; /* 0x00000804041b7981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0690*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000168000c1e1900 */
/*06a0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R21, [R4.64+0x1c] ; /* 0x00001c0404157981 */
/* 0x000f68000c1e1900 */
/*06c0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000162000c1e1900 */
/*06d0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*06e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*06f0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fe20007f3e0ff */
/*0720*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc600087fe43f */
/*0730*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*0740*/ IMAD R22, R22, R23, R13 ; /* 0x0000001716167224 */
/* 0x004fc800078e020d */
/*0750*/ IMAD R22, R25, R24, R22 ; /* 0x0000001819167224 */
/* 0x008fc800078e0216 */
/*0760*/ IMAD R22, R27, R26, R22 ; /* 0x0000001a1b167224 */
/* 0x010fc800078e0216 */
/*0770*/ IMAD R18, R18, R19, R22 ; /* 0x0000001312127224 */
/* 0x020fc800078e0216 */
/*0780*/ IMAD R16, R16, R17, R18 ; /* 0x0000001110107224 */
/* 0x000fc800078e0212 */
/*0790*/ IMAD R14, R14, R15, R16 ; /* 0x0000000f0e0e7224 */
/* 0x000fc800078e0210 */
/*07a0*/ IMAD R11, R11, R12, R14 ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e020e */
/*07b0*/ IMAD R13, R21, R20, R11 ; /* 0x00000014150d7224 */
/* 0x000fe400078e020b */
/*07c0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*07d0*/ @!P0 BRA 0x960 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*07e0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*07f0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0810*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee4000c1e1900 */
/*0820*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0830*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000f28000c1e1900 */
/*0870*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000162000c1e1900 */
/*0890*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*08b0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*08c0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ IMAD R11, R12, R11, R13 ; /* 0x0000000b0c0b7224 */
/* 0x004fe200078e020d */
/*08f0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fc60007f3e0ff */
/*0900*/ IMAD R11, R14, R15, R11 ; /* 0x0000000f0e0b7224 */
/* 0x008fc800078e020b */
/*0910*/ IMAD R11, R16, R17, R11 ; /* 0x00000011100b7224 */
/* 0x010fe200078e020b */
/*0920*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x001fe20000000f00 */
/*0930*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0940*/ IMAD R13, R18, R19, R11 ; /* 0x00000013120d7224 */
/* 0x020fe200078e020b */
/*0950*/ @P0 BRA 0x7e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0960*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0970*/ @!P0 BRA 0xab0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0990*/ IMAD R2, R0, c[0x0][0x178], R10 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e020a */
/*09a0*/ IADD3 R4, R7, R10, RZ ; /* 0x0000000a07047210 */
/* 0x000fd00007ffe0ff */
/*09b0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*09c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*09e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*09f0*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x000fe40000000f00 */
/*0a00*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fc80000000f00 */
/*0a10*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0a20*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0a30*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f3e0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a60*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f5e0ff */
/*0a70*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fc600008e0603 */
/*0a80*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0a90*/ IMAD R13, R2, R4, R13 ; /* 0x00000004020d7224 */
/* 0x004fcc00078e020d */
/*0aa0*/ @P0 BRA 0x9f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fd20007ffe0ff */
/*0ad0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0ae0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
v_mul_lo_u32 v4, v0, s2
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v9, v[5:6], off
global_load_b32 v10, v[3:4], off
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v2, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014cb54_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMult.hip"
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef __STD_KERNEL_CU__
#define __STD_KERNEL_CU__
#ifndef M_PI
#define M_PI 3.1415926535897
#endif
__device__ int getLargest(double* v) {
if (v[0]>v[1]) {
if (v[0]>v[2]) {
return 0;
}
else {
return 2;
}
}
else {
if (v[1]>v[2]) {
return 1;
}
else {
return 2;
}
}
}
__device__ int CalculateRoots2(double* a, double* r) {
double p = a[1]-a[2]*a[2]/3.0;
double q = 2.0*a[2]*a[2]*a[2]/27.0 - a[2]*a[1]/3.0 + a[0];
double R = q*q/4.0+p*p*p/27.0;
//casus irreducibilis
if (abs(R) < 0.00000000001) {
double u = pow(-q/2.0,1.0/3.0);
r[0] = 2*u - a[2]/3.0;
r[1] = -u - a[2]/3.0;
r[2] = -u - a[2]/3.0;
return 2;
}
if (R < 0) {
double u = sqrt(-p*p*p/27.0);
double cos_w = -q/(2.0*u);
double w = acos(cos_w);
double y[3];
double cubicrt_u = pow(u,1.0/3.0);
y[0] = 2*cubicrt_u*cos(w/3.0);
y[1] = 2*cubicrt_u*cos((w+2.0*M_PI)/3.0);
y[2] = 2*cubicrt_u*cos((w+4.0*M_PI)/3.0);
r[0] = y[0] - a[2]/3.0;
r[1] = y[1] - a[2]/3.0;
r[2] = y[2] - a[2]/3.0;
return 3;
}
return 0; //we had complex eigenvalues
}
__device__ int CalculateRoots(double* a, double* r) {
double c1 = a[1] - a[2]*a[2]/3.;
double c0 = a[0] - a[1]*a[2]/3. + 2./27.*a[2]*a[2]*a[2];
// Make cubic coefficient 4 and linear coefficient +- 3
// by substituting y = z*k and multiplying with 4/k^3
if (c1 == 0) {
if (c0 == 0) r[0] = 0;
else if (c0 > 0) r[0] = -pow(c0, 1./3.);
else r[0] = pow(-c0, 1./3.);
}
else {
bool negc1 = c1 < 0;
double absc1 = negc1 ? -c1 : c1;
double k = sqrt(4./3.*absc1);
double d0 = c0 * 4./(k*k*k);
// Find the first solution
if (negc1) {
if (d0 > 1) r[0] = -cosh(acosh(d0)/3);
else if (d0 > -1) r[0] = -cos(acos(d0)/3);
else r[0] = cosh(acosh(-d0)/3);
}
else {
r[0] = -sinh(asinh(d0)/3);
}
// Transform back
r[0] *= k;
}
r[0] -= a[2]/3;
// Other two solutions
double p = r[0] + a[2];
double q = r[0]*p + a[1];
double discrim = p*p - 4*q;
// if (forceReal && discrim < 0.0) discrim = 0.0;
if (discrim >= 0) {
double root = sqrt(discrim);
r[1] = (-p - root)/2.;
r[2] = (-p + root)/2.;
return 3;
}
else {
double root = sqrt(-discrim);
r[1] = -p/2;
r[2] = root/2.;
return 1;
}
}
__device__ void GetInvariants(double* m, double* pqr) {
pqr[0] = -m[0*3+0]*m[1*3+1]*m[2*3+2]
-m[0*3+1]*m[1*3+2]*m[2*3+0]
-m[0*3+2]*m[1*3+0]*m[2*3+1]
+m[2*3+0]*m[1*3+1]*m[0*3+2]
+m[2*3+1]*m[1*3+2]*m[0*3+0]
+m[2*3+2]*m[1*3+0]*m[0*3+1];
pqr[1] = m[1*3+1]*m[2*3+2] - m[2*3+1]*m[1*3+2]
+ m[0*3+0]*m[1*3+1] - m[1*3+0]*m[0*3+1]
+ m[0*3+0]*m[2*3+2] - m[0*3+2]*m[2*3+0];
pqr[2] = -(m[0*3+0]+m[1*3+1]+m[2*3+2]);
}
__device__ void CalculateCross(double* v1, double* v2, double* res) {
res[0] = v1[1]*v2[2] - v1[2]*v2[1];
res[1] = v1[2]*v2[0] - v1[0]*v2[2];
res[2] = v1[0]*v2[1] - v1[1]*v2[0];
}
__device__ double NormSquared(double* v) {
return (v[0]*v[0]+v[1]*v[1]+v[2]*v[2]);
}
__device__ void CalculateEigenvector(double* m, double lambda, double* evect) {
double norm[3];
double cross[9];
double red[9];
red[0] = m[0]-lambda;
red[1] = m[1];
red[2] = m[2];
red[3] = m[3];
red[4] = m[4]-lambda;
red[5] = m[5];
red[6] = m[6];
red[7] = m[7];
red[8] = m[8]-lambda;
CalculateCross(&red[3], &red[6], &cross[0]);
CalculateCross(&red[6], &red[0], &cross[3]);
CalculateCross(&red[0], &red[3], &cross[6]);
norm[0] = NormSquared(&cross[0]);
norm[1] = NormSquared(&cross[3]);
norm[2] = NormSquared(&cross[6]);
int best = getLargest(norm);
double len = sqrt(norm[best]);
if (len > 0) {
evect[0] = cross[best*3+0] / len;
evect[1] = cross[best*3+1] / len;
evect[2] = cross[best*3+2] / len;
}
else {
evect[0] = 0.0;
evect[1] = 0.0;
evect[2] = 0.0;
}
}
__device__ void swap(double* v1, double* v2) {
double temp = *v1;
*v1 = *v2;
*v2 = temp;
}
__device__ void sortInplace(double* v, int* idx) {
if ( v[0] > v[1] ) swap( &v[0], &v[1] );
if ( v[0] > v[2] ) swap( &v[0], &v[2] );
if ( v[1] > v[2] ) swap( &v[1], &v[2] );
}
__device__ double dotProduct(double* v1, double* v2) {
return (v1[0]*v2[0]+v1[1]*v2[1]+v1[2]*v2[2]);
}
__device__ double findValueOE(double f1, double x1, double f2, double x2, double c){
return ((f2-c)*x1+(c-f1)*x2)/(f2-f1);
}
__device__ void interpolateVector(double g1[3], double g2[3], double t, double* out){
out[0] = (g2[0]-g1[0])*t+g1[0];
out[1] = (g2[1]-g1[1])*t+g1[1];
out[2] = (g2[2]-g1[2])*t+g1[2];
}
typedef double vec3[3];
typedef float fvec3[3];
typedef int ivec3[3];
typedef vec3 mat3[3];
typedef fvec3 fmat3[3];
typedef ivec3 imat3[3];
__device__ inline void vec3sub( vec3 a, vec3 b, vec3 c) { c[0] = a[0] - b[0]; c[1] = a[1] - b[1]; c[2] = a[2] - b[2]; }
__device__ inline double mat3det( mat3 a)
{
return a[0][0]*(a[1][1]*a[2][2] - a[1][2]*a[2][1]) +
a[0][1]*(a[1][2]*a[2][0] - a[1][0]*a[2][2]) +
a[0][2]*(a[1][0]*a[2][1] - a[1][1]*a[2][0]);
}
__device__ inline double vec3det( vec3 a, vec3 b, vec3 c)
{
return a[0]*(b[1]*c[2] - b[2]*c[1]) +
a[1]*(b[2]*c[0] - b[0]*c[2]) +
a[2]*(b[0]*c[1] - b[1]*c[0]);
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __STD_KERNEL_CU__
#define __STD_KERNEL_CU__
#ifndef M_PI
#define M_PI 3.1415926535897
#endif
__device__ int getLargest(double* v) {
if (v[0]>v[1]) {
if (v[0]>v[2]) {
return 0;
}
else {
return 2;
}
}
else {
if (v[1]>v[2]) {
return 1;
}
else {
return 2;
}
}
}
__device__ int CalculateRoots2(double* a, double* r) {
double p = a[1]-a[2]*a[2]/3.0;
double q = 2.0*a[2]*a[2]*a[2]/27.0 - a[2]*a[1]/3.0 + a[0];
double R = q*q/4.0+p*p*p/27.0;
//casus irreducibilis
if (abs(R) < 0.00000000001) {
double u = pow(-q/2.0,1.0/3.0);
r[0] = 2*u - a[2]/3.0;
r[1] = -u - a[2]/3.0;
r[2] = -u - a[2]/3.0;
return 2;
}
if (R < 0) {
double u = sqrt(-p*p*p/27.0);
double cos_w = -q/(2.0*u);
double w = acos(cos_w);
double y[3];
double cubicrt_u = pow(u,1.0/3.0);
y[0] = 2*cubicrt_u*cos(w/3.0);
y[1] = 2*cubicrt_u*cos((w+2.0*M_PI)/3.0);
y[2] = 2*cubicrt_u*cos((w+4.0*M_PI)/3.0);
r[0] = y[0] - a[2]/3.0;
r[1] = y[1] - a[2]/3.0;
r[2] = y[2] - a[2]/3.0;
return 3;
}
return 0; //we had complex eigenvalues
}
__device__ int CalculateRoots(double* a, double* r) {
double c1 = a[1] - a[2]*a[2]/3.;
double c0 = a[0] - a[1]*a[2]/3. + 2./27.*a[2]*a[2]*a[2];
// Make cubic coefficient 4 and linear coefficient +- 3
// by substituting y = z*k and multiplying with 4/k^3
if (c1 == 0) {
if (c0 == 0) r[0] = 0;
else if (c0 > 0) r[0] = -pow(c0, 1./3.);
else r[0] = pow(-c0, 1./3.);
}
else {
bool negc1 = c1 < 0;
double absc1 = negc1 ? -c1 : c1;
double k = sqrt(4./3.*absc1);
double d0 = c0 * 4./(k*k*k);
// Find the first solution
if (negc1) {
if (d0 > 1) r[0] = -cosh(acosh(d0)/3);
else if (d0 > -1) r[0] = -cos(acos(d0)/3);
else r[0] = cosh(acosh(-d0)/3);
}
else {
r[0] = -sinh(asinh(d0)/3);
}
// Transform back
r[0] *= k;
}
r[0] -= a[2]/3;
// Other two solutions
double p = r[0] + a[2];
double q = r[0]*p + a[1];
double discrim = p*p - 4*q;
// if (forceReal && discrim < 0.0) discrim = 0.0;
if (discrim >= 0) {
double root = sqrt(discrim);
r[1] = (-p - root)/2.;
r[2] = (-p + root)/2.;
return 3;
}
else {
double root = sqrt(-discrim);
r[1] = -p/2;
r[2] = root/2.;
return 1;
}
}
__device__ void GetInvariants(double* m, double* pqr) {
pqr[0] = -m[0*3+0]*m[1*3+1]*m[2*3+2]
-m[0*3+1]*m[1*3+2]*m[2*3+0]
-m[0*3+2]*m[1*3+0]*m[2*3+1]
+m[2*3+0]*m[1*3+1]*m[0*3+2]
+m[2*3+1]*m[1*3+2]*m[0*3+0]
+m[2*3+2]*m[1*3+0]*m[0*3+1];
pqr[1] = m[1*3+1]*m[2*3+2] - m[2*3+1]*m[1*3+2]
+ m[0*3+0]*m[1*3+1] - m[1*3+0]*m[0*3+1]
+ m[0*3+0]*m[2*3+2] - m[0*3+2]*m[2*3+0];
pqr[2] = -(m[0*3+0]+m[1*3+1]+m[2*3+2]);
}
__device__ void CalculateCross(double* v1, double* v2, double* res) {
res[0] = v1[1]*v2[2] - v1[2]*v2[1];
res[1] = v1[2]*v2[0] - v1[0]*v2[2];
res[2] = v1[0]*v2[1] - v1[1]*v2[0];
}
__device__ double NormSquared(double* v) {
return (v[0]*v[0]+v[1]*v[1]+v[2]*v[2]);
}
__device__ void CalculateEigenvector(double* m, double lambda, double* evect) {
double norm[3];
double cross[9];
double red[9];
red[0] = m[0]-lambda;
red[1] = m[1];
red[2] = m[2];
red[3] = m[3];
red[4] = m[4]-lambda;
red[5] = m[5];
red[6] = m[6];
red[7] = m[7];
red[8] = m[8]-lambda;
CalculateCross(&red[3], &red[6], &cross[0]);
CalculateCross(&red[6], &red[0], &cross[3]);
CalculateCross(&red[0], &red[3], &cross[6]);
norm[0] = NormSquared(&cross[0]);
norm[1] = NormSquared(&cross[3]);
norm[2] = NormSquared(&cross[6]);
int best = getLargest(norm);
double len = sqrt(norm[best]);
if (len > 0) {
evect[0] = cross[best*3+0] / len;
evect[1] = cross[best*3+1] / len;
evect[2] = cross[best*3+2] / len;
}
else {
evect[0] = 0.0;
evect[1] = 0.0;
evect[2] = 0.0;
}
}
__device__ void swap(double* v1, double* v2) {
double temp = *v1;
*v1 = *v2;
*v2 = temp;
}
__device__ void sortInplace(double* v, int* idx) {
if ( v[0] > v[1] ) swap( &v[0], &v[1] );
if ( v[0] > v[2] ) swap( &v[0], &v[2] );
if ( v[1] > v[2] ) swap( &v[1], &v[2] );
}
__device__ double dotProduct(double* v1, double* v2) {
return (v1[0]*v2[0]+v1[1]*v2[1]+v1[2]*v2[2]);
}
__device__ double findValueOE(double f1, double x1, double f2, double x2, double c){
return ((f2-c)*x1+(c-f1)*x2)/(f2-f1);
}
__device__ void interpolateVector(double g1[3], double g2[3], double t, double* out){
out[0] = (g2[0]-g1[0])*t+g1[0];
out[1] = (g2[1]-g1[1])*t+g1[1];
out[2] = (g2[2]-g1[2])*t+g1[2];
}
typedef double vec3[3];
typedef float fvec3[3];
typedef int ivec3[3];
typedef vec3 mat3[3];
typedef fvec3 fmat3[3];
typedef ivec3 imat3[3];
__device__ inline void vec3sub( vec3 a, vec3 b, vec3 c) { c[0] = a[0] - b[0]; c[1] = a[1] - b[1]; c[2] = a[2] - b[2]; }
__device__ inline double mat3det( mat3 a)
{
return a[0][0]*(a[1][1]*a[2][2] - a[1][2]*a[2][1]) +
a[0][1]*(a[1][2]*a[2][0] - a[1][0]*a[2][2]) +
a[0][2]*(a[1][0]*a[2][1] - a[1][1]*a[2][0]);
}
__device__ inline double vec3det( vec3 a, vec3 b, vec3 c)
{
return a[0]*(b[1]*c[2] - b[2]*c[1]) +
a[1]*(b[2]*c[0] - b[0]*c[2]) +
a[2]*(b[0]*c[1] - b[1]*c[0]);
}
#endif | .file "tmpxft_0006dabc_00000000-6_std_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2044:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2044:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getLargestPd
.type _Z10getLargestPd, @function
_Z10getLargestPd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getLargestPd, .-_Z10getLargestPd
.globl _Z15CalculateRoots2PdS_
.type _Z15CalculateRoots2PdS_, @function
_Z15CalculateRoots2PdS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z15CalculateRoots2PdS_, .-_Z15CalculateRoots2PdS_
.globl _Z14CalculateRootsPdS_
.type _Z14CalculateRootsPdS_, @function
_Z14CalculateRootsPdS_:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z14CalculateRootsPdS_, .-_Z14CalculateRootsPdS_
.globl _Z13GetInvariantsPdS_
.type _Z13GetInvariantsPdS_, @function
_Z13GetInvariantsPdS_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z13GetInvariantsPdS_, .-_Z13GetInvariantsPdS_
.globl _Z14CalculateCrossPdS_S_
.type _Z14CalculateCrossPdS_S_, @function
_Z14CalculateCrossPdS_S_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z14CalculateCrossPdS_S_, .-_Z14CalculateCrossPdS_S_
.globl _Z11NormSquaredPd
.type _Z11NormSquaredPd, @function
_Z11NormSquaredPd:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z11NormSquaredPd, .-_Z11NormSquaredPd
.globl _Z20CalculateEigenvectorPddS_
.type _Z20CalculateEigenvectorPddS_, @function
_Z20CalculateEigenvectorPddS_:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z20CalculateEigenvectorPddS_, .-_Z20CalculateEigenvectorPddS_
.globl _Z4swapPdS_
.type _Z4swapPdS_, @function
_Z4swapPdS_:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z4swapPdS_, .-_Z4swapPdS_
.globl _Z11sortInplacePdPi
.type _Z11sortInplacePdPi, @function
_Z11sortInplacePdPi:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z11sortInplacePdPi, .-_Z11sortInplacePdPi
.globl _Z10dotProductPdS_
.type _Z10dotProductPdS_, @function
_Z10dotProductPdS_:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z10dotProductPdS_, .-_Z10dotProductPdS_
.globl _Z11findValueOEddddd
.type _Z11findValueOEddddd, @function
_Z11findValueOEddddd:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z11findValueOEddddd, .-_Z11findValueOEddddd
.globl _Z17interpolateVectorPdS_dS_
.type _Z17interpolateVectorPdS_dS_, @function
_Z17interpolateVectorPdS_dS_:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Z17interpolateVectorPdS_dS_, .-_Z17interpolateVectorPdS_dS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __STD_KERNEL_CU__
#define __STD_KERNEL_CU__
#ifndef M_PI
#define M_PI 3.1415926535897
#endif
__device__ int getLargest(double* v) {
if (v[0]>v[1]) {
if (v[0]>v[2]) {
return 0;
}
else {
return 2;
}
}
else {
if (v[1]>v[2]) {
return 1;
}
else {
return 2;
}
}
}
__device__ int CalculateRoots2(double* a, double* r) {
double p = a[1]-a[2]*a[2]/3.0;
double q = 2.0*a[2]*a[2]*a[2]/27.0 - a[2]*a[1]/3.0 + a[0];
double R = q*q/4.0+p*p*p/27.0;
//casus irreducibilis
if (abs(R) < 0.00000000001) {
double u = pow(-q/2.0,1.0/3.0);
r[0] = 2*u - a[2]/3.0;
r[1] = -u - a[2]/3.0;
r[2] = -u - a[2]/3.0;
return 2;
}
if (R < 0) {
double u = sqrt(-p*p*p/27.0);
double cos_w = -q/(2.0*u);
double w = acos(cos_w);
double y[3];
double cubicrt_u = pow(u,1.0/3.0);
y[0] = 2*cubicrt_u*cos(w/3.0);
y[1] = 2*cubicrt_u*cos((w+2.0*M_PI)/3.0);
y[2] = 2*cubicrt_u*cos((w+4.0*M_PI)/3.0);
r[0] = y[0] - a[2]/3.0;
r[1] = y[1] - a[2]/3.0;
r[2] = y[2] - a[2]/3.0;
return 3;
}
return 0; //we had complex eigenvalues
}
__device__ int CalculateRoots(double* a, double* r) {
double c1 = a[1] - a[2]*a[2]/3.;
double c0 = a[0] - a[1]*a[2]/3. + 2./27.*a[2]*a[2]*a[2];
// Make cubic coefficient 4 and linear coefficient +- 3
// by substituting y = z*k and multiplying with 4/k^3
if (c1 == 0) {
if (c0 == 0) r[0] = 0;
else if (c0 > 0) r[0] = -pow(c0, 1./3.);
else r[0] = pow(-c0, 1./3.);
}
else {
bool negc1 = c1 < 0;
double absc1 = negc1 ? -c1 : c1;
double k = sqrt(4./3.*absc1);
double d0 = c0 * 4./(k*k*k);
// Find the first solution
if (negc1) {
if (d0 > 1) r[0] = -cosh(acosh(d0)/3);
else if (d0 > -1) r[0] = -cos(acos(d0)/3);
else r[0] = cosh(acosh(-d0)/3);
}
else {
r[0] = -sinh(asinh(d0)/3);
}
// Transform back
r[0] *= k;
}
r[0] -= a[2]/3;
// Other two solutions
double p = r[0] + a[2];
double q = r[0]*p + a[1];
double discrim = p*p - 4*q;
// if (forceReal && discrim < 0.0) discrim = 0.0;
if (discrim >= 0) {
double root = sqrt(discrim);
r[1] = (-p - root)/2.;
r[2] = (-p + root)/2.;
return 3;
}
else {
double root = sqrt(-discrim);
r[1] = -p/2;
r[2] = root/2.;
return 1;
}
}
__device__ void GetInvariants(double* m, double* pqr) {
pqr[0] = -m[0*3+0]*m[1*3+1]*m[2*3+2]
-m[0*3+1]*m[1*3+2]*m[2*3+0]
-m[0*3+2]*m[1*3+0]*m[2*3+1]
+m[2*3+0]*m[1*3+1]*m[0*3+2]
+m[2*3+1]*m[1*3+2]*m[0*3+0]
+m[2*3+2]*m[1*3+0]*m[0*3+1];
pqr[1] = m[1*3+1]*m[2*3+2] - m[2*3+1]*m[1*3+2]
+ m[0*3+0]*m[1*3+1] - m[1*3+0]*m[0*3+1]
+ m[0*3+0]*m[2*3+2] - m[0*3+2]*m[2*3+0];
pqr[2] = -(m[0*3+0]+m[1*3+1]+m[2*3+2]);
}
__device__ void CalculateCross(double* v1, double* v2, double* res) {
res[0] = v1[1]*v2[2] - v1[2]*v2[1];
res[1] = v1[2]*v2[0] - v1[0]*v2[2];
res[2] = v1[0]*v2[1] - v1[1]*v2[0];
}
__device__ double NormSquared(double* v) {
return (v[0]*v[0]+v[1]*v[1]+v[2]*v[2]);
}
__device__ void CalculateEigenvector(double* m, double lambda, double* evect) {
double norm[3];
double cross[9];
double red[9];
red[0] = m[0]-lambda;
red[1] = m[1];
red[2] = m[2];
red[3] = m[3];
red[4] = m[4]-lambda;
red[5] = m[5];
red[6] = m[6];
red[7] = m[7];
red[8] = m[8]-lambda;
CalculateCross(&red[3], &red[6], &cross[0]);
CalculateCross(&red[6], &red[0], &cross[3]);
CalculateCross(&red[0], &red[3], &cross[6]);
norm[0] = NormSquared(&cross[0]);
norm[1] = NormSquared(&cross[3]);
norm[2] = NormSquared(&cross[6]);
int best = getLargest(norm);
double len = sqrt(norm[best]);
if (len > 0) {
evect[0] = cross[best*3+0] / len;
evect[1] = cross[best*3+1] / len;
evect[2] = cross[best*3+2] / len;
}
else {
evect[0] = 0.0;
evect[1] = 0.0;
evect[2] = 0.0;
}
}
__device__ void swap(double* v1, double* v2) {
double temp = *v1;
*v1 = *v2;
*v2 = temp;
}
__device__ void sortInplace(double* v, int* idx) {
if ( v[0] > v[1] ) swap( &v[0], &v[1] );
if ( v[0] > v[2] ) swap( &v[0], &v[2] );
if ( v[1] > v[2] ) swap( &v[1], &v[2] );
}
__device__ double dotProduct(double* v1, double* v2) {
return (v1[0]*v2[0]+v1[1]*v2[1]+v1[2]*v2[2]);
}
__device__ double findValueOE(double f1, double x1, double f2, double x2, double c){
return ((f2-c)*x1+(c-f1)*x2)/(f2-f1);
}
__device__ void interpolateVector(double g1[3], double g2[3], double t, double* out){
out[0] = (g2[0]-g1[0])*t+g1[0];
out[1] = (g2[1]-g1[1])*t+g1[1];
out[2] = (g2[2]-g1[2])*t+g1[2];
}
typedef double vec3[3];
typedef float fvec3[3];
typedef int ivec3[3];
typedef vec3 mat3[3];
typedef fvec3 fmat3[3];
typedef ivec3 imat3[3];
__device__ inline void vec3sub( vec3 a, vec3 b, vec3 c) { c[0] = a[0] - b[0]; c[1] = a[1] - b[1]; c[2] = a[2] - b[2]; }
__device__ inline double mat3det( mat3 a)
{
return a[0][0]*(a[1][1]*a[2][2] - a[1][2]*a[2][1]) +
a[0][1]*(a[1][2]*a[2][0] - a[1][0]*a[2][2]) +
a[0][2]*(a[1][0]*a[2][1] - a[1][1]*a[2][0]);
}
__device__ inline double vec3det( vec3 a, vec3 b, vec3 c)
{
return a[0]*(b[1]*c[2] - b[2]*c[1]) +
a[1]*(b[2]*c[0] - b[0]*c[2]) +
a[2]*(b[0]*c[1] - b[1]*c[0]);
}
#endif | #ifndef __STD_KERNEL_CU__
#define __STD_KERNEL_CU__
#ifndef M_PI
#define M_PI 3.1415926535897
#endif
__device__ int getLargest(double* v) {
if (v[0]>v[1]) {
if (v[0]>v[2]) {
return 0;
}
else {
return 2;
}
}
else {
if (v[1]>v[2]) {
return 1;
}
else {
return 2;
}
}
}
__device__ int CalculateRoots2(double* a, double* r) {
double p = a[1]-a[2]*a[2]/3.0;
double q = 2.0*a[2]*a[2]*a[2]/27.0 - a[2]*a[1]/3.0 + a[0];
double R = q*q/4.0+p*p*p/27.0;
//casus irreducibilis
if (abs(R) < 0.00000000001) {
double u = pow(-q/2.0,1.0/3.0);
r[0] = 2*u - a[2]/3.0;
r[1] = -u - a[2]/3.0;
r[2] = -u - a[2]/3.0;
return 2;
}
if (R < 0) {
double u = sqrt(-p*p*p/27.0);
double cos_w = -q/(2.0*u);
double w = acos(cos_w);
double y[3];
double cubicrt_u = pow(u,1.0/3.0);
y[0] = 2*cubicrt_u*cos(w/3.0);
y[1] = 2*cubicrt_u*cos((w+2.0*M_PI)/3.0);
y[2] = 2*cubicrt_u*cos((w+4.0*M_PI)/3.0);
r[0] = y[0] - a[2]/3.0;
r[1] = y[1] - a[2]/3.0;
r[2] = y[2] - a[2]/3.0;
return 3;
}
return 0; //we had complex eigenvalues
}
__device__ int CalculateRoots(double* a, double* r) {
double c1 = a[1] - a[2]*a[2]/3.;
double c0 = a[0] - a[1]*a[2]/3. + 2./27.*a[2]*a[2]*a[2];
// Make cubic coefficient 4 and linear coefficient +- 3
// by substituting y = z*k and multiplying with 4/k^3
if (c1 == 0) {
if (c0 == 0) r[0] = 0;
else if (c0 > 0) r[0] = -pow(c0, 1./3.);
else r[0] = pow(-c0, 1./3.);
}
else {
bool negc1 = c1 < 0;
double absc1 = negc1 ? -c1 : c1;
double k = sqrt(4./3.*absc1);
double d0 = c0 * 4./(k*k*k);
// Find the first solution
if (negc1) {
if (d0 > 1) r[0] = -cosh(acosh(d0)/3);
else if (d0 > -1) r[0] = -cos(acos(d0)/3);
else r[0] = cosh(acosh(-d0)/3);
}
else {
r[0] = -sinh(asinh(d0)/3);
}
// Transform back
r[0] *= k;
}
r[0] -= a[2]/3;
// Other two solutions
double p = r[0] + a[2];
double q = r[0]*p + a[1];
double discrim = p*p - 4*q;
// if (forceReal && discrim < 0.0) discrim = 0.0;
if (discrim >= 0) {
double root = sqrt(discrim);
r[1] = (-p - root)/2.;
r[2] = (-p + root)/2.;
return 3;
}
else {
double root = sqrt(-discrim);
r[1] = -p/2;
r[2] = root/2.;
return 1;
}
}
__device__ void GetInvariants(double* m, double* pqr) {
pqr[0] = -m[0*3+0]*m[1*3+1]*m[2*3+2]
-m[0*3+1]*m[1*3+2]*m[2*3+0]
-m[0*3+2]*m[1*3+0]*m[2*3+1]
+m[2*3+0]*m[1*3+1]*m[0*3+2]
+m[2*3+1]*m[1*3+2]*m[0*3+0]
+m[2*3+2]*m[1*3+0]*m[0*3+1];
pqr[1] = m[1*3+1]*m[2*3+2] - m[2*3+1]*m[1*3+2]
+ m[0*3+0]*m[1*3+1] - m[1*3+0]*m[0*3+1]
+ m[0*3+0]*m[2*3+2] - m[0*3+2]*m[2*3+0];
pqr[2] = -(m[0*3+0]+m[1*3+1]+m[2*3+2]);
}
__device__ void CalculateCross(double* v1, double* v2, double* res) {
res[0] = v1[1]*v2[2] - v1[2]*v2[1];
res[1] = v1[2]*v2[0] - v1[0]*v2[2];
res[2] = v1[0]*v2[1] - v1[1]*v2[0];
}
__device__ double NormSquared(double* v) {
return (v[0]*v[0]+v[1]*v[1]+v[2]*v[2]);
}
__device__ void CalculateEigenvector(double* m, double lambda, double* evect) {
double norm[3];
double cross[9];
double red[9];
red[0] = m[0]-lambda;
red[1] = m[1];
red[2] = m[2];
red[3] = m[3];
red[4] = m[4]-lambda;
red[5] = m[5];
red[6] = m[6];
red[7] = m[7];
red[8] = m[8]-lambda;
CalculateCross(&red[3], &red[6], &cross[0]);
CalculateCross(&red[6], &red[0], &cross[3]);
CalculateCross(&red[0], &red[3], &cross[6]);
norm[0] = NormSquared(&cross[0]);
norm[1] = NormSquared(&cross[3]);
norm[2] = NormSquared(&cross[6]);
int best = getLargest(norm);
double len = sqrt(norm[best]);
if (len > 0) {
evect[0] = cross[best*3+0] / len;
evect[1] = cross[best*3+1] / len;
evect[2] = cross[best*3+2] / len;
}
else {
evect[0] = 0.0;
evect[1] = 0.0;
evect[2] = 0.0;
}
}
__device__ void swap(double* v1, double* v2) {
double temp = *v1;
*v1 = *v2;
*v2 = temp;
}
__device__ void sortInplace(double* v, int* idx) {
if ( v[0] > v[1] ) swap( &v[0], &v[1] );
if ( v[0] > v[2] ) swap( &v[0], &v[2] );
if ( v[1] > v[2] ) swap( &v[1], &v[2] );
}
__device__ double dotProduct(double* v1, double* v2) {
return (v1[0]*v2[0]+v1[1]*v2[1]+v1[2]*v2[2]);
}
__device__ double findValueOE(double f1, double x1, double f2, double x2, double c){
return ((f2-c)*x1+(c-f1)*x2)/(f2-f1);
}
__device__ void interpolateVector(double g1[3], double g2[3], double t, double* out){
out[0] = (g2[0]-g1[0])*t+g1[0];
out[1] = (g2[1]-g1[1])*t+g1[1];
out[2] = (g2[2]-g1[2])*t+g1[2];
}
typedef double vec3[3];
typedef float fvec3[3];
typedef int ivec3[3];
typedef vec3 mat3[3];
typedef fvec3 fmat3[3];
typedef ivec3 imat3[3];
__device__ inline void vec3sub( vec3 a, vec3 b, vec3 c) { c[0] = a[0] - b[0]; c[1] = a[1] - b[1]; c[2] = a[2] - b[2]; }
__device__ inline double mat3det( mat3 a)
{
return a[0][0]*(a[1][1]*a[2][2] - a[1][2]*a[2][1]) +
a[0][1]*(a[1][2]*a[2][0] - a[1][0]*a[2][2]) +
a[0][2]*(a[1][0]*a[2][1] - a[1][1]*a[2][0]);
}
__device__ inline double vec3det( vec3 a, vec3 b, vec3 c)
{
return a[0]*(b[1]*c[2] - b[2]*c[1]) +
a[1]*(b[2]*c[0] - b[0]*c[2]) +
a[2]*(b[0]*c[1] - b[1]*c[0]);
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __STD_KERNEL_CU__
#define __STD_KERNEL_CU__
#ifndef M_PI
#define M_PI 3.1415926535897
#endif
__device__ int getLargest(double* v) {
if (v[0]>v[1]) {
if (v[0]>v[2]) {
return 0;
}
else {
return 2;
}
}
else {
if (v[1]>v[2]) {
return 1;
}
else {
return 2;
}
}
}
__device__ int CalculateRoots2(double* a, double* r) {
double p = a[1]-a[2]*a[2]/3.0;
double q = 2.0*a[2]*a[2]*a[2]/27.0 - a[2]*a[1]/3.0 + a[0];
double R = q*q/4.0+p*p*p/27.0;
//casus irreducibilis
if (abs(R) < 0.00000000001) {
double u = pow(-q/2.0,1.0/3.0);
r[0] = 2*u - a[2]/3.0;
r[1] = -u - a[2]/3.0;
r[2] = -u - a[2]/3.0;
return 2;
}
if (R < 0) {
double u = sqrt(-p*p*p/27.0);
double cos_w = -q/(2.0*u);
double w = acos(cos_w);
double y[3];
double cubicrt_u = pow(u,1.0/3.0);
y[0] = 2*cubicrt_u*cos(w/3.0);
y[1] = 2*cubicrt_u*cos((w+2.0*M_PI)/3.0);
y[2] = 2*cubicrt_u*cos((w+4.0*M_PI)/3.0);
r[0] = y[0] - a[2]/3.0;
r[1] = y[1] - a[2]/3.0;
r[2] = y[2] - a[2]/3.0;
return 3;
}
return 0; //we had complex eigenvalues
}
__device__ int CalculateRoots(double* a, double* r) {
double c1 = a[1] - a[2]*a[2]/3.;
double c0 = a[0] - a[1]*a[2]/3. + 2./27.*a[2]*a[2]*a[2];
// Make cubic coefficient 4 and linear coefficient +- 3
// by substituting y = z*k and multiplying with 4/k^3
if (c1 == 0) {
if (c0 == 0) r[0] = 0;
else if (c0 > 0) r[0] = -pow(c0, 1./3.);
else r[0] = pow(-c0, 1./3.);
}
else {
bool negc1 = c1 < 0;
double absc1 = negc1 ? -c1 : c1;
double k = sqrt(4./3.*absc1);
double d0 = c0 * 4./(k*k*k);
// Find the first solution
if (negc1) {
if (d0 > 1) r[0] = -cosh(acosh(d0)/3);
else if (d0 > -1) r[0] = -cos(acos(d0)/3);
else r[0] = cosh(acosh(-d0)/3);
}
else {
r[0] = -sinh(asinh(d0)/3);
}
// Transform back
r[0] *= k;
}
r[0] -= a[2]/3;
// Other two solutions
double p = r[0] + a[2];
double q = r[0]*p + a[1];
double discrim = p*p - 4*q;
// if (forceReal && discrim < 0.0) discrim = 0.0;
if (discrim >= 0) {
double root = sqrt(discrim);
r[1] = (-p - root)/2.;
r[2] = (-p + root)/2.;
return 3;
}
else {
double root = sqrt(-discrim);
r[1] = -p/2;
r[2] = root/2.;
return 1;
}
}
__device__ void GetInvariants(double* m, double* pqr) {
pqr[0] = -m[0*3+0]*m[1*3+1]*m[2*3+2]
-m[0*3+1]*m[1*3+2]*m[2*3+0]
-m[0*3+2]*m[1*3+0]*m[2*3+1]
+m[2*3+0]*m[1*3+1]*m[0*3+2]
+m[2*3+1]*m[1*3+2]*m[0*3+0]
+m[2*3+2]*m[1*3+0]*m[0*3+1];
pqr[1] = m[1*3+1]*m[2*3+2] - m[2*3+1]*m[1*3+2]
+ m[0*3+0]*m[1*3+1] - m[1*3+0]*m[0*3+1]
+ m[0*3+0]*m[2*3+2] - m[0*3+2]*m[2*3+0];
pqr[2] = -(m[0*3+0]+m[1*3+1]+m[2*3+2]);
}
__device__ void CalculateCross(double* v1, double* v2, double* res) {
res[0] = v1[1]*v2[2] - v1[2]*v2[1];
res[1] = v1[2]*v2[0] - v1[0]*v2[2];
res[2] = v1[0]*v2[1] - v1[1]*v2[0];
}
__device__ double NormSquared(double* v) {
return (v[0]*v[0]+v[1]*v[1]+v[2]*v[2]);
}
__device__ void CalculateEigenvector(double* m, double lambda, double* evect) {
double norm[3];
double cross[9];
double red[9];
red[0] = m[0]-lambda;
red[1] = m[1];
red[2] = m[2];
red[3] = m[3];
red[4] = m[4]-lambda;
red[5] = m[5];
red[6] = m[6];
red[7] = m[7];
red[8] = m[8]-lambda;
CalculateCross(&red[3], &red[6], &cross[0]);
CalculateCross(&red[6], &red[0], &cross[3]);
CalculateCross(&red[0], &red[3], &cross[6]);
norm[0] = NormSquared(&cross[0]);
norm[1] = NormSquared(&cross[3]);
norm[2] = NormSquared(&cross[6]);
int best = getLargest(norm);
double len = sqrt(norm[best]);
if (len > 0) {
evect[0] = cross[best*3+0] / len;
evect[1] = cross[best*3+1] / len;
evect[2] = cross[best*3+2] / len;
}
else {
evect[0] = 0.0;
evect[1] = 0.0;
evect[2] = 0.0;
}
}
__device__ void swap(double* v1, double* v2) {
double temp = *v1;
*v1 = *v2;
*v2 = temp;
}
__device__ void sortInplace(double* v, int* idx) {
if ( v[0] > v[1] ) swap( &v[0], &v[1] );
if ( v[0] > v[2] ) swap( &v[0], &v[2] );
if ( v[1] > v[2] ) swap( &v[1], &v[2] );
}
__device__ double dotProduct(double* v1, double* v2) {
return (v1[0]*v2[0]+v1[1]*v2[1]+v1[2]*v2[2]);
}
__device__ double findValueOE(double f1, double x1, double f2, double x2, double c){
return ((f2-c)*x1+(c-f1)*x2)/(f2-f1);
}
__device__ void interpolateVector(double g1[3], double g2[3], double t, double* out){
out[0] = (g2[0]-g1[0])*t+g1[0];
out[1] = (g2[1]-g1[1])*t+g1[1];
out[2] = (g2[2]-g1[2])*t+g1[2];
}
typedef double vec3[3];
typedef float fvec3[3];
typedef int ivec3[3];
typedef vec3 mat3[3];
typedef fvec3 fmat3[3];
typedef ivec3 imat3[3];
__device__ inline void vec3sub( vec3 a, vec3 b, vec3 c) { c[0] = a[0] - b[0]; c[1] = a[1] - b[1]; c[2] = a[2] - b[2]; }
__device__ inline double mat3det( mat3 a)
{
return a[0][0]*(a[1][1]*a[2][2] - a[1][2]*a[2][1]) +
a[0][1]*(a[1][2]*a[2][0] - a[1][0]*a[2][2]) +
a[0][2]*(a[1][0]*a[2][1] - a[1][1]*a[2][0]);
}
__device__ inline double vec3det( vec3 a, vec3 b, vec3 c)
{
return a[0]*(b[1]*c[2] - b[2]*c[1]) +
a[1]*(b[2]*c[0] - b[0]*c[2]) +
a[2]*(b[0]*c[1] - b[1]*c[0]);
}
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __STD_KERNEL_CU__
#define __STD_KERNEL_CU__
#ifndef M_PI
#define M_PI 3.1415926535897
#endif
__device__ int getLargest(double* v) {
if (v[0]>v[1]) {
if (v[0]>v[2]) {
return 0;
}
else {
return 2;
}
}
else {
if (v[1]>v[2]) {
return 1;
}
else {
return 2;
}
}
}
__device__ int CalculateRoots2(double* a, double* r) {
double p = a[1]-a[2]*a[2]/3.0;
double q = 2.0*a[2]*a[2]*a[2]/27.0 - a[2]*a[1]/3.0 + a[0];
double R = q*q/4.0+p*p*p/27.0;
//casus irreducibilis
if (abs(R) < 0.00000000001) {
double u = pow(-q/2.0,1.0/3.0);
r[0] = 2*u - a[2]/3.0;
r[1] = -u - a[2]/3.0;
r[2] = -u - a[2]/3.0;
return 2;
}
if (R < 0) {
double u = sqrt(-p*p*p/27.0);
double cos_w = -q/(2.0*u);
double w = acos(cos_w);
double y[3];
double cubicrt_u = pow(u,1.0/3.0);
y[0] = 2*cubicrt_u*cos(w/3.0);
y[1] = 2*cubicrt_u*cos((w+2.0*M_PI)/3.0);
y[2] = 2*cubicrt_u*cos((w+4.0*M_PI)/3.0);
r[0] = y[0] - a[2]/3.0;
r[1] = y[1] - a[2]/3.0;
r[2] = y[2] - a[2]/3.0;
return 3;
}
return 0; //we had complex eigenvalues
}
__device__ int CalculateRoots(double* a, double* r) {
double c1 = a[1] - a[2]*a[2]/3.;
double c0 = a[0] - a[1]*a[2]/3. + 2./27.*a[2]*a[2]*a[2];
// Make cubic coefficient 4 and linear coefficient +- 3
// by substituting y = z*k and multiplying with 4/k^3
if (c1 == 0) {
if (c0 == 0) r[0] = 0;
else if (c0 > 0) r[0] = -pow(c0, 1./3.);
else r[0] = pow(-c0, 1./3.);
}
else {
bool negc1 = c1 < 0;
double absc1 = negc1 ? -c1 : c1;
double k = sqrt(4./3.*absc1);
double d0 = c0 * 4./(k*k*k);
// Find the first solution
if (negc1) {
if (d0 > 1) r[0] = -cosh(acosh(d0)/3);
else if (d0 > -1) r[0] = -cos(acos(d0)/3);
else r[0] = cosh(acosh(-d0)/3);
}
else {
r[0] = -sinh(asinh(d0)/3);
}
// Transform back
r[0] *= k;
}
r[0] -= a[2]/3;
// Other two solutions
double p = r[0] + a[2];
double q = r[0]*p + a[1];
double discrim = p*p - 4*q;
// if (forceReal && discrim < 0.0) discrim = 0.0;
if (discrim >= 0) {
double root = sqrt(discrim);
r[1] = (-p - root)/2.;
r[2] = (-p + root)/2.;
return 3;
}
else {
double root = sqrt(-discrim);
r[1] = -p/2;
r[2] = root/2.;
return 1;
}
}
__device__ void GetInvariants(double* m, double* pqr) {
pqr[0] = -m[0*3+0]*m[1*3+1]*m[2*3+2]
-m[0*3+1]*m[1*3+2]*m[2*3+0]
-m[0*3+2]*m[1*3+0]*m[2*3+1]
+m[2*3+0]*m[1*3+1]*m[0*3+2]
+m[2*3+1]*m[1*3+2]*m[0*3+0]
+m[2*3+2]*m[1*3+0]*m[0*3+1];
pqr[1] = m[1*3+1]*m[2*3+2] - m[2*3+1]*m[1*3+2]
+ m[0*3+0]*m[1*3+1] - m[1*3+0]*m[0*3+1]
+ m[0*3+0]*m[2*3+2] - m[0*3+2]*m[2*3+0];
pqr[2] = -(m[0*3+0]+m[1*3+1]+m[2*3+2]);
}
__device__ void CalculateCross(double* v1, double* v2, double* res) {
res[0] = v1[1]*v2[2] - v1[2]*v2[1];
res[1] = v1[2]*v2[0] - v1[0]*v2[2];
res[2] = v1[0]*v2[1] - v1[1]*v2[0];
}
__device__ double NormSquared(double* v) {
return (v[0]*v[0]+v[1]*v[1]+v[2]*v[2]);
}
__device__ void CalculateEigenvector(double* m, double lambda, double* evect) {
double norm[3];
double cross[9];
double red[9];
red[0] = m[0]-lambda;
red[1] = m[1];
red[2] = m[2];
red[3] = m[3];
red[4] = m[4]-lambda;
red[5] = m[5];
red[6] = m[6];
red[7] = m[7];
red[8] = m[8]-lambda;
CalculateCross(&red[3], &red[6], &cross[0]);
CalculateCross(&red[6], &red[0], &cross[3]);
CalculateCross(&red[0], &red[3], &cross[6]);
norm[0] = NormSquared(&cross[0]);
norm[1] = NormSquared(&cross[3]);
norm[2] = NormSquared(&cross[6]);
int best = getLargest(norm);
double len = sqrt(norm[best]);
if (len > 0) {
evect[0] = cross[best*3+0] / len;
evect[1] = cross[best*3+1] / len;
evect[2] = cross[best*3+2] / len;
}
else {
evect[0] = 0.0;
evect[1] = 0.0;
evect[2] = 0.0;
}
}
__device__ void swap(double* v1, double* v2) {
double temp = *v1;
*v1 = *v2;
*v2 = temp;
}
__device__ void sortInplace(double* v, int* idx) {
if ( v[0] > v[1] ) swap( &v[0], &v[1] );
if ( v[0] > v[2] ) swap( &v[0], &v[2] );
if ( v[1] > v[2] ) swap( &v[1], &v[2] );
}
__device__ double dotProduct(double* v1, double* v2) {
return (v1[0]*v2[0]+v1[1]*v2[1]+v1[2]*v2[2]);
}
__device__ double findValueOE(double f1, double x1, double f2, double x2, double c){
return ((f2-c)*x1+(c-f1)*x2)/(f2-f1);
}
__device__ void interpolateVector(double g1[3], double g2[3], double t, double* out){
out[0] = (g2[0]-g1[0])*t+g1[0];
out[1] = (g2[1]-g1[1])*t+g1[1];
out[2] = (g2[2]-g1[2])*t+g1[2];
}
typedef double vec3[3];
typedef float fvec3[3];
typedef int ivec3[3];
typedef vec3 mat3[3];
typedef fvec3 fmat3[3];
typedef ivec3 imat3[3];
__device__ inline void vec3sub( vec3 a, vec3 b, vec3 c) { c[0] = a[0] - b[0]; c[1] = a[1] - b[1]; c[2] = a[2] - b[2]; }
__device__ inline double mat3det( mat3 a)
{
return a[0][0]*(a[1][1]*a[2][2] - a[1][2]*a[2][1]) +
a[0][1]*(a[1][2]*a[2][0] - a[1][0]*a[2][2]) +
a[0][2]*(a[1][0]*a[2][1] - a[1][1]*a[2][0]);
}
__device__ inline double vec3det( vec3 a, vec3 b, vec3 c)
{
return a[0]*(b[1]*c[2] - b[2]*c[1]) +
a[1]*(b[2]*c[0] - b[0]*c[2]) +
a[2]*(b[0]*c[1] - b[1]*c[0]);
}
#endif | .text
.file "std_kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006dabc_00000000-6_std_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2044:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2044:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getLargestPd
.type _Z10getLargestPd, @function
_Z10getLargestPd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getLargestPd, .-_Z10getLargestPd
.globl _Z15CalculateRoots2PdS_
.type _Z15CalculateRoots2PdS_, @function
_Z15CalculateRoots2PdS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z15CalculateRoots2PdS_, .-_Z15CalculateRoots2PdS_
.globl _Z14CalculateRootsPdS_
.type _Z14CalculateRootsPdS_, @function
_Z14CalculateRootsPdS_:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z14CalculateRootsPdS_, .-_Z14CalculateRootsPdS_
.globl _Z13GetInvariantsPdS_
.type _Z13GetInvariantsPdS_, @function
_Z13GetInvariantsPdS_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z13GetInvariantsPdS_, .-_Z13GetInvariantsPdS_
.globl _Z14CalculateCrossPdS_S_
.type _Z14CalculateCrossPdS_S_, @function
_Z14CalculateCrossPdS_S_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z14CalculateCrossPdS_S_, .-_Z14CalculateCrossPdS_S_
.globl _Z11NormSquaredPd
.type _Z11NormSquaredPd, @function
_Z11NormSquaredPd:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z11NormSquaredPd, .-_Z11NormSquaredPd
.globl _Z20CalculateEigenvectorPddS_
.type _Z20CalculateEigenvectorPddS_, @function
_Z20CalculateEigenvectorPddS_:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z20CalculateEigenvectorPddS_, .-_Z20CalculateEigenvectorPddS_
.globl _Z4swapPdS_
.type _Z4swapPdS_, @function
_Z4swapPdS_:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z4swapPdS_, .-_Z4swapPdS_
.globl _Z11sortInplacePdPi
.type _Z11sortInplacePdPi, @function
_Z11sortInplacePdPi:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z11sortInplacePdPi, .-_Z11sortInplacePdPi
.globl _Z10dotProductPdS_
.type _Z10dotProductPdS_, @function
_Z10dotProductPdS_:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z10dotProductPdS_, .-_Z10dotProductPdS_
.globl _Z11findValueOEddddd
.type _Z11findValueOEddddd, @function
_Z11findValueOEddddd:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z11findValueOEddddd, .-_Z11findValueOEddddd
.globl _Z17interpolateVectorPdS_dS_
.type _Z17interpolateVectorPdS_dS_, @function
_Z17interpolateVectorPdS_dS_:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Z17interpolateVectorPdS_dS_, .-_Z17interpolateVectorPdS_dS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "std_kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void init_topp_id_val(int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
}
while(tid < vocab_size)
{
topp_id_val_buf[bid * vocab_size + tid] = tid;
tid += blockDim.x;
}
} | code for sm_80
Function : _Z16init_topp_id_valPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x120 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GT.AND P0, PT, R5.reuse, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x041fe40003f04270 */
/*0060*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe40003f26270 */
/*0070*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x002fda0000705670 */
/*0080*/ @P0 BRA 0x110 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fce00078e0005 */
/*00b0*/ IMAD R7, R0.reuse, c[0x0][0x174], RZ ; /* 0x00005d0000077a24 */
/* 0x040fe400078e02ff */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0209 */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*00f0*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 BRA 0xb0 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD R2, R4, c[0x0][0x174], R5 ; /* 0x00005d0004027a24 */
/* 0x000fc800078e0205 */
/*0150*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0170*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x001fc80007ffe0ff */
/*0180*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06270 */
/*0190*/ @!P0 BRA 0x140 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void init_topp_id_val(int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
}
while(tid < vocab_size)
{
topp_id_val_buf[bid * vocab_size + tid] = tid;
tid += blockDim.x;
}
} | .file "tmpxft_000dc697_00000000-6_init_topp_id_val.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii
.type _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii, @function
_Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16init_topp_id_valPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii, .-_Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii
.globl _Z16init_topp_id_valPiS_ii
.type _Z16init_topp_id_valPiS_ii, @function
_Z16init_topp_id_valPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16init_topp_id_valPiS_ii, .-_Z16init_topp_id_valPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16init_topp_id_valPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16init_topp_id_valPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void init_topp_id_val(int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
}
while(tid < vocab_size)
{
topp_id_val_buf[bid * vocab_size + tid] = tid;
tid += blockDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_topp_id_val(int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
}
while(tid < vocab_size)
{
topp_id_val_buf[bid * vocab_size + tid] = tid;
tid += blockDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_topp_id_val(int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
}
while(tid < vocab_size)
{
topp_id_val_buf[bid * vocab_size + tid] = tid;
tid += blockDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16init_topp_id_valPiS_ii
.globl _Z16init_topp_id_valPiS_ii
.p2align 8
.type _Z16init_topp_id_valPiS_ii,@function
_Z16init_topp_id_valPiS_ii:
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_eq_u32 s15, 0
s_mov_b32 s6, 0
s_cselect_b32 s4, -1, 0
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_and_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s4
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v3, v0, s3
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s9, s3, s8
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s2, v1
global_store_b32 v[4:5], v3, off
v_add_nc_u32_e32 v3, s9, v3
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s15, s15, s3
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
.LBB0_5:
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v0
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16init_topp_id_valPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16init_topp_id_valPiS_ii, .Lfunc_end0-_Z16init_topp_id_valPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16init_topp_id_valPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16init_topp_id_valPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_topp_id_val(int* topp_id_val_buf, int* topp_offset_buf, const int batch_size, const int vocab_size)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
if(bid == 0)
{
for(int i = tid; i < batch_size + 1; i+= blockDim.x)
{
topp_offset_buf[i] = i * vocab_size;
}
}
while(tid < vocab_size)
{
topp_id_val_buf[bid * vocab_size + tid] = tid;
tid += blockDim.x;
}
} | .text
.file "init_topp_id_val.hip"
.globl _Z31__device_stub__init_topp_id_valPiS_ii # -- Begin function _Z31__device_stub__init_topp_id_valPiS_ii
.p2align 4, 0x90
.type _Z31__device_stub__init_topp_id_valPiS_ii,@function
_Z31__device_stub__init_topp_id_valPiS_ii: # @_Z31__device_stub__init_topp_id_valPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16init_topp_id_valPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__init_topp_id_valPiS_ii, .Lfunc_end0-_Z31__device_stub__init_topp_id_valPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16init_topp_id_valPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16init_topp_id_valPiS_ii,@object # @_Z16init_topp_id_valPiS_ii
.section .rodata,"a",@progbits
.globl _Z16init_topp_id_valPiS_ii
.p2align 3, 0x0
_Z16init_topp_id_valPiS_ii:
.quad _Z31__device_stub__init_topp_id_valPiS_ii
.size _Z16init_topp_id_valPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16init_topp_id_valPiS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__init_topp_id_valPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16init_topp_id_valPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16init_topp_id_valPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x120 ; /* 0x000000e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GT.AND P0, PT, R5.reuse, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x041fe40003f04270 */
/*0060*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe40003f26270 */
/*0070*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x002fda0000705670 */
/*0080*/ @P0 BRA 0x110 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fce00078e0005 */
/*00b0*/ IMAD R7, R0.reuse, c[0x0][0x174], RZ ; /* 0x00005d0000077a24 */
/* 0x040fe400078e02ff */
/*00c0*/ IMAD.WIDE R2, R0.reuse, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0209 */
/*00d0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*00f0*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 BRA 0xb0 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD R2, R4, c[0x0][0x174], R5 ; /* 0x00005d0004027a24 */
/* 0x000fc800078e0205 */
/*0150*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0170*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x001fc80007ffe0ff */
/*0180*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06270 */
/*0190*/ @!P0 BRA 0x140 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16init_topp_id_valPiS_ii
.globl _Z16init_topp_id_valPiS_ii
.p2align 8
.type _Z16init_topp_id_valPiS_ii,@function
_Z16init_topp_id_valPiS_ii:
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_eq_u32 s15, 0
s_mov_b32 s6, 0
s_cselect_b32 s4, -1, 0
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_and_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s7, s4
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s8, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v3, v0, s3
v_mov_b32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s9, s3, s8
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s2, v1
global_store_b32 v[4:5], v3, off
v_add_nc_u32_e32 v3, s9, v3
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s15, s15, s3
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
.LBB0_5:
v_add_nc_u32_e32 v1, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v0
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16init_topp_id_valPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16init_topp_id_valPiS_ii, .Lfunc_end0-_Z16init_topp_id_valPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16init_topp_id_valPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16init_topp_id_valPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dc697_00000000-6_init_topp_id_val.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii
.type _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii, @function
_Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16init_topp_id_valPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii, .-_Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii
.globl _Z16init_topp_id_valPiS_ii
.type _Z16init_topp_id_valPiS_ii, @function
_Z16init_topp_id_valPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16init_topp_id_valPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16init_topp_id_valPiS_ii, .-_Z16init_topp_id_valPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16init_topp_id_valPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16init_topp_id_valPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init_topp_id_val.hip"
.globl _Z31__device_stub__init_topp_id_valPiS_ii # -- Begin function _Z31__device_stub__init_topp_id_valPiS_ii
.p2align 4, 0x90
.type _Z31__device_stub__init_topp_id_valPiS_ii,@function
_Z31__device_stub__init_topp_id_valPiS_ii: # @_Z31__device_stub__init_topp_id_valPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16init_topp_id_valPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__init_topp_id_valPiS_ii, .Lfunc_end0-_Z31__device_stub__init_topp_id_valPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16init_topp_id_valPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16init_topp_id_valPiS_ii,@object # @_Z16init_topp_id_valPiS_ii
.section .rodata,"a",@progbits
.globl _Z16init_topp_id_valPiS_ii
.p2align 3, 0x0
_Z16init_topp_id_valPiS_ii:
.quad _Z31__device_stub__init_topp_id_valPiS_ii
.size _Z16init_topp_id_valPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16init_topp_id_valPiS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__init_topp_id_valPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16init_topp_id_valPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/sequence.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
int main(void)
{
int N = 20;
// --- Filter parameters
double alpha = 2.7;
double beta = -0.3;
// --- Defining and initializing the input vector on the device
thrust::device_vector<double> d_input(N,alpha * 1.);
d_input[0] = d_input[0]/alpha;
// --- Defining the output vector on the device
thrust::device_vector<double> d_output(d_input);
// --- Defining the {1/beta^n} sequence
thrust::device_vector<double> d_1_over_beta(N,1./beta);
thrust::device_vector<double> d_1_over_beta_to_the_n(N,1./beta);
thrust::device_vector<double> d_n(N);
thrust::sequence(d_n.begin(), d_n.end());
thrust::inclusive_scan(d_1_over_beta.begin(), d_1_over_beta.end(), d_1_over_beta_to_the_n.begin(), thrust::multiplies<double>());
thrust::transform(d_1_over_beta_to_the_n.begin(), d_1_over_beta_to_the_n.end(), d_input.begin(), d_input.begin(), thrust::multiplies<double>());
thrust::inclusive_scan(d_input.begin(), d_input.end(), d_output.begin(), thrust::plus<double>());
thrust::transform(d_output.begin(), d_output.end(), d_1_over_beta_to_the_n.begin(), d_output.begin(), thrust::divides<double>());
for (int i=0; i<N; i++) {
double val = d_output[i];
printf("Device vector element number %i equal to %f\n",i,val);
}
// --- Defining and initializing the input vector on the host
thrust::host_vector<double> h_input(N,1.);
// --- Defining the output vector on the host
thrust::host_vector<double> h_output(h_input);
h_output[0] = h_input[0];
for(int i=1; i<N; i++)
{
h_output[i] = h_input[i] * alpha + beta * h_output[i-1];
}
for (int i=0; i<N; i++) {
double val = h_output[i];
printf("Host vector element number %i equal to %f\n",i,val);
}
for (int i=0; i<N; i++) {
double val = h_output[i] - d_output[i];
printf("Difference between host and device vector element number %i equal to %f\n",i,val);
}
getchar();
} | #include <hip/hip_runtime.h>
#include <thrust/sequence.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
int main(void)
{
int N = 20;
// --- Filter parameters
double alpha = 2.7;
double beta = -0.3;
// --- Defining and initializing the input vector on the device
thrust::device_vector<double> d_input(N,alpha * 1.);
d_input[0] = d_input[0]/alpha;
// --- Defining the output vector on the device
thrust::device_vector<double> d_output(d_input);
// --- Defining the {1/beta^n} sequence
thrust::device_vector<double> d_1_over_beta(N,1./beta);
thrust::device_vector<double> d_1_over_beta_to_the_n(N,1./beta);
thrust::device_vector<double> d_n(N);
thrust::sequence(d_n.begin(), d_n.end());
thrust::inclusive_scan(d_1_over_beta.begin(), d_1_over_beta.end(), d_1_over_beta_to_the_n.begin(), thrust::multiplies<double>());
thrust::transform(d_1_over_beta_to_the_n.begin(), d_1_over_beta_to_the_n.end(), d_input.begin(), d_input.begin(), thrust::multiplies<double>());
thrust::inclusive_scan(d_input.begin(), d_input.end(), d_output.begin(), thrust::plus<double>());
thrust::transform(d_output.begin(), d_output.end(), d_1_over_beta_to_the_n.begin(), d_output.begin(), thrust::divides<double>());
for (int i=0; i<N; i++) {
double val = d_output[i];
printf("Device vector element number %i equal to %f\n",i,val);
}
// --- Defining and initializing the input vector on the host
thrust::host_vector<double> h_input(N,1.);
// --- Defining the output vector on the host
thrust::host_vector<double> h_output(h_input);
h_output[0] = h_input[0];
for(int i=1; i<N; i++)
{
h_output[i] = h_input[i] * alpha + beta * h_output[i-1];
}
for (int i=0; i<N; i++) {
double val = h_output[i];
printf("Host vector element number %i equal to %f\n",i,val);
}
for (int i=0; i<N; i++) {
double val = h_output[i] - d_output[i];
printf("Difference between host and device vector element number %i equal to %f\n",i,val);
}
getchar();
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <unistd.h>
#define NUM_ELEMENTS 1<<20
#define BLOCK_SIZE 1024
#define CUDA_ERROR_CHECK(func) { gpuAssert((func), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void reduce(volatile bool *timeout, bool *executedBlocks, int *input, int *output) {
__shared__ unsigned int block_timeout;
/*Calculate block ID in grid */
unsigned long long int bid = blockIdx.x + gridDim.x *
(blockIdx.y + gridDim.z * blockIdx.z);
/* Copy timeout signal from host to local block variable */
if(threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0){
block_timeout = *timeout;
}
/* Return if block was previously executed */
if(executedBlocks[bid]){
return;
}
/* Preventy any warps from proceeding until timeout is copied */
__syncthreads();
/* Return if block_timeout is true */
if(block_timeout){
return;
}
/* Mark block as executed */
executedBlocks[bid] = true;
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = input[i];
__syncthreads();
for (unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0){
output[blockIdx.x] = sdata[0];
}
}
int main(){
size_t elems = NUM_ELEMENTS;
size_t grid_size = (size_t)(ceill((long double)elems/(long double)BLOCK_SIZE));
size_t input_size = elems * sizeof(int);
size_t output_size = grid_size * sizeof(int);
int *deviceInput = NULL;
int *deviceOutput = NULL;
int *hostInput = NULL;
int *hostOutput = NULL;
hostInput = (int *)malloc(input_size);
hostOutput = (int *)malloc(output_size);
if(hostInput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for input!\n", input_size);
exit(EXIT_FAILURE);
}
if(hostOutput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for output!\n", output_size);
exit(EXIT_FAILURE);
}
CUDA_ERROR_CHECK(cudaMalloc((void **)&deviceInput, input_size));
CUDA_ERROR_CHECK(cudaMalloc((void **)&deviceOutput, output_size));
size_t i = 0;
for(i = 0; i < elems; i++){
hostInput[i] = 1;
}
volatile bool *timeout = NULL;
bool complete = false;
bool *executedBlocks = NULL;
cudaMallocManaged((void **)&timeout, sizeof(volatile bool), cudaMemAttachGlobal);
cudaMallocManaged((void **)&executedBlocks, grid_size * sizeof(bool), cudaMemAttachGlobal);
memset(executedBlocks, 0, grid_size * sizeof(bool));
*timeout = false;
size_t interrupt_count = 0;
CUDA_ERROR_CHECK(cudaMemcpy(deviceInput, hostInput, input_size, cudaMemcpyHostToDevice));
while(!complete){
reduce<<<grid_size, BLOCK_SIZE, BLOCK_SIZE*sizeof(int)>>>(timeout, executedBlocks, deviceInput, deviceOutput);
CUDA_ERROR_CHECK(cudaPeekAtLastError());
usleep(0.001);
*timeout = true;
CUDA_ERROR_CHECK(cudaDeviceSynchronize());
/* Check if kernel is complete */
size_t i = 0;
for(i = 0; i < grid_size; i++){
if(executedBlocks[i] == false){
break;
}
}
interrupt_count++;
if(i == grid_size){
complete = true;
}else{
*timeout = false;
}
}
fprintf(stdout, "Interrupt count: %zu\n", interrupt_count);
CUDA_ERROR_CHECK(cudaMemcpy(hostOutput, deviceOutput, output_size, cudaMemcpyDeviceToHost));
for(i = 1; i < grid_size; i++){
hostOutput[0] += hostOutput[i];
}
fprintf(stdout, "Result: ");
if(hostOutput[0] == NUM_ELEMENTS){
fprintf(stdout, "PASS\n");
}else{
fprintf(stderr, "FAIL\n");
}
fprintf(stdout, "Sum = %d\n", hostOutput[0]);
free(hostInput);
free(hostOutput);
CUDA_ERROR_CHECK(cudaFree(deviceInput));
CUDA_ERROR_CHECK(cudaFree(deviceOutput));
CUDA_ERROR_CHECK(cudaFree(executedBlocks));
CUDA_ERROR_CHECK(cudaFree((void *)timeout));
CUDA_ERROR_CHECK(cudaDeviceReset());
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z6reducePVbPbPiS2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R6, SR_CTAID.Z ; /* 0x0000000000067919 */
/* 0x000e280000002700 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000ea80000002200 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea80000002100 */
/*0070*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0080*/ IMAD R5, R6, c[0x0][0x14], R5 ; /* 0x0000050006057a24 */
/* 0x001fc800078e0205 */
/*0090*/ IMAD R5, R5, c[0x0][0xc], R0 ; /* 0x0000030005057a24 */
/* 0x002fca00078e0200 */
/*00a0*/ IADD3 R6, P1, R5, c[0x0][0x168], RZ ; /* 0x00005a0005067a10 */
/* 0x000fca0007f3e0ff */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff077624 */
/* 0x000fe200008e06ff */
/*00c0*/ LOP3.LUT P0, RZ, R4, R3, R2, 0xfe, !PT ; /* 0x0000000304ff7212 */
/* 0x004fc8000780fe02 */
/*00d0*/ LDG.E.U8 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000eb2000c1e1100 */
/*00e0*/ @!P0 MOV R4, c[0x0][0x160] ; /* 0x0000580000048a02 */
/* 0x000fe20000000f00 */
/*00f0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff058624 */
/* 0x000fca00078e00ff */
/*0100*/ @!P0 LDG.E.S8.STRONG.SYS R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ee2000c1f5300 */
/*0110*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc60003f25270 */
/*0120*/ @!P0 STS [RZ], R4 ; /* 0x00000004ff008388 */
/* 0x0081f40000000800 */
/*0130*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e640000000800 */
/*0160*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x002fda0003f05270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0190*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fe400078e0203 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E.U8 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0001e4000c101104 */
/*01c0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0005 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05270 */
/*0200*/ ISETP.GE.U32.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f26070 */
/*0210*/ STS [R3.X4+0x10], R4 ; /* 0x0000100403007388 */
/* 0x0041e80000004800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0230*/ @!P1 BRA 0x420 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0240*/ LEA R2, R3, 0x10, 0x2 ; /* 0x0000001003027811 */
/* 0x001fe400078e10ff */
/*0250*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fca0000000f00 */
/*0260*/ IMAD.SHL.U32 R10, R7, 0x2, RZ ; /* 0x00000002070a7824 */
/* 0x000fc800078e00ff */
/*0270*/ I2F.U32.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e220000209000 */
/*0280*/ IADD3 R9, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fca0003f45070 */
/*02a0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*02b0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*02c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*02e0*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*02f0*/ IMAD.HI.U32 R8, R5, R9, R4 ; /* 0x0000000905087227 */
/* 0x000fcc00078e0004 */
/*0300*/ IMAD.HI.U32 R8, R8, R3, RZ ; /* 0x0000000308087227 */
/* 0x000fca00078e00ff */
/*0310*/ IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08087210 */
/* 0x000fca0007ffe1ff */
/*0320*/ IMAD R5, R10, R8, R3 ; /* 0x000000080a057224 */
/* 0x000fca00078e0203 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fda0003f26070 */
/*0340*/ @P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105051824 */
/* 0x000fca00078e0a0a */
/*0350*/ ISETP.GE.U32.AND P1, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fda0003f26070 */
/*0360*/ @P1 IADD3 R5, -R10, R5, RZ ; /* 0x000000050a051210 */
/* 0x000fe40007ffe1ff */
/*0370*/ @!P2 LOP3.LUT R5, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff05a212 */
/* 0x000fc800078e33ff */
/*0380*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0390*/ @!P1 IMAD R4, R7, 0x4, R2 ; /* 0x0000000407049824 */
/* 0x000fe200078e0202 */
/*03a0*/ @!P1 LDS R5, [R3.X4+0x10] ; /* 0x0000100003059984 */
/* 0x000fe20000004800 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fc800078e000a */
/*03c0*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*03d0*/ @!P1 IADD3 R6, R5, R4, RZ ; /* 0x0000000405069210 */
/* 0x001fca0007ffe0ff */
/*03e0*/ @!P1 STS [R3.X4+0x10], R6 ; /* 0x0000100603009388 */
/* 0x0001e80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*0410*/ @!P1 BRA 0x260 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*0420*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0430*/ LDS R5, [0x10] ; /* 0x00001000ff057984 */
/* 0x000e220000000800 */
/*0440*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0450*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0003 */
/*0460*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <unistd.h>
#define NUM_ELEMENTS 1<<20
#define BLOCK_SIZE 1024
#define CUDA_ERROR_CHECK(func) { gpuAssert((func), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void reduce(volatile bool *timeout, bool *executedBlocks, int *input, int *output) {
__shared__ unsigned int block_timeout;
/*Calculate block ID in grid */
unsigned long long int bid = blockIdx.x + gridDim.x *
(blockIdx.y + gridDim.z * blockIdx.z);
/* Copy timeout signal from host to local block variable */
if(threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0){
block_timeout = *timeout;
}
/* Return if block was previously executed */
if(executedBlocks[bid]){
return;
}
/* Preventy any warps from proceeding until timeout is copied */
__syncthreads();
/* Return if block_timeout is true */
if(block_timeout){
return;
}
/* Mark block as executed */
executedBlocks[bid] = true;
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = input[i];
__syncthreads();
for (unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0){
output[blockIdx.x] = sdata[0];
}
}
int main(){
size_t elems = NUM_ELEMENTS;
size_t grid_size = (size_t)(ceill((long double)elems/(long double)BLOCK_SIZE));
size_t input_size = elems * sizeof(int);
size_t output_size = grid_size * sizeof(int);
int *deviceInput = NULL;
int *deviceOutput = NULL;
int *hostInput = NULL;
int *hostOutput = NULL;
hostInput = (int *)malloc(input_size);
hostOutput = (int *)malloc(output_size);
if(hostInput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for input!\n", input_size);
exit(EXIT_FAILURE);
}
if(hostOutput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for output!\n", output_size);
exit(EXIT_FAILURE);
}
CUDA_ERROR_CHECK(cudaMalloc((void **)&deviceInput, input_size));
CUDA_ERROR_CHECK(cudaMalloc((void **)&deviceOutput, output_size));
size_t i = 0;
for(i = 0; i < elems; i++){
hostInput[i] = 1;
}
volatile bool *timeout = NULL;
bool complete = false;
bool *executedBlocks = NULL;
cudaMallocManaged((void **)&timeout, sizeof(volatile bool), cudaMemAttachGlobal);
cudaMallocManaged((void **)&executedBlocks, grid_size * sizeof(bool), cudaMemAttachGlobal);
memset(executedBlocks, 0, grid_size * sizeof(bool));
*timeout = false;
size_t interrupt_count = 0;
CUDA_ERROR_CHECK(cudaMemcpy(deviceInput, hostInput, input_size, cudaMemcpyHostToDevice));
while(!complete){
reduce<<<grid_size, BLOCK_SIZE, BLOCK_SIZE*sizeof(int)>>>(timeout, executedBlocks, deviceInput, deviceOutput);
CUDA_ERROR_CHECK(cudaPeekAtLastError());
usleep(0.001);
*timeout = true;
CUDA_ERROR_CHECK(cudaDeviceSynchronize());
/* Check if kernel is complete */
size_t i = 0;
for(i = 0; i < grid_size; i++){
if(executedBlocks[i] == false){
break;
}
}
interrupt_count++;
if(i == grid_size){
complete = true;
}else{
*timeout = false;
}
}
fprintf(stdout, "Interrupt count: %zu\n", interrupt_count);
CUDA_ERROR_CHECK(cudaMemcpy(hostOutput, deviceOutput, output_size, cudaMemcpyDeviceToHost));
for(i = 1; i < grid_size; i++){
hostOutput[0] += hostOutput[i];
}
fprintf(stdout, "Result: ");
if(hostOutput[0] == NUM_ELEMENTS){
fprintf(stdout, "PASS\n");
}else{
fprintf(stderr, "FAIL\n");
}
fprintf(stdout, "Sum = %d\n", hostOutput[0]);
free(hostInput);
free(hostOutput);
CUDA_ERROR_CHECK(cudaFree(deviceInput));
CUDA_ERROR_CHECK(cudaFree(deviceOutput));
CUDA_ERROR_CHECK(cudaFree(executedBlocks));
CUDA_ERROR_CHECK(cudaFree((void *)timeout));
CUDA_ERROR_CHECK(cudaDeviceReset());
return EXIT_SUCCESS;
} | .file "tmpxft_000c6629_00000000-6_reduction_interrupt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2070:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
.type _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_, @function
_Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePVbPbPiS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_, .-_Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
.globl _Z6reducePVbPbPiS2_
.type _Z6reducePVbPbPiS2_, @function
_Z6reducePVbPbPiS2_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z6reducePVbPbPiS2_, .-_Z6reducePVbPbPiS2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate %zu bytes for input!\n"
.align 8
.LC2:
.string "Failed to allocate %zu bytes for output!\n"
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/maxbaird/appendix/master/a2/reduction_interrupt.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Result: "
.LC5:
.string "PASS\n"
.LC6:
.string "FAIL\n"
.LC7:
.string "Sum = %d\n"
.LC8:
.string "Interrupt count: %zu\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
testq %rbp, %rbp
je .L40
movq %rax, %rbx
testq %rax, %rax
je .L41
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $92, %edx
leaq .LC3(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $93, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rbp, %rax
leaq 4194304(%rbp), %rdx
.L22:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $1, %edx
movl $1, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
movq 24(%rsp), %rax
movq $0, (%rax)
movq $0, 1016(%rax)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
leal 1024(%rax), %ecx
shrl $3, %ecx
movl %ecx, %ecx
movl $0, %eax
rep stosq
movq 16(%rsp), %rax
movb $0, (%rax)
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $113, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %r13d
.L32:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L23:
call cudaPeekAtLastError@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L43
movl $0, %edi
call usleep@PLT
movq 16(%rsp), %rax
movb $1, (%rax)
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L44
movq 24(%rsp), %rdx
movl $0, %eax
.L27:
cmpb $0, (%rdx,%rax)
je .L26
addq $1, %rax
cmpq $1024, %rax
jne .L27
leaq 1(%r13), %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $140, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 4(%rbx), %rax
leaq 4096(%rbx), %rcx
.L29:
movl (%rax), %edx
addl %edx, (%rbx)
addq $4, %rax
cmpq %rcx, %rax
jne .L29
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $1048576, (%rbx)
je .L45
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L31:
movl (%rbx), %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $159, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $160, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $161, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $162, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceReset@PLT
movl %eax, %edi
movl $1, %ecx
movl $164, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $4194304, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl $4096, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
jmp .L23
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $117, %r9d
leaq .LC3(%rip), %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC3(%rip), %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L45:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L31
.L26:
addq $1, %r13
movq 16(%rsp), %rax
movb $0, (%rax)
jmp .L32
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6reducePVbPbPiS2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePVbPbPiS2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <unistd.h>
#define NUM_ELEMENTS 1<<20
#define BLOCK_SIZE 1024
#define CUDA_ERROR_CHECK(func) { gpuAssert((func), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void reduce(volatile bool *timeout, bool *executedBlocks, int *input, int *output) {
__shared__ unsigned int block_timeout;
/*Calculate block ID in grid */
unsigned long long int bid = blockIdx.x + gridDim.x *
(blockIdx.y + gridDim.z * blockIdx.z);
/* Copy timeout signal from host to local block variable */
if(threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0){
block_timeout = *timeout;
}
/* Return if block was previously executed */
if(executedBlocks[bid]){
return;
}
/* Preventy any warps from proceeding until timeout is copied */
__syncthreads();
/* Return if block_timeout is true */
if(block_timeout){
return;
}
/* Mark block as executed */
executedBlocks[bid] = true;
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = input[i];
__syncthreads();
for (unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0){
output[blockIdx.x] = sdata[0];
}
}
int main(){
size_t elems = NUM_ELEMENTS;
size_t grid_size = (size_t)(ceill((long double)elems/(long double)BLOCK_SIZE));
size_t input_size = elems * sizeof(int);
size_t output_size = grid_size * sizeof(int);
int *deviceInput = NULL;
int *deviceOutput = NULL;
int *hostInput = NULL;
int *hostOutput = NULL;
hostInput = (int *)malloc(input_size);
hostOutput = (int *)malloc(output_size);
if(hostInput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for input!\n", input_size);
exit(EXIT_FAILURE);
}
if(hostOutput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for output!\n", output_size);
exit(EXIT_FAILURE);
}
CUDA_ERROR_CHECK(cudaMalloc((void **)&deviceInput, input_size));
CUDA_ERROR_CHECK(cudaMalloc((void **)&deviceOutput, output_size));
size_t i = 0;
for(i = 0; i < elems; i++){
hostInput[i] = 1;
}
volatile bool *timeout = NULL;
bool complete = false;
bool *executedBlocks = NULL;
cudaMallocManaged((void **)&timeout, sizeof(volatile bool), cudaMemAttachGlobal);
cudaMallocManaged((void **)&executedBlocks, grid_size * sizeof(bool), cudaMemAttachGlobal);
memset(executedBlocks, 0, grid_size * sizeof(bool));
*timeout = false;
size_t interrupt_count = 0;
CUDA_ERROR_CHECK(cudaMemcpy(deviceInput, hostInput, input_size, cudaMemcpyHostToDevice));
while(!complete){
reduce<<<grid_size, BLOCK_SIZE, BLOCK_SIZE*sizeof(int)>>>(timeout, executedBlocks, deviceInput, deviceOutput);
CUDA_ERROR_CHECK(cudaPeekAtLastError());
usleep(0.001);
*timeout = true;
CUDA_ERROR_CHECK(cudaDeviceSynchronize());
/* Check if kernel is complete */
size_t i = 0;
for(i = 0; i < grid_size; i++){
if(executedBlocks[i] == false){
break;
}
}
interrupt_count++;
if(i == grid_size){
complete = true;
}else{
*timeout = false;
}
}
fprintf(stdout, "Interrupt count: %zu\n", interrupt_count);
CUDA_ERROR_CHECK(cudaMemcpy(hostOutput, deviceOutput, output_size, cudaMemcpyDeviceToHost));
for(i = 1; i < grid_size; i++){
hostOutput[0] += hostOutput[i];
}
fprintf(stdout, "Result: ");
if(hostOutput[0] == NUM_ELEMENTS){
fprintf(stdout, "PASS\n");
}else{
fprintf(stderr, "FAIL\n");
}
fprintf(stdout, "Sum = %d\n", hostOutput[0]);
free(hostInput);
free(hostOutput);
CUDA_ERROR_CHECK(cudaFree(deviceInput));
CUDA_ERROR_CHECK(cudaFree(deviceOutput));
CUDA_ERROR_CHECK(cudaFree(executedBlocks));
CUDA_ERROR_CHECK(cudaFree((void *)timeout));
CUDA_ERROR_CHECK(cudaDeviceReset());
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <unistd.h>
#define NUM_ELEMENTS 1<<20
#define BLOCK_SIZE 1024
#define CUDA_ERROR_CHECK(func) { gpuAssert((func), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void reduce(volatile bool *timeout, bool *executedBlocks, int *input, int *output) {
__shared__ unsigned int block_timeout;
/*Calculate block ID in grid */
unsigned long long int bid = blockIdx.x + gridDim.x *
(blockIdx.y + gridDim.z * blockIdx.z);
/* Copy timeout signal from host to local block variable */
if(threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0){
block_timeout = *timeout;
}
/* Return if block was previously executed */
if(executedBlocks[bid]){
return;
}
/* Preventy any warps from proceeding until timeout is copied */
__syncthreads();
/* Return if block_timeout is true */
if(block_timeout){
return;
}
/* Mark block as executed */
executedBlocks[bid] = true;
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = input[i];
__syncthreads();
for (unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0){
output[blockIdx.x] = sdata[0];
}
}
int main(){
size_t elems = NUM_ELEMENTS;
size_t grid_size = (size_t)(ceill((long double)elems/(long double)BLOCK_SIZE));
size_t input_size = elems * sizeof(int);
size_t output_size = grid_size * sizeof(int);
int *deviceInput = NULL;
int *deviceOutput = NULL;
int *hostInput = NULL;
int *hostOutput = NULL;
hostInput = (int *)malloc(input_size);
hostOutput = (int *)malloc(output_size);
if(hostInput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for input!\n", input_size);
exit(EXIT_FAILURE);
}
if(hostOutput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for output!\n", output_size);
exit(EXIT_FAILURE);
}
CUDA_ERROR_CHECK(hipMalloc((void **)&deviceInput, input_size));
CUDA_ERROR_CHECK(hipMalloc((void **)&deviceOutput, output_size));
size_t i = 0;
for(i = 0; i < elems; i++){
hostInput[i] = 1;
}
volatile bool *timeout = NULL;
bool complete = false;
bool *executedBlocks = NULL;
hipMallocManaged((void **)&timeout, sizeof(volatile bool), hipMemAttachGlobal);
hipMallocManaged((void **)&executedBlocks, grid_size * sizeof(bool), hipMemAttachGlobal);
memset(executedBlocks, 0, grid_size * sizeof(bool));
*timeout = false;
size_t interrupt_count = 0;
CUDA_ERROR_CHECK(hipMemcpy(deviceInput, hostInput, input_size, hipMemcpyHostToDevice));
while(!complete){
reduce<<<grid_size, BLOCK_SIZE, BLOCK_SIZE*sizeof(int)>>>(timeout, executedBlocks, deviceInput, deviceOutput);
CUDA_ERROR_CHECK(hipPeekAtLastError());
usleep(0.001);
*timeout = true;
CUDA_ERROR_CHECK(hipDeviceSynchronize());
/* Check if kernel is complete */
size_t i = 0;
for(i = 0; i < grid_size; i++){
if(executedBlocks[i] == false){
break;
}
}
interrupt_count++;
if(i == grid_size){
complete = true;
}else{
*timeout = false;
}
}
fprintf(stdout, "Interrupt count: %zu\n", interrupt_count);
CUDA_ERROR_CHECK(hipMemcpy(hostOutput, deviceOutput, output_size, hipMemcpyDeviceToHost));
for(i = 1; i < grid_size; i++){
hostOutput[0] += hostOutput[i];
}
fprintf(stdout, "Result: ");
if(hostOutput[0] == NUM_ELEMENTS){
fprintf(stdout, "PASS\n");
}else{
fprintf(stderr, "FAIL\n");
}
fprintf(stdout, "Sum = %d\n", hostOutput[0]);
free(hostInput);
free(hostOutput);
CUDA_ERROR_CHECK(hipFree(deviceInput));
CUDA_ERROR_CHECK(hipFree(deviceOutput));
CUDA_ERROR_CHECK(hipFree(executedBlocks));
CUDA_ERROR_CHECK(hipFree((void *)timeout));
CUDA_ERROR_CHECK(hipDeviceReset());
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <unistd.h>
#define NUM_ELEMENTS 1<<20
#define BLOCK_SIZE 1024
#define CUDA_ERROR_CHECK(func) { gpuAssert((func), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void reduce(volatile bool *timeout, bool *executedBlocks, int *input, int *output) {
__shared__ unsigned int block_timeout;
/*Calculate block ID in grid */
unsigned long long int bid = blockIdx.x + gridDim.x *
(blockIdx.y + gridDim.z * blockIdx.z);
/* Copy timeout signal from host to local block variable */
if(threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0){
block_timeout = *timeout;
}
/* Return if block was previously executed */
if(executedBlocks[bid]){
return;
}
/* Preventy any warps from proceeding until timeout is copied */
__syncthreads();
/* Return if block_timeout is true */
if(block_timeout){
return;
}
/* Mark block as executed */
executedBlocks[bid] = true;
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = input[i];
__syncthreads();
for (unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0){
output[blockIdx.x] = sdata[0];
}
}
int main(){
size_t elems = NUM_ELEMENTS;
size_t grid_size = (size_t)(ceill((long double)elems/(long double)BLOCK_SIZE));
size_t input_size = elems * sizeof(int);
size_t output_size = grid_size * sizeof(int);
int *deviceInput = NULL;
int *deviceOutput = NULL;
int *hostInput = NULL;
int *hostOutput = NULL;
hostInput = (int *)malloc(input_size);
hostOutput = (int *)malloc(output_size);
if(hostInput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for input!\n", input_size);
exit(EXIT_FAILURE);
}
if(hostOutput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for output!\n", output_size);
exit(EXIT_FAILURE);
}
CUDA_ERROR_CHECK(hipMalloc((void **)&deviceInput, input_size));
CUDA_ERROR_CHECK(hipMalloc((void **)&deviceOutput, output_size));
size_t i = 0;
for(i = 0; i < elems; i++){
hostInput[i] = 1;
}
volatile bool *timeout = NULL;
bool complete = false;
bool *executedBlocks = NULL;
hipMallocManaged((void **)&timeout, sizeof(volatile bool), hipMemAttachGlobal);
hipMallocManaged((void **)&executedBlocks, grid_size * sizeof(bool), hipMemAttachGlobal);
memset(executedBlocks, 0, grid_size * sizeof(bool));
*timeout = false;
size_t interrupt_count = 0;
CUDA_ERROR_CHECK(hipMemcpy(deviceInput, hostInput, input_size, hipMemcpyHostToDevice));
while(!complete){
reduce<<<grid_size, BLOCK_SIZE, BLOCK_SIZE*sizeof(int)>>>(timeout, executedBlocks, deviceInput, deviceOutput);
CUDA_ERROR_CHECK(hipPeekAtLastError());
usleep(0.001);
*timeout = true;
CUDA_ERROR_CHECK(hipDeviceSynchronize());
/* Check if kernel is complete */
size_t i = 0;
for(i = 0; i < grid_size; i++){
if(executedBlocks[i] == false){
break;
}
}
interrupt_count++;
if(i == grid_size){
complete = true;
}else{
*timeout = false;
}
}
fprintf(stdout, "Interrupt count: %zu\n", interrupt_count);
CUDA_ERROR_CHECK(hipMemcpy(hostOutput, deviceOutput, output_size, hipMemcpyDeviceToHost));
for(i = 1; i < grid_size; i++){
hostOutput[0] += hostOutput[i];
}
fprintf(stdout, "Result: ");
if(hostOutput[0] == NUM_ELEMENTS){
fprintf(stdout, "PASS\n");
}else{
fprintf(stderr, "FAIL\n");
}
fprintf(stdout, "Sum = %d\n", hostOutput[0]);
free(hostInput);
free(hostOutput);
CUDA_ERROR_CHECK(hipFree(deviceInput));
CUDA_ERROR_CHECK(hipFree(deviceOutput));
CUDA_ERROR_CHECK(hipFree(executedBlocks));
CUDA_ERROR_CHECK(hipFree((void *)timeout));
CUDA_ERROR_CHECK(hipDeviceReset());
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reducePVbPbPiS2_
.globl _Z6reducePVbPbPiS2_
.p2align 8
.type _Z6reducePVbPbPiS2_,@function
_Z6reducePVbPbPiS2_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s6, s0, 32
s_mov_b32 s4, s13
v_cmp_eq_u32_e64 s2, 0, v1
s_addc_u32 s7, s1, 0
v_or3_b32 v0, v1, v0, v2
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[10:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
flat_load_u8 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[8:9], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s5, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s14
s_mul_i32 s3, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
v_mov_b32_e32 v0, s3
global_load_u8 v0, v0, s[8:9]
s_add_u32 s8, s8, s3
s_addc_u32 s9, s9, 0
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v0
s_cbranch_vccz .LBB0_4
.LBB0_3:
s_endpgm
.LBB0_4:
v_mov_b32_e32 v0, 0
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v0
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v2, 1
s_mov_b32 s5, 1
global_store_b8 v0, v2, s[8:9]
s_load_b32 s3, s[6:7], 0xc
s_load_b64 s[6:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s4, s3, v[1:2]
v_mov_b32_e32 v3, v0
v_lshl_add_u32 v0, v1, 2, 4
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_ge_u32 s6, s3
s_mov_b32 s5, s6
.LBB0_7:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
s_lshl_b32 s6, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s6, -1
v_and_b32_e32 v2, s7, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v2, s5, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 4
ds_load_b32 v2, v2
ds_load_b32 v3, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v0, v2
s_branch .LBB0_6
.LBB0_10:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePVbPbPiS2_
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reducePVbPbPiS2_, .Lfunc_end0-_Z6reducePVbPbPiS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePVbPbPiS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePVbPbPiS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <unistd.h>
#define NUM_ELEMENTS 1<<20
#define BLOCK_SIZE 1024
#define CUDA_ERROR_CHECK(func) { gpuAssert((func), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void reduce(volatile bool *timeout, bool *executedBlocks, int *input, int *output) {
__shared__ unsigned int block_timeout;
/*Calculate block ID in grid */
unsigned long long int bid = blockIdx.x + gridDim.x *
(blockIdx.y + gridDim.z * blockIdx.z);
/* Copy timeout signal from host to local block variable */
if(threadIdx.x == 0 && threadIdx.y == 0 && threadIdx.z == 0){
block_timeout = *timeout;
}
/* Return if block was previously executed */
if(executedBlocks[bid]){
return;
}
/* Preventy any warps from proceeding until timeout is copied */
__syncthreads();
/* Return if block_timeout is true */
if(block_timeout){
return;
}
/* Mark block as executed */
executedBlocks[bid] = true;
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = input[i];
__syncthreads();
for (unsigned int s = 1; s < blockDim.x; s *= 2) {
if (tid % (2 * s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0){
output[blockIdx.x] = sdata[0];
}
}
int main(){
size_t elems = NUM_ELEMENTS;
size_t grid_size = (size_t)(ceill((long double)elems/(long double)BLOCK_SIZE));
size_t input_size = elems * sizeof(int);
size_t output_size = grid_size * sizeof(int);
int *deviceInput = NULL;
int *deviceOutput = NULL;
int *hostInput = NULL;
int *hostOutput = NULL;
hostInput = (int *)malloc(input_size);
hostOutput = (int *)malloc(output_size);
if(hostInput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for input!\n", input_size);
exit(EXIT_FAILURE);
}
if(hostOutput == NULL){
fprintf(stderr, "Failed to allocate %zu bytes for output!\n", output_size);
exit(EXIT_FAILURE);
}
CUDA_ERROR_CHECK(hipMalloc((void **)&deviceInput, input_size));
CUDA_ERROR_CHECK(hipMalloc((void **)&deviceOutput, output_size));
size_t i = 0;
for(i = 0; i < elems; i++){
hostInput[i] = 1;
}
volatile bool *timeout = NULL;
bool complete = false;
bool *executedBlocks = NULL;
hipMallocManaged((void **)&timeout, sizeof(volatile bool), hipMemAttachGlobal);
hipMallocManaged((void **)&executedBlocks, grid_size * sizeof(bool), hipMemAttachGlobal);
memset(executedBlocks, 0, grid_size * sizeof(bool));
*timeout = false;
size_t interrupt_count = 0;
CUDA_ERROR_CHECK(hipMemcpy(deviceInput, hostInput, input_size, hipMemcpyHostToDevice));
while(!complete){
reduce<<<grid_size, BLOCK_SIZE, BLOCK_SIZE*sizeof(int)>>>(timeout, executedBlocks, deviceInput, deviceOutput);
CUDA_ERROR_CHECK(hipPeekAtLastError());
usleep(0.001);
*timeout = true;
CUDA_ERROR_CHECK(hipDeviceSynchronize());
/* Check if kernel is complete */
size_t i = 0;
for(i = 0; i < grid_size; i++){
if(executedBlocks[i] == false){
break;
}
}
interrupt_count++;
if(i == grid_size){
complete = true;
}else{
*timeout = false;
}
}
fprintf(stdout, "Interrupt count: %zu\n", interrupt_count);
CUDA_ERROR_CHECK(hipMemcpy(hostOutput, deviceOutput, output_size, hipMemcpyDeviceToHost));
for(i = 1; i < grid_size; i++){
hostOutput[0] += hostOutput[i];
}
fprintf(stdout, "Result: ");
if(hostOutput[0] == NUM_ELEMENTS){
fprintf(stdout, "PASS\n");
}else{
fprintf(stderr, "FAIL\n");
}
fprintf(stdout, "Sum = %d\n", hostOutput[0]);
free(hostInput);
free(hostOutput);
CUDA_ERROR_CHECK(hipFree(deviceInput));
CUDA_ERROR_CHECK(hipFree(deviceOutput));
CUDA_ERROR_CHECK(hipFree(executedBlocks));
CUDA_ERROR_CHECK(hipFree((void *)timeout));
CUDA_ERROR_CHECK(hipDeviceReset());
return EXIT_SUCCESS;
} | .text
.file "reduction_interrupt.hip"
.globl _Z21__device_stub__reducePVbPbPiS2_ # -- Begin function _Z21__device_stub__reducePVbPbPiS2_
.p2align 4, 0x90
.type _Z21__device_stub__reducePVbPbPiS2_,@function
_Z21__device_stub__reducePVbPbPiS2_: # @_Z21__device_stub__reducePVbPbPiS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePVbPbPiS2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePVbPbPiS2_, .Lfunc_end0-_Z21__device_stub__reducePVbPbPiS2_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
testq %rbx, %rbx
je .LBB1_1
# %bb.3:
movq %rax, %r15
testq %rax, %rax
je .LBB1_4
# %bb.5:
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_47
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit51.preheader
movl $1024, %r14d # imm = 0x400
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_10: # %_Z9gpuAssert10hipError_tPKcib.exit51
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_10
# %bb.11:
movq %r15, 40(%rsp) # 8-byte Spill
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $1, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
movq (%rsp), %rax
movb $0, (%rax)
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, 32(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit53.preheader
movabsq $4294967296, %r15 # imm = 0x100000000
leaq (%r14,%r15), %r12
xorl %ebx, %ebx
addq $1024, %r15 # imm = 0x400
xorl %r13d, %r13d
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_27: # %_Z9gpuAssert10hipError_tPKcib.exit53
# in Loop: Header=BB1_13 Depth=1
incq %r13
movl %ecx, %ebx
testb $1, %cl
jne .LBB1_28
.LBB1_13: # =>This Loop Header: Depth=1
# Child Loop BB1_22 Depth 2
movl $4096, %r8d # imm = 0x1000
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z6reducePVbPbPiS2_, %edi
leaq 128(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15: # in Loop: Header=BB1_13 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit55
# in Loop: Header=BB1_13 Depth=1
xorl %edi, %edi
callq usleep
movq (%rsp), %rax
movb $1, (%rax)
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_20
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit57.preheader
# in Loop: Header=BB1_13 Depth=1
testq %r14, %r14
je .LBB1_19
# %bb.21: # %.lr.ph
# in Loop: Header=BB1_13 Depth=1
movq 8(%rsp), %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_22: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rcx,%rax)
je .LBB1_25
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit57
# in Loop: Header=BB1_22 Depth=2
incq %rax
cmpq %rax, %r14
jne .LBB1_22
# %bb.24: # in Loop: Header=BB1_13 Depth=1
movl $1024, %eax # imm = 0x400
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_13 Depth=1
xorl %eax, %eax
.LBB1_25: # %._crit_edge
# in Loop: Header=BB1_13 Depth=1
movb $1, %cl
cmpq %r14, %rax
je .LBB1_27
# %bb.26: # in Loop: Header=BB1_13 Depth=1
movq (%rsp), %rax
movb $0, (%rax)
movl %ebx, %ecx
jmp .LBB1_27
.LBB1_28:
movq stdout(%rip), %rdi
movl $.L.str.3, %esi
movq %r13, %rdx
xorl %eax, %eax
callq fprintf
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_49
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit59.preheader
cmpl $2, %r14d
movq 32(%rsp), %rbx # 8-byte Reload
jb .LBB1_33
# %bb.30: # %.lr.ph83
movl (%r15), %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB1_31: # %_Z9gpuAssert10hipError_tPKcib.exit59
# =>This Inner Loop Header: Depth=1
addl (%r15,%rcx,4), %eax
incq %rcx
cmpq %rcx, %r14
jne .LBB1_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit59._crit_edge.loopexit
movl %eax, (%r15)
.LBB1_33: # %_Z9gpuAssert10hipError_tPKcib.exit59._crit_edge
movq stdout(%rip), %rcx
movl $.L.str.4, %edi
movl $8, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $1048576, (%r15) # imm = 0x100000
jne .LBB1_35
# %bb.34:
movq stdout(%rip), %rcx
movl $.L.str.5, %edi
.LBB1_36:
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl (%r15), %edx
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_37
# %bb.38: # %_Z9gpuAssert10hipError_tPKcib.exit61
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_39
# %bb.40: # %_Z9gpuAssert10hipError_tPKcib.exit63
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_41
# %bb.42: # %_Z9gpuAssert10hipError_tPKcib.exit65
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.44: # %_Z9gpuAssert10hipError_tPKcib.exit67
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_45
# %bb.46: # %_Z9gpuAssert10hipError_tPKcib.exit69
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_35:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB1_36
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB1_7
.LBB1_16:
movl %eax, %ebp
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $119, %r8d
.LBB1_7:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $4194304, %edx # imm = 0x400000
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movl $4096, %edx # imm = 0x1000
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $94, %r8d
jmp .LBB1_7
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $95, %r8d
jmp .LBB1_7
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB1_7
.LBB1_49:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $142, %r8d
jmp .LBB1_7
.LBB1_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $161, %r8d
jmp .LBB1_7
.LBB1_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $162, %r8d
jmp .LBB1_7
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
jmp .LBB1_7
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $164, %r8d
jmp .LBB1_7
.LBB1_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $166, %r8d
jmp .LBB1_7
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePVbPbPiS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePVbPbPiS2_,@object # @_Z6reducePVbPbPiS2_
.section .rodata,"a",@progbits
.globl _Z6reducePVbPbPiS2_
.p2align 3, 0x0
_Z6reducePVbPbPiS2_:
.quad _Z21__device_stub__reducePVbPbPiS2_
.size _Z6reducePVbPbPiS2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate %zu bytes for input!\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate %zu bytes for output!\n"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/maxbaird/appendix/master/a2/reduction_interrupt.hip"
.size .L.str.2, 109
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Interrupt count: %zu\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Result: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "PASS\n"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "FAIL\n"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Sum = %d\n"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6reducePVbPbPiS2_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePVbPbPiS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePVbPbPiS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6reducePVbPbPiS2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R6, SR_CTAID.Z ; /* 0x0000000000067919 */
/* 0x000e280000002700 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000ea80000002200 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea80000002100 */
/*0070*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0080*/ IMAD R5, R6, c[0x0][0x14], R5 ; /* 0x0000050006057a24 */
/* 0x001fc800078e0205 */
/*0090*/ IMAD R5, R5, c[0x0][0xc], R0 ; /* 0x0000030005057a24 */
/* 0x002fca00078e0200 */
/*00a0*/ IADD3 R6, P1, R5, c[0x0][0x168], RZ ; /* 0x00005a0005067a10 */
/* 0x000fca0007f3e0ff */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff077624 */
/* 0x000fe200008e06ff */
/*00c0*/ LOP3.LUT P0, RZ, R4, R3, R2, 0xfe, !PT ; /* 0x0000000304ff7212 */
/* 0x004fc8000780fe02 */
/*00d0*/ LDG.E.U8 R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000eb2000c1e1100 */
/*00e0*/ @!P0 MOV R4, c[0x0][0x160] ; /* 0x0000580000048a02 */
/* 0x000fe20000000f00 */
/*00f0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff058624 */
/* 0x000fca00078e00ff */
/*0100*/ @!P0 LDG.E.S8.STRONG.SYS R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ee2000c1f5300 */
/*0110*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc60003f25270 */
/*0120*/ @!P0 STS [RZ], R4 ; /* 0x00000004ff008388 */
/* 0x0081f40000000800 */
/*0130*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x000e640000000800 */
/*0160*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x002fda0003f05270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0190*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fe400078e0203 */
/*01a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E.U8 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0001e4000c101104 */
/*01c0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0005 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*01f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05270 */
/*0200*/ ISETP.GE.U32.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f26070 */
/*0210*/ STS [R3.X4+0x10], R4 ; /* 0x0000100403007388 */
/* 0x0041e80000004800 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0230*/ @!P1 BRA 0x420 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0240*/ LEA R2, R3, 0x10, 0x2 ; /* 0x0000001003027811 */
/* 0x001fe400078e10ff */
/*0250*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fca0000000f00 */
/*0260*/ IMAD.SHL.U32 R10, R7, 0x2, RZ ; /* 0x00000002070a7824 */
/* 0x000fc800078e00ff */
/*0270*/ I2F.U32.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e220000209000 */
/*0280*/ IADD3 R9, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fca0003f45070 */
/*02a0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*02b0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*02c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*02e0*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*02f0*/ IMAD.HI.U32 R8, R5, R9, R4 ; /* 0x0000000905087227 */
/* 0x000fcc00078e0004 */
/*0300*/ IMAD.HI.U32 R8, R8, R3, RZ ; /* 0x0000000308087227 */
/* 0x000fca00078e00ff */
/*0310*/ IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08087210 */
/* 0x000fca0007ffe1ff */
/*0320*/ IMAD R5, R10, R8, R3 ; /* 0x000000080a057224 */
/* 0x000fca00078e0203 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fda0003f26070 */
/*0340*/ @P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105051824 */
/* 0x000fca00078e0a0a */
/*0350*/ ISETP.GE.U32.AND P1, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fda0003f26070 */
/*0360*/ @P1 IADD3 R5, -R10, R5, RZ ; /* 0x000000050a051210 */
/* 0x000fe40007ffe1ff */
/*0370*/ @!P2 LOP3.LUT R5, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff05a212 */
/* 0x000fc800078e33ff */
/*0380*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0390*/ @!P1 IMAD R4, R7, 0x4, R2 ; /* 0x0000000407049824 */
/* 0x000fe200078e0202 */
/*03a0*/ @!P1 LDS R5, [R3.X4+0x10] ; /* 0x0000100003059984 */
/* 0x000fe20000004800 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fc800078e000a */
/*03c0*/ @!P1 LDS R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000800 */
/*03d0*/ @!P1 IADD3 R6, R5, R4, RZ ; /* 0x0000000405069210 */
/* 0x001fca0007ffe0ff */
/*03e0*/ @!P1 STS [R3.X4+0x10], R6 ; /* 0x0000100603009388 */
/* 0x0001e80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*0410*/ @!P1 BRA 0x260 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*0420*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0430*/ LDS R5, [0x10] ; /* 0x00001000ff057984 */
/* 0x000e220000000800 */
/*0440*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0450*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0003 */
/*0460*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ BRA 0x480; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reducePVbPbPiS2_
.globl _Z6reducePVbPbPiS2_
.p2align 8
.type _Z6reducePVbPbPiS2_,@function
_Z6reducePVbPbPiS2_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s6, s0, 32
s_mov_b32 s4, s13
v_cmp_eq_u32_e64 s2, 0, v1
s_addc_u32 s7, s1, 0
v_or3_b32 v0, v1, v0, v2
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[10:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
flat_load_u8 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[8:9], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s5, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s5, s14
s_mul_i32 s3, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
v_mov_b32_e32 v0, s3
global_load_u8 v0, v0, s[8:9]
s_add_u32 s8, s8, s3
s_addc_u32 s9, s9, 0
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v0
s_cbranch_vccz .LBB0_4
.LBB0_3:
s_endpgm
.LBB0_4:
v_mov_b32_e32 v0, 0
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v0
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v2, 1
s_mov_b32 s5, 1
global_store_b8 v0, v2, s[8:9]
s_load_b32 s3, s[6:7], 0xc
s_load_b64 s[6:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s4, s3, v[1:2]
v_mov_b32_e32 v3, v0
v_lshl_add_u32 v0, v1, 2, 4
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_ge_u32 s6, s3
s_mov_b32 s5, s6
.LBB0_7:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
s_lshl_b32 s6, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s6, -1
v_and_b32_e32 v2, s7, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v2, s5, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 4
ds_load_b32 v2, v2
ds_load_b32 v3, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v0, v2
s_branch .LBB0_6
.LBB0_10:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePVbPbPiS2_
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reducePVbPbPiS2_, .Lfunc_end0-_Z6reducePVbPbPiS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePVbPbPiS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePVbPbPiS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6629_00000000-6_reduction_interrupt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2070:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
.type _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_, @function
_Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePVbPbPiS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_, .-_Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
.globl _Z6reducePVbPbPiS2_
.type _Z6reducePVbPbPiS2_, @function
_Z6reducePVbPbPiS2_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z6reducePVbPbPiS2_, .-_Z6reducePVbPbPiS2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate %zu bytes for input!\n"
.align 8
.LC2:
.string "Failed to allocate %zu bytes for output!\n"
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/maxbaird/appendix/master/a2/reduction_interrupt.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Result: "
.LC5:
.string "PASS\n"
.LC6:
.string "FAIL\n"
.LC7:
.string "Sum = %d\n"
.LC8:
.string "Interrupt count: %zu\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
testq %rbp, %rbp
je .L40
movq %rax, %rbx
testq %rax, %rax
je .L41
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $92, %edx
leaq .LC3(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $93, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq %rbp, %rax
leaq 4194304(%rbp), %rdx
.L22:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $1, %edx
movl $1, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
movq 24(%rsp), %rax
movq $0, (%rax)
movq $0, 1016(%rax)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
leal 1024(%rax), %ecx
shrl $3, %ecx
movl %ecx, %ecx
movl $0, %eax
rep stosq
movq 16(%rsp), %rax
movb $0, (%rax)
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $113, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %r13d
.L32:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L23:
call cudaPeekAtLastError@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L43
movl $0, %edi
call usleep@PLT
movq 16(%rsp), %rax
movb $1, (%rax)
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L44
movq 24(%rsp), %rdx
movl $0, %eax
.L27:
cmpb $0, (%rdx,%rax)
je .L26
addq $1, %rax
cmpq $1024, %rax
jne .L27
leaq 1(%r13), %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $140, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 4(%rbx), %rax
leaq 4096(%rbx), %rcx
.L29:
movl (%rax), %edx
addl %edx, (%rbx)
addq $4, %rax
cmpq %rcx, %rax
jne .L29
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $1048576, (%rbx)
je .L45
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L31:
movl (%rbx), %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $159, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $160, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $161, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $162, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceReset@PLT
movl %eax, %edi
movl $1, %ecx
movl $164, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $4194304, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl $4096, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z6reducePVbPbPiS2_PVbPbPiS2_
jmp .L23
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $117, %r9d
leaq .LC3(%rip), %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC3(%rip), %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L45:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L31
.L26:
addq $1, %r13
movq 16(%rsp), %rax
movb $0, (%rax)
jmp .L32
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6reducePVbPbPiS2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePVbPbPiS2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction_interrupt.hip"
.globl _Z21__device_stub__reducePVbPbPiS2_ # -- Begin function _Z21__device_stub__reducePVbPbPiS2_
.p2align 4, 0x90
.type _Z21__device_stub__reducePVbPbPiS2_,@function
_Z21__device_stub__reducePVbPbPiS2_: # @_Z21__device_stub__reducePVbPbPiS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePVbPbPiS2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePVbPbPiS2_, .Lfunc_end0-_Z21__device_stub__reducePVbPbPiS2_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
testq %rbx, %rbx
je .LBB1_1
# %bb.3:
movq %rax, %r15
testq %rax, %rax
je .LBB1_4
# %bb.5:
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_47
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit51.preheader
movl $1024, %r14d # imm = 0x400
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_10: # %_Z9gpuAssert10hipError_tPKcib.exit51
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_10
# %bb.11:
movq %r15, 40(%rsp) # 8-byte Spill
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $1, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq memset@PLT
movq (%rsp), %rax
movb $0, (%rax)
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, 32(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit53.preheader
movabsq $4294967296, %r15 # imm = 0x100000000
leaq (%r14,%r15), %r12
xorl %ebx, %ebx
addq $1024, %r15 # imm = 0x400
xorl %r13d, %r13d
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_27: # %_Z9gpuAssert10hipError_tPKcib.exit53
# in Loop: Header=BB1_13 Depth=1
incq %r13
movl %ecx, %ebx
testb $1, %cl
jne .LBB1_28
.LBB1_13: # =>This Loop Header: Depth=1
# Child Loop BB1_22 Depth 2
movl $4096, %r8d # imm = 0x1000
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z6reducePVbPbPiS2_, %edi
leaq 128(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15: # in Loop: Header=BB1_13 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit55
# in Loop: Header=BB1_13 Depth=1
xorl %edi, %edi
callq usleep
movq (%rsp), %rax
movb $1, (%rax)
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_20
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit57.preheader
# in Loop: Header=BB1_13 Depth=1
testq %r14, %r14
je .LBB1_19
# %bb.21: # %.lr.ph
# in Loop: Header=BB1_13 Depth=1
movq 8(%rsp), %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_22: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rcx,%rax)
je .LBB1_25
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit57
# in Loop: Header=BB1_22 Depth=2
incq %rax
cmpq %rax, %r14
jne .LBB1_22
# %bb.24: # in Loop: Header=BB1_13 Depth=1
movl $1024, %eax # imm = 0x400
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_13 Depth=1
xorl %eax, %eax
.LBB1_25: # %._crit_edge
# in Loop: Header=BB1_13 Depth=1
movb $1, %cl
cmpq %r14, %rax
je .LBB1_27
# %bb.26: # in Loop: Header=BB1_13 Depth=1
movq (%rsp), %rax
movb $0, (%rax)
movl %ebx, %ecx
jmp .LBB1_27
.LBB1_28:
movq stdout(%rip), %rdi
movl $.L.str.3, %esi
movq %r13, %rdx
xorl %eax, %eax
callq fprintf
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_49
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit59.preheader
cmpl $2, %r14d
movq 32(%rsp), %rbx # 8-byte Reload
jb .LBB1_33
# %bb.30: # %.lr.ph83
movl (%r15), %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB1_31: # %_Z9gpuAssert10hipError_tPKcib.exit59
# =>This Inner Loop Header: Depth=1
addl (%r15,%rcx,4), %eax
incq %rcx
cmpq %rcx, %r14
jne .LBB1_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit59._crit_edge.loopexit
movl %eax, (%r15)
.LBB1_33: # %_Z9gpuAssert10hipError_tPKcib.exit59._crit_edge
movq stdout(%rip), %rcx
movl $.L.str.4, %edi
movl $8, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $1048576, (%r15) # imm = 0x100000
jne .LBB1_35
# %bb.34:
movq stdout(%rip), %rcx
movl $.L.str.5, %edi
.LBB1_36:
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl (%r15), %edx
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_37
# %bb.38: # %_Z9gpuAssert10hipError_tPKcib.exit61
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_39
# %bb.40: # %_Z9gpuAssert10hipError_tPKcib.exit63
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_41
# %bb.42: # %_Z9gpuAssert10hipError_tPKcib.exit65
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.44: # %_Z9gpuAssert10hipError_tPKcib.exit67
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_45
# %bb.46: # %_Z9gpuAssert10hipError_tPKcib.exit69
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_35:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB1_36
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB1_7
.LBB1_16:
movl %eax, %ebp
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $119, %r8d
.LBB1_7:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB1_1:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl $4194304, %edx # imm = 0x400000
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movl $4096, %edx # imm = 0x1000
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $94, %r8d
jmp .LBB1_7
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $95, %r8d
jmp .LBB1_7
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB1_7
.LBB1_49:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $142, %r8d
jmp .LBB1_7
.LBB1_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $161, %r8d
jmp .LBB1_7
.LBB1_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $162, %r8d
jmp .LBB1_7
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
jmp .LBB1_7
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $164, %r8d
jmp .LBB1_7
.LBB1_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $166, %r8d
jmp .LBB1_7
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePVbPbPiS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePVbPbPiS2_,@object # @_Z6reducePVbPbPiS2_
.section .rodata,"a",@progbits
.globl _Z6reducePVbPbPiS2_
.p2align 3, 0x0
_Z6reducePVbPbPiS2_:
.quad _Z21__device_stub__reducePVbPbPiS2_
.size _Z6reducePVbPbPiS2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate %zu bytes for input!\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate %zu bytes for output!\n"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/maxbaird/appendix/master/a2/reduction_interrupt.hip"
.size .L.str.2, 109
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Interrupt count: %zu\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Result: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "PASS\n"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "FAIL\n"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Sum = %d\n"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6reducePVbPbPiS2_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePVbPbPiS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePVbPbPiS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
const int N = 7;
const int blocksize = 7;
__global__ void hello(char *a, int *b)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x; // Finds the thread_id
//a[threadIdx.x] += b[threadIdx.x];
a[idx] += b[idx];
printf("yan yan yan! \n");
}
int main()
{
char a[N] = "Hello ";
int b[N] = {15, 10, 6, 0, -11, 1};
char *ad;
int *bd;
const int csize = N*sizeof(char);
const int isize = N*sizeof(int);
printf("The original string: %s\n", a);
cudaMalloc( (void**)&ad, csize );
cudaMalloc( (void**)&bd, isize );
cudaMemcpy( ad, a, csize, cudaMemcpyHostToDevice );
cudaMemcpy( bd, b, isize, cudaMemcpyHostToDevice );
dim3 Block( 1, 1 ); // Number of threads per block
dim3 Grid( blocksize, 1 ); // Number of thread blocks
hello<<<Grid, Block>>>(ad, bd);
cudaMemcpy( a, ad, csize, cudaMemcpyDeviceToHost );
cudaFree( ad );
cudaFree( bd );
printf("The modified string: %s\n", a);
return 0;
} | code for sm_80
Function : _Z5helloPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0060*/ IADD3 R8, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x040fe20007f1e0ff */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0203 */
/*0080*/ LEA.HI.X.SX32 R9, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000097a11 */
/* 0x000fc600000f0eff */
/*0090*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1100 */
/*00a0*/ LDG.E.U8 R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00f0*/ LDC.64 R12, c[0x4][R0] ; /* 0x01000000000c7b82 */
/* 0x0000620000000a00 */
/*0100*/ IMAD.IADD R11, R11, 0x1, R2 ; /* 0x000000010b0b7824 */
/* 0x004fca00078e0202 */
/*0110*/ STG.E.U8 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e4000c101104 */
/*0120*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*0130*/ MOV R9, 0x1a0 ; /* 0x000001a000097802 */
/* 0x001fe40000000f00 */
/*0140*/ MOV R20, 0x120 ; /* 0x0000012000147802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0170*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0180*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0190*/ CALL.ABS.NOINC R12 ; /* 0x000000000c007343 */
/* 0x000fea0003c00000 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
const int N = 7;
const int blocksize = 7;
__global__ void hello(char *a, int *b)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x; // Finds the thread_id
//a[threadIdx.x] += b[threadIdx.x];
a[idx] += b[idx];
printf("yan yan yan! \n");
}
int main()
{
char a[N] = "Hello ";
int b[N] = {15, 10, 6, 0, -11, 1};
char *ad;
int *bd;
const int csize = N*sizeof(char);
const int isize = N*sizeof(int);
printf("The original string: %s\n", a);
cudaMalloc( (void**)&ad, csize );
cudaMalloc( (void**)&bd, isize );
cudaMemcpy( ad, a, csize, cudaMemcpyHostToDevice );
cudaMemcpy( bd, b, isize, cudaMemcpyHostToDevice );
dim3 Block( 1, 1 ); // Number of threads per block
dim3 Grid( blocksize, 1 ); // Number of thread blocks
hello<<<Grid, Block>>>(ad, bd);
cudaMemcpy( a, ad, csize, cudaMemcpyDeviceToHost );
cudaFree( ad );
cudaFree( bd );
printf("The modified string: %s\n", a);
return 0;
} | .file "tmpxft_0005c77b_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5helloPcPiPcPi
.type _Z26__device_stub__Z5helloPcPiPcPi, @function
_Z26__device_stub__Z5helloPcPiPcPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5helloPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5helloPcPiPcPi, .-_Z26__device_stub__Z5helloPcPiPcPi
.globl _Z5helloPcPi
.type _Z5helloPcPi, @function
_Z5helloPcPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5helloPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5helloPcPi, .-_Z5helloPcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The original string: %s\n"
.LC1:
.string "The modified string: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1819043144, 81(%rsp)
movl $2125676, 84(%rsp)
movq $0, 60(%rsp)
movq $0, 68(%rsp)
movl $15, 48(%rsp)
movl $10, 52(%rsp)
movl $6, 56(%rsp)
movl $-11, 64(%rsp)
movl $1, 68(%rsp)
leaq 81(%rsp), %rbx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $7, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $7, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $28, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $7, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 81(%rsp), %rbx
movl $2, %ecx
movl $7, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5helloPcPiPcPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5helloPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5helloPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
const int N = 7;
const int blocksize = 7;
__global__ void hello(char *a, int *b)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x; // Finds the thread_id
//a[threadIdx.x] += b[threadIdx.x];
a[idx] += b[idx];
printf("yan yan yan! \n");
}
int main()
{
char a[N] = "Hello ";
int b[N] = {15, 10, 6, 0, -11, 1};
char *ad;
int *bd;
const int csize = N*sizeof(char);
const int isize = N*sizeof(int);
printf("The original string: %s\n", a);
cudaMalloc( (void**)&ad, csize );
cudaMalloc( (void**)&bd, isize );
cudaMemcpy( ad, a, csize, cudaMemcpyHostToDevice );
cudaMemcpy( bd, b, isize, cudaMemcpyHostToDevice );
dim3 Block( 1, 1 ); // Number of threads per block
dim3 Grid( blocksize, 1 ); // Number of thread blocks
hello<<<Grid, Block>>>(ad, bd);
cudaMemcpy( a, ad, csize, cudaMemcpyDeviceToHost );
cudaFree( ad );
cudaFree( bd );
printf("The modified string: %s\n", a);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
const int N = 7;
const int blocksize = 7;
__global__ void hello(char *a, int *b)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x; // Finds the thread_id
//a[threadIdx.x] += b[threadIdx.x];
a[idx] += b[idx];
printf("yan yan yan! \n");
}
int main()
{
char a[N] = "Hello ";
int b[N] = {15, 10, 6, 0, -11, 1};
char *ad;
int *bd;
const int csize = N*sizeof(char);
const int isize = N*sizeof(int);
printf("The original string: %s\n", a);
hipMalloc( (void**)&ad, csize );
hipMalloc( (void**)&bd, isize );
hipMemcpy( ad, a, csize, hipMemcpyHostToDevice );
hipMemcpy( bd, b, isize, hipMemcpyHostToDevice );
dim3 Block( 1, 1 ); // Number of threads per block
dim3 Grid( blocksize, 1 ); // Number of thread blocks
hello<<<Grid, Block>>>(ad, bd);
hipMemcpy( a, ad, csize, hipMemcpyDeviceToHost );
hipFree( ad );
hipFree( bd );
printf("The modified string: %s\n", a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
const int N = 7;
const int blocksize = 7;
__global__ void hello(char *a, int *b)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x; // Finds the thread_id
//a[threadIdx.x] += b[threadIdx.x];
a[idx] += b[idx];
printf("yan yan yan! \n");
}
int main()
{
char a[N] = "Hello ";
int b[N] = {15, 10, 6, 0, -11, 1};
char *ad;
int *bd;
const int csize = N*sizeof(char);
const int isize = N*sizeof(int);
printf("The original string: %s\n", a);
hipMalloc( (void**)&ad, csize );
hipMalloc( (void**)&bd, isize );
hipMemcpy( ad, a, csize, hipMemcpyHostToDevice );
hipMemcpy( bd, b, isize, hipMemcpyHostToDevice );
dim3 Block( 1, 1 ); // Number of threads per block
dim3 Grid( blocksize, 1 ); // Number of thread blocks
hello<<<Grid, Block>>>(ad, bd);
hipMemcpy( a, ad, csize, hipMemcpyDeviceToHost );
hipFree( ad );
hipFree( bd );
printf("The modified string: %s\n", a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5helloPcPi
.globl _Z5helloPcPi
.p2align 8
.type _Z5helloPcPi,@function
_Z5helloPcPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v0, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
global_load_u8 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v2, v4, v2
v_mov_b32_e32 v4, v20
global_store_b8 v[0:1], v2, off
s_load_b64 s[2:3], s[0:1], 0x60
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 15
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5helloPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5helloPcPi, .Lfunc_end0-_Z5helloPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "yan yan yan! \n"
.size .str, 15
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 96
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5helloPcPi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5helloPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
const int N = 7;
const int blocksize = 7;
__global__ void hello(char *a, int *b)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x; // Finds the thread_id
//a[threadIdx.x] += b[threadIdx.x];
a[idx] += b[idx];
printf("yan yan yan! \n");
}
int main()
{
char a[N] = "Hello ";
int b[N] = {15, 10, 6, 0, -11, 1};
char *ad;
int *bd;
const int csize = N*sizeof(char);
const int isize = N*sizeof(int);
printf("The original string: %s\n", a);
hipMalloc( (void**)&ad, csize );
hipMalloc( (void**)&bd, isize );
hipMemcpy( ad, a, csize, hipMemcpyHostToDevice );
hipMemcpy( bd, b, isize, hipMemcpyHostToDevice );
dim3 Block( 1, 1 ); // Number of threads per block
dim3 Grid( blocksize, 1 ); // Number of thread blocks
hello<<<Grid, Block>>>(ad, bd);
hipMemcpy( a, ad, csize, hipMemcpyDeviceToHost );
hipFree( ad );
hipFree( bd );
printf("The modified string: %s\n", a);
return 0;
} | .text
.file "hello.hip"
.globl _Z20__device_stub__helloPcPi # -- Begin function _Z20__device_stub__helloPcPi
.p2align 4, 0x90
.type _Z20__device_stub__helloPcPi,@function
_Z20__device_stub__helloPcPi: # @_Z20__device_stub__helloPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5helloPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__helloPcPi, .Lfunc_end0-_Z20__device_stub__helloPcPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 15 # 0xf
.long 10 # 0xa
.long 6 # 0x6
.long 0 # 0x0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movl $1819043144, 9(%rsp) # imm = 0x6C6C6548
movw $8303, 13(%rsp) # imm = 0x206F
movb $0, 15(%rsp)
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [15,10,6,0]
movaps %xmm0, 112(%rsp)
movabsq $8589934581, %rax # imm = 0x1FFFFFFF5
movq %rax, 128(%rsp)
movl $0, 136(%rsp)
leaq 9(%rsp), %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $7, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $28, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $7, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $28, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 6(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5helloPcPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 9(%rsp), %rbx
movl $7, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5helloPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5helloPcPi,@object # @_Z5helloPcPi
.section .rodata,"a",@progbits
.globl _Z5helloPcPi
.p2align 3, 0x0
_Z5helloPcPi:
.quad _Z20__device_stub__helloPcPi
.size _Z5helloPcPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The original string: %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The modified string: %s\n"
.size .L.str.1, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5helloPcPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__helloPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5helloPcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005c77b_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5helloPcPiPcPi
.type _Z26__device_stub__Z5helloPcPiPcPi, @function
_Z26__device_stub__Z5helloPcPiPcPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5helloPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5helloPcPiPcPi, .-_Z26__device_stub__Z5helloPcPiPcPi
.globl _Z5helloPcPi
.type _Z5helloPcPi, @function
_Z5helloPcPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5helloPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5helloPcPi, .-_Z5helloPcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The original string: %s\n"
.LC1:
.string "The modified string: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1819043144, 81(%rsp)
movl $2125676, 84(%rsp)
movq $0, 60(%rsp)
movq $0, 68(%rsp)
movl $15, 48(%rsp)
movl $10, 52(%rsp)
movl $6, 56(%rsp)
movl $-11, 64(%rsp)
movl $1, 68(%rsp)
leaq 81(%rsp), %rbx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $7, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $7, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $28, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $7, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 81(%rsp), %rbx
movl $2, %ecx
movl $7, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5helloPcPiPcPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5helloPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5helloPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z20__device_stub__helloPcPi # -- Begin function _Z20__device_stub__helloPcPi
.p2align 4, 0x90
.type _Z20__device_stub__helloPcPi,@function
_Z20__device_stub__helloPcPi: # @_Z20__device_stub__helloPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5helloPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__helloPcPi, .Lfunc_end0-_Z20__device_stub__helloPcPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 15 # 0xf
.long 10 # 0xa
.long 6 # 0x6
.long 0 # 0x0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movl $1819043144, 9(%rsp) # imm = 0x6C6C6548
movw $8303, 13(%rsp) # imm = 0x206F
movb $0, 15(%rsp)
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [15,10,6,0]
movaps %xmm0, 112(%rsp)
movabsq $8589934581, %rax # imm = 0x1FFFFFFF5
movq %rax, 128(%rsp)
movl $0, 136(%rsp)
leaq 9(%rsp), %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $7, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $28, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $7, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $28, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 6(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5helloPcPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 9(%rsp), %rbx
movl $7, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5helloPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5helloPcPi,@object # @_Z5helloPcPi
.section .rodata,"a",@progbits
.globl _Z5helloPcPi
.p2align 3, 0x0
_Z5helloPcPi:
.quad _Z20__device_stub__helloPcPi
.size _Z5helloPcPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The original string: %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The modified string: %s\n"
.size .L.str.1, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5helloPcPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__helloPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5helloPcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | struct Real3
{
double value[3];
};
template<class T1, class T2>
struct Pair
{
T1 first;
T2 second;
template<class U1, class U2>
__device__ Pair& operator=(const Pair<U1, U2>& other)
{
first = other.first;
second = other.second;
return *this;
}
};
template<class T1, class T2>
inline __device__ Pair<T1&,T2&> pair_tie(T1& first, T2& second)
{
return {first, second};
}
__device__ Pair<Real3, Real3> copy(const Real3& in1, const Real3& in2)
{
return {in1, in2};
}
__global__ void call_min(int* offsets, const Real3* inputs, Real3* outputs)
{
int idx = offsets[threadIdx.x];
// Copy with some bogus offsets
pair_tie(outputs[idx - 1], outputs[idx])
= copy(inputs[idx], inputs[idx + 1]);
} | code for sm_80
Function : _Z8call_minPiPK5Real3PS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0003 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ HFMA2.MMA R19, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff137435 */
/* 0x000fd400000001ff */
/*0070*/ IMAD.WIDE R4, R2, R19, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fca00078e0213 */
/*0080*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ee8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000f28000c1e1b00 */
/*00b0*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1b00 */
/*00c0*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000f68000c1e1b00 */
/*00d0*/ LDG.E.64 R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000f62000c1e1b00 */
/*00e0*/ IMAD.WIDE R18, R2, R19, c[0x0][0x170] ; /* 0x00005c0002127625 */
/* 0x000fca00078e0213 */
/*00f0*/ STG.E.64 [R18.64+-0x18], R6 ; /* 0xffffe80612007986 */
/* 0x004fe8000c101b04 */
/*0100*/ STG.E.64 [R18.64+-0x10], R8 ; /* 0xfffff00812007986 */
/* 0x008fe8000c101b04 */
/*0110*/ STG.E.64 [R18.64+-0x8], R10 ; /* 0xfffff80a12007986 */
/* 0x010fe8000c101b04 */
/*0120*/ STG.E.64 [R18.64], R12 ; /* 0x0000000c12007986 */
/* 0x020fe8000c101b04 */
/*0130*/ STG.E.64 [R18.64+0x8], R14 ; /* 0x0000080e12007986 */
/* 0x000fe8000c101b04 */
/*0140*/ STG.E.64 [R18.64+0x10], R16 ; /* 0x0000101012007986 */
/* 0x000fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | struct Real3
{
double value[3];
};
template<class T1, class T2>
struct Pair
{
T1 first;
T2 second;
template<class U1, class U2>
__device__ Pair& operator=(const Pair<U1, U2>& other)
{
first = other.first;
second = other.second;
return *this;
}
};
template<class T1, class T2>
inline __device__ Pair<T1&,T2&> pair_tie(T1& first, T2& second)
{
return {first, second};
}
__device__ Pair<Real3, Real3> copy(const Real3& in1, const Real3& in2)
{
return {in1, in2};
}
__global__ void call_min(int* offsets, const Real3* inputs, Real3* outputs)
{
int idx = offsets[threadIdx.x];
// Copy with some bogus offsets
pair_tie(outputs[idx - 1], outputs[idx])
= copy(inputs[idx], inputs[idx + 1]);
} | .file "tmpxft_001071af_00000000-6_tie.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4copyRK5Real3S1_
.type _Z4copyRK5Real3S1_, @function
_Z4copyRK5Real3S1_:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z4copyRK5Real3S1_, .-_Z4copyRK5Real3S1_
.globl _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_
.type _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_, @function
_Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_:
.LFB2054:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8call_minPiPK5Real3PS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_, .-_Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_
.globl _Z8call_minPiPK5Real3PS0_
.type _Z8call_minPiPK5Real3PS0_, @function
_Z8call_minPiPK5Real3PS0_:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z8call_minPiPK5Real3PS0_, .-_Z8call_minPiPK5Real3PS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8call_minPiPK5Real3PS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8call_minPiPK5Real3PS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | struct Real3
{
double value[3];
};
template<class T1, class T2>
struct Pair
{
T1 first;
T2 second;
template<class U1, class U2>
__device__ Pair& operator=(const Pair<U1, U2>& other)
{
first = other.first;
second = other.second;
return *this;
}
};
template<class T1, class T2>
inline __device__ Pair<T1&,T2&> pair_tie(T1& first, T2& second)
{
return {first, second};
}
__device__ Pair<Real3, Real3> copy(const Real3& in1, const Real3& in2)
{
return {in1, in2};
}
__global__ void call_min(int* offsets, const Real3* inputs, Real3* outputs)
{
int idx = offsets[threadIdx.x];
// Copy with some bogus offsets
pair_tie(outputs[idx - 1], outputs[idx])
= copy(inputs[idx], inputs[idx + 1]);
} | #include <hip/hip_runtime.h>
struct Real3
{
double value[3];
};
template<class T1, class T2>
struct Pair
{
T1 first;
T2 second;
template<class U1, class U2>
__device__ Pair& operator=(const Pair<U1, U2>& other)
{
first = other.first;
second = other.second;
return *this;
}
};
template<class T1, class T2>
inline __device__ Pair<T1&,T2&> pair_tie(T1& first, T2& second)
{
return {first, second};
}
__device__ Pair<Real3, Real3> copy(const Real3& in1, const Real3& in2)
{
return {in1, in2};
}
__global__ void call_min(int* offsets, const Real3* inputs, Real3* outputs)
{
int idx = offsets[threadIdx.x];
// Copy with some bogus offsets
pair_tie(outputs[idx - 1], outputs[idx])
= copy(inputs[idx], inputs[idx + 1]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
struct Real3
{
double value[3];
};
template<class T1, class T2>
struct Pair
{
T1 first;
T2 second;
template<class U1, class U2>
__device__ Pair& operator=(const Pair<U1, U2>& other)
{
first = other.first;
second = other.second;
return *this;
}
};
template<class T1, class T2>
inline __device__ Pair<T1&,T2&> pair_tie(T1& first, T2& second)
{
return {first, second};
}
__device__ Pair<Real3, Real3> copy(const Real3& in1, const Real3& in2)
{
return {in1, in2};
}
__global__ void call_min(int* offsets, const Real3* inputs, Real3* outputs)
{
int idx = offsets[threadIdx.x];
// Copy with some bogus offsets
pair_tie(outputs[idx - 1], outputs[idx])
= copy(inputs[idx], inputs[idx + 1]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8call_minPiPK5Real3PS0_
.globl _Z8call_minPiPK5Real3PS0_
.p2align 8
.type _Z8call_minPiPK5Real3PS0_,@function
_Z8call_minPiPK5Real3PS0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v14, v0, s[4:5]
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[8:9], null, v14, 24, s[6:7]
v_mad_i64_i32 v[12:13], null, v14, 24, s[0:1]
s_clause 0x2
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[8:9], off offset:16
global_load_b128 v[8:11], v[8:9], off offset:32
s_waitcnt vmcnt(2)
global_store_b128 v[12:13], v[0:3], off offset:-24
s_waitcnt vmcnt(1)
global_store_b128 v[12:13], v[4:7], off offset:-8
s_waitcnt vmcnt(0)
global_store_b128 v[12:13], v[8:11], off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8call_minPiPK5Real3PS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8call_minPiPK5Real3PS0_, .Lfunc_end0-_Z8call_minPiPK5Real3PS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8call_minPiPK5Real3PS0_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8call_minPiPK5Real3PS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
struct Real3
{
double value[3];
};
template<class T1, class T2>
struct Pair
{
T1 first;
T2 second;
template<class U1, class U2>
__device__ Pair& operator=(const Pair<U1, U2>& other)
{
first = other.first;
second = other.second;
return *this;
}
};
template<class T1, class T2>
inline __device__ Pair<T1&,T2&> pair_tie(T1& first, T2& second)
{
return {first, second};
}
__device__ Pair<Real3, Real3> copy(const Real3& in1, const Real3& in2)
{
return {in1, in2};
}
__global__ void call_min(int* offsets, const Real3* inputs, Real3* outputs)
{
int idx = offsets[threadIdx.x];
// Copy with some bogus offsets
pair_tie(outputs[idx - 1], outputs[idx])
= copy(inputs[idx], inputs[idx + 1]);
} | .text
.file "tie.hip"
.globl _Z23__device_stub__call_minPiPK5Real3PS0_ # -- Begin function _Z23__device_stub__call_minPiPK5Real3PS0_
.p2align 4, 0x90
.type _Z23__device_stub__call_minPiPK5Real3PS0_,@function
_Z23__device_stub__call_minPiPK5Real3PS0_: # @_Z23__device_stub__call_minPiPK5Real3PS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8call_minPiPK5Real3PS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__call_minPiPK5Real3PS0_, .Lfunc_end0-_Z23__device_stub__call_minPiPK5Real3PS0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8call_minPiPK5Real3PS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8call_minPiPK5Real3PS0_,@object # @_Z8call_minPiPK5Real3PS0_
.section .rodata,"a",@progbits
.globl _Z8call_minPiPK5Real3PS0_
.p2align 3, 0x0
_Z8call_minPiPK5Real3PS0_:
.quad _Z23__device_stub__call_minPiPK5Real3PS0_
.size _Z8call_minPiPK5Real3PS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8call_minPiPK5Real3PS0_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__call_minPiPK5Real3PS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8call_minPiPK5Real3PS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8call_minPiPK5Real3PS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fcc00078e0003 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ HFMA2.MMA R19, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff137435 */
/* 0x000fd400000001ff */
/*0070*/ IMAD.WIDE R4, R2, R19, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fca00078e0213 */
/*0080*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ee8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000f28000c1e1b00 */
/*00b0*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1b00 */
/*00c0*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000f68000c1e1b00 */
/*00d0*/ LDG.E.64 R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000f62000c1e1b00 */
/*00e0*/ IMAD.WIDE R18, R2, R19, c[0x0][0x170] ; /* 0x00005c0002127625 */
/* 0x000fca00078e0213 */
/*00f0*/ STG.E.64 [R18.64+-0x18], R6 ; /* 0xffffe80612007986 */
/* 0x004fe8000c101b04 */
/*0100*/ STG.E.64 [R18.64+-0x10], R8 ; /* 0xfffff00812007986 */
/* 0x008fe8000c101b04 */
/*0110*/ STG.E.64 [R18.64+-0x8], R10 ; /* 0xfffff80a12007986 */
/* 0x010fe8000c101b04 */
/*0120*/ STG.E.64 [R18.64], R12 ; /* 0x0000000c12007986 */
/* 0x020fe8000c101b04 */
/*0130*/ STG.E.64 [R18.64+0x8], R14 ; /* 0x0000080e12007986 */
/* 0x000fe8000c101b04 */
/*0140*/ STG.E.64 [R18.64+0x10], R16 ; /* 0x0000101012007986 */
/* 0x000fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8call_minPiPK5Real3PS0_
.globl _Z8call_minPiPK5Real3PS0_
.p2align 8
.type _Z8call_minPiPK5Real3PS0_,@function
_Z8call_minPiPK5Real3PS0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v14, v0, s[4:5]
s_waitcnt vmcnt(0)
v_mad_i64_i32 v[8:9], null, v14, 24, s[6:7]
v_mad_i64_i32 v[12:13], null, v14, 24, s[0:1]
s_clause 0x2
global_load_b128 v[0:3], v[8:9], off
global_load_b128 v[4:7], v[8:9], off offset:16
global_load_b128 v[8:11], v[8:9], off offset:32
s_waitcnt vmcnt(2)
global_store_b128 v[12:13], v[0:3], off offset:-24
s_waitcnt vmcnt(1)
global_store_b128 v[12:13], v[4:7], off offset:-8
s_waitcnt vmcnt(0)
global_store_b128 v[12:13], v[8:11], off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8call_minPiPK5Real3PS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8call_minPiPK5Real3PS0_, .Lfunc_end0-_Z8call_minPiPK5Real3PS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8call_minPiPK5Real3PS0_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8call_minPiPK5Real3PS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001071af_00000000-6_tie.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4copyRK5Real3S1_
.type _Z4copyRK5Real3S1_, @function
_Z4copyRK5Real3S1_:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z4copyRK5Real3S1_, .-_Z4copyRK5Real3S1_
.globl _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_
.type _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_, @function
_Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_:
.LFB2054:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8call_minPiPK5Real3PS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_, .-_Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_
.globl _Z8call_minPiPK5Real3PS0_
.type _Z8call_minPiPK5Real3PS0_, @function
_Z8call_minPiPK5Real3PS0_:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z8call_minPiPK5Real3PS0_PiPK5Real3PS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z8call_minPiPK5Real3PS0_, .-_Z8call_minPiPK5Real3PS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8call_minPiPK5Real3PS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8call_minPiPK5Real3PS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tie.hip"
.globl _Z23__device_stub__call_minPiPK5Real3PS0_ # -- Begin function _Z23__device_stub__call_minPiPK5Real3PS0_
.p2align 4, 0x90
.type _Z23__device_stub__call_minPiPK5Real3PS0_,@function
_Z23__device_stub__call_minPiPK5Real3PS0_: # @_Z23__device_stub__call_minPiPK5Real3PS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8call_minPiPK5Real3PS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__call_minPiPK5Real3PS0_, .Lfunc_end0-_Z23__device_stub__call_minPiPK5Real3PS0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8call_minPiPK5Real3PS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8call_minPiPK5Real3PS0_,@object # @_Z8call_minPiPK5Real3PS0_
.section .rodata,"a",@progbits
.globl _Z8call_minPiPK5Real3PS0_
.p2align 3, 0x0
_Z8call_minPiPK5Real3PS0_:
.quad _Z23__device_stub__call_minPiPK5Real3PS0_
.size _Z8call_minPiPK5Real3PS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8call_minPiPK5Real3PS0_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__call_minPiPK5Real3PS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8call_minPiPK5Real3PS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Francisco Rodriguez Jimenez
cazz@correo.ugr.es
nvcc - The NVIDIA CUDA Compiler
cuobjdump - The NVIDIA CUDA Object Utility
nvdisasm - The NVIDIA CUDA disassembler
nvprune - The NVIDIA CUDA Prune Tool
nsight - NVIDIA NSight, Eclipse Edition
nvvp - The NVIDIA CUDA Visual Profiler
nvprof - The NVIDIA CUDA Command-Line Profiler
cuda-memcheck - The NVIDIA CUDA Check Tool
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include "cuda_runtime.h"
using namespace std;
__host__ void check_CUDA_Error(const char *mensaje){
cudaError_t error;
cudaDeviceSynchronize();
error = cudaGetLastError();
if(error != cudaSuccess){
printf("ERROR %d: %s (%s)\n", error, cudaGetErrorString(error), mensaje);
exit(EXIT_FAILURE);
}
}
__global__ void reduceSum(int *d_V, int *Out, int N, int smen){
extern __shared__ int sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockDim.x*2) + threadIdx.x;
// printf("\nTAM MEMORIA: %d | tid: %d -> id: %d",smen, tid, i);
sdata[tid] = ((i < N/2) ? d_V[i] + d_V[i+blockDim.x] : 0.0f);
__syncthreads();
for (int s = (blockDim.x/2); s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0){
Out[blockIdx.x] = sdata[0];
}
}
int main(int argc, char** argv){
if(argc != 2){
cout << "Error de sintaxis: ejer8 <TAM>" << endl;
return(EXIT_FAILURE);
}
const int TAM = atoi(argv[1]);
//Punteros memoria host
int *vector_entrada, *host_o;
//Punteros memoria device
int *device_i, *device_o;
//Reserva de memoria host
vector_entrada = new int[TAM];
//Reserva de memoria device
cudaMalloc((void **) &device_i, TAM * sizeof(int));
check_CUDA_Error("Error en la reserva del device");
//Inicialización vector
for(int i = 0 ; i < TAM; ++i){
vector_entrada[i] = 1;
}
cout << "VECTOR ENTRADA: " << endl;
for(int i = 0 ; i < TAM; ++i){
cout << vector_entrada[i] << " ";
}
//Copia de host a device
cudaMemcpy(device_i, vector_entrada, sizeof(int)*TAM, cudaMemcpyHostToDevice);
check_CUDA_Error("Errir en la copia del host al device");
//Preparo y lanzo el kernel
dim3 threadsPerBlock(TAM);
dim3 numBlocks(ceil((float)TAM / threadsPerBlock.x));
int smemSize = threadsPerBlock.x * sizeof(int);
cudaMalloc((void **) &device_o, numBlocks.x * sizeof(int));
host_o = new int[numBlocks.x];
reduceSum<<<numBlocks, threadsPerBlock, smemSize>>>(device_i, device_o, TAM, threadsPerBlock.x);
cudaDeviceSynchronize();
//Copio el resultado de device a host
cudaMemcpy(host_o, device_o, sizeof(int)*numBlocks.x, cudaMemcpyDeviceToHost);
int suma = 0;
cout << "\nVECTOR RESULTADO: " << endl;
for(int i = 0 ; i < numBlocks.x; ++i){
cout << host_o[i] << " ";
suma += host_o[i];
}
cout << "\n.....................\nRESULTADO FINAL: " << suma << endl;
delete [] vector_entrada;
delete [] host_o;
cudaFree(device_i);
cudaFree(device_o);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z9reduceSumPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ USHF.L.U32 UR6, UR5, 0x1, URZ ; /* 0x0000000105067899 */
/* 0x000fe4000800063f */
/*0060*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0080*/ IMAD R2, R7, UR6, R8 ; /* 0x0000000607027c24 */
/* 0x001fe2000f8e0208 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @!P0 IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002048a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*00d0*/ @!P0 IMAD.WIDE.U32 R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fc800078e0003 */
/*00e0*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fe400078e0203 */
/*00f0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000604048981 */
/* 0x000ea8000c1e1900 */
/*0100*/ @!P0 LDG.E R3, [R2.64] ; /* 0x0000000602038981 */
/* 0x000ea2000c1e1900 */
/*0110*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0120*/ USHF.R.U32.HI UR4, URZ, 0x1, UR5 ; /* 0x000000013f047899 */
/* 0x000fcc0008011605 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0140*/ @!P0 IMAD.IADD R6, R4, 0x1, R3 ; /* 0x0000000104068824 */
/* 0x004fc800078e0203 */
/*0150*/ @!P0 I2F R0, R6 ; /* 0x0000000600008306 */
/* 0x000e220000201400 */
/*0160*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fce0003f05270 */
/*0170*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x001e24000020f100 */
/*0180*/ STS [R8.X4], R0 ; /* 0x0000000008007388 */
/* 0x0011e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ @!P1 BRA 0x270 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*01b0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01c0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01d0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01e0*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*01f0*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe20000004800 */
/*0200*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104049824 */
/* 0x001fca00078e0205 */
/*0230*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0260*/ @P1 BRA 0x1d0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0280*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0290*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*02a0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*02b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Francisco Rodriguez Jimenez
cazz@correo.ugr.es
nvcc - The NVIDIA CUDA Compiler
cuobjdump - The NVIDIA CUDA Object Utility
nvdisasm - The NVIDIA CUDA disassembler
nvprune - The NVIDIA CUDA Prune Tool
nsight - NVIDIA NSight, Eclipse Edition
nvvp - The NVIDIA CUDA Visual Profiler
nvprof - The NVIDIA CUDA Command-Line Profiler
cuda-memcheck - The NVIDIA CUDA Check Tool
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include "cuda_runtime.h"
using namespace std;
__host__ void check_CUDA_Error(const char *mensaje){
cudaError_t error;
cudaDeviceSynchronize();
error = cudaGetLastError();
if(error != cudaSuccess){
printf("ERROR %d: %s (%s)\n", error, cudaGetErrorString(error), mensaje);
exit(EXIT_FAILURE);
}
}
__global__ void reduceSum(int *d_V, int *Out, int N, int smen){
extern __shared__ int sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockDim.x*2) + threadIdx.x;
// printf("\nTAM MEMORIA: %d | tid: %d -> id: %d",smen, tid, i);
sdata[tid] = ((i < N/2) ? d_V[i] + d_V[i+blockDim.x] : 0.0f);
__syncthreads();
for (int s = (blockDim.x/2); s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0){
Out[blockIdx.x] = sdata[0];
}
}
int main(int argc, char** argv){
if(argc != 2){
cout << "Error de sintaxis: ejer8 <TAM>" << endl;
return(EXIT_FAILURE);
}
const int TAM = atoi(argv[1]);
//Punteros memoria host
int *vector_entrada, *host_o;
//Punteros memoria device
int *device_i, *device_o;
//Reserva de memoria host
vector_entrada = new int[TAM];
//Reserva de memoria device
cudaMalloc((void **) &device_i, TAM * sizeof(int));
check_CUDA_Error("Error en la reserva del device");
//Inicialización vector
for(int i = 0 ; i < TAM; ++i){
vector_entrada[i] = 1;
}
cout << "VECTOR ENTRADA: " << endl;
for(int i = 0 ; i < TAM; ++i){
cout << vector_entrada[i] << " ";
}
//Copia de host a device
cudaMemcpy(device_i, vector_entrada, sizeof(int)*TAM, cudaMemcpyHostToDevice);
check_CUDA_Error("Errir en la copia del host al device");
//Preparo y lanzo el kernel
dim3 threadsPerBlock(TAM);
dim3 numBlocks(ceil((float)TAM / threadsPerBlock.x));
int smemSize = threadsPerBlock.x * sizeof(int);
cudaMalloc((void **) &device_o, numBlocks.x * sizeof(int));
host_o = new int[numBlocks.x];
reduceSum<<<numBlocks, threadsPerBlock, smemSize>>>(device_i, device_o, TAM, threadsPerBlock.x);
cudaDeviceSynchronize();
//Copio el resultado de device a host
cudaMemcpy(host_o, device_o, sizeof(int)*numBlocks.x, cudaMemcpyDeviceToHost);
int suma = 0;
cout << "\nVECTOR RESULTADO: " << endl;
for(int i = 0 ; i < numBlocks.x; ++i){
cout << host_o[i] << " ";
suma += host_o[i];
}
cout << "\n.....................\nRESULTADO FINAL: " << suma << endl;
delete [] vector_entrada;
delete [] host_o;
cudaFree(device_i);
cudaFree(device_o);
return EXIT_SUCCESS;
} | .file "tmpxft_0005e5ce_00000000-6_ejercicio88.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR %d: %s (%s)\n"
.text
.globl _Z16check_CUDA_ErrorPKc
.type _Z16check_CUDA_ErrorPKc, @function
_Z16check_CUDA_ErrorPKc:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %r8
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z16check_CUDA_ErrorPKc, .-_Z16check_CUDA_ErrorPKc
.globl _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
.type _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii, @function
_Z32__device_stub__Z9reduceSumPiS_iiPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reduceSumPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii, .-_Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
.globl _Z9reduceSumPiS_ii
.type _Z9reduceSumPiS_ii, @function
_Z9reduceSumPiS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9reduceSumPiS_ii, .-_Z9reduceSumPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error de sintaxis: ejer8 <TAM>"
.align 8
.LC2:
.string "Error en la reserva del device"
.section .rodata.str1.1
.LC3:
.string "VECTOR ENTRADA: "
.LC4:
.string " "
.section .rodata.str1.8
.align 8
.LC5:
.string "Errir en la copia del host al device"
.section .rodata.str1.1
.LC6:
.string "\nVECTOR RESULTADO: "
.section .rodata.str1.8
.align 8
.LC7:
.string "\n.....................\nRESULTADO FINAL: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L16
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %eax
.L15:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 12(%rsp)
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L18
leaq 0(,%rax,4), %rbx
movq %rbx, (%rsp)
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z16check_CUDA_ErrorPKc
testl %r12d, %r12d
jle .L38
movq %r15, %rbx
leal -1(%r12), %eax
leaq 4(%r15,%rax,4), %rbp
movq %r15, %rax
.L22:
movl $1, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L22
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %r14
leaq .LC4(%rip), %r13
.L23:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
.L29:
movl $1, %ecx
movq (%rsp), %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdi
call _Z16check_CUDA_ErrorPKc
movl $1, 36(%rsp)
movl $1, 40(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
movl %r12d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
divss %xmm1, %xmm0
call ceilf@PLT
cvttss2siq %xmm0, %rbx
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, %ebp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movl %ebx, 44(%rsp)
movl %r12d, 32(%rsp)
leal 0(,%r12,4), %r8d
movl 40(%rsp), %ecx
movl $0, %r9d
movslq %r8d, %r8
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L26:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq (%rsp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %ebx, %ebx
je .L31
movq %r14, %rbx
leaq 0(%rbp,%r14), %r12
movl $0, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC4(%rip), %r13
.L28:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl (%rbx), %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L28
.L27:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L15
.L18:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
call __cxa_throw_bad_array_new_length@PLT
.L39:
movl 12(%rsp), %ecx
movl %ecx, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
jmp .L26
.L31:
movl $0, %ebp
jmp .L27
.L38:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L29
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9reduceSumPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reduceSumPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Francisco Rodriguez Jimenez
cazz@correo.ugr.es
nvcc - The NVIDIA CUDA Compiler
cuobjdump - The NVIDIA CUDA Object Utility
nvdisasm - The NVIDIA CUDA disassembler
nvprune - The NVIDIA CUDA Prune Tool
nsight - NVIDIA NSight, Eclipse Edition
nvvp - The NVIDIA CUDA Visual Profiler
nvprof - The NVIDIA CUDA Command-Line Profiler
cuda-memcheck - The NVIDIA CUDA Check Tool
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include "cuda_runtime.h"
using namespace std;
__host__ void check_CUDA_Error(const char *mensaje){
cudaError_t error;
cudaDeviceSynchronize();
error = cudaGetLastError();
if(error != cudaSuccess){
printf("ERROR %d: %s (%s)\n", error, cudaGetErrorString(error), mensaje);
exit(EXIT_FAILURE);
}
}
__global__ void reduceSum(int *d_V, int *Out, int N, int smen){
extern __shared__ int sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockDim.x*2) + threadIdx.x;
// printf("\nTAM MEMORIA: %d | tid: %d -> id: %d",smen, tid, i);
sdata[tid] = ((i < N/2) ? d_V[i] + d_V[i+blockDim.x] : 0.0f);
__syncthreads();
for (int s = (blockDim.x/2); s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0){
Out[blockIdx.x] = sdata[0];
}
}
int main(int argc, char** argv){
if(argc != 2){
cout << "Error de sintaxis: ejer8 <TAM>" << endl;
return(EXIT_FAILURE);
}
const int TAM = atoi(argv[1]);
//Punteros memoria host
int *vector_entrada, *host_o;
//Punteros memoria device
int *device_i, *device_o;
//Reserva de memoria host
vector_entrada = new int[TAM];
//Reserva de memoria device
cudaMalloc((void **) &device_i, TAM * sizeof(int));
check_CUDA_Error("Error en la reserva del device");
//Inicialización vector
for(int i = 0 ; i < TAM; ++i){
vector_entrada[i] = 1;
}
cout << "VECTOR ENTRADA: " << endl;
for(int i = 0 ; i < TAM; ++i){
cout << vector_entrada[i] << " ";
}
//Copia de host a device
cudaMemcpy(device_i, vector_entrada, sizeof(int)*TAM, cudaMemcpyHostToDevice);
check_CUDA_Error("Errir en la copia del host al device");
//Preparo y lanzo el kernel
dim3 threadsPerBlock(TAM);
dim3 numBlocks(ceil((float)TAM / threadsPerBlock.x));
int smemSize = threadsPerBlock.x * sizeof(int);
cudaMalloc((void **) &device_o, numBlocks.x * sizeof(int));
host_o = new int[numBlocks.x];
reduceSum<<<numBlocks, threadsPerBlock, smemSize>>>(device_i, device_o, TAM, threadsPerBlock.x);
cudaDeviceSynchronize();
//Copio el resultado de device a host
cudaMemcpy(host_o, device_o, sizeof(int)*numBlocks.x, cudaMemcpyDeviceToHost);
int suma = 0;
cout << "\nVECTOR RESULTADO: " << endl;
for(int i = 0 ; i < numBlocks.x; ++i){
cout << host_o[i] << " ";
suma += host_o[i];
}
cout << "\n.....................\nRESULTADO FINAL: " << suma << endl;
delete [] vector_entrada;
delete [] host_o;
cudaFree(device_i);
cudaFree(device_o);
return EXIT_SUCCESS;
} | /*
Francisco Rodriguez Jimenez
cazz@correo.ugr.es
nvcc - The NVIDIA CUDA Compiler
cuobjdump - The NVIDIA CUDA Object Utility
nvdisasm - The NVIDIA CUDA disassembler
nvprune - The NVIDIA CUDA Prune Tool
nsight - NVIDIA NSight, Eclipse Edition
nvvp - The NVIDIA CUDA Visual Profiler
nvprof - The NVIDIA CUDA Command-Line Profiler
cuda-memcheck - The NVIDIA CUDA Check Tool
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include "hip/hip_runtime.h"
using namespace std;
__host__ void check_CUDA_Error(const char *mensaje){
hipError_t error;
hipDeviceSynchronize();
error = hipGetLastError();
if(error != hipSuccess){
printf("ERROR %d: %s (%s)\n", error, hipGetErrorString(error), mensaje);
exit(EXIT_FAILURE);
}
}
__global__ void reduceSum(int *d_V, int *Out, int N, int smen){
extern __shared__ int sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockDim.x*2) + threadIdx.x;
// printf("\nTAM MEMORIA: %d | tid: %d -> id: %d",smen, tid, i);
sdata[tid] = ((i < N/2) ? d_V[i] + d_V[i+blockDim.x] : 0.0f);
__syncthreads();
for (int s = (blockDim.x/2); s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0){
Out[blockIdx.x] = sdata[0];
}
}
int main(int argc, char** argv){
if(argc != 2){
cout << "Error de sintaxis: ejer8 <TAM>" << endl;
return(EXIT_FAILURE);
}
const int TAM = atoi(argv[1]);
//Punteros memoria host
int *vector_entrada, *host_o;
//Punteros memoria device
int *device_i, *device_o;
//Reserva de memoria host
vector_entrada = new int[TAM];
//Reserva de memoria device
hipMalloc((void **) &device_i, TAM * sizeof(int));
check_CUDA_Error("Error en la reserva del device");
//Inicialización vector
for(int i = 0 ; i < TAM; ++i){
vector_entrada[i] = 1;
}
cout << "VECTOR ENTRADA: " << endl;
for(int i = 0 ; i < TAM; ++i){
cout << vector_entrada[i] << " ";
}
//Copia de host a device
hipMemcpy(device_i, vector_entrada, sizeof(int)*TAM, hipMemcpyHostToDevice);
check_CUDA_Error("Errir en la copia del host al device");
//Preparo y lanzo el kernel
dim3 threadsPerBlock(TAM);
dim3 numBlocks(ceil((float)TAM / threadsPerBlock.x));
int smemSize = threadsPerBlock.x * sizeof(int);
hipMalloc((void **) &device_o, numBlocks.x * sizeof(int));
host_o = new int[numBlocks.x];
reduceSum<<<numBlocks, threadsPerBlock, smemSize>>>(device_i, device_o, TAM, threadsPerBlock.x);
hipDeviceSynchronize();
//Copio el resultado de device a host
hipMemcpy(host_o, device_o, sizeof(int)*numBlocks.x, hipMemcpyDeviceToHost);
int suma = 0;
cout << "\nVECTOR RESULTADO: " << endl;
for(int i = 0 ; i < numBlocks.x; ++i){
cout << host_o[i] << " ";
suma += host_o[i];
}
cout << "\n.....................\nRESULTADO FINAL: " << suma << endl;
delete [] vector_entrada;
delete [] host_o;
hipFree(device_i);
hipFree(device_o);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Francisco Rodriguez Jimenez
cazz@correo.ugr.es
nvcc - The NVIDIA CUDA Compiler
cuobjdump - The NVIDIA CUDA Object Utility
nvdisasm - The NVIDIA CUDA disassembler
nvprune - The NVIDIA CUDA Prune Tool
nsight - NVIDIA NSight, Eclipse Edition
nvvp - The NVIDIA CUDA Visual Profiler
nvprof - The NVIDIA CUDA Command-Line Profiler
cuda-memcheck - The NVIDIA CUDA Check Tool
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include "hip/hip_runtime.h"
using namespace std;
__host__ void check_CUDA_Error(const char *mensaje){
hipError_t error;
hipDeviceSynchronize();
error = hipGetLastError();
if(error != hipSuccess){
printf("ERROR %d: %s (%s)\n", error, hipGetErrorString(error), mensaje);
exit(EXIT_FAILURE);
}
}
__global__ void reduceSum(int *d_V, int *Out, int N, int smen){
extern __shared__ int sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockDim.x*2) + threadIdx.x;
// printf("\nTAM MEMORIA: %d | tid: %d -> id: %d",smen, tid, i);
sdata[tid] = ((i < N/2) ? d_V[i] + d_V[i+blockDim.x] : 0.0f);
__syncthreads();
for (int s = (blockDim.x/2); s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0){
Out[blockIdx.x] = sdata[0];
}
}
int main(int argc, char** argv){
if(argc != 2){
cout << "Error de sintaxis: ejer8 <TAM>" << endl;
return(EXIT_FAILURE);
}
const int TAM = atoi(argv[1]);
//Punteros memoria host
int *vector_entrada, *host_o;
//Punteros memoria device
int *device_i, *device_o;
//Reserva de memoria host
vector_entrada = new int[TAM];
//Reserva de memoria device
hipMalloc((void **) &device_i, TAM * sizeof(int));
check_CUDA_Error("Error en la reserva del device");
//Inicialización vector
for(int i = 0 ; i < TAM; ++i){
vector_entrada[i] = 1;
}
cout << "VECTOR ENTRADA: " << endl;
for(int i = 0 ; i < TAM; ++i){
cout << vector_entrada[i] << " ";
}
//Copia de host a device
hipMemcpy(device_i, vector_entrada, sizeof(int)*TAM, hipMemcpyHostToDevice);
check_CUDA_Error("Errir en la copia del host al device");
//Preparo y lanzo el kernel
dim3 threadsPerBlock(TAM);
dim3 numBlocks(ceil((float)TAM / threadsPerBlock.x));
int smemSize = threadsPerBlock.x * sizeof(int);
hipMalloc((void **) &device_o, numBlocks.x * sizeof(int));
host_o = new int[numBlocks.x];
reduceSum<<<numBlocks, threadsPerBlock, smemSize>>>(device_i, device_o, TAM, threadsPerBlock.x);
hipDeviceSynchronize();
//Copio el resultado de device a host
hipMemcpy(host_o, device_o, sizeof(int)*numBlocks.x, hipMemcpyDeviceToHost);
int suma = 0;
cout << "\nVECTOR RESULTADO: " << endl;
for(int i = 0 ; i < numBlocks.x; ++i){
cout << host_o[i] << " ";
suma += host_o[i];
}
cout << "\n.....................\nRESULTADO FINAL: " << suma << endl;
delete [] vector_entrada;
delete [] host_o;
hipFree(device_i);
hipFree(device_o);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reduceSumPiS_ii
.globl _Z9reduceSumPiS_ii
.p2align 8
.type _Z9reduceSumPiS_ii,@function
_Z9reduceSumPiS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_lshr_b32 s6, s4, 31
s_mul_i32 s5, s15, s3
s_add_i32 s4, s4, s6
v_lshl_add_u32 v1, s5, 1, v0
s_ashr_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_cvt_i32_f32_e32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_4:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_3
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reduceSumPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reduceSumPiS_ii, .Lfunc_end0-_Z9reduceSumPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reduceSumPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reduceSumPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Francisco Rodriguez Jimenez
cazz@correo.ugr.es
nvcc - The NVIDIA CUDA Compiler
cuobjdump - The NVIDIA CUDA Object Utility
nvdisasm - The NVIDIA CUDA disassembler
nvprune - The NVIDIA CUDA Prune Tool
nsight - NVIDIA NSight, Eclipse Edition
nvvp - The NVIDIA CUDA Visual Profiler
nvprof - The NVIDIA CUDA Command-Line Profiler
cuda-memcheck - The NVIDIA CUDA Check Tool
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <sys/time.h>
#include "hip/hip_runtime.h"
using namespace std;
__host__ void check_CUDA_Error(const char *mensaje){
hipError_t error;
hipDeviceSynchronize();
error = hipGetLastError();
if(error != hipSuccess){
printf("ERROR %d: %s (%s)\n", error, hipGetErrorString(error), mensaje);
exit(EXIT_FAILURE);
}
}
__global__ void reduceSum(int *d_V, int *Out, int N, int smen){
extern __shared__ int sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockDim.x*2) + threadIdx.x;
// printf("\nTAM MEMORIA: %d | tid: %d -> id: %d",smen, tid, i);
sdata[tid] = ((i < N/2) ? d_V[i] + d_V[i+blockDim.x] : 0.0f);
__syncthreads();
for (int s = (blockDim.x/2); s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0){
Out[blockIdx.x] = sdata[0];
}
}
int main(int argc, char** argv){
if(argc != 2){
cout << "Error de sintaxis: ejer8 <TAM>" << endl;
return(EXIT_FAILURE);
}
const int TAM = atoi(argv[1]);
//Punteros memoria host
int *vector_entrada, *host_o;
//Punteros memoria device
int *device_i, *device_o;
//Reserva de memoria host
vector_entrada = new int[TAM];
//Reserva de memoria device
hipMalloc((void **) &device_i, TAM * sizeof(int));
check_CUDA_Error("Error en la reserva del device");
//Inicialización vector
for(int i = 0 ; i < TAM; ++i){
vector_entrada[i] = 1;
}
cout << "VECTOR ENTRADA: " << endl;
for(int i = 0 ; i < TAM; ++i){
cout << vector_entrada[i] << " ";
}
//Copia de host a device
hipMemcpy(device_i, vector_entrada, sizeof(int)*TAM, hipMemcpyHostToDevice);
check_CUDA_Error("Errir en la copia del host al device");
//Preparo y lanzo el kernel
dim3 threadsPerBlock(TAM);
dim3 numBlocks(ceil((float)TAM / threadsPerBlock.x));
int smemSize = threadsPerBlock.x * sizeof(int);
hipMalloc((void **) &device_o, numBlocks.x * sizeof(int));
host_o = new int[numBlocks.x];
reduceSum<<<numBlocks, threadsPerBlock, smemSize>>>(device_i, device_o, TAM, threadsPerBlock.x);
hipDeviceSynchronize();
//Copio el resultado de device a host
hipMemcpy(host_o, device_o, sizeof(int)*numBlocks.x, hipMemcpyDeviceToHost);
int suma = 0;
cout << "\nVECTOR RESULTADO: " << endl;
for(int i = 0 ; i < numBlocks.x; ++i){
cout << host_o[i] << " ";
suma += host_o[i];
}
cout << "\n.....................\nRESULTADO FINAL: " << suma << endl;
delete [] vector_entrada;
delete [] host_o;
hipFree(device_i);
hipFree(device_o);
return EXIT_SUCCESS;
} | .text
.file "ejercicio88.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z16check_CUDA_ErrorPKc # -- Begin function _Z16check_CUDA_ErrorPKc
.p2align 4, 0x90
.type _Z16check_CUDA_ErrorPKc,@function
_Z16check_CUDA_ErrorPKc: # @_Z16check_CUDA_ErrorPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movl %ebp, %esi
movq %rax, %rdx
movq %rbx, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z16check_CUDA_ErrorPKc, .Lfunc_end0-_Z16check_CUDA_ErrorPKc
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reduceSumPiS_ii # -- Begin function _Z24__device_stub__reduceSumPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__reduceSumPiS_ii,@function
_Z24__device_stub__reduceSumPiS_ii: # @_Z24__device_stub__reduceSumPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reduceSumPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__reduceSumPiS_ii, .Lfunc_end1-_Z24__device_stub__reduceSumPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.7:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r13d, %rax
leaq (,%rax,4), %r14
testl %eax, %eax
movq $-1, %rdi
cmovnsq %r14, %rdi
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.8: # %_Z16check_CUDA_ErrorPKc.exit.preheader
testl %r13d, %r13d
jle .LBB2_11
# %bb.9: # %_Z16check_CUDA_ErrorPKc.exit.preheader81
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_10: # %_Z16check_CUDA_ErrorPKc.exit
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_10
.LBB2_11: # %_Z16check_CUDA_ErrorPKc.exit._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_37
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r12)
je .LBB2_16
# %bb.13:
movzbl 67(%r12), %eax
jmp .LBB2_17
.LBB2_1:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_37
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB2_5
.LBB2_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
jmp .LBB2_6
.LBB2_16:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r13d, %r13d
jle .LBB2_20
# %bb.18: # %.lr.ph75.preheader
movl %r13d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_19: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB2_19
.LBB2_20: # %._crit_edge
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_21
# %bb.22: # %_Z16check_CUDA_ErrorPKc.exit44
cvtsi2ss %r13d, %xmm0
movq %r13, %r14
movl %r14d, %r13d
cvtsi2ss %r13, %xmm1
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl %eax, %r12d
orq %r12, %rbp
movq %r14, 24(%rsp) # 8-byte Spill
leal (,%r14,4), %r15d
leaq (,%r12,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movslq %r15d, %r8
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
movl %eax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9reduceSumPiS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_24:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq %r14, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_37
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r15)
je .LBB2_27
# %bb.26:
movzbl 67(%r15), %eax
jmp .LBB2_28
.LBB2_27:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 32(%rsp) # 4-byte Folded Reload
je .LBB2_29
# %bb.35: # %.lr.ph78.preheader
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_36: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addl (%r14,%r15,4), %ebp
incq %r15
cmpq %r15, %r12
jne .LBB2_36
jmp .LBB2_30
.LBB2_29:
xorl %ebp, %ebp
.LBB2_30: # %._crit_edge79
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_37
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB2_33
# %bb.32:
movzbl 67(%r15), %ecx
jmp .LBB2_34
.LBB2_33:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB2_6:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_37:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.LBB2_14:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %ecx
jmp .LBB2_15
.LBB2_21:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %ecx
.LBB2_15:
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reduceSumPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR %d: %s (%s)\n"
.size .L.str, 19
.type _Z9reduceSumPiS_ii,@object # @_Z9reduceSumPiS_ii
.section .rodata,"a",@progbits
.globl _Z9reduceSumPiS_ii
.p2align 3, 0x0
_Z9reduceSumPiS_ii:
.quad _Z24__device_stub__reduceSumPiS_ii
.size _Z9reduceSumPiS_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Error de sintaxis: ejer8 <TAM>"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error en la reserva del device"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "VECTOR ENTRADA: "
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Errir en la copia del host al device"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nVECTOR RESULTADO: "
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n.....................\nRESULTADO FINAL: "
.size .L.str.7, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reduceSumPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reduceSumPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reduceSumPiS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reduceSumPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0050*/ USHF.L.U32 UR6, UR5, 0x1, URZ ; /* 0x0000000105067899 */
/* 0x000fe4000800063f */
/*0060*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0080*/ IMAD R2, R7, UR6, R8 ; /* 0x0000000607027c24 */
/* 0x001fe2000f8e0208 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @!P0 IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002048a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*00d0*/ @!P0 IMAD.WIDE.U32 R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fc800078e0003 */
/*00e0*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002028625 */
/* 0x000fe400078e0203 */
/*00f0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000604048981 */
/* 0x000ea8000c1e1900 */
/*0100*/ @!P0 LDG.E R3, [R2.64] ; /* 0x0000000602038981 */
/* 0x000ea2000c1e1900 */
/*0110*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0120*/ USHF.R.U32.HI UR4, URZ, 0x1, UR5 ; /* 0x000000013f047899 */
/* 0x000fcc0008011605 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0140*/ @!P0 IMAD.IADD R6, R4, 0x1, R3 ; /* 0x0000000104068824 */
/* 0x004fc800078e0203 */
/*0150*/ @!P0 I2F R0, R6 ; /* 0x0000000600008306 */
/* 0x000e220000201400 */
/*0160*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fce0003f05270 */
/*0170*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x001e24000020f100 */
/*0180*/ STS [R8.X4], R0 ; /* 0x0000000008007388 */
/* 0x0011e80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ @!P1 BRA 0x270 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*01b0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01c0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01d0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01e0*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*01f0*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe20000004800 */
/*0200*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104049824 */
/* 0x001fca00078e0205 */
/*0230*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0260*/ @P1 BRA 0x1d0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0280*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0290*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*02a0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*02b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reduceSumPiS_ii
.globl _Z9reduceSumPiS_ii
.p2align 8
.type _Z9reduceSumPiS_ii,@function
_Z9reduceSumPiS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_lshr_b32 s6, s4, 31
s_mul_i32 s5, s15, s3
s_add_i32 s4, s4, s6
v_lshl_add_u32 v1, s5, 1, v0
s_ashr_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_cvt_i32_f32_e32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_4:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_3
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reduceSumPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reduceSumPiS_ii, .Lfunc_end0-_Z9reduceSumPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reduceSumPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reduceSumPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005e5ce_00000000-6_ejercicio88.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR %d: %s (%s)\n"
.text
.globl _Z16check_CUDA_ErrorPKc
.type _Z16check_CUDA_ErrorPKc, @function
_Z16check_CUDA_ErrorPKc:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbp, %r8
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z16check_CUDA_ErrorPKc, .-_Z16check_CUDA_ErrorPKc
.globl _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
.type _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii, @function
_Z32__device_stub__Z9reduceSumPiS_iiPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reduceSumPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii, .-_Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
.globl _Z9reduceSumPiS_ii
.type _Z9reduceSumPiS_ii, @function
_Z9reduceSumPiS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9reduceSumPiS_ii, .-_Z9reduceSumPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error de sintaxis: ejer8 <TAM>"
.align 8
.LC2:
.string "Error en la reserva del device"
.section .rodata.str1.1
.LC3:
.string "VECTOR ENTRADA: "
.LC4:
.string " "
.section .rodata.str1.8
.align 8
.LC5:
.string "Errir en la copia del host al device"
.section .rodata.str1.1
.LC6:
.string "\nVECTOR RESULTADO: "
.section .rodata.str1.8
.align 8
.LC7:
.string "\n.....................\nRESULTADO FINAL: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L16
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %eax
.L15:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 12(%rsp)
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L18
leaq 0(,%rax,4), %rbx
movq %rbx, (%rsp)
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC2(%rip), %rdi
call _Z16check_CUDA_ErrorPKc
testl %r12d, %r12d
jle .L38
movq %r15, %rbx
leal -1(%r12), %eax
leaq 4(%r15,%rax,4), %rbp
movq %r15, %rax
.L22:
movl $1, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L22
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %r14
leaq .LC4(%rip), %r13
.L23:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
.L29:
movl $1, %ecx
movq (%rsp), %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdi
call _Z16check_CUDA_ErrorPKc
movl $1, 36(%rsp)
movl $1, 40(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
movl %r12d, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
divss %xmm1, %xmm0
call ceilf@PLT
cvttss2siq %xmm0, %rbx
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, %ebp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movl %ebx, 44(%rsp)
movl %r12d, 32(%rsp)
leal 0(,%r12,4), %r8d
movl 40(%rsp), %ecx
movl $0, %r9d
movslq %r8d, %r8
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L26:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq (%rsp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %ebx, %ebx
je .L31
movq %r14, %rbx
leaq 0(%rbp,%r14), %r12
movl $0, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC4(%rip), %r13
.L28:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl (%rbx), %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L28
.L27:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq (%rsp), %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
jmp .L15
.L18:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
call __cxa_throw_bad_array_new_length@PLT
.L39:
movl 12(%rsp), %ecx
movl %ecx, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9reduceSumPiS_iiPiS_ii
jmp .L26
.L31:
movl $0, %ebp
jmp .L27
.L38:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L29
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9reduceSumPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reduceSumPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ejercicio88.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z16check_CUDA_ErrorPKc # -- Begin function _Z16check_CUDA_ErrorPKc
.p2align 4, 0x90
.type _Z16check_CUDA_ErrorPKc,@function
_Z16check_CUDA_ErrorPKc: # @_Z16check_CUDA_ErrorPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movl %ebp, %esi
movq %rax, %rdx
movq %rbx, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z16check_CUDA_ErrorPKc, .Lfunc_end0-_Z16check_CUDA_ErrorPKc
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reduceSumPiS_ii # -- Begin function _Z24__device_stub__reduceSumPiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__reduceSumPiS_ii,@function
_Z24__device_stub__reduceSumPiS_ii: # @_Z24__device_stub__reduceSumPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reduceSumPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__reduceSumPiS_ii, .Lfunc_end1-_Z24__device_stub__reduceSumPiS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.7:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r13d, %rax
leaq (,%rax,4), %r14
testl %eax, %eax
movq $-1, %rdi
cmovnsq %r14, %rdi
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_14
# %bb.8: # %_Z16check_CUDA_ErrorPKc.exit.preheader
testl %r13d, %r13d
jle .LBB2_11
# %bb.9: # %_Z16check_CUDA_ErrorPKc.exit.preheader81
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_10: # %_Z16check_CUDA_ErrorPKc.exit
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_10
.LBB2_11: # %_Z16check_CUDA_ErrorPKc.exit._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB2_37
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r12)
je .LBB2_16
# %bb.13:
movzbl 67(%r12), %eax
jmp .LBB2_17
.LBB2_1:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_37
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB2_5
.LBB2_4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
jmp .LBB2_6
.LBB2_16:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r13d, %r13d
jle .LBB2_20
# %bb.18: # %.lr.ph75.preheader
movl %r13d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_19: # %.lr.ph75
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB2_19
.LBB2_20: # %._crit_edge
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_21
# %bb.22: # %_Z16check_CUDA_ErrorPKc.exit44
cvtsi2ss %r13d, %xmm0
movq %r13, %r14
movl %r14d, %r13d
cvtsi2ss %r13, %xmm1
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl %eax, %r12d
orq %r12, %rbp
movq %r14, 24(%rsp) # 8-byte Spill
leal (,%r14,4), %r15d
leaq (,%r12,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq %r14, 40(%rsp) # 8-byte Spill
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movslq %r15d, %r8
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_24
# %bb.23:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
movl %eax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9reduceSumPiS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_24:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq %r14, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_37
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r15)
je .LBB2_27
# %bb.26:
movzbl 67(%r15), %eax
jmp .LBB2_28
.LBB2_27:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 32(%rsp) # 4-byte Folded Reload
je .LBB2_29
# %bb.35: # %.lr.ph78.preheader
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_36: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
addl (%r14,%r15,4), %ebp
incq %r15
cmpq %r15, %r12
jne .LBB2_36
jmp .LBB2_30
.LBB2_29:
xorl %ebp, %ebp
.LBB2_30: # %._crit_edge79
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_37
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r15)
je .LBB2_33
# %bb.32:
movzbl 67(%r15), %ecx
jmp .LBB2_34
.LBB2_33:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB2_6:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_37:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.LBB2_14:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %ecx
jmp .LBB2_15
.LBB2_21:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.5, %ecx
.LBB2_15:
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reduceSumPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR %d: %s (%s)\n"
.size .L.str, 19
.type _Z9reduceSumPiS_ii,@object # @_Z9reduceSumPiS_ii
.section .rodata,"a",@progbits
.globl _Z9reduceSumPiS_ii
.p2align 3, 0x0
_Z9reduceSumPiS_ii:
.quad _Z24__device_stub__reduceSumPiS_ii
.size _Z9reduceSumPiS_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Error de sintaxis: ejer8 <TAM>"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error en la reserva del device"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "VECTOR ENTRADA: "
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Errir en la copia del host al device"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nVECTOR RESULTADO: "
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n.....................\nRESULTADO FINAL: "
.size .L.str.7, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reduceSumPiS_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reduceSumPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reduceSumPiS_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <fstream>
#include <iostream>
#include <stdlib.h>
using namespace std;
int main(){
// make an undirected and connected graph
// remember n is vertices and m is edges
cout << "hello world";
FILE* pFile = fopen("input.txt", "r");
if(pFile == NULL){
cout << "Fam u can't do that stop";
return 0;
}
// read in first line with n and m
int n, m;
fscanf(pFile, "%d %d", &n, &m);
cout << "Settings: " << n << " " << m << endl;
int adj_mat[n][n]; // idk what values we want but I'm starting with 4 nodes
// iterate thru all edges
for(int i = 0; i<m; i++){
int n1, n2, weight;
fscanf(pFile, "%d %d %d", &n1, &n2, &weight);
adj_mat[n1][n2] = weight; // put that node in
adj_mat[n2][n1] = weight; //gotta put it in for both
}
// adjacency graph built now it's dumb lit
// okay fam lets get this bread with the normal sequential algorithm
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <fstream>
#include <iostream>
#include <stdlib.h>
using namespace std;
int main(){
// make an undirected and connected graph
// remember n is vertices and m is edges
cout << "hello world";
FILE* pFile = fopen("input.txt", "r");
if(pFile == NULL){
cout << "Fam u can't do that stop";
return 0;
}
// read in first line with n and m
int n, m;
fscanf(pFile, "%d %d", &n, &m);
cout << "Settings: " << n << " " << m << endl;
int adj_mat[n][n]; // idk what values we want but I'm starting with 4 nodes
// iterate thru all edges
for(int i = 0; i<m; i++){
int n1, n2, weight;
fscanf(pFile, "%d %d %d", &n1, &n2, &weight);
adj_mat[n1][n2] = weight; // put that node in
adj_mat[n2][n1] = weight; //gotta put it in for both
}
// adjacency graph built now it's dumb lit
// okay fam lets get this bread with the normal sequential algorithm
return 0;
} | .file "tmpxft_00172db7_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello world"
.LC1:
.string "r"
.LC2:
.string "input.txt"
.LC3:
.string "Fam u can't do that stop"
.LC4:
.string "%d %d"
.LC5:
.string "Settings: "
.LC6:
.string " "
.LC7:
.string "%d %d %d"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $40, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L13
movq %rax, %r14
leaq -72(%rbp), %rcx
leaq -76(%rbp), %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -76(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -72(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq -76(%rbp), %rax
leaq 0(,%rax,4), %r12
imulq %rax, %rax
leaq 15(,%rax,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L6:
cmpq %rdx, %rsp
je .L7
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L6
.L13:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.L7:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L8
orq $0, -8(%rsp,%rax)
.L8:
movq %rsp, %r13
cmpl $0, -72(%rbp)
jle .L5
shrq $2, %r12
movl $0, %ebx
leaq .LC7(%rip), %r15
.L9:
leaq -64(%rbp), %rcx
leaq -68(%rbp), %rdx
leaq -60(%rbp), %r8
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl -60(%rbp), %esi
movslq -64(%rbp), %rdx
movslq -68(%rbp), %rax
movq %rax, %rcx
imulq %r12, %rcx
addq %rdx, %rcx
movl %esi, 0(%r13,%rcx,4)
imulq %r12, %rdx
addq %rdx, %rax
movl %esi, 0(%r13,%rax,4)
addl $1, %ebx
cmpl %ebx, -72(%rbp)
jg .L9
.L5:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <fstream>
#include <iostream>
#include <stdlib.h>
using namespace std;
int main(){
// make an undirected and connected graph
// remember n is vertices and m is edges
cout << "hello world";
FILE* pFile = fopen("input.txt", "r");
if(pFile == NULL){
cout << "Fam u can't do that stop";
return 0;
}
// read in first line with n and m
int n, m;
fscanf(pFile, "%d %d", &n, &m);
cout << "Settings: " << n << " " << m << endl;
int adj_mat[n][n]; // idk what values we want but I'm starting with 4 nodes
// iterate thru all edges
for(int i = 0; i<m; i++){
int n1, n2, weight;
fscanf(pFile, "%d %d %d", &n1, &n2, &weight);
adj_mat[n1][n2] = weight; // put that node in
adj_mat[n2][n1] = weight; //gotta put it in for both
}
// adjacency graph built now it's dumb lit
// okay fam lets get this bread with the normal sequential algorithm
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <stdlib.h>
using namespace std;
int main(){
// make an undirected and connected graph
// remember n is vertices and m is edges
cout << "hello world";
FILE* pFile = fopen("input.txt", "r");
if(pFile == NULL){
cout << "Fam u can't do that stop";
return 0;
}
// read in first line with n and m
int n, m;
fscanf(pFile, "%d %d", &n, &m);
cout << "Settings: " << n << " " << m << endl;
int adj_mat[n][n]; // idk what values we want but I'm starting with 4 nodes
// iterate thru all edges
for(int i = 0; i<m; i++){
int n1, n2, weight;
fscanf(pFile, "%d %d %d", &n1, &n2, &weight);
adj_mat[n1][n2] = weight; // put that node in
adj_mat[n2][n1] = weight; //gotta put it in for both
}
// adjacency graph built now it's dumb lit
// okay fam lets get this bread with the normal sequential algorithm
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <stdlib.h>
using namespace std;
int main(){
// make an undirected and connected graph
// remember n is vertices and m is edges
cout << "hello world";
FILE* pFile = fopen("input.txt", "r");
if(pFile == NULL){
cout << "Fam u can't do that stop";
return 0;
}
// read in first line with n and m
int n, m;
fscanf(pFile, "%d %d", &n, &m);
cout << "Settings: " << n << " " << m << endl;
int adj_mat[n][n]; // idk what values we want but I'm starting with 4 nodes
// iterate thru all edges
for(int i = 0; i<m; i++){
int n1, n2, weight;
fscanf(pFile, "%d %d %d", &n1, &n2, &weight);
adj_mat[n1][n2] = weight; // put that node in
adj_mat[n2][n1] = weight; //gotta put it in for both
}
// adjacency graph built now it's dumb lit
// okay fam lets get this bread with the normal sequential algorithm
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <stdlib.h>
using namespace std;
int main(){
// make an undirected and connected graph
// remember n is vertices and m is edges
cout << "hello world";
FILE* pFile = fopen("input.txt", "r");
if(pFile == NULL){
cout << "Fam u can't do that stop";
return 0;
}
// read in first line with n and m
int n, m;
fscanf(pFile, "%d %d", &n, &m);
cout << "Settings: " << n << " " << m << endl;
int adj_mat[n][n]; // idk what values we want but I'm starting with 4 nodes
// iterate thru all edges
for(int i = 0; i<m; i++){
int n1, n2, weight;
fscanf(pFile, "%d %d %d", &n1, &n2, &weight);
adj_mat[n1][n2] = weight; // put that node in
adj_mat[n2][n1] = weight; //gotta put it in for both
}
// adjacency graph built now it's dumb lit
// okay fam lets get this bread with the normal sequential algorithm
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %rbx
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rcx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_5
# %bb.4:
movzbl 67(%r14), %ecx
jmp .LBB0_6
.LBB0_1:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_10
.LBB0_5:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %r13
cmpl $0, 4(%rsp)
jle .LBB0_9
# %bb.7: # %.lr.ph.preheader
leaq 20(%rsp), %r14
leaq 16(%rsp), %r15
leaq 12(%rsp), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.7, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %r12, %r8
xorl %eax, %eax
callq __isoc23_fscanf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_8
.LBB0_9: # %._crit_edge
movq %r13, %rsp
.LBB0_10:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hello world"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "input.txt"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Fam u can't do that stop"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Settings: "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d %d"
.size .L.str.7, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00172db7_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello world"
.LC1:
.string "r"
.LC2:
.string "input.txt"
.LC3:
.string "Fam u can't do that stop"
.LC4:
.string "%d %d"
.LC5:
.string "Settings: "
.LC6:
.string " "
.LC7:
.string "%d %d %d"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $40, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L13
movq %rax, %r14
leaq -72(%rbp), %rcx
leaq -76(%rbp), %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -76(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -72(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq -76(%rbp), %rax
leaq 0(,%rax,4), %r12
imulq %rax, %rax
leaq 15(,%rax,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L6:
cmpq %rdx, %rsp
je .L7
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L6
.L13:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.L7:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L8
orq $0, -8(%rsp,%rax)
.L8:
movq %rsp, %r13
cmpl $0, -72(%rbp)
jle .L5
shrq $2, %r12
movl $0, %ebx
leaq .LC7(%rip), %r15
.L9:
leaq -64(%rbp), %rcx
leaq -68(%rbp), %rdx
leaq -60(%rbp), %r8
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl -60(%rbp), %esi
movslq -64(%rbp), %rdx
movslq -68(%rbp), %rax
movq %rax, %rcx
imulq %r12, %rcx
addq %rdx, %rcx
movl %esi, 0(%r13,%rcx,4)
imulq %r12, %rdx
addq %rdx, %rax
movl %esi, 0(%r13,%rax,4)
addl $1, %ebx
cmpl %ebx, -72(%rbp)
jg .L9
.L5:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3826:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3826:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %rbx
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rcx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_11
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_5
# %bb.4:
movzbl 67(%r14), %ecx
jmp .LBB0_6
.LBB0_1:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_10
.LBB0_5:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %r13
cmpl $0, 4(%rsp)
jle .LBB0_9
# %bb.7: # %.lr.ph.preheader
leaq 20(%rsp), %r14
leaq 16(%rsp), %r15
leaq 12(%rsp), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.7, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %r12, %r8
xorl %eax, %eax
callq __isoc23_fscanf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_8
.LBB0_9: # %._crit_edge
movq %r13, %rsp
.LBB0_10:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hello world"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "input.txt"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Fam u can't do that stop"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d %d"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Settings: "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d %d"
.size .L.str.7, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <random>
__global__ void randSumKernel(int *arr, int a) {
// threadIdx.x is x and blockIdx.x is y
arr[blockIdx.x * blockDim.x + threadIdx.x] = a * threadIdx.x + blockIdx.x;
}
// reference is https://github.com/DanNegrut/ME759/blob/main/2021Spring/GPU/setArray.cu
int main(){
const int numBlocks = 2;
const int numThreads = 8;
const int numElement = 16;
// set up random number generator
std::random_device entropy_source;
std::mt19937_64 generator(entropy_source());
const int min = 0, max = 10; // The range for the random number generator is 0 to 10
// there are tons of oter distributino that could be found from https://en.cppreference.com/w/cpp/header/random
std::uniform_int_distribution<> dist(min, max);
// use random number generator to generate integer a
int a = dist(generator);
// initialize device array dA
int *dA;
// allocate memory on the device; zero out all entries in this device array
cudaMalloc((void **)&dA, sizeof(int) * numElement);
cudaMemset(dA, 0, numElement * sizeof(int));
// initialize host array hA
int hA[numElement];
// invoke GPU kernel with 2 blocks that has eight threads
randSumKernel<<<numBlocks, numThreads>>>(dA, a);
cudaDeviceSynchronize();
// bring the result back from the GPU into the hostArray
cudaMemcpy(hA, dA, sizeof(int) * numElement, cudaMemcpyDeviceToHost);
// free array
cudaFree(dA);
// print out element
for (int i = 0; i < numElement - 1; i++) {
std::printf("%d ", hA[i]);
}
std::printf("%d\n", hA[numElement - 1]);
return 0;
} | code for sm_80
Function : _Z13randSumKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R0, c[0x0][0x0], R5 ; /* 0x0000000000027a24 */
/* 0x001fe400078e0205 */
/*0060*/ IMAD R5, R5, c[0x0][0x168], R0 ; /* 0x00005a0005057a24 */
/* 0x000fc600078e0200 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <random>
__global__ void randSumKernel(int *arr, int a) {
// threadIdx.x is x and blockIdx.x is y
arr[blockIdx.x * blockDim.x + threadIdx.x] = a * threadIdx.x + blockIdx.x;
}
// reference is https://github.com/DanNegrut/ME759/blob/main/2021Spring/GPU/setArray.cu
int main(){
const int numBlocks = 2;
const int numThreads = 8;
const int numElement = 16;
// set up random number generator
std::random_device entropy_source;
std::mt19937_64 generator(entropy_source());
const int min = 0, max = 10; // The range for the random number generator is 0 to 10
// there are tons of oter distributino that could be found from https://en.cppreference.com/w/cpp/header/random
std::uniform_int_distribution<> dist(min, max);
// use random number generator to generate integer a
int a = dist(generator);
// initialize device array dA
int *dA;
// allocate memory on the device; zero out all entries in this device array
cudaMalloc((void **)&dA, sizeof(int) * numElement);
cudaMemset(dA, 0, numElement * sizeof(int));
// initialize host array hA
int hA[numElement];
// invoke GPU kernel with 2 blocks that has eight threads
randSumKernel<<<numBlocks, numThreads>>>(dA, a);
cudaDeviceSynchronize();
// bring the result back from the GPU into the hostArray
cudaMemcpy(hA, dA, sizeof(int) * numElement, cudaMemcpyDeviceToHost);
// free array
cudaFree(dA);
// print out element
for (int i = 0; i < numElement - 1; i++) {
std::printf("%d ", hA[i]);
}
std::printf("%d\n", hA[numElement - 1]);
return 0;
} | .file "tmpxft_00042adf_00000000-6_task2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4144:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4144:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13randSumKernelPiiPii
.type _Z34__device_stub__Z13randSumKernelPiiPii, @function
_Z34__device_stub__Z13randSumKernelPiiPii:
.LFB4166:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13randSumKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4166:
.size _Z34__device_stub__Z13randSumKernelPiiPii, .-_Z34__device_stub__Z13randSumKernelPiiPii
.globl _Z13randSumKernelPii
.type _Z13randSumKernelPii, @function
_Z13randSumKernelPii:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13randSumKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _Z13randSumKernelPii, .-_Z13randSumKernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13randSumKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13randSumKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv:
.LFB4802:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1248(%rdi), %r9
movq %rdi, %rcx
movabsq $-5403634167711393303, %r8
.L15:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 1248(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L15
leaq 1240(%rdi), %r8
movabsq $-5403634167711393303, %rsi
.L17:
movq 1248(%rdx), %rax
andq $-2147483648, %rax
movq 1256(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1248(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L17
movq 2488(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 1240(%rdi), %rdx
andl $1, %eax
movabsq $-5403634167711393303, %rcx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 2488(%rdi)
movq $0, 2496(%rdi)
ret
.cfi_endproc
.LFE4802:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv:
.LFB4741:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $311, 2496(%rdi)
ja .L24
.L22:
movq 2496(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 2496(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $29, %rdx
movabsq $6148914691236517205, %rcx
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
salq $17, %rax
movabsq $8202884508482404352, %rcx
andq %rcx, %rax
xorq %rdx, %rax
movq %rax, %rdx
salq $37, %rdx
movabsq $-2270628950310912, %rcx
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
jmp .L22
.cfi_endproc
.LFE4741:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.section .rodata.str1.1
.LC1:
.string "%d "
.LC2:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB4141:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4141
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $3520, %rsp
.cfi_def_cfa_offset 7648
movq %fs:40, %rax
movq %rax, 7608(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rsi
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
movl $1634100580, 112(%rsp)
movl $1953264993, 115(%rsp)
movq $7, 104(%rsp)
movb $0, 119(%rsp)
leaq 2608(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq 96(%rsp), %rdi
leaq 112(%rsp), %rax
cmpq %rax, %rdi
je .L26
movq 112(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L26:
leaq 2608(%rsp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
movl %eax, %eax
movq %rax, 96(%rsp)
movl $1, %ecx
movabsq $6364136223846793005, %r8
movabsq $945986875574848801, %rdi
.L30:
movq 88(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $62, %rdx
xorq %rdx, %rax
imulq %r8, %rax
movq %rax, %rsi
movq %rcx, %rdx
shrq $3, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $312, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addq %rsi, %rax
movq %rax, 96(%rsp,%rcx,8)
addq $1, %rcx
cmpq $312, %rcx
jne .L30
movq $312, 2592(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
movq %rax, %rcx
movl $0, %ebx
movq %rbx, %rdx
shldq $1, %rax, %rdx
addq %rax, %rax
addq %rcx, %rax
adcq %rbx, %rdx
shldq $2, %rax, %rdx
salq $2, %rax
subq %rcx, %rax
sbbq %rbx, %rdx
movq %rdx, %rbp
cmpq $4, %rax
ja .L31
leaq 96(%rsp), %rbx
.L32:
movq %rbx, %rdi
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
movq %rax, %rsi
movl $0, %edi
movq %rdi, %rdx
shldq $1, %rax, %rdx
addq %rax, %rax
addq %rsi, %rax
adcq %rdi, %rdx
shldq $2, %rax, %rdx
salq $2, %rax
subq %rsi, %rax
sbbq %rdi, %rdx
movq %rdx, %rbp
cmpq $4, %rax
jbe .L32
.L31:
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
.LEHE1:
jmp .L45
.L39:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 7608(%rsp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L45:
movl $64, %edx
movl $0, %esi
movq (%rsp), %rdi
.LEHB3:
call cudaMemset@PLT
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %ebp, %esi
movq (%rsp), %rdi
call _Z34__device_stub__Z13randSumKernelPiiPii
.L33:
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq 32(%rsp), %rbx
leaq 92(%rsp), %rbp
leaq .LC1(%rip), %r12
jmp .L34
.L47:
addq $4, %rbx
cmpq %rbx, %rbp
je .L46
.L34:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L46:
movl 92(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE3:
leaq 2608(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 7608(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $7616, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 2608(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 7608(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4141:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4141:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4141-.LLSDACSB4141
.LLSDACSB4141:
.uleb128 .LEHB0-.LFB4141
.uleb128 .LEHE0-.LEHB0
.uleb128 .L39-.LFB4141
.uleb128 0
.uleb128 .LEHB1-.LFB4141
.uleb128 .LEHE1-.LEHB1
.uleb128 .L38-.LFB4141
.uleb128 0
.uleb128 .LEHB2-.LFB4141
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4141
.uleb128 .LEHE3-.LEHB3
.uleb128 .L38-.LFB4141
.uleb128 0
.uleb128 .LEHB4-.LFB4141
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4141:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <random>
__global__ void randSumKernel(int *arr, int a) {
// threadIdx.x is x and blockIdx.x is y
arr[blockIdx.x * blockDim.x + threadIdx.x] = a * threadIdx.x + blockIdx.x;
}
// reference is https://github.com/DanNegrut/ME759/blob/main/2021Spring/GPU/setArray.cu
int main(){
const int numBlocks = 2;
const int numThreads = 8;
const int numElement = 16;
// set up random number generator
std::random_device entropy_source;
std::mt19937_64 generator(entropy_source());
const int min = 0, max = 10; // The range for the random number generator is 0 to 10
// there are tons of oter distributino that could be found from https://en.cppreference.com/w/cpp/header/random
std::uniform_int_distribution<> dist(min, max);
// use random number generator to generate integer a
int a = dist(generator);
// initialize device array dA
int *dA;
// allocate memory on the device; zero out all entries in this device array
cudaMalloc((void **)&dA, sizeof(int) * numElement);
cudaMemset(dA, 0, numElement * sizeof(int));
// initialize host array hA
int hA[numElement];
// invoke GPU kernel with 2 blocks that has eight threads
randSumKernel<<<numBlocks, numThreads>>>(dA, a);
cudaDeviceSynchronize();
// bring the result back from the GPU into the hostArray
cudaMemcpy(hA, dA, sizeof(int) * numElement, cudaMemcpyDeviceToHost);
// free array
cudaFree(dA);
// print out element
for (int i = 0; i < numElement - 1; i++) {
std::printf("%d ", hA[i]);
}
std::printf("%d\n", hA[numElement - 1]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <random>
__global__ void randSumKernel(int *arr, int a) {
// threadIdx.x is x and blockIdx.x is y
arr[blockIdx.x * blockDim.x + threadIdx.x] = a * threadIdx.x + blockIdx.x;
}
// reference is https://github.com/DanNegrut/ME759/blob/main/2021Spring/GPU/setArray.cu
int main(){
const int numBlocks = 2;
const int numThreads = 8;
const int numElement = 16;
// set up random number generator
std::random_device entropy_source;
std::mt19937_64 generator(entropy_source());
const int min = 0, max = 10; // The range for the random number generator is 0 to 10
// there are tons of oter distributino that could be found from https://en.cppreference.com/w/cpp/header/random
std::uniform_int_distribution<> dist(min, max);
// use random number generator to generate integer a
int a = dist(generator);
// initialize device array dA
int *dA;
// allocate memory on the device; zero out all entries in this device array
hipMalloc((void **)&dA, sizeof(int) * numElement);
hipMemset(dA, 0, numElement * sizeof(int));
// initialize host array hA
int hA[numElement];
// invoke GPU kernel with 2 blocks that has eight threads
randSumKernel<<<numBlocks, numThreads>>>(dA, a);
hipDeviceSynchronize();
// bring the result back from the GPU into the hostArray
hipMemcpy(hA, dA, sizeof(int) * numElement, hipMemcpyDeviceToHost);
// free array
hipFree(dA);
// print out element
for (int i = 0; i < numElement - 1; i++) {
std::printf("%d ", hA[i]);
}
std::printf("%d\n", hA[numElement - 1]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <random>
__global__ void randSumKernel(int *arr, int a) {
// threadIdx.x is x and blockIdx.x is y
arr[blockIdx.x * blockDim.x + threadIdx.x] = a * threadIdx.x + blockIdx.x;
}
// reference is https://github.com/DanNegrut/ME759/blob/main/2021Spring/GPU/setArray.cu
int main(){
const int numBlocks = 2;
const int numThreads = 8;
const int numElement = 16;
// set up random number generator
std::random_device entropy_source;
std::mt19937_64 generator(entropy_source());
const int min = 0, max = 10; // The range for the random number generator is 0 to 10
// there are tons of oter distributino that could be found from https://en.cppreference.com/w/cpp/header/random
std::uniform_int_distribution<> dist(min, max);
// use random number generator to generate integer a
int a = dist(generator);
// initialize device array dA
int *dA;
// allocate memory on the device; zero out all entries in this device array
hipMalloc((void **)&dA, sizeof(int) * numElement);
hipMemset(dA, 0, numElement * sizeof(int));
// initialize host array hA
int hA[numElement];
// invoke GPU kernel with 2 blocks that has eight threads
randSumKernel<<<numBlocks, numThreads>>>(dA, a);
hipDeviceSynchronize();
// bring the result back from the GPU into the hostArray
hipMemcpy(hA, dA, sizeof(int) * numElement, hipMemcpyDeviceToHost);
// free array
hipFree(dA);
// print out element
for (int i = 0; i < numElement - 1; i++) {
std::printf("%d ", hA[i]);
}
std::printf("%d\n", hA[numElement - 1]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13randSumKernelPii
.globl _Z13randSumKernelPii
.p2align 8
.type _Z13randSumKernelPii,@function
_Z13randSumKernelPii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_mad_u64_u32 v[3:4], null, v0, s4, s[2:3]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13randSumKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13randSumKernelPii, .Lfunc_end0-_Z13randSumKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13randSumKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13randSumKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <random>
__global__ void randSumKernel(int *arr, int a) {
// threadIdx.x is x and blockIdx.x is y
arr[blockIdx.x * blockDim.x + threadIdx.x] = a * threadIdx.x + blockIdx.x;
}
// reference is https://github.com/DanNegrut/ME759/blob/main/2021Spring/GPU/setArray.cu
int main(){
const int numBlocks = 2;
const int numThreads = 8;
const int numElement = 16;
// set up random number generator
std::random_device entropy_source;
std::mt19937_64 generator(entropy_source());
const int min = 0, max = 10; // The range for the random number generator is 0 to 10
// there are tons of oter distributino that could be found from https://en.cppreference.com/w/cpp/header/random
std::uniform_int_distribution<> dist(min, max);
// use random number generator to generate integer a
int a = dist(generator);
// initialize device array dA
int *dA;
// allocate memory on the device; zero out all entries in this device array
hipMalloc((void **)&dA, sizeof(int) * numElement);
hipMemset(dA, 0, numElement * sizeof(int));
// initialize host array hA
int hA[numElement];
// invoke GPU kernel with 2 blocks that has eight threads
randSumKernel<<<numBlocks, numThreads>>>(dA, a);
hipDeviceSynchronize();
// bring the result back from the GPU into the hostArray
hipMemcpy(hA, dA, sizeof(int) * numElement, hipMemcpyDeviceToHost);
// free array
hipFree(dA);
// print out element
for (int i = 0; i < numElement - 1; i++) {
std::printf("%d ", hA[i]);
}
std::printf("%d\n", hA[numElement - 1]);
return 0;
} | .text
.file "task2.hip"
.globl _Z28__device_stub__randSumKernelPii # -- Begin function _Z28__device_stub__randSumKernelPii
.p2align 4, 0x90
.type _Z28__device_stub__randSumKernelPii,@function
_Z28__device_stub__randSumKernelPii: # @_Z28__device_stub__randSumKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13randSumKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__randSumKernelPii, .Lfunc_end0-_Z28__device_stub__randSumKernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $7664, %rsp # imm = 0x1DF0
.cfi_def_cfa_offset 7696
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 176(%rsp), %r14
movq %r14, 160(%rsp)
movl $1634100580, 176(%rsp) # imm = 0x61666564
movl $1953264993, 179(%rsp) # imm = 0x746C7561
movq $7, 168(%rsp)
movb $0, 183(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
leaq 160(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 160(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %esi
movq %rsi, 160(%rsp)
movl $1, %eax
movabsq $6364136223846793005, %rcx # imm = 0x5851F42D4C957F2D
movq %rsi, %rdx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
shrq $62, %rdx
xorq %rsi, %rdx
imulq %rcx, %rdx
addq %rax, %rdx
movq %rdx, 160(%rsp,%rax,8)
incq %rax
movq %rdx, %rsi
cmpq $312, %rax # imm = 0x138
jne .LBB1_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEC2Em.exit
movq $312, 2656(%rsp) # imm = 0x138
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp7:
# %bb.7: # %.noexc
movl $11, %r15d
mulq %r15
cmpq $4, %rax
ja .LBB1_11
# %bb.8: # %.lr.ph.i.i.i.preheader
leaq 160(%rsp), %r14
.p2align 4, 0x90
.LBB1_9: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp10:
# %bb.10: # %.noexc17
# in Loop: Header=BB1_9 Depth=1
mulq %r15
cmpq $5, %rax
jb .LBB1_9
.LBB1_11: # %..loopexit_crit_edge.i.i.i
movq %rdx, %rbx
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
.Ltmp13:
# %bb.12:
movq 8(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $64, %edx
xorl %esi, %esi
callq hipMemset
.Ltmp15:
# %bb.13:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4294967298, %rdi # imm = 0x100000002
movabsq $4294967304, %rdx # imm = 0x100000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.14:
testl %eax, %eax
jne .LBB1_17
# %bb.15:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebx, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.16: # %.noexc19
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z13randSumKernelPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB1_17:
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp24:
# %bb.18:
movq 8(%rsp), %rsi
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp26:
# %bb.19:
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.20: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_21: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $15, %rbx
jne .LBB1_21
# %bb.22:
movl 156(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp34:
# %bb.23: # %_ZNSt13random_deviceD2Ev.exit
xorl %eax, %eax
addq $7664, %rsp # imm = 0x1DF0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 7696
.Ltmp35:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_29: # %.loopexit.split-lp
.Ltmp8:
jmp .LBB1_33
.LBB1_27:
.Ltmp5:
jmp .LBB1_33
.LBB1_24:
.Ltmp2:
movq %rax, %rbx
movq 160(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_26
# %bb.25: # %.critedge.i.i6.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_32:
.Ltmp16:
jmp .LBB1_33
.LBB1_30:
.Ltmp29:
jmp .LBB1_33
.LBB1_28: # %.loopexit
.Ltmp11:
.LBB1_33:
movq %rax, %rbx
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp31:
.LBB1_26: # %common.resume
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_34:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp12 # Call between .Ltmp12 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp17 # Call between .Ltmp17 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 1 # On action: 1
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp30-.Ltmp34 # Call between .Ltmp34 and .Ltmp30
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,@function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv: # @_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_startproc
# %bb.0:
cmpq $312, 2496(%rdi) # imm = 0x138
jb .LBB3_6
# %bb.1: # %.preheader.preheader
movabsq $-5403634167711393303, %rax # imm = 0xB5026F5AA96619E9
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 1248(%rdi,%rdx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $156, %rsi
jne .LBB3_2
# %bb.3: # %.preheader.i.preheader
movl $157, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB3_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1256(%rdi,%rcx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $312, %rcx # imm = 0x138
jne .LBB3_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 2488(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 1240(%rdi), %rsi
andl $1, %edx
negq %rdx
andq %rax, %rdx
xorq %rsi, %rdx
movq %rdx, 2488(%rdi)
movq $0, 2496(%rdi)
.LBB3_6:
movq 2496(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 2496(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $29, %rcx
movabsq $22906492245, %rdx # imm = 0x555555555
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shlq $17, %rax
movabsq $8202884508482404352, %rcx # imm = 0x71D67FFFEDA60000
andq %rax, %rcx
xorq %rdx, %rcx
movl %ecx, %edx
andl $134201207, %edx # imm = 0x7FFBF77
shlq $37, %rdx
xorq %rcx, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
retq
.Lfunc_end3:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .Lfunc_end3-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13randSumKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13randSumKernelPii,@object # @_Z13randSumKernelPii
.section .rodata,"a",@progbits
.globl _Z13randSumKernelPii
.p2align 3, 0x0
_Z13randSumKernelPii:
.quad _Z28__device_stub__randSumKernelPii
.size _Z13randSumKernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "default"
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13randSumKernelPii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__randSumKernelPii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z13randSumKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13randSumKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R0, c[0x0][0x0], R5 ; /* 0x0000000000027a24 */
/* 0x001fe400078e0205 */
/*0060*/ IMAD R5, R5, c[0x0][0x168], R0 ; /* 0x00005a0005057a24 */
/* 0x000fc600078e0200 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13randSumKernelPii
.globl _Z13randSumKernelPii
.p2align 8
.type _Z13randSumKernelPii,@function
_Z13randSumKernelPii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_mad_u64_u32 v[3:4], null, v0, s4, s[2:3]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13randSumKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13randSumKernelPii, .Lfunc_end0-_Z13randSumKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13randSumKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13randSumKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00042adf_00000000-6_task2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4144:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4144:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13randSumKernelPiiPii
.type _Z34__device_stub__Z13randSumKernelPiiPii, @function
_Z34__device_stub__Z13randSumKernelPiiPii:
.LFB4166:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13randSumKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4166:
.size _Z34__device_stub__Z13randSumKernelPiiPii, .-_Z34__device_stub__Z13randSumKernelPiiPii
.globl _Z13randSumKernelPii
.type _Z13randSumKernelPii, @function
_Z13randSumKernelPii:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13randSumKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _Z13randSumKernelPii, .-_Z13randSumKernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13randSumKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13randSumKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv:
.LFB4802:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1248(%rdi), %r9
movq %rdi, %rcx
movabsq $-5403634167711393303, %r8
.L15:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 1248(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L15
leaq 1240(%rdi), %r8
movabsq $-5403634167711393303, %rsi
.L17:
movq 1248(%rdx), %rax
andq $-2147483648, %rax
movq 1256(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1248(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L17
movq 2488(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 1240(%rdi), %rdx
andl $1, %eax
movabsq $-5403634167711393303, %rcx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 2488(%rdi)
movq $0, 2496(%rdi)
ret
.cfi_endproc
.LFE4802:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv:
.LFB4741:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $311, 2496(%rdi)
ja .L24
.L22:
movq 2496(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 2496(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $29, %rdx
movabsq $6148914691236517205, %rcx
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
salq $17, %rax
movabsq $8202884508482404352, %rcx
andq %rcx, %rax
xorq %rdx, %rax
movq %rax, %rdx
salq $37, %rdx
movabsq $-2270628950310912, %rcx
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
jmp .L22
.cfi_endproc
.LFE4741:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.section .rodata.str1.1
.LC1:
.string "%d "
.LC2:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB4141:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4141
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $3520, %rsp
.cfi_def_cfa_offset 7648
movq %fs:40, %rax
movq %rax, 7608(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rsi
leaq 112(%rsp), %rax
movq %rax, 96(%rsp)
movl $1634100580, 112(%rsp)
movl $1953264993, 115(%rsp)
movq $7, 104(%rsp)
movb $0, 119(%rsp)
leaq 2608(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq 96(%rsp), %rdi
leaq 112(%rsp), %rax
cmpq %rax, %rdi
je .L26
movq 112(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L26:
leaq 2608(%rsp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
movl %eax, %eax
movq %rax, 96(%rsp)
movl $1, %ecx
movabsq $6364136223846793005, %r8
movabsq $945986875574848801, %rdi
.L30:
movq 88(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $62, %rdx
xorq %rdx, %rax
imulq %r8, %rax
movq %rax, %rsi
movq %rcx, %rdx
shrq $3, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $312, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addq %rsi, %rax
movq %rax, 96(%rsp,%rcx,8)
addq $1, %rcx
cmpq $312, %rcx
jne .L30
movq $312, 2592(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
movq %rax, %rcx
movl $0, %ebx
movq %rbx, %rdx
shldq $1, %rax, %rdx
addq %rax, %rax
addq %rcx, %rax
adcq %rbx, %rdx
shldq $2, %rax, %rdx
salq $2, %rax
subq %rcx, %rax
sbbq %rbx, %rdx
movq %rdx, %rbp
cmpq $4, %rax
ja .L31
leaq 96(%rsp), %rbx
.L32:
movq %rbx, %rdi
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
movq %rax, %rsi
movl $0, %edi
movq %rdi, %rdx
shldq $1, %rax, %rdx
addq %rax, %rax
addq %rsi, %rax
adcq %rdi, %rdx
shldq $2, %rax, %rdx
salq $2, %rax
subq %rsi, %rax
sbbq %rdi, %rdx
movq %rdx, %rbp
cmpq $4, %rax
jbe .L32
.L31:
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
.LEHE1:
jmp .L45
.L39:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 7608(%rsp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L45:
movl $64, %edx
movl $0, %esi
movq (%rsp), %rdi
.LEHB3:
call cudaMemset@PLT
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %ebp, %esi
movq (%rsp), %rdi
call _Z34__device_stub__Z13randSumKernelPiiPii
.L33:
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq 32(%rsp), %rbx
leaq 92(%rsp), %rbp
leaq .LC1(%rip), %r12
jmp .L34
.L47:
addq $4, %rbx
cmpq %rbx, %rbp
je .L46
.L34:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L46:
movl 92(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE3:
leaq 2608(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 7608(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $7616, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 2608(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 7608(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4141:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4141:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4141-.LLSDACSB4141
.LLSDACSB4141:
.uleb128 .LEHB0-.LFB4141
.uleb128 .LEHE0-.LEHB0
.uleb128 .L39-.LFB4141
.uleb128 0
.uleb128 .LEHB1-.LFB4141
.uleb128 .LEHE1-.LEHB1
.uleb128 .L38-.LFB4141
.uleb128 0
.uleb128 .LEHB2-.LFB4141
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4141
.uleb128 .LEHE3-.LEHB3
.uleb128 .L38-.LFB4141
.uleb128 0
.uleb128 .LEHB4-.LFB4141
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4141:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task2.hip"
.globl _Z28__device_stub__randSumKernelPii # -- Begin function _Z28__device_stub__randSumKernelPii
.p2align 4, 0x90
.type _Z28__device_stub__randSumKernelPii,@function
_Z28__device_stub__randSumKernelPii: # @_Z28__device_stub__randSumKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13randSumKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__randSumKernelPii, .Lfunc_end0-_Z28__device_stub__randSumKernelPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $7664, %rsp # imm = 0x1DF0
.cfi_def_cfa_offset 7696
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 176(%rsp), %r14
movq %r14, 160(%rsp)
movl $1634100580, 176(%rsp) # imm = 0x61666564
movl $1953264993, 179(%rsp) # imm = 0x746C7561
movq $7, 168(%rsp)
movb $0, 183(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
leaq 160(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 160(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %esi
movq %rsi, 160(%rsp)
movl $1, %eax
movabsq $6364136223846793005, %rcx # imm = 0x5851F42D4C957F2D
movq %rsi, %rdx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
shrq $62, %rdx
xorq %rsi, %rdx
imulq %rcx, %rdx
addq %rax, %rdx
movq %rdx, 160(%rsp,%rax,8)
incq %rax
movq %rdx, %rsi
cmpq $312, %rax # imm = 0x138
jne .LBB1_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEC2Em.exit
movq $312, 2656(%rsp) # imm = 0x138
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp7:
# %bb.7: # %.noexc
movl $11, %r15d
mulq %r15
cmpq $4, %rax
ja .LBB1_11
# %bb.8: # %.lr.ph.i.i.i.preheader
leaq 160(%rsp), %r14
.p2align 4, 0x90
.LBB1_9: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp10:
# %bb.10: # %.noexc17
# in Loop: Header=BB1_9 Depth=1
mulq %r15
cmpq $5, %rax
jb .LBB1_9
.LBB1_11: # %..loopexit_crit_edge.i.i.i
movq %rdx, %rbx
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
.Ltmp13:
# %bb.12:
movq 8(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $64, %edx
xorl %esi, %esi
callq hipMemset
.Ltmp15:
# %bb.13:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4294967298, %rdi # imm = 0x100000002
movabsq $4294967304, %rdx # imm = 0x100000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.14:
testl %eax, %eax
jne .LBB1_17
# %bb.15:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebx, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.16: # %.noexc19
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z13randSumKernelPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB1_17:
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp24:
# %bb.18:
movq 8(%rsp), %rsi
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp26:
# %bb.19:
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.20: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_21: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $15, %rbx
jne .LBB1_21
# %bb.22:
movl 156(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp34:
# %bb.23: # %_ZNSt13random_deviceD2Ev.exit
xorl %eax, %eax
addq $7664, %rsp # imm = 0x1DF0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 7696
.Ltmp35:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_29: # %.loopexit.split-lp
.Ltmp8:
jmp .LBB1_33
.LBB1_27:
.Ltmp5:
jmp .LBB1_33
.LBB1_24:
.Ltmp2:
movq %rax, %rbx
movq 160(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_26
# %bb.25: # %.critedge.i.i6.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_32:
.Ltmp16:
jmp .LBB1_33
.LBB1_30:
.Ltmp29:
jmp .LBB1_33
.LBB1_28: # %.loopexit
.Ltmp11:
.LBB1_33:
movq %rax, %rbx
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 2664(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp31:
.LBB1_26: # %common.resume
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_34:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp12 # Call between .Ltmp12 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp17 # Call between .Ltmp17 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 1 # On action: 1
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp30-.Ltmp34 # Call between .Ltmp34 and .Ltmp30
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 1 # On action: 1
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,@function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv: # @_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_startproc
# %bb.0:
cmpq $312, 2496(%rdi) # imm = 0x138
jb .LBB3_6
# %bb.1: # %.preheader.preheader
movabsq $-5403634167711393303, %rax # imm = 0xB5026F5AA96619E9
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 1248(%rdi,%rdx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $156, %rsi
jne .LBB3_2
# %bb.3: # %.preheader.i.preheader
movl $157, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB3_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1256(%rdi,%rcx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $312, %rcx # imm = 0x138
jne .LBB3_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 2488(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 1240(%rdi), %rsi
andl $1, %edx
negq %rdx
andq %rax, %rdx
xorq %rsi, %rdx
movq %rdx, 2488(%rdi)
movq $0, 2496(%rdi)
.LBB3_6:
movq 2496(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 2496(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $29, %rcx
movabsq $22906492245, %rdx # imm = 0x555555555
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shlq $17, %rax
movabsq $8202884508482404352, %rcx # imm = 0x71D67FFFEDA60000
andq %rax, %rcx
xorq %rdx, %rcx
movl %ecx, %edx
andl $134201207, %edx # imm = 0x7FFBF77
shlq $37, %rdx
xorq %rcx, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
retq
.Lfunc_end3:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .Lfunc_end3-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13randSumKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13randSumKernelPii,@object # @_Z13randSumKernelPii
.section .rodata,"a",@progbits
.globl _Z13randSumKernelPii
.p2align 3, 0x0
_Z13randSumKernelPii:
.quad _Z28__device_stub__randSumKernelPii
.size _Z13randSumKernelPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "default"
.size .L.str.2, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13randSumKernelPii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__randSumKernelPii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z13randSumKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void vec_add ( int * l, int * r, int n ){
int thid = threadIdx.x + blockDim.x * blockIdx.x;
if(thid >= n) return;
l[thid] += r[thid];
}
int main(){
int l[] = {1,2,3,4};
int * gpu_l;
cudaMalloc( &gpu_l, sizeof(int) * 4);
cudaMemcpy(gpu_l, l, sizeof(int) * 4, cudaMemcpyHostToDevice);
int r[] = {4, 3, 2, 1};
int * gpu_r;
cudaMalloc( &gpu_r, sizeof(int) * 4);
cudaMemcpy(gpu_r, r, sizeof(int) * 4, cudaMemcpyHostToDevice);
vec_add<<<2,2>>>( gpu_l,gpu_r,4);
printf("Last error: %s \n", cudaGetErrorString(cudaDeviceSynchronize()));
cudaMemcpy(l, gpu_l, sizeof(int) * 4, cudaMemcpyDeviceToHost);
cudaFree( gpu_l);
for(int i = 0; i < 4; i++)
printf("l[%d] : %d\n", i, l[i]);
cudaMemcpy(r, gpu_r, sizeof(int) * 4, cudaMemcpyDeviceToHost);
cudaFree( gpu_r);
for(int i = 0; i < 4; i++)
printf("r[%d] : %d\n", i, r[i]);
} | code for sm_80
Function : _Z7vec_addPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void vec_add ( int * l, int * r, int n ){
int thid = threadIdx.x + blockDim.x * blockIdx.x;
if(thid >= n) return;
l[thid] += r[thid];
}
int main(){
int l[] = {1,2,3,4};
int * gpu_l;
cudaMalloc( &gpu_l, sizeof(int) * 4);
cudaMemcpy(gpu_l, l, sizeof(int) * 4, cudaMemcpyHostToDevice);
int r[] = {4, 3, 2, 1};
int * gpu_r;
cudaMalloc( &gpu_r, sizeof(int) * 4);
cudaMemcpy(gpu_r, r, sizeof(int) * 4, cudaMemcpyHostToDevice);
vec_add<<<2,2>>>( gpu_l,gpu_r,4);
printf("Last error: %s \n", cudaGetErrorString(cudaDeviceSynchronize()));
cudaMemcpy(l, gpu_l, sizeof(int) * 4, cudaMemcpyDeviceToHost);
cudaFree( gpu_l);
for(int i = 0; i < 4; i++)
printf("l[%d] : %d\n", i, l[i]);
cudaMemcpy(r, gpu_r, sizeof(int) * 4, cudaMemcpyDeviceToHost);
cudaFree( gpu_r);
for(int i = 0; i < 4; i++)
printf("r[%d] : %d\n", i, r[i]);
} | .file "tmpxft_000521b5_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7vec_addPiS_iPiS_i
.type _Z29__device_stub__Z7vec_addPiS_iPiS_i, @function
_Z29__device_stub__Z7vec_addPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vec_addPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7vec_addPiS_iPiS_i, .-_Z29__device_stub__Z7vec_addPiS_iPiS_i
.globl _Z7vec_addPiS_i
.type _Z7vec_addPiS_i, @function
_Z7vec_addPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7vec_addPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7vec_addPiS_i, .-_Z7vec_addPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Last error: %s \n"
.LC1:
.string "l[%d] : %d\n"
.LC2:
.string "r[%d] : %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 64(%rsp)
movl $3, 68(%rsp)
movl $2, 72(%rsp)
movl $1, 76(%rsp)
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L13:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L13
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L14:
movl 64(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L14
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $4, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z7vec_addPiS_iPiS_i
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7vec_addPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vec_addPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void vec_add ( int * l, int * r, int n ){
int thid = threadIdx.x + blockDim.x * blockIdx.x;
if(thid >= n) return;
l[thid] += r[thid];
}
int main(){
int l[] = {1,2,3,4};
int * gpu_l;
cudaMalloc( &gpu_l, sizeof(int) * 4);
cudaMemcpy(gpu_l, l, sizeof(int) * 4, cudaMemcpyHostToDevice);
int r[] = {4, 3, 2, 1};
int * gpu_r;
cudaMalloc( &gpu_r, sizeof(int) * 4);
cudaMemcpy(gpu_r, r, sizeof(int) * 4, cudaMemcpyHostToDevice);
vec_add<<<2,2>>>( gpu_l,gpu_r,4);
printf("Last error: %s \n", cudaGetErrorString(cudaDeviceSynchronize()));
cudaMemcpy(l, gpu_l, sizeof(int) * 4, cudaMemcpyDeviceToHost);
cudaFree( gpu_l);
for(int i = 0; i < 4; i++)
printf("l[%d] : %d\n", i, l[i]);
cudaMemcpy(r, gpu_r, sizeof(int) * 4, cudaMemcpyDeviceToHost);
cudaFree( gpu_r);
for(int i = 0; i < 4; i++)
printf("r[%d] : %d\n", i, r[i]);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vec_add ( int * l, int * r, int n ){
int thid = threadIdx.x + blockDim.x * blockIdx.x;
if(thid >= n) return;
l[thid] += r[thid];
}
int main(){
int l[] = {1,2,3,4};
int * gpu_l;
hipMalloc( &gpu_l, sizeof(int) * 4);
hipMemcpy(gpu_l, l, sizeof(int) * 4, hipMemcpyHostToDevice);
int r[] = {4, 3, 2, 1};
int * gpu_r;
hipMalloc( &gpu_r, sizeof(int) * 4);
hipMemcpy(gpu_r, r, sizeof(int) * 4, hipMemcpyHostToDevice);
vec_add<<<2,2>>>( gpu_l,gpu_r,4);
printf("Last error: %s \n", hipGetErrorString(hipDeviceSynchronize()));
hipMemcpy(l, gpu_l, sizeof(int) * 4, hipMemcpyDeviceToHost);
hipFree( gpu_l);
for(int i = 0; i < 4; i++)
printf("l[%d] : %d\n", i, l[i]);
hipMemcpy(r, gpu_r, sizeof(int) * 4, hipMemcpyDeviceToHost);
hipFree( gpu_r);
for(int i = 0; i < 4; i++)
printf("r[%d] : %d\n", i, r[i]);
} |
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