system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void poisson_jacobi_kernel(float *targetimg, float *outimg, int *boundary_array,int c, int w, int h, int boundBoxMinX, int boundBoxMaxX, int boundBoxMinY, int boundBoxMaxY){
int x = threadIdx.x + blockIdx.x * blockDim.x + boundBoxMinX;
int y = threadIdx.y + blockIdx.y * blockDim.y + boundBoxMinY;
for(int channel = 0; channel < c; channel++){
int id = x + y*w + channel * w * h;
int idx_nextX = x+1 + w*y +w*h*channel;
int idx_prevX = x-1 + w*y + w*h*channel;
int idx_nextY = x + w*(y+1) +w*h*channel;
int idx_prevY = x + w*(y-1) +w*h*channel;
//printf("id: %d, idx_nextX: %d, idx_prevX: %d, idx_nextY: %d, idx_prevY: %d\n", id, idx_nextX, idx_prevX, idx_nextY, idx_prevY);
if(boundary_array[id] == INSIDE_MASK){
double neighbor_target = targetimg[idx_nextY]+targetimg[idx_nextX]+targetimg[idx_prevX]+targetimg[idx_prevY];
double neighbor_output = outimg[idx_nextY]+outimg[idx_nextX]+outimg[idx_prevX]+outimg[idx_prevY];
outimg[id] = 0.25*(4*targetimg[id]-neighbor_target + neighbor_output);
}
}
} | .text
.file "poisson_jacobi_kernel.hip"
.globl _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii # -- Begin function _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.p2align 4, 0x90
.type _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii,@function
_Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii: # @_Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21poisson_jacobi_kernelPfS_Piiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii, .Lfunc_end0-_Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21poisson_jacobi_kernelPfS_Piiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21poisson_jacobi_kernelPfS_Piiiiiiii,@object # @_Z21poisson_jacobi_kernelPfS_Piiiiiiii
.section .rodata,"a",@progbits
.globl _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.p2align 3, 0x0
_Z21poisson_jacobi_kernelPfS_Piiiiiiii:
.quad _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.size _Z21poisson_jacobi_kernelPfS_Piiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21poisson_jacobi_kernelPfS_Piiiiiiii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002600 */
/*0050*/ ISETP.NE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f05270 */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0070*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102027812 */
/* 0x000fe400078ec0ff */
/*00b0*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*00c0*/ IMAD R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a24 */
/* 0x000fc600078e02ff */
/*00d0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*00e0*/ IMAD R5, R9, c[0x0][0x4], R6 ; /* 0x0000010009057a24 */
/* 0x001fca00078e0206 */
/*00f0*/ IADD3 R5, R5, c[0x0][0x18c], RZ ; /* 0x0000630005057a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ @!P0 BRA 0x780 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, R6, c[0x0][0x18c], RZ ; /* 0x0000630006067a10 */
/* 0x002fe20007ffe0ff */
/*0120*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0130*/ IADD3 R7, R3, c[0x0][0x184], RZ ; /* 0x0000610003077a10 */
/* 0x004fe40007ffe0ff */
/*0140*/ IADD3 R8, R6, c[0x0][0x180], RZ ; /* 0x0000600006087a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD R10, R9.reuse, c[0x0][0x4], R6 ; /* 0x00000100090a7a24 */
/* 0x040fe400078e0206 */
/*0160*/ IMAD R6, R0, c[0x0][0x0], R7 ; /* 0x0000000000067a24 */
/* 0x000fe400078e0207 */
/*0170*/ IMAD R9, R9, c[0x0][0x4], R8 ; /* 0x0000010009097a24 */
/* 0x000fe200078e0208 */
/*0180*/ IADD3 R11, R10.reuse, 0x1, RZ ; /* 0x000000010a0b7810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD R7, R5, c[0x0][0x17c], R6 ; /* 0x00005f0005077a24 */
/* 0x000fe200078e0206 */
/*01a0*/ IADD3 R13, R10, -0x1, RZ ; /* 0xffffffff0a0d7810 */
/* 0x000fc40007ffe0ff */
/*01b0*/ IADD3 R15, R9, -0x1, RZ ; /* 0xffffffff090f7810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD R11, R11, c[0x0][0x17c], R6.reuse ; /* 0x00005f000b0b7a24 */
/* 0x100fe200078e0206 */
/*01d0*/ IADD3 R25, R9.reuse, 0x1, RZ ; /* 0x0000000109197810 */
/* 0x040fe20007ffe0ff */
/*01e0*/ IMAD R9, R9, c[0x0][0x17c], R6.reuse ; /* 0x00005f0009097a24 */
/* 0x100fe200078e0206 */
/*01f0*/ IADD3 R27, R7, 0x1, RZ ; /* 0x00000001071b7810 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD R13, R13, c[0x0][0x17c], R6.reuse ; /* 0x00005f000d0d7a24 */
/* 0x100fe400078e0206 */
/*0210*/ IMAD R15, R15, c[0x0][0x17c], R6.reuse ; /* 0x00005f000f0f7a24 */
/* 0x100fe400078e0206 */
/*0220*/ IMAD R25, R25, c[0x0][0x17c], R6 ; /* 0x00005f0019197a24 */
/* 0x000fe200078e0206 */
/*0230*/ IADD3 R6, R2, -c[0x0][0x178], RZ ; /* 0x80005e0002067a10 */
/* 0x000fc40007ffe0ff */
/*0240*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0250*/ IMAD.WIDE R16, R7, R8, c[0x0][0x170] ; /* 0x00005c0007107625 */
/* 0x001fcc00078e0208 */
/*0260*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea2000c1e1900 */
/*0270*/ BSSY B0, 0x490 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fda0003f05270 */
/*0290*/ @P0 BRA 0x480 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.WIDE R28, R11, R8, c[0x0][0x160] ; /* 0x000058000b1c7625 */
/* 0x000fc800078e0208 */
/*02b0*/ IMAD.WIDE R18, R27, R8.reuse, c[0x0][0x160] ; /* 0x000058001b127625 */
/* 0x080fe200078e0208 */
/*02c0*/ LDG.E R10, [R28.64] ; /* 0x000000061c0a7981 */
/* 0x0000a6000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R11, R8.reuse, c[0x0][0x168] ; /* 0x00005a000b147625 */
/* 0x080fe200078e0208 */
/*02e0*/ LDG.E R12, [R18.64] ; /* 0x00000006120c7981 */
/* 0x000ea6000c1e1900 */
/*02f0*/ IMAD.WIDE R16, R27, R8.reuse, c[0x0][0x168] ; /* 0x00005a001b107625 */
/* 0x080fe200078e0208 */
/*0300*/ LDG.E R24, [R18.64+-0x8] ; /* 0xfffff80612187981 */
/* 0x000ee6000c1e1900 */
/*0310*/ IMAD.WIDE R22, R13.reuse, R8.reuse, c[0x0][0x160] ; /* 0x000058000d167625 */
/* 0x0c0fe200078e0208 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000328000c1e1900 */
/*0330*/ LDG.E R26, [R16.64] ; /* 0x00000006101a7981 */
/* 0x000f22000c1e1900 */
/*0340*/ IMAD.WIDE R28, R13, R8, c[0x0][0x168] ; /* 0x00005a000d1c7625 */
/* 0x001fc600078e0208 */
/*0350*/ LDG.E R14, [R18.64+-0x4] ; /* 0xfffffc06120e7981 */
/* 0x000f68000c1e1900 */
/*0360*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R21, [R16.64+-0x8] ; /* 0xfffff80610157981 */
/* 0x002f68000c1e1900 */
/*0380*/ LDG.E R28, [R28.64] ; /* 0x000000061c1c7981 */
/* 0x000f62000c1e1900 */
/*0390*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x004fc80000000000 */
/*03a0*/ FADD R10, R10, R24 ; /* 0x000000180a0a7221 */
/* 0x008fe40000000000 */
/*03b0*/ FADD R26, R26, R20 ; /* 0x000000141a1a7221 */
/* 0x010fe40000000000 */
/*03c0*/ FMUL R14, R14, 4 ; /* 0x408000000e0e7820 */
/* 0x020fe40000400000 */
/*03d0*/ FADD R10, R10, R22 ; /* 0x000000160a0a7221 */
/* 0x000fe40000000000 */
/*03e0*/ FADD R26, R26, R21 ; /* 0x000000151a1a7221 */
/* 0x000fe20000000000 */
/*03f0*/ F2F.F64.F32 R18, R14 ; /* 0x0000000e00127310 */
/* 0x000fe60000201800 */
/*0400*/ FADD R22, R26, R28 ; /* 0x0000001c1a167221 */
/* 0x000fca0000000000 */
/*0410*/ F2F.F64.F32 R20, R10 ; /* 0x0000000a00147310 */
/* 0x000e300000201800 */
/*0420*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x000e620000201800 */
/*0430*/ DADD R18, -R20, R18 ; /* 0x0000000014127229 */
/* 0x001e4c0000000112 */
/*0440*/ DADD R18, R22, R18 ; /* 0x0000000016127229 */
/* 0x002e0c0000000012 */
/*0450*/ DMUL R18, R18, 0.25 ; /* 0x3fd0000012127828 */
/* 0x001e140000000000 */
/*0460*/ F2F.F32.F64 R19, R18 ; /* 0x0000001200137310 */
/* 0x001e240000301000 */
/*0470*/ STG.E [R16.64+-0x4], R19 ; /* 0xfffffc1310007986 */
/* 0x0011e4000c101906 */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0490*/ IMAD.WIDE R16, R9, R8, c[0x0][0x170] ; /* 0x00005c0009107625 */
/* 0x001fcc00078e0208 */
/*04a0*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ BSSY B0, 0x6d0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*04c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fda0003f05270 */
/*04d0*/ @P0 BRA 0x6c0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*04e0*/ IMAD.WIDE R28, R25, R8, c[0x0][0x160] ; /* 0x00005800191c7625 */
/* 0x000fc800078e0208 */
/*04f0*/ IMAD.WIDE R18, R9, R8.reuse, c[0x0][0x160] ; /* 0x0000580009127625 */
/* 0x080fe200078e0208 */
/*0500*/ LDG.E R10, [R28.64] ; /* 0x000000061c0a7981 */
/* 0x0000a6000c1e1900 */
/*0510*/ IMAD.WIDE R20, R25, R8.reuse, c[0x0][0x168] ; /* 0x00005a0019147625 */
/* 0x080fe200078e0208 */
/*0520*/ LDG.E R12, [R18.64+0x4] ; /* 0x00000406120c7981 */
/* 0x000ea6000c1e1900 */
/*0530*/ IMAD.WIDE R16, R9, R8.reuse, c[0x0][0x168] ; /* 0x00005a0009107625 */
/* 0x080fe200078e0208 */
/*0540*/ LDG.E R24, [R18.64+-0x4] ; /* 0xfffffc0612187981 */
/* 0x000ee6000c1e1900 */
/*0550*/ IMAD.WIDE R22, R15.reuse, R8.reuse, c[0x0][0x160] ; /* 0x000058000f167625 */
/* 0x0c0fe200078e0208 */
/*0560*/ LDG.E R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R26, [R16.64+0x4] ; /* 0x00000406101a7981 */
/* 0x000f22000c1e1900 */
/*0580*/ IMAD.WIDE R28, R15, R8, c[0x0][0x168] ; /* 0x00005a000f1c7625 */
/* 0x001fc600078e0208 */
/*0590*/ LDG.E R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x000f68000c1e1900 */
/*05a0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000f68000c1e1900 */
/*05b0*/ LDG.E R8, [R16.64+-0x4] ; /* 0xfffffc0610087981 */
/* 0x000f68000c1e1900 */
/*05c0*/ LDG.E R28, [R28.64] ; /* 0x000000061c1c7981 */
/* 0x000f62000c1e1900 */
/*05d0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x004fc80000000000 */
/*05e0*/ FADD R10, R10, R24 ; /* 0x000000180a0a7221 */
/* 0x008fe40000000000 */
/*05f0*/ FADD R26, R26, R20 ; /* 0x000000141a1a7221 */
/* 0x010fe40000000000 */
/*0600*/ FMUL R14, R14, 4 ; /* 0x408000000e0e7820 */
/* 0x020fe40000400000 */
/*0610*/ FADD R10, R10, R22 ; /* 0x000000160a0a7221 */
/* 0x000fe40000000000 */
/*0620*/ F2F.F64.F32 R18, R14 ; /* 0x0000000e00127310 */
/* 0x000fe20000201800 */
/*0630*/ FADD R8, R26, R8 ; /* 0x000000081a087221 */
/* 0x000fce0000000000 */
/*0640*/ F2F.F64.F32 R20, R10 ; /* 0x0000000a00147310 */
/* 0x000e220000201800 */
/*0650*/ FADD R8, R8, R28 ; /* 0x0000001c08087221 */
/* 0x000fce0000000000 */
/*0660*/ F2F.F64.F32 R22, R8 ; /* 0x0000000800167310 */
/* 0x000e620000201800 */
/*0670*/ DADD R18, -R20, R18 ; /* 0x0000000014127229 */
/* 0x001e4c0000000112 */
/*0680*/ DADD R18, R22, R18 ; /* 0x0000000016127229 */
/* 0x002e0c0000000012 */
/*0690*/ DMUL R18, R18, 0.25 ; /* 0x3fd0000012127828 */
/* 0x001e140000000000 */
/*06a0*/ F2F.F32.F64 R19, R18 ; /* 0x0000001200137310 */
/* 0x001e240000301000 */
/*06b0*/ STG.E [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0011e4000c101906 */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ UIADD3 UR4, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fe2000fffe03f */
/*06e0*/ LEA R9, R4.reuse, R9, 0x1 ; /* 0x0000000904097211 */
/* 0x040fe400078e08ff */
/*06f0*/ LEA R15, R4.reuse, R15, 0x1 ; /* 0x0000000f040f7211 */
/* 0x040fe400078e08ff */
/*0700*/ LEA R25, R4, R25, 0x1 ; /* 0x0000001904197211 */
/* 0x000fe400078e08ff */
/*0710*/ IADD3 R8, R6, UR4, RZ ; /* 0x0000000406087c10 */
/* 0x000fe4000fffe0ff */
/*0720*/ LEA R27, R4, R27, 0x1 ; /* 0x0000001b041b7211 */
/* 0x000fc400078e08ff */
/*0730*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0740*/ LEA R11, R4.reuse, R11, 0x1 ; /* 0x0000000b040b7211 */
/* 0x040fe400078e08ff */
/*0750*/ LEA R13, R4.reuse, R13, 0x1 ; /* 0x0000000d040d7211 */
/* 0x040fe400078e08ff */
/*0760*/ LEA R7, R4, R7, 0x1 ; /* 0x0000000704077211 */
/* 0x000fce00078e08ff */
/*0770*/ @P0 BRA 0x240 ; /* 0xfffffac000000947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x002fe20003f05270 */
/*0790*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fd800078e0203 */
/*07a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07b0*/ IADD3 R6, R0, c[0x0][0x184], RZ ; /* 0x0000610000067a10 */
/* 0x000fe40007ffe0ff */
/*07c0*/ MOV R0, 0x4 ; /* 0x0000000400007802 */
/* 0x000fc60000000f00 */
/*07d0*/ IMAD R3, R5, c[0x0][0x17c], R6 ; /* 0x00005f0005037a24 */
/* 0x000fc800078e0206 */
/*07e0*/ IMAD R9, R4, UR4, R3 ; /* 0x0000000404097c24 */
/* 0x000fc8000f8e0203 */
/*07f0*/ IMAD.WIDE R2, R9, R0, c[0x0][0x170] ; /* 0x00005c0009027625 */
/* 0x000fcc00078e0200 */
/*0800*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0810*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fca0000000f00 */
/*0820*/ IMAD R5, R5, R8, c[0x0][0x17c] ; /* 0x00005f0005057624 */
/* 0x000fe200078e0208 */
/*0830*/ IADD3 R8, RZ, -c[0x0][0x17c], RZ ; /* 0x80005f00ff087a10 */
/* 0x000fc80007ffe0ff */
/*0840*/ LEA R7, R8, R5.reuse, 0x1 ; /* 0x0000000508077211 */
/* 0x080fe400078e08ff */
/*0850*/ IADD3 R5, R6.reuse, R5, RZ ; /* 0x0000000506057210 */
/* 0x040fe40007ffe0ff */
/*0860*/ IADD3 R7, R6, R7, RZ ; /* 0x0000000706077210 */
/* 0x000fc60007ffe0ff */
/*0870*/ IMAD R11, R4.reuse, UR4, R5 ; /* 0x00000004040b7c24 */
/* 0x040fe4000f8e0205 */
/*0880*/ IMAD R13, R4, UR4, R7 ; /* 0x00000004040d7c24 */
/* 0x000fe2000f8e0207 */
/*0890*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*08a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08b0*/ IMAD.WIDE R4, R11, R0, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fc800078e0200 */
/*08c0*/ IMAD.WIDE R6, R9, R0.reuse, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x080fe400078e0200 */
/*08d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*08e0*/ IMAD.WIDE R10, R11, R0.reuse, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x080fe400078e0200 */
/*08f0*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000406060e7981 */
/* 0x000ea4000c1e1900 */
/*0900*/ IMAD.WIDE R2, R9, R0.reuse, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x080fe400078e0200 */
/*0910*/ LDG.E R16, [R6.64+-0x4] ; /* 0xfffffc0606107981 */
/* 0x001ee4000c1e1900 */
/*0920*/ IMAD.WIDE R8, R13, R0, c[0x0][0x160] ; /* 0x000058000d087625 */
/* 0x000fc400078e0200 */
/*0930*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f24000c1e1900 */
/*0940*/ IMAD.WIDE R12, R13, R0, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe400078e0200 */
/*0950*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040602117981 */
/* 0x000f28000c1e1900 */
/*0960*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000f68000c1e1900 */
/*0970*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000f68000c1e1900 */
/*0980*/ LDG.E R18, [R2.64+-0x4] ; /* 0xfffffc0602127981 */
/* 0x000f68000c1e1900 */
/*0990*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f62000c1e1900 */
/*09a0*/ FADD R5, R14, R5 ; /* 0x000000050e057221 */
/* 0x004fc80000000000 */
/*09b0*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x008fe40000000000 */
/*09c0*/ FADD R17, R17, R10 ; /* 0x0000000a11117221 */
/* 0x010fe40000000000 */
/*09d0*/ FMUL R15, R15, 4 ; /* 0x408000000f0f7820 */
/* 0x020fe40000400000 */
/*09e0*/ FADD R0, R5, R8 ; /* 0x0000000805007221 */
/* 0x000fe40000000000 */
/*09f0*/ FADD R17, R17, R18 ; /* 0x0000001211117221 */
/* 0x000fe40000000000 */
/*0a00*/ F2F.F64.F32 R14, R15 ; /* 0x0000000f000e7310 */
/* 0x000fe40000201800 */
/*0a10*/ FADD R6, R17, R12 ; /* 0x0000000c11067221 */
/* 0x000fcc0000000000 */
/*0a20*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x000e300000201800 */
/*0a30*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x000e620000201800 */
/*0a40*/ DADD R4, -R4, R14 ; /* 0x0000000004047229 */
/* 0x001e4c000000010e */
/*0a50*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e0c0000000004 */
/*0a60*/ DMUL R4, R4, 0.25 ; /* 0x3fd0000004047828 */
/* 0x001e140000000000 */
/*0a70*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0a80*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0a90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0aa0*/ BRA 0xaa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.globl _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.p2align 8
.type _Z21poisson_jacobi_kernelPfS_Piiiiiiii,@function
_Z21poisson_jacobi_kernelPfS_Piiiiiiii:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x3
s_load_b32 s3, s[0:1], 0x44
s_load_b32 s10, s[0:1], 0x2c
s_load_b32 s11, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s3, 16
s_and_b32 s3, s3, 0xffff
s_mul_i32 s15, s15, s12
v_add_nc_u32_e32 v2, s11, v0
v_add3_u32 v1, s15, s10, v1
s_mul_i32 s14, s14, s3
s_mul_i32 s3, s9, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v1, s8
v_add_nc_u32_e32 v4, -1, v1
v_mad_u64_u32 v[0:1], null, v4, s8, v[2:3]
v_add3_u32 v5, v3, s8, v2
v_add_nc_u32_e32 v6, v2, v3
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v5, s3, v5
v_add_nc_u32_e32 v0, s3, v0
v_add_nc_u32_e32 v6, s3, v6
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s14, v6
s_mov_b32 s8, exec_lo
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[3:4]
v_add_co_u32 v7, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v2, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v7, s14, v5
v_add_nc_u32_e32 v9, 1, v3
v_add_nc_u32_e32 v3, -1, v3
v_add_nc_u32_e32 v11, s14, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v15, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v4, vcc_lo
s_clause 0x2
global_load_b32 v19, v[13:14], off
global_load_b32 v20, v[15:16], off
global_load_b32 v17, v[17:18], off
v_add_co_u32 v13, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v15, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[15:16], off
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_clause 0x1
global_load_b32 v15, v[7:8], off
global_load_b32 v9, v[9:10], off
v_add_co_u32 v7, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v12, vcc_lo
s_clause 0x1
global_load_b32 v10, v[3:4], off
global_load_b32 v11, v[7:8], off
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt vmcnt(7)
v_add_f32_e32 v3, v19, v20
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v17
s_waitcnt vmcnt(5)
v_add_f32_e32 v3, v3, v13
s_waitcnt vmcnt(4)
v_mul_f32_e32 v7, 4.0, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[3:4], v3
v_cvt_f64_f32_e32 v[7:8], v7
s_waitcnt vmcnt(2)
v_add_f32_e32 v9, v15, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v9, v10
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_add_f64 v[3:4], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], -2
v_cvt_f32_f64_e32 v3, v[3:4]
global_store_b32 v[1:2], v3, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21poisson_jacobi_kernelPfS_Piiiiiiii, .Lfunc_end0-_Z21poisson_jacobi_kernelPfS_Piiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21poisson_jacobi_kernelPfS_Piiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00093fc1_00000000-6_poisson_jacobi_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z21poisson_jacobi_kernelPfS_PiiiiiiiiPfS_Piiiiiiii
.type _Z52__device_stub__Z21poisson_jacobi_kernelPfS_PiiiiiiiiPfS_Piiiiiiii, @function
_Z52__device_stub__Z21poisson_jacobi_kernelPfS_PiiiiiiiiPfS_Piiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21poisson_jacobi_kernelPfS_Piiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z21poisson_jacobi_kernelPfS_PiiiiiiiiPfS_Piiiiiiii, .-_Z52__device_stub__Z21poisson_jacobi_kernelPfS_PiiiiiiiiPfS_Piiiiiiii
.globl _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.type _Z21poisson_jacobi_kernelPfS_Piiiiiiii, @function
_Z21poisson_jacobi_kernelPfS_Piiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z52__device_stub__Z21poisson_jacobi_kernelPfS_PiiiiiiiiPfS_Piiiiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21poisson_jacobi_kernelPfS_Piiiiiiii, .-_Z21poisson_jacobi_kernelPfS_Piiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21poisson_jacobi_kernelPfS_Piiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21poisson_jacobi_kernelPfS_Piiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "poisson_jacobi_kernel.hip"
.globl _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii # -- Begin function _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.p2align 4, 0x90
.type _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii,@function
_Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii: # @_Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21poisson_jacobi_kernelPfS_Piiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii, .Lfunc_end0-_Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21poisson_jacobi_kernelPfS_Piiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21poisson_jacobi_kernelPfS_Piiiiiiii,@object # @_Z21poisson_jacobi_kernelPfS_Piiiiiiii
.section .rodata,"a",@progbits
.globl _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.p2align 3, 0x0
_Z21poisson_jacobi_kernelPfS_Piiiiiiii:
.quad _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.size _Z21poisson_jacobi_kernelPfS_Piiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21poisson_jacobi_kernelPfS_Piiiiiiii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__poisson_jacobi_kernelPfS_Piiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21poisson_jacobi_kernelPfS_Piiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define W 500
#define H 500
#define TX 32
#define TY 32
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos)
{
const int c = blockIdx.x*blockDim.x+threadIdx.x;
const int r = blockIdx.y*blockDim.y+threadIdx.y;
const int i = c+r*w;
if((c>=w) || (r>=h)) return;
d_out[i]=sqrtf((c-pos.x)*(c-pos.x)+(r-pos.y)*(r-pos.y));
}
int main()
{
float *out=(float *)calloc(W*H, sizeof(float));
float *d_out;
cudaMalloc(&d_out, W*H*sizeof(float));
const float2 pos={0.0f,0.0f};
const dim3 blockSize(TX,TY);
const int bx = (W+TX-1)/TX;
const int by = (H+TY-1)/TY;
const dim3 gridSize(bx,by);
distanceKernel<<<gridSize,blockSize>>>(d_out, W,H,pos);
cudaMemcpy(out, d_out, W*H*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPfii6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e220000201400 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x1e0 ; /* 0x0000011000007945 */
/* 0x000fec0003800000 */
/*00d0*/ I2F R2, R5 ; /* 0x0000000500027306 */
/* 0x000e620000201400 */
/*00e0*/ FADD R3, R3, -c[0x0][0x174] ; /* 0x80005d0003037621 */
/* 0x001fc80000000000 */
/*00f0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x000fe40000400000 */
/*0100*/ FADD R2, R2, -c[0x0][0x170] ; /* 0x80005c0002027621 */
/* 0x002fc80000000000 */
/*0110*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000003 */
/*0120*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R8, 0x180 ; /* 0x0000018000087802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x230 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R2 ; /* 0x0000000203047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R7, R3, R2, R4 ; /* 0x0000000203077223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*01f0*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x000fd200078e0205 */
/*0200*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0240*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fe20000000f00 */
/*0250*/ @!P0 BRA 0x360 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0270*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0280*/ @!P0 BRA 0x360 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*02a0*/ @P0 FADD.FTZ R2, R3, 1 ; /* 0x3f80000003020421 */
/* 0x000fe20000010000 */
/*02b0*/ @P0 BRA 0x360 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*02d0*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*02e0*/ @P0 MUFU.RSQ R7, R4 ; /* 0x0000000400070308 */
/* 0x000e240000001400 */
/*02f0*/ @P0 FMUL.FTZ R9, R4, R7 ; /* 0x0000000704090220 */
/* 0x001fe40000410000 */
/*0300*/ @P0 FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007070820 */
/* 0x000fe40000410000 */
/*0310*/ @P0 FADD.FTZ R2, -R9, -RZ ; /* 0x800000ff09020221 */
/* 0x000fc80000010100 */
/*0320*/ @P0 FFMA R6, R9, R2, R4 ; /* 0x0000000209060223 */
/* 0x000fe20000000004 */
/*0330*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fc60000000f00 */
/*0340*/ @P0 FFMA R6, R6, R7, R9 ; /* 0x0000000706060223 */
/* 0x000fc80000000009 */
/*0350*/ @P0 FMUL.FTZ R2, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006020820 */
/* 0x000fc80000410000 */
/*0360*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0370*/ MOV R7, R2 ; /* 0x0000000200077202 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0390*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc6002007950 */
/* 0x000fea0003c3ffff */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define W 500
#define H 500
#define TX 32
#define TY 32
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos)
{
const int c = blockIdx.x*blockDim.x+threadIdx.x;
const int r = blockIdx.y*blockDim.y+threadIdx.y;
const int i = c+r*w;
if((c>=w) || (r>=h)) return;
d_out[i]=sqrtf((c-pos.x)*(c-pos.x)+(r-pos.y)*(r-pos.y));
}
int main()
{
float *out=(float *)calloc(W*H, sizeof(float));
float *d_out;
cudaMalloc(&d_out, W*H*sizeof(float));
const float2 pos={0.0f,0.0f};
const dim3 blockSize(TX,TY);
const int bx = (W+TX-1)/TX;
const int by = (H+TY-1)/TY;
const dim3 gridSize(bx,by);
distanceKernel<<<gridSize,blockSize>>>(d_out, W,H,pos);
cudaMemcpy(out, d_out, W*H*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | .file "tmpxft_0003f393_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.type _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, @function
_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPfii6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, .-_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.globl _Z14distanceKernelPfii6float2
.type _Z14distanceKernelPfii6float2, @function
_Z14distanceKernelPfii6float2:
.LFB2053:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %xmm0, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14distanceKernelPfii6float2, .-_Z14distanceKernelPfii6float2
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $250000, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $1000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0x00000000, 8(%rsp)
movl $0x00000000, 12(%rsp)
leaq 8(%rsp), %rcx
movl $500, %edx
movl $500, %esi
movq (%rsp), %rdi
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPfii6float2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfii6float2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define W 500
#define H 500
#define TX 32
#define TY 32
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos)
{
const int c = blockIdx.x*blockDim.x+threadIdx.x;
const int r = blockIdx.y*blockDim.y+threadIdx.y;
const int i = c+r*w;
if((c>=w) || (r>=h)) return;
d_out[i]=sqrtf((c-pos.x)*(c-pos.x)+(r-pos.y)*(r-pos.y));
}
int main()
{
float *out=(float *)calloc(W*H, sizeof(float));
float *d_out;
cudaMalloc(&d_out, W*H*sizeof(float));
const float2 pos={0.0f,0.0f};
const dim3 blockSize(TX,TY);
const int bx = (W+TX-1)/TX;
const int by = (H+TY-1)/TY;
const dim3 gridSize(bx,by);
distanceKernel<<<gridSize,blockSize>>>(d_out, W,H,pos);
cudaMemcpy(out, d_out, W*H*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_out);
free(out);
return 0;
} | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32
#define TY 32
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos)
{
const int c = blockIdx.x*blockDim.x+threadIdx.x;
const int r = blockIdx.y*blockDim.y+threadIdx.y;
const int i = c+r*w;
if((c>=w) || (r>=h)) return;
d_out[i]=sqrtf((c-pos.x)*(c-pos.x)+(r-pos.y)*(r-pos.y));
}
int main()
{
float *out=(float *)calloc(W*H, sizeof(float));
float *d_out;
hipMalloc(&d_out, W*H*sizeof(float));
const float2 pos={0.0f,0.0f};
const dim3 blockSize(TX,TY);
const int bx = (W+TX-1)/TX;
const int by = (H+TY-1)/TY;
const dim3 gridSize(bx,by);
distanceKernel<<<gridSize,blockSize>>>(d_out, W,H,pos);
hipMemcpy(out, d_out, W*H*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32
#define TY 32
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos)
{
const int c = blockIdx.x*blockDim.x+threadIdx.x;
const int r = blockIdx.y*blockDim.y+threadIdx.y;
const int i = c+r*w;
if((c>=w) || (r>=h)) return;
d_out[i]=sqrtf((c-pos.x)*(c-pos.x)+(r-pos.y)*(r-pos.y));
}
int main()
{
float *out=(float *)calloc(W*H, sizeof(float));
float *d_out;
hipMalloc(&d_out, W*H*sizeof(float));
const float2 pos={0.0f,0.0f};
const dim3 blockSize(TX,TY);
const int bx = (W+TX-1)/TX;
const int by = (H+TY-1)/TY;
const dim3 gridSize(bx,by);
distanceKernel<<<gridSize,blockSize>>>(d_out, W,H,pos);
hipMemcpy(out, d_out, W*H*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_subrev_f32 v2, s2, v2 :: v_dual_subrev_f32 v3, s3, v3
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v6, v2, v3, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v7
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cndmask_b32_e64 v0, v6, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_f32_e32 v1, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v0, v1, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define W 500
#define H 500
#define TX 32
#define TY 32
__global__
void distanceKernel(float *d_out, int w, int h, float2 pos)
{
const int c = blockIdx.x*blockDim.x+threadIdx.x;
const int r = blockIdx.y*blockDim.y+threadIdx.y;
const int i = c+r*w;
if((c>=w) || (r>=h)) return;
d_out[i]=sqrtf((c-pos.x)*(c-pos.x)+(r-pos.y)*(r-pos.y));
}
int main()
{
float *out=(float *)calloc(W*H, sizeof(float));
float *d_out;
hipMalloc(&d_out, W*H*sizeof(float));
const float2 pos={0.0f,0.0f};
const dim3 blockSize(TX,TY);
const int bx = (W+TX-1)/TX;
const int by = (H+TY-1)/TY;
const dim3 gridSize(bx,by);
distanceKernel<<<gridSize,blockSize>>>(d_out, W,H,pos);
hipMemcpy(out, d_out, W*H*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_out);
free(out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE # -- Begin function _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE: # @_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $250000, %edi # imm = 0x3D090
movl $4, %esi
callq calloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq $0, 72(%rsp)
movq %rax, 64(%rsp)
movl $500, 12(%rsp) # imm = 0x1F4
movl $500, 8(%rsp) # imm = 0x1F4
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@object # @_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
.quad _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14distanceKernelPfii6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e220000201400 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x1e0 ; /* 0x0000011000007945 */
/* 0x000fec0003800000 */
/*00d0*/ I2F R2, R5 ; /* 0x0000000500027306 */
/* 0x000e620000201400 */
/*00e0*/ FADD R3, R3, -c[0x0][0x174] ; /* 0x80005d0003037621 */
/* 0x001fc80000000000 */
/*00f0*/ FMUL R3, R3, R3 ; /* 0x0000000303037220 */
/* 0x000fe40000400000 */
/*0100*/ FADD R2, R2, -c[0x0][0x170] ; /* 0x80005c0002027621 */
/* 0x002fc80000000000 */
/*0110*/ FFMA R3, R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000003 */
/*0120*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R8, 0x180 ; /* 0x0000018000087802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x230 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R2 ; /* 0x0000000203047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R7, R3, R2, R4 ; /* 0x0000000203077223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*01f0*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x000fd200078e0205 */
/*0200*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0240*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fe20000000f00 */
/*0250*/ @!P0 BRA 0x360 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0270*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0280*/ @!P0 BRA 0x360 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*02a0*/ @P0 FADD.FTZ R2, R3, 1 ; /* 0x3f80000003020421 */
/* 0x000fe20000010000 */
/*02b0*/ @P0 BRA 0x360 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*02d0*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*02e0*/ @P0 MUFU.RSQ R7, R4 ; /* 0x0000000400070308 */
/* 0x000e240000001400 */
/*02f0*/ @P0 FMUL.FTZ R9, R4, R7 ; /* 0x0000000704090220 */
/* 0x001fe40000410000 */
/*0300*/ @P0 FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007070820 */
/* 0x000fe40000410000 */
/*0310*/ @P0 FADD.FTZ R2, -R9, -RZ ; /* 0x800000ff09020221 */
/* 0x000fc80000010100 */
/*0320*/ @P0 FFMA R6, R9, R2, R4 ; /* 0x0000000209060223 */
/* 0x000fe20000000004 */
/*0330*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fc60000000f00 */
/*0340*/ @P0 FFMA R6, R6, R7, R9 ; /* 0x0000000706060223 */
/* 0x000fc80000000009 */
/*0350*/ @P0 FMUL.FTZ R2, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006020820 */
/* 0x000fc80000410000 */
/*0360*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0370*/ MOV R7, R2 ; /* 0x0000000200077202 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0390*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc6002007950 */
/* 0x000fea0003c3ffff */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_subrev_f32 v2, s2, v2 :: v_dual_subrev_f32 v3, s3, v3
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v3
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v2, v3, vcc_lo
v_sqrt_f32_e32 v2, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v2, v4
v_fma_f32 v7, -v5, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v6, v2, v3, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v7
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cndmask_b32_e64 v0, v6, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_f32_e32 v1, 0x37800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v0, v1, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003f393_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.type _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, @function
_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movq %rcx, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPfii6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2, .-_Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
.globl _Z14distanceKernelPfii6float2
.type _Z14distanceKernelPfii6float2, @function
_Z14distanceKernelPfii6float2:
.LFB2053:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %xmm0, 8(%rsp)
leaq 8(%rsp), %rcx
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14distanceKernelPfii6float2, .-_Z14distanceKernelPfii6float2
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $250000, %edi
call calloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $16, 28(%rsp)
movl $16, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $1000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $0x00000000, 8(%rsp)
movl $0x00000000, 12(%rsp)
leaq 8(%rsp), %rcx
movl $500, %edx
movl $500, %esi
movq (%rsp), %rdi
call _Z43__device_stub__Z14distanceKernelPfii6float2PfiiR6float2
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPfii6float2"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfii6float2(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE # -- Begin function _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE,@function
_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE: # @_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $250000, %edi # imm = 0x3D090
movl $4, %esi
callq calloc
movq %rax, %rbx
movq %rsp, %rdi
movl $1000000, %esi # imm = 0xF4240
callq hipMalloc
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq $0, 72(%rsp)
movq %rax, 64(%rsp)
movl $500, 12(%rsp) # imm = 0x1F4
movl $500, 8(%rsp) # imm = 0x1F4
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $1000000, %edx # imm = 0xF4240
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE,@object # @_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE:
.quad _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.size _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfii15HIP_vector_typeIfLj2EE"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfii15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "deinterleave.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
#include "summed_area_table.cuh"
__global__ void deinterleave_kernel(unsigned char* image, unsigned int NxN, float* r, float* g, float* b)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < NxN) {
unsigned char* pixelOffset = image + tid * 3;
r[tid] = pixelOffset[0];
g[tid] = pixelOffset[1];
b[tid] = pixelOffset[2];
tid += blockDim.x * gridDim.x;
}
}
void deinterleave(unsigned char* image, unsigned int NxN, float** r, float** g, float** b)
{
//input: img
//output: r, g, b
unsigned char* dev_img;
cudaMalloc((void**)&dev_img, 3 * NxN * sizeof(char));
float* dev_r, *dev_g, *dev_b;
cudaMalloc((void**)&dev_r, NxN * sizeof(float));
cudaMalloc((void**)&dev_g, NxN * sizeof(float));
cudaMalloc((void**)&dev_b, NxN * sizeof(float));
cudaMemcpy(dev_img, image, 3 * NxN * sizeof(char), cudaMemcpyHostToDevice);
deinterleave_kernel << <512, 512>> > (dev_img, NxN, dev_r, dev_g, dev_b);
cudaMemcpy(*r, dev_r, NxN * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(*g, dev_g, NxN * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(*b, dev_b, NxN * sizeof(float), cudaMemcpyDeviceToHost);
/*for (int i = 0; i < 4; i++)
{
for (int j = 0; j < 4; j++)
{
std::cout << *r[i * 512 + j] << " ";
}
std::cout << std::endl;
}
std::cout << std::endl;*/
cudaFree(dev_r);
cudaFree(dev_g);
cudaFree(dev_b);
}
//int main()
//{
// //input: img
// //output: r, g, b
//
// unsigned int N = 4; //N x N image
//
// unsigned char* img = (unsigned char*)malloc(3 * N * N * sizeof(char));
// for (int i = 0; i < 3 * N * N; i++)
// img[i] = 1;
// unsigned int* r = (unsigned int*)malloc(N * N * sizeof(int));
// unsigned int* g = (unsigned int*)malloc(N * N * sizeof(int));
// unsigned int* b = (unsigned int*)malloc(N * N *sizeof(int));
//
// deinterleave(img, N * N, &r, &g, &b);
//
// /*for (int i = 0; i < N; i++)
// {
// std::cout << r[i] << " " << g[i] << " " << b[i] << " ";
// }*/
//
// summed_area_table(g, N);
//
// for (int i = 0; i < N; i++)
// {
// for (int j = 0; j < N; j++)
// {
// std::cout << g[i * N + j] << " ";
// }
// std::cout << std::endl;
// }
//
//
// return 0;
//} | code for sm_80
Function : _Z19deinterleave_kernelPhjPfS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*0080*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00a0*/ LDG.E.U8 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fd400000001ff */
/*00c0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe200078e0209 */
/*00d0*/ I2F.U16 R11, R10 ; /* 0x0000000a000b7306 */
/* 0x004e280000101000 */
/*00e0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0011e8000c101904 */
/*00f0*/ LDG.E.U8 R12, [R2.64+0x1] ; /* 0x00000104020c7981 */
/* 0x000ea2000c1e1100 */
/*0100*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x0c0fe200078e0209 */
/*0110*/ I2F.U16 R13, R12 ; /* 0x0000000c000d7306 */
/* 0x004e680000101000 */
/*0120*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0021e8000c101904 */
/*0130*/ LDG.E.U8 R14, [R2.64+0x2] ; /* 0x00000204020e7981 */
/* 0x000ea2000c1e1100 */
/*0140*/ IMAD.WIDE R8, R0, R9, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fe200078e0209 */
/*0150*/ MOV R17, c[0x0][0x0] ; /* 0x0000000000117a02 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD R0, R17, c[0x0][0xc], R0 ; /* 0x0000030011007a24 */
/* 0x000fca00078e0200 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0180*/ I2F.U16 R15, R14 ; /* 0x0000000e000f7306 */
/* 0x004e640000101000 */
/*0190*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0021f4000c101904 */
/*01a0*/ @!P0 BRA 0x70 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "deinterleave.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
#include "summed_area_table.cuh"
__global__ void deinterleave_kernel(unsigned char* image, unsigned int NxN, float* r, float* g, float* b)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < NxN) {
unsigned char* pixelOffset = image + tid * 3;
r[tid] = pixelOffset[0];
g[tid] = pixelOffset[1];
b[tid] = pixelOffset[2];
tid += blockDim.x * gridDim.x;
}
}
void deinterleave(unsigned char* image, unsigned int NxN, float** r, float** g, float** b)
{
//input: img
//output: r, g, b
unsigned char* dev_img;
cudaMalloc((void**)&dev_img, 3 * NxN * sizeof(char));
float* dev_r, *dev_g, *dev_b;
cudaMalloc((void**)&dev_r, NxN * sizeof(float));
cudaMalloc((void**)&dev_g, NxN * sizeof(float));
cudaMalloc((void**)&dev_b, NxN * sizeof(float));
cudaMemcpy(dev_img, image, 3 * NxN * sizeof(char), cudaMemcpyHostToDevice);
deinterleave_kernel << <512, 512>> > (dev_img, NxN, dev_r, dev_g, dev_b);
cudaMemcpy(*r, dev_r, NxN * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(*g, dev_g, NxN * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(*b, dev_b, NxN * sizeof(float), cudaMemcpyDeviceToHost);
/*for (int i = 0; i < 4; i++)
{
for (int j = 0; j < 4; j++)
{
std::cout << *r[i * 512 + j] << " ";
}
std::cout << std::endl;
}
std::cout << std::endl;*/
cudaFree(dev_r);
cudaFree(dev_g);
cudaFree(dev_b);
}
//int main()
//{
// //input: img
// //output: r, g, b
//
// unsigned int N = 4; //N x N image
//
// unsigned char* img = (unsigned char*)malloc(3 * N * N * sizeof(char));
// for (int i = 0; i < 3 * N * N; i++)
// img[i] = 1;
// unsigned int* r = (unsigned int*)malloc(N * N * sizeof(int));
// unsigned int* g = (unsigned int*)malloc(N * N * sizeof(int));
// unsigned int* b = (unsigned int*)malloc(N * N *sizeof(int));
//
// deinterleave(img, N * N, &r, &g, &b);
//
// /*for (int i = 0; i < N; i++)
// {
// std::cout << r[i] << " " << g[i] << " " << b[i] << " ";
// }*/
//
// summed_area_table(g, N);
//
// for (int i = 0; i < N; i++)
// {
// for (int j = 0; j < N; j++)
// {
// std::cout << g[i * N + j] << " ";
// }
// std::cout << std::endl;
// }
//
//
// return 0;
//} | .file "tmpxft_00048fb3_00000000-6_deinterleave.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
.type _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_, @function
_Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19deinterleave_kernelPhjPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_, .-_Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
.globl _Z19deinterleave_kernelPhjPfS0_S0_
.type _Z19deinterleave_kernelPhjPfS0_S0_, @function
_Z19deinterleave_kernelPhjPfS0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z19deinterleave_kernelPhjPfS0_S0_, .-_Z19deinterleave_kernelPhjPfS0_S0_
.globl _Z12deinterleavePhjPPfS1_S1_
.type _Z12deinterleavePhjPPfS1_S1_, @function
_Z12deinterleavePhjPPfS1_S1_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, %ebp
movq %rdx, %r14
movq %rcx, %r13
movq %r8, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal (%rsi,%rsi,2), %r15d
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %ebp, %ebx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq (%r14), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 0(%r13), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq (%r12), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z12deinterleavePhjPPfS1_S1_, .-_Z12deinterleavePhjPPfS1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19deinterleave_kernelPhjPfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19deinterleave_kernelPhjPfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "deinterleave.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
#include "summed_area_table.cuh"
__global__ void deinterleave_kernel(unsigned char* image, unsigned int NxN, float* r, float* g, float* b)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < NxN) {
unsigned char* pixelOffset = image + tid * 3;
r[tid] = pixelOffset[0];
g[tid] = pixelOffset[1];
b[tid] = pixelOffset[2];
tid += blockDim.x * gridDim.x;
}
}
void deinterleave(unsigned char* image, unsigned int NxN, float** r, float** g, float** b)
{
//input: img
//output: r, g, b
unsigned char* dev_img;
cudaMalloc((void**)&dev_img, 3 * NxN * sizeof(char));
float* dev_r, *dev_g, *dev_b;
cudaMalloc((void**)&dev_r, NxN * sizeof(float));
cudaMalloc((void**)&dev_g, NxN * sizeof(float));
cudaMalloc((void**)&dev_b, NxN * sizeof(float));
cudaMemcpy(dev_img, image, 3 * NxN * sizeof(char), cudaMemcpyHostToDevice);
deinterleave_kernel << <512, 512>> > (dev_img, NxN, dev_r, dev_g, dev_b);
cudaMemcpy(*r, dev_r, NxN * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(*g, dev_g, NxN * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(*b, dev_b, NxN * sizeof(float), cudaMemcpyDeviceToHost);
/*for (int i = 0; i < 4; i++)
{
for (int j = 0; j < 4; j++)
{
std::cout << *r[i * 512 + j] << " ";
}
std::cout << std::endl;
}
std::cout << std::endl;*/
cudaFree(dev_r);
cudaFree(dev_g);
cudaFree(dev_b);
}
//int main()
//{
// //input: img
// //output: r, g, b
//
// unsigned int N = 4; //N x N image
//
// unsigned char* img = (unsigned char*)malloc(3 * N * N * sizeof(char));
// for (int i = 0; i < 3 * N * N; i++)
// img[i] = 1;
// unsigned int* r = (unsigned int*)malloc(N * N * sizeof(int));
// unsigned int* g = (unsigned int*)malloc(N * N * sizeof(int));
// unsigned int* b = (unsigned int*)malloc(N * N *sizeof(int));
//
// deinterleave(img, N * N, &r, &g, &b);
//
// /*for (int i = 0; i < N; i++)
// {
// std::cout << r[i] << " " << g[i] << " " << b[i] << " ";
// }*/
//
// summed_area_table(g, N);
//
// for (int i = 0; i < N; i++)
// {
// for (int j = 0; j < N; j++)
// {
// std::cout << g[i * N + j] << " ";
// }
// std::cout << std::endl;
// }
//
//
// return 0;
//} | #include <hip/hip_runtime.h>
void deinterleave(unsigned char* in_image, unsigned int NxN, float** out_r, float** out_g, float** out_b); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void deinterleave(unsigned char* in_image, unsigned int NxN, float** out_r, float** out_g, float** out_b); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void deinterleave(unsigned char* in_image, unsigned int NxN, float** out_r, float** out_g, float** out_b); | .text
.file "deinterleave.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19deinterleave_kernelPhjPfS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD R3, R0, 0x3, RZ ; /* 0x0000000300037824 */
/* 0x000fca00078e02ff */
/*0080*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*00a0*/ LDG.E.U8 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fd400000001ff */
/*00c0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe200078e0209 */
/*00d0*/ I2F.U16 R11, R10 ; /* 0x0000000a000b7306 */
/* 0x004e280000101000 */
/*00e0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0011e8000c101904 */
/*00f0*/ LDG.E.U8 R12, [R2.64+0x1] ; /* 0x00000104020c7981 */
/* 0x000ea2000c1e1100 */
/*0100*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x0c0fe200078e0209 */
/*0110*/ I2F.U16 R13, R12 ; /* 0x0000000c000d7306 */
/* 0x004e680000101000 */
/*0120*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0021e8000c101904 */
/*0130*/ LDG.E.U8 R14, [R2.64+0x2] ; /* 0x00000204020e7981 */
/* 0x000ea2000c1e1100 */
/*0140*/ IMAD.WIDE R8, R0, R9, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fe200078e0209 */
/*0150*/ MOV R17, c[0x0][0x0] ; /* 0x0000000000117a02 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD R0, R17, c[0x0][0xc], R0 ; /* 0x0000030011007a24 */
/* 0x000fca00078e0200 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0180*/ I2F.U16 R15, R14 ; /* 0x0000000e000f7306 */
/* 0x004e640000101000 */
/*0190*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0021f4000c101904 */
/*01a0*/ @!P0 BRA 0x70 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00048fb3_00000000-6_deinterleave.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
.type _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_, @function
_Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19deinterleave_kernelPhjPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_, .-_Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
.globl _Z19deinterleave_kernelPhjPfS0_S0_
.type _Z19deinterleave_kernelPhjPfS0_S0_, @function
_Z19deinterleave_kernelPhjPfS0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z19deinterleave_kernelPhjPfS0_S0_, .-_Z19deinterleave_kernelPhjPfS0_S0_
.globl _Z12deinterleavePhjPPfS1_S1_
.type _Z12deinterleavePhjPPfS1_S1_, @function
_Z12deinterleavePhjPPfS1_S1_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, %ebp
movq %rdx, %r14
movq %rcx, %r13
movq %r8, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal (%rsi,%rsi,2), %r15d
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %ebp, %ebx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq (%r14), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 0(%r13), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq (%r12), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z48__device_stub__Z19deinterleave_kernelPhjPfS0_S0_PhjPfS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z12deinterleavePhjPPfS1_S1_, .-_Z12deinterleavePhjPPfS1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19deinterleave_kernelPhjPfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19deinterleave_kernelPhjPfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "deinterleave.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <string.h>
#include <vector>
#include <utility>
using namespace std;
const int ARRAY_SIZE = 12005;
const int ARRAY_BYTES_INT = ARRAY_SIZE * sizeof(int);
const int ARRAY_SIZE_MOTIF = 601;
const int ARRAY_BYTES_MOTIF = ARRAY_SIZE_MOTIF * ( sizeof(int) + ( 40 * sizeof(int) ) );
typedef struct {
int dis;// dis_Haming
int* motif;//str_motif[40]
}MOTIF;
//Host memory
int l, d;
int h_dataMotif[12005];
int* d_datainp;
MOTIF h_motif[602];
MOTIF* d_motif;
//device memory
//nhap tu file va chuyen sang kieu int
void File_Input()
{
l = 9; d = 2;
char temp[ARRAY_SIZE];
FILE * pFile;
pFile = fopen("datacu.txt", "r");
if (pFile == NULL)
perror("Error opening file");
else
{
if (fgets(temp, ARRAY_SIZE, pFile) != NULL)
cout << "nhap du lieu thanh cong!\n";
fclose(pFile);
}
for (int i = 0; i < strlen(temp); ++i) {
//A=0 C=1 G=2 T=3
switch (temp[i])
{
case 'A': { h_dataMotif[i] = 0; break; }
case 'C': { h_dataMotif[i] = 1; break; }
case 'G': { h_dataMotif[i] = 2; break; }
case 'T': { h_dataMotif[i] = 3; break; }
default: cout << "error chuyen sang int";
break;
}
}
}
//code dis_haming gpu
__device__ int dis_haming(const int* d_datainp, const int* s1, const int l) {
//printf("\n dis_ham %d %d", s1, l);
int ans = 0;
int temp, tempRow;
for (int i = 0; i < 20; ++i)
{
tempRow = 999;
for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
{
temp = 0;
for (int k = 0; k < l; k++) {
if (s1[k] != d_datainp[k + j]) temp++;
}
if (temp < tempRow) tempRow = temp;
}
ans += tempRow;
}
//printf("device code %d", ans);
return ans;
}
//code best nay
//__device__ int bestNeighbor(const int* d_datainp, int* s1, const int l) {
// int temp_val;
// int temp_dis;
// int best_dis = 99999;
// int motif[40];
// int ans = 0;
// printf("\nbestNeighbor\n");
// for (int i = 0; i < l; ++i) {
// //trg hop 0
// if (s1[i] != 0) {
// temp_val = s1[i];
// s1[i] = 0;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 1
// if (s1[i] != 1) {
// temp_val = s1[i];
// s1[i] = 1;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 2
// if (s1[i] != 2) {
// temp_val = s1[i];
// s1[i] = 2;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 3
// if (s1[i] != 3) {
// temp_val = s1[i];
// s1[i] = 3;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// }
// // chuan bi trc khi tra kq
// int k = 0;
// for (int i = 0; i < l; ++i) {
// ans = ans ^ (motif[i] << k);
// k += 2;
// }
// return ans;
// printf("ans %d \n", ans);
//}
//code ham chinh goi
__global__ void patternBarching(const int* d_datainp, const int l, const int d, MOTIF* d_motif) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < 600 - l) {
//khai bao bien
int motif_temp[40];
int temp_val;
int temp_dis;
int best_dis = 99999;
int motif_bN[40];
int score_motif;
//lay chuoi can duyet
for (int i = 0; i < l; ++i) {
motif_temp[i] = d_datainp[i + index];
motif_bN[i] = motif_temp[i];
}
printf("\n 1 \n");
score_motif = dis_haming(d_datainp, motif_temp, l);
//ham dis_hamming
//int ans = 0;
//int temp, tempRow;
//for (int i = 0; i < 20; ++i)
//{
// tempRow = 999;
// for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
// {
// temp = 0;
// for (int k = 0; k < l; k++) {
// if (s1[k] != d_datainp[k + j]) temp++;
// }
// if (temp < tempRow) tempRow = temp;
// }
// ans += tempRow;
//}
//printf("device code %d", ans);
//chay ham patternBarching
for (int k = 0; k < d; ++k) {
//kiem tra chuoi tot
printf("\n 2 \n");
if (best_dis < score_motif) {
score_motif = best_dis;
for (int i = 0; i < l; ++i) {
motif_temp[i] = motif_bN[i];
}
}
//ham bestNeighbor
printf("\nbestNeighbor\n");
for (int i = 0; i < l; ++i) {
printf("\n 3 \n");
//trg hop 0
if (motif_temp[i] != 0) {
temp_val = motif_temp[i];
motif_temp[i] = 0;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 1
if (motif_temp[i] != 1) {
temp_val = motif_temp[i];
motif_temp[i] = 1;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 2
if (motif_temp[i] != 2) {
temp_val = motif_temp[i];
motif_temp[i] = 2;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 3
if (motif_temp[i] != 3) {
temp_val = motif_temp[i];
motif_temp[i] = 3;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
}
// END ham bestNeighbor
}
printf("\n 4 \n");
//du lieu tra lai
printf("\n gan du lieu vao d_motif \n");
d_motif[index].dis = score_motif;
printf("\n d_ motif: dis = %d", d_motif[index].dis);
for (int i = 0; i < l; ++i) {
d_motif[index].motif[i] = motif_temp[i];
}
/*for (int k = 0; k <= d; k++)
{
i_temp = dis_hamming(a);
fo << i_temp << " " << bestScore << endl;
if (i_temp < bestScore)
{
cout << "Change ";
cout << a << " " << i_temp << " || ";
f = a;
bestScore = i_temp;
}
a = bestNeighbor(a);
}*/
}
}
int main() {
File_Input();
//cout << h_dataMotif[1];
if (cudaMalloc(&d_datainp, ARRAY_BYTES_INT) != cudaSuccess)
cout << "\n Khai bao ko thanh cong\n";
if (cudaMemcpy(d_datainp, h_dataMotif, ARRAY_BYTES_INT, cudaMemcpyHostToDevice) != cudaSuccess)
cout << "\n copy ko thanh cong\n";
if (cudaMalloc(&d_motif, ARRAY_BYTES_MOTIF) != cudaSuccess) {
cout << "\n khai bao ko thanh cong d_motif\n";
}
//chay gpu
patternBarching <<< 1, 1 >>> (d_datainp, l, d, d_motif);
//cudaMemcpy(h_datainp, d_datainp, ARRAY_BYTES, cudaMemcpyDeviceToHost);
if (cudaMemcpy(h_motif, d_motif, ARRAY_BYTES_MOTIF, cudaMemcpyDeviceToHost) != cudaSuccess)
cout << "\n ko copy dc data sang host" << endl;
//cout << h_motif[0].dis << h_motif[0].motif[1];
cudaFree(d_datainp);
cudaFree(d_motif);
return 0;
} | .file "tmpxft_0010ce05_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4168:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4168:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "datacu.txt"
.LC2:
.string "Error opening file"
.LC3:
.string "nhap du lieu thanh cong!\n"
.LC4:
.string "error chuyen sang int"
.text
.globl _Z10File_Inputv
.type _Z10File_Inputv, @function
_Z10File_Inputv:
.LFB4163:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8240
orq $0, (%rsp)
subq $3824, %rsp
.cfi_def_cfa_offset 12064
movq %fs:40, %rax
movq %rax, 12008(%rsp)
xorl %eax, %eax
movl $9, l(%rip)
movl $2, d(%rip)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L18
movq %rax, %rbx
movq %rsp, %rdi
movq %rax, %rcx
movl $12005, %edx
movl $12005, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L6
movl $25, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movq %rbx, %rdi
call fclose@PLT
.L7:
leaq h_dataMotif(%rip), %rbp
movl $0, %ebx
movq %rsp, %r12
leaq .LC4(%rip), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L5
.L18:
leaq .LC2(%rip), %rdi
call perror@PLT
jmp .L7
.L9:
cmpb $84, %al
jne .L12
movl $3, 0(%rbp)
jmp .L14
.L10:
movl $0, 0(%rbp)
.L14:
addq $1, %rbx
addq $4, %rbp
.L5:
movq %r12, %rdi
call strlen@PLT
cmpq %rax, %rbx
jnb .L19
movzbl (%rbx,%r12), %eax
cmpb $71, %al
je .L8
jg .L9
cmpb $65, %al
je .L10
cmpb $67, %al
jne .L12
movl $1, 0(%rbp)
jmp .L14
.L8:
movl $2, 0(%rbp)
jmp .L14
.L12:
movl $21, %edx
movq %r14, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L14
.L19:
movq 12008(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $12016, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.size _Z10File_Inputv, .-_Z10File_Inputv
.globl _Z10dis_hamingPKiS0_i
.type _Z10dis_hamingPKiS0_i, @function
_Z10dis_hamingPKiS0_i:
.LFB4164:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4164:
.size _Z10dis_hamingPKiS0_i, .-_Z10dis_hamingPKiS0_i
.globl _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
.type _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF, @function
_Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF:
.LFB4190:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15patternBarchingPKiiiP5MOTIF(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4190:
.size _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF, .-_Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
.globl _Z15patternBarchingPKiiiP5MOTIF
.type _Z15patternBarchingPKiiiP5MOTIF, @function
_Z15patternBarchingPKiiiP5MOTIF:
.LFB4191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4191:
.size _Z15patternBarchingPKiiiP5MOTIF, .-_Z15patternBarchingPKiiiP5MOTIF
.section .rodata.str1.1
.LC5:
.string "\n Khai bao ko thanh cong\n"
.LC6:
.string "\n copy ko thanh cong\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\n khai bao ko thanh cong d_motif\n"
.section .rodata.str1.1
.LC8:
.string "\n ko copy dc data sang host"
.text
.globl main
.type main, @function
main:
.LFB4165:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
call _Z10File_Inputv
movl $48020, %esi
leaq d_datainp(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L38
.L32:
movl $1, %ecx
movl $48020, %edx
leaq h_dataMotif(%rip), %rsi
movq d_datainp(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
.L33:
movl $98564, %esi
leaq d_motif(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
.L34:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L35:
movl $2, %ecx
movl $98564, %edx
movq d_motif(%rip), %rsi
leaq h_motif(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
.L36:
movq d_datainp(%rip), %rdi
call cudaFree@PLT
movq d_motif(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L32
.L39:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L33
.L40:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L34
.L41:
movq d_motif(%rip), %rcx
movl d(%rip), %edx
movl l(%rip), %esi
movq d_datainp(%rip), %rdi
call _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
jmp .L35
.L42:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L36
.cfi_endproc
.LFE4165:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z15patternBarchingPKiiiP5MOTIF"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4193:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15patternBarchingPKiiiP5MOTIF(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_motif
.bss
.align 8
.type d_motif, @object
.size d_motif, 8
d_motif:
.zero 8
.globl h_motif
.align 32
.type h_motif, @object
.size h_motif, 9632
h_motif:
.zero 9632
.globl d_datainp
.align 8
.type d_datainp, @object
.size d_datainp, 8
d_datainp:
.zero 8
.globl h_dataMotif
.align 32
.type h_dataMotif, @object
.size h_dataMotif, 48020
h_dataMotif:
.zero 48020
.globl d
.align 4
.type d, @object
.size d, 4
d:
.zero 4
.globl l
.align 4
.type l, @object
.size l, 4
l:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <string.h>
#include <vector>
#include <utility>
using namespace std;
const int ARRAY_SIZE = 12005;
const int ARRAY_BYTES_INT = ARRAY_SIZE * sizeof(int);
const int ARRAY_SIZE_MOTIF = 601;
const int ARRAY_BYTES_MOTIF = ARRAY_SIZE_MOTIF * ( sizeof(int) + ( 40 * sizeof(int) ) );
typedef struct {
int dis;// dis_Haming
int* motif;//str_motif[40]
}MOTIF;
//Host memory
int l, d;
int h_dataMotif[12005];
int* d_datainp;
MOTIF h_motif[602];
MOTIF* d_motif;
//device memory
//nhap tu file va chuyen sang kieu int
void File_Input()
{
l = 9; d = 2;
char temp[ARRAY_SIZE];
FILE * pFile;
pFile = fopen("datacu.txt", "r");
if (pFile == NULL)
perror("Error opening file");
else
{
if (fgets(temp, ARRAY_SIZE, pFile) != NULL)
cout << "nhap du lieu thanh cong!\n";
fclose(pFile);
}
for (int i = 0; i < strlen(temp); ++i) {
//A=0 C=1 G=2 T=3
switch (temp[i])
{
case 'A': { h_dataMotif[i] = 0; break; }
case 'C': { h_dataMotif[i] = 1; break; }
case 'G': { h_dataMotif[i] = 2; break; }
case 'T': { h_dataMotif[i] = 3; break; }
default: cout << "error chuyen sang int";
break;
}
}
}
//code dis_haming gpu
__device__ int dis_haming(const int* d_datainp, const int* s1, const int l) {
//printf("\n dis_ham %d %d", s1, l);
int ans = 0;
int temp, tempRow;
for (int i = 0; i < 20; ++i)
{
tempRow = 999;
for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
{
temp = 0;
for (int k = 0; k < l; k++) {
if (s1[k] != d_datainp[k + j]) temp++;
}
if (temp < tempRow) tempRow = temp;
}
ans += tempRow;
}
//printf("device code %d", ans);
return ans;
}
//code best nay
//__device__ int bestNeighbor(const int* d_datainp, int* s1, const int l) {
// int temp_val;
// int temp_dis;
// int best_dis = 99999;
// int motif[40];
// int ans = 0;
// printf("\nbestNeighbor\n");
// for (int i = 0; i < l; ++i) {
// //trg hop 0
// if (s1[i] != 0) {
// temp_val = s1[i];
// s1[i] = 0;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 1
// if (s1[i] != 1) {
// temp_val = s1[i];
// s1[i] = 1;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 2
// if (s1[i] != 2) {
// temp_val = s1[i];
// s1[i] = 2;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 3
// if (s1[i] != 3) {
// temp_val = s1[i];
// s1[i] = 3;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// }
// // chuan bi trc khi tra kq
// int k = 0;
// for (int i = 0; i < l; ++i) {
// ans = ans ^ (motif[i] << k);
// k += 2;
// }
// return ans;
// printf("ans %d \n", ans);
//}
//code ham chinh goi
__global__ void patternBarching(const int* d_datainp, const int l, const int d, MOTIF* d_motif) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < 600 - l) {
//khai bao bien
int motif_temp[40];
int temp_val;
int temp_dis;
int best_dis = 99999;
int motif_bN[40];
int score_motif;
//lay chuoi can duyet
for (int i = 0; i < l; ++i) {
motif_temp[i] = d_datainp[i + index];
motif_bN[i] = motif_temp[i];
}
printf("\n 1 \n");
score_motif = dis_haming(d_datainp, motif_temp, l);
//ham dis_hamming
//int ans = 0;
//int temp, tempRow;
//for (int i = 0; i < 20; ++i)
//{
// tempRow = 999;
// for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
// {
// temp = 0;
// for (int k = 0; k < l; k++) {
// if (s1[k] != d_datainp[k + j]) temp++;
// }
// if (temp < tempRow) tempRow = temp;
// }
// ans += tempRow;
//}
//printf("device code %d", ans);
//chay ham patternBarching
for (int k = 0; k < d; ++k) {
//kiem tra chuoi tot
printf("\n 2 \n");
if (best_dis < score_motif) {
score_motif = best_dis;
for (int i = 0; i < l; ++i) {
motif_temp[i] = motif_bN[i];
}
}
//ham bestNeighbor
printf("\nbestNeighbor\n");
for (int i = 0; i < l; ++i) {
printf("\n 3 \n");
//trg hop 0
if (motif_temp[i] != 0) {
temp_val = motif_temp[i];
motif_temp[i] = 0;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 1
if (motif_temp[i] != 1) {
temp_val = motif_temp[i];
motif_temp[i] = 1;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 2
if (motif_temp[i] != 2) {
temp_val = motif_temp[i];
motif_temp[i] = 2;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 3
if (motif_temp[i] != 3) {
temp_val = motif_temp[i];
motif_temp[i] = 3;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
}
// END ham bestNeighbor
}
printf("\n 4 \n");
//du lieu tra lai
printf("\n gan du lieu vao d_motif \n");
d_motif[index].dis = score_motif;
printf("\n d_ motif: dis = %d", d_motif[index].dis);
for (int i = 0; i < l; ++i) {
d_motif[index].motif[i] = motif_temp[i];
}
/*for (int k = 0; k <= d; k++)
{
i_temp = dis_hamming(a);
fo << i_temp << " " << bestScore << endl;
if (i_temp < bestScore)
{
cout << "Change ";
cout << a << " " << i_temp << " || ";
f = a;
bestScore = i_temp;
}
a = bestNeighbor(a);
}*/
}
}
int main() {
File_Input();
//cout << h_dataMotif[1];
if (cudaMalloc(&d_datainp, ARRAY_BYTES_INT) != cudaSuccess)
cout << "\n Khai bao ko thanh cong\n";
if (cudaMemcpy(d_datainp, h_dataMotif, ARRAY_BYTES_INT, cudaMemcpyHostToDevice) != cudaSuccess)
cout << "\n copy ko thanh cong\n";
if (cudaMalloc(&d_motif, ARRAY_BYTES_MOTIF) != cudaSuccess) {
cout << "\n khai bao ko thanh cong d_motif\n";
}
//chay gpu
patternBarching <<< 1, 1 >>> (d_datainp, l, d, d_motif);
//cudaMemcpy(h_datainp, d_datainp, ARRAY_BYTES, cudaMemcpyDeviceToHost);
if (cudaMemcpy(h_motif, d_motif, ARRAY_BYTES_MOTIF, cudaMemcpyDeviceToHost) != cudaSuccess)
cout << "\n ko copy dc data sang host" << endl;
//cout << h_motif[0].dis << h_motif[0].motif[1];
cudaFree(d_datainp);
cudaFree(d_motif);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <string.h>
#include <vector>
#include <utility>
using namespace std;
const int ARRAY_SIZE = 12005;
const int ARRAY_BYTES_INT = ARRAY_SIZE * sizeof(int);
const int ARRAY_SIZE_MOTIF = 601;
const int ARRAY_BYTES_MOTIF = ARRAY_SIZE_MOTIF * ( sizeof(int) + ( 40 * sizeof(int) ) );
typedef struct {
int dis;// dis_Haming
int* motif;//str_motif[40]
}MOTIF;
//Host memory
int l, d;
int h_dataMotif[12005];
int* d_datainp;
MOTIF h_motif[602];
MOTIF* d_motif;
//device memory
//nhap tu file va chuyen sang kieu int
void File_Input()
{
l = 9; d = 2;
char temp[ARRAY_SIZE];
FILE * pFile;
pFile = fopen("datacu.txt", "r");
if (pFile == NULL)
perror("Error opening file");
else
{
if (fgets(temp, ARRAY_SIZE, pFile) != NULL)
cout << "nhap du lieu thanh cong!\n";
fclose(pFile);
}
for (int i = 0; i < strlen(temp); ++i) {
//A=0 C=1 G=2 T=3
switch (temp[i])
{
case 'A': { h_dataMotif[i] = 0; break; }
case 'C': { h_dataMotif[i] = 1; break; }
case 'G': { h_dataMotif[i] = 2; break; }
case 'T': { h_dataMotif[i] = 3; break; }
default: cout << "error chuyen sang int";
break;
}
}
}
//code dis_haming gpu
__device__ int dis_haming(const int* d_datainp, const int* s1, const int l) {
//printf("\n dis_ham %d %d", s1, l);
int ans = 0;
int temp, tempRow;
for (int i = 0; i < 20; ++i)
{
tempRow = 999;
for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
{
temp = 0;
for (int k = 0; k < l; k++) {
if (s1[k] != d_datainp[k + j]) temp++;
}
if (temp < tempRow) tempRow = temp;
}
ans += tempRow;
}
//printf("device code %d", ans);
return ans;
}
//code best nay
//__device__ int bestNeighbor(const int* d_datainp, int* s1, const int l) {
// int temp_val;
// int temp_dis;
// int best_dis = 99999;
// int motif[40];
// int ans = 0;
// printf("\nbestNeighbor\n");
// for (int i = 0; i < l; ++i) {
// //trg hop 0
// if (s1[i] != 0) {
// temp_val = s1[i];
// s1[i] = 0;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 1
// if (s1[i] != 1) {
// temp_val = s1[i];
// s1[i] = 1;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 2
// if (s1[i] != 2) {
// temp_val = s1[i];
// s1[i] = 2;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 3
// if (s1[i] != 3) {
// temp_val = s1[i];
// s1[i] = 3;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// }
// // chuan bi trc khi tra kq
// int k = 0;
// for (int i = 0; i < l; ++i) {
// ans = ans ^ (motif[i] << k);
// k += 2;
// }
// return ans;
// printf("ans %d \n", ans);
//}
//code ham chinh goi
__global__ void patternBarching(const int* d_datainp, const int l, const int d, MOTIF* d_motif) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < 600 - l) {
//khai bao bien
int motif_temp[40];
int temp_val;
int temp_dis;
int best_dis = 99999;
int motif_bN[40];
int score_motif;
//lay chuoi can duyet
for (int i = 0; i < l; ++i) {
motif_temp[i] = d_datainp[i + index];
motif_bN[i] = motif_temp[i];
}
printf("\n 1 \n");
score_motif = dis_haming(d_datainp, motif_temp, l);
//ham dis_hamming
//int ans = 0;
//int temp, tempRow;
//for (int i = 0; i < 20; ++i)
//{
// tempRow = 999;
// for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
// {
// temp = 0;
// for (int k = 0; k < l; k++) {
// if (s1[k] != d_datainp[k + j]) temp++;
// }
// if (temp < tempRow) tempRow = temp;
// }
// ans += tempRow;
//}
//printf("device code %d", ans);
//chay ham patternBarching
for (int k = 0; k < d; ++k) {
//kiem tra chuoi tot
printf("\n 2 \n");
if (best_dis < score_motif) {
score_motif = best_dis;
for (int i = 0; i < l; ++i) {
motif_temp[i] = motif_bN[i];
}
}
//ham bestNeighbor
printf("\nbestNeighbor\n");
for (int i = 0; i < l; ++i) {
printf("\n 3 \n");
//trg hop 0
if (motif_temp[i] != 0) {
temp_val = motif_temp[i];
motif_temp[i] = 0;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 1
if (motif_temp[i] != 1) {
temp_val = motif_temp[i];
motif_temp[i] = 1;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 2
if (motif_temp[i] != 2) {
temp_val = motif_temp[i];
motif_temp[i] = 2;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 3
if (motif_temp[i] != 3) {
temp_val = motif_temp[i];
motif_temp[i] = 3;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
}
// END ham bestNeighbor
}
printf("\n 4 \n");
//du lieu tra lai
printf("\n gan du lieu vao d_motif \n");
d_motif[index].dis = score_motif;
printf("\n d_ motif: dis = %d", d_motif[index].dis);
for (int i = 0; i < l; ++i) {
d_motif[index].motif[i] = motif_temp[i];
}
/*for (int k = 0; k <= d; k++)
{
i_temp = dis_hamming(a);
fo << i_temp << " " << bestScore << endl;
if (i_temp < bestScore)
{
cout << "Change ";
cout << a << " " << i_temp << " || ";
f = a;
bestScore = i_temp;
}
a = bestNeighbor(a);
}*/
}
}
int main() {
File_Input();
//cout << h_dataMotif[1];
if (hipMalloc(&d_datainp, ARRAY_BYTES_INT) != hipSuccess)
cout << "\n Khai bao ko thanh cong\n";
if (hipMemcpy(d_datainp, h_dataMotif, ARRAY_BYTES_INT, hipMemcpyHostToDevice) != hipSuccess)
cout << "\n copy ko thanh cong\n";
if (hipMalloc(&d_motif, ARRAY_BYTES_MOTIF) != hipSuccess) {
cout << "\n khai bao ko thanh cong d_motif\n";
}
//chay gpu
patternBarching <<< 1, 1 >>> (d_datainp, l, d, d_motif);
//cudaMemcpy(h_datainp, d_datainp, ARRAY_BYTES, cudaMemcpyDeviceToHost);
if (hipMemcpy(h_motif, d_motif, ARRAY_BYTES_MOTIF, hipMemcpyDeviceToHost) != hipSuccess)
cout << "\n ko copy dc data sang host" << endl;
//cout << h_motif[0].dis << h_motif[0].motif[1];
hipFree(d_datainp);
hipFree(d_motif);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <string.h>
#include <vector>
#include <utility>
using namespace std;
const int ARRAY_SIZE = 12005;
const int ARRAY_BYTES_INT = ARRAY_SIZE * sizeof(int);
const int ARRAY_SIZE_MOTIF = 601;
const int ARRAY_BYTES_MOTIF = ARRAY_SIZE_MOTIF * ( sizeof(int) + ( 40 * sizeof(int) ) );
typedef struct {
int dis;// dis_Haming
int* motif;//str_motif[40]
}MOTIF;
//Host memory
int l, d;
int h_dataMotif[12005];
int* d_datainp;
MOTIF h_motif[602];
MOTIF* d_motif;
//device memory
//nhap tu file va chuyen sang kieu int
void File_Input()
{
l = 9; d = 2;
char temp[ARRAY_SIZE];
FILE * pFile;
pFile = fopen("datacu.txt", "r");
if (pFile == NULL)
perror("Error opening file");
else
{
if (fgets(temp, ARRAY_SIZE, pFile) != NULL)
cout << "nhap du lieu thanh cong!\n";
fclose(pFile);
}
for (int i = 0; i < strlen(temp); ++i) {
//A=0 C=1 G=2 T=3
switch (temp[i])
{
case 'A': { h_dataMotif[i] = 0; break; }
case 'C': { h_dataMotif[i] = 1; break; }
case 'G': { h_dataMotif[i] = 2; break; }
case 'T': { h_dataMotif[i] = 3; break; }
default: cout << "error chuyen sang int";
break;
}
}
}
//code dis_haming gpu
__device__ int dis_haming(const int* d_datainp, const int* s1, const int l) {
//printf("\n dis_ham %d %d", s1, l);
int ans = 0;
int temp, tempRow;
for (int i = 0; i < 20; ++i)
{
tempRow = 999;
for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
{
temp = 0;
for (int k = 0; k < l; k++) {
if (s1[k] != d_datainp[k + j]) temp++;
}
if (temp < tempRow) tempRow = temp;
}
ans += tempRow;
}
//printf("device code %d", ans);
return ans;
}
//code best nay
//__device__ int bestNeighbor(const int* d_datainp, int* s1, const int l) {
// int temp_val;
// int temp_dis;
// int best_dis = 99999;
// int motif[40];
// int ans = 0;
// printf("\nbestNeighbor\n");
// for (int i = 0; i < l; ++i) {
// //trg hop 0
// if (s1[i] != 0) {
// temp_val = s1[i];
// s1[i] = 0;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 1
// if (s1[i] != 1) {
// temp_val = s1[i];
// s1[i] = 1;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 2
// if (s1[i] != 2) {
// temp_val = s1[i];
// s1[i] = 2;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// //trg hop 3
// if (s1[i] != 3) {
// temp_val = s1[i];
// s1[i] = 3;
// temp_dis = dis_haming(d_datainp, s1, l);
// s1[i] = temp_val;
// //lay best neighbor
// if (temp_dis < best_dis)
// {
// best_dis = temp_dis;
// for (int j = 0; j < l; ++j) {
// motif[j] = s1[j];
// }
// }
// }
// }
// // chuan bi trc khi tra kq
// int k = 0;
// for (int i = 0; i < l; ++i) {
// ans = ans ^ (motif[i] << k);
// k += 2;
// }
// return ans;
// printf("ans %d \n", ans);
//}
//code ham chinh goi
__global__ void patternBarching(const int* d_datainp, const int l, const int d, MOTIF* d_motif) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < 600 - l) {
//khai bao bien
int motif_temp[40];
int temp_val;
int temp_dis;
int best_dis = 99999;
int motif_bN[40];
int score_motif;
//lay chuoi can duyet
for (int i = 0; i < l; ++i) {
motif_temp[i] = d_datainp[i + index];
motif_bN[i] = motif_temp[i];
}
printf("\n 1 \n");
score_motif = dis_haming(d_datainp, motif_temp, l);
//ham dis_hamming
//int ans = 0;
//int temp, tempRow;
//for (int i = 0; i < 20; ++i)
//{
// tempRow = 999;
// for (int j = i * 600; j < (i + 1) * 600 - l; ++j)
// {
// temp = 0;
// for (int k = 0; k < l; k++) {
// if (s1[k] != d_datainp[k + j]) temp++;
// }
// if (temp < tempRow) tempRow = temp;
// }
// ans += tempRow;
//}
//printf("device code %d", ans);
//chay ham patternBarching
for (int k = 0; k < d; ++k) {
//kiem tra chuoi tot
printf("\n 2 \n");
if (best_dis < score_motif) {
score_motif = best_dis;
for (int i = 0; i < l; ++i) {
motif_temp[i] = motif_bN[i];
}
}
//ham bestNeighbor
printf("\nbestNeighbor\n");
for (int i = 0; i < l; ++i) {
printf("\n 3 \n");
//trg hop 0
if (motif_temp[i] != 0) {
temp_val = motif_temp[i];
motif_temp[i] = 0;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 1
if (motif_temp[i] != 1) {
temp_val = motif_temp[i];
motif_temp[i] = 1;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 2
if (motif_temp[i] != 2) {
temp_val = motif_temp[i];
motif_temp[i] = 2;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
//trg hop 3
if (motif_temp[i] != 3) {
temp_val = motif_temp[i];
motif_temp[i] = 3;
temp_dis = dis_haming(d_datainp, motif_temp, l);
//lay best neighbor
if (temp_dis < best_dis)
{
best_dis = temp_dis;
for (int j = 0; j < l; ++j) {
motif_bN[j] = motif_temp[j];
}
}
motif_temp[i] = temp_val;
}
}
// END ham bestNeighbor
}
printf("\n 4 \n");
//du lieu tra lai
printf("\n gan du lieu vao d_motif \n");
d_motif[index].dis = score_motif;
printf("\n d_ motif: dis = %d", d_motif[index].dis);
for (int i = 0; i < l; ++i) {
d_motif[index].motif[i] = motif_temp[i];
}
/*for (int k = 0; k <= d; k++)
{
i_temp = dis_hamming(a);
fo << i_temp << " " << bestScore << endl;
if (i_temp < bestScore)
{
cout << "Change ";
cout << a << " " << i_temp << " || ";
f = a;
bestScore = i_temp;
}
a = bestNeighbor(a);
}*/
}
}
int main() {
File_Input();
//cout << h_dataMotif[1];
if (hipMalloc(&d_datainp, ARRAY_BYTES_INT) != hipSuccess)
cout << "\n Khai bao ko thanh cong\n";
if (hipMemcpy(d_datainp, h_dataMotif, ARRAY_BYTES_INT, hipMemcpyHostToDevice) != hipSuccess)
cout << "\n copy ko thanh cong\n";
if (hipMalloc(&d_motif, ARRAY_BYTES_MOTIF) != hipSuccess) {
cout << "\n khai bao ko thanh cong d_motif\n";
}
//chay gpu
patternBarching <<< 1, 1 >>> (d_datainp, l, d, d_motif);
//cudaMemcpy(h_datainp, d_datainp, ARRAY_BYTES, cudaMemcpyDeviceToHost);
if (hipMemcpy(h_motif, d_motif, ARRAY_BYTES_MOTIF, hipMemcpyDeviceToHost) != hipSuccess)
cout << "\n ko copy dc data sang host" << endl;
//cout << h_motif[0].dis << h_motif[0].motif[1];
hipFree(d_datainp);
hipFree(d_motif);
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10File_Inputv # -- Begin function _Z10File_Inputv
.p2align 4, 0x90
.type _Z10File_Inputv,@function
_Z10File_Inputv: # @_Z10File_Inputv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $12008, %rsp # imm = 0x2EE8
.cfi_def_cfa_offset 12032
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $9, l(%rip)
movl $2, d(%rip)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %rbx
movq %rsp, %rdi
movl $12005, %esi # imm = 0x2EE5
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB0_4
# %bb.3:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_4:
movq %rbx, %rdi
callq fclose
cmpb $0, (%rsp)
je .LBB0_15
.LBB0_6: # %.lr.ph.preheader
xorl %r14d, %r14d
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_11: # in Loop: Header=BB0_7 Depth=1
movl $2, h_dataMotif(,%r14,4)
.LBB0_14: # in Loop: Header=BB0_7 Depth=1
incq %r14
movq %rbx, %rdi
callq strlen
cmpq %r14, %rax
jbe .LBB0_15
.LBB0_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rsp,%r14), %eax
addl $-65, %eax
cmpl $19, %eax
ja .LBB0_13
# %bb.8: # %.lr.ph
# in Loop: Header=BB0_7 Depth=1
jmpq *.LJTI0_0(,%rax,8)
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl $0, h_dataMotif(,%r14,4)
jmp .LBB0_14
.LBB0_10: # in Loop: Header=BB0_7 Depth=1
movl $1, h_dataMotif(,%r14,4)
jmp .LBB0_14
.LBB0_12: # in Loop: Header=BB0_7 Depth=1
movl $3, h_dataMotif(,%r14,4)
jmp .LBB0_14
.LBB0_13: # in Loop: Header=BB0_7 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_14
.LBB0_1:
movl $.L.str.2, %edi
callq perror
cmpb $0, (%rsp)
jne .LBB0_6
.LBB0_15: # %._crit_edge
addq $12008, %rsp # imm = 0x2EE8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10File_Inputv, .Lfunc_end0-_Z10File_Inputv
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_9
.quad .LBB0_13
.quad .LBB0_10
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_11
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_12
# -- End function
.text
.globl _Z30__device_stub__patternBarchingPKiiiP5MOTIF # -- Begin function _Z30__device_stub__patternBarchingPKiiiP5MOTIF
.p2align 4, 0x90
.type _Z30__device_stub__patternBarchingPKiiiP5MOTIF,@function
_Z30__device_stub__patternBarchingPKiiiP5MOTIF: # @_Z30__device_stub__patternBarchingPKiiiP5MOTIF
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15patternBarchingPKiiiP5MOTIF, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__patternBarchingPKiiiP5MOTIF, .Lfunc_end1-_Z30__device_stub__patternBarchingPKiiiP5MOTIF
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
callq _Z10File_Inputv
movl $d_datainp, %edi
movl $48020, %esi # imm = 0xBB94
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_2:
movq d_datainp(%rip), %rdi
movl $h_dataMotif, %esi
movl $48020, %edx # imm = 0xBB94
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_4:
movl $d_motif, %edi
movl $98564, %esi # imm = 0x18104
callq hipMalloc
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_6:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq d_datainp(%rip), %rax
movl l(%rip), %ecx
movl d(%rip), %edx
movq d_motif(%rip), %rsi
movq %rax, 72(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 8(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15patternBarchingPKiiiP5MOTIF, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq d_motif(%rip), %rsi
movl $h_motif, %edi
movl $98564, %edx # imm = 0x18104
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_14
# %bb.9:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_12
# %bb.11:
movzbl 67(%rbx), %eax
jmp .LBB2_13
.LBB2_12:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB2_14:
movq d_datainp(%rip), %rdi
callq hipFree
movq d_motif(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15patternBarchingPKiiiP5MOTIF, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type l,@object # @l
.bss
.globl l
.p2align 2, 0x0
l:
.long 0 # 0x0
.size l, 4
.type d,@object # @d
.globl d
.p2align 2, 0x0
d:
.long 0 # 0x0
.size d, 4
.type h_dataMotif,@object # @h_dataMotif
.globl h_dataMotif
.p2align 4, 0x0
h_dataMotif:
.zero 48020
.size h_dataMotif, 48020
.type d_datainp,@object # @d_datainp
.globl d_datainp
.p2align 3, 0x0
d_datainp:
.quad 0
.size d_datainp, 8
.type h_motif,@object # @h_motif
.globl h_motif
.p2align 4, 0x0
h_motif:
.zero 9632
.size h_motif, 9632
.type d_motif,@object # @d_motif
.globl d_motif
.p2align 3, 0x0
d_motif:
.quad 0
.size d_motif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "datacu.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error opening file"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "nhap du lieu thanh cong!\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error chuyen sang int"
.size .L.str.4, 22
.type _Z15patternBarchingPKiiiP5MOTIF,@object # @_Z15patternBarchingPKiiiP5MOTIF
.section .rodata,"a",@progbits
.globl _Z15patternBarchingPKiiiP5MOTIF
.p2align 3, 0x0
_Z15patternBarchingPKiiiP5MOTIF:
.quad _Z30__device_stub__patternBarchingPKiiiP5MOTIF
.size _Z15patternBarchingPKiiiP5MOTIF, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "\n Khai bao ko thanh cong\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n copy ko thanh cong\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n khai bao ko thanh cong d_motif\n"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n ko copy dc data sang host"
.size .L.str.8, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15patternBarchingPKiiiP5MOTIF"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__patternBarchingPKiiiP5MOTIF
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym h_dataMotif
.addrsig_sym d_datainp
.addrsig_sym h_motif
.addrsig_sym d_motif
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15patternBarchingPKiiiP5MOTIF
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010ce05_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4168:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4168:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "datacu.txt"
.LC2:
.string "Error opening file"
.LC3:
.string "nhap du lieu thanh cong!\n"
.LC4:
.string "error chuyen sang int"
.text
.globl _Z10File_Inputv
.type _Z10File_Inputv, @function
_Z10File_Inputv:
.LFB4163:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8240
orq $0, (%rsp)
subq $3824, %rsp
.cfi_def_cfa_offset 12064
movq %fs:40, %rax
movq %rax, 12008(%rsp)
xorl %eax, %eax
movl $9, l(%rip)
movl $2, d(%rip)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L18
movq %rax, %rbx
movq %rsp, %rdi
movq %rax, %rcx
movl $12005, %edx
movl $12005, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L6
movl $25, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L6:
movq %rbx, %rdi
call fclose@PLT
.L7:
leaq h_dataMotif(%rip), %rbp
movl $0, %ebx
movq %rsp, %r12
leaq .LC4(%rip), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L5
.L18:
leaq .LC2(%rip), %rdi
call perror@PLT
jmp .L7
.L9:
cmpb $84, %al
jne .L12
movl $3, 0(%rbp)
jmp .L14
.L10:
movl $0, 0(%rbp)
.L14:
addq $1, %rbx
addq $4, %rbp
.L5:
movq %r12, %rdi
call strlen@PLT
cmpq %rax, %rbx
jnb .L19
movzbl (%rbx,%r12), %eax
cmpb $71, %al
je .L8
jg .L9
cmpb $65, %al
je .L10
cmpb $67, %al
jne .L12
movl $1, 0(%rbp)
jmp .L14
.L8:
movl $2, 0(%rbp)
jmp .L14
.L12:
movl $21, %edx
movq %r14, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L14
.L19:
movq 12008(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $12016, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.size _Z10File_Inputv, .-_Z10File_Inputv
.globl _Z10dis_hamingPKiS0_i
.type _Z10dis_hamingPKiS0_i, @function
_Z10dis_hamingPKiS0_i:
.LFB4164:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4164:
.size _Z10dis_hamingPKiS0_i, .-_Z10dis_hamingPKiS0_i
.globl _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
.type _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF, @function
_Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF:
.LFB4190:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15patternBarchingPKiiiP5MOTIF(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4190:
.size _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF, .-_Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
.globl _Z15patternBarchingPKiiiP5MOTIF
.type _Z15patternBarchingPKiiiP5MOTIF, @function
_Z15patternBarchingPKiiiP5MOTIF:
.LFB4191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4191:
.size _Z15patternBarchingPKiiiP5MOTIF, .-_Z15patternBarchingPKiiiP5MOTIF
.section .rodata.str1.1
.LC5:
.string "\n Khai bao ko thanh cong\n"
.LC6:
.string "\n copy ko thanh cong\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\n khai bao ko thanh cong d_motif\n"
.section .rodata.str1.1
.LC8:
.string "\n ko copy dc data sang host"
.text
.globl main
.type main, @function
main:
.LFB4165:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
call _Z10File_Inputv
movl $48020, %esi
leaq d_datainp(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L38
.L32:
movl $1, %ecx
movl $48020, %edx
leaq h_dataMotif(%rip), %rsi
movq d_datainp(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
.L33:
movl $98564, %esi
leaq d_motif(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
.L34:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L35:
movl $2, %ecx
movl $98564, %edx
movq d_motif(%rip), %rsi
leaq h_motif(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
.L36:
movq d_datainp(%rip), %rdi
call cudaFree@PLT
movq d_motif(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L32
.L39:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L33
.L40:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L34
.L41:
movq d_motif(%rip), %rcx
movl d(%rip), %edx
movl l(%rip), %esi
movq d_datainp(%rip), %rdi
call _Z45__device_stub__Z15patternBarchingPKiiiP5MOTIFPKiiiP5MOTIF
jmp .L35
.L42:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L36
.cfi_endproc
.LFE4165:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z15patternBarchingPKiiiP5MOTIF"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4193:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15patternBarchingPKiiiP5MOTIF(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_motif
.bss
.align 8
.type d_motif, @object
.size d_motif, 8
d_motif:
.zero 8
.globl h_motif
.align 32
.type h_motif, @object
.size h_motif, 9632
h_motif:
.zero 9632
.globl d_datainp
.align 8
.type d_datainp, @object
.size d_datainp, 8
d_datainp:
.zero 8
.globl h_dataMotif
.align 32
.type h_dataMotif, @object
.size h_dataMotif, 48020
h_dataMotif:
.zero 48020
.globl d
.align 4
.type d, @object
.size d, 4
d:
.zero 4
.globl l
.align 4
.type l, @object
.size l, 4
l:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10File_Inputv # -- Begin function _Z10File_Inputv
.p2align 4, 0x90
.type _Z10File_Inputv,@function
_Z10File_Inputv: # @_Z10File_Inputv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $12008, %rsp # imm = 0x2EE8
.cfi_def_cfa_offset 12032
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $9, l(%rip)
movl $2, d(%rip)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %rbx
movq %rsp, %rdi
movl $12005, %esi # imm = 0x2EE5
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB0_4
# %bb.3:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_4:
movq %rbx, %rdi
callq fclose
cmpb $0, (%rsp)
je .LBB0_15
.LBB0_6: # %.lr.ph.preheader
xorl %r14d, %r14d
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_11: # in Loop: Header=BB0_7 Depth=1
movl $2, h_dataMotif(,%r14,4)
.LBB0_14: # in Loop: Header=BB0_7 Depth=1
incq %r14
movq %rbx, %rdi
callq strlen
cmpq %r14, %rax
jbe .LBB0_15
.LBB0_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rsp,%r14), %eax
addl $-65, %eax
cmpl $19, %eax
ja .LBB0_13
# %bb.8: # %.lr.ph
# in Loop: Header=BB0_7 Depth=1
jmpq *.LJTI0_0(,%rax,8)
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl $0, h_dataMotif(,%r14,4)
jmp .LBB0_14
.LBB0_10: # in Loop: Header=BB0_7 Depth=1
movl $1, h_dataMotif(,%r14,4)
jmp .LBB0_14
.LBB0_12: # in Loop: Header=BB0_7 Depth=1
movl $3, h_dataMotif(,%r14,4)
jmp .LBB0_14
.LBB0_13: # in Loop: Header=BB0_7 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_14
.LBB0_1:
movl $.L.str.2, %edi
callq perror
cmpb $0, (%rsp)
jne .LBB0_6
.LBB0_15: # %._crit_edge
addq $12008, %rsp # imm = 0x2EE8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10File_Inputv, .Lfunc_end0-_Z10File_Inputv
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_9
.quad .LBB0_13
.quad .LBB0_10
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_11
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_13
.quad .LBB0_12
# -- End function
.text
.globl _Z30__device_stub__patternBarchingPKiiiP5MOTIF # -- Begin function _Z30__device_stub__patternBarchingPKiiiP5MOTIF
.p2align 4, 0x90
.type _Z30__device_stub__patternBarchingPKiiiP5MOTIF,@function
_Z30__device_stub__patternBarchingPKiiiP5MOTIF: # @_Z30__device_stub__patternBarchingPKiiiP5MOTIF
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15patternBarchingPKiiiP5MOTIF, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__patternBarchingPKiiiP5MOTIF, .Lfunc_end1-_Z30__device_stub__patternBarchingPKiiiP5MOTIF
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
callq _Z10File_Inputv
movl $d_datainp, %edi
movl $48020, %esi # imm = 0xBB94
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_2:
movq d_datainp(%rip), %rdi
movl $h_dataMotif, %esi
movl $48020, %edx # imm = 0xBB94
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_4:
movl $d_motif, %edi
movl $98564, %esi # imm = 0x18104
callq hipMalloc
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB2_6:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq d_datainp(%rip), %rax
movl l(%rip), %ecx
movl d(%rip), %edx
movq d_motif(%rip), %rsi
movq %rax, 72(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 8(%rsp)
movq %rsi, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15patternBarchingPKiiiP5MOTIF, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq d_motif(%rip), %rsi
movl $h_motif, %edi
movl $98564, %edx # imm = 0x18104
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_14
# %bb.9:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_12
# %bb.11:
movzbl 67(%rbx), %eax
jmp .LBB2_13
.LBB2_12:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB2_14:
movq d_datainp(%rip), %rdi
callq hipFree
movq d_motif(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15patternBarchingPKiiiP5MOTIF, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type l,@object # @l
.bss
.globl l
.p2align 2, 0x0
l:
.long 0 # 0x0
.size l, 4
.type d,@object # @d
.globl d
.p2align 2, 0x0
d:
.long 0 # 0x0
.size d, 4
.type h_dataMotif,@object # @h_dataMotif
.globl h_dataMotif
.p2align 4, 0x0
h_dataMotif:
.zero 48020
.size h_dataMotif, 48020
.type d_datainp,@object # @d_datainp
.globl d_datainp
.p2align 3, 0x0
d_datainp:
.quad 0
.size d_datainp, 8
.type h_motif,@object # @h_motif
.globl h_motif
.p2align 4, 0x0
h_motif:
.zero 9632
.size h_motif, 9632
.type d_motif,@object # @d_motif
.globl d_motif
.p2align 3, 0x0
d_motif:
.quad 0
.size d_motif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "datacu.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error opening file"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "nhap du lieu thanh cong!\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error chuyen sang int"
.size .L.str.4, 22
.type _Z15patternBarchingPKiiiP5MOTIF,@object # @_Z15patternBarchingPKiiiP5MOTIF
.section .rodata,"a",@progbits
.globl _Z15patternBarchingPKiiiP5MOTIF
.p2align 3, 0x0
_Z15patternBarchingPKiiiP5MOTIF:
.quad _Z30__device_stub__patternBarchingPKiiiP5MOTIF
.size _Z15patternBarchingPKiiiP5MOTIF, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "\n Khai bao ko thanh cong\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n copy ko thanh cong\n"
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n khai bao ko thanh cong d_motif\n"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n ko copy dc data sang host"
.size .L.str.8, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15patternBarchingPKiiiP5MOTIF"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__patternBarchingPKiiiP5MOTIF
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym h_dataMotif
.addrsig_sym d_datainp
.addrsig_sym h_motif
.addrsig_sym d_motif
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15patternBarchingPKiiiP5MOTIF
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void writeSimilarities(const float* nvccResults, int* activelayers, int writestep, int writenum, float* similarities, int active_patches, int patches)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < active_patches)
{
float res = nvccResults[tid];
int patch = activelayers[tid];
for (int i = 0; i < writenum; ++i)
similarities[patches*writestep*i + patch] = res;
}
} | code for sm_80
Function : _Z17writeSimilaritiesPKfPiiiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0c7624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00a0*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fca0003f26070 */
/*00d0*/ IMAD.WIDE R4, R3, R0, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0200 */
/*00f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*0100*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000168000c1e1900 */
/*0110*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0120*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0130*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0140*/ @!P1 BRA 0x270 ; /* 0x0000012000009947 */
/* 0x000ff60003800000 */
/*0150*/ MOV R15, c[0x0][0x184] ; /* 0x00006100000f7a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R18, R12, -c[0x0][0x174], RZ ; /* 0x80005d000c127a10 */
/* 0x000fc40007ffe0ff */
/*0180*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x020fe20000000f00 */
/*0190*/ IMAD R15, R15, c[0x0][0x170], RZ ; /* 0x00005c000f0f7a24 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD.WIDE R2, R14, R0, c[0x0][0x178] ; /* 0x00005e000e027625 */
/* 0x001fe200078e0200 */
/*01b0*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LEA R14, R15.reuse, R14, 0x2 ; /* 0x0000000e0f0e7211 */
/* 0x040fe400078e10ff */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*01e0*/ IMAD.WIDE R4, R15, 0x4, R2 ; /* 0x000000040f047825 */
/* 0x000fc800078e0202 */
/*01f0*/ IMAD.IADD R16, R18, 0x1, R13 ; /* 0x0000000112107824 */
/* 0x000fe200078e020d */
/*0200*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e2000c101904 */
/*0210*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x000fc600078e0204 */
/*0220*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f25270 */
/*0230*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e2000c101904 */
/*0240*/ IMAD.WIDE R8, R15, 0x4, R6 ; /* 0x000000040f087825 */
/* 0x000fca00078e0206 */
/*0250*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001ea000c101904 */
/*0260*/ @P1 BRA 0x1a0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ IMAD R13, R13, c[0x0][0x184], RZ ; /* 0x000061000d0d7a24 */
/* 0x000fe200078e02ff */
/*0290*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x001fc60000000f00 */
/*02a0*/ IMAD R13, R13, c[0x0][0x170], R10 ; /* 0x00005c000d0d7a24 */
/* 0x020fc600078e020a */
/*02b0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE R2, R13, R0, c[0x0][0x178] ; /* 0x00005e000d027625 */
/* 0x001fc600078e0200 */
/*02d0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*02e0*/ IMAD R13, R4, c[0x0][0x170], R13 ; /* 0x00005c00040d7a24 */
/* 0x000fe200078e020d */
/*02f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001f6000c101904 */
/*0300*/ @P0 BRA 0x2b0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void writeSimilarities(const float* nvccResults, int* activelayers, int writestep, int writenum, float* similarities, int active_patches, int patches)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < active_patches)
{
float res = nvccResults[tid];
int patch = activelayers[tid];
for (int i = 0; i < writenum; ++i)
similarities[patches*writestep*i + patch] = res;
}
} | .file "tmpxft_00057cec_00000000-6_writeSimilarities.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii
.type _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii, @function
_Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17writeSimilaritiesPKfPiiiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii, .-_Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii
.globl _Z17writeSimilaritiesPKfPiiiPfii
.type _Z17writeSimilaritiesPKfPiiiPfii, @function
_Z17writeSimilaritiesPKfPiiiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17writeSimilaritiesPKfPiiiPfii, .-_Z17writeSimilaritiesPKfPiiiPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17writeSimilaritiesPKfPiiiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17writeSimilaritiesPKfPiiiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void writeSimilarities(const float* nvccResults, int* activelayers, int writestep, int writenum, float* similarities, int active_patches, int patches)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < active_patches)
{
float res = nvccResults[tid];
int patch = activelayers[tid];
for (int i = 0; i < writenum; ++i)
similarities[patches*writestep*i + patch] = res;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void writeSimilarities(const float* nvccResults, int* activelayers, int writestep, int writenum, float* similarities, int active_patches, int patches)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < active_patches)
{
float res = nvccResults[tid];
int patch = activelayers[tid];
for (int i = 0; i < writenum; ++i)
similarities[patches*writestep*i + patch] = res;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void writeSimilarities(const float* nvccResults, int* activelayers, int writestep, int writenum, float* similarities, int active_patches, int patches)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < active_patches)
{
float res = nvccResults[tid];
int patch = activelayers[tid];
for (int i = 0; i < writenum; ++i)
similarities[patches*writestep*i + patch] = res;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17writeSimilaritiesPKfPiiiPfii
.globl _Z17writeSimilaritiesPKfPiiiPfii
.p2align 8
.type _Z17writeSimilaritiesPKfPiiiPfii,@function
_Z17writeSimilaritiesPKfPiiiPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s3
.LBB0_3:
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v2, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17writeSimilaritiesPKfPiiiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17writeSimilaritiesPKfPiiiPfii, .Lfunc_end0-_Z17writeSimilaritiesPKfPiiiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17writeSimilaritiesPKfPiiiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17writeSimilaritiesPKfPiiiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void writeSimilarities(const float* nvccResults, int* activelayers, int writestep, int writenum, float* similarities, int active_patches, int patches)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < active_patches)
{
float res = nvccResults[tid];
int patch = activelayers[tid];
for (int i = 0; i < writenum; ++i)
similarities[patches*writestep*i + patch] = res;
}
} | .text
.file "writeSimilarities.hip"
.globl _Z32__device_stub__writeSimilaritiesPKfPiiiPfii # -- Begin function _Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.p2align 4, 0x90
.type _Z32__device_stub__writeSimilaritiesPKfPiiiPfii,@function
_Z32__device_stub__writeSimilaritiesPKfPiiiPfii: # @_Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17writeSimilaritiesPKfPiiiPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__writeSimilaritiesPKfPiiiPfii, .Lfunc_end0-_Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17writeSimilaritiesPKfPiiiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17writeSimilaritiesPKfPiiiPfii,@object # @_Z17writeSimilaritiesPKfPiiiPfii
.section .rodata,"a",@progbits
.globl _Z17writeSimilaritiesPKfPiiiPfii
.p2align 3, 0x0
_Z17writeSimilaritiesPKfPiiiPfii:
.quad _Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.size _Z17writeSimilaritiesPKfPiiiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17writeSimilaritiesPKfPiiiPfii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17writeSimilaritiesPKfPiiiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17writeSimilaritiesPKfPiiiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0c7624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00a0*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fca0003f26070 */
/*00d0*/ IMAD.WIDE R4, R3, R0, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0200 */
/*00f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*0100*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000168000c1e1900 */
/*0110*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0120*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0130*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0140*/ @!P1 BRA 0x270 ; /* 0x0000012000009947 */
/* 0x000ff60003800000 */
/*0150*/ MOV R15, c[0x0][0x184] ; /* 0x00006100000f7a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0170*/ IADD3 R18, R12, -c[0x0][0x174], RZ ; /* 0x80005d000c127a10 */
/* 0x000fc40007ffe0ff */
/*0180*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x020fe20000000f00 */
/*0190*/ IMAD R15, R15, c[0x0][0x170], RZ ; /* 0x00005c000f0f7a24 */
/* 0x000fc800078e02ff */
/*01a0*/ IMAD.WIDE R2, R14, R0, c[0x0][0x178] ; /* 0x00005e000e027625 */
/* 0x001fe200078e0200 */
/*01b0*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LEA R14, R15.reuse, R14, 0x2 ; /* 0x0000000e0f0e7211 */
/* 0x040fe400078e10ff */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*01e0*/ IMAD.WIDE R4, R15, 0x4, R2 ; /* 0x000000040f047825 */
/* 0x000fc800078e0202 */
/*01f0*/ IMAD.IADD R16, R18, 0x1, R13 ; /* 0x0000000112107824 */
/* 0x000fe200078e020d */
/*0200*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e2000c101904 */
/*0210*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x000fc600078e0204 */
/*0220*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f25270 */
/*0230*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e2000c101904 */
/*0240*/ IMAD.WIDE R8, R15, 0x4, R6 ; /* 0x000000040f087825 */
/* 0x000fca00078e0206 */
/*0250*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001ea000c101904 */
/*0260*/ @P1 BRA 0x1a0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ IMAD R13, R13, c[0x0][0x184], RZ ; /* 0x000061000d0d7a24 */
/* 0x000fe200078e02ff */
/*0290*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x001fc60000000f00 */
/*02a0*/ IMAD R13, R13, c[0x0][0x170], R10 ; /* 0x00005c000d0d7a24 */
/* 0x020fc600078e020a */
/*02b0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE R2, R13, R0, c[0x0][0x178] ; /* 0x00005e000d027625 */
/* 0x001fc600078e0200 */
/*02d0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*02e0*/ IMAD R13, R4, c[0x0][0x170], R13 ; /* 0x00005c00040d7a24 */
/* 0x000fe200078e020d */
/*02f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001f6000c101904 */
/*0300*/ @P0 BRA 0x2b0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17writeSimilaritiesPKfPiiiPfii
.globl _Z17writeSimilaritiesPKfPiiiPfii
.p2align 8
.type _Z17writeSimilaritiesPKfPiiiPfii,@function
_Z17writeSimilaritiesPKfPiiiPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s3
.LBB0_3:
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v2, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17writeSimilaritiesPKfPiiiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17writeSimilaritiesPKfPiiiPfii, .Lfunc_end0-_Z17writeSimilaritiesPKfPiiiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17writeSimilaritiesPKfPiiiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17writeSimilaritiesPKfPiiiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00057cec_00000000-6_writeSimilarities.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii
.type _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii, @function
_Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17writeSimilaritiesPKfPiiiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii, .-_Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii
.globl _Z17writeSimilaritiesPKfPiiiPfii
.type _Z17writeSimilaritiesPKfPiiiPfii, @function
_Z17writeSimilaritiesPKfPiiiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z17writeSimilaritiesPKfPiiiPfiiPKfPiiiPfii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17writeSimilaritiesPKfPiiiPfii, .-_Z17writeSimilaritiesPKfPiiiPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17writeSimilaritiesPKfPiiiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17writeSimilaritiesPKfPiiiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "writeSimilarities.hip"
.globl _Z32__device_stub__writeSimilaritiesPKfPiiiPfii # -- Begin function _Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.p2align 4, 0x90
.type _Z32__device_stub__writeSimilaritiesPKfPiiiPfii,@function
_Z32__device_stub__writeSimilaritiesPKfPiiiPfii: # @_Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17writeSimilaritiesPKfPiiiPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__writeSimilaritiesPKfPiiiPfii, .Lfunc_end0-_Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17writeSimilaritiesPKfPiiiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17writeSimilaritiesPKfPiiiPfii,@object # @_Z17writeSimilaritiesPKfPiiiPfii
.section .rodata,"a",@progbits
.globl _Z17writeSimilaritiesPKfPiiiPfii
.p2align 3, 0x0
_Z17writeSimilaritiesPKfPiiiPfii:
.quad _Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.size _Z17writeSimilaritiesPKfPiiiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17writeSimilaritiesPKfPiiiPfii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__writeSimilaritiesPKfPiiiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17writeSimilaritiesPKfPiiiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Author:
* Yixin Li, Email: liyixin@mit.edu
* convert the image from RGB to LAB
*/
__global__ void rgb_to_lab( double * img, const int nPts) {
// getting the index of the pixel
const int t = threadIdx.x + blockIdx.x * blockDim.x;
if (t>=nPts) return;
double sR = img[3*t];
double sG = img[3*t+1];
double sB = img[3*t+2];
if (sR!=sR || sG!=sG || sB!=sB) return;
//RGB (D65 illuninant assumption) to XYZ conversion
double R = sR/255.0;
double G = sG/255.0;
double B = sB/255.0;
double r, g, b;
if(R <= 0.04045) r = R/12.92;
else r = pow((R+0.055)/1.055,2.4);
if(G <= 0.04045) g = G/12.92;
else g = pow((G+0.055)/1.055,2.4);
if(B <= 0.04045) b = B/12.92;
else b = pow((B+0.055)/1.055,2.4);
double X = r*0.4124564 + g*0.3575761 + b*0.1804375;
double Y = r*0.2126729 + g*0.7151522 + b*0.0721750;
double Z = r*0.0193339 + g*0.1191920 + b*0.9503041;
//convert from XYZ to LAB
double epsilon = 0.008856; //actual CIE standard
double kappa = 903.3; //actual CIE standard
double Xr = 0.950456; //reference white
double Yr = 1.0; //reference white
double Zr = 1.088754; //reference white
double xr = X/Xr;
double yr = Y/Yr;
double zr = Z/Zr;
double fx, fy, fz;
if(xr > epsilon) fx = pow(xr, 1.0/3.0);
else fx = (kappa*xr + 16.0)/116.0;
if(yr > epsilon) fy = pow(yr, 1.0/3.0);
else fy = (kappa*yr + 16.0)/116.0;
if(zr > epsilon) fz = pow(zr, 1.0/3.0);
else fz = (kappa*zr + 16.0)/116.0;
double lval = 116.0*fy-16.0;
double aval = 500.0*(fx-fy);
double bval = 200.0*(fy-fz);
img[3*t] = lval;
img[3*t+1] = aval;
img[3*t+2] = bval;
} | .file "tmpxft_000cb290_00000000-6_rgb_to_lab.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z10rgb_to_labPdiPdi
.type _Z31__device_stub__Z10rgb_to_labPdiPdi, @function
_Z31__device_stub__Z10rgb_to_labPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10rgb_to_labPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z10rgb_to_labPdiPdi, .-_Z31__device_stub__Z10rgb_to_labPdiPdi
.globl _Z10rgb_to_labPdi
.type _Z10rgb_to_labPdi, @function
_Z10rgb_to_labPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10rgb_to_labPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10rgb_to_labPdi, .-_Z10rgb_to_labPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10rgb_to_labPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10rgb_to_labPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Author:
* Yixin Li, Email: liyixin@mit.edu
* convert the image from RGB to LAB
*/
__global__ void rgb_to_lab( double * img, const int nPts) {
// getting the index of the pixel
const int t = threadIdx.x + blockIdx.x * blockDim.x;
if (t>=nPts) return;
double sR = img[3*t];
double sG = img[3*t+1];
double sB = img[3*t+2];
if (sR!=sR || sG!=sG || sB!=sB) return;
//RGB (D65 illuninant assumption) to XYZ conversion
double R = sR/255.0;
double G = sG/255.0;
double B = sB/255.0;
double r, g, b;
if(R <= 0.04045) r = R/12.92;
else r = pow((R+0.055)/1.055,2.4);
if(G <= 0.04045) g = G/12.92;
else g = pow((G+0.055)/1.055,2.4);
if(B <= 0.04045) b = B/12.92;
else b = pow((B+0.055)/1.055,2.4);
double X = r*0.4124564 + g*0.3575761 + b*0.1804375;
double Y = r*0.2126729 + g*0.7151522 + b*0.0721750;
double Z = r*0.0193339 + g*0.1191920 + b*0.9503041;
//convert from XYZ to LAB
double epsilon = 0.008856; //actual CIE standard
double kappa = 903.3; //actual CIE standard
double Xr = 0.950456; //reference white
double Yr = 1.0; //reference white
double Zr = 1.088754; //reference white
double xr = X/Xr;
double yr = Y/Yr;
double zr = Z/Zr;
double fx, fy, fz;
if(xr > epsilon) fx = pow(xr, 1.0/3.0);
else fx = (kappa*xr + 16.0)/116.0;
if(yr > epsilon) fy = pow(yr, 1.0/3.0);
else fy = (kappa*yr + 16.0)/116.0;
if(zr > epsilon) fz = pow(zr, 1.0/3.0);
else fz = (kappa*zr + 16.0)/116.0;
double lval = 116.0*fy-16.0;
double aval = 500.0*(fx-fy);
double bval = 200.0*(fy-fz);
img[3*t] = lval;
img[3*t+1] = aval;
img[3*t+2] = bval;
} | #include <hip/hip_runtime.h>
/*
* Author:
* Yixin Li, Email: liyixin@mit.edu
* convert the image from RGB to LAB
*/
__global__ void rgb_to_lab( double * img, const int nPts) {
// getting the index of the pixel
const int t = threadIdx.x + blockIdx.x * blockDim.x;
if (t>=nPts) return;
double sR = img[3*t];
double sG = img[3*t+1];
double sB = img[3*t+2];
if (sR!=sR || sG!=sG || sB!=sB) return;
//RGB (D65 illuninant assumption) to XYZ conversion
double R = sR/255.0;
double G = sG/255.0;
double B = sB/255.0;
double r, g, b;
if(R <= 0.04045) r = R/12.92;
else r = pow((R+0.055)/1.055,2.4);
if(G <= 0.04045) g = G/12.92;
else g = pow((G+0.055)/1.055,2.4);
if(B <= 0.04045) b = B/12.92;
else b = pow((B+0.055)/1.055,2.4);
double X = r*0.4124564 + g*0.3575761 + b*0.1804375;
double Y = r*0.2126729 + g*0.7151522 + b*0.0721750;
double Z = r*0.0193339 + g*0.1191920 + b*0.9503041;
//convert from XYZ to LAB
double epsilon = 0.008856; //actual CIE standard
double kappa = 903.3; //actual CIE standard
double Xr = 0.950456; //reference white
double Yr = 1.0; //reference white
double Zr = 1.088754; //reference white
double xr = X/Xr;
double yr = Y/Yr;
double zr = Z/Zr;
double fx, fy, fz;
if(xr > epsilon) fx = pow(xr, 1.0/3.0);
else fx = (kappa*xr + 16.0)/116.0;
if(yr > epsilon) fy = pow(yr, 1.0/3.0);
else fy = (kappa*yr + 16.0)/116.0;
if(zr > epsilon) fz = pow(zr, 1.0/3.0);
else fz = (kappa*zr + 16.0)/116.0;
double lval = 116.0*fy-16.0;
double aval = 500.0*(fx-fy);
double bval = 200.0*(fy-fz);
img[3*t] = lval;
img[3*t+1] = aval;
img[3*t+2] = bval;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Author:
* Yixin Li, Email: liyixin@mit.edu
* convert the image from RGB to LAB
*/
__global__ void rgb_to_lab( double * img, const int nPts) {
// getting the index of the pixel
const int t = threadIdx.x + blockIdx.x * blockDim.x;
if (t>=nPts) return;
double sR = img[3*t];
double sG = img[3*t+1];
double sB = img[3*t+2];
if (sR!=sR || sG!=sG || sB!=sB) return;
//RGB (D65 illuninant assumption) to XYZ conversion
double R = sR/255.0;
double G = sG/255.0;
double B = sB/255.0;
double r, g, b;
if(R <= 0.04045) r = R/12.92;
else r = pow((R+0.055)/1.055,2.4);
if(G <= 0.04045) g = G/12.92;
else g = pow((G+0.055)/1.055,2.4);
if(B <= 0.04045) b = B/12.92;
else b = pow((B+0.055)/1.055,2.4);
double X = r*0.4124564 + g*0.3575761 + b*0.1804375;
double Y = r*0.2126729 + g*0.7151522 + b*0.0721750;
double Z = r*0.0193339 + g*0.1191920 + b*0.9503041;
//convert from XYZ to LAB
double epsilon = 0.008856; //actual CIE standard
double kappa = 903.3; //actual CIE standard
double Xr = 0.950456; //reference white
double Yr = 1.0; //reference white
double Zr = 1.088754; //reference white
double xr = X/Xr;
double yr = Y/Yr;
double zr = Z/Zr;
double fx, fy, fz;
if(xr > epsilon) fx = pow(xr, 1.0/3.0);
else fx = (kappa*xr + 16.0)/116.0;
if(yr > epsilon) fy = pow(yr, 1.0/3.0);
else fy = (kappa*yr + 16.0)/116.0;
if(zr > epsilon) fz = pow(zr, 1.0/3.0);
else fz = (kappa*zr + 16.0)/116.0;
double lval = 116.0*fy-16.0;
double aval = 500.0*(fx-fy);
double bval = 200.0*(fy-fz);
img[3*t] = lval;
img[3*t+1] = aval;
img[3*t+2] = bval;
} | .text
.file "rgb_to_lab.hip"
.globl _Z25__device_stub__rgb_to_labPdi # -- Begin function _Z25__device_stub__rgb_to_labPdi
.p2align 4, 0x90
.type _Z25__device_stub__rgb_to_labPdi,@function
_Z25__device_stub__rgb_to_labPdi: # @_Z25__device_stub__rgb_to_labPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10rgb_to_labPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__rgb_to_labPdi, .Lfunc_end0-_Z25__device_stub__rgb_to_labPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10rgb_to_labPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10rgb_to_labPdi,@object # @_Z10rgb_to_labPdi
.section .rodata,"a",@progbits
.globl _Z10rgb_to_labPdi
.p2align 3, 0x0
_Z10rgb_to_labPdi:
.quad _Z25__device_stub__rgb_to_labPdi
.size _Z10rgb_to_labPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10rgb_to_labPdi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__rgb_to_labPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10rgb_to_labPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cb290_00000000-6_rgb_to_lab.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z10rgb_to_labPdiPdi
.type _Z31__device_stub__Z10rgb_to_labPdiPdi, @function
_Z31__device_stub__Z10rgb_to_labPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10rgb_to_labPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z10rgb_to_labPdiPdi, .-_Z31__device_stub__Z10rgb_to_labPdiPdi
.globl _Z10rgb_to_labPdi
.type _Z10rgb_to_labPdi, @function
_Z10rgb_to_labPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10rgb_to_labPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10rgb_to_labPdi, .-_Z10rgb_to_labPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10rgb_to_labPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10rgb_to_labPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rgb_to_lab.hip"
.globl _Z25__device_stub__rgb_to_labPdi # -- Begin function _Z25__device_stub__rgb_to_labPdi
.p2align 4, 0x90
.type _Z25__device_stub__rgb_to_labPdi,@function
_Z25__device_stub__rgb_to_labPdi: # @_Z25__device_stub__rgb_to_labPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10rgb_to_labPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__rgb_to_labPdi, .Lfunc_end0-_Z25__device_stub__rgb_to_labPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10rgb_to_labPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10rgb_to_labPdi,@object # @_Z10rgb_to_labPdi
.section .rodata,"a",@progbits
.globl _Z10rgb_to_labPdi
.p2align 3, 0x0
_Z10rgb_to_labPdi:
.quad _Z25__device_stub__rgb_to_labPdi
.size _Z10rgb_to_labPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10rgb_to_labPdi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__rgb_to_labPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10rgb_to_labPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<conio.h>
#define width 4
__global__ void sumReductionEff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=blockDim.x/2; stride>0; stride/=2)
{
__syncthreads();
if(t<stride)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
__global__ void sumReductionIneff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=1; stride<blockDim.x; stride*=2)
{
__syncthreads();
if(t%2 == 0)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
int main()
{
int pSum[] = {1,2,3,4,5,6,7,8};
int n = 8, *d_pSum, i = 0;
int size = n*sizeof(int);
cudaMalloc((void**)&d_pSum, size);
cudaMemcpy(d_pSum, pSum, size, cudaMemcpyHostToDevice);
printf("\n Elements of the array : \n");
for(i=0; i<n; i++)
printf("%d \t", pSum[i]);
sumReductionIneff<<<1, n>>>(d_pSum, n);
cudaMemcpy(pSum, d_pSum, size, cudaMemcpyDeviceToHost);
printf("\n");
printf("Sum of the array elements = %d", pSum[0]);
getch();
return 0;
}
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<conio.h>
#define width 4
__global__ void sumReductionEff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=blockDim.x/2; stride>0; stride/=2)
{
__syncthreads();
if(t<stride)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
__global__ void sumReductionIneff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=1; stride<blockDim.x; stride*=2)
{
__syncthreads();
if(t%2 == 0)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
int main()
{
int pSum[] = {1,2,3,4,5,6,7,8};
int n = 8, *d_pSum, i = 0;
int size = n*sizeof(int);
cudaMalloc((void**)&d_pSum, size);
cudaMemcpy(d_pSum, pSum, size, cudaMemcpyHostToDevice);
printf("\n Elements of the array : \n");
for(i=0; i<n; i++)
printf("%d \t", pSum[i]);
sumReductionIneff<<<1, n>>>(d_pSum, n);
cudaMemcpy(pSum, d_pSum, size, cudaMemcpyDeviceToHost);
printf("\n");
printf("Sum of the array elements = %d", pSum[0]);
getch();
return 0;
}
*/ | .file "tmpxft_0017105e_00000000-6_Reduction_Sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<conio.h>
#define width 4
__global__ void sumReductionEff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=blockDim.x/2; stride>0; stride/=2)
{
__syncthreads();
if(t<stride)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
__global__ void sumReductionIneff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=1; stride<blockDim.x; stride*=2)
{
__syncthreads();
if(t%2 == 0)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
int main()
{
int pSum[] = {1,2,3,4,5,6,7,8};
int n = 8, *d_pSum, i = 0;
int size = n*sizeof(int);
cudaMalloc((void**)&d_pSum, size);
cudaMemcpy(d_pSum, pSum, size, cudaMemcpyHostToDevice);
printf("\n Elements of the array : \n");
for(i=0; i<n; i++)
printf("%d \t", pSum[i]);
sumReductionIneff<<<1, n>>>(d_pSum, n);
cudaMemcpy(pSum, d_pSum, size, cudaMemcpyDeviceToHost);
printf("\n");
printf("Sum of the array elements = %d", pSum[0]);
getch();
return 0;
}
*/ | #include <hip/hip_runtime.h>
/*
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<conio.h>
#define width 4
__global__ void sumReductionEff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=blockDim.x/2; stride>0; stride/=2)
{
__syncthreads();
if(t<stride)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
__global__ void sumReductionIneff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=1; stride<blockDim.x; stride*=2)
{
__syncthreads();
if(t%2 == 0)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
int main()
{
int pSum[] = {1,2,3,4,5,6,7,8};
int n = 8, *d_pSum, i = 0;
int size = n*sizeof(int);
cudaMalloc((void**)&d_pSum, size);
cudaMemcpy(d_pSum, pSum, size, cudaMemcpyHostToDevice);
printf("\n Elements of the array : \n");
for(i=0; i<n; i++)
printf("%d \t", pSum[i]);
sumReductionIneff<<<1, n>>>(d_pSum, n);
cudaMemcpy(pSum, d_pSum, size, cudaMemcpyDeviceToHost);
printf("\n");
printf("Sum of the array elements = %d", pSum[0]);
getch();
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<conio.h>
#define width 4
__global__ void sumReductionEff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=blockDim.x/2; stride>0; stride/=2)
{
__syncthreads();
if(t<stride)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
__global__ void sumReductionIneff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=1; stride<blockDim.x; stride*=2)
{
__syncthreads();
if(t%2 == 0)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
int main()
{
int pSum[] = {1,2,3,4,5,6,7,8};
int n = 8, *d_pSum, i = 0;
int size = n*sizeof(int);
cudaMalloc((void**)&d_pSum, size);
cudaMemcpy(d_pSum, pSum, size, cudaMemcpyHostToDevice);
printf("\n Elements of the array : \n");
for(i=0; i<n; i++)
printf("%d \t", pSum[i]);
sumReductionIneff<<<1, n>>>(d_pSum, n);
cudaMemcpy(pSum, d_pSum, size, cudaMemcpyDeviceToHost);
printf("\n");
printf("Sum of the array elements = %d", pSum[0]);
getch();
return 0;
}
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
#ifndef __CUDACC__
#define __CUDACC__
#endif
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<conio.h>
#define width 4
__global__ void sumReductionEff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=blockDim.x/2; stride>0; stride/=2)
{
__syncthreads();
if(t<stride)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
__global__ void sumReductionIneff(int *d_pSum, int n)
{
int i = 0;
__shared__ int partialSum[width];
unsigned int t=threadIdx.x;
partialSum[t] = d_pSum[t];
__syncthreads();
for(unsigned int stride=1; stride<blockDim.x; stride*=2)
{
__syncthreads();
if(t%2 == 0)
partialSum[t] += partialSum[t+stride];
}
d_pSum[t] = partialSum[t];
}
int main()
{
int pSum[] = {1,2,3,4,5,6,7,8};
int n = 8, *d_pSum, i = 0;
int size = n*sizeof(int);
cudaMalloc((void**)&d_pSum, size);
cudaMemcpy(d_pSum, pSum, size, cudaMemcpyHostToDevice);
printf("\n Elements of the array : \n");
for(i=0; i<n; i++)
printf("%d \t", pSum[i]);
sumReductionIneff<<<1, n>>>(d_pSum, n);
cudaMemcpy(pSum, d_pSum, size, cudaMemcpyDeviceToHost);
printf("\n");
printf("Sum of the array elements = %d", pSum[0]);
getch();
return 0;
}
*/ | .text
.file "Reduction_Sum.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017105e_00000000-6_Reduction_Sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Reduction_Sum.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Prashant Solanki (Unity: psolank)
* Simple Image convolutions implementation without tiling
* Convolutions mask is stored in constant memory
* Tested with CUDA Toolkit 3.0
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#include <cuda.h>
#define BUF_SIZE 200000
#define ThreadsPerBlockX 8
#define ThreadsPerBlockY 8
#define CUDA_CALL(X) if(cudaSuccess != X) printf("Call Failed at %s\n",__LINE__);
int count_cols(char *buff);
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2);
void print2D(float *arr, int r, int c);
float* alloc2D(int r, int c);
void free2D(float *arr);
void parse2D(FILE *f, float *arr, int r, int c);
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py);
void flip_kernel(float * arr, int r, int c);
// Constant cache memory to store convolution mask and its size
__constant__ float dMask[100];
__constant__ int dHalfW;
__constant__ int dHalfH;
// kernel to convolve image with mask
// one thread processes one pixel in input image
__global__ void conv2DKernel(float *in, float *out, int r1, int c1) {
int i,j; int x,y;
int maskIndex = 0;
// computing row and column of pixel for which convolution os to be done
int r = blockIdx.y*blockDim.y + threadIdx.y;
int c = blockIdx.x*blockDim.x + threadIdx.x;
float acc = 0.0f;
// accessing neighbouring pixels and multiplying with mask
for(i = -dHalfH; i <= dHalfH; i++){
for(j = -dHalfW; j <= dHalfW; j++){
x = c + j;
y = r + i;
// condition to check if element is outside the image
if(x >= 0 && x < c1 && y >= 0 && y < r1){
acc = acc + (dMask[maskIndex] * in[ y*c1 + x ]);
}
maskIndex++;
}
}
// condition to check if element is outside image
if(r < r1 && c < c1){
out[ r*c1 + c ] = acc;
}
}
int main(int argc, char **argv) {
float *hInput;
float *hMask;
float *hOutput;
float *dInput;
float *dOutput;
int r1,c1,r2,c2, R, C;
FILE *fptr;
if(argc < 2) { printf(" Please specify input filename\n"); return -1;}
// Finding dimensions of input matricex
count_rc(argv[1],&r1, &c1, &r2, &c2);
if(r1 == 0) return -1;
// conputing dimensions of output matrix
R = (r1 + r2) -1;
C = (c1 + c2) -1;
// allocating input matrices
hInput = alloc2D(R, C);
// zeroing the input matrix
memset(hInput, 0, sizeof(float)*R*C);
// allocation mask
hMask = alloc2D(10, 10);
// allocating output matix
hOutput = alloc2D(R, C);
// opening input file
fptr = fopen(argv[1], "rb");
// parsing first matrix withing the padded region defined as c2/2 and r2/2
parse2DPadded(fptr, hInput, r1, c1, c2/2, r2/2);
// parsing mask
parse2D(fptr, hMask, r2, c2);
// closing the file
fclose(fptr);
// flipping kernel vertically and horizontally
flip_kernel(hMask, r2, c2);
// print2D(hMask, r2, c2);
r2 = r2/2;
c2 = c2/2;
// allocating gpu memory
CUDA_CALL(cudaMalloc((void**)&dInput, R*C*sizeof(float)));
//err = cudaMalloc((void**)&dMask, r2*c2*sizeof(float));
CUDA_CALL(cudaMalloc((void**)&dOutput, R*C*sizeof(float)));
// Copy memory to the GPU
CUDA_CALL(cudaMemcpy(dInput, hInput, sizeof(float)*R*C, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dMask, hMask, sizeof(float)*10*10, 0, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dHalfW, (const int*)&r2, sizeof(int), 0, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dHalfH, (const int*)&c2, sizeof(int), 0, cudaMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 numThreads(ThreadsPerBlockX,ThreadsPerBlockY,1);
dim3 numBlocks( ((C-1)/ThreadsPerBlockX)+1, ((R-1)/ThreadsPerBlockY)+1, 1 );
// Launch the GPU Kernel
conv2DKernel<<<numBlocks, numThreads>>>(dInput, dOutput, R, C);
//cudaDeviceSynchronize();
CUDA_CALL(cudaThreadSynchronize());
// Copy the GPU memory back to the CPU
CUDA_CALL(cudaMemcpy(hOutput, dOutput, R*C*sizeof(float), cudaMemcpyDeviceToHost));
// free the GPU memory
CUDA_CALL(cudaFree(dInput));
CUDA_CALL(cudaFree(dOutput));
// printing result
print2D(hOutput, R, C);
// free the host memory
free2D(hInput);
free2D(hMask);
free2D(hOutput);
return 0;
}
// count number of rows and columns for the given input file
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2)
{
*r1 = 0; *c1 = 0; *r2 = 0; *c2 =0;
char *buff = (char*)malloc(BUF_SIZE);
FILE *f = fopen(fname, "rb");
if(f == NULL){ printf("Unable to open file %s\n",fname); free(buff); return; }
fgets(buff, BUF_SIZE, f);
*c1 = count_cols(buff);
while(strlen(buff) > 1){
(*r1)++;
fgets(buff, BUF_SIZE, f);
}
fgets(buff, BUF_SIZE, f);
*c2 = count_cols(buff);
while(strlen(buff) > 1){
(*r2)++;
if(NULL == fgets(buff, BUF_SIZE, f)) break;
if((feof(f)) && (strlen(buff) > 1) ){(*r2)++; break;}
}
free(buff);
fclose(f);
}
// count number of columns in given buffer
int count_cols(char *buff)
{
int i;int n=1;
for(i=0; i<strlen(buff)-1; i++)
{
if(buff[i] == ' '){
if(buff[i+1] != '\n' && buff[i+1] != '\r' && buff[i+1] != ' '){
n++;
}
}
}
return n;
}
// print a 2D matrix
void print2D(float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
if(j>0) printf(" ");
printf("%f",arr[ i*r + j]);
}
printf("\n");
}
}
// allocate memory for matrix of size rxc
float* alloc2D(int r, int c)
{
return (float*)malloc( r*c*sizeof(float) );
}
// free memory
void free2D(float *arr)
{
free(arr);
}
// parsing a matrix of size rxc
void parse2D(FILE *f, float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ (i*c) + j] );
}
}
}
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py)
{
int i,j;
int wStep = c + 2*px;
int offset = py*wStep + px;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ offset + (i*wStep) + j] );
}
}
}
void flip_kernel(float * arr, int r, int c)
{
float f;
int i,j;
int R = r-1;
int C = c-1;
for(i=0; i<=r/2; i++){
for(j=0; j<c; j++){
f = arr[i*c +j];
arr[i*c +j] = arr[(R-i)*c + (C-j)];
arr[(R-i)*c + (C-j)] = f;
}
}
} | code for sm_80
Function : _Z12conv2DKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV R4, RZ, RZ, -c[0x3][0x190] ; /* 0x80c06400ff047624 */
/* 0x000fe200078e02ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV R8, RZ, RZ, -c[0x3][0x194] ; /* 0x80c06500ff087624 */
/* 0x000fe200078e02ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.LE.AND P0, PT, R4, c[0x3][0x190], PT ; /* 0x00c0640004007a0c */
/* 0x000fe40003f03270 */
/*0070*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e640000002500 */
/*0080*/ ISETP.GT.OR P0, PT, R8, c[0x3][0x194], !P0 ; /* 0x00c0650008007a0c */
/* 0x000fc40004704670 */
/*0090*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x001fe400078e0200 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x002fcc00078e0203 */
/*00d0*/ @P0 BRA 0x780 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*00e0*/ IMNMX R9, R4, c[0x3][0x190], !PT ; /* 0x00c0640004097a17 */
/* 0x000fe20007800200 */
/*00f0*/ ULDC UR4, c[0x3][0x190] ; /* 0x00c0640000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ IADD3 R7, R6.reuse, -c[0x3][0x190], RZ ; /* 0x80c0640006077a10 */
/* 0x040fe20007ffe0ff */
/*0110*/ UIADD3 UR5, -UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe13f */
/*0120*/ IADD3 R9, R9, c[0x3][0x190], RZ ; /* 0x00c0640009097a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ UIADD3 UR6, -UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe13f */
/*0140*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0150*/ UIADD3 UR4, -UR4, 0x3, URZ ; /* 0x0000000304047890 */
/* 0x000fe2000fffe13f */
/*0160*/ IADD3 R12, R9, 0x1, RZ ; /* 0x00000001090c7810 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R10, R6.reuse, UR5, RZ ; /* 0x00000005060a7c10 */
/* 0x040fe2000fffe0ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R11, R6, UR6, RZ ; /* 0x00000006060b7c10 */
/* 0x000fc4000fffe0ff */
/*01b0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fc800078ec0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*01d0*/ IMAD.IADD R14, R5, 0x1, R8 ; /* 0x00000001050e7824 */
/* 0x000fe200078e0208 */
/*01e0*/ ISETP.GE.AND P4, PT, R8.reuse, c[0x3][0x194], PT ; /* 0x00c0650008007a0c */
/* 0x040fe20003f86270 */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0004 */
/*0200*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fd20007ffe0ff */
/*0210*/ @!P0 BRA 0x4b0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0220*/ LOP3.LUT R2, R7, R14, RZ, 0xfc, !PT ; /* 0x0000000e07027212 */
/* 0x000fe200078efcff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0240*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*0250*/ IMAD R2, R14, c[0x0][0x174], R7 ; /* 0x00005d000e027a24 */
/* 0x000fc600078e0207 */
/*0260*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x174], !P0 ; /* 0x00005d0007007a0c */
/* 0x000fe20004706670 */
/*0270*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0203 */
/*0280*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fda0000706670 */
/*0290*/ @!P0 LDG.E R18, [R2.64] ; /* 0x0000000802128981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IMAD.SHL.U32 R17, R16, 0x4, RZ ; /* 0x0000000410117824 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f25270 */
/*02c0*/ IADD3 R13, R16, 0x1, RZ ; /* 0x00000001100d7810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ @!P0 LDC R15, c[0x3][R17] ; /* 0x00c00000110f8b82 */
/* 0x000ea40000000800 */
/*02e0*/ @!P0 FFMA R0, R15, R18, R0 ; /* 0x000000120f008223 */
/* 0x004fe40000000000 */
/*02f0*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fcc000f8e00ff */
/*0300*/ @!P1 BRA 0x4b0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0310*/ LOP3.LUT R13, R10, R14, RZ, 0xfc, !PT ; /* 0x0000000e0a0d7212 */
/* 0x000fe200078efcff */
/*0320*/ BSSY B0, 0x3c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0330*/ ISETP.NE.AND P1, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f25270 */
/*0340*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*0350*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x174], !P0 ; /* 0x00005d000a007a0c */
/* 0x000fc80004706670 */
/*0360*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fda0000706670 */
/*0370*/ @P0 BRA 0x3b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000408020d7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ LDC R15, c[0x3][R17+0x4] ; /* 0x00c00100110f7b82 */
/* 0x000ea40000000800 */
/*03a0*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x004fcc0000000000 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ IADD3 R13, R16, 0x2, RZ ; /* 0x00000002100d7810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD.U32 R15, RZ, RZ, UR6 ; /* 0x00000006ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*03e0*/ @!P1 BRA 0x4b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT R13, R11, R14, RZ, 0xfc, !PT ; /* 0x0000000e0b0d7212 */
/* 0x000fe200078efcff */
/*0400*/ BSSY B0, 0x490 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*0420*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x174], !P0 ; /* 0x00005d000b007a0c */
/* 0x000fc80004706670 */
/*0430*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fda0000706670 */
/*0440*/ @P0 BRA 0x480 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000080802037981 */
/* 0x000ea2000c1e1900 */
/*0460*/ LDC R17, c[0x3][R17+0x8] ; /* 0x00c0020011117b82 */
/* 0x000ea40000000800 */
/*0470*/ FFMA R0, R3, R17, R0 ; /* 0x0000001103007223 */
/* 0x004fcc0000000000 */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0490*/ IADD3 R13, R16, 0x3, RZ ; /* 0x00000003100d7810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD.U32 R15, RZ, RZ, UR4 ; /* 0x00000004ff0f7e24 */
/* 0x000fe4000f8e00ff */
/*04b0*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f06070 */
/*04c0*/ @!P0 BRA 0x760 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.IADD R23, R6, 0x1, R15 ; /* 0x0000000106177824 */
/* 0x000fe200078e020f */
/*04e0*/ IADD3 R17, R15, 0x3, RZ ; /* 0x000000030f117810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ LOP3.LUT R2, R23.reuse, R14.reuse, RZ, 0xfc, !PT ; /* 0x0000000e17027212 */
/* 0x0c0fe200078efcff */
/*0500*/ IMAD.IADD R21, R6, 0x1, R17 ; /* 0x0000000106157824 */
/* 0x000fe200078e0211 */
/*0510*/ IADD3 R3, R23.reuse, 0x1, RZ ; /* 0x0000000117037810 */
/* 0x040fe40007ffe0ff */
/*0520*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*0530*/ IADD3 R19, R23, 0x2, RZ ; /* 0x0000000217137810 */
/* 0x000fe40007ffe0ff */
/*0540*/ LOP3.LUT R16, R3, R14, RZ, 0xfc, !PT ; /* 0x0000000e03107212 */
/* 0x000fe400078efcff */
/*0550*/ ISETP.GE.OR P1, PT, R23, c[0x0][0x174], !P1 ; /* 0x00005d0017007a0c */
/* 0x000fc40004f26670 */
/*0560*/ LOP3.LUT R2, R19, R14.reuse, RZ, 0xfc, !PT ; /* 0x0000000e13027212 */
/* 0x080fe400078efcff */
/*0570*/ ISETP.GE.AND P3, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f66270 */
/*0580*/ ISETP.GE.OR P1, PT, R14, c[0x0][0x170], P1 ; /* 0x00005c000e007a0c */
/* 0x000fe40000f26670 */
/*0590*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*05a0*/ IMAD R2, R14, c[0x0][0x174], R23 ; /* 0x00005d000e027a24 */
/* 0x000fe200078e0217 */
/*05b0*/ ISETP.GE.OR P3, PT, R3, c[0x0][0x174], !P3 ; /* 0x00005d0003007a0c */
/* 0x000fe20005f66670 */
/*05c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*05d0*/ LOP3.LUT R18, R21, R14, RZ, 0xfc, !PT ; /* 0x0000000e15127212 */
/* 0x000fc400078efcff */
/*05e0*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x174], !P0 ; /* 0x00005d0013007a0c */
/* 0x000fe20004706670 */
/*05f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0600*/ ISETP.GE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f46270 */
/*0610*/ ISETP.GE.OR P3, PT, R14.reuse, c[0x0][0x170], P3 ; /* 0x00005c000e007a0c */
/* 0x040fe40001f66670 */
/*0620*/ ISETP.GE.OR P2, PT, R21, c[0x0][0x174], !P2 ; /* 0x00005d0015007a0c */
/* 0x000fe20005746670 */
/*0630*/ @!P1 LDG.E R18, [R2.64] ; /* 0x0000000802129981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.GE.OR P0, PT, R14.reuse, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x040fe40000706670 */
/*0650*/ ISETP.GE.OR P2, PT, R14, c[0x0][0x170], P2 ; /* 0x00005c000e007a0c */
/* 0x000fce0001746670 */
/*0660*/ @!P3 LDG.E R21, [R2.64+0x4] ; /* 0x000004080215b981 */
/* 0x000ee8000c1e1900 */
/*0670*/ @!P0 LDG.E R23, [R2.64+0x8] ; /* 0x0000080802178981 */
/* 0x000f28000c1e1900 */
/*0680*/ @!P2 LDG.E R25, [R2.64+0xc] ; /* 0x00000c080219a981 */
/* 0x000f62000c1e1900 */
/*0690*/ IMAD.SHL.U32 R16, R13, 0x4, RZ ; /* 0x000000040d107824 */
/* 0x000fc800078e00ff */
/*06a0*/ @!P1 LDC R19, c[0x3][R16] ; /* 0x00c0000010139b82 */
/* 0x000eb00000000800 */
/*06b0*/ @!P3 LDC R20, c[0x3][R16+0x4] ; /* 0x00c001001014bb82 */
/* 0x000ef00000000800 */
/*06c0*/ @!P0 LDC R22, c[0x3][R16+0x8] ; /* 0x00c0020010168b82 */
/* 0x000f300000000800 */
/*06d0*/ @!P2 LDC R24, c[0x3][R16+0xc] ; /* 0x00c003001018ab82 */
/* 0x000f620000000800 */
/*06e0*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fc40007ffe0ff */
/*06f0*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe20007ffe0ff */
/*0700*/ @!P1 FFMA R0, R19, R18, R0 ; /* 0x0000001213009223 */
/* 0x004fe20000000000 */
/*0710*/ ISETP.GE.AND P1, PT, R17, c[0x3][0x190], PT ; /* 0x00c0640011007a0c */
/* 0x000fc60003f26270 */
/*0720*/ @!P3 FFMA R0, R21, R20, R0 ; /* 0x000000141500b223 */
/* 0x008fc80000000000 */
/*0730*/ @!P0 FFMA R0, R23, R22, R0 ; /* 0x0000001617008223 */
/* 0x010fc80000000000 */
/*0740*/ @!P2 FFMA R0, R25, R24, R0 ; /* 0x000000181900a223 */
/* 0x020fe40000000000 */
/*0750*/ @!P1 BRA 0x4d0 ; /* 0xfffffd7000009947 */
/* 0x000fea000383ffff */
/*0760*/ IMAD.MOV.U32 R16, RZ, RZ, R13 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000d */
/*0770*/ @!P4 BRA 0x1c0 ; /* 0xfffffa400000c947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fc80003f06270 */
/*0790*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*07a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*07c0*/ IMAD R2, R5, c[0x0][0x174], R6 ; /* 0x00005d0005027a24 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*07e0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101908 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Prashant Solanki (Unity: psolank)
* Simple Image convolutions implementation without tiling
* Convolutions mask is stored in constant memory
* Tested with CUDA Toolkit 3.0
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#include <cuda.h>
#define BUF_SIZE 200000
#define ThreadsPerBlockX 8
#define ThreadsPerBlockY 8
#define CUDA_CALL(X) if(cudaSuccess != X) printf("Call Failed at %s\n",__LINE__);
int count_cols(char *buff);
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2);
void print2D(float *arr, int r, int c);
float* alloc2D(int r, int c);
void free2D(float *arr);
void parse2D(FILE *f, float *arr, int r, int c);
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py);
void flip_kernel(float * arr, int r, int c);
// Constant cache memory to store convolution mask and its size
__constant__ float dMask[100];
__constant__ int dHalfW;
__constant__ int dHalfH;
// kernel to convolve image with mask
// one thread processes one pixel in input image
__global__ void conv2DKernel(float *in, float *out, int r1, int c1) {
int i,j; int x,y;
int maskIndex = 0;
// computing row and column of pixel for which convolution os to be done
int r = blockIdx.y*blockDim.y + threadIdx.y;
int c = blockIdx.x*blockDim.x + threadIdx.x;
float acc = 0.0f;
// accessing neighbouring pixels and multiplying with mask
for(i = -dHalfH; i <= dHalfH; i++){
for(j = -dHalfW; j <= dHalfW; j++){
x = c + j;
y = r + i;
// condition to check if element is outside the image
if(x >= 0 && x < c1 && y >= 0 && y < r1){
acc = acc + (dMask[maskIndex] * in[ y*c1 + x ]);
}
maskIndex++;
}
}
// condition to check if element is outside image
if(r < r1 && c < c1){
out[ r*c1 + c ] = acc;
}
}
int main(int argc, char **argv) {
float *hInput;
float *hMask;
float *hOutput;
float *dInput;
float *dOutput;
int r1,c1,r2,c2, R, C;
FILE *fptr;
if(argc < 2) { printf(" Please specify input filename\n"); return -1;}
// Finding dimensions of input matricex
count_rc(argv[1],&r1, &c1, &r2, &c2);
if(r1 == 0) return -1;
// conputing dimensions of output matrix
R = (r1 + r2) -1;
C = (c1 + c2) -1;
// allocating input matrices
hInput = alloc2D(R, C);
// zeroing the input matrix
memset(hInput, 0, sizeof(float)*R*C);
// allocation mask
hMask = alloc2D(10, 10);
// allocating output matix
hOutput = alloc2D(R, C);
// opening input file
fptr = fopen(argv[1], "rb");
// parsing first matrix withing the padded region defined as c2/2 and r2/2
parse2DPadded(fptr, hInput, r1, c1, c2/2, r2/2);
// parsing mask
parse2D(fptr, hMask, r2, c2);
// closing the file
fclose(fptr);
// flipping kernel vertically and horizontally
flip_kernel(hMask, r2, c2);
// print2D(hMask, r2, c2);
r2 = r2/2;
c2 = c2/2;
// allocating gpu memory
CUDA_CALL(cudaMalloc((void**)&dInput, R*C*sizeof(float)));
//err = cudaMalloc((void**)&dMask, r2*c2*sizeof(float));
CUDA_CALL(cudaMalloc((void**)&dOutput, R*C*sizeof(float)));
// Copy memory to the GPU
CUDA_CALL(cudaMemcpy(dInput, hInput, sizeof(float)*R*C, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dMask, hMask, sizeof(float)*10*10, 0, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dHalfW, (const int*)&r2, sizeof(int), 0, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dHalfH, (const int*)&c2, sizeof(int), 0, cudaMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 numThreads(ThreadsPerBlockX,ThreadsPerBlockY,1);
dim3 numBlocks( ((C-1)/ThreadsPerBlockX)+1, ((R-1)/ThreadsPerBlockY)+1, 1 );
// Launch the GPU Kernel
conv2DKernel<<<numBlocks, numThreads>>>(dInput, dOutput, R, C);
//cudaDeviceSynchronize();
CUDA_CALL(cudaThreadSynchronize());
// Copy the GPU memory back to the CPU
CUDA_CALL(cudaMemcpy(hOutput, dOutput, R*C*sizeof(float), cudaMemcpyDeviceToHost));
// free the GPU memory
CUDA_CALL(cudaFree(dInput));
CUDA_CALL(cudaFree(dOutput));
// printing result
print2D(hOutput, R, C);
// free the host memory
free2D(hInput);
free2D(hMask);
free2D(hOutput);
return 0;
}
// count number of rows and columns for the given input file
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2)
{
*r1 = 0; *c1 = 0; *r2 = 0; *c2 =0;
char *buff = (char*)malloc(BUF_SIZE);
FILE *f = fopen(fname, "rb");
if(f == NULL){ printf("Unable to open file %s\n",fname); free(buff); return; }
fgets(buff, BUF_SIZE, f);
*c1 = count_cols(buff);
while(strlen(buff) > 1){
(*r1)++;
fgets(buff, BUF_SIZE, f);
}
fgets(buff, BUF_SIZE, f);
*c2 = count_cols(buff);
while(strlen(buff) > 1){
(*r2)++;
if(NULL == fgets(buff, BUF_SIZE, f)) break;
if((feof(f)) && (strlen(buff) > 1) ){(*r2)++; break;}
}
free(buff);
fclose(f);
}
// count number of columns in given buffer
int count_cols(char *buff)
{
int i;int n=1;
for(i=0; i<strlen(buff)-1; i++)
{
if(buff[i] == ' '){
if(buff[i+1] != '\n' && buff[i+1] != '\r' && buff[i+1] != ' '){
n++;
}
}
}
return n;
}
// print a 2D matrix
void print2D(float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
if(j>0) printf(" ");
printf("%f",arr[ i*r + j]);
}
printf("\n");
}
}
// allocate memory for matrix of size rxc
float* alloc2D(int r, int c)
{
return (float*)malloc( r*c*sizeof(float) );
}
// free memory
void free2D(float *arr)
{
free(arr);
}
// parsing a matrix of size rxc
void parse2D(FILE *f, float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ (i*c) + j] );
}
}
}
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py)
{
int i,j;
int wStep = c + 2*px;
int offset = py*wStep + px;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ offset + (i*wStep) + j] );
}
}
}
void flip_kernel(float * arr, int r, int c)
{
float f;
int i,j;
int R = r-1;
int C = c-1;
for(i=0; i<=r/2; i++){
for(j=0; j<c; j++){
f = arr[i*c +j];
arr[i*c +j] = arr[(R-i)*c + (C-j)];
arr[(R-i)*c + (C-j)] = f;
}
}
} | .file "tmpxft_00178a3b_00000000-6_2d_convolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10count_colsPc
.type _Z10count_colsPc, @function
_Z10count_colsPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rax
leaq -1(%rbx,%rdx), %rdx
movl $1, %esi
movabsq $4294976512, %rdi
jmp .L4
.L6:
addl $1, %esi
.L5:
addq $1, %rax
.L4:
cmpq %rdx, %rax
je .L9
cmpb $32, (%rax)
jne .L5
movzbl 1(%rax), %ecx
cmpb $32, %cl
ja .L6
btq %rcx, %rdi
jc .L5
jmp .L6
.L9:
movl %esi, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10count_colsPc, .-_Z10count_colsPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Unable to open file %s\n"
.text
.globl _Z8count_rcPcPiS0_S0_S0_
.type _Z8count_rcPcPiS0_S0_S0_, @function
_Z8count_rcPcPiS0_S0_S0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rdi, 8(%rsp)
movq %rsi, %r13
movq %rdx, %r15
movq %rcx, %r12
movq %r8, %r14
movl $0, (%rsi)
movl $0, (%rdx)
movl $0, (%rcx)
movl $0, (%r8)
movl $200000, %edi
call malloc@PLT
movq %rax, %rbx
leaq .LC0(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %rbp
movq %rax, %rcx
movl $200000, %edx
movl $200000, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rdi
call _Z10count_colsPc
movl %eax, (%r15)
jmp .L13
.L20:
movq 8(%rsp), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
jmp .L10
.L14:
addl $1, 0(%r13)
movq %rbp, %rcx
movl $200000, %edx
movl $200000, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
.L13:
movq %rbx, %rdi
call strlen@PLT
cmpq $1, %rax
ja .L14
movq %rbp, %rcx
movl $200000, %edx
movl $200000, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
movq %rbx, %rdi
call _Z10count_colsPc
movl %eax, (%r14)
.L18:
movq %rbx, %rdi
call strlen@PLT
cmpq $1, %rax
jbe .L16
addl $1, (%r12)
movq %rbp, %rcx
movl $200000, %edx
movl $200000, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L16
movq %rbp, %rdi
call feof@PLT
testl %eax, %eax
je .L18
movq %rbx, %rdi
call strlen@PLT
cmpq $1, %rax
jbe .L18
addl $1, (%r12)
.L16:
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call fclose@PLT
.L10:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8count_rcPcPiS0_S0_S0_, .-_Z8count_rcPcPiS0_S0_S0_
.section .rodata.str1.1
.LC2:
.string " "
.LC3:
.string "%f"
.LC4:
.string "\n"
.text
.globl _Z7print2DPfii
.type _Z7print2DPfii, @function
_Z7print2DPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 24(%rsp)
movl %esi, 16(%rsp)
movl %edx, 20(%rsp)
testl %esi, %esi
jle .L21
movl $0, 12(%rsp)
movl $0, %r15d
movslq %edx, %r13
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r12
jmp .L23
.L24:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
je .L27
.L25:
testl %ebx, %ebx
jle .L24
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L27:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
movl 16(%rsp), %ecx
addl %ecx, 12(%rsp)
cmpl %r15d, %ecx
je .L21
.L23:
cmpl $0, 20(%rsp)
jle .L27
movslq 12(%rsp), %rax
movq 24(%rsp), %rdx
leaq (%rdx,%rax,4), %rbp
movl $0, %ebx
jmp .L25
.L21:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z7print2DPfii, .-_Z7print2DPfii
.globl _Z7alloc2Dii
.type _Z7alloc2Dii, @function
_Z7alloc2Dii:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
imull %esi, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z7alloc2Dii, .-_Z7alloc2Dii
.globl _Z6free2DPf
.type _Z6free2DPf, @function
_Z6free2DPf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z6free2DPf, .-_Z6free2DPf
.globl _Z7parse2DP8_IO_FILEPfii
.type _Z7parse2DP8_IO_FILEPfii, @function
_Z7parse2DP8_IO_FILEPfii:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
testl %edx, %edx
jle .L34
movq %rdi, %r12
movl %ecx, %r14d
movl $0, (%rsp)
movl $0, %r15d
leaq .LC3(%rip), %r13
jmp .L36
.L38:
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L37:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L37
.L39:
addl $1, %r15d
addl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L34
.L36:
testl %r14d, %r14d
jg .L38
jmp .L39
.L34:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z7parse2DP8_IO_FILEPfii, .-_Z7parse2DP8_IO_FILEPfii
.globl _Z13parse2DPaddedP8_IO_FILEPfiiii
.type _Z13parse2DPaddedP8_IO_FILEPfiiii, @function
_Z13parse2DPaddedP8_IO_FILEPfiiii:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 12(%rsp)
leal (%rcx,%r8,2), %eax
movl %eax, 16(%rsp)
imull %eax, %r9d
leal (%r9,%r8), %r14d
testl %edx, %edx
jle .L42
movq %rdi, %r12
movl $0, %r15d
leaq .LC3(%rip), %r13
jmp .L44
.L46:
movslq %r14d, %rdx
movq 24(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq 12(%rsp), %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L45:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L45
.L47:
addl $1, %r15d
movl 16(%rsp), %eax
addl %eax, %r14d
cmpl %r15d, 20(%rsp)
je .L42
.L44:
cmpl $0, 12(%rsp)
jg .L46
jmp .L47
.L42:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z13parse2DPaddedP8_IO_FILEPfiiii, .-_Z13parse2DPaddedP8_IO_FILEPfiiii
.globl _Z11flip_kernelPfii
.type _Z11flip_kernelPfii, @function
_Z11flip_kernelPfii:
.LFB2065:
.cfi_startproc
endbr64
movl %esi, %r11d
shrl $31, %r11d
addl %esi, %r11d
sarl %r11d
cmpl $-1, %esi
jl .L58
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r10
movl %edx, %edi
leal -1(%rsi), %esi
leal -1(%rdx), %ebx
imull %edx, %esi
movl $0, %r9d
movl $0, %r8d
movslq %ebx, %rbx
leaq -4(%r10), %rbp
jmp .L52
.L54:
movslq %r9d, %rax
leaq (%r10,%rax,4), %rdx
movslq %esi, %rcx
leaq (%rbx,%rcx), %rax
leaq (%r10,%rax,4), %rax
leaq 0(%rbp,%rcx,4), %rcx
.L53:
movss (%rdx), %xmm0
movss (%rax), %xmm1
movss %xmm1, (%rdx)
movss %xmm0, (%rax)
addq $4, %rdx
subq $4, %rax
cmpq %rcx, %rax
jne .L53
.L55:
addl $1, %r8d
addl %edi, %r9d
subl %edi, %esi
cmpl %r11d, %r8d
jg .L50
.L52:
testl %edi, %edi
jg .L54
jmp .L55
.L50:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2065:
.size _Z11flip_kernelPfii, .-_Z11flip_kernelPfii
.globl _Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii
.type _Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii, @function
_Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12conv2DKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii, .-_Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii
.globl _Z12conv2DKernelPfS_ii
.type _Z12conv2DKernelPfS_ii, @function
_Z12conv2DKernelPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12conv2DKernelPfS_ii, .-_Z12conv2DKernelPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " Please specify input filename\n"
.section .rodata.str1.1
.LC6:
.string "Call Failed at %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, 24(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L86
leaq 56(%rsp), %rcx
leaq 52(%rsp), %rdx
leaq 48(%rsp), %rsi
movq 24(%rsp), %rax
movq 8(%rax), %rdi
leaq 60(%rsp), %r8
call _Z8count_rcPcPiS0_S0_S0_
movl 48(%rsp), %r15d
testl %r15d, %r15d
je .L84
movl %r15d, %ebp
addl 56(%rsp), %ebp
leal -1(%rbp), %r13d
movl 52(%rsp), %eax
movl %eax, 44(%rsp)
movl %eax, %r12d
addl 60(%rsp), %r12d
leal -1(%r12), %r14d
movl %r14d, %esi
movl %r13d, %edi
call _Z7alloc2Dii
movq %rax, %rdi
movslq %r13d, %rbx
movslq %r14d, %rax
imulq %rax, %rbx
salq $2, %rbx
movq %rbx, %rdx
movl $0, %esi
movq %rdi, 16(%rsp)
call memset@PLT
movl $10, %esi
movl $10, %edi
call _Z7alloc2Dii
movq %rax, 8(%rsp)
movl %r14d, %esi
movl %r13d, %edi
call _Z7alloc2Dii
movq %rax, 32(%rsp)
movq 24(%rsp), %rdx
movq 8(%rdx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r10
movl 56(%rsp), %eax
movl %eax, %r9d
shrl $31, %r9d
addl %eax, %r9d
movl 60(%rsp), %eax
movl %eax, %r8d
shrl $31, %r8d
addl %eax, %r8d
sarl %r9d
sarl %r8d
movl 44(%rsp), %ecx
movl %r15d, %edx
movq 16(%rsp), %rsi
movq %r10, %r15
movq %r10, %rdi
call _Z13parse2DPaddedP8_IO_FILEPfiiii
movl 60(%rsp), %ecx
movl 56(%rsp), %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call _Z7parse2DP8_IO_FILEPfii
movq %r15, %rdi
call fclose@PLT
movl 60(%rsp), %ecx
movl 56(%rsp), %r15d
movl %ecx, 24(%rsp)
movl %ecx, %edx
movl %r15d, %esi
movq 8(%rsp), %rdi
call _Z11flip_kernelPfii
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
movl %eax, 56(%rsp)
movl 24(%rsp), %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
movl %eax, 60(%rsp)
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
.L72:
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L88
.L73:
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L89
.L74:
movl $1, %r8d
movl $0, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
leaq _ZL5dMask(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L90
.L75:
leaq 56(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6dHalfW(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L91
.L76:
leaq 60(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6dHalfH(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L92
.L77:
movl $8, 80(%rsp)
movl $8, 84(%rsp)
leal 5(%r12), %eax
subl $2, %r12d
cmovs %eax, %r12d
sarl $3, %r12d
addl $1, %r12d
movl %r12d, 92(%rsp)
leal 5(%rbp), %eax
subl $2, %ebp
cmovs %eax, %ebp
sarl $3, %ebp
addl $1, %ebp
movl %ebp, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L78:
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L94
.L79:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L95
.L80:
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L96
.L81:
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L97
.L82:
movl %r14d, %edx
movl %r13d, %esi
movq 32(%rsp), %rbx
movq %rbx, %rdi
call _Z7print2DPfii
movq 16(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L69:
movq 104(%rsp), %rdx
subq %fs:40, %rdx
jne .L98
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L69
.L87:
movl $114, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.L88:
movl $116, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L73
.L89:
movl $119, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L74
.L90:
movl $120, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L75
.L91:
movl $121, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L76
.L92:
movl $122, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L77
.L93:
movl %r14d, %ecx
movl %r13d, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z36__device_stub__Z12conv2DKernelPfS_iiPfS_ii
jmp .L78
.L94:
movl $132, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L79
.L95:
movl $135, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L96:
movl $138, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L81
.L97:
movl $139, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L82
.L84:
movl $-1, %eax
jmp .L69
.L98:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12conv2DKernelPfS_ii"
.LC8:
.string "dMask"
.LC9:
.string "dHalfW"
.LC10:
.string "dHalfH"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12conv2DKernelPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5dMask(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6dHalfW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6dHalfH(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6dHalfH
.comm _ZL6dHalfH,4,4
.local _ZL6dHalfW
.comm _ZL6dHalfW,4,4
.local _ZL5dMask
.comm _ZL5dMask,400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Prashant Solanki (Unity: psolank)
* Simple Image convolutions implementation without tiling
* Convolutions mask is stored in constant memory
* Tested with CUDA Toolkit 3.0
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#include <cuda.h>
#define BUF_SIZE 200000
#define ThreadsPerBlockX 8
#define ThreadsPerBlockY 8
#define CUDA_CALL(X) if(cudaSuccess != X) printf("Call Failed at %s\n",__LINE__);
int count_cols(char *buff);
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2);
void print2D(float *arr, int r, int c);
float* alloc2D(int r, int c);
void free2D(float *arr);
void parse2D(FILE *f, float *arr, int r, int c);
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py);
void flip_kernel(float * arr, int r, int c);
// Constant cache memory to store convolution mask and its size
__constant__ float dMask[100];
__constant__ int dHalfW;
__constant__ int dHalfH;
// kernel to convolve image with mask
// one thread processes one pixel in input image
__global__ void conv2DKernel(float *in, float *out, int r1, int c1) {
int i,j; int x,y;
int maskIndex = 0;
// computing row and column of pixel for which convolution os to be done
int r = blockIdx.y*blockDim.y + threadIdx.y;
int c = blockIdx.x*blockDim.x + threadIdx.x;
float acc = 0.0f;
// accessing neighbouring pixels and multiplying with mask
for(i = -dHalfH; i <= dHalfH; i++){
for(j = -dHalfW; j <= dHalfW; j++){
x = c + j;
y = r + i;
// condition to check if element is outside the image
if(x >= 0 && x < c1 && y >= 0 && y < r1){
acc = acc + (dMask[maskIndex] * in[ y*c1 + x ]);
}
maskIndex++;
}
}
// condition to check if element is outside image
if(r < r1 && c < c1){
out[ r*c1 + c ] = acc;
}
}
int main(int argc, char **argv) {
float *hInput;
float *hMask;
float *hOutput;
float *dInput;
float *dOutput;
int r1,c1,r2,c2, R, C;
FILE *fptr;
if(argc < 2) { printf(" Please specify input filename\n"); return -1;}
// Finding dimensions of input matricex
count_rc(argv[1],&r1, &c1, &r2, &c2);
if(r1 == 0) return -1;
// conputing dimensions of output matrix
R = (r1 + r2) -1;
C = (c1 + c2) -1;
// allocating input matrices
hInput = alloc2D(R, C);
// zeroing the input matrix
memset(hInput, 0, sizeof(float)*R*C);
// allocation mask
hMask = alloc2D(10, 10);
// allocating output matix
hOutput = alloc2D(R, C);
// opening input file
fptr = fopen(argv[1], "rb");
// parsing first matrix withing the padded region defined as c2/2 and r2/2
parse2DPadded(fptr, hInput, r1, c1, c2/2, r2/2);
// parsing mask
parse2D(fptr, hMask, r2, c2);
// closing the file
fclose(fptr);
// flipping kernel vertically and horizontally
flip_kernel(hMask, r2, c2);
// print2D(hMask, r2, c2);
r2 = r2/2;
c2 = c2/2;
// allocating gpu memory
CUDA_CALL(cudaMalloc((void**)&dInput, R*C*sizeof(float)));
//err = cudaMalloc((void**)&dMask, r2*c2*sizeof(float));
CUDA_CALL(cudaMalloc((void**)&dOutput, R*C*sizeof(float)));
// Copy memory to the GPU
CUDA_CALL(cudaMemcpy(dInput, hInput, sizeof(float)*R*C, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dMask, hMask, sizeof(float)*10*10, 0, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dHalfW, (const int*)&r2, sizeof(int), 0, cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpyToSymbol(dHalfH, (const int*)&c2, sizeof(int), 0, cudaMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 numThreads(ThreadsPerBlockX,ThreadsPerBlockY,1);
dim3 numBlocks( ((C-1)/ThreadsPerBlockX)+1, ((R-1)/ThreadsPerBlockY)+1, 1 );
// Launch the GPU Kernel
conv2DKernel<<<numBlocks, numThreads>>>(dInput, dOutput, R, C);
//cudaDeviceSynchronize();
CUDA_CALL(cudaThreadSynchronize());
// Copy the GPU memory back to the CPU
CUDA_CALL(cudaMemcpy(hOutput, dOutput, R*C*sizeof(float), cudaMemcpyDeviceToHost));
// free the GPU memory
CUDA_CALL(cudaFree(dInput));
CUDA_CALL(cudaFree(dOutput));
// printing result
print2D(hOutput, R, C);
// free the host memory
free2D(hInput);
free2D(hMask);
free2D(hOutput);
return 0;
}
// count number of rows and columns for the given input file
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2)
{
*r1 = 0; *c1 = 0; *r2 = 0; *c2 =0;
char *buff = (char*)malloc(BUF_SIZE);
FILE *f = fopen(fname, "rb");
if(f == NULL){ printf("Unable to open file %s\n",fname); free(buff); return; }
fgets(buff, BUF_SIZE, f);
*c1 = count_cols(buff);
while(strlen(buff) > 1){
(*r1)++;
fgets(buff, BUF_SIZE, f);
}
fgets(buff, BUF_SIZE, f);
*c2 = count_cols(buff);
while(strlen(buff) > 1){
(*r2)++;
if(NULL == fgets(buff, BUF_SIZE, f)) break;
if((feof(f)) && (strlen(buff) > 1) ){(*r2)++; break;}
}
free(buff);
fclose(f);
}
// count number of columns in given buffer
int count_cols(char *buff)
{
int i;int n=1;
for(i=0; i<strlen(buff)-1; i++)
{
if(buff[i] == ' '){
if(buff[i+1] != '\n' && buff[i+1] != '\r' && buff[i+1] != ' '){
n++;
}
}
}
return n;
}
// print a 2D matrix
void print2D(float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
if(j>0) printf(" ");
printf("%f",arr[ i*r + j]);
}
printf("\n");
}
}
// allocate memory for matrix of size rxc
float* alloc2D(int r, int c)
{
return (float*)malloc( r*c*sizeof(float) );
}
// free memory
void free2D(float *arr)
{
free(arr);
}
// parsing a matrix of size rxc
void parse2D(FILE *f, float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ (i*c) + j] );
}
}
}
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py)
{
int i,j;
int wStep = c + 2*px;
int offset = py*wStep + px;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ offset + (i*wStep) + j] );
}
}
}
void flip_kernel(float * arr, int r, int c)
{
float f;
int i,j;
int R = r-1;
int C = c-1;
for(i=0; i<=r/2; i++){
for(j=0; j<c; j++){
f = arr[i*c +j];
arr[i*c +j] = arr[(R-i)*c + (C-j)];
arr[(R-i)*c + (C-j)] = f;
}
}
} | /*
* Prashant Solanki (Unity: psolank)
* Simple Image convolutions implementation without tiling
* Convolutions mask is stored in constant memory
* Tested with CUDA Toolkit 3.0
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#include <cuda.h>
#define BUF_SIZE 200000
#define ThreadsPerBlockX 8
#define ThreadsPerBlockY 8
#define CUDA_CALL(X) if(hipSuccess != X) printf("Call Failed at %s\n",__LINE__);
int count_cols(char *buff);
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2);
void print2D(float *arr, int r, int c);
float* alloc2D(int r, int c);
void free2D(float *arr);
void parse2D(FILE *f, float *arr, int r, int c);
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py);
void flip_kernel(float * arr, int r, int c);
// Constant cache memory to store convolution mask and its size
__constant__ float dMask[100];
__constant__ int dHalfW;
__constant__ int dHalfH;
// kernel to convolve image with mask
// one thread processes one pixel in input image
__global__ void conv2DKernel(float *in, float *out, int r1, int c1) {
int i,j; int x,y;
int maskIndex = 0;
// computing row and column of pixel for which convolution os to be done
int r = blockIdx.y*blockDim.y + threadIdx.y;
int c = blockIdx.x*blockDim.x + threadIdx.x;
float acc = 0.0f;
// accessing neighbouring pixels and multiplying with mask
for(i = -dHalfH; i <= dHalfH; i++){
for(j = -dHalfW; j <= dHalfW; j++){
x = c + j;
y = r + i;
// condition to check if element is outside the image
if(x >= 0 && x < c1 && y >= 0 && y < r1){
acc = acc + (dMask[maskIndex] * in[ y*c1 + x ]);
}
maskIndex++;
}
}
// condition to check if element is outside image
if(r < r1 && c < c1){
out[ r*c1 + c ] = acc;
}
}
int main(int argc, char **argv) {
float *hInput;
float *hMask;
float *hOutput;
float *dInput;
float *dOutput;
int r1,c1,r2,c2, R, C;
FILE *fptr;
if(argc < 2) { printf(" Please specify input filename\n"); return -1;}
// Finding dimensions of input matricex
count_rc(argv[1],&r1, &c1, &r2, &c2);
if(r1 == 0) return -1;
// conputing dimensions of output matrix
R = (r1 + r2) -1;
C = (c1 + c2) -1;
// allocating input matrices
hInput = alloc2D(R, C);
// zeroing the input matrix
memset(hInput, 0, sizeof(float)*R*C);
// allocation mask
hMask = alloc2D(10, 10);
// allocating output matix
hOutput = alloc2D(R, C);
// opening input file
fptr = fopen(argv[1], "rb");
// parsing first matrix withing the padded region defined as c2/2 and r2/2
parse2DPadded(fptr, hInput, r1, c1, c2/2, r2/2);
// parsing mask
parse2D(fptr, hMask, r2, c2);
// closing the file
fclose(fptr);
// flipping kernel vertically and horizontally
flip_kernel(hMask, r2, c2);
// print2D(hMask, r2, c2);
r2 = r2/2;
c2 = c2/2;
// allocating gpu memory
CUDA_CALL(hipMalloc((void**)&dInput, R*C*sizeof(float)));
//err = cudaMalloc((void**)&dMask, r2*c2*sizeof(float));
CUDA_CALL(hipMalloc((void**)&dOutput, R*C*sizeof(float)));
// Copy memory to the GPU
CUDA_CALL(hipMemcpy(dInput, hInput, sizeof(float)*R*C, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dMask), hMask, sizeof(float)*10*10, 0, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dHalfW), (const int*)&r2, sizeof(int), 0, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dHalfH), (const int*)&c2, sizeof(int), 0, hipMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 numThreads(ThreadsPerBlockX,ThreadsPerBlockY,1);
dim3 numBlocks( ((C-1)/ThreadsPerBlockX)+1, ((R-1)/ThreadsPerBlockY)+1, 1 );
// Launch the GPU Kernel
conv2DKernel<<<numBlocks, numThreads>>>(dInput, dOutput, R, C);
//cudaDeviceSynchronize();
CUDA_CALL(hipDeviceSynchronize());
// Copy the GPU memory back to the CPU
CUDA_CALL(hipMemcpy(hOutput, dOutput, R*C*sizeof(float), hipMemcpyDeviceToHost));
// free the GPU memory
CUDA_CALL(hipFree(dInput));
CUDA_CALL(hipFree(dOutput));
// printing result
print2D(hOutput, R, C);
// free the host memory
free2D(hInput);
free2D(hMask);
free2D(hOutput);
return 0;
}
// count number of rows and columns for the given input file
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2)
{
*r1 = 0; *c1 = 0; *r2 = 0; *c2 =0;
char *buff = (char*)malloc(BUF_SIZE);
FILE *f = fopen(fname, "rb");
if(f == NULL){ printf("Unable to open file %s\n",fname); free(buff); return; }
fgets(buff, BUF_SIZE, f);
*c1 = count_cols(buff);
while(strlen(buff) > 1){
(*r1)++;
fgets(buff, BUF_SIZE, f);
}
fgets(buff, BUF_SIZE, f);
*c2 = count_cols(buff);
while(strlen(buff) > 1){
(*r2)++;
if(NULL == fgets(buff, BUF_SIZE, f)) break;
if((feof(f)) && (strlen(buff) > 1) ){(*r2)++; break;}
}
free(buff);
fclose(f);
}
// count number of columns in given buffer
int count_cols(char *buff)
{
int i;int n=1;
for(i=0; i<strlen(buff)-1; i++)
{
if(buff[i] == ' '){
if(buff[i+1] != '\n' && buff[i+1] != '\r' && buff[i+1] != ' '){
n++;
}
}
}
return n;
}
// print a 2D matrix
void print2D(float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
if(j>0) printf(" ");
printf("%f",arr[ i*r + j]);
}
printf("\n");
}
}
// allocate memory for matrix of size rxc
float* alloc2D(int r, int c)
{
return (float*)malloc( r*c*sizeof(float) );
}
// free memory
void free2D(float *arr)
{
free(arr);
}
// parsing a matrix of size rxc
void parse2D(FILE *f, float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ (i*c) + j] );
}
}
}
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py)
{
int i,j;
int wStep = c + 2*px;
int offset = py*wStep + px;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ offset + (i*wStep) + j] );
}
}
}
void flip_kernel(float * arr, int r, int c)
{
float f;
int i,j;
int R = r-1;
int C = c-1;
for(i=0; i<=r/2; i++){
for(j=0; j<c; j++){
f = arr[i*c +j];
arr[i*c +j] = arr[(R-i)*c + (C-j)];
arr[(R-i)*c + (C-j)] = f;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Prashant Solanki (Unity: psolank)
* Simple Image convolutions implementation without tiling
* Convolutions mask is stored in constant memory
* Tested with CUDA Toolkit 3.0
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#include <cuda.h>
#define BUF_SIZE 200000
#define ThreadsPerBlockX 8
#define ThreadsPerBlockY 8
#define CUDA_CALL(X) if(hipSuccess != X) printf("Call Failed at %s\n",__LINE__);
int count_cols(char *buff);
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2);
void print2D(float *arr, int r, int c);
float* alloc2D(int r, int c);
void free2D(float *arr);
void parse2D(FILE *f, float *arr, int r, int c);
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py);
void flip_kernel(float * arr, int r, int c);
// Constant cache memory to store convolution mask and its size
__constant__ float dMask[100];
__constant__ int dHalfW;
__constant__ int dHalfH;
// kernel to convolve image with mask
// one thread processes one pixel in input image
__global__ void conv2DKernel(float *in, float *out, int r1, int c1) {
int i,j; int x,y;
int maskIndex = 0;
// computing row and column of pixel for which convolution os to be done
int r = blockIdx.y*blockDim.y + threadIdx.y;
int c = blockIdx.x*blockDim.x + threadIdx.x;
float acc = 0.0f;
// accessing neighbouring pixels and multiplying with mask
for(i = -dHalfH; i <= dHalfH; i++){
for(j = -dHalfW; j <= dHalfW; j++){
x = c + j;
y = r + i;
// condition to check if element is outside the image
if(x >= 0 && x < c1 && y >= 0 && y < r1){
acc = acc + (dMask[maskIndex] * in[ y*c1 + x ]);
}
maskIndex++;
}
}
// condition to check if element is outside image
if(r < r1 && c < c1){
out[ r*c1 + c ] = acc;
}
}
int main(int argc, char **argv) {
float *hInput;
float *hMask;
float *hOutput;
float *dInput;
float *dOutput;
int r1,c1,r2,c2, R, C;
FILE *fptr;
if(argc < 2) { printf(" Please specify input filename\n"); return -1;}
// Finding dimensions of input matricex
count_rc(argv[1],&r1, &c1, &r2, &c2);
if(r1 == 0) return -1;
// conputing dimensions of output matrix
R = (r1 + r2) -1;
C = (c1 + c2) -1;
// allocating input matrices
hInput = alloc2D(R, C);
// zeroing the input matrix
memset(hInput, 0, sizeof(float)*R*C);
// allocation mask
hMask = alloc2D(10, 10);
// allocating output matix
hOutput = alloc2D(R, C);
// opening input file
fptr = fopen(argv[1], "rb");
// parsing first matrix withing the padded region defined as c2/2 and r2/2
parse2DPadded(fptr, hInput, r1, c1, c2/2, r2/2);
// parsing mask
parse2D(fptr, hMask, r2, c2);
// closing the file
fclose(fptr);
// flipping kernel vertically and horizontally
flip_kernel(hMask, r2, c2);
// print2D(hMask, r2, c2);
r2 = r2/2;
c2 = c2/2;
// allocating gpu memory
CUDA_CALL(hipMalloc((void**)&dInput, R*C*sizeof(float)));
//err = cudaMalloc((void**)&dMask, r2*c2*sizeof(float));
CUDA_CALL(hipMalloc((void**)&dOutput, R*C*sizeof(float)));
// Copy memory to the GPU
CUDA_CALL(hipMemcpy(dInput, hInput, sizeof(float)*R*C, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dMask), hMask, sizeof(float)*10*10, 0, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dHalfW), (const int*)&r2, sizeof(int), 0, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dHalfH), (const int*)&c2, sizeof(int), 0, hipMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 numThreads(ThreadsPerBlockX,ThreadsPerBlockY,1);
dim3 numBlocks( ((C-1)/ThreadsPerBlockX)+1, ((R-1)/ThreadsPerBlockY)+1, 1 );
// Launch the GPU Kernel
conv2DKernel<<<numBlocks, numThreads>>>(dInput, dOutput, R, C);
//cudaDeviceSynchronize();
CUDA_CALL(hipDeviceSynchronize());
// Copy the GPU memory back to the CPU
CUDA_CALL(hipMemcpy(hOutput, dOutput, R*C*sizeof(float), hipMemcpyDeviceToHost));
// free the GPU memory
CUDA_CALL(hipFree(dInput));
CUDA_CALL(hipFree(dOutput));
// printing result
print2D(hOutput, R, C);
// free the host memory
free2D(hInput);
free2D(hMask);
free2D(hOutput);
return 0;
}
// count number of rows and columns for the given input file
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2)
{
*r1 = 0; *c1 = 0; *r2 = 0; *c2 =0;
char *buff = (char*)malloc(BUF_SIZE);
FILE *f = fopen(fname, "rb");
if(f == NULL){ printf("Unable to open file %s\n",fname); free(buff); return; }
fgets(buff, BUF_SIZE, f);
*c1 = count_cols(buff);
while(strlen(buff) > 1){
(*r1)++;
fgets(buff, BUF_SIZE, f);
}
fgets(buff, BUF_SIZE, f);
*c2 = count_cols(buff);
while(strlen(buff) > 1){
(*r2)++;
if(NULL == fgets(buff, BUF_SIZE, f)) break;
if((feof(f)) && (strlen(buff) > 1) ){(*r2)++; break;}
}
free(buff);
fclose(f);
}
// count number of columns in given buffer
int count_cols(char *buff)
{
int i;int n=1;
for(i=0; i<strlen(buff)-1; i++)
{
if(buff[i] == ' '){
if(buff[i+1] != '\n' && buff[i+1] != '\r' && buff[i+1] != ' '){
n++;
}
}
}
return n;
}
// print a 2D matrix
void print2D(float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
if(j>0) printf(" ");
printf("%f",arr[ i*r + j]);
}
printf("\n");
}
}
// allocate memory for matrix of size rxc
float* alloc2D(int r, int c)
{
return (float*)malloc( r*c*sizeof(float) );
}
// free memory
void free2D(float *arr)
{
free(arr);
}
// parsing a matrix of size rxc
void parse2D(FILE *f, float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ (i*c) + j] );
}
}
}
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py)
{
int i,j;
int wStep = c + 2*px;
int offset = py*wStep + px;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ offset + (i*wStep) + j] );
}
}
}
void flip_kernel(float * arr, int r, int c)
{
float f;
int i,j;
int R = r-1;
int C = c-1;
for(i=0; i<=r/2; i++){
for(j=0; j<c; j++){
f = arr[i*c +j];
arr[i*c +j] = arr[(R-i)*c + (C-j)];
arr[(R-i)*c + (C-j)] = f;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12conv2DKernelPfS_ii
.globl _Z12conv2DKernelPfS_ii
.p2align 8
.type _Z12conv2DKernelPfS_ii,@function
_Z12conv2DKernelPfS_ii:
s_load_b32 s6, s[0:1], 0x24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dHalfH@rel32@lo+4
s_addc_u32 s3, s3, dHalfH@rel32@hi+12
s_load_b32 s12, s[2:3], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_and_b32 s2, s6, 0xffff
v_add_nc_u32_e32 v1, s15, v1
s_mul_i32 s14, s14, s2
s_cmp_lt_i32 s12, 0
s_mov_b32 s6, 0
s_cbranch_scc1 .LBB0_10
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dHalfW@rel32@lo+4
s_addc_u32 s3, s3, dHalfW@rel32@hi+12
v_subrev_nc_u32_e32 v3, s12, v1
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[8:9], s[0:1], 0x0
v_add_nc_u32_e32 v4, s14, v0
s_sub_i32 s13, 0, s12
v_mov_b32_e32 v2, 0
v_mul_lo_u32 v3, s5, v3
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, -1
v_subrev_nc_u32_e32 v4, s2, v4
s_cselect_b32 s15, -1, 0
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s16, s2, 1
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_8
.LBB0_2:
v_add_nc_u32_e32 v5, s13, v1
s_ashr_i32 s7, s6, 31
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, dMask@rel32@lo+4
s_addc_u32 s11, s11, dMask@rel32@hi+12
s_lshl_b64 s[18:19], s[6:7], 2
s_mov_b32 s7, s16
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s4, v5
v_mov_b32_e32 v5, v4
s_add_u32 s10, s18, s10
s_addc_u32 s11, s19, s11
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s18
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s6, s6, 1
s_add_i32 s7, s7, -1
v_add_nc_u32_e32 v5, 1, v5
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_8
.LBB0_5:
s_mov_b32 s17, exec_lo
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_4
v_cmp_gt_i32_e64 s3, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s18, s3
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s3, s8, v6
v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
s_load_b32 s3, s[10:11], 0x0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s3, v6
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v3, s5, v3
s_add_i32 s2, s13, 1
s_cmp_lg_u32 s13, s12
s_cbranch_scc0 .LBB0_10
s_mov_b32 s13, s2
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccz .LBB0_2
s_branch .LBB0_8
.LBB0_10:
v_add_nc_u32_e32 v0, s14, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12conv2DKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12conv2DKernelPfS_ii, .Lfunc_end0-_Z12conv2DKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dMask
.type dMask,@object
.section .bss,"aw",@nobits
.globl dMask
.p2align 4, 0x0
dMask:
.zero 400
.size dMask, 400
.protected dHalfW
.type dHalfW,@object
.globl dHalfW
.p2align 2, 0x0
dHalfW:
.long 0
.size dHalfW, 4
.protected dHalfH
.type dHalfH,@object
.globl dHalfH
.p2align 2, 0x0
dHalfH:
.long 0
.size dHalfH, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dMask
.addrsig_sym dHalfW
.addrsig_sym dHalfH
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12conv2DKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z12conv2DKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Prashant Solanki (Unity: psolank)
* Simple Image convolutions implementation without tiling
* Convolutions mask is stored in constant memory
* Tested with CUDA Toolkit 3.0
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//#include <cuda.h>
#define BUF_SIZE 200000
#define ThreadsPerBlockX 8
#define ThreadsPerBlockY 8
#define CUDA_CALL(X) if(hipSuccess != X) printf("Call Failed at %s\n",__LINE__);
int count_cols(char *buff);
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2);
void print2D(float *arr, int r, int c);
float* alloc2D(int r, int c);
void free2D(float *arr);
void parse2D(FILE *f, float *arr, int r, int c);
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py);
void flip_kernel(float * arr, int r, int c);
// Constant cache memory to store convolution mask and its size
__constant__ float dMask[100];
__constant__ int dHalfW;
__constant__ int dHalfH;
// kernel to convolve image with mask
// one thread processes one pixel in input image
__global__ void conv2DKernel(float *in, float *out, int r1, int c1) {
int i,j; int x,y;
int maskIndex = 0;
// computing row and column of pixel for which convolution os to be done
int r = blockIdx.y*blockDim.y + threadIdx.y;
int c = blockIdx.x*blockDim.x + threadIdx.x;
float acc = 0.0f;
// accessing neighbouring pixels and multiplying with mask
for(i = -dHalfH; i <= dHalfH; i++){
for(j = -dHalfW; j <= dHalfW; j++){
x = c + j;
y = r + i;
// condition to check if element is outside the image
if(x >= 0 && x < c1 && y >= 0 && y < r1){
acc = acc + (dMask[maskIndex] * in[ y*c1 + x ]);
}
maskIndex++;
}
}
// condition to check if element is outside image
if(r < r1 && c < c1){
out[ r*c1 + c ] = acc;
}
}
int main(int argc, char **argv) {
float *hInput;
float *hMask;
float *hOutput;
float *dInput;
float *dOutput;
int r1,c1,r2,c2, R, C;
FILE *fptr;
if(argc < 2) { printf(" Please specify input filename\n"); return -1;}
// Finding dimensions of input matricex
count_rc(argv[1],&r1, &c1, &r2, &c2);
if(r1 == 0) return -1;
// conputing dimensions of output matrix
R = (r1 + r2) -1;
C = (c1 + c2) -1;
// allocating input matrices
hInput = alloc2D(R, C);
// zeroing the input matrix
memset(hInput, 0, sizeof(float)*R*C);
// allocation mask
hMask = alloc2D(10, 10);
// allocating output matix
hOutput = alloc2D(R, C);
// opening input file
fptr = fopen(argv[1], "rb");
// parsing first matrix withing the padded region defined as c2/2 and r2/2
parse2DPadded(fptr, hInput, r1, c1, c2/2, r2/2);
// parsing mask
parse2D(fptr, hMask, r2, c2);
// closing the file
fclose(fptr);
// flipping kernel vertically and horizontally
flip_kernel(hMask, r2, c2);
// print2D(hMask, r2, c2);
r2 = r2/2;
c2 = c2/2;
// allocating gpu memory
CUDA_CALL(hipMalloc((void**)&dInput, R*C*sizeof(float)));
//err = cudaMalloc((void**)&dMask, r2*c2*sizeof(float));
CUDA_CALL(hipMalloc((void**)&dOutput, R*C*sizeof(float)));
// Copy memory to the GPU
CUDA_CALL(hipMemcpy(dInput, hInput, sizeof(float)*R*C, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dMask), hMask, sizeof(float)*10*10, 0, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dHalfW), (const int*)&r2, sizeof(int), 0, hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpyToSymbol(HIP_SYMBOL(dHalfH), (const int*)&c2, sizeof(int), 0, hipMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 numThreads(ThreadsPerBlockX,ThreadsPerBlockY,1);
dim3 numBlocks( ((C-1)/ThreadsPerBlockX)+1, ((R-1)/ThreadsPerBlockY)+1, 1 );
// Launch the GPU Kernel
conv2DKernel<<<numBlocks, numThreads>>>(dInput, dOutput, R, C);
//cudaDeviceSynchronize();
CUDA_CALL(hipDeviceSynchronize());
// Copy the GPU memory back to the CPU
CUDA_CALL(hipMemcpy(hOutput, dOutput, R*C*sizeof(float), hipMemcpyDeviceToHost));
// free the GPU memory
CUDA_CALL(hipFree(dInput));
CUDA_CALL(hipFree(dOutput));
// printing result
print2D(hOutput, R, C);
// free the host memory
free2D(hInput);
free2D(hMask);
free2D(hOutput);
return 0;
}
// count number of rows and columns for the given input file
void count_rc(char *fname, int *r1, int *c1, int *r2, int *c2)
{
*r1 = 0; *c1 = 0; *r2 = 0; *c2 =0;
char *buff = (char*)malloc(BUF_SIZE);
FILE *f = fopen(fname, "rb");
if(f == NULL){ printf("Unable to open file %s\n",fname); free(buff); return; }
fgets(buff, BUF_SIZE, f);
*c1 = count_cols(buff);
while(strlen(buff) > 1){
(*r1)++;
fgets(buff, BUF_SIZE, f);
}
fgets(buff, BUF_SIZE, f);
*c2 = count_cols(buff);
while(strlen(buff) > 1){
(*r2)++;
if(NULL == fgets(buff, BUF_SIZE, f)) break;
if((feof(f)) && (strlen(buff) > 1) ){(*r2)++; break;}
}
free(buff);
fclose(f);
}
// count number of columns in given buffer
int count_cols(char *buff)
{
int i;int n=1;
for(i=0; i<strlen(buff)-1; i++)
{
if(buff[i] == ' '){
if(buff[i+1] != '\n' && buff[i+1] != '\r' && buff[i+1] != ' '){
n++;
}
}
}
return n;
}
// print a 2D matrix
void print2D(float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
if(j>0) printf(" ");
printf("%f",arr[ i*r + j]);
}
printf("\n");
}
}
// allocate memory for matrix of size rxc
float* alloc2D(int r, int c)
{
return (float*)malloc( r*c*sizeof(float) );
}
// free memory
void free2D(float *arr)
{
free(arr);
}
// parsing a matrix of size rxc
void parse2D(FILE *f, float *arr, int r, int c)
{
int i,j;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ (i*c) + j] );
}
}
}
void parse2DPadded(FILE *f, float *arr, int r, int c, int px, int py)
{
int i,j;
int wStep = c + 2*px;
int offset = py*wStep + px;
for(i=0; i<r; i++){
for(j=0; j<c; j++){
fscanf( f, "%f", &arr[ offset + (i*wStep) + j] );
}
}
}
void flip_kernel(float * arr, int r, int c)
{
float f;
int i,j;
int R = r-1;
int C = c-1;
for(i=0; i<=r/2; i++){
for(j=0; j<c; j++){
f = arr[i*c +j];
arr[i*c +j] = arr[(R-i)*c + (C-j)];
arr[(R-i)*c + (C-j)] = f;
}
}
} | .text
.file "2d_convolution.hip"
.globl _Z27__device_stub__conv2DKernelPfS_ii # -- Begin function _Z27__device_stub__conv2DKernelPfS_ii
.p2align 4, 0x90
.type _Z27__device_stub__conv2DKernelPfS_ii,@function
_Z27__device_stub__conv2DKernelPfS_ii: # @_Z27__device_stub__conv2DKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12conv2DKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__conv2DKernelPfS_ii, .Lfunc_end0-_Z27__device_stub__conv2DKernelPfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jg .LBB1_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB1_47
.LBB1_2:
movq %rsi, %rbp
movq 8(%rsi), %rdi
leaq 76(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 4(%rsp), %rcx
movq %rsp, %r8
callq _Z8count_rcPcPiS0_S0_S0_
movslq 76(%rsp), %r12
testq %r12, %r12
je .LBB1_47
# %bb.3:
movslq 4(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
leaq (%rax,%r12), %rbx
decq %rbx
movslq 72(%rsp), %rdx
movslq (%rsp), %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rdx, 96(%rsp) # 8-byte Spill
leaq (%rcx,%rdx), %r14
decq %r14
movl %r14d, %eax
imull %ebx, %eax
movslq %eax, %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rbx, 24(%rsp) # 8-byte Spill
movq %rbx, %rdx
movq %r14, 88(%rsp) # 8-byte Spill
imulq %r14, %rdx
shlq $2, %rdx
movq %rax, 48(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rdx, 112(%rsp) # 8-byte Spill
callq memset@PLT
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, 136(%rsp) # 8-byte Spill
movq %r15, 120(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq 8(%rbp), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
movq %r12, 104(%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB1_9
# %bb.4: # %.preheader.lr.ph.i
movq 96(%rsp), %rdx # 8-byte Reload
movl %edx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl (%rsp), %eax
movl %eax, %esi
shrl $31, %esi
addl %eax, %esi
movl %esi, %eax
sarl %eax
movl 4(%rsp), %ecx
movl %ecx, %r13d
shrl $31, %r13d
addl %ecx, %r13d
sarl %r13d
andl $-2, %esi
addl %edx, %esi
movl %esi, 40(%rsp) # 4-byte Spill
imull %esi, %r13d
addl %eax, %r13d
xorl %r15d, %r15d
movq 48(%rsp), %r14 # 8-byte Reload
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_5: # %._crit_edge.i
# in Loop: Header=BB1_6 Depth=1
incl %r15d
addl 40(%rsp), %r13d # 4-byte Folded Reload
cmpl 104(%rsp), %r15d # 4-byte Folded Reload
je .LBB1_9
.LBB1_6: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.7: # %.lr.ph.i
# in Loop: Header=BB1_6 Depth=1
movl %r13d, %ebx
movq 8(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_6 Depth=1
# => This Inner Loop Header: Depth=2
movslq %ebx, %rbx
leaq (%r14,%rbx,4), %rdx
movl $.L.str.5, %esi
movq %rbp, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
incl %ebx
decq %r12
jne .LBB1_8
jmp .LBB1_5
.LBB1_47:
movl $-1, %eax
jmp .LBB1_48
.LBB1_9: # %_Z13parse2DPaddedP8_IO_FILEPfiiii.exit
movl 4(%rsp), %eax
movq %rax, 40(%rsp) # 8-byte Spill
testl %eax, %eax
movq 136(%rsp), %r14 # 8-byte Reload
jle .LBB1_15
# %bb.10: # %.preheader.lr.ph.i54
movl (%rsp), %eax
xorl %r15d, %r15d
xorl %ebx, %ebx
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_11: # %._crit_edge.i56
# in Loop: Header=BB1_12 Depth=1
incq %rbx
movq 8(%rsp), %rax # 8-byte Reload
addl %eax, %r15d
cmpq 40(%rsp), %rbx # 8-byte Folded Reload
je .LBB1_15
.LBB1_12: # %.preheader.i55
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
testl %eax, %eax
jle .LBB1_11
# %bb.13: # %.lr.ph.i57
# in Loop: Header=BB1_12 Depth=1
movl %r15d, %eax
leaq (%r14,%rax,4), %r12
movq 8(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.5, %esi
movq %rbp, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
decq %r13
jne .LBB1_14
jmp .LBB1_11
.LBB1_15: # %_Z7parse2DP8_IO_FILEPfii.exit
movq %rbp, %rdi
callq fclose
movl 4(%rsp), %ecx
movslq (%rsp), %rax
cmpl $-1, %ecx
movq 120(%rsp), %r15 # 8-byte Reload
movq 104(%rsp), %r12 # 8-byte Reload
jge .LBB1_49
.LBB1_16: # %_Z11flip_kernelPfii.exit
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
movl %edx, 4(%rsp)
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl %ecx, (%rsp)
leaq 64(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
movq 48(%rsp), %rbx # 8-byte Reload
je .LBB1_18
# %bb.17:
movl $.L.str.2, %edi
movl $116, %esi
xorl %eax, %eax
callq printf
.LBB1_18:
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_20
# %bb.19:
movl $.L.str.2, %edi
movl $118, %esi
xorl %eax, %eax
callq printf
.LBB1_20:
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_22
# %bb.21:
movl $.L.str.2, %edi
movl $121, %esi
xorl %eax, %eax
callq printf
.LBB1_22:
movl $dMask, %edi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
movq 128(%rsp), %rbx # 8-byte Reload
je .LBB1_24
# %bb.23:
movl $.L.str.2, %edi
movl $122, %esi
xorl %eax, %eax
callq printf
.LBB1_24:
addq %r12, %rbx
movq 96(%rsp), %rax # 8-byte Reload
addq %rax, 32(%rsp) # 8-byte Folded Spill
leaq 4(%rsp), %rsi
movl $dHalfW, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
je .LBB1_26
# %bb.25:
movl $.L.str.2, %edi
movl $123, %esi
xorl %eax, %eax
callq printf
.LBB1_26:
movq %rsp, %rsi
movl $dHalfH, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
je .LBB1_28
# %bb.27:
movl $.L.str.2, %edi
movl $124, %esi
xorl %eax, %eax
callq printf
.LBB1_28:
movq 32(%rsp), %rcx # 8-byte Reload
leal -2(%rcx), %eax
addl $5, %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
incl %ecx
leal -2(%rbx), %eax
leal 5(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $3, %edi
incl %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_30
# %bb.29:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 84(%rsp)
movq 88(%rsp), %rax # 8-byte Reload
movl %eax, 80(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 84(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z12conv2DKernelPfS_ii, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_30:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_32
# %bb.31:
movl $.L.str.2, %edi
movl $134, %esi
xorl %eax, %eax
callq printf
.LBB1_32:
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_34
# %bb.33:
movl $.L.str.2, %edi
movl $137, %esi
xorl %eax, %eax
callq printf
.LBB1_34:
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_36
# %bb.35:
movl $.L.str.2, %edi
movl $140, %esi
xorl %eax, %eax
callq printf
.LBB1_36:
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB1_38
# %bb.37:
movl $.L.str.2, %edi
movl $141, %esi
xorl %eax, %eax
callq printf
.LBB1_38:
cmpl $2, %ebx
jl .LBB1_46
# %bb.39: # %.preheader.lr.ph.i70
movl 24(%rsp), %eax # 4-byte Reload
movq %rax, 8(%rsp) # 8-byte Spill
movl 88(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_41
.p2align 4, 0x90
.LBB1_40: # %._crit_edge.i72
# in Loop: Header=BB1_41 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl 24(%rsp), %r13d # 4-byte Folded Reload
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_46
.LBB1_41: # %.preheader.i71
# =>This Loop Header: Depth=1
# Child Loop BB1_44 Depth 2
cmpl $2, 32(%rsp) # 4-byte Folded Reload
jl .LBB1_40
# %bb.42: # %.lr.ph.i74
# in Loop: Header=BB1_41 Depth=1
movl %r13d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
jmp .LBB1_44
.p2align 4, 0x90
.LBB1_43: # in Loop: Header=BB1_44 Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
je .LBB1_40
.LBB1_44: # Parent Loop BB1_41 Depth=1
# => This Inner Loop Header: Depth=2
testq %r15, %r15
je .LBB1_43
# %bb.45: # in Loop: Header=BB1_44 Depth=2
movl $32, %edi
callq putchar@PLT
jmp .LBB1_43
.LBB1_46: # %_Z7print2DPfii.exit
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
.LBB1_48:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_49: # %.preheader.lr.ph.i62
.cfi_def_cfa_offset 304
movl %eax, %edx
movl %ecx, %esi
shrl $31, %esi
addl %ecx, %esi
sarl %esi
incl %esi
leaq (,%rax,4), %rdi
movl %ecx, %r8d
imull %edx, %r8d
decl %r8d
xorl %r9d, %r9d
movq %r14, %r10
jmp .LBB1_51
.p2align 4, 0x90
.LBB1_50: # %._crit_edge.i64
# in Loop: Header=BB1_51 Depth=1
incq %r9
addq %rdi, %r10
subl %edx, %r8d
cmpq %rsi, %r9
je .LBB1_16
.LBB1_51: # %.preheader.i63
# =>This Loop Header: Depth=1
# Child Loop BB1_53 Depth 2
testl %eax, %eax
jle .LBB1_50
# %bb.52: # %.lr.ph.i65
# in Loop: Header=BB1_51 Depth=1
movl %r8d, %r11d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_53: # Parent Loop BB1_51 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq %r11d, %r11
movss (%r14,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%r10,%rbx,4)
movss %xmm0, (%r14,%r11,4)
incq %rbx
decl %r11d
cmpq %rbx, %rdx
jne .LBB1_53
jmp .LBB1_50
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z8count_rcPcPiS0_S0_S0_ # -- Begin function _Z8count_rcPcPiS0_S0_S0_
.p2align 4, 0x90
.type _Z8count_rcPcPiS0_S0_S0_,@function
_Z8count_rcPcPiS0_S0_S0_: # @_Z8count_rcPcPiS0_S0_S0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r14
movq %rdx, %rbp
movq %rsi, %r13
movq %rdi, %r12
movl $0, (%rsi)
movl $0, (%rdx)
movl $0, (%rcx)
movq %r8, (%rsp) # 8-byte Spill
movl $0, (%r8)
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %rbx
movl $.L.str.1, %esi
movq %r12, %rdi
callq fopen
testq %rax, %rax
je .LBB2_24
# %bb.1:
movq %rax, %r15
movq %rbx, %rdi
movl $200000, %esi # imm = 0x30D40
movq %rax, %rdx
callq fgets
movq %rbx, %rdi
callq strlen
movabsq $4294976512, %r12 # imm = 0x100002400
movl $1, %ecx
cmpq $1, %rax
je .LBB2_8
# %bb.2: # %.lr.ph.i.preheader
movl $1, %edx
jmp .LBB2_3
.LBB2_6: # in Loop: Header=BB2_3 Depth=1
incl %ecx
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=1
incq %rdx
cmpq %rdx, %rax
je .LBB2_8
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpb $32, -1(%rbx,%rdx)
jne .LBB2_7
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movzbl (%rbx,%rdx), %esi
cmpq $32, %rsi
ja .LBB2_6
# %bb.5: # in Loop: Header=BB2_3 Depth=1
btq %rsi, %r12
jb .LBB2_7
jmp .LBB2_6
.LBB2_8: # %_Z10count_colsPc.exit
movl %ecx, (%rbp)
movq %rbx, %rdi
callq strlen
cmpq $2, %rax
jb .LBB2_10
.p2align 4, 0x90
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
incl (%r13)
movq %rbx, %rdi
movl $200000, %esi # imm = 0x30D40
movq %r15, %rdx
callq fgets
movq %rbx, %rdi
callq strlen
cmpq $1, %rax
ja .LBB2_9
.LBB2_10: # %._crit_edge
movq %rbx, %rdi
movl $200000, %esi # imm = 0x30D40
movq %r15, %rdx
callq fgets
movq %rbx, %rdi
callq strlen
movl $1, %ecx
cmpq $1, %rax
je .LBB2_17
# %bb.11: # %.lr.ph.i30.preheader
movl $1, %edx
jmp .LBB2_12
.LBB2_15: # in Loop: Header=BB2_12 Depth=1
incl %ecx
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_12 Depth=1
incq %rdx
cmpq %rdx, %rax
je .LBB2_17
.LBB2_12: # %.lr.ph.i30
# =>This Inner Loop Header: Depth=1
cmpb $32, -1(%rbx,%rdx)
jne .LBB2_16
# %bb.13: # in Loop: Header=BB2_12 Depth=1
movzbl (%rbx,%rdx), %esi
cmpq $32, %rsi
ja .LBB2_15
# %bb.14: # in Loop: Header=BB2_12 Depth=1
btq %rsi, %r12
jb .LBB2_16
jmp .LBB2_15
.LBB2_17: # %_Z10count_colsPc.exit37
movq (%rsp), %rax # 8-byte Reload
movl %ecx, (%rax)
movq %rbx, %rdi
callq strlen
cmpq $2, %rax
jae .LBB2_18
.LBB2_23: # %.loopexit
movq %rbx, %rdi
callq free
movq %r15, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_18 Depth=1
.cfi_def_cfa_offset 64
movq %rbx, %rdi
callq strlen
cmpq $1, %rax
jbe .LBB2_23
.LBB2_18: # %.lr.ph38
# =>This Inner Loop Header: Depth=1
incl (%r14)
movq %rbx, %rdi
movl $200000, %esi # imm = 0x30D40
movq %r15, %rdx
callq fgets
testq %rax, %rax
je .LBB2_23
# %bb.19: # in Loop: Header=BB2_18 Depth=1
movq %r15, %rdi
callq feof
testl %eax, %eax
je .LBB2_22
# %bb.20: # in Loop: Header=BB2_18 Depth=1
movq %rbx, %rdi
callq strlen
cmpq $2, %rax
jb .LBB2_22
# %bb.21:
incl (%r14)
jmp .LBB2_23
.LBB2_24:
movl $.L.str.3, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end2:
.size _Z8count_rcPcPiS0_S0_S0_, .Lfunc_end2-_Z8count_rcPcPiS0_S0_S0_
.cfi_endproc
# -- End function
.globl _Z7alloc2Dii # -- Begin function _Z7alloc2Dii
.p2align 4, 0x90
.type _Z7alloc2Dii,@function
_Z7alloc2Dii: # @_Z7alloc2Dii
.cfi_startproc
# %bb.0:
imull %esi, %edi
movslq %edi, %rdi
shlq $2, %rdi
jmp malloc # TAILCALL
.Lfunc_end3:
.size _Z7alloc2Dii, .Lfunc_end3-_Z7alloc2Dii
.cfi_endproc
# -- End function
.globl _Z13parse2DPaddedP8_IO_FILEPfiiii # -- Begin function _Z13parse2DPaddedP8_IO_FILEPfiiii
.p2align 4, 0x90
.type _Z13parse2DPaddedP8_IO_FILEPfiiii,@function
_Z13parse2DPaddedP8_IO_FILEPfiiii: # @_Z13parse2DPaddedP8_IO_FILEPfiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
# kill: def $ecx killed $ecx def $rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movl %edx, 4(%rsp) # 4-byte Spill
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %r9d, %ebx
movq %rsi, %r15
movq %rdi, %r12
movq 8(%rsp), %rax # 8-byte Reload
leal (%rax,%r8,2), %ecx
movl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ecx, (%rsp) # 4-byte Spill
imull %ecx, %ebx
addl %r8d, %ebx
xorl %r14d, %r14d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incl %r14d
addl (%rsp), %ebx # 4-byte Folded Reload
cmpl 4(%rsp), %r14d # 4-byte Folded Reload
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movq 16(%rsp), %rbp # 8-byte Reload
movl %ebx, %r13d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq %r13d, %r13
leaq (%r15,%r13,4), %rdx
movl $.L.str.5, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
incl %r13d
decq %rbp
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge19
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z13parse2DPaddedP8_IO_FILEPfiiii, .Lfunc_end4-_Z13parse2DPaddedP8_IO_FILEPfiiii
.cfi_endproc
# -- End function
.globl _Z7parse2DP8_IO_FILEPfii # -- Begin function _Z7parse2DP8_IO_FILEPfii
.p2align 4, 0x90
.type _Z7parse2DP8_IO_FILEPfii,@function
_Z7parse2DP8_IO_FILEPfii: # @_Z7parse2DP8_IO_FILEPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB5_6
# %bb.1: # %.preheader.lr.ph
movl %ecx, %ebx
movq %rdi, %r15
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ecx, %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebp, %ebp
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %rbp
addl %ebx, %r14d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB5_6
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
testl %ebx, %ebx
jle .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq (%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.5, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
decq %r13
jne .LBB5_4
jmp .LBB5_5
.LBB5_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z7parse2DP8_IO_FILEPfii, .Lfunc_end5-_Z7parse2DP8_IO_FILEPfii
.cfi_endproc
# -- End function
.globl _Z11flip_kernelPfii # -- Begin function _Z11flip_kernelPfii
.p2align 4, 0x90
.type _Z11flip_kernelPfii,@function
_Z11flip_kernelPfii: # @_Z11flip_kernelPfii
.cfi_startproc
# %bb.0:
cmpl $-1, %esi
jl .LBB6_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
movslq %edx, %rcx
incl %eax
movl %ecx, %r8d
shlq $2, %rcx
imull %edx, %esi
decl %esi
xorl %r9d, %r9d
movq %rdi, %r10
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %r9
addq %rcx, %r10
subl %edx, %esi
cmpq %rax, %r9
je .LBB6_6
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
testl %edx, %edx
jle .LBB6_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
movl %esi, %r11d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq %r11d, %r11
movss (%rdi,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm1, (%r10,%rbx,4)
movss %xmm0, (%rdi,%r11,4)
incq %rbx
decl %r11d
cmpq %rbx, %r8
jne .LBB6_4
jmp .LBB6_5
.LBB6_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB6_7: # %._crit_edge33
retq
.Lfunc_end6:
.size _Z11flip_kernelPfii, .Lfunc_end6-_Z11flip_kernelPfii
.cfi_endproc
# -- End function
.globl _Z7print2DPfii # -- Begin function _Z7print2DPfii
.p2align 4, 0x90
.type _Z7print2DPfii,@function
_Z7print2DPfii: # @_Z7print2DPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB7_8
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_7: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebp, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB7_8
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB7_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_6: # in Loop: Header=BB7_4 Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
je .LBB7_7
.LBB7_4: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
testq %r15, %r15
je .LBB7_6
# %bb.5: # in Loop: Header=BB7_4 Depth=2
movl $32, %edi
callq putchar@PLT
jmp .LBB7_6
.LBB7_8: # %._crit_edge15
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z7print2DPfii, .Lfunc_end7-_Z7print2DPfii
.cfi_endproc
# -- End function
.globl _Z6free2DPf # -- Begin function _Z6free2DPf
.p2align 4, 0x90
.type _Z6free2DPf,@function
_Z6free2DPf: # @_Z6free2DPf
.cfi_startproc
# %bb.0:
jmp free # TAILCALL
.Lfunc_end8:
.size _Z6free2DPf, .Lfunc_end8-_Z6free2DPf
.cfi_endproc
# -- End function
.globl _Z10count_colsPc # -- Begin function _Z10count_colsPc
.p2align 4, 0x90
.type _Z10count_colsPc,@function
_Z10count_colsPc: # @_Z10count_colsPc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq strlen
cmpq $1, %rax
je .LBB9_1
# %bb.2: # %.lr.ph.preheader
movq %rax, %rcx
movl $1, %eax
movl $1, %edx
movabsq $4294976512, %rsi # imm = 0x100002400
jmp .LBB9_3
.LBB9_6: # in Loop: Header=BB9_3 Depth=1
incl %eax
.p2align 4, 0x90
.LBB9_7: # in Loop: Header=BB9_3 Depth=1
incq %rdx
cmpq %rdx, %rcx
je .LBB9_8
.LBB9_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpb $32, -1(%rbx,%rdx)
jne .LBB9_7
# %bb.4: # in Loop: Header=BB9_3 Depth=1
movzbl (%rbx,%rdx), %edi
cmpq $32, %rdi
ja .LBB9_6
# %bb.5: # in Loop: Header=BB9_3 Depth=1
btq %rdi, %rsi
jb .LBB9_7
jmp .LBB9_6
.LBB9_8: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB9_1:
.cfi_def_cfa_offset 16
movl $1, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z10count_colsPc, .Lfunc_end9-_Z10count_colsPc
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12conv2DKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dMask, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $400, %r9d # imm = 0x190
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dHalfW, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $dHalfH, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type dMask,@object # @dMask
.local dMask
.comm dMask,400,16
.type dHalfW,@object # @dHalfW
.local dHalfW
.comm dHalfW,4,4
.type dHalfH,@object # @dHalfH
.local dHalfH
.comm dHalfH,4,4
.type _Z12conv2DKernelPfS_ii,@object # @_Z12conv2DKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z12conv2DKernelPfS_ii
.p2align 3, 0x0
_Z12conv2DKernelPfS_ii:
.quad _Z27__device_stub__conv2DKernelPfS_ii
.size _Z12conv2DKernelPfS_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "rb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Call Failed at %s\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Unable to open file %s\n"
.size .L.str.3, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f"
.size .L.str.5, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12conv2DKernelPfS_ii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dMask"
.size .L__unnamed_2, 6
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "dHalfW"
.size .L__unnamed_3, 7
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "dHalfH"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " Please specify input filename"
.size .Lstr, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__conv2DKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dMask
.addrsig_sym dHalfW
.addrsig_sym dHalfH
.addrsig_sym _Z12conv2DKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12conv2DKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV R4, RZ, RZ, -c[0x3][0x190] ; /* 0x80c06400ff047624 */
/* 0x000fe200078e02ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV R8, RZ, RZ, -c[0x3][0x194] ; /* 0x80c06500ff087624 */
/* 0x000fe200078e02ff */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.LE.AND P0, PT, R4, c[0x3][0x190], PT ; /* 0x00c0640004007a0c */
/* 0x000fe40003f03270 */
/*0070*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e640000002500 */
/*0080*/ ISETP.GT.OR P0, PT, R8, c[0x3][0x194], !P0 ; /* 0x00c0650008007a0c */
/* 0x000fc40004704670 */
/*0090*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*00a0*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x001fe400078e0200 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x002fcc00078e0203 */
/*00d0*/ @P0 BRA 0x780 ; /* 0x000006a000000947 */
/* 0x000fea0003800000 */
/*00e0*/ IMNMX R9, R4, c[0x3][0x190], !PT ; /* 0x00c0640004097a17 */
/* 0x000fe20007800200 */
/*00f0*/ ULDC UR4, c[0x3][0x190] ; /* 0x00c0640000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ IADD3 R7, R6.reuse, -c[0x3][0x190], RZ ; /* 0x80c0640006077a10 */
/* 0x040fe20007ffe0ff */
/*0110*/ UIADD3 UR5, -UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe13f */
/*0120*/ IADD3 R9, R9, c[0x3][0x190], RZ ; /* 0x00c0640009097a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ UIADD3 UR6, -UR4, 0x2, URZ ; /* 0x0000000204067890 */
/* 0x000fe2000fffe13f */
/*0140*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0150*/ UIADD3 UR4, -UR4, 0x3, URZ ; /* 0x0000000304047890 */
/* 0x000fe2000fffe13f */
/*0160*/ IADD3 R12, R9, 0x1, RZ ; /* 0x00000001090c7810 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R10, R6.reuse, UR5, RZ ; /* 0x00000005060a7c10 */
/* 0x040fe2000fffe0ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R11, R6, UR6, RZ ; /* 0x00000006060b7c10 */
/* 0x000fc4000fffe0ff */
/*01b0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fc800078ec0ff */
/*01c0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*01d0*/ IMAD.IADD R14, R5, 0x1, R8 ; /* 0x00000001050e7824 */
/* 0x000fe200078e0208 */
/*01e0*/ ISETP.GE.AND P4, PT, R8.reuse, c[0x3][0x194], PT ; /* 0x00c0650008007a0c */
/* 0x040fe20003f86270 */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0004 */
/*0200*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fd20007ffe0ff */
/*0210*/ @!P0 BRA 0x4b0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0220*/ LOP3.LUT R2, R7, R14, RZ, 0xfc, !PT ; /* 0x0000000e07027212 */
/* 0x000fe200078efcff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0240*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*0250*/ IMAD R2, R14, c[0x0][0x174], R7 ; /* 0x00005d000e027a24 */
/* 0x000fc600078e0207 */
/*0260*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x174], !P0 ; /* 0x00005d0007007a0c */
/* 0x000fe20004706670 */
/*0270*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0203 */
/*0280*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fda0000706670 */
/*0290*/ @!P0 LDG.E R18, [R2.64] ; /* 0x0000000802128981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IMAD.SHL.U32 R17, R16, 0x4, RZ ; /* 0x0000000410117824 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f25270 */
/*02c0*/ IADD3 R13, R16, 0x1, RZ ; /* 0x00000001100d7810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ @!P0 LDC R15, c[0x3][R17] ; /* 0x00c00000110f8b82 */
/* 0x000ea40000000800 */
/*02e0*/ @!P0 FFMA R0, R15, R18, R0 ; /* 0x000000120f008223 */
/* 0x004fe40000000000 */
/*02f0*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fcc000f8e00ff */
/*0300*/ @!P1 BRA 0x4b0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0310*/ LOP3.LUT R13, R10, R14, RZ, 0xfc, !PT ; /* 0x0000000e0a0d7212 */
/* 0x000fe200078efcff */
/*0320*/ BSSY B0, 0x3c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0330*/ ISETP.NE.AND P1, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f25270 */
/*0340*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*0350*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x174], !P0 ; /* 0x00005d000a007a0c */
/* 0x000fc80004706670 */
/*0360*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fda0000706670 */
/*0370*/ @P0 BRA 0x3b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000408020d7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ LDC R15, c[0x3][R17+0x4] ; /* 0x00c00100110f7b82 */
/* 0x000ea40000000800 */
/*03a0*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x004fcc0000000000 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ IADD3 R13, R16, 0x2, RZ ; /* 0x00000002100d7810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD.U32 R15, RZ, RZ, UR6 ; /* 0x00000006ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*03e0*/ @!P1 BRA 0x4b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT R13, R11, R14, RZ, 0xfc, !PT ; /* 0x0000000e0b0d7212 */
/* 0x000fe200078efcff */
/*0400*/ BSSY B0, 0x490 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*0420*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x174], !P0 ; /* 0x00005d000b007a0c */
/* 0x000fc80004706670 */
/*0430*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x000fda0000706670 */
/*0440*/ @P0 BRA 0x480 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000080802037981 */
/* 0x000ea2000c1e1900 */
/*0460*/ LDC R17, c[0x3][R17+0x8] ; /* 0x00c0020011117b82 */
/* 0x000ea40000000800 */
/*0470*/ FFMA R0, R3, R17, R0 ; /* 0x0000001103007223 */
/* 0x004fcc0000000000 */
/*0480*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0490*/ IADD3 R13, R16, 0x3, RZ ; /* 0x00000003100d7810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD.U32 R15, RZ, RZ, UR4 ; /* 0x00000004ff0f7e24 */
/* 0x000fe4000f8e00ff */
/*04b0*/ ISETP.GE.U32.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f06070 */
/*04c0*/ @!P0 BRA 0x760 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*04d0*/ IMAD.IADD R23, R6, 0x1, R15 ; /* 0x0000000106177824 */
/* 0x000fe200078e020f */
/*04e0*/ IADD3 R17, R15, 0x3, RZ ; /* 0x000000030f117810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ LOP3.LUT R2, R23.reuse, R14.reuse, RZ, 0xfc, !PT ; /* 0x0000000e17027212 */
/* 0x0c0fe200078efcff */
/*0500*/ IMAD.IADD R21, R6, 0x1, R17 ; /* 0x0000000106157824 */
/* 0x000fe200078e0211 */
/*0510*/ IADD3 R3, R23.reuse, 0x1, RZ ; /* 0x0000000117037810 */
/* 0x040fe40007ffe0ff */
/*0520*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*0530*/ IADD3 R19, R23, 0x2, RZ ; /* 0x0000000217137810 */
/* 0x000fe40007ffe0ff */
/*0540*/ LOP3.LUT R16, R3, R14, RZ, 0xfc, !PT ; /* 0x0000000e03107212 */
/* 0x000fe400078efcff */
/*0550*/ ISETP.GE.OR P1, PT, R23, c[0x0][0x174], !P1 ; /* 0x00005d0017007a0c */
/* 0x000fc40004f26670 */
/*0560*/ LOP3.LUT R2, R19, R14.reuse, RZ, 0xfc, !PT ; /* 0x0000000e13027212 */
/* 0x080fe400078efcff */
/*0570*/ ISETP.GE.AND P3, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f66270 */
/*0580*/ ISETP.GE.OR P1, PT, R14, c[0x0][0x170], P1 ; /* 0x00005c000e007a0c */
/* 0x000fe40000f26670 */
/*0590*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*05a0*/ IMAD R2, R14, c[0x0][0x174], R23 ; /* 0x00005d000e027a24 */
/* 0x000fe200078e0217 */
/*05b0*/ ISETP.GE.OR P3, PT, R3, c[0x0][0x174], !P3 ; /* 0x00005d0003007a0c */
/* 0x000fe20005f66670 */
/*05c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*05d0*/ LOP3.LUT R18, R21, R14, RZ, 0xfc, !PT ; /* 0x0000000e15127212 */
/* 0x000fc400078efcff */
/*05e0*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x174], !P0 ; /* 0x00005d0013007a0c */
/* 0x000fe20004706670 */
/*05f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0600*/ ISETP.GE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f46270 */
/*0610*/ ISETP.GE.OR P3, PT, R14.reuse, c[0x0][0x170], P3 ; /* 0x00005c000e007a0c */
/* 0x040fe40001f66670 */
/*0620*/ ISETP.GE.OR P2, PT, R21, c[0x0][0x174], !P2 ; /* 0x00005d0015007a0c */
/* 0x000fe20005746670 */
/*0630*/ @!P1 LDG.E R18, [R2.64] ; /* 0x0000000802129981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.GE.OR P0, PT, R14.reuse, c[0x0][0x170], P0 ; /* 0x00005c000e007a0c */
/* 0x040fe40000706670 */
/*0650*/ ISETP.GE.OR P2, PT, R14, c[0x0][0x170], P2 ; /* 0x00005c000e007a0c */
/* 0x000fce0001746670 */
/*0660*/ @!P3 LDG.E R21, [R2.64+0x4] ; /* 0x000004080215b981 */
/* 0x000ee8000c1e1900 */
/*0670*/ @!P0 LDG.E R23, [R2.64+0x8] ; /* 0x0000080802178981 */
/* 0x000f28000c1e1900 */
/*0680*/ @!P2 LDG.E R25, [R2.64+0xc] ; /* 0x00000c080219a981 */
/* 0x000f62000c1e1900 */
/*0690*/ IMAD.SHL.U32 R16, R13, 0x4, RZ ; /* 0x000000040d107824 */
/* 0x000fc800078e00ff */
/*06a0*/ @!P1 LDC R19, c[0x3][R16] ; /* 0x00c0000010139b82 */
/* 0x000eb00000000800 */
/*06b0*/ @!P3 LDC R20, c[0x3][R16+0x4] ; /* 0x00c001001014bb82 */
/* 0x000ef00000000800 */
/*06c0*/ @!P0 LDC R22, c[0x3][R16+0x8] ; /* 0x00c0020010168b82 */
/* 0x000f300000000800 */
/*06d0*/ @!P2 LDC R24, c[0x3][R16+0xc] ; /* 0x00c003001018ab82 */
/* 0x000f620000000800 */
/*06e0*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fc40007ffe0ff */
/*06f0*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe20007ffe0ff */
/*0700*/ @!P1 FFMA R0, R19, R18, R0 ; /* 0x0000001213009223 */
/* 0x004fe20000000000 */
/*0710*/ ISETP.GE.AND P1, PT, R17, c[0x3][0x190], PT ; /* 0x00c0640011007a0c */
/* 0x000fc60003f26270 */
/*0720*/ @!P3 FFMA R0, R21, R20, R0 ; /* 0x000000141500b223 */
/* 0x008fc80000000000 */
/*0730*/ @!P0 FFMA R0, R23, R22, R0 ; /* 0x0000001617008223 */
/* 0x010fc80000000000 */
/*0740*/ @!P2 FFMA R0, R25, R24, R0 ; /* 0x000000181900a223 */
/* 0x020fe40000000000 */
/*0750*/ @!P1 BRA 0x4d0 ; /* 0xfffffd7000009947 */
/* 0x000fea000383ffff */
/*0760*/ IMAD.MOV.U32 R16, RZ, RZ, R13 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000d */
/*0770*/ @!P4 BRA 0x1c0 ; /* 0xfffffa400000c947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fc80003f06270 */
/*0790*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*07a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*07c0*/ IMAD R2, R5, c[0x0][0x174], R6 ; /* 0x00005d0005027a24 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*07e0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101908 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12conv2DKernelPfS_ii
.globl _Z12conv2DKernelPfS_ii
.p2align 8
.type _Z12conv2DKernelPfS_ii,@function
_Z12conv2DKernelPfS_ii:
s_load_b32 s6, s[0:1], 0x24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dHalfH@rel32@lo+4
s_addc_u32 s3, s3, dHalfH@rel32@hi+12
s_load_b32 s12, s[2:3], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_and_b32 s2, s6, 0xffff
v_add_nc_u32_e32 v1, s15, v1
s_mul_i32 s14, s14, s2
s_cmp_lt_i32 s12, 0
s_mov_b32 s6, 0
s_cbranch_scc1 .LBB0_10
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, dHalfW@rel32@lo+4
s_addc_u32 s3, s3, dHalfW@rel32@hi+12
v_subrev_nc_u32_e32 v3, s12, v1
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[8:9], s[0:1], 0x0
v_add_nc_u32_e32 v4, s14, v0
s_sub_i32 s13, 0, s12
v_mov_b32_e32 v2, 0
v_mul_lo_u32 v3, s5, v3
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s2, -1
v_subrev_nc_u32_e32 v4, s2, v4
s_cselect_b32 s15, -1, 0
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s16, s2, 1
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_8
.LBB0_2:
v_add_nc_u32_e32 v5, s13, v1
s_ashr_i32 s7, s6, 31
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, dMask@rel32@lo+4
s_addc_u32 s11, s11, dMask@rel32@hi+12
s_lshl_b64 s[18:19], s[6:7], 2
s_mov_b32 s7, s16
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s4, v5
v_mov_b32_e32 v5, v4
s_add_u32 s10, s18, s10
s_addc_u32 s11, s19, s11
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s18
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s6, s6, 1
s_add_i32 s7, s7, -1
v_add_nc_u32_e32 v5, 1, v5
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_8
.LBB0_5:
s_mov_b32 s17, exec_lo
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_4
v_cmp_gt_i32_e64 s3, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s18, s3
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s3, s8, v6
v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
s_load_b32 s3, s[10:11], 0x0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s3, v6
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v3, s5, v3
s_add_i32 s2, s13, 1
s_cmp_lg_u32 s13, s12
s_cbranch_scc0 .LBB0_10
s_mov_b32 s13, s2
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccz .LBB0_2
s_branch .LBB0_8
.LBB0_10:
v_add_nc_u32_e32 v0, s14, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v1, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12conv2DKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12conv2DKernelPfS_ii, .Lfunc_end0-_Z12conv2DKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dMask
.type dMask,@object
.section .bss,"aw",@nobits
.globl dMask
.p2align 4, 0x0
dMask:
.zero 400
.size dMask, 400
.protected dHalfW
.type dHalfW,@object
.globl dHalfW
.p2align 2, 0x0
dHalfW:
.long 0
.size dHalfW, 4
.protected dHalfH
.type dHalfH,@object
.globl dHalfH
.p2align 2, 0x0
dHalfH:
.long 0
.size dHalfH, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dMask
.addrsig_sym dHalfW
.addrsig_sym dHalfH
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12conv2DKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z12conv2DKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
///////////////////////////////////////////////////////////////////////////////
#include <cufft.h>
#include <math_constants.h>
//Round a / b to nearest higher integer value
int cuda_iDivUp(int a, int b)
{
return (a + (b - 1)) / b;
}
// complex math functions
__device__
float2 conjugate(float2 arg)
{
return make_float2(arg.x, -arg.y);
}
__device__
float2 complex_exp(float arg)
{
return make_float2(cosf(arg), sinf(arg));
}
__device__
float2 complex_add(float2 a, float2 b)
{
return make_float2(a.x + b.x, a.y + b.y);
}
__device__
float2 complex_mult(float2 ab, float2 cd)
{
return make_float2(ab.x * cd.x - ab.y * cd.y, ab.x * cd.y + ab.y * cd.x);
}
// generate wave heightfield at time t based on initial heightfield and dispersion relationship
__global__ void generateSpectrumKernel(float2* h0, float2 *ht, unsigned int width, unsigned int height, float t, float patchSize)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
// calculate coordinates
float2 k;
k.x = CUDART_PI_F * x / (float) patchSize;
k.y = 2.0f * CUDART_PI_F * y / (float) patchSize;
// calculate dispersion w(k)
float k_len = sqrtf(k.x*k.x + k.y*k.y);
float w = sqrtf(9.81f * k_len);
if ((x < width) && (y < height)) {
float2 h0_k = h0[i];
float2 h0_mk = h0[(((height-1)-y)*width)+x];
float2 h_tilda = complex_add( complex_mult(h0_k, complex_exp(w * t)),
complex_mult(conjugate(h0_mk),
complex_exp(-w * t)) );
// output frequency-space complex values
ht[i] = h_tilda;
}
}
// generate slope by partial differences in spatial domain
__global__ void calculateSlopeKernel(float* h, float2 *slopeOut, unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float2 slope;
if ((x > 0) && (y > 0) && (x < width-1) && (y < height-1)) {
slope.x = h[i+1] - h[i-1];
slope.y = h[i+width] - h[i-width];
} else {
slope = make_float2(0.0f, 0.0f);
}
slopeOut[i] = slope;
}
extern "C"
void cudaGenerateSpectrumKernel(float2* d_h0, float2 *d_ht,
unsigned int width, unsigned int height,
float animTime, float patchSize)
{
dim3 block(8, 8, 1);
dim3 grid(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
generateSpectrumKernel<<<grid, block>>>(d_h0, d_ht, width, height, animTime, patchSize);
}
extern "C"
void cudaCalculateSlopeKernel( float* hptr, float2 *slopeOut,
unsigned int width, unsigned int height)
{
dim3 block(8, 8, 1);
dim3 grid2(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
calculateSlopeKernel<<<grid2, block>>>(hptr, slopeOut, width, height);
} | .file "tmpxft_001b3df5_00000000-6_oceanFFT_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cuda_iDivUpii
.type _Z11cuda_iDivUpii, @function
_Z11cuda_iDivUpii:
.LFB2050:
.cfi_startproc
endbr64
leal -1(%rsi,%rdi), %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE2050:
.size _Z11cuda_iDivUpii, .-_Z11cuda_iDivUpii
.globl _Z9conjugate6float2
.type _Z9conjugate6float2, @function
_Z9conjugate6float2:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _Z9conjugate6float2, .-_Z9conjugate6float2
.globl _Z11complex_expf
.type _Z11complex_expf, @function
_Z11complex_expf:
.LFB2052:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2052:
.size _Z11complex_expf, .-_Z11complex_expf
.globl _Z11complex_add6float2S_
.type _Z11complex_add6float2S_, @function
_Z11complex_add6float2S_:
.LFB2053:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2053:
.size _Z11complex_add6float2S_, .-_Z11complex_add6float2S_
.globl _Z12complex_mult6float2S_
.type _Z12complex_mult6float2S_, @function
_Z12complex_mult6float2S_:
.LFB2054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2054:
.size _Z12complex_mult6float2S_, .-_Z12complex_mult6float2S_
.globl _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
.type _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff, @function
_Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff:
.LFB2081:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22generateSpectrumKernelP6float2S0_jjff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff, .-_Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
.globl _Z22generateSpectrumKernelP6float2S0_jjff
.type _Z22generateSpectrumKernelP6float2S0_jjff, @function
_Z22generateSpectrumKernelP6float2S0_jjff:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z22generateSpectrumKernelP6float2S0_jjff, .-_Z22generateSpectrumKernelP6float2S0_jjff
.globl cudaGenerateSpectrumKernel
.type cudaGenerateSpectrumKernel, @function
cudaGenerateSpectrumKernel:
.LFB2055:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
leal 14(%rdx), %eax
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 36(%rsp)
leal 14(%rcx), %eax
movl %ecx, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 40(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm0
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
jmp .L20
.cfi_endproc
.LFE2055:
.size cudaGenerateSpectrumKernel, .-cudaGenerateSpectrumKernel
.globl _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
.type _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj, @function
_Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20calculateSlopeKernelPfP6float2jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj, .-_Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
.globl _Z20calculateSlopeKernelPfP6float2jj
.type _Z20calculateSlopeKernelPfP6float2jj, @function
_Z20calculateSlopeKernelPfP6float2jj:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z20calculateSlopeKernelPfP6float2jj, .-_Z20calculateSlopeKernelPfP6float2jj
.globl cudaCalculateSlopeKernel
.type cudaCalculateSlopeKernel, @function
cudaCalculateSlopeKernel:
.LFB2056:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
leal 14(%rdx), %eax
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 20(%rsp)
leal 14(%rcx), %eax
movl %ecx, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 24(%rsp)
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
jmp .L32
.cfi_endproc
.LFE2056:
.size cudaCalculateSlopeKernel, .-cudaCalculateSlopeKernel
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20calculateSlopeKernelPfP6float2jj"
.align 8
.LC1:
.string "_Z22generateSpectrumKernelP6float2S0_jjff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20calculateSlopeKernelPfP6float2jj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22generateSpectrumKernelP6float2S0_jjff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
///////////////////////////////////////////////////////////////////////////////
#include <cufft.h>
#include <math_constants.h>
//Round a / b to nearest higher integer value
int cuda_iDivUp(int a, int b)
{
return (a + (b - 1)) / b;
}
// complex math functions
__device__
float2 conjugate(float2 arg)
{
return make_float2(arg.x, -arg.y);
}
__device__
float2 complex_exp(float arg)
{
return make_float2(cosf(arg), sinf(arg));
}
__device__
float2 complex_add(float2 a, float2 b)
{
return make_float2(a.x + b.x, a.y + b.y);
}
__device__
float2 complex_mult(float2 ab, float2 cd)
{
return make_float2(ab.x * cd.x - ab.y * cd.y, ab.x * cd.y + ab.y * cd.x);
}
// generate wave heightfield at time t based on initial heightfield and dispersion relationship
__global__ void generateSpectrumKernel(float2* h0, float2 *ht, unsigned int width, unsigned int height, float t, float patchSize)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
// calculate coordinates
float2 k;
k.x = CUDART_PI_F * x / (float) patchSize;
k.y = 2.0f * CUDART_PI_F * y / (float) patchSize;
// calculate dispersion w(k)
float k_len = sqrtf(k.x*k.x + k.y*k.y);
float w = sqrtf(9.81f * k_len);
if ((x < width) && (y < height)) {
float2 h0_k = h0[i];
float2 h0_mk = h0[(((height-1)-y)*width)+x];
float2 h_tilda = complex_add( complex_mult(h0_k, complex_exp(w * t)),
complex_mult(conjugate(h0_mk),
complex_exp(-w * t)) );
// output frequency-space complex values
ht[i] = h_tilda;
}
}
// generate slope by partial differences in spatial domain
__global__ void calculateSlopeKernel(float* h, float2 *slopeOut, unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float2 slope;
if ((x > 0) && (y > 0) && (x < width-1) && (y < height-1)) {
slope.x = h[i+1] - h[i-1];
slope.y = h[i+width] - h[i-width];
} else {
slope = make_float2(0.0f, 0.0f);
}
slopeOut[i] = slope;
}
extern "C"
void cudaGenerateSpectrumKernel(float2* d_h0, float2 *d_ht,
unsigned int width, unsigned int height,
float animTime, float patchSize)
{
dim3 block(8, 8, 1);
dim3 grid(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
generateSpectrumKernel<<<grid, block>>>(d_h0, d_ht, width, height, animTime, patchSize);
}
extern "C"
void cudaCalculateSlopeKernel( float* hptr, float2 *slopeOut,
unsigned int width, unsigned int height)
{
dim3 block(8, 8, 1);
dim3 grid2(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
calculateSlopeKernel<<<grid2, block>>>(hptr, slopeOut, width, height);
} | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
///////////////////////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_math_constants.h>
//Round a / b to nearest higher integer value
int cuda_iDivUp(int a, int b)
{
return (a + (b - 1)) / b;
}
// complex math functions
__device__
float2 conjugate(float2 arg)
{
return make_float2(arg.x, -arg.y);
}
__device__
float2 complex_exp(float arg)
{
return make_float2(cosf(arg), sinf(arg));
}
__device__
float2 complex_add(float2 a, float2 b)
{
return make_float2(a.x + b.x, a.y + b.y);
}
__device__
float2 complex_mult(float2 ab, float2 cd)
{
return make_float2(ab.x * cd.x - ab.y * cd.y, ab.x * cd.y + ab.y * cd.x);
}
// generate wave heightfield at time t based on initial heightfield and dispersion relationship
__global__ void generateSpectrumKernel(float2* h0, float2 *ht, unsigned int width, unsigned int height, float t, float patchSize)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
// calculate coordinates
float2 k;
k.x = HIP_PI_F * x / (float) patchSize;
k.y = 2.0f * HIP_PI_F * y / (float) patchSize;
// calculate dispersion w(k)
float k_len = sqrtf(k.x*k.x + k.y*k.y);
float w = sqrtf(9.81f * k_len);
if ((x < width) && (y < height)) {
float2 h0_k = h0[i];
float2 h0_mk = h0[(((height-1)-y)*width)+x];
float2 h_tilda = complex_add( complex_mult(h0_k, complex_exp(w * t)),
complex_mult(conjugate(h0_mk),
complex_exp(-w * t)) );
// output frequency-space complex values
ht[i] = h_tilda;
}
}
// generate slope by partial differences in spatial domain
__global__ void calculateSlopeKernel(float* h, float2 *slopeOut, unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float2 slope;
if ((x > 0) && (y > 0) && (x < width-1) && (y < height-1)) {
slope.x = h[i+1] - h[i-1];
slope.y = h[i+width] - h[i-width];
} else {
slope = make_float2(0.0f, 0.0f);
}
slopeOut[i] = slope;
}
extern "C"
void cudaGenerateSpectrumKernel(float2* d_h0, float2 *d_ht,
unsigned int width, unsigned int height,
float animTime, float patchSize)
{
dim3 block(8, 8, 1);
dim3 grid(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
generateSpectrumKernel<<<grid, block>>>(d_h0, d_ht, width, height, animTime, patchSize);
}
extern "C"
void cudaCalculateSlopeKernel( float* hptr, float2 *slopeOut,
unsigned int width, unsigned int height)
{
dim3 block(8, 8, 1);
dim3 grid2(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
calculateSlopeKernel<<<grid2, block>>>(hptr, slopeOut, width, height);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
///////////////////////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_math_constants.h>
//Round a / b to nearest higher integer value
int cuda_iDivUp(int a, int b)
{
return (a + (b - 1)) / b;
}
// complex math functions
__device__
float2 conjugate(float2 arg)
{
return make_float2(arg.x, -arg.y);
}
__device__
float2 complex_exp(float arg)
{
return make_float2(cosf(arg), sinf(arg));
}
__device__
float2 complex_add(float2 a, float2 b)
{
return make_float2(a.x + b.x, a.y + b.y);
}
__device__
float2 complex_mult(float2 ab, float2 cd)
{
return make_float2(ab.x * cd.x - ab.y * cd.y, ab.x * cd.y + ab.y * cd.x);
}
// generate wave heightfield at time t based on initial heightfield and dispersion relationship
__global__ void generateSpectrumKernel(float2* h0, float2 *ht, unsigned int width, unsigned int height, float t, float patchSize)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
// calculate coordinates
float2 k;
k.x = HIP_PI_F * x / (float) patchSize;
k.y = 2.0f * HIP_PI_F * y / (float) patchSize;
// calculate dispersion w(k)
float k_len = sqrtf(k.x*k.x + k.y*k.y);
float w = sqrtf(9.81f * k_len);
if ((x < width) && (y < height)) {
float2 h0_k = h0[i];
float2 h0_mk = h0[(((height-1)-y)*width)+x];
float2 h_tilda = complex_add( complex_mult(h0_k, complex_exp(w * t)),
complex_mult(conjugate(h0_mk),
complex_exp(-w * t)) );
// output frequency-space complex values
ht[i] = h_tilda;
}
}
// generate slope by partial differences in spatial domain
__global__ void calculateSlopeKernel(float* h, float2 *slopeOut, unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float2 slope;
if ((x > 0) && (y > 0) && (x < width-1) && (y < height-1)) {
slope.x = h[i+1] - h[i-1];
slope.y = h[i+width] - h[i-width];
} else {
slope = make_float2(0.0f, 0.0f);
}
slopeOut[i] = slope;
}
extern "C"
void cudaGenerateSpectrumKernel(float2* d_h0, float2 *d_ht,
unsigned int width, unsigned int height,
float animTime, float patchSize)
{
dim3 block(8, 8, 1);
dim3 grid(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
generateSpectrumKernel<<<grid, block>>>(d_h0, d_ht, width, height, animTime, patchSize);
}
extern "C"
void cudaCalculateSlopeKernel( float* hptr, float2 *slopeOut,
unsigned int width, unsigned int height)
{
dim3 block(8, 8, 1);
dim3 grid2(cuda_iDivUp(width, block.x), cuda_iDivUp(height, block.y), 1);
calculateSlopeKernel<<<grid2, block>>>(hptr, slopeOut, width, height);
} | .text
.file "oceanFFT_kernel.hip"
.globl _Z11cuda_iDivUpii # -- Begin function _Z11cuda_iDivUpii
.p2align 4, 0x90
.type _Z11cuda_iDivUpii,@function
_Z11cuda_iDivUpii: # @_Z11cuda_iDivUpii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
decl %eax
cltd
idivl %esi
retq
.Lfunc_end0:
.size _Z11cuda_iDivUpii, .Lfunc_end0-_Z11cuda_iDivUpii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff # -- Begin function _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.p2align 4, 0x90
.type _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff,@function
_Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff: # @_Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, .Lfunc_end1-_Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.cfi_endproc
# -- End function
.globl _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj # -- Begin function _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.p2align 4, 0x90
.type _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj,@function
_Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj: # @_Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, .Lfunc_end2-_Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.cfi_endproc
# -- End function
.globl cudaGenerateSpectrumKernel # -- Begin function cudaGenerateSpectrumKernel
.p2align 4, 0x90
.type cudaGenerateSpectrumKernel,@function
cudaGenerateSpectrumKernel: # @cudaGenerateSpectrumKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movss %xmm1, 12(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %ecx, %ebx
movl %edx, %r14d
movq %rsi, %r15
leal 7(%r14), %eax
leal 14(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
leal 7(%rbx), %edx
leal 14(%rbx), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r12
sarl $3, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $34359738376, %rdx # imm = 0x800000008
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movl %r14d, 28(%rsp)
movl %ebx, 24(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size cudaGenerateSpectrumKernel, .Lfunc_end3-cudaGenerateSpectrumKernel
.cfi_endproc
# -- End function
.globl cudaCalculateSlopeKernel # -- Begin function cudaCalculateSlopeKernel
.p2align 4, 0x90
.type cudaCalculateSlopeKernel,@function
cudaCalculateSlopeKernel: # @cudaCalculateSlopeKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movl %edx, %r14d
movq %rsi, %r15
leal 7(%r14), %eax
leal 14(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
leal 7(%rbx), %edx
leal 14(%rbx), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r12
sarl $3, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $34359738376, %rdx # imm = 0x800000008
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size cudaCalculateSlopeKernel, .Lfunc_end4-cudaCalculateSlopeKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff,@object # @_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.section .rodata,"a",@progbits
.globl _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.p2align 3, 0x0
_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff:
.quad _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.size _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, 8
.type _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj,@object # @_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.globl _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.p2align 3, 0x0
_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj:
.quad _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.size _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff"
.size .L__unnamed_1, 59
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj"
.size .L__unnamed_2, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.addrsig_sym _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.addrsig_sym _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b3df5_00000000-6_oceanFFT_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cuda_iDivUpii
.type _Z11cuda_iDivUpii, @function
_Z11cuda_iDivUpii:
.LFB2050:
.cfi_startproc
endbr64
leal -1(%rsi,%rdi), %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE2050:
.size _Z11cuda_iDivUpii, .-_Z11cuda_iDivUpii
.globl _Z9conjugate6float2
.type _Z9conjugate6float2, @function
_Z9conjugate6float2:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _Z9conjugate6float2, .-_Z9conjugate6float2
.globl _Z11complex_expf
.type _Z11complex_expf, @function
_Z11complex_expf:
.LFB2052:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2052:
.size _Z11complex_expf, .-_Z11complex_expf
.globl _Z11complex_add6float2S_
.type _Z11complex_add6float2S_, @function
_Z11complex_add6float2S_:
.LFB2053:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2053:
.size _Z11complex_add6float2S_, .-_Z11complex_add6float2S_
.globl _Z12complex_mult6float2S_
.type _Z12complex_mult6float2S_, @function
_Z12complex_mult6float2S_:
.LFB2054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2054:
.size _Z12complex_mult6float2S_, .-_Z12complex_mult6float2S_
.globl _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
.type _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff, @function
_Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff:
.LFB2081:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22generateSpectrumKernelP6float2S0_jjff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff, .-_Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
.globl _Z22generateSpectrumKernelP6float2S0_jjff
.type _Z22generateSpectrumKernelP6float2S0_jjff, @function
_Z22generateSpectrumKernelP6float2S0_jjff:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z22generateSpectrumKernelP6float2S0_jjff, .-_Z22generateSpectrumKernelP6float2S0_jjff
.globl cudaGenerateSpectrumKernel
.type cudaGenerateSpectrumKernel, @function
cudaGenerateSpectrumKernel:
.LFB2055:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
leal 14(%rdx), %eax
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 36(%rsp)
leal 14(%rcx), %eax
movl %ecx, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 40(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movss 12(%rsp), %xmm1
movss 8(%rsp), %xmm0
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z55__device_stub__Z22generateSpectrumKernelP6float2S0_jjffP6float2S0_jjff
jmp .L20
.cfi_endproc
.LFE2055:
.size cudaGenerateSpectrumKernel, .-cudaGenerateSpectrumKernel
.globl _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
.type _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj, @function
_Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20calculateSlopeKernelPfP6float2jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj, .-_Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
.globl _Z20calculateSlopeKernelPfP6float2jj
.type _Z20calculateSlopeKernelPfP6float2jj, @function
_Z20calculateSlopeKernelPfP6float2jj:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z20calculateSlopeKernelPfP6float2jj, .-_Z20calculateSlopeKernelPfP6float2jj
.globl cudaCalculateSlopeKernel
.type cudaCalculateSlopeKernel, @function
cudaCalculateSlopeKernel:
.LFB2056:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
leal 14(%rdx), %eax
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 20(%rsp)
leal 14(%rcx), %eax
movl %ecx, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 24(%rsp)
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z50__device_stub__Z20calculateSlopeKernelPfP6float2jjPfP6float2jj
jmp .L32
.cfi_endproc
.LFE2056:
.size cudaCalculateSlopeKernel, .-cudaCalculateSlopeKernel
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20calculateSlopeKernelPfP6float2jj"
.align 8
.LC1:
.string "_Z22generateSpectrumKernelP6float2S0_jjff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20calculateSlopeKernelPfP6float2jj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22generateSpectrumKernelP6float2S0_jjff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "oceanFFT_kernel.hip"
.globl _Z11cuda_iDivUpii # -- Begin function _Z11cuda_iDivUpii
.p2align 4, 0x90
.type _Z11cuda_iDivUpii,@function
_Z11cuda_iDivUpii: # @_Z11cuda_iDivUpii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
decl %eax
cltd
idivl %esi
retq
.Lfunc_end0:
.size _Z11cuda_iDivUpii, .Lfunc_end0-_Z11cuda_iDivUpii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff # -- Begin function _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.p2align 4, 0x90
.type _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff,@function
_Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff: # @_Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, .Lfunc_end1-_Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.cfi_endproc
# -- End function
.globl _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj # -- Begin function _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.p2align 4, 0x90
.type _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj,@function
_Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj: # @_Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, .Lfunc_end2-_Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.cfi_endproc
# -- End function
.globl cudaGenerateSpectrumKernel # -- Begin function cudaGenerateSpectrumKernel
.p2align 4, 0x90
.type cudaGenerateSpectrumKernel,@function
cudaGenerateSpectrumKernel: # @cudaGenerateSpectrumKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movss %xmm1, 12(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %ecx, %ebx
movl %edx, %r14d
movq %rsi, %r15
leal 7(%r14), %eax
leal 14(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
leal 7(%rbx), %edx
leal 14(%rbx), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r12
sarl $3, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $34359738376, %rdx # imm = 0x800000008
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movl %r14d, 28(%rsp)
movl %ebx, 24(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size cudaGenerateSpectrumKernel, .Lfunc_end3-cudaGenerateSpectrumKernel
.cfi_endproc
# -- End function
.globl cudaCalculateSlopeKernel # -- Begin function cudaCalculateSlopeKernel
.p2align 4, 0x90
.type cudaCalculateSlopeKernel,@function
cudaCalculateSlopeKernel: # @cudaCalculateSlopeKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movl %edx, %r14d
movq %rsi, %r15
leal 7(%r14), %eax
leal 14(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
leal 7(%rbx), %edx
leal 14(%rbx), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r12
sarl $3, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $34359738376, %rdx # imm = 0x800000008
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size cudaCalculateSlopeKernel, .Lfunc_end4-cudaCalculateSlopeKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff,@object # @_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.section .rodata,"a",@progbits
.globl _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.p2align 3, 0x0
_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff:
.quad _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.size _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff, 8
.type _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj,@object # @_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.globl _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.p2align 3, 0x0
_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj:
.quad _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.size _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff"
.size .L__unnamed_1, 59
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj"
.size .L__unnamed_2, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.addrsig_sym _Z35__device_stub__calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22generateSpectrumKernelP15HIP_vector_typeIfLj2EES1_jjff
.addrsig_sym _Z20calculateSlopeKernelPfP15HIP_vector_typeIfLj2EEjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
void getSourceFile(std::vector<double>& eNomVec, std::vector<double>& rangeVec,
std::vector<double>& sigmaXVec,std::vector<double>& sigmaYVec,
std::vector<double>& eMeanVec, std::vector<double>& sigmaEVec,
std::vector<double>& xVec, std::vector<double>& yVec,
std::vector<double>& nxVec,std::vector<double>& nyVec,
std::vector<double>& weightVec, int& numGroups)
{
int dateOfMeasurement;
long int numberOfGroups;
double eNom, range, sigmaX, sigmaY, eMean, sigmaE, xcoord, ycoord, weight, nx, ny;
std::string line;
//declare and open file
std::ifstream ifile("IMPT_source.dat", std::ios::in);
if(!ifile){
std::cout << "Error, IMPT_source not found" << std::endl;
}else{
//read in date of measurement
ifile >> dateOfMeasurement;
//read in number of groups
ifile >> numberOfGroups;
numGroups = numberOfGroups;
//skip over header line
std::string e, r, x, y, m, s, nx1, ny1, x1, y1, w;
ifile >> e;
ifile >> r;
ifile >> x;
ifile >> y;
ifile >> m;
ifile >> s;
ifile >> x1;
ifile >> y1;
ifile >> nx1;
ifile >> ny1;
ifile >> w;
eNomVec.reserve(numberOfGroups);
//read in data to vectors
for(int i = 0; i < numberOfGroups; i++){
ifile >> eNom;
ifile >> range;
ifile >> sigmaX;
ifile >> sigmaY;
ifile >> eMean;
ifile >> sigmaE;
ifile >> xcoord;
ifile >> ycoord;
ifile >> nx;
ifile >> ny;
ifile >> weight;
eNomVec.push_back(eNom);
// rangeVec.push_back(range);
// sigmaXVec.push_back(sigmaX);
// sigmaYVec.push_back(sigmaY);
// eMeanVec.push_back(eMean);
xVec.push_back(xcoord);
yVec.push_back(ycoord);
nxVec.push_back(nx);
nyVec.push_back(ny);
// weightVec.push_back(weight);
}
}
}
int main(){
int numberOfGroups;
std::vector<double> eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight;
getSourceFile(eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight, numberOfGroups);
std::vector< std::vector<double> > zRange;
for(int master = 0; master < 94; master++){
std::vector<double> temp;
//declare stream size variables and open file/check for errors
std::streampos bufferSize;
double fieldSize = -1*(xCoord[master]+yCoord[master])/(nx[master]-1);
//create fileName to read in data
std::ostringstream fName;
if(master < 9){
fName << std::fixed << "GyPerMU3D_0" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}else{
fName << std::fixed << "GyPerMU3D_" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}
std::string fileName = fName.str();
std::cout << fileName << std::endl;
std::ifstream ifile(fileName.c_str(), std::ios::in | std::ios::binary);
if(!ifile){
std::cout << "Error, no file found" << std::endl;
exit(1);
}
//get file size
ifile.seekg(0, std::ios::end);
bufferSize = ifile.tellg();
ifile.seekg(0, std::ios::beg);
//declare buffer
std::vector<double> buffer(bufferSize/sizeof(double));
//read in data
ifile.read(reinterpret_cast<char*>(buffer.data()), bufferSize);
int size = bufferSize/(sizeof(double)*400);
//copy memory from buffer to energy
double *energy;
energy = (double*)malloc(64000000*sizeof(double));
std::copy(buffer.begin(), buffer.end(), energy);
//so the equation for location is 200y*x, thus for four points (100,100), (100, 101), (101, 100), (101,101)
//we just start at 20100 and add in the needed 20101, 20300, 20301 respectively and then iterate to next layer
//by adding 40000 as the grid size is 200x200.
for(int i = 80200; i < 64000000; i+= 160000){
temp.push_back((energy[i] + energy[i+1] + energy[i+400] + energy[i+401])/4);
}
zRange.push_back(temp);
}
std::cout << zRange.size() << std::endl;
std::ofstream zfile("depthDose.txt", std::ios::out);
zfile << "Z(mm)";
for(int i = 0; i < 94; i++){
zfile << std::fixed << std::setprecision(1) << std::setw(10) << eNom[i] << "(MeV)";
}
zfile << std::endl;
for(int i = 0; i < 400; i++){
zfile << i << " ";
for(int j = 0; j < 94; j++){
zfile << std::scientific << std::setprecision(3) << std::setw(10) << zRange[j][i] << " ";
}
zfile << std::endl;
}
zfile << std::endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
void getSourceFile(std::vector<double>& eNomVec, std::vector<double>& rangeVec,
std::vector<double>& sigmaXVec,std::vector<double>& sigmaYVec,
std::vector<double>& eMeanVec, std::vector<double>& sigmaEVec,
std::vector<double>& xVec, std::vector<double>& yVec,
std::vector<double>& nxVec,std::vector<double>& nyVec,
std::vector<double>& weightVec, int& numGroups)
{
int dateOfMeasurement;
long int numberOfGroups;
double eNom, range, sigmaX, sigmaY, eMean, sigmaE, xcoord, ycoord, weight, nx, ny;
std::string line;
//declare and open file
std::ifstream ifile("IMPT_source.dat", std::ios::in);
if(!ifile){
std::cout << "Error, IMPT_source not found" << std::endl;
}else{
//read in date of measurement
ifile >> dateOfMeasurement;
//read in number of groups
ifile >> numberOfGroups;
numGroups = numberOfGroups;
//skip over header line
std::string e, r, x, y, m, s, nx1, ny1, x1, y1, w;
ifile >> e;
ifile >> r;
ifile >> x;
ifile >> y;
ifile >> m;
ifile >> s;
ifile >> x1;
ifile >> y1;
ifile >> nx1;
ifile >> ny1;
ifile >> w;
eNomVec.reserve(numberOfGroups);
//read in data to vectors
for(int i = 0; i < numberOfGroups; i++){
ifile >> eNom;
ifile >> range;
ifile >> sigmaX;
ifile >> sigmaY;
ifile >> eMean;
ifile >> sigmaE;
ifile >> xcoord;
ifile >> ycoord;
ifile >> nx;
ifile >> ny;
ifile >> weight;
eNomVec.push_back(eNom);
// rangeVec.push_back(range);
// sigmaXVec.push_back(sigmaX);
// sigmaYVec.push_back(sigmaY);
// eMeanVec.push_back(eMean);
xVec.push_back(xcoord);
yVec.push_back(ycoord);
nxVec.push_back(nx);
nyVec.push_back(ny);
// weightVec.push_back(weight);
}
}
}
int main(){
int numberOfGroups;
std::vector<double> eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight;
getSourceFile(eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight, numberOfGroups);
std::vector< std::vector<double> > zRange;
for(int master = 0; master < 94; master++){
std::vector<double> temp;
//declare stream size variables and open file/check for errors
std::streampos bufferSize;
double fieldSize = -1*(xCoord[master]+yCoord[master])/(nx[master]-1);
//create fileName to read in data
std::ostringstream fName;
if(master < 9){
fName << std::fixed << "GyPerMU3D_0" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}else{
fName << std::fixed << "GyPerMU3D_" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}
std::string fileName = fName.str();
std::cout << fileName << std::endl;
std::ifstream ifile(fileName.c_str(), std::ios::in | std::ios::binary);
if(!ifile){
std::cout << "Error, no file found" << std::endl;
exit(1);
}
//get file size
ifile.seekg(0, std::ios::end);
bufferSize = ifile.tellg();
ifile.seekg(0, std::ios::beg);
//declare buffer
std::vector<double> buffer(bufferSize/sizeof(double));
//read in data
ifile.read(reinterpret_cast<char*>(buffer.data()), bufferSize);
int size = bufferSize/(sizeof(double)*400);
//copy memory from buffer to energy
double *energy;
energy = (double*)malloc(64000000*sizeof(double));
std::copy(buffer.begin(), buffer.end(), energy);
//so the equation for location is 200y*x, thus for four points (100,100), (100, 101), (101, 100), (101,101)
//we just start at 20100 and add in the needed 20101, 20300, 20301 respectively and then iterate to next layer
//by adding 40000 as the grid size is 200x200.
for(int i = 80200; i < 64000000; i+= 160000){
temp.push_back((energy[i] + energy[i+1] + energy[i+400] + energy[i+401])/4);
}
zRange.push_back(temp);
}
std::cout << zRange.size() << std::endl;
std::ofstream zfile("depthDose.txt", std::ios::out);
zfile << "Z(mm)";
for(int i = 0; i < 94; i++){
zfile << std::fixed << std::setprecision(1) << std::setw(10) << eNom[i] << "(MeV)";
}
zfile << std::endl;
for(int i = 0; i < 400; i++){
zfile << i << " ";
for(int j = 0; j < 94; j++){
zfile << std::scientific << std::setprecision(3) << std::setw(10) << zRange[j][i] << " ";
}
zfile << std::endl;
}
zfile << std::endl;
} | #include <hip/hip_runtime.h>
#include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
void getSourceFile(std::vector<double>& eNomVec, std::vector<double>& rangeVec,
std::vector<double>& sigmaXVec,std::vector<double>& sigmaYVec,
std::vector<double>& eMeanVec, std::vector<double>& sigmaEVec,
std::vector<double>& xVec, std::vector<double>& yVec,
std::vector<double>& nxVec,std::vector<double>& nyVec,
std::vector<double>& weightVec, int& numGroups)
{
int dateOfMeasurement;
long int numberOfGroups;
double eNom, range, sigmaX, sigmaY, eMean, sigmaE, xcoord, ycoord, weight, nx, ny;
std::string line;
//declare and open file
std::ifstream ifile("IMPT_source.dat", std::ios::in);
if(!ifile){
std::cout << "Error, IMPT_source not found" << std::endl;
}else{
//read in date of measurement
ifile >> dateOfMeasurement;
//read in number of groups
ifile >> numberOfGroups;
numGroups = numberOfGroups;
//skip over header line
std::string e, r, x, y, m, s, nx1, ny1, x1, y1, w;
ifile >> e;
ifile >> r;
ifile >> x;
ifile >> y;
ifile >> m;
ifile >> s;
ifile >> x1;
ifile >> y1;
ifile >> nx1;
ifile >> ny1;
ifile >> w;
eNomVec.reserve(numberOfGroups);
//read in data to vectors
for(int i = 0; i < numberOfGroups; i++){
ifile >> eNom;
ifile >> range;
ifile >> sigmaX;
ifile >> sigmaY;
ifile >> eMean;
ifile >> sigmaE;
ifile >> xcoord;
ifile >> ycoord;
ifile >> nx;
ifile >> ny;
ifile >> weight;
eNomVec.push_back(eNom);
// rangeVec.push_back(range);
// sigmaXVec.push_back(sigmaX);
// sigmaYVec.push_back(sigmaY);
// eMeanVec.push_back(eMean);
xVec.push_back(xcoord);
yVec.push_back(ycoord);
nxVec.push_back(nx);
nyVec.push_back(ny);
// weightVec.push_back(weight);
}
}
}
int main(){
int numberOfGroups;
std::vector<double> eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight;
getSourceFile(eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight, numberOfGroups);
std::vector< std::vector<double> > zRange;
for(int master = 0; master < 94; master++){
std::vector<double> temp;
//declare stream size variables and open file/check for errors
std::streampos bufferSize;
double fieldSize = -1*(xCoord[master]+yCoord[master])/(nx[master]-1);
//create fileName to read in data
std::ostringstream fName;
if(master < 9){
fName << std::fixed << "GyPerMU3D_0" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}else{
fName << std::fixed << "GyPerMU3D_" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}
std::string fileName = fName.str();
std::cout << fileName << std::endl;
std::ifstream ifile(fileName.c_str(), std::ios::in | std::ios::binary);
if(!ifile){
std::cout << "Error, no file found" << std::endl;
exit(1);
}
//get file size
ifile.seekg(0, std::ios::end);
bufferSize = ifile.tellg();
ifile.seekg(0, std::ios::beg);
//declare buffer
std::vector<double> buffer(bufferSize/sizeof(double));
//read in data
ifile.read(reinterpret_cast<char*>(buffer.data()), bufferSize);
int size = bufferSize/(sizeof(double)*400);
//copy memory from buffer to energy
double *energy;
energy = (double*)malloc(64000000*sizeof(double));
std::copy(buffer.begin(), buffer.end(), energy);
//so the equation for location is 200y*x, thus for four points (100,100), (100, 101), (101, 100), (101,101)
//we just start at 20100 and add in the needed 20101, 20300, 20301 respectively and then iterate to next layer
//by adding 40000 as the grid size is 200x200.
for(int i = 80200; i < 64000000; i+= 160000){
temp.push_back((energy[i] + energy[i+1] + energy[i+400] + energy[i+401])/4);
}
zRange.push_back(temp);
}
std::cout << zRange.size() << std::endl;
std::ofstream zfile("depthDose.txt", std::ios::out);
zfile << "Z(mm)";
for(int i = 0; i < 94; i++){
zfile << std::fixed << std::setprecision(1) << std::setw(10) << eNom[i] << "(MeV)";
}
zfile << std::endl;
for(int i = 0; i < 400; i++){
zfile << i << " ";
for(int j = 0; j < 94; j++){
zfile << std::scientific << std::setprecision(3) << std::setw(10) << zRange[j][i] << " ";
}
zfile << std::endl;
}
zfile << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <fstream>
#include <iterator>
#include <vector>
#include <iostream>
#include <cstdlib>
#include <string>
#include <sstream>
#include <iomanip>
#include <math.h>
#include <stdio.h>
void getSourceFile(std::vector<double>& eNomVec, std::vector<double>& rangeVec,
std::vector<double>& sigmaXVec,std::vector<double>& sigmaYVec,
std::vector<double>& eMeanVec, std::vector<double>& sigmaEVec,
std::vector<double>& xVec, std::vector<double>& yVec,
std::vector<double>& nxVec,std::vector<double>& nyVec,
std::vector<double>& weightVec, int& numGroups)
{
int dateOfMeasurement;
long int numberOfGroups;
double eNom, range, sigmaX, sigmaY, eMean, sigmaE, xcoord, ycoord, weight, nx, ny;
std::string line;
//declare and open file
std::ifstream ifile("IMPT_source.dat", std::ios::in);
if(!ifile){
std::cout << "Error, IMPT_source not found" << std::endl;
}else{
//read in date of measurement
ifile >> dateOfMeasurement;
//read in number of groups
ifile >> numberOfGroups;
numGroups = numberOfGroups;
//skip over header line
std::string e, r, x, y, m, s, nx1, ny1, x1, y1, w;
ifile >> e;
ifile >> r;
ifile >> x;
ifile >> y;
ifile >> m;
ifile >> s;
ifile >> x1;
ifile >> y1;
ifile >> nx1;
ifile >> ny1;
ifile >> w;
eNomVec.reserve(numberOfGroups);
//read in data to vectors
for(int i = 0; i < numberOfGroups; i++){
ifile >> eNom;
ifile >> range;
ifile >> sigmaX;
ifile >> sigmaY;
ifile >> eMean;
ifile >> sigmaE;
ifile >> xcoord;
ifile >> ycoord;
ifile >> nx;
ifile >> ny;
ifile >> weight;
eNomVec.push_back(eNom);
// rangeVec.push_back(range);
// sigmaXVec.push_back(sigmaX);
// sigmaYVec.push_back(sigmaY);
// eMeanVec.push_back(eMean);
xVec.push_back(xcoord);
yVec.push_back(ycoord);
nxVec.push_back(nx);
nyVec.push_back(ny);
// weightVec.push_back(weight);
}
}
}
int main(){
int numberOfGroups;
std::vector<double> eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight;
getSourceFile(eNom, range, sigmaX, sigmaY, eMean, sigmaE, xCoord, yCoord, nx, ny, weight, numberOfGroups);
std::vector< std::vector<double> > zRange;
for(int master = 0; master < 94; master++){
std::vector<double> temp;
//declare stream size variables and open file/check for errors
std::streampos bufferSize;
double fieldSize = -1*(xCoord[master]+yCoord[master])/(nx[master]-1);
//create fileName to read in data
std::ostringstream fName;
if(master < 9){
fName << std::fixed << "GyPerMU3D_0" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}else{
fName << std::fixed << "GyPerMU3D_" << master+1 << "_" << std::setprecision(1) << eNom[master] << "MeV_field_" << std::setprecision(0) << nx[master] << "by"
<< ny[master] << "spots_" << std::setprecision(2) << fieldSize << "by" << std::setprecision(2) << fieldSize << "cm2spacing.bin";
}
std::string fileName = fName.str();
std::cout << fileName << std::endl;
std::ifstream ifile(fileName.c_str(), std::ios::in | std::ios::binary);
if(!ifile){
std::cout << "Error, no file found" << std::endl;
exit(1);
}
//get file size
ifile.seekg(0, std::ios::end);
bufferSize = ifile.tellg();
ifile.seekg(0, std::ios::beg);
//declare buffer
std::vector<double> buffer(bufferSize/sizeof(double));
//read in data
ifile.read(reinterpret_cast<char*>(buffer.data()), bufferSize);
int size = bufferSize/(sizeof(double)*400);
//copy memory from buffer to energy
double *energy;
energy = (double*)malloc(64000000*sizeof(double));
std::copy(buffer.begin(), buffer.end(), energy);
//so the equation for location is 200y*x, thus for four points (100,100), (100, 101), (101, 100), (101,101)
//we just start at 20100 and add in the needed 20101, 20300, 20301 respectively and then iterate to next layer
//by adding 40000 as the grid size is 200x200.
for(int i = 80200; i < 64000000; i+= 160000){
temp.push_back((energy[i] + energy[i+1] + energy[i+400] + energy[i+401])/4);
}
zRange.push_back(temp);
}
std::cout << zRange.size() << std::endl;
std::ofstream zfile("depthDose.txt", std::ios::out);
zfile << "Z(mm)";
for(int i = 0; i < 94; i++){
zfile << std::fixed << std::setprecision(1) << std::setw(10) << eNom[i] << "(MeV)";
}
zfile << std::endl;
for(int i = 0; i < 400; i++){
zfile << i << " ";
for(int j = 0; j < 94; j++){
zfile << std::scientific << std::setprecision(3) << std::setw(10) << zRange[j][i] << " ";
}
zfile << std::endl;
}
zfile << std::endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cunnx_LazyKBest_updateGradInput_kernel( float *gradInput, const float *indice, const float *gradOutput, int inputSize, int outputSize)
{
int tx = threadIdx.x;
int step = blockDim.x;
int k = blockIdx.x;
float *gradInput_k = gradInput + k*inputSize;
const float *gradOutput_k = gradOutput + k*outputSize;
const float *indice_k = indice + k*outputSize;
for (int i=tx; i<outputSize; i+=step)
gradInput_k[(int)(indice_k[i] - 1)] = gradOutput_k[i];
} | code for sm_80
Function : _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ BSSY B0, 0x400 ; /* 0x0000035000007945 */
/* 0x000fe40003800000 */
/*00b0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e220000001000 */
/*00c0*/ UIMAD UR4, UR5, UR6, URZ ; /* 0x00000006050472a4 */
/* 0x002fe4000f8e023f */
/*00d0*/ UIMAD UR5, UR5, UR7, URZ ; /* 0x00000007050572a4 */
/* 0x000fc4000f8e023f */
/*00e0*/ USHF.R.S32.HI UR8, URZ, 0x1f, UR4 ; /* 0x0000001f3f087899 */
/* 0x000fe20008011404 */
/*00f0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fe20007ffe0ff */
/*0100*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0110*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR5 ; /* 0x0000001f3f097899 */
/* 0x000fe20008011405 */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0150*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0220*/ LOP3.LUT P1, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000782c0ff */
/*0230*/ @!P1 BRA 0x3f0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R5, P1, R0, UR5, RZ ; /* 0x0000000500057c10 */
/* 0x000fe2000ff3e0ff */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0002 */
/*0260*/ LEA.HI.X.SX32 R6, R0, UR9, 0x1, P1 ; /* 0x0000000900067c11 */
/* 0x000fe200088f0eff */
/*0270*/ IMAD.SHL.U32 R4, R5, 0x4, RZ ; /* 0x0000000405047824 */
/* 0x000fc600078e00ff */
/*0280*/ SHF.L.U64.HI R5, R5, 0x2, R6 ; /* 0x0000000205057819 */
/* 0x000fe40000010206 */
/*0290*/ IADD3 R10, P1, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a00040a7a10 */
/* 0x040fe40007f3e0ff */
/*02a0*/ IADD3 R4, P2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fe40007f5e0ff */
/*02b0*/ IADD3.X R3, R5.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0005037a10 */
/* 0x040fe40000ffe4ff */
/*02c0*/ IADD3.X R5, R5, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0005057a10 */
/* 0x000fc800017fe4ff */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*02e0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x0000a8000c1e1900 */
/*02f0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x0002e2000c1e1900 */
/*0300*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*0330*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fc800078e0204 */
/*0340*/ IMAD.WIDE R2, R11, 0x4, R2 ; /* 0x000000040b027825 */
/* 0x002fc800078e0202 */
/*0350*/ FADD R10, R6, -1 ; /* 0xbf800000060a7421 */
/* 0x008fcc0000000000 */
/*0360*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e24000020f100 */
/*0370*/ IADD3 R7, P1, R10, UR4, RZ ; /* 0x000000040a077c10 */
/* 0x001fc8000ff3e0ff */
/*0380*/ LEA.HI.X.SX32 R12, R10, UR8, 0x1, P1 ; /* 0x000000080a0c7c11 */
/* 0x000fe400088f0eff */
/*0390*/ LEA R6, P1, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078210ff */
/*03a0*/ LEA.HI.X R7, R7, c[0x0][0x164], R12, 0x2, P1 ; /* 0x0000590007077a11 */
/* 0x000fca00008f140c */
/*03b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0041e2000c101906 */
/*03c0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*03d0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fd800078e0002 */
/*03e0*/ @P1 BRA 0x2d0 ; /* 0xfffffee000001947 */
/* 0x001fea000383ffff */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R3, P0, R0, UR5, RZ ; /* 0x0000000500037c10 */
/* 0x001fc8000ff1e0ff */
/*0420*/ LEA.HI.X.SX32 R2, R0, UR9, 0x1, P0 ; /* 0x0000000900027c11 */
/* 0x000fe200080f0eff */
/*0430*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fc600078e00ff */
/*0440*/ SHF.L.U64.HI R3, R3, 0x2, R2 ; /* 0x0000000203037819 */
/* 0x000fe40000010202 */
/*0450*/ IADD3 R6, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004067a10 */
/* 0x000fc80007f1e0ff */
/*0460*/ IADD3.X R7, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x000fca00007fe4ff */
/*0470*/ LDG.E R2, [R6.64] ; /* 0x0000000606027981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R4, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fc80007f1e0ff */
/*0490*/ IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003057a10 */
/* 0x000fca00007fe4ff */
/*04a0*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ FADD R8, R2, -1 ; /* 0xbf80000002087421 */
/* 0x004fe40000000000 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fc800078e00ff */
/*04d0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*04e0*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fe200078e0206 */
/*04f0*/ IADD3 R9, P0, R8, UR4, RZ ; /* 0x0000000408097c10 */
/* 0x001fc8000ff1e0ff */
/*0500*/ LEA.HI.X.SX32 R12, R8, UR8, 0x1, P0 ; /* 0x00000008080c7c11 */
/* 0x000fe400080f0eff */
/*0510*/ LEA R10, P0, R9, c[0x0][0x160], 0x2 ; /* 0x00005800090a7a11 */
/* 0x000fc800078010ff */
/*0520*/ LEA.HI.X R11, R9, c[0x0][0x164], R12, 0x2, P0 ; /* 0x00005900090b7a11 */
/* 0x000fca00000f140c */
/*0530*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x0081e8000c101906 */
/*0540*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x000fca00078e0204 */
/*0560*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ee2000c1e1900 */
/*0570*/ FADD R14, R9, -1 ; /* 0xbf800000090e7421 */
/* 0x004fcc0000000000 */
/*0580*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e64000020f100 */
/*0590*/ IADD3 R8, P0, R14, UR4, RZ ; /* 0x000000040e087c10 */
/* 0x002fc8000ff1e0ff */
/*05a0*/ LEA.HI.X.SX32 R9, R14, UR8, 0x1, P0 ; /* 0x000000080e097c11 */
/* 0x000fe400080f0eff */
/*05b0*/ LEA R12, P0, R8, c[0x0][0x160], 0x2 ; /* 0x00005800080c7a11 */
/* 0x000fc800078010ff */
/*05c0*/ LEA.HI.X R13, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x00005900080d7a11 */
/* 0x000fe200000f1409 */
/*05d0*/ IMAD.WIDE R8, R2, 0x4, R6 ; /* 0x0000000402087825 */
/* 0x000fc800078e0206 */
/*05e0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0083e8000c101906 */
/*05f0*/ LDG.E R3, [R8.64] ; /* 0x0000000608037981 */
/* 0x001ea2000c1e1900 */
/*0600*/ IMAD.WIDE R6, R2, 0x4, R4 ; /* 0x0000000402067825 */
/* 0x000fca00078e0204 */
/*0610*/ LDG.E R17, [R6.64] ; /* 0x0000000606117981 */
/* 0x000ee2000c1e1900 */
/*0620*/ FADD R16, R3, -1 ; /* 0xbf80000003107421 */
/* 0x004fcc0000000000 */
/*0630*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e24000020f100 */
/*0640*/ IADD3 R3, P0, R16, UR4, RZ ; /* 0x0000000410037c10 */
/* 0x001fc8000ff1e0ff */
/*0650*/ LEA.HI.X.SX32 R4, R16, UR8, 0x1, P0 ; /* 0x0000000810047c11 */
/* 0x000fe400080f0eff */
/*0660*/ LEA R10, P0, R3, c[0x0][0x160], 0x2 ; /* 0x00005800030a7a11 */
/* 0x000fc800078010ff */
/*0670*/ LEA.HI.X R11, R3, c[0x0][0x164], R4, 0x2, P0 ; /* 0x00005900030b7a11 */
/* 0x000fe200000f1404 */
/*0680*/ IMAD.WIDE R4, R2, 0x4, R8 ; /* 0x0000000402047825 */
/* 0x000fc800078e0208 */
/*0690*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0081e8000c101906 */
/*06a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0004e2000c1e1900 */
/*06b0*/ IMAD.WIDE R2, R2, 0x4, R6 ; /* 0x0000000402027825 */
/* 0x000fcc00078e0206 */
/*06c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000f22000c1e1900 */
/*06d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x004fe400078e00ff */
/*06f0*/ IMAD R0, R9, 0x2, R0 ; /* 0x0000000209007824 */
/* 0x000fc800078e0200 */
/*0700*/ IMAD R0, R5, 0x2, R0 ; /* 0x0000000205007824 */
/* 0x000fe400078e0200 */
/*0710*/ FADD R8, R4, -1 ; /* 0xbf80000004087421 */
/* 0x008fcc0000000000 */
/*0720*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000ea4000020f100 */
/*0730*/ IADD3 R7, P0, R8, UR4, RZ ; /* 0x0000000408077c10 */
/* 0x004fc8000ff1e0ff */
/*0740*/ LEA.HI.X.SX32 R12, R8, UR8, 0x1, P0 ; /* 0x00000008080c7c11 */
/* 0x002fe400080f0eff */
/*0750*/ LEA R6, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078010ff */
/*0760*/ LEA.HI.X R7, R7, c[0x0][0x164], R12, 0x2, P0 ; /* 0x0000590007077a11 */
/* 0x000fe400000f140c */
/*0770*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc60003f06270 */
/*0780*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0101f4000c101906 */
/*0790*/ @!P0 BRA 0x410 ; /* 0xfffffc7000008947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cunnx_LazyKBest_updateGradInput_kernel( float *gradInput, const float *indice, const float *gradOutput, int inputSize, int outputSize)
{
int tx = threadIdx.x;
int step = blockDim.x;
int k = blockIdx.x;
float *gradInput_k = gradInput + k*inputSize;
const float *gradOutput_k = gradOutput + k*outputSize;
const float *indice_k = indice + k*outputSize;
for (int i=tx; i<outputSize; i+=step)
gradInput_k[(int)(indice_k[i] - 1)] = gradOutput_k[i];
} | .file "tmpxft_00163be7_00000000-6_cunnx_LazyKBest_updateGradInput_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii
.type _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii, @function
_Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii, .-_Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii
.globl _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.type _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, @function
_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, .-_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cunnx_LazyKBest_updateGradInput_kernel( float *gradInput, const float *indice, const float *gradOutput, int inputSize, int outputSize)
{
int tx = threadIdx.x;
int step = blockDim.x;
int k = blockIdx.x;
float *gradInput_k = gradInput + k*inputSize;
const float *gradOutput_k = gradOutput + k*outputSize;
const float *indice_k = indice + k*outputSize;
for (int i=tx; i<outputSize; i+=step)
gradInput_k[(int)(indice_k[i] - 1)] = gradOutput_k[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunnx_LazyKBest_updateGradInput_kernel( float *gradInput, const float *indice, const float *gradOutput, int inputSize, int outputSize)
{
int tx = threadIdx.x;
int step = blockDim.x;
int k = blockIdx.x;
float *gradInput_k = gradInput + k*inputSize;
const float *gradOutput_k = gradOutput + k*outputSize;
const float *indice_k = indice + k*outputSize;
for (int i=tx; i<outputSize; i+=step)
gradInput_k[(int)(indice_k[i] - 1)] = gradOutput_k[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunnx_LazyKBest_updateGradInput_kernel( float *gradInput, const float *indice, const float *gradOutput, int inputSize, int outputSize)
{
int tx = threadIdx.x;
int step = blockDim.x;
int k = blockIdx.x;
float *gradInput_k = gradInput + k*inputSize;
const float *gradOutput_k = gradOutput + k*outputSize;
const float *indice_k = indice + k*outputSize;
for (int i=tx; i<outputSize; i+=step)
gradInput_k[(int)(indice_k[i] - 1)] = gradOutput_k[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.globl _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.p2align 8
.type _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii,@function
_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii:
s_load_b32 s8, s[0:1], 0x1c
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x3
s_load_b32 s9, s[0:1], 0x18
s_load_b32 s11, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s10, s15, s8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s15, s9
s_and_b32 s9, s11, 0xffff
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[10:11], 2
s_mov_b32 s10, 0
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_lshl_b32 s11, s9, 2
s_mov_b32 s12, s10
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s9, v0
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s11
v_add_co_ci_u32_e32 v2, vcc_lo, s10, v2, vcc_lo
global_load_b32 v6, v[3:4], off
v_cmp_le_i32_e64 s0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s12, s0, s12
s_waitcnt vmcnt(1)
v_add_f32_e32 v3, -1.0, v5
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s1, s4, v3
v_add_co_ci_u32_e64 v4, s1, s5, v4, s1
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v6, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, .Lfunc_end0-_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cunnx_LazyKBest_updateGradInput_kernel( float *gradInput, const float *indice, const float *gradOutput, int inputSize, int outputSize)
{
int tx = threadIdx.x;
int step = blockDim.x;
int k = blockIdx.x;
float *gradInput_k = gradInput + k*inputSize;
const float *gradOutput_k = gradOutput + k*outputSize;
const float *indice_k = indice + k*outputSize;
for (int i=tx; i<outputSize; i+=step)
gradInput_k[(int)(indice_k[i] - 1)] = gradOutput_k[i];
} | .text
.file "cunnx_LazyKBest_updateGradInput_kernel.hip"
.globl _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii # -- Begin function _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.p2align 4, 0x90
.type _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii,@function
_Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii: # @_Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, .Lfunc_end0-_Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii,@object # @_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.section .rodata,"a",@progbits
.globl _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.p2align 3, 0x0
_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii:
.quad _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.size _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R4, R4, c[0x0][0x17c], RZ ; /* 0x00005f0004047a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ BSSY B0, 0x400 ; /* 0x0000035000007945 */
/* 0x000fe40003800000 */
/*00b0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e220000001000 */
/*00c0*/ UIMAD UR4, UR5, UR6, URZ ; /* 0x00000006050472a4 */
/* 0x002fe4000f8e023f */
/*00d0*/ UIMAD UR5, UR5, UR7, URZ ; /* 0x00000007050572a4 */
/* 0x000fc4000f8e023f */
/*00e0*/ USHF.R.S32.HI UR8, URZ, 0x1f, UR4 ; /* 0x0000001f3f087899 */
/* 0x000fe20008011404 */
/*00f0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fe20007ffe0ff */
/*0100*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0110*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR5 ; /* 0x0000001f3f097899 */
/* 0x000fe20008011405 */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0150*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0220*/ LOP3.LUT P1, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000782c0ff */
/*0230*/ @!P1 BRA 0x3f0 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R5, P1, R0, UR5, RZ ; /* 0x0000000500057c10 */
/* 0x000fe2000ff3e0ff */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0002 */
/*0260*/ LEA.HI.X.SX32 R6, R0, UR9, 0x1, P1 ; /* 0x0000000900067c11 */
/* 0x000fe200088f0eff */
/*0270*/ IMAD.SHL.U32 R4, R5, 0x4, RZ ; /* 0x0000000405047824 */
/* 0x000fc600078e00ff */
/*0280*/ SHF.L.U64.HI R5, R5, 0x2, R6 ; /* 0x0000000205057819 */
/* 0x000fe40000010206 */
/*0290*/ IADD3 R10, P1, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a00040a7a10 */
/* 0x040fe40007f3e0ff */
/*02a0*/ IADD3 R4, P2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fe40007f5e0ff */
/*02b0*/ IADD3.X R3, R5.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0005037a10 */
/* 0x040fe40000ffe4ff */
/*02c0*/ IADD3.X R5, R5, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0005057a10 */
/* 0x000fc800017fe4ff */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*02e0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x0000a8000c1e1900 */
/*02f0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x0002e2000c1e1900 */
/*0300*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*0330*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fc800078e0204 */
/*0340*/ IMAD.WIDE R2, R11, 0x4, R2 ; /* 0x000000040b027825 */
/* 0x002fc800078e0202 */
/*0350*/ FADD R10, R6, -1 ; /* 0xbf800000060a7421 */
/* 0x008fcc0000000000 */
/*0360*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e24000020f100 */
/*0370*/ IADD3 R7, P1, R10, UR4, RZ ; /* 0x000000040a077c10 */
/* 0x001fc8000ff3e0ff */
/*0380*/ LEA.HI.X.SX32 R12, R10, UR8, 0x1, P1 ; /* 0x000000080a0c7c11 */
/* 0x000fe400088f0eff */
/*0390*/ LEA R6, P1, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078210ff */
/*03a0*/ LEA.HI.X R7, R7, c[0x0][0x164], R12, 0x2, P1 ; /* 0x0000590007077a11 */
/* 0x000fca00008f140c */
/*03b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0041e2000c101906 */
/*03c0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*03d0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fd800078e0002 */
/*03e0*/ @P1 BRA 0x2d0 ; /* 0xfffffee000001947 */
/* 0x001fea000383ffff */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R3, P0, R0, UR5, RZ ; /* 0x0000000500037c10 */
/* 0x001fc8000ff1e0ff */
/*0420*/ LEA.HI.X.SX32 R2, R0, UR9, 0x1, P0 ; /* 0x0000000900027c11 */
/* 0x000fe200080f0eff */
/*0430*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fc600078e00ff */
/*0440*/ SHF.L.U64.HI R3, R3, 0x2, R2 ; /* 0x0000000203037819 */
/* 0x000fe40000010202 */
/*0450*/ IADD3 R6, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004067a10 */
/* 0x000fc80007f1e0ff */
/*0460*/ IADD3.X R7, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x000fca00007fe4ff */
/*0470*/ LDG.E R2, [R6.64] ; /* 0x0000000606027981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R4, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fc80007f1e0ff */
/*0490*/ IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003057a10 */
/* 0x000fca00007fe4ff */
/*04a0*/ LDG.E R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ FADD R8, R2, -1 ; /* 0xbf80000002087421 */
/* 0x004fe40000000000 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fc800078e00ff */
/*04d0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e22000020f100 */
/*04e0*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fe200078e0206 */
/*04f0*/ IADD3 R9, P0, R8, UR4, RZ ; /* 0x0000000408097c10 */
/* 0x001fc8000ff1e0ff */
/*0500*/ LEA.HI.X.SX32 R12, R8, UR8, 0x1, P0 ; /* 0x00000008080c7c11 */
/* 0x000fe400080f0eff */
/*0510*/ LEA R10, P0, R9, c[0x0][0x160], 0x2 ; /* 0x00005800090a7a11 */
/* 0x000fc800078010ff */
/*0520*/ LEA.HI.X R11, R9, c[0x0][0x164], R12, 0x2, P0 ; /* 0x00005900090b7a11 */
/* 0x000fca00000f140c */
/*0530*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x0081e8000c101906 */
/*0540*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x000fca00078e0204 */
/*0560*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ee2000c1e1900 */
/*0570*/ FADD R14, R9, -1 ; /* 0xbf800000090e7421 */
/* 0x004fcc0000000000 */
/*0580*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000e64000020f100 */
/*0590*/ IADD3 R8, P0, R14, UR4, RZ ; /* 0x000000040e087c10 */
/* 0x002fc8000ff1e0ff */
/*05a0*/ LEA.HI.X.SX32 R9, R14, UR8, 0x1, P0 ; /* 0x000000080e097c11 */
/* 0x000fe400080f0eff */
/*05b0*/ LEA R12, P0, R8, c[0x0][0x160], 0x2 ; /* 0x00005800080c7a11 */
/* 0x000fc800078010ff */
/*05c0*/ LEA.HI.X R13, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x00005900080d7a11 */
/* 0x000fe200000f1409 */
/*05d0*/ IMAD.WIDE R8, R2, 0x4, R6 ; /* 0x0000000402087825 */
/* 0x000fc800078e0206 */
/*05e0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0083e8000c101906 */
/*05f0*/ LDG.E R3, [R8.64] ; /* 0x0000000608037981 */
/* 0x001ea2000c1e1900 */
/*0600*/ IMAD.WIDE R6, R2, 0x4, R4 ; /* 0x0000000402067825 */
/* 0x000fca00078e0204 */
/*0610*/ LDG.E R17, [R6.64] ; /* 0x0000000606117981 */
/* 0x000ee2000c1e1900 */
/*0620*/ FADD R16, R3, -1 ; /* 0xbf80000003107421 */
/* 0x004fcc0000000000 */
/*0630*/ F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000107305 */
/* 0x000e24000020f100 */
/*0640*/ IADD3 R3, P0, R16, UR4, RZ ; /* 0x0000000410037c10 */
/* 0x001fc8000ff1e0ff */
/*0650*/ LEA.HI.X.SX32 R4, R16, UR8, 0x1, P0 ; /* 0x0000000810047c11 */
/* 0x000fe400080f0eff */
/*0660*/ LEA R10, P0, R3, c[0x0][0x160], 0x2 ; /* 0x00005800030a7a11 */
/* 0x000fc800078010ff */
/*0670*/ LEA.HI.X R11, R3, c[0x0][0x164], R4, 0x2, P0 ; /* 0x00005900030b7a11 */
/* 0x000fe200000f1404 */
/*0680*/ IMAD.WIDE R4, R2, 0x4, R8 ; /* 0x0000000402047825 */
/* 0x000fc800078e0208 */
/*0690*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0081e8000c101906 */
/*06a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0004e2000c1e1900 */
/*06b0*/ IMAD.WIDE R2, R2, 0x4, R6 ; /* 0x0000000402027825 */
/* 0x000fcc00078e0206 */
/*06c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000f22000c1e1900 */
/*06d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x004fe400078e00ff */
/*06f0*/ IMAD R0, R9, 0x2, R0 ; /* 0x0000000209007824 */
/* 0x000fc800078e0200 */
/*0700*/ IMAD R0, R5, 0x2, R0 ; /* 0x0000000205007824 */
/* 0x000fe400078e0200 */
/*0710*/ FADD R8, R4, -1 ; /* 0xbf80000004087421 */
/* 0x008fcc0000000000 */
/*0720*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000ea4000020f100 */
/*0730*/ IADD3 R7, P0, R8, UR4, RZ ; /* 0x0000000408077c10 */
/* 0x004fc8000ff1e0ff */
/*0740*/ LEA.HI.X.SX32 R12, R8, UR8, 0x1, P0 ; /* 0x00000008080c7c11 */
/* 0x002fe400080f0eff */
/*0750*/ LEA R6, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078010ff */
/*0760*/ LEA.HI.X R7, R7, c[0x0][0x164], R12, 0x2, P0 ; /* 0x0000590007077a11 */
/* 0x000fe400000f140c */
/*0770*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc60003f06270 */
/*0780*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0101f4000c101906 */
/*0790*/ @!P0 BRA 0x410 ; /* 0xfffffc7000008947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.globl _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.p2align 8
.type _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii,@function
_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii:
s_load_b32 s8, s[0:1], 0x1c
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x3
s_load_b32 s9, s[0:1], 0x18
s_load_b32 s11, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s10, s15, s8
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s15, s9
s_and_b32 s9, s11, 0xffff
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[10:11], 2
s_mov_b32 s10, 0
v_add_co_u32 v1, s0, s0, v1
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_lshl_b32 s11, s9, 2
s_mov_b32 s12, s10
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s9, v0
global_load_b32 v5, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s11
v_add_co_ci_u32_e32 v2, vcc_lo, s10, v2, vcc_lo
global_load_b32 v6, v[3:4], off
v_cmp_le_i32_e64 s0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s12, s0, s12
s_waitcnt vmcnt(1)
v_add_f32_e32 v3, -1.0, v5
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s1, s4, v3
v_add_co_ci_u32_e64 v4, s1, s5, v4, s1
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v6, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, .Lfunc_end0-_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00163be7_00000000-6_cunnx_LazyKBest_updateGradInput_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii
.type _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii, @function
_Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii, .-_Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii
.globl _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.type _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, @function
_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_iiPfPKfS1_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, .-_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cunnx_LazyKBest_updateGradInput_kernel.hip"
.globl _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii # -- Begin function _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.p2align 4, 0x90
.type _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii,@function
_Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii: # @_Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, .Lfunc_end0-_Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii,@object # @_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.section .rodata,"a",@progbits
.globl _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.p2align 3, 0x0
_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii:
.quad _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.size _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z53__device_stub__cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z38cunnx_LazyKBest_updateGradInput_kernelPfPKfS1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void ReducePI(
float* d_sum,
int num
);
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
);
int __main()
{
return 0;
}
__global__ void ReducePI(
float* d_sum,
int num
){
int id = blockIdx.x * blockDim.x + threadIdx.x;
int gid = id;
float temp;
extern float __shared__ s_pi[];
s_pi[threadIdx.x] = 0.f;
while(gid < num){
temp = (gid + 0.5) / num;
s_pi[threadIdx.x] += 4.0f / (1 + temp*temp);
gid = blockDim.x * gridDim.x;
}
for(int i=(blockIdx.x >> 1); i>0; i++){
if(threadIdx.x < i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
if(threadIdx.x == 0){
d_sum[blockIdx.x] = s_pi[0];
}
}
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
){
int id=threadIdx.x;
extern float __shared__ s_sum[];
s_sum[id]=d_sum[id];
__syncthreads();
for(int i=(blockDim.x>>1);i>0;i>>=1){
if(id<i)
s_sum[id]+=s_sum[id+i];
__syncthreads();
}
printf("%d,%f\n",id,s_sum[id]);
if(id==0){
*d_pi=s_sum[0]/num;
printf("%d,%f\n",id,*d_pi);
}
} | .file "tmpxft_0000c2ba_00000000-6_GpuPI.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6__mainv
.type _Z6__mainv, @function
_Z6__mainv:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z6__mainv, .-_Z6__mainv
.globl _Z28__device_stub__Z8ReducePIPfiPfi
.type _Z28__device_stub__Z8ReducePIPfiPfi, @function
_Z28__device_stub__Z8ReducePIPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8ReducePIPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8ReducePIPfiPfi, .-_Z28__device_stub__Z8ReducePIPfiPfi
.globl _Z8ReducePIPfi
.type _Z8ReducePIPfi, @function
_Z8ReducePIPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8ReducePIPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8ReducePIPfi, .-_Z8ReducePIPfi
.globl _Z31__device_stub__Z9ReducePI2PfiS_PfiS_
.type _Z31__device_stub__Z9ReducePI2PfiS_PfiS_, @function
_Z31__device_stub__Z9ReducePI2PfiS_PfiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9ReducePI2PfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z9ReducePI2PfiS_PfiS_, .-_Z31__device_stub__Z9ReducePI2PfiS_PfiS_
.globl _Z9ReducePI2PfiS_
.type _Z9ReducePI2PfiS_, @function
_Z9ReducePI2PfiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9ReducePI2PfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9ReducePI2PfiS_, .-_Z9ReducePI2PfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9ReducePI2PfiS_"
.LC1:
.string "_Z8ReducePIPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ReducePI2PfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8ReducePIPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void ReducePI(
float* d_sum,
int num
);
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
);
int __main()
{
return 0;
}
__global__ void ReducePI(
float* d_sum,
int num
){
int id = blockIdx.x * blockDim.x + threadIdx.x;
int gid = id;
float temp;
extern float __shared__ s_pi[];
s_pi[threadIdx.x] = 0.f;
while(gid < num){
temp = (gid + 0.5) / num;
s_pi[threadIdx.x] += 4.0f / (1 + temp*temp);
gid = blockDim.x * gridDim.x;
}
for(int i=(blockIdx.x >> 1); i>0; i++){
if(threadIdx.x < i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
if(threadIdx.x == 0){
d_sum[blockIdx.x] = s_pi[0];
}
}
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
){
int id=threadIdx.x;
extern float __shared__ s_sum[];
s_sum[id]=d_sum[id];
__syncthreads();
for(int i=(blockDim.x>>1);i>0;i>>=1){
if(id<i)
s_sum[id]+=s_sum[id+i];
__syncthreads();
}
printf("%d,%f\n",id,s_sum[id]);
if(id==0){
*d_pi=s_sum[0]/num;
printf("%d,%f\n",id,*d_pi);
}
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void ReducePI(
float* d_sum,
int num
);
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
);
int __main()
{
return 0;
}
__global__ void ReducePI(
float* d_sum,
int num
){
int id = blockIdx.x * blockDim.x + threadIdx.x;
int gid = id;
float temp;
extern float __shared__ s_pi[];
s_pi[threadIdx.x] = 0.f;
while(gid < num){
temp = (gid + 0.5) / num;
s_pi[threadIdx.x] += 4.0f / (1 + temp*temp);
gid = blockDim.x * gridDim.x;
}
for(int i=(blockIdx.x >> 1); i>0; i++){
if(threadIdx.x < i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
if(threadIdx.x == 0){
d_sum[blockIdx.x] = s_pi[0];
}
}
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
){
int id=threadIdx.x;
extern float __shared__ s_sum[];
s_sum[id]=d_sum[id];
__syncthreads();
for(int i=(blockDim.x>>1);i>0;i>>=1){
if(id<i)
s_sum[id]+=s_sum[id+i];
__syncthreads();
}
printf("%d,%f\n",id,s_sum[id]);
if(id==0){
*d_pi=s_sum[0]/num;
printf("%d,%f\n",id,*d_pi);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void ReducePI(
float* d_sum,
int num
);
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
);
int __main()
{
return 0;
}
__global__ void ReducePI(
float* d_sum,
int num
){
int id = blockIdx.x * blockDim.x + threadIdx.x;
int gid = id;
float temp;
extern float __shared__ s_pi[];
s_pi[threadIdx.x] = 0.f;
while(gid < num){
temp = (gid + 0.5) / num;
s_pi[threadIdx.x] += 4.0f / (1 + temp*temp);
gid = blockDim.x * gridDim.x;
}
for(int i=(blockIdx.x >> 1); i>0; i++){
if(threadIdx.x < i){
s_pi[threadIdx.x] += s_pi[threadIdx.x+i];
}
__syncthreads();
}
if(threadIdx.x == 0){
d_sum[blockIdx.x] = s_pi[0];
}
}
__global__ void ReducePI2(
float* d_sum,
int num,
float* d_pi
){
int id=threadIdx.x;
extern float __shared__ s_sum[];
s_sum[id]=d_sum[id];
__syncthreads();
for(int i=(blockDim.x>>1);i>0;i>>=1){
if(id<i)
s_sum[id]+=s_sum[id+i];
__syncthreads();
}
printf("%d,%f\n",id,s_sum[id]);
if(id==0){
*d_pi=s_sum[0]/num;
printf("%d,%f\n",id,*d_pi);
}
} | .text
.file "GpuPI.hip"
.globl _Z6__mainv # -- Begin function _Z6__mainv
.p2align 4, 0x90
.type _Z6__mainv,@function
_Z6__mainv: # @_Z6__mainv
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z6__mainv, .Lfunc_end0-_Z6__mainv
.cfi_endproc
# -- End function
.globl _Z23__device_stub__ReducePIPfi # -- Begin function _Z23__device_stub__ReducePIPfi
.p2align 4, 0x90
.type _Z23__device_stub__ReducePIPfi,@function
_Z23__device_stub__ReducePIPfi: # @_Z23__device_stub__ReducePIPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8ReducePIPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__ReducePIPfi, .Lfunc_end1-_Z23__device_stub__ReducePIPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__ReducePI2PfiS_ # -- Begin function _Z24__device_stub__ReducePI2PfiS_
.p2align 4, 0x90
.type _Z24__device_stub__ReducePI2PfiS_,@function
_Z24__device_stub__ReducePI2PfiS_: # @_Z24__device_stub__ReducePI2PfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9ReducePI2PfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__ReducePI2PfiS_, .Lfunc_end2-_Z24__device_stub__ReducePI2PfiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8ReducePIPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ReducePI2PfiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8ReducePIPfi,@object # @_Z8ReducePIPfi
.section .rodata,"a",@progbits
.globl _Z8ReducePIPfi
.p2align 3, 0x0
_Z8ReducePIPfi:
.quad _Z23__device_stub__ReducePIPfi
.size _Z8ReducePIPfi, 8
.type _Z9ReducePI2PfiS_,@object # @_Z9ReducePI2PfiS_
.globl _Z9ReducePI2PfiS_
.p2align 3, 0x0
_Z9ReducePI2PfiS_:
.quad _Z24__device_stub__ReducePI2PfiS_
.size _Z9ReducePI2PfiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8ReducePIPfi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9ReducePI2PfiS_"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__ReducePIPfi
.addrsig_sym _Z24__device_stub__ReducePI2PfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8ReducePIPfi
.addrsig_sym _Z9ReducePI2PfiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000c2ba_00000000-6_GpuPI.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6__mainv
.type _Z6__mainv, @function
_Z6__mainv:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z6__mainv, .-_Z6__mainv
.globl _Z28__device_stub__Z8ReducePIPfiPfi
.type _Z28__device_stub__Z8ReducePIPfiPfi, @function
_Z28__device_stub__Z8ReducePIPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8ReducePIPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z8ReducePIPfiPfi, .-_Z28__device_stub__Z8ReducePIPfiPfi
.globl _Z8ReducePIPfi
.type _Z8ReducePIPfi, @function
_Z8ReducePIPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8ReducePIPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8ReducePIPfi, .-_Z8ReducePIPfi
.globl _Z31__device_stub__Z9ReducePI2PfiS_PfiS_
.type _Z31__device_stub__Z9ReducePI2PfiS_PfiS_, @function
_Z31__device_stub__Z9ReducePI2PfiS_PfiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9ReducePI2PfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z9ReducePI2PfiS_PfiS_, .-_Z31__device_stub__Z9ReducePI2PfiS_PfiS_
.globl _Z9ReducePI2PfiS_
.type _Z9ReducePI2PfiS_, @function
_Z9ReducePI2PfiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9ReducePI2PfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9ReducePI2PfiS_, .-_Z9ReducePI2PfiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9ReducePI2PfiS_"
.LC1:
.string "_Z8ReducePIPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ReducePI2PfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8ReducePIPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GpuPI.hip"
.globl _Z6__mainv # -- Begin function _Z6__mainv
.p2align 4, 0x90
.type _Z6__mainv,@function
_Z6__mainv: # @_Z6__mainv
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z6__mainv, .Lfunc_end0-_Z6__mainv
.cfi_endproc
# -- End function
.globl _Z23__device_stub__ReducePIPfi # -- Begin function _Z23__device_stub__ReducePIPfi
.p2align 4, 0x90
.type _Z23__device_stub__ReducePIPfi,@function
_Z23__device_stub__ReducePIPfi: # @_Z23__device_stub__ReducePIPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8ReducePIPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__ReducePIPfi, .Lfunc_end1-_Z23__device_stub__ReducePIPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__ReducePI2PfiS_ # -- Begin function _Z24__device_stub__ReducePI2PfiS_
.p2align 4, 0x90
.type _Z24__device_stub__ReducePI2PfiS_,@function
_Z24__device_stub__ReducePI2PfiS_: # @_Z24__device_stub__ReducePI2PfiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9ReducePI2PfiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__ReducePI2PfiS_, .Lfunc_end2-_Z24__device_stub__ReducePI2PfiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8ReducePIPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ReducePI2PfiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8ReducePIPfi,@object # @_Z8ReducePIPfi
.section .rodata,"a",@progbits
.globl _Z8ReducePIPfi
.p2align 3, 0x0
_Z8ReducePIPfi:
.quad _Z23__device_stub__ReducePIPfi
.size _Z8ReducePIPfi, 8
.type _Z9ReducePI2PfiS_,@object # @_Z9ReducePI2PfiS_
.globl _Z9ReducePI2PfiS_
.p2align 3, 0x0
_Z9ReducePI2PfiS_:
.quad _Z24__device_stub__ReducePI2PfiS_
.size _Z9ReducePI2PfiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8ReducePIPfi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9ReducePI2PfiS_"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__ReducePIPfi
.addrsig_sym _Z24__device_stub__ReducePI2PfiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8ReducePIPfi
.addrsig_sym _Z9ReducePI2PfiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void shared1R8C1W1G1RG(float *A, float *B, float *C, const int N)
{
// compilador é esperto e aproveita o valor de i, mas faz 1W, 2 R nas outras posições da Shared
__shared__ float Smem[512];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
Smem[(threadIdx.x+1)%512] = A[i];
C[i] = Smem[(threadIdx.x*8)%512];
}
/*if ( blockIdx.x == 2 && threadIdx.x < 32 ) {
printf("th %d smem %d\n",threadIdx.x,(threadIdx.x*8)%512);
}*/
} | code for sm_80
Function : _Z17shared1R8C1W1G1RGPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e020b */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA R0, R5.reuse, 0x4, 0x2 ; /* 0x0000000405007811 */
/* 0x040fe200078e10ff */
/*00b0*/ IMAD.SHL.U32 R5, R5, 0x20, RZ ; /* 0x0000002005057824 */
/* 0x000fc600078e00ff */
/*00c0*/ LOP3.LUT R7, R0, 0x7fc, RZ, 0xc0, !PT ; /* 0x000007fc00077812 */
/* 0x000fe400078ec0ff */
/*00d0*/ LOP3.LUT R0, R5, 0x7e0, RZ, 0xc0, !PT ; /* 0x000007e005007812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e020b */
/*00f0*/ STS [R7], R2 ; /* 0x0000000207007388 */
/* 0x004fe80000000800 */
/*0100*/ LDS R9, [R0] ; /* 0x0000000000097984 */
/* 0x000e280000000800 */
/*0110*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void shared1R8C1W1G1RG(float *A, float *B, float *C, const int N)
{
// compilador é esperto e aproveita o valor de i, mas faz 1W, 2 R nas outras posições da Shared
__shared__ float Smem[512];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
Smem[(threadIdx.x+1)%512] = A[i];
C[i] = Smem[(threadIdx.x*8)%512];
}
/*if ( blockIdx.x == 2 && threadIdx.x < 32 ) {
printf("th %d smem %d\n",threadIdx.x,(threadIdx.x*8)%512);
}*/
} | .file "tmpxft_0007212c_00000000-6_shared1R8C1W1G1RG.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17shared1R8C1W1G1RGPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i
.globl _Z17shared1R8C1W1G1RGPfS_S_i
.type _Z17shared1R8C1W1G1RGPfS_S_i, @function
_Z17shared1R8C1W1G1RGPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17shared1R8C1W1G1RGPfS_S_i, .-_Z17shared1R8C1W1G1RGPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17shared1R8C1W1G1RGPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17shared1R8C1W1G1RGPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void shared1R8C1W1G1RG(float *A, float *B, float *C, const int N)
{
// compilador é esperto e aproveita o valor de i, mas faz 1W, 2 R nas outras posições da Shared
__shared__ float Smem[512];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
Smem[(threadIdx.x+1)%512] = A[i];
C[i] = Smem[(threadIdx.x*8)%512];
}
/*if ( blockIdx.x == 2 && threadIdx.x < 32 ) {
printf("th %d smem %d\n",threadIdx.x,(threadIdx.x*8)%512);
}*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void shared1R8C1W1G1RG(float *A, float *B, float *C, const int N)
{
// compilador é esperto e aproveita o valor de i, mas faz 1W, 2 R nas outras posições da Shared
__shared__ float Smem[512];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
Smem[(threadIdx.x+1)%512] = A[i];
C[i] = Smem[(threadIdx.x*8)%512];
}
/*if ( blockIdx.x == 2 && threadIdx.x < 32 ) {
printf("th %d smem %d\n",threadIdx.x,(threadIdx.x*8)%512);
}*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void shared1R8C1W1G1RG(float *A, float *B, float *C, const int N)
{
// compilador é esperto e aproveita o valor de i, mas faz 1W, 2 R nas outras posições da Shared
__shared__ float Smem[512];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
Smem[(threadIdx.x+1)%512] = A[i];
C[i] = Smem[(threadIdx.x*8)%512];
}
/*if ( blockIdx.x == 2 && threadIdx.x < 32 ) {
printf("th %d smem %d\n",threadIdx.x,(threadIdx.x*8)%512);
}*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17shared1R8C1W1G1RGPfS_S_i
.globl _Z17shared1R8C1W1G1RGPfS_S_i
.p2align 8
.type _Z17shared1R8C1W1G1RGPfS_S_i,@function
_Z17shared1R8C1W1G1RGPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_nc_u32_e32 v4, 1, v0
v_lshlrev_b32_e32 v0, 5, v0
v_and_b32_e32 v4, 0x1ff, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 0x7e0, v0
v_lshlrev_b32_e32 v4, 2, v4
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
ds_load_b32 v3, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17shared1R8C1W1G1RGPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17shared1R8C1W1G1RGPfS_S_i, .Lfunc_end0-_Z17shared1R8C1W1G1RGPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17shared1R8C1W1G1RGPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17shared1R8C1W1G1RGPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void shared1R8C1W1G1RG(float *A, float *B, float *C, const int N)
{
// compilador é esperto e aproveita o valor de i, mas faz 1W, 2 R nas outras posições da Shared
__shared__ float Smem[512];
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
Smem[(threadIdx.x+1)%512] = A[i];
C[i] = Smem[(threadIdx.x*8)%512];
}
/*if ( blockIdx.x == 2 && threadIdx.x < 32 ) {
printf("th %d smem %d\n",threadIdx.x,(threadIdx.x*8)%512);
}*/
} | .text
.file "shared1R8C1W1G1RG.hip"
.globl _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i # -- Begin function _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i,@function
_Z32__device_stub__shared1R8C1W1G1RGPfS_S_i: # @_Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17shared1R8C1W1G1RGPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i, .Lfunc_end0-_Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17shared1R8C1W1G1RGPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17shared1R8C1W1G1RGPfS_S_i,@object # @_Z17shared1R8C1W1G1RGPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17shared1R8C1W1G1RGPfS_S_i
.p2align 3, 0x0
_Z17shared1R8C1W1G1RGPfS_S_i:
.quad _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.size _Z17shared1R8C1W1G1RGPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17shared1R8C1W1G1RGPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17shared1R8C1W1G1RGPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17shared1R8C1W1G1RGPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R11, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e020b */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA R0, R5.reuse, 0x4, 0x2 ; /* 0x0000000405007811 */
/* 0x040fe200078e10ff */
/*00b0*/ IMAD.SHL.U32 R5, R5, 0x20, RZ ; /* 0x0000002005057824 */
/* 0x000fc600078e00ff */
/*00c0*/ LOP3.LUT R7, R0, 0x7fc, RZ, 0xc0, !PT ; /* 0x000007fc00077812 */
/* 0x000fe400078ec0ff */
/*00d0*/ LOP3.LUT R0, R5, 0x7e0, RZ, 0xc0, !PT ; /* 0x000007e005007812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e020b */
/*00f0*/ STS [R7], R2 ; /* 0x0000000207007388 */
/* 0x004fe80000000800 */
/*0100*/ LDS R9, [R0] ; /* 0x0000000000097984 */
/* 0x000e280000000800 */
/*0110*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17shared1R8C1W1G1RGPfS_S_i
.globl _Z17shared1R8C1W1G1RGPfS_S_i
.p2align 8
.type _Z17shared1R8C1W1G1RGPfS_S_i,@function
_Z17shared1R8C1W1G1RGPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_nc_u32_e32 v4, 1, v0
v_lshlrev_b32_e32 v0, 5, v0
v_and_b32_e32 v4, 0x1ff, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 0x7e0, v0
v_lshlrev_b32_e32 v4, 2, v4
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
ds_load_b32 v3, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17shared1R8C1W1G1RGPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17shared1R8C1W1G1RGPfS_S_i, .Lfunc_end0-_Z17shared1R8C1W1G1RGPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17shared1R8C1W1G1RGPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17shared1R8C1W1G1RGPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007212c_00000000-6_shared1R8C1W1G1RG.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17shared1R8C1W1G1RGPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i
.globl _Z17shared1R8C1W1G1RGPfS_S_i
.type _Z17shared1R8C1W1G1RGPfS_S_i, @function
_Z17shared1R8C1W1G1RGPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17shared1R8C1W1G1RGPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17shared1R8C1W1G1RGPfS_S_i, .-_Z17shared1R8C1W1G1RGPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17shared1R8C1W1G1RGPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17shared1R8C1W1G1RGPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shared1R8C1W1G1RG.hip"
.globl _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i # -- Begin function _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i,@function
_Z32__device_stub__shared1R8C1W1G1RGPfS_S_i: # @_Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17shared1R8C1W1G1RGPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i, .Lfunc_end0-_Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17shared1R8C1W1G1RGPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17shared1R8C1W1G1RGPfS_S_i,@object # @_Z17shared1R8C1W1G1RGPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17shared1R8C1W1G1RGPfS_S_i
.p2align 3, 0x0
_Z17shared1R8C1W1G1RGPfS_S_i:
.quad _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.size _Z17shared1R8C1W1G1RGPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17shared1R8C1W1G1RGPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__shared1R8C1W1G1RGPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17shared1R8C1W1G1RGPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* KERNEL d_MM() - Takes two 2D matrices and multiplies them
* Result is divided into threads, each thread iterating over datasets
* to obtain the final answer. C[Thread] = Sum { A column * B Row }
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM(float *a, float *b, float *c, int wA, int wB, int hA)
{
// global index
int gidx = blockDim.x * blockIdx.x + threadIdx.x; // col
int gidy = blockDim.y * blockIdx.y + threadIdx.y; // row
if(gidx < wB && gidy < hA)
{
float sum = 0.f;
for(int k=0; k<wA; k++)
{
// Multiply row of A by column of B
sum += a[gidy*wA + k] * b[k*wB +gidx];
}
c[gidy * wB + gidx] = sum;
}
}
/**
* KERNEL d_MM_OPT() - Takes two 2D matrices and multiplies them optimally
* Output set is divided into blocks of powers of two.
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM_OPT(
float *a,
float *b,
float *c,
int wA,
int wB,
int hA)
{
#define blockTile 16
/* Blocksize is 16x16 */
/* Allocate shared memory */
__shared__ float aBlock[blockTile][blockTile];
__shared__ float bBlock[blockTile][blockTile];
/* Calculate global index X, Y */
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = blockDim.x * bx + tx; // column
int gy = blockDim.y * by + ty; // row
/* Compute offset idx for A & B */
// First A index (row shift) Block.row * Block.width * A.width
int a0 = wA * 16 * by;
// aBegin -> last element in row -> + width - 1
int aZ = a0 + wA - 1;
// Column block iteration = blockDim.x
int aD = 16;
// b_0 -> Column Shift
int b0 = 16 * bx;
// Row block iteration = blockDim.y * width B
int bD = 16 * wB;
float sum = 0.f;
for(int aI = a0, bI = b0; aI <= aZ; aI += aD, bI += bD)
{
/* Assign shared memory and sync */
/* Warning, wA*gidy may be out of bounds */
aBlock[ty][tx] = a[aI + ty*wA + tx];
bBlock[ty][tx] = b[bI + ty*wB + tx];
/* Make sure all of the threads have updated the memory cache */
__syncthreads();
/* Sum over NK */
for(int k=0; k < 16; k++)
{
/* C = (A x B) */
sum += aBlock[ty][k] * bBlock[k][tx];
}
}
c[gy*wB + gx] = sum;
//c[i * NJ + j] = ALPHA*sum + BETA*c[i * NJ + j];
} | code for sm_80
Function : _Z8d_MM_OPTPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R16, SR_CTAID.Y ; /* 0x0000000000107919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R16, c[0x0][0x4], R3 ; /* 0x0000010010007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R7, c[0x0][0x0], R2 ; /* 0x0000000007037a24 */
/* 0x002fe200078e0202 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*00c0*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fce00078e0203 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fe200078e0202 */
/*00e0*/ @!P0 BRA 0x4f0 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*00f0*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e220000002200 */
/*0100*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x000fe20000000f00 */
/*0120*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0130*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*0140*/ SHF.L.U32 R19, R19, 0x4, RZ ; /* 0x0000000413137819 */
/* 0x000fe400000006ff */
/*0150*/ LEA R5, R16.reuse, R17, 0x4 ; /* 0x0000001110057211 */
/* 0x041fe200078e20ff */
/*0160*/ IMAD R16, R16, c[0x0][0x178], RZ ; /* 0x00005e0010107a24 */
/* 0x000fc400078e02ff */
/*0170*/ IMAD R4, R17.reuse, c[0x0][0x17c], R0.reuse ; /* 0x00005f0011047a24 */
/* 0x142fe200078e0200 */
/*0180*/ SHF.L.U32 R17, R17, 0x6, RZ ; /* 0x0000000611117819 */
/* 0x000fe200000006ff */
/*0190*/ IMAD R5, R5, c[0x0][0x178], R0 ; /* 0x00005e0005057a24 */
/* 0x000fe200078e0200 */
/*01a0*/ SHF.L.U32 R16, R16, 0x4, RZ ; /* 0x0000000410107819 */
/* 0x000fe400000006ff */
/*01b0*/ LEA R4, R7, R4, 0x4 ; /* 0x0000000407047211 */
/* 0x000fe200078e20ff */
/*01c0*/ IMAD.WIDE R14, R5, R12.reuse, c[0x0][0x160] ; /* 0x00005800050e7625 */
/* 0x080fe200078e020c */
/*01d0*/ LEA R18, R0, R17, 0x2 ; /* 0x0000001100127211 */
/* 0x000fe400078e10ff */
/*01e0*/ IADD3 R21, R16, c[0x0][0x178], RZ ; /* 0x00005e0010157a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.WIDE R12, R4, R12, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fca00078e020c */
/*0200*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x0000a8000c1e1900 */
/*0210*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0002e2000c1e1900 */
/*0220*/ IADD3 R16, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GE.AND P0, PT, R16, R21, PT ; /* 0x000000151000720c */
/* 0x000fe20003f06270 */
/*0240*/ IMAD.WIDE R12, R19, 0x4, R12 ; /* 0x00000004130c7825 */
/* 0x001fe200078e020c */
/*0250*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x002fc80007f3e0ff */
/*0260*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0270*/ STS [R18+0x400], R22 ; /* 0x0004001612007388 */
/* 0x004fe80000000800 */
/*0280*/ STS [R18], R27 ; /* 0x0000001b12007388 */
/* 0x008fe80000000800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDS R24, [R0.X4+0x400] ; /* 0x0004000000187984 */
/* 0x000fe80000004800 */
/*02b0*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*02c0*/ LDS R26, [R0.X4+0x440] ; /* 0x00044000001a7984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R29, [R0.X4+0x480] ; /* 0x00048000001d7984 */
/* 0x000ea80000004800 */
/*02e0*/ LDS R20, [R0.X4+0x4c0] ; /* 0x0004c00000147984 */
/* 0x000ee80000004800 */
/*02f0*/ LDS R25, [R0.X4+0x500] ; /* 0x0005000000197984 */
/* 0x000fe80000004800 */
/*0300*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0310*/ LDS R22, [R0.X4+0x540] ; /* 0x0005400000167984 */
/* 0x000f680000004800 */
/*0320*/ LDS R27, [R0.X4+0x580] ; /* 0x00058000001b7984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R8, R24, R8, R23 ; /* 0x0000000818087223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R24, [R0.X4+0x5c0] ; /* 0x0005c00000187984 */
/* 0x000e220000004800 */
/*0350*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc60000000008 */
/*0360*/ LDS R23, [R0.X4+0x600] ; /* 0x0006000000177984 */
/* 0x000fe20000004800 */
/*0370*/ FFMA R8, R29, R10, R8 ; /* 0x0000000a1d087223 */
/* 0x004fc80000000008 */
/*0380*/ FFMA R20, R20, R11, R8 ; /* 0x0000000b14147223 */
/* 0x008fe40000000008 */
/*0390*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e640000000c00 */
/*03a0*/ FFMA R4, R25, R4, R20 ; /* 0x0000000419047223 */
/* 0x010fe40000000014 */
/*03b0*/ LDS R20, [R0.X4+0x640] ; /* 0x0006400000147984 */
/* 0x000ea40000004800 */
/*03c0*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x020fe40000000004 */
/*03d0*/ LDS R25, [R0.X4+0x680] ; /* 0x0006800000197984 */
/* 0x000ee40000004800 */
/*03e0*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc40000000004 */
/*03f0*/ LDS R22, [R0.X4+0x6c0] ; /* 0x0006c00000167984 */
/* 0x000f280000004800 */
/*0400*/ LDS R27, [R0.X4+0x700] ; /* 0x00070000001b7984 */
/* 0x000fe20000004800 */
/*0410*/ FFMA R24, R24, R7, R4 ; /* 0x0000000718187223 */
/* 0x001fc60000000004 */
/*0420*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000e220000000c00 */
/*0430*/ FFMA R24, R23, R8, R24 ; /* 0x0000000817187223 */
/* 0x002fc60000000018 */
/*0440*/ LDS R8, [R0.X4+0x740] ; /* 0x0007400000087984 */
/* 0x000e680000004800 */
/*0450*/ LDS R23, [R0.X4+0x780] ; /* 0x0007800000177984 */
/* 0x000f620000004800 */
/*0460*/ FFMA R9, R20, R9, R24 ; /* 0x0000000914097223 */
/* 0x004fc60000000018 */
/*0470*/ LDS R20, [R0.X4+0x7c0] ; /* 0x0007c00000147984 */
/* 0x000ea20000004800 */
/*0480*/ FFMA R9, R25, R10, R9 ; /* 0x0000000a19097223 */
/* 0x008fc80000000009 */
/*0490*/ FFMA R9, R22, R11, R9 ; /* 0x0000000b16097223 */
/* 0x010fc80000000009 */
/*04a0*/ FFMA R4, R27, R4, R9 ; /* 0x000000041b047223 */
/* 0x001fc80000000009 */
/*04b0*/ FFMA R4, R8, R5, R4 ; /* 0x0000000508047223 */
/* 0x002fc80000000004 */
/*04c0*/ FFMA R23, R23, R6, R4 ; /* 0x0000000617177223 */
/* 0x020fc80000000004 */
/*04d0*/ FFMA R23, R20, R7, R23 ; /* 0x0000000714177223 */
/* 0x004fe20000000017 */
/*04e0*/ @!P0 BRA 0x200 ; /* 0xfffffd1000008947 */
/* 0x000fea000383ffff */
/*04f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101904 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4d_MMPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fcc00078e0208 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R0, c[0x0][0x178], R2 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x17c], R3 ; /* 0x00005f0002027a24 */
/* 0x000fce00078e0203 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fc800078e0203 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* KERNEL d_MM() - Takes two 2D matrices and multiplies them
* Result is divided into threads, each thread iterating over datasets
* to obtain the final answer. C[Thread] = Sum { A column * B Row }
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM(float *a, float *b, float *c, int wA, int wB, int hA)
{
// global index
int gidx = blockDim.x * blockIdx.x + threadIdx.x; // col
int gidy = blockDim.y * blockIdx.y + threadIdx.y; // row
if(gidx < wB && gidy < hA)
{
float sum = 0.f;
for(int k=0; k<wA; k++)
{
// Multiply row of A by column of B
sum += a[gidy*wA + k] * b[k*wB +gidx];
}
c[gidy * wB + gidx] = sum;
}
}
/**
* KERNEL d_MM_OPT() - Takes two 2D matrices and multiplies them optimally
* Output set is divided into blocks of powers of two.
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM_OPT(
float *a,
float *b,
float *c,
int wA,
int wB,
int hA)
{
#define blockTile 16
/* Blocksize is 16x16 */
/* Allocate shared memory */
__shared__ float aBlock[blockTile][blockTile];
__shared__ float bBlock[blockTile][blockTile];
/* Calculate global index X, Y */
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = blockDim.x * bx + tx; // column
int gy = blockDim.y * by + ty; // row
/* Compute offset idx for A & B */
// First A index (row shift) Block.row * Block.width * A.width
int a0 = wA * 16 * by;
// aBegin -> last element in row -> + width - 1
int aZ = a0 + wA - 1;
// Column block iteration = blockDim.x
int aD = 16;
// b_0 -> Column Shift
int b0 = 16 * bx;
// Row block iteration = blockDim.y * width B
int bD = 16 * wB;
float sum = 0.f;
for(int aI = a0, bI = b0; aI <= aZ; aI += aD, bI += bD)
{
/* Assign shared memory and sync */
/* Warning, wA*gidy may be out of bounds */
aBlock[ty][tx] = a[aI + ty*wA + tx];
bBlock[ty][tx] = b[bI + ty*wB + tx];
/* Make sure all of the threads have updated the memory cache */
__syncthreads();
/* Sum over NK */
for(int k=0; k < 16; k++)
{
/* C = (A x B) */
sum += aBlock[ty][k] * bBlock[k][tx];
}
}
c[gy*wB + gx] = sum;
//c[i * NJ + j] = ALPHA*sum + BETA*c[i * NJ + j];
} | .file "tmpxft_00048ba0_00000000-6_d_MM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii
.type _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii, @function
_Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4d_MMPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii, .-_Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii
.globl _Z4d_MMPfS_S_iii
.type _Z4d_MMPfS_S_iii, @function
_Z4d_MMPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4d_MMPfS_S_iii, .-_Z4d_MMPfS_S_iii
.globl _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8d_MM_OPTPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii
.globl _Z8d_MM_OPTPfS_S_iii
.type _Z8d_MM_OPTPfS_S_iii, @function
_Z8d_MM_OPTPfS_S_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8d_MM_OPTPfS_S_iii, .-_Z8d_MM_OPTPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8d_MM_OPTPfS_S_iii"
.LC1:
.string "_Z4d_MMPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8d_MM_OPTPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4d_MMPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* KERNEL d_MM() - Takes two 2D matrices and multiplies them
* Result is divided into threads, each thread iterating over datasets
* to obtain the final answer. C[Thread] = Sum { A column * B Row }
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM(float *a, float *b, float *c, int wA, int wB, int hA)
{
// global index
int gidx = blockDim.x * blockIdx.x + threadIdx.x; // col
int gidy = blockDim.y * blockIdx.y + threadIdx.y; // row
if(gidx < wB && gidy < hA)
{
float sum = 0.f;
for(int k=0; k<wA; k++)
{
// Multiply row of A by column of B
sum += a[gidy*wA + k] * b[k*wB +gidx];
}
c[gidy * wB + gidx] = sum;
}
}
/**
* KERNEL d_MM_OPT() - Takes two 2D matrices and multiplies them optimally
* Output set is divided into blocks of powers of two.
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM_OPT(
float *a,
float *b,
float *c,
int wA,
int wB,
int hA)
{
#define blockTile 16
/* Blocksize is 16x16 */
/* Allocate shared memory */
__shared__ float aBlock[blockTile][blockTile];
__shared__ float bBlock[blockTile][blockTile];
/* Calculate global index X, Y */
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = blockDim.x * bx + tx; // column
int gy = blockDim.y * by + ty; // row
/* Compute offset idx for A & B */
// First A index (row shift) Block.row * Block.width * A.width
int a0 = wA * 16 * by;
// aBegin -> last element in row -> + width - 1
int aZ = a0 + wA - 1;
// Column block iteration = blockDim.x
int aD = 16;
// b_0 -> Column Shift
int b0 = 16 * bx;
// Row block iteration = blockDim.y * width B
int bD = 16 * wB;
float sum = 0.f;
for(int aI = a0, bI = b0; aI <= aZ; aI += aD, bI += bD)
{
/* Assign shared memory and sync */
/* Warning, wA*gidy may be out of bounds */
aBlock[ty][tx] = a[aI + ty*wA + tx];
bBlock[ty][tx] = b[bI + ty*wB + tx];
/* Make sure all of the threads have updated the memory cache */
__syncthreads();
/* Sum over NK */
for(int k=0; k < 16; k++)
{
/* C = (A x B) */
sum += aBlock[ty][k] * bBlock[k][tx];
}
}
c[gy*wB + gx] = sum;
//c[i * NJ + j] = ALPHA*sum + BETA*c[i * NJ + j];
} | #include <hip/hip_runtime.h>
/**
* KERNEL d_MM() - Takes two 2D matrices and multiplies them
* Result is divided into threads, each thread iterating over datasets
* to obtain the final answer. C[Thread] = Sum { A column * B Row }
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM(float *a, float *b, float *c, int wA, int wB, int hA)
{
// global index
int gidx = blockDim.x * blockIdx.x + threadIdx.x; // col
int gidy = blockDim.y * blockIdx.y + threadIdx.y; // row
if(gidx < wB && gidy < hA)
{
float sum = 0.f;
for(int k=0; k<wA; k++)
{
// Multiply row of A by column of B
sum += a[gidy*wA + k] * b[k*wB +gidx];
}
c[gidy * wB + gidx] = sum;
}
}
/**
* KERNEL d_MM_OPT() - Takes two 2D matrices and multiplies them optimally
* Output set is divided into blocks of powers of two.
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM_OPT(
float *a,
float *b,
float *c,
int wA,
int wB,
int hA)
{
#define blockTile 16
/* Blocksize is 16x16 */
/* Allocate shared memory */
__shared__ float aBlock[blockTile][blockTile];
__shared__ float bBlock[blockTile][blockTile];
/* Calculate global index X, Y */
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = blockDim.x * bx + tx; // column
int gy = blockDim.y * by + ty; // row
/* Compute offset idx for A & B */
// First A index (row shift) Block.row * Block.width * A.width
int a0 = wA * 16 * by;
// aBegin -> last element in row -> + width - 1
int aZ = a0 + wA - 1;
// Column block iteration = blockDim.x
int aD = 16;
// b_0 -> Column Shift
int b0 = 16 * bx;
// Row block iteration = blockDim.y * width B
int bD = 16 * wB;
float sum = 0.f;
for(int aI = a0, bI = b0; aI <= aZ; aI += aD, bI += bD)
{
/* Assign shared memory and sync */
/* Warning, wA*gidy may be out of bounds */
aBlock[ty][tx] = a[aI + ty*wA + tx];
bBlock[ty][tx] = b[bI + ty*wB + tx];
/* Make sure all of the threads have updated the memory cache */
__syncthreads();
/* Sum over NK */
for(int k=0; k < 16; k++)
{
/* C = (A x B) */
sum += aBlock[ty][k] * bBlock[k][tx];
}
}
c[gy*wB + gx] = sum;
//c[i * NJ + j] = ALPHA*sum + BETA*c[i * NJ + j];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/**
* KERNEL d_MM() - Takes two 2D matrices and multiplies them
* Result is divided into threads, each thread iterating over datasets
* to obtain the final answer. C[Thread] = Sum { A column * B Row }
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM(float *a, float *b, float *c, int wA, int wB, int hA)
{
// global index
int gidx = blockDim.x * blockIdx.x + threadIdx.x; // col
int gidy = blockDim.y * blockIdx.y + threadIdx.y; // row
if(gidx < wB && gidy < hA)
{
float sum = 0.f;
for(int k=0; k<wA; k++)
{
// Multiply row of A by column of B
sum += a[gidy*wA + k] * b[k*wB +gidx];
}
c[gidy * wB + gidx] = sum;
}
}
/**
* KERNEL d_MM_OPT() - Takes two 2D matrices and multiplies them optimally
* Output set is divided into blocks of powers of two.
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM_OPT(
float *a,
float *b,
float *c,
int wA,
int wB,
int hA)
{
#define blockTile 16
/* Blocksize is 16x16 */
/* Allocate shared memory */
__shared__ float aBlock[blockTile][blockTile];
__shared__ float bBlock[blockTile][blockTile];
/* Calculate global index X, Y */
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = blockDim.x * bx + tx; // column
int gy = blockDim.y * by + ty; // row
/* Compute offset idx for A & B */
// First A index (row shift) Block.row * Block.width * A.width
int a0 = wA * 16 * by;
// aBegin -> last element in row -> + width - 1
int aZ = a0 + wA - 1;
// Column block iteration = blockDim.x
int aD = 16;
// b_0 -> Column Shift
int b0 = 16 * bx;
// Row block iteration = blockDim.y * width B
int bD = 16 * wB;
float sum = 0.f;
for(int aI = a0, bI = b0; aI <= aZ; aI += aD, bI += bD)
{
/* Assign shared memory and sync */
/* Warning, wA*gidy may be out of bounds */
aBlock[ty][tx] = a[aI + ty*wA + tx];
bBlock[ty][tx] = b[bI + ty*wB + tx];
/* Make sure all of the threads have updated the memory cache */
__syncthreads();
/* Sum over NK */
for(int k=0; k < 16; k++)
{
/* C = (A x B) */
sum += aBlock[ty][k] * bBlock[k][tx];
}
}
c[gy*wB + gx] = sum;
//c[i * NJ + j] = ALPHA*sum + BETA*c[i * NJ + j];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4d_MMPfS_S_iii
.globl _Z4d_MMPfS_S_iii
.p2align 8
.type _Z4d_MMPfS_S_iii,@function
_Z4d_MMPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4d_MMPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4d_MMPfS_S_iii, .Lfunc_end0-_Z4d_MMPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8d_MM_OPTPfS_S_iii
.globl _Z8d_MM_OPTPfS_S_iii
.p2align 8
.type _Z8d_MM_OPTPfS_S_iii,@function
_Z8d_MM_OPTPfS_S_iii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x34
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_lshlrev_b32_e32 v7, 2, v1
v_lshlrev_b32_e32 v5, 6, v0
s_mul_i32 s9, s2, s15
s_lshl_b32 s10, s3, 4
s_lshl_b32 s9, s9, 4
s_lshl_b32 s11, s14, 4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
v_mov_b32_e32 v4, 0
v_add_nc_u32_e32 v6, 0x400, v7
v_add_nc_u32_e32 v7, v5, v7
s_add_i32 s2, s9, s2
v_add_nc_u32_e32 v8, v6, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v9, s9, v2
v_add_nc_u32_e32 v11, s11, v3
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v9
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v6
s_waitcnt vmcnt(1)
ds_store_b32 v7, v10
s_waitcnt vmcnt(0)
ds_store_b32 v8, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_3:
v_add_nc_u32_e32 v10, s12, v5
s_add_i32 s12, s12, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 64, v9
s_cmp_eq_u32 s12, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, v10, v11
s_cbranch_scc0 .LBB1_3
s_add_i32 s9, s9, 16
s_add_i32 s11, s11, s10
s_cmp_ge_i32 s9, s2
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_6
.LBB1_5:
v_mov_b32_e32 v4, 0
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_lshr_b32 s2, s8, 16
s_load_b64 s[0:1], s[0:1], 0x10
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_and_b32 s2, 0xffff, s8
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v2, s3
v_add3_u32 v0, s14, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8d_MM_OPTPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8d_MM_OPTPfS_S_iii, .Lfunc_end1-_Z8d_MM_OPTPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4d_MMPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4d_MMPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8d_MM_OPTPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8d_MM_OPTPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/**
* KERNEL d_MM() - Takes two 2D matrices and multiplies them
* Result is divided into threads, each thread iterating over datasets
* to obtain the final answer. C[Thread] = Sum { A column * B Row }
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM(float *a, float *b, float *c, int wA, int wB, int hA)
{
// global index
int gidx = blockDim.x * blockIdx.x + threadIdx.x; // col
int gidy = blockDim.y * blockIdx.y + threadIdx.y; // row
if(gidx < wB && gidy < hA)
{
float sum = 0.f;
for(int k=0; k<wA; k++)
{
// Multiply row of A by column of B
sum += a[gidy*wA + k] * b[k*wB +gidx];
}
c[gidy * wB + gidx] = sum;
}
}
/**
* KERNEL d_MM_OPT() - Takes two 2D matrices and multiplies them optimally
* Output set is divided into blocks of powers of two.
* @param a - 1st Matrix
* @param b - 2nd Matrix
* @param c - Result Matrix
* @param wA - length of A and depth of B
* @param wB - length of matrix B and C
* @param hA - depth of matrix A and C
*/
__global__ void d_MM_OPT(
float *a,
float *b,
float *c,
int wA,
int wB,
int hA)
{
#define blockTile 16
/* Blocksize is 16x16 */
/* Allocate shared memory */
__shared__ float aBlock[blockTile][blockTile];
__shared__ float bBlock[blockTile][blockTile];
/* Calculate global index X, Y */
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int gx = blockDim.x * bx + tx; // column
int gy = blockDim.y * by + ty; // row
/* Compute offset idx for A & B */
// First A index (row shift) Block.row * Block.width * A.width
int a0 = wA * 16 * by;
// aBegin -> last element in row -> + width - 1
int aZ = a0 + wA - 1;
// Column block iteration = blockDim.x
int aD = 16;
// b_0 -> Column Shift
int b0 = 16 * bx;
// Row block iteration = blockDim.y * width B
int bD = 16 * wB;
float sum = 0.f;
for(int aI = a0, bI = b0; aI <= aZ; aI += aD, bI += bD)
{
/* Assign shared memory and sync */
/* Warning, wA*gidy may be out of bounds */
aBlock[ty][tx] = a[aI + ty*wA + tx];
bBlock[ty][tx] = b[bI + ty*wB + tx];
/* Make sure all of the threads have updated the memory cache */
__syncthreads();
/* Sum over NK */
for(int k=0; k < 16; k++)
{
/* C = (A x B) */
sum += aBlock[ty][k] * bBlock[k][tx];
}
}
c[gy*wB + gx] = sum;
//c[i * NJ + j] = ALPHA*sum + BETA*c[i * NJ + j];
} | .text
.file "d_MM.hip"
.globl _Z19__device_stub__d_MMPfS_S_iii # -- Begin function _Z19__device_stub__d_MMPfS_S_iii
.p2align 4, 0x90
.type _Z19__device_stub__d_MMPfS_S_iii,@function
_Z19__device_stub__d_MMPfS_S_iii: # @_Z19__device_stub__d_MMPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4d_MMPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__d_MMPfS_S_iii, .Lfunc_end0-_Z19__device_stub__d_MMPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__d_MM_OPTPfS_S_iii # -- Begin function _Z23__device_stub__d_MM_OPTPfS_S_iii
.p2align 4, 0x90
.type _Z23__device_stub__d_MM_OPTPfS_S_iii,@function
_Z23__device_stub__d_MM_OPTPfS_S_iii: # @_Z23__device_stub__d_MM_OPTPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8d_MM_OPTPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z23__device_stub__d_MM_OPTPfS_S_iii, .Lfunc_end1-_Z23__device_stub__d_MM_OPTPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4d_MMPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8d_MM_OPTPfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4d_MMPfS_S_iii,@object # @_Z4d_MMPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z4d_MMPfS_S_iii
.p2align 3, 0x0
_Z4d_MMPfS_S_iii:
.quad _Z19__device_stub__d_MMPfS_S_iii
.size _Z4d_MMPfS_S_iii, 8
.type _Z8d_MM_OPTPfS_S_iii,@object # @_Z8d_MM_OPTPfS_S_iii
.globl _Z8d_MM_OPTPfS_S_iii
.p2align 3, 0x0
_Z8d_MM_OPTPfS_S_iii:
.quad _Z23__device_stub__d_MM_OPTPfS_S_iii
.size _Z8d_MM_OPTPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4d_MMPfS_S_iii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8d_MM_OPTPfS_S_iii"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__d_MMPfS_S_iii
.addrsig_sym _Z23__device_stub__d_MM_OPTPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4d_MMPfS_S_iii
.addrsig_sym _Z8d_MM_OPTPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00048ba0_00000000-6_d_MM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii
.type _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii, @function
_Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4d_MMPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii, .-_Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii
.globl _Z4d_MMPfS_S_iii
.type _Z4d_MMPfS_S_iii, @function
_Z4d_MMPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4d_MMPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4d_MMPfS_S_iii, .-_Z4d_MMPfS_S_iii
.globl _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8d_MM_OPTPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii
.globl _Z8d_MM_OPTPfS_S_iii
.type _Z8d_MM_OPTPfS_S_iii, @function
_Z8d_MM_OPTPfS_S_iii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8d_MM_OPTPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8d_MM_OPTPfS_S_iii, .-_Z8d_MM_OPTPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8d_MM_OPTPfS_S_iii"
.LC1:
.string "_Z4d_MMPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8d_MM_OPTPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4d_MMPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "d_MM.hip"
.globl _Z19__device_stub__d_MMPfS_S_iii # -- Begin function _Z19__device_stub__d_MMPfS_S_iii
.p2align 4, 0x90
.type _Z19__device_stub__d_MMPfS_S_iii,@function
_Z19__device_stub__d_MMPfS_S_iii: # @_Z19__device_stub__d_MMPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4d_MMPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__d_MMPfS_S_iii, .Lfunc_end0-_Z19__device_stub__d_MMPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__d_MM_OPTPfS_S_iii # -- Begin function _Z23__device_stub__d_MM_OPTPfS_S_iii
.p2align 4, 0x90
.type _Z23__device_stub__d_MM_OPTPfS_S_iii,@function
_Z23__device_stub__d_MM_OPTPfS_S_iii: # @_Z23__device_stub__d_MM_OPTPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8d_MM_OPTPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z23__device_stub__d_MM_OPTPfS_S_iii, .Lfunc_end1-_Z23__device_stub__d_MM_OPTPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4d_MMPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8d_MM_OPTPfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4d_MMPfS_S_iii,@object # @_Z4d_MMPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z4d_MMPfS_S_iii
.p2align 3, 0x0
_Z4d_MMPfS_S_iii:
.quad _Z19__device_stub__d_MMPfS_S_iii
.size _Z4d_MMPfS_S_iii, 8
.type _Z8d_MM_OPTPfS_S_iii,@object # @_Z8d_MM_OPTPfS_S_iii
.globl _Z8d_MM_OPTPfS_S_iii
.p2align 3, 0x0
_Z8d_MM_OPTPfS_S_iii:
.quad _Z23__device_stub__d_MM_OPTPfS_S_iii
.size _Z8d_MM_OPTPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4d_MMPfS_S_iii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8d_MM_OPTPfS_S_iii"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__d_MMPfS_S_iii
.addrsig_sym _Z23__device_stub__d_MM_OPTPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4d_MMPfS_S_iii
.addrsig_sym _Z8d_MM_OPTPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cassert>
struct type { /* a regular type */ };
__host__ __device__
void ordinary_function(type* tc_operand, int block, int thread) {
assert(block == 0 && thread == 0);
// use tc_operand
}
__global__
void entry_point_function(type* tc_operand) {
ordinary_function(tc_operand, blockIdx.x, threadIdx.x);
}
#include <memory>
template <class T> struct managed {
typedef T value_type;
managed () = default;
template <class U> constexpr managed (const managed<U>&) noexcept {}
T* allocate(std::size_t n) {
void* out = nullptr;
cudaMallocManaged(&out, n*sizeof(T));
return static_cast<T*>(out);
}
void deallocate(T* p, std::size_t) noexcept { cudaFree(p); }
};
int main() {
auto managed_object = managed<type>().allocate(1);
entry_point_function<<<1,1>>>(managed_object);
cudaDeviceSynchronize();
ordinary_function(managed_object, 0, 0);
managed<type>().deallocate(managed_object, 1);
return 0;
} | code for sm_80
Function : _Z20entry_point_functionP4type
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cassert>
struct type { /* a regular type */ };
__host__ __device__
void ordinary_function(type* tc_operand, int block, int thread) {
assert(block == 0 && thread == 0);
// use tc_operand
}
__global__
void entry_point_function(type* tc_operand) {
ordinary_function(tc_operand, blockIdx.x, threadIdx.x);
}
#include <memory>
template <class T> struct managed {
typedef T value_type;
managed () = default;
template <class U> constexpr managed (const managed<U>&) noexcept {}
T* allocate(std::size_t n) {
void* out = nullptr;
cudaMallocManaged(&out, n*sizeof(T));
return static_cast<T*>(out);
}
void deallocate(T* p, std::size_t) noexcept { cudaFree(p); }
};
int main() {
auto managed_object = managed<type>().allocate(1);
entry_point_function<<<1,1>>>(managed_object);
cudaDeviceSynchronize();
ordinary_function(managed_object, 0, 0);
managed<type>().deallocate(managed_object, 1);
return 0;
} | .file "tmpxft_001af748_00000000-6_trial.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3248:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3248:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17ordinary_functionP4typeii
.type _Z17ordinary_functionP4typeii, @function
_Z17ordinary_functionP4typeii:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size _Z17ordinary_functionP4typeii, .-_Z17ordinary_functionP4typeii
.globl _Z44__device_stub__Z20entry_point_functionP4typeP4type
.type _Z44__device_stub__Z20entry_point_functionP4typeP4type, @function
_Z44__device_stub__Z20entry_point_functionP4typeP4type:
.LFB3270:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20entry_point_functionP4type(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3270:
.size _Z44__device_stub__Z20entry_point_functionP4typeP4type, .-_Z44__device_stub__Z20entry_point_functionP4typeP4type
.globl _Z20entry_point_functionP4type
.type _Z20entry_point_functionP4type, @function
_Z20entry_point_functionP4type:
.LFB3271:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20entry_point_functionP4typeP4type
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3271:
.size _Z20entry_point_functionP4type, .-_Z20entry_point_functionP4type
.globl main
.type main, @function
main:
.LFB3245:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3245
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1, %esi
.LEHB0:
call cudaMallocManaged@PLT
movq 24(%rsp), %rbx
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
call cudaDeviceSynchronize@PLT
.LEHE0:
movq %rbx, %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %rbx, %rdi
.LEHB1:
call _Z44__device_stub__Z20entry_point_functionP4typeP4type
.LEHE1:
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3245:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3245:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3245-.LLSDACSB3245
.LLSDACSB3245:
.uleb128 .LEHB0-.LFB3245
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3245
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3245:
.text
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20entry_point_functionP4type"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20entry_point_functionP4type(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3273:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
struct type { /* a regular type */ };
__host__ __device__
void ordinary_function(type* tc_operand, int block, int thread) {
assert(block == 0 && thread == 0);
// use tc_operand
}
__global__
void entry_point_function(type* tc_operand) {
ordinary_function(tc_operand, blockIdx.x, threadIdx.x);
}
#include <memory>
template <class T> struct managed {
typedef T value_type;
managed () = default;
template <class U> constexpr managed (const managed<U>&) noexcept {}
T* allocate(std::size_t n) {
void* out = nullptr;
cudaMallocManaged(&out, n*sizeof(T));
return static_cast<T*>(out);
}
void deallocate(T* p, std::size_t) noexcept { cudaFree(p); }
};
int main() {
auto managed_object = managed<type>().allocate(1);
entry_point_function<<<1,1>>>(managed_object);
cudaDeviceSynchronize();
ordinary_function(managed_object, 0, 0);
managed<type>().deallocate(managed_object, 1);
return 0;
} | #include <hip/hip_runtime.h>
#include <cassert>
struct type { /* a regular type */ };
__host__ __device__
void ordinary_function(type* tc_operand, int block, int thread) {
assert(block == 0 && thread == 0);
// use tc_operand
}
__global__
void entry_point_function(type* tc_operand) {
ordinary_function(tc_operand, blockIdx.x, threadIdx.x);
}
#include <memory>
template <class T> struct managed {
typedef T value_type;
managed () = default;
template <class U> constexpr managed (const managed<U>&) noexcept {}
T* allocate(std::size_t n) {
void* out = nullptr;
hipMallocManaged(&out, n*sizeof(T));
return static_cast<T*>(out);
}
void deallocate(T* p, std::size_t) noexcept { hipFree(p); }
};
int main() {
auto managed_object = managed<type>().allocate(1);
entry_point_function<<<1,1>>>(managed_object);
hipDeviceSynchronize();
ordinary_function(managed_object, 0, 0);
managed<type>().deallocate(managed_object, 1);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cassert>
struct type { /* a regular type */ };
__host__ __device__
void ordinary_function(type* tc_operand, int block, int thread) {
assert(block == 0 && thread == 0);
// use tc_operand
}
__global__
void entry_point_function(type* tc_operand) {
ordinary_function(tc_operand, blockIdx.x, threadIdx.x);
}
#include <memory>
template <class T> struct managed {
typedef T value_type;
managed () = default;
template <class U> constexpr managed (const managed<U>&) noexcept {}
T* allocate(std::size_t n) {
void* out = nullptr;
hipMallocManaged(&out, n*sizeof(T));
return static_cast<T*>(out);
}
void deallocate(T* p, std::size_t) noexcept { hipFree(p); }
};
int main() {
auto managed_object = managed<type>().allocate(1);
entry_point_function<<<1,1>>>(managed_object);
hipDeviceSynchronize();
ordinary_function(managed_object, 0, 0);
managed<type>().deallocate(managed_object, 1);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20entry_point_functionP4type
.globl _Z20entry_point_functionP4type
.p2align 8
.type _Z20entry_point_functionP4type,@function
_Z20entry_point_functionP4type:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20entry_point_functionP4type
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20entry_point_functionP4type, .Lfunc_end0-_Z20entry_point_functionP4type
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20entry_point_functionP4type
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z20entry_point_functionP4type.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cassert>
struct type { /* a regular type */ };
__host__ __device__
void ordinary_function(type* tc_operand, int block, int thread) {
assert(block == 0 && thread == 0);
// use tc_operand
}
__global__
void entry_point_function(type* tc_operand) {
ordinary_function(tc_operand, blockIdx.x, threadIdx.x);
}
#include <memory>
template <class T> struct managed {
typedef T value_type;
managed () = default;
template <class U> constexpr managed (const managed<U>&) noexcept {}
T* allocate(std::size_t n) {
void* out = nullptr;
hipMallocManaged(&out, n*sizeof(T));
return static_cast<T*>(out);
}
void deallocate(T* p, std::size_t) noexcept { hipFree(p); }
};
int main() {
auto managed_object = managed<type>().allocate(1);
entry_point_function<<<1,1>>>(managed_object);
hipDeviceSynchronize();
ordinary_function(managed_object, 0, 0);
managed<type>().deallocate(managed_object, 1);
return 0;
} | .text
.file "trial.hip"
.globl _Z17ordinary_functionP4typeii # -- Begin function _Z17ordinary_functionP4typeii
.p2align 4, 0x90
.type _Z17ordinary_functionP4typeii,@function
_Z17ordinary_functionP4typeii: # @_Z17ordinary_functionP4typeii
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z17ordinary_functionP4typeii, .Lfunc_end0-_Z17ordinary_functionP4typeii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__entry_point_functionP4type # -- Begin function _Z35__device_stub__entry_point_functionP4type
.p2align 4, 0x90
.type _Z35__device_stub__entry_point_functionP4type,@function
_Z35__device_stub__entry_point_functionP4type: # @_Z35__device_stub__entry_point_functionP4type
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z20entry_point_functionP4type, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z35__device_stub__entry_point_functionP4type, .Lfunc_end1-_Z35__device_stub__entry_point_functionP4type
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq $0, (%rsp)
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $1, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rbx
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z20entry_point_functionP4type, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq hipFree
.Ltmp1:
# %bb.3: # %_ZN7managedI4typeE10deallocateEPS0_m.exit
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 80
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20entry_point_functionP4type, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20entry_point_functionP4type,@object # @_Z20entry_point_functionP4type
.section .rodata,"a",@progbits
.globl _Z20entry_point_functionP4type
.p2align 3, 0x0
_Z20entry_point_functionP4type:
.quad _Z35__device_stub__entry_point_functionP4type
.size _Z20entry_point_functionP4type, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20entry_point_functionP4type"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__entry_point_functionP4type
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20entry_point_functionP4type
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20entry_point_functionP4type
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20entry_point_functionP4type
.globl _Z20entry_point_functionP4type
.p2align 8
.type _Z20entry_point_functionP4type,@function
_Z20entry_point_functionP4type:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20entry_point_functionP4type
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20entry_point_functionP4type, .Lfunc_end0-_Z20entry_point_functionP4type
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20entry_point_functionP4type
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z20entry_point_functionP4type.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001af748_00000000-6_trial.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3248:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3248:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17ordinary_functionP4typeii
.type _Z17ordinary_functionP4typeii, @function
_Z17ordinary_functionP4typeii:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size _Z17ordinary_functionP4typeii, .-_Z17ordinary_functionP4typeii
.globl _Z44__device_stub__Z20entry_point_functionP4typeP4type
.type _Z44__device_stub__Z20entry_point_functionP4typeP4type, @function
_Z44__device_stub__Z20entry_point_functionP4typeP4type:
.LFB3270:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20entry_point_functionP4type(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3270:
.size _Z44__device_stub__Z20entry_point_functionP4typeP4type, .-_Z44__device_stub__Z20entry_point_functionP4typeP4type
.globl _Z20entry_point_functionP4type
.type _Z20entry_point_functionP4type, @function
_Z20entry_point_functionP4type:
.LFB3271:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20entry_point_functionP4typeP4type
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3271:
.size _Z20entry_point_functionP4type, .-_Z20entry_point_functionP4type
.globl main
.type main, @function
main:
.LFB3245:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3245
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1, %esi
.LEHB0:
call cudaMallocManaged@PLT
movq 24(%rsp), %rbx
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
call cudaDeviceSynchronize@PLT
.LEHE0:
movq %rbx, %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %rbx, %rdi
.LEHB1:
call _Z44__device_stub__Z20entry_point_functionP4typeP4type
.LEHE1:
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3245:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3245:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3245-.LLSDACSB3245
.LLSDACSB3245:
.uleb128 .LEHB0-.LFB3245
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3245
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3245:
.text
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20entry_point_functionP4type"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20entry_point_functionP4type(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3273:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "trial.hip"
.globl _Z17ordinary_functionP4typeii # -- Begin function _Z17ordinary_functionP4typeii
.p2align 4, 0x90
.type _Z17ordinary_functionP4typeii,@function
_Z17ordinary_functionP4typeii: # @_Z17ordinary_functionP4typeii
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z17ordinary_functionP4typeii, .Lfunc_end0-_Z17ordinary_functionP4typeii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__entry_point_functionP4type # -- Begin function _Z35__device_stub__entry_point_functionP4type
.p2align 4, 0x90
.type _Z35__device_stub__entry_point_functionP4type,@function
_Z35__device_stub__entry_point_functionP4type: # @_Z35__device_stub__entry_point_functionP4type
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z20entry_point_functionP4type, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z35__device_stub__entry_point_functionP4type, .Lfunc_end1-_Z35__device_stub__entry_point_functionP4type
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq $0, (%rsp)
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $1, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rbx
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z20entry_point_functionP4type, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq hipFree
.Ltmp1:
# %bb.3: # %_ZN7managedI4typeE10deallocateEPS0_m.exit
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 80
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20entry_point_functionP4type, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20entry_point_functionP4type,@object # @_Z20entry_point_functionP4type
.section .rodata,"a",@progbits
.globl _Z20entry_point_functionP4type
.p2align 3, 0x0
_Z20entry_point_functionP4type:
.quad _Z35__device_stub__entry_point_functionP4type
.size _Z20entry_point_functionP4type, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20entry_point_functionP4type"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__entry_point_functionP4type
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20entry_point_functionP4type
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
extern "C" __device__ void exit(int ret) __THROW { assert(0); } | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
extern "C" __device__ void exit(int ret) __THROW { assert(0); } | .file "tmpxft_00031855_00000000-6_exit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl exit
.type exit, @function
exit:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit
.cfi_endproc
.LFE2027:
.size exit, .-exit
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
extern "C" __device__ void exit(int ret) __THROW { assert(0); } | #include <hip/hip_runtime.h>
#include <assert.h>
extern "C" __device__ void exit(int ret) __THROW { assert(0); } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <assert.h>
extern "C" __device__ void exit(int ret) __THROW { assert(0); } | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <assert.h>
extern "C" __device__ void exit(int ret) __THROW { assert(0); } | .text
.file "exit.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00031855_00000000-6_exit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl exit
.type exit, @function
exit:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit
.cfi_endproc
.LFE2027:
.size exit, .-exit
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exit.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void MHDUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Bx, float *By, float *Bz, float *Phi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dt, float C_h, float C_p, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
Bx[igrid] += dUBx[igrid];
By[igrid] += dUBy[igrid];
Bz[igrid] += dUBz[igrid];
Phi[igrid] += dUPhi[igrid];
Phi[igrid] *= expf(-dt*(C_h/C_p)*(C_h/C_p));
} | code for sm_80
Function : _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x1fc] ; /* 0x00007f0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x3, URZ ; /* 0xfffffffd04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0060*/ LEA R0, R3, R0, 0x6 ; /* 0x0000000003007211 */
/* 0x001fca00078e30ff */
/*0070*/ IMAD R0, R5, 0xa000, R0 ; /* 0x0000a00005007824 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GT.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf04270 */
/*0090*/ ISETP.LT.OR P0, PT, R0, 0x2, P0 ; /* 0x000000020000780c */
/* 0x000fda0000701670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R8, R0, R21, c[0x0][0x1a8] ; /* 0x00006a0000087625 */
/* 0x000fc800078e0215 */
/*00e0*/ IMAD.WIDE R10, R0.reuse, R21.reuse, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x0c0fe200078e0215 */
/*00f0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x0000a8000c1e1900 */
/*0100*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R24, R0, R21, c[0x0][0x1b0] ; /* 0x00006c0000187625 */
/* 0x000fc800078e0215 */
/*0120*/ IMAD.WIDE R2, R0.reuse, R21.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe200078e0215 */
/*0130*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee6000c1e1900 */
/*0140*/ IMAD.WIDE R14, R0.reuse, R21.reuse, c[0x0][0x1c8] ; /* 0x00007200000e7625 */
/* 0x0c0fe200078e0215 */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ee6000c1e1900 */
/*0160*/ IMAD.WIDE R26, R0.reuse, R21.reuse, c[0x0][0x1b8] ; /* 0x00006e00001a7625 */
/* 0x0c0fe400078e0215 */
/*0170*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000324000c1e1900 */
/*0180*/ IMAD.WIDE R28, R0, R21, c[0x0][0x1c0] ; /* 0x00007000001c7625 */
/* 0x000fc400078e0215 */
/*0190*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x000b24000c1e1900 */
/*01a0*/ IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0215 */
/*01b0*/ IMAD.WIDE R6, R0.reuse, R21.reuse, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x0c0fe200078e0215 */
/*01c0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000f26000c1e1900 */
/*01d0*/ IMAD.WIDE R8, R0, R21, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x001fe200078e0215 */
/*01e0*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000e68000c1e1900 */
/*01f0*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x000e68000c1e1900 */
/*0200*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000f22000c1e1900 */
/*0210*/ BSSY B0, 0x330 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0220*/ FADD R13, R16, R13 ; /* 0x0000000d100d7221 */
/* 0x004fc80000000000 */
/*0230*/ MUFU.RCP R26, R13 ; /* 0x0000000d001a7308 */
/* 0x020e220000001000 */
/*0240*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0005e2000c101904 */
/*0250*/ FFMA R24, R17, R16, R12 ; /* 0x0000001011187223 */
/* 0x008fcc000000000c */
/*0260*/ FCHK P0, R24, R13 ; /* 0x0000000d18007302 */
/* 0x000ee20000000000 */
/*0270*/ FFMA R23, -R13, R26, 1 ; /* 0x3f8000000d177423 */
/* 0x001fc8000000011a */
/*0280*/ FFMA R23, R26, R23, R26 ; /* 0x000000171a177223 */
/* 0x000fc8000000001a */
/*0290*/ FFMA R26, R24, R23, RZ ; /* 0x00000017181a7223 */
/* 0x000fc800000000ff */
/*02a0*/ FFMA R17, -R13, R26, R24 ; /* 0x0000001a0d117223 */
/* 0x000fe40000000118 */
/*02b0*/ FFMA R12, R16.reuse, R22, R19 ; /* 0x00000016100c7223 */
/* 0x050fe40000000013 */
/*02c0*/ FFMA R14, R16.reuse, R18, R21 ; /* 0x00000012100e7223 */
/* 0x042fe40000000015 */
/*02d0*/ FFMA R17, R23, R17, R26 ; /* 0x0000001117117223 */
/* 0x000fe4000000001a */
/*02e0*/ FFMA R20, R16, R20, R15 ; /* 0x0000001410147223 */
/* 0x000fe2000000000f */
/*02f0*/ @!P0 BRA 0x320 ; /* 0x0000002000008947 */
/* 0x008fea0003800000 */
/*0300*/ MOV R10, 0x320 ; /* 0x00000320000a7802 */
/* 0x004fe40000000f00 */
/*0310*/ CALL.REL.NOINC 0x980 ; /* 0x0000066000007944 */
/* 0x000fea0003c00000 */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0330*/ MUFU.RCP R10, R13 ; /* 0x0000000d000a7308 */
/* 0x000e620000001000 */
/*0340*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0011e2000c101904 */
/*0350*/ BSSY B0, 0x420 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0360*/ FCHK P0, R12, R13 ; /* 0x0000000d0c007302 */
/* 0x000ea20000000000 */
/*0370*/ FFMA R11, -R13, R10, 1 ; /* 0x3f8000000d0b7423 */
/* 0x002fc8000000010a */
/*0380*/ FFMA R15, R10, R11, R10 ; /* 0x0000000b0a0f7223 */
/* 0x000fc8000000000a */
/*0390*/ FFMA R10, R12, R15, RZ ; /* 0x0000000f0c0a7223 */
/* 0x000fc800000000ff */
/*03a0*/ FFMA R11, -R13, R10, R12 ; /* 0x0000000a0d0b7223 */
/* 0x000fc8000000010c */
/*03b0*/ FFMA R11, R15, R11, R10 ; /* 0x0000000b0f0b7223 */
/* 0x000fe2000000000a */
/*03c0*/ @!P0 BRA 0x410 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R24, RZ, RZ, R12 ; /* 0x000000ffff187224 */
/* 0x001fe200078e000c */
/*03e0*/ MOV R10, 0x400 ; /* 0x00000400000a7802 */
/* 0x000fe40000000f00 */
/*03f0*/ CALL.REL.NOINC 0x980 ; /* 0x0000058000007944 */
/* 0x000fea0003c00000 */
/*0400*/ MOV R11, R17 ; /* 0x00000011000b7202 */
/* 0x001fe40000000f00 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0420*/ MUFU.RCP R2, R13 ; /* 0x0000000d00027308 */
/* 0x000e220000001000 */
/*0430*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e2000c101904 */
/*0440*/ BSSY B0, 0x510 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0450*/ FCHK P0, R14, R13 ; /* 0x0000000d0e007302 */
/* 0x000ea20000000000 */
/*0460*/ FFMA R3, -R13, R2, 1 ; /* 0x3f8000000d037423 */
/* 0x001fc80000000102 */
/*0470*/ FFMA R15, R2, R3, R2 ; /* 0x00000003020f7223 */
/* 0x000fc80000000002 */
/*0480*/ FFMA R2, R14, R15, RZ ; /* 0x0000000f0e027223 */
/* 0x000fc800000000ff */
/*0490*/ FFMA R3, -R13, R2, R14 ; /* 0x000000020d037223 */
/* 0x000fc8000000010e */
/*04a0*/ FFMA R3, R15, R3, R2 ; /* 0x000000030f037223 */
/* 0x000fe20000000002 */
/*04b0*/ @!P0 BRA 0x500 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*04c0*/ MOV R24, R14 ; /* 0x0000000e00187202 */
/* 0x002fe40000000f00 */
/*04d0*/ MOV R10, 0x4f0 ; /* 0x000004f0000a7802 */
/* 0x000fe40000000f00 */
/*04e0*/ CALL.REL.NOINC 0x980 ; /* 0x0000049000007944 */
/* 0x000fea0003c00000 */
/*04f0*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0011 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0510*/ MUFU.RCP R2, R13 ; /* 0x0000000d00027308 */
/* 0x000e220000001000 */
/*0520*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0003e2000c101904 */
/*0530*/ BSSY B0, 0x600 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0540*/ FCHK P0, R20, R13 ; /* 0x0000000d14007302 */
/* 0x000ea20000000000 */
/*0550*/ FFMA R5, -R13, R2, 1 ; /* 0x3f8000000d057423 */
/* 0x001fc80000000102 */
/*0560*/ FFMA R15, R2, R5, R2 ; /* 0x00000005020f7223 */
/* 0x000fc80000000002 */
/*0570*/ FFMA R2, R20, R15, RZ ; /* 0x0000000f14027223 */
/* 0x000fc800000000ff */
/*0580*/ FFMA R5, -R13, R2, R20 ; /* 0x000000020d057223 */
/* 0x000fc80000000114 */
/*0590*/ FFMA R15, R15, R5, R2 ; /* 0x000000050f0f7223 */
/* 0x000fe20000000002 */
/*05a0*/ @!P0 BRA 0x5f0 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*05b0*/ MOV R24, R20 ; /* 0x0000001400187202 */
/* 0x002fe40000000f00 */
/*05c0*/ MOV R10, 0x5e0 ; /* 0x000005e0000a7802 */
/* 0x000fe40000000f00 */
/*05d0*/ CALL.REL.NOINC 0x980 ; /* 0x000003a000007944 */
/* 0x000fea0003c00000 */
/*05e0*/ MOV R15, R17 ; /* 0x00000011000f7202 */
/* 0x001fe40000000f00 */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0600*/ HFMA2.MMA R23, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff177435 */
/* 0x000fe200000001ff */
/*0610*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001f2000c101904 */
/*0620*/ IMAD.WIDE R2, R0, R23, c[0x0][0x1d0] ; /* 0x0000740000027625 */
/* 0x000fc800078e0217 */
/*0630*/ IMAD.WIDE R4, R0.reuse, R23.reuse, c[0x0][0x188] ; /* 0x0000620000047625 */
/* 0x0c0fe400078e0217 */
/*0640*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0650*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0660*/ IMAD.WIDE R10, R0, R23, c[0x0][0x190] ; /* 0x00006400000a7625 */
/* 0x000fc800078e0217 */
/*0670*/ FADD R17, R6, R3 ; /* 0x0000000306117221 */
/* 0x004fe40000000000 */
/*0680*/ IMAD.WIDE R6, R0, R23, c[0x0][0x1d8] ; /* 0x0000760000067625 */
/* 0x000fc600078e0217 */
/*0690*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0003e8000c101904 */
/*06a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R0, R23, c[0x0][0x198] ; /* 0x0000660000087625 */
/* 0x001fc800078e0217 */
/*06d0*/ FADD R19, R12, R7 ; /* 0x000000070c137221 */
/* 0x004fe40000000000 */
/*06e0*/ IMAD.WIDE R12, R0, R23, c[0x0][0x1e0] ; /* 0x00007800000c7625 */
/* 0x000fc600078e0217 */
/*06f0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e8000c101904 */
/*0700*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*0720*/ IMAD.WIDE R14, R0, R23, c[0x0][0x1e8] ; /* 0x00007a00000e7625 */
/* 0x000fe200078e0217 */
/*0730*/ MUFU.RCP R4, c[0x0][0x1f8] ; /* 0x00007e0000047b08 */
/* 0x002e620000001000 */
/*0740*/ ULDC UR6, c[0x0][0x1f4] ; /* 0x00007d0000067ab9 */
/* 0x000fc40000000800 */
/*0750*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x001fe20008000f00 */
/*0760*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1f8] ; /* 0x00007e00ff077624 */
/* 0x000fc800078e00ff */
/*0770*/ FCHK P0, R10, c[0x0][0x1f8] ; /* 0x00007e000a007b02 */
/* 0x000e220000000000 */
/*0780*/ FADD R21, R2, R13 ; /* 0x0000000d02157221 */
/* 0x004fe40000000000 */
/*0790*/ IMAD.WIDE R2, R0, R23, c[0x0][0x1a0] ; /* 0x0000680000027625 */
/* 0x000fc600078e0217 */
/*07a0*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0005e8000c101904 */
/*07b0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*07c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee2000c1e1900 */
/*07d0*/ FFMA R5, R4, -R7, 1 ; /* 0x3f80000004057423 */
/* 0x002fc80000000807 */
/*07e0*/ FFMA R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fc80000000004 */
/*07f0*/ FFMA R4, R5, c[0x0][0x1f4], RZ ; /* 0x00007d0005047a23 */
/* 0x000fc800000000ff */
/*0800*/ FFMA R6, R4, -R7, c[0x0][0x1f4] ; /* 0x00007d0004067623 */
/* 0x000fc80000000807 */
/*0810*/ FFMA R4, R5, R6, R4 ; /* 0x0000000605047223 */
/* 0x000fe40000000004 */
/*0820*/ FADD R0, R0, R15 ; /* 0x0000000f00007221 */
/* 0x008fe20000000000 */
/*0830*/ @!P0 BRA 0x890 ; /* 0x0000005000008947 */
/* 0x001fea0003800000 */
/*0840*/ MOV R24, c[0x0][0x1f4] ; /* 0x00007d0000187a02 */
/* 0x004fe40000000f00 */
/*0850*/ MOV R13, c[0x0][0x1f8] ; /* 0x00007e00000d7a02 */
/* 0x000fe40000000f00 */
/*0860*/ MOV R10, 0x880 ; /* 0x00000880000a7802 */
/* 0x000fe40000000f00 */
/*0870*/ CALL.REL.NOINC 0x980 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, R17 ; /* 0x000000ffff047224 */
/* 0x001fc800078e0011 */
/*0890*/ FMUL R5, R4, c[0x0][0x1f0] ; /* 0x00007c0004057a20 */
/* 0x004fe20000400000 */
/*08a0*/ MOV R6, 0x3bbb989d ; /* 0x3bbb989d00067802 */
/* 0x000fe40000000f00 */
/*08b0*/ MOV R7, 0x437c0000 ; /* 0x437c000000077802 */
/* 0x000fe20000000f00 */
/*08c0*/ FMUL R5, R5, R4 ; /* 0x0000000405057220 */
/* 0x000fc80000400000 */
/*08d0*/ FFMA.SAT R4, -R5, R6, 0.5 ; /* 0x3f00000005047423 */
/* 0x000fc80000002106 */
/*08e0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*08f0*/ FADD R6, R4.reuse, -12583039 ; /* 0xcb40007f04067421 */
/* 0x040fe20000000000 */
/*0900*/ SHF.L.U32 R4, R4, 0x17, RZ ; /* 0x0000001704047819 */
/* 0x000fc600000006ff */
/*0910*/ FFMA R6, -R5, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b05067823 */
/* 0x000fc80000000906 */
/*0920*/ FFMA R6, -R5, 1.925963033500011079e-08, R6 ; /* 0x32a5706005067823 */
/* 0x000fc80000000106 */
/*0930*/ MUFU.EX2 R5, R6 ; /* 0x0000000600057308 */
/* 0x000e240000000800 */
/*0940*/ FMUL R5, R4, R5 ; /* 0x0000000504057220 */
/* 0x001fc80000400000 */
/*0950*/ FMUL R5, R0, R5 ; /* 0x0000000500057220 */
/* 0x000fca0000400000 */
/*0960*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ SHF.R.U32.HI R11, RZ, 0x17, R13 ; /* 0x00000017ff0b7819 */
/* 0x000fe2000001160d */
/*0990*/ BSSY B1, 0xfe0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*09a0*/ SHF.R.U32.HI R16, RZ, 0x17, R24.reuse ; /* 0x00000017ff107819 */
/* 0x100fe20000011618 */
/*09b0*/ IMAD.MOV.U32 R19, RZ, RZ, R24 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0018 */
/*09c0*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*09d0*/ LOP3.LUT R16, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10107812 */
/* 0x000fe400078ec0ff */
/*09e0*/ IADD3 R21, R11, -0x1, RZ ; /* 0xffffffff0b157810 */
/* 0x000fe40007ffe0ff */
/*09f0*/ IADD3 R17, R16, -0x1, RZ ; /* 0xffffffff10117810 */
/* 0x000fc40007ffe0ff */
/*0a00*/ ISETP.GT.U32.AND P0, PT, R21, 0xfd, PT ; /* 0x000000fd1500780c */
/* 0x000fe40003f04070 */
/*0a10*/ MOV R18, R13 ; /* 0x0000000d00127202 */
/* 0x000fe40000000f00 */
/*0a20*/ ISETP.GT.U32.OR P0, PT, R17, 0xfd, P0 ; /* 0x000000fd1100780c */
/* 0x000fda0000704470 */
/*0a30*/ @!P0 MOV R15, RZ ; /* 0x000000ff000f8202 */
/* 0x000fe20000000f00 */
/*0a40*/ @!P0 BRA 0xbc0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a50*/ FSETP.GTU.FTZ.AND P0, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fe40003f1c200 */
/*0a60*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0a70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0a80*/ @P0 BRA 0xfc0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0a90*/ LOP3.LUT P0, RZ, R18, 0x7fffffff, R19, 0xc8, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fda000780c813 */
/*0aa0*/ @!P0 BRA 0xfa0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ FSETP.NEU.FTZ.AND P2, PT, |R24|.reuse, +INF , PT ; /* 0x7f8000001800780b */
/* 0x040fe40003f5d200 */
/*0ac0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0ad0*/ FSETP.NEU.FTZ.AND P0, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fd60003f1d200 */
/*0ae0*/ @!P1 BRA !P2, 0xfa0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0af0*/ LOP3.LUT P2, RZ, R19, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff13ff7812 */
/* 0x000fc8000784c0ff */
/*0b00*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b10*/ @P1 BRA 0xf80 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b20*/ LOP3.LUT P1, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fc8000782c0ff */
/*0b30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0b40*/ @P0 BRA 0xf50 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0b50*/ ISETP.GE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f06270 */
/*0b60*/ ISETP.GE.AND P1, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fd60003f26270 */
/*0b70*/ @P0 MOV R15, RZ ; /* 0x000000ff000f0202 */
/* 0x000fe20000000f00 */
/*0b80*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, -0x40 ; /* 0xffffffc0ff0f8424 */
/* 0x000fe400078e00ff */
/*0b90*/ @!P0 FFMA R19, R24, 1.84467440737095516160e+19, RZ ; /* 0x5f80000018138823 */
/* 0x000fe400000000ff */
/*0ba0*/ @!P1 FFMA R18, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d129823 */
/* 0x000fe200000000ff */
/*0bb0*/ @!P1 IADD3 R15, R15, 0x40, RZ ; /* 0x000000400f0f9810 */
/* 0x000fe40007ffe0ff */
/*0bc0*/ LEA R17, R11, 0xc0800000, 0x17 ; /* 0xc08000000b117811 */
/* 0x000fe200078eb8ff */
/*0bd0*/ BSSY B2, 0xf40 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0be0*/ IADD3 R16, R16, -0x7f, RZ ; /* 0xffffff8110107810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ IADD3 R23, -R17, R18, RZ ; /* 0x0000001211177210 */
/* 0x000fc60007ffe1ff */
/*0c00*/ IMAD R22, R16.reuse, -0x800000, R19 ; /* 0xff80000010167824 */
/* 0x040fe200078e0213 */
/*0c10*/ MUFU.RCP R18, R23 ; /* 0x0000001700127308 */
/* 0x000e220000001000 */
/*0c20*/ FADD.FTZ R17, -R23, -RZ ; /* 0x800000ff17117221 */
/* 0x000fe20000010100 */
/*0c30*/ IADD3 R16, R16, 0x7f, -R11 ; /* 0x0000007f10107810 */
/* 0x000fc80007ffe80b */
/*0c40*/ IADD3 R16, R16, R15, RZ ; /* 0x0000000f10107210 */
/* 0x000fe20007ffe0ff */
/*0c50*/ FFMA R21, R18, R17, 1 ; /* 0x3f80000012157423 */
/* 0x001fc80000000011 */
/*0c60*/ FFMA R18, R18, R21, R18 ; /* 0x0000001512127223 */
/* 0x000fc80000000012 */
/*0c70*/ FFMA R19, R22, R18, RZ ; /* 0x0000001216137223 */
/* 0x000fc800000000ff */
/*0c80*/ FFMA R21, R17, R19, R22 ; /* 0x0000001311157223 */
/* 0x000fc80000000016 */
/*0c90*/ FFMA R19, R18, R21, R19 ; /* 0x0000001512137223 */
/* 0x000fc80000000013 */
/*0ca0*/ FFMA R21, R17, R19, R22 ; /* 0x0000001311157223 */
/* 0x000fc80000000016 */
/*0cb0*/ FFMA R17, R18, R21, R19 ; /* 0x0000001512117223 */
/* 0x000fca0000000013 */
/*0cc0*/ SHF.R.U32.HI R11, RZ, 0x17, R17 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011611 */
/*0cd0*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fc800078ec0ff */
/*0ce0*/ IADD3 R11, R11, R16, RZ ; /* 0x000000100b0b7210 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ IADD3 R15, R11, -0x1, RZ ; /* 0xffffffff0b0f7810 */
/* 0x000fc80007ffe0ff */
/*0d00*/ ISETP.GE.U32.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f06070 */
/*0d10*/ @!P0 BRA 0xf20 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d20*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0d30*/ @P0 BRA 0xef0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0d40*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0d50*/ @P0 BRA 0xf30 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0d60*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0d70*/ LOP3.LUT R17, R17, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000011117812 */
/* 0x000fd600078ec0ff */
/*0d80*/ @!P0 BRA 0xf30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0d90*/ FFMA.RZ R15, R18.reuse, R21.reuse, R19.reuse ; /* 0x00000015120f7223 */
/* 0x1c0fe2000000c013 */
/*0da0*/ ISETP.NE.AND P2, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x040fe40003f45270 */
/*0db0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f25270 */
/*0dc0*/ LOP3.LUT R16, R15, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0f107812 */
/* 0x000fe200078ec0ff */
/*0dd0*/ FFMA.RP R15, R18.reuse, R21.reuse, R19.reuse ; /* 0x00000015120f7223 */
/* 0x1c0fe40000008013 */
/*0de0*/ FFMA.RM R18, R18, R21, R19 ; /* 0x0000001512127223 */
/* 0x000fe20000004013 */
/*0df0*/ IADD3 R19, R11, 0x20, RZ ; /* 0x000000200b137810 */
/* 0x000fe20007ffe0ff */
/*0e00*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0e10*/ LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000010107812 */
/* 0x000fc400078efcff */
/*0e20*/ FSETP.NEU.FTZ.AND P0, PT, R15, R18, PT ; /* 0x000000120f00720b */
/* 0x000fe40003f1d000 */
/*0e30*/ SHF.L.U32 R19, R16, R19, RZ ; /* 0x0000001310137219 */
/* 0x000fe400000006ff */
/*0e40*/ SEL R11, R11, RZ, P2 ; /* 0x000000ff0b0b7207 */
/* 0x000fe40001000000 */
/*0e50*/ ISETP.NE.AND P1, PT, R19, RZ, P1 ; /* 0x000000ff1300720c */
/* 0x000fe40000f25270 */
/*0e60*/ SHF.R.U32.HI R11, RZ, R11, R16 ; /* 0x0000000bff0b7219 */
/* 0x000fe40000011610 */
/*0e70*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0e80*/ SHF.R.U32.HI R16, RZ, 0x1, R11 ; /* 0x00000001ff107819 */
/* 0x000fe4000001160b */
/*0e90*/ SEL R15, RZ, 0x1, !P0 ; /* 0x00000001ff0f7807 */
/* 0x000fc80004000000 */
/*0ea0*/ LOP3.LUT R18, R15, 0x1, R16, 0xf8, !PT ; /* 0x000000010f127812 */
/* 0x000fc800078ef810 */
/*0eb0*/ LOP3.LUT R11, R18, R11, RZ, 0xc0, !PT ; /* 0x0000000b120b7212 */
/* 0x000fc800078ec0ff */
/*0ec0*/ IADD3 R16, R16, R11, RZ ; /* 0x0000000b10107210 */
/* 0x000fc80007ffe0ff */
/*0ed0*/ LOP3.LUT R17, R16, R17, RZ, 0xfc, !PT ; /* 0x0000001110117212 */
/* 0x000fe200078efcff */
/*0ee0*/ BRA 0xf30 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ef0*/ LOP3.LUT R17, R17, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ec0ff */
/*0f00*/ LOP3.LUT R17, R17, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000011117812 */
/* 0x000fe200078efcff */
/*0f10*/ BRA 0xf30 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f20*/ LEA R17, R16, R17, 0x17 ; /* 0x0000001110117211 */
/* 0x000fe400078eb8ff */
/*0f30*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f40*/ BRA 0xfd0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0f50*/ LOP3.LUT R17, R18, 0x80000000, R19, 0x48, !PT ; /* 0x8000000012117812 */
/* 0x000fc800078e4813 */
/*0f60*/ LOP3.LUT R17, R17, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000011117812 */
/* 0x000fe200078efcff */
/*0f70*/ BRA 0xfd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f80*/ LOP3.LUT R17, R18, 0x80000000, R19, 0x48, !PT ; /* 0x8000000012117812 */
/* 0x000fe200078e4813 */
/*0f90*/ BRA 0xfd0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0fa0*/ MUFU.RSQ R17, -QNAN ; /* 0xffc0000000117908 */
/* 0x000e220000001400 */
/*0fb0*/ BRA 0xfd0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fc0*/ FADD.FTZ R17, R24, R13 ; /* 0x0000000d18117221 */
/* 0x000fe40000010000 */
/*0fd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0fe0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fcc00000001ff */
/*0ff0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0000a007950 */
/* 0x000fea0003c3ffff */
/*1000*/ BRA 0x1000; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void MHDUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Bx, float *By, float *Bz, float *Phi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dt, float C_h, float C_p, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
Bx[igrid] += dUBx[igrid];
By[igrid] += dUBy[igrid];
Bz[igrid] += dUBz[igrid];
Phi[igrid] += dUPhi[igrid];
Phi[igrid] *= expf(-dt*(C_h/C_p)*(C_h/C_p));
} | .file "tmpxft_001025d5_00000000-6_MHDUpdatePrim_CUDA3_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.type _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, @function
_Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
.LFB2051:
.cfi_startproc
endbr64
subq $424, %rsp
.cfi_def_cfa_offset 432
movq %rdi, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rcx, 128(%rsp)
movq %r8, 120(%rsp)
movq %r9, 112(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq 432(%rsp), %rax
movq %rax, 104(%rsp)
movq 440(%rsp), %rax
movq %rax, 96(%rsp)
movq 448(%rsp), %rax
movq %rax, 88(%rsp)
movq 456(%rsp), %rax
movq %rax, 80(%rsp)
movq 464(%rsp), %rax
movq %rax, 72(%rsp)
movq 472(%rsp), %rax
movq %rax, 64(%rsp)
movq 480(%rsp), %rax
movq %rax, 56(%rsp)
movq 488(%rsp), %rax
movq %rax, 48(%rsp)
movq 496(%rsp), %rax
movq %rax, 40(%rsp)
movq 504(%rsp), %rax
movq %rax, 32(%rsp)
movq 512(%rsp), %rax
movq %rax, 24(%rsp)
movq 520(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 408(%rsp)
xorl %eax, %eax
leaq 152(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rax
movq %rax, 248(%rsp)
leaq 120(%rsp), %rax
movq %rax, 256(%rsp)
leaq 112(%rsp), %rax
movq %rax, 264(%rsp)
leaq 104(%rsp), %rax
movq %rax, 272(%rsp)
leaq 96(%rsp), %rax
movq %rax, 280(%rsp)
leaq 88(%rsp), %rax
movq %rax, 288(%rsp)
leaq 80(%rsp), %rax
movq %rax, 296(%rsp)
leaq 72(%rsp), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rax
movq %rax, 312(%rsp)
leaq 56(%rsp), %rax
movq %rax, 320(%rsp)
leaq 48(%rsp), %rax
movq %rax, 328(%rsp)
leaq 40(%rsp), %rax
movq %rax, 336(%rsp)
leaq 32(%rsp), %rax
movq %rax, 344(%rsp)
leaq 24(%rsp), %rax
movq %rax, 352(%rsp)
leaq 16(%rsp), %rax
movq %rax, 360(%rsp)
leaq 12(%rsp), %rax
movq %rax, 368(%rsp)
leaq 8(%rsp), %rax
movq %rax, 376(%rsp)
leaq 4(%rsp), %rax
movq %rax, 384(%rsp)
leaq 528(%rsp), %rax
movq %rax, 392(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
leaq 168(%rsp), %rcx
leaq 160(%rsp), %rdx
leaq 188(%rsp), %rsi
leaq 176(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 408(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $424, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 168(%rsp)
.cfi_def_cfa_offset 440
pushq 168(%rsp)
.cfi_def_cfa_offset 448
leaq 240(%rsp), %r9
movq 204(%rsp), %rcx
movl 212(%rsp), %r8d
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
leaq _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 432
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .-_Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.globl _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.type _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, @function
_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 120(%rsp)
.cfi_def_cfa_offset 40
pushq 120(%rsp)
.cfi_def_cfa_offset 48
pushq 120(%rsp)
.cfi_def_cfa_offset 56
pushq 120(%rsp)
.cfi_def_cfa_offset 64
pushq 120(%rsp)
.cfi_def_cfa_offset 72
pushq 120(%rsp)
.cfi_def_cfa_offset 80
pushq 120(%rsp)
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
call _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .-_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void MHDUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Bx, float *By, float *Bz, float *Phi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dt, float C_h, float C_p, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
Bx[igrid] += dUBx[igrid];
By[igrid] += dUBy[igrid];
Bz[igrid] += dUBz[igrid];
Phi[igrid] += dUPhi[igrid];
Phi[igrid] *= expf(-dt*(C_h/C_p)*(C_h/C_p));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MHDUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Bx, float *By, float *Bz, float *Phi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dt, float C_h, float C_p, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
Bx[igrid] += dUBx[igrid];
By[igrid] += dUBy[igrid];
Bz[igrid] += dUBz[igrid];
Phi[igrid] += dUPhi[igrid];
Phi[igrid] *= expf(-dt*(C_h/C_p)*(C_h/C_p));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MHDUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Bx, float *By, float *Bz, float *Phi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dt, float C_h, float C_p, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
Bx[igrid] += dUBx[igrid];
By[igrid] += dUBy[igrid];
Bz[igrid] += dUBz[igrid];
Phi[igrid] += dUPhi[igrid];
Phi[igrid] *= expf(-dt*(C_h/C_p)*(C_h/C_p));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.globl _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.p2align 8
.type _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi,@function
_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
s_load_b32 s2, s[0:1], 0x9c
s_lshl_b32 s3, s14, 6
s_mul_i32 s15, s15, 0xa000
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s3, v0
v_cmp_lt_i32_e32 vcc_lo, 1, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[36:43], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_clause 0x2
s_load_b256 s[16:23], s[0:1], 0x20
s_load_b256 s[8:15], s[0:1], 0x40
s_load_b256 s[24:31], s[0:1], 0x60
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s36, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s37, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s38, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s39, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s40, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s41, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s42, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s43, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s17, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v14, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v15, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v16, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v17, vcc_lo, s15, v1, vcc_lo
v_add_co_u32 v18, vcc_lo, s24, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s25, v1, vcc_lo
v_add_co_u32 v20, vcc_lo, s26, v0
v_add_co_ci_u32_e32 v21, vcc_lo, s27, v1, vcc_lo
global_load_b32 v22, v[2:3], off
global_load_b32 v23, v[4:5], off
global_load_b32 v24, v[6:7], off
global_load_b32 v25, v[8:9], off
global_load_b32 v26, v[10:11], off
global_load_b32 v12, v[12:13], off
global_load_b32 v27, v[14:15], off
global_load_b32 v16, v[16:17], off
global_load_b32 v17, v[18:19], off
global_load_b32 v18, v[20:21], off
s_waitcnt vmcnt(4)
v_add_f32_e32 v19, v22, v12
s_waitcnt vmcnt(3)
v_fmac_f32_e32 v27, v22, v23
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v16, v22, v24
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v17, v22, v25
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v18, v22, v26
v_div_scale_f32 v14, null, v19, v19, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v22, v14
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v14, v22, 1.0
v_fmac_f32_e32 v22, v12, v22
v_div_scale_f32 v15, null, v19, v19, v16
v_div_scale_f32 v20, null, v19, v19, v17
v_div_scale_f32 v28, s2, v16, v19, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v23, v15
v_rcp_f32_e32 v24, v20
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v15, v23, 1.0
v_fma_f32 v30, -v20, v24, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v23, v13, v23
v_div_scale_f32 v21, null, v19, v19, v18
v_div_scale_f32 v32, s4, v18, v19, v18
v_rcp_f32_e32 v25, v21
s_waitcnt_depctr 0xfff
v_fma_f32 v31, -v21, v25, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v24, v30, v24 :: v_dual_fmac_f32 v25, v31, v25
v_mul_f32_e32 v31, v28, v23
v_mul_f32_e32 v34, v32, v25
v_div_scale_f32 v26, vcc_lo, v27, v19, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v13, -v15, v31, v28
v_fma_f32 v36, -v21, v34, v32
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v30, v26, v22 :: v_dual_fmac_f32 v31, v13, v23
v_fmac_f32_e32 v34, v36, v25
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v12, -v14, v30, v26
v_fma_f32 v15, -v15, v31, v28
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v21, -v21, v34, v32
v_fmac_f32_e32 v30, v12, v22
v_div_scale_f32 v29, s3, v17, v19, v17
v_add_co_u32 v12, s5, s28, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v14, -v14, v30, v26
v_mul_f32_e32 v33, v29, v24
v_add_co_ci_u32_e64 v13, s5, s29, v1, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v22, v14, v22, v30
v_fma_f32 v35, -v20, v33, v29
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v23, v15, v23, v31
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v33, v35, v24
v_div_fixup_f32 v22, v22, v19, v27
v_div_fixup_f32 v16, v23, v19, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v20, -v20, v33, v29
v_div_fmas_f32 v20, v20, v24, v33
s_mov_b32 vcc_lo, s4
v_div_fmas_f32 v21, v21, v25, v34
v_add_co_u32 v14, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v15, vcc_lo, s19, v1, vcc_lo
v_div_fixup_f32 v17, v20, v19, v17
s_delay_alu instid0(VALU_DEP_4)
v_div_fixup_f32 v18, v21, v19, v18
global_store_b32 v[2:3], v19, off
global_store_b32 v[4:5], v22, off
global_store_b32 v[6:7], v16, off
global_store_b32 v[8:9], v17, off
global_store_b32 v[10:11], v18, off
global_load_b32 v4, v[12:13], off
global_load_b32 v5, v[14:15], off
v_add_co_u32 v2, vcc_lo, s30, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s31, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v4, v5
v_add_co_u32 v4, vcc_lo, s20, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s21, v1, vcc_lo
global_store_b32 v[14:15], v6, off
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x80
s_load_b64 s[2:3], s[0:1], 0x90
s_load_b32 s0, s[0:1], 0x98
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v6, v7
v_add_co_u32 v6, vcc_lo, s22, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s23, v1, vcc_lo
global_store_b32 v[4:5], v8, off
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[6:7], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[6:7], v4, off
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
v_div_scale_f32 v4, null, s0, s0, s3
v_div_scale_f32 v7, vcc_lo, s3, s0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v6
v_div_fixup_f32 v4, v4, s0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e64 v5, v4, -s2
v_mul_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_fma_f32 v6, v4, 0x3fb8aa3b, -v5
v_rndne_f32_e32 v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v6, v4, 0x32a5705f, v6 :: v_dual_sub_f32 v5, v5, v7
v_add_f32_e32 v5, v5, v6
v_cvt_i32_f32_e32 v6, v7
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v2, v2, v3 :: v_dual_cndmask_b32 v3, 0x7f800000, v5
v_mul_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 160
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 37
.amdhsa_next_free_sgpr 44
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .Lfunc_end0-_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 128
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 136
.size: 8
.value_kind: global_buffer
- .offset: 144
.size: 4
.value_kind: by_value
- .offset: 148
.size: 4
.value_kind: by_value
- .offset: 152
.size: 4
.value_kind: by_value
- .offset: 156
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 160
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.private_segment_fixed_size: 0
.sgpr_count: 46
.sgpr_spill_count: 0
.symbol: _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 37
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MHDUpdatePrim_CUDA3_kernel(float *Rho, float *Vx, float *Vy, float *Vz, float *Etot, float *Bx, float *By, float *Bz, float *Phi, float *dUD, float *dUS1, float *dUS2, float *dUS3, float *dUTau, float *dUBx, float *dUBy, float *dUBz, float *dUPhi, float dt, float C_h, float C_p, int size)
{
// get thread and block index
const long tx = threadIdx.x;
const long bx = blockIdx.x;
const long by = blockIdx.y;
int igrid = tx + bx*CUDA_BLOCK_SIZE + by*CUDA_BLOCK_SIZE*CUDA_GRID_SIZE;
if (igrid < 2 || igrid > size - 3)
return;
float D, S1, S2, S3, Tau;
D = Rho[igrid];
S1 = D*Vx[igrid];
S2 = D*Vy[igrid];
S3 = D*Vz[igrid];
Tau = D*Etot[igrid];
D += dUD[igrid];
S1 += dUS1[igrid];
S2 += dUS2[igrid];
S3 += dUS3[igrid];
Tau += dUTau[igrid];
Rho[igrid] = D;
Vx[igrid] = S1/D;
Vy[igrid] = S2/D;
Vz[igrid] = S3/D;
Etot[igrid] = Tau/D;
Bx[igrid] += dUBx[igrid];
By[igrid] += dUBy[igrid];
Bz[igrid] += dUBz[igrid];
Phi[igrid] += dUPhi[igrid];
Phi[igrid] *= expf(-dt*(C_h/C_p)*(C_h/C_p));
} | .text
.file "MHDUpdatePrim_CUDA3_kernel.hip"
.globl _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi # -- Begin function _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.p2align 4, 0x90
.type _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi,@function
_Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi: # @_Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 392(%rsp), %rax
movq %rax, 248(%rsp)
leaq 12(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 4(%rsp), %rax
movq %rax, 272(%rsp)
leaq 400(%rsp), %rax
movq %rax, 280(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .Lfunc_end0-_Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi,@object # @_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.section .rodata,"a",@progbits
.globl _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.p2align 3, 0x0
_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
.quad _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.size _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi"
.size .L__unnamed_1, 71
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001025d5_00000000-6_MHDUpdatePrim_CUDA3_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.type _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, @function
_Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
.LFB2051:
.cfi_startproc
endbr64
subq $424, %rsp
.cfi_def_cfa_offset 432
movq %rdi, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rcx, 128(%rsp)
movq %r8, 120(%rsp)
movq %r9, 112(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq 432(%rsp), %rax
movq %rax, 104(%rsp)
movq 440(%rsp), %rax
movq %rax, 96(%rsp)
movq 448(%rsp), %rax
movq %rax, 88(%rsp)
movq 456(%rsp), %rax
movq %rax, 80(%rsp)
movq 464(%rsp), %rax
movq %rax, 72(%rsp)
movq 472(%rsp), %rax
movq %rax, 64(%rsp)
movq 480(%rsp), %rax
movq %rax, 56(%rsp)
movq 488(%rsp), %rax
movq %rax, 48(%rsp)
movq 496(%rsp), %rax
movq %rax, 40(%rsp)
movq 504(%rsp), %rax
movq %rax, 32(%rsp)
movq 512(%rsp), %rax
movq %rax, 24(%rsp)
movq 520(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 408(%rsp)
xorl %eax, %eax
leaq 152(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rax
movq %rax, 248(%rsp)
leaq 120(%rsp), %rax
movq %rax, 256(%rsp)
leaq 112(%rsp), %rax
movq %rax, 264(%rsp)
leaq 104(%rsp), %rax
movq %rax, 272(%rsp)
leaq 96(%rsp), %rax
movq %rax, 280(%rsp)
leaq 88(%rsp), %rax
movq %rax, 288(%rsp)
leaq 80(%rsp), %rax
movq %rax, 296(%rsp)
leaq 72(%rsp), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rax
movq %rax, 312(%rsp)
leaq 56(%rsp), %rax
movq %rax, 320(%rsp)
leaq 48(%rsp), %rax
movq %rax, 328(%rsp)
leaq 40(%rsp), %rax
movq %rax, 336(%rsp)
leaq 32(%rsp), %rax
movq %rax, 344(%rsp)
leaq 24(%rsp), %rax
movq %rax, 352(%rsp)
leaq 16(%rsp), %rax
movq %rax, 360(%rsp)
leaq 12(%rsp), %rax
movq %rax, 368(%rsp)
leaq 8(%rsp), %rax
movq %rax, 376(%rsp)
leaq 4(%rsp), %rax
movq %rax, 384(%rsp)
leaq 528(%rsp), %rax
movq %rax, 392(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
leaq 168(%rsp), %rcx
leaq 160(%rsp), %rdx
leaq 188(%rsp), %rsi
leaq 176(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 408(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $424, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 168(%rsp)
.cfi_def_cfa_offset 440
pushq 168(%rsp)
.cfi_def_cfa_offset 448
leaq 240(%rsp), %r9
movq 204(%rsp), %rcx
movl 212(%rsp), %r8d
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
leaq _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 432
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .-_Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.globl _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.type _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, @function
_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 120(%rsp)
.cfi_def_cfa_offset 40
pushq 120(%rsp)
.cfi_def_cfa_offset 48
pushq 120(%rsp)
.cfi_def_cfa_offset 56
pushq 120(%rsp)
.cfi_def_cfa_offset 64
pushq 120(%rsp)
.cfi_def_cfa_offset 72
pushq 120(%rsp)
.cfi_def_cfa_offset 80
pushq 120(%rsp)
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
call _Z84__device_stub__Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffiPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .-_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MHDUpdatePrim_CUDA3_kernel.hip"
.globl _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi # -- Begin function _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.p2align 4, 0x90
.type _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi,@function
_Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi: # @_Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 392(%rsp), %rax
movq %rax, 248(%rsp)
leaq 12(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 4(%rsp), %rax
movq %rax, 272(%rsp)
leaq 400(%rsp), %rax
movq %rax, 280(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, .Lfunc_end0-_Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi,@object # @_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.section .rodata,"a",@progbits
.globl _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.p2align 3, 0x0
_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi:
.quad _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.size _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi"
.size .L__unnamed_1, 71
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26MHDUpdatePrim_CUDA3_kernelPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_S_fffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Add 2 numbers
#include<iostream>
__global__ void numadd(float *d_a, float *d_b, float *d_c){
// int i = blockDim.x * blockIdx.x + threadIdx.x;
*d_c = *d_a + *d_b;
}
int main(){
float h_a, h_b, h_c;
std::cout << "Enter a number" << std::endl;
std::cin >> h_a;
std::cout << "Enter another number" << std::endl;
std::cin >> h_b;
size_t size = sizeof(float);
float *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
cudaMemcpy(d_a, &h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, size, cudaMemcpyHostToDevice);
int numBlocks = 1;
int threadsPerBlock = 1;
numadd<<<numBlocks, threadsPerBlock>>>(d_a, d_b, d_c);
cudaMemcpy(&h_c, d_c, size, cudaMemcpyDeviceToHost);
std::cout << "The sum is: "<< h_c << std::endl;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z6numaddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*00a0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Add 2 numbers
#include<iostream>
__global__ void numadd(float *d_a, float *d_b, float *d_c){
// int i = blockDim.x * blockIdx.x + threadIdx.x;
*d_c = *d_a + *d_b;
}
int main(){
float h_a, h_b, h_c;
std::cout << "Enter a number" << std::endl;
std::cin >> h_a;
std::cout << "Enter another number" << std::endl;
std::cin >> h_b;
size_t size = sizeof(float);
float *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
cudaMemcpy(d_a, &h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, size, cudaMemcpyHostToDevice);
int numBlocks = 1;
int threadsPerBlock = 1;
numadd<<<numBlocks, threadsPerBlock>>>(d_a, d_b, d_c);
cudaMemcpy(&h_c, d_c, size, cudaMemcpyDeviceToHost);
std::cout << "The sum is: "<< h_c << std::endl;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_001aa085_00000000-6_num_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6numaddPfS_S_PfS_S_
.type _Z29__device_stub__Z6numaddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6numaddPfS_S_PfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6numaddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6numaddPfS_S_PfS_S_, .-_Z29__device_stub__Z6numaddPfS_S_PfS_S_
.globl _Z6numaddPfS_S_
.type _Z6numaddPfS_S_, @function
_Z6numaddPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6numaddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6numaddPfS_S_, .-_Z6numaddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter a number"
.LC1:
.string "Enter another number"
.LC2:
.string "The sum is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rbp
movq %rbp, %rsi
leaq _ZSt3cin(%rip), %r12
movq %r12, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 4(%rsp), %rbx
movq %rbx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6numaddPfS_S_PfS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6numaddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6numaddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Add 2 numbers
#include<iostream>
__global__ void numadd(float *d_a, float *d_b, float *d_c){
// int i = blockDim.x * blockIdx.x + threadIdx.x;
*d_c = *d_a + *d_b;
}
int main(){
float h_a, h_b, h_c;
std::cout << "Enter a number" << std::endl;
std::cin >> h_a;
std::cout << "Enter another number" << std::endl;
std::cin >> h_b;
size_t size = sizeof(float);
float *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
cudaMemcpy(d_a, &h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, size, cudaMemcpyHostToDevice);
int numBlocks = 1;
int threadsPerBlock = 1;
numadd<<<numBlocks, threadsPerBlock>>>(d_a, d_b, d_c);
cudaMemcpy(&h_c, d_c, size, cudaMemcpyDeviceToHost);
std::cout << "The sum is: "<< h_c << std::endl;
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | // Add 2 numbers
#include <hip/hip_runtime.h>
#include<iostream>
__global__ void numadd(float *d_a, float *d_b, float *d_c){
// int i = blockDim.x * blockIdx.x + threadIdx.x;
*d_c = *d_a + *d_b;
}
int main(){
float h_a, h_b, h_c;
std::cout << "Enter a number" << std::endl;
std::cin >> h_a;
std::cout << "Enter another number" << std::endl;
std::cin >> h_b;
size_t size = sizeof(float);
float *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
hipMemcpy(d_a, &h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, size, hipMemcpyHostToDevice);
int numBlocks = 1;
int threadsPerBlock = 1;
numadd<<<numBlocks, threadsPerBlock>>>(d_a, d_b, d_c);
hipMemcpy(&h_c, d_c, size, hipMemcpyDeviceToHost);
std::cout << "The sum is: "<< h_c << std::endl;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
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