system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Add 2 numbers
#include <hip/hip_runtime.h>
#include<iostream>
__global__ void numadd(float *d_a, float *d_b, float *d_c){
// int i = blockDim.x * blockIdx.x + threadIdx.x;
*d_c = *d_a + *d_b;
}
int main(){
float h_a, h_b, h_c;
std::cout << "Enter a number" << std::endl;
std::cin >> h_a;
std::cout << "Enter another number" << std::endl;
std::cin >> h_b;
size_t size = sizeof(float);
float *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
hipMemcpy(d_a, &h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, size, hipMemcpyHostToDevice);
int numBlocks = 1;
int threadsPerBlock = 1;
numadd<<<numBlocks, threadsPerBlock>>>(d_a, d_b, d_c);
hipMemcpy(&h_c, d_c, size, hipMemcpyDeviceToHost);
std::cout << "The sum is: "<< h_c << std::endl;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6numaddPfS_S_
.globl _Z6numaddPfS_S_
.p2align 8
.type _Z6numaddPfS_S_,@function
_Z6numaddPfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s2, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6numaddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6numaddPfS_S_, .Lfunc_end0-_Z6numaddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6numaddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6numaddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Add 2 numbers
#include <hip/hip_runtime.h>
#include<iostream>
__global__ void numadd(float *d_a, float *d_b, float *d_c){
// int i = blockDim.x * blockIdx.x + threadIdx.x;
*d_c = *d_a + *d_b;
}
int main(){
float h_a, h_b, h_c;
std::cout << "Enter a number" << std::endl;
std::cin >> h_a;
std::cout << "Enter another number" << std::endl;
std::cin >> h_b;
size_t size = sizeof(float);
float *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
hipMemcpy(d_a, &h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, size, hipMemcpyHostToDevice);
int numBlocks = 1;
int threadsPerBlock = 1;
numadd<<<numBlocks, threadsPerBlock>>>(d_a, d_b, d_c);
hipMemcpy(&h_c, d_c, size, hipMemcpyDeviceToHost);
std::cout << "The sum is: "<< h_c << std::endl;
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "num_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__numaddPfS_S_ # -- Begin function _Z21__device_stub__numaddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__numaddPfS_S_,@function
_Z21__device_stub__numaddPfS_S_: # @_Z21__device_stub__numaddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6numaddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__numaddPfS_S_, .Lfunc_end0-_Z21__device_stub__numaddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 28(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSi10_M_extractIfEERSiRT_
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 132(%rsp), %rbx
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6numaddPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6numaddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6numaddPfS_S_,@object # @_Z6numaddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6numaddPfS_S_
.p2align 3, 0x0
_Z6numaddPfS_S_:
.quad _Z21__device_stub__numaddPfS_S_
.size _Z6numaddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter a number"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enter another number"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The sum is: "
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6numaddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__numaddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6numaddPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6numaddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*00a0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6numaddPfS_S_
.globl _Z6numaddPfS_S_
.p2align 8
.type _Z6numaddPfS_S_,@function
_Z6numaddPfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s2, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6numaddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6numaddPfS_S_, .Lfunc_end0-_Z6numaddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6numaddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6numaddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa085_00000000-6_num_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6numaddPfS_S_PfS_S_
.type _Z29__device_stub__Z6numaddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6numaddPfS_S_PfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6numaddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6numaddPfS_S_PfS_S_, .-_Z29__device_stub__Z6numaddPfS_S_PfS_S_
.globl _Z6numaddPfS_S_
.type _Z6numaddPfS_S_, @function
_Z6numaddPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6numaddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6numaddPfS_S_, .-_Z6numaddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter a number"
.LC1:
.string "Enter another number"
.LC2:
.string "The sum is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rbp
movq %rbp, %rsi
leaq _ZSt3cin(%rip), %r12
movq %r12, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 4(%rsp), %rbx
movq %rbx, %rsi
movq %r12, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6numaddPfS_S_PfS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6numaddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6numaddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "num_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__numaddPfS_S_ # -- Begin function _Z21__device_stub__numaddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__numaddPfS_S_,@function
_Z21__device_stub__numaddPfS_S_: # @_Z21__device_stub__numaddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6numaddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__numaddPfS_S_, .Lfunc_end0-_Z21__device_stub__numaddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 28(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSi10_M_extractIfEERSiRT_
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 132(%rsp), %rbx
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6numaddPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6numaddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6numaddPfS_S_,@object # @_Z6numaddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6numaddPfS_S_
.p2align 3, 0x0
_Z6numaddPfS_S_:
.quad _Z21__device_stub__numaddPfS_S_
.size _Z6numaddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter a number"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enter another number"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The sum is: "
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6numaddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__numaddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6numaddPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "torch_kernels.cuh"
__global__ void indexSelectSmallIndex(float *dst, float *src, int64_t *indices,
int64_t innerSize, int64_t numIndices) {
// In order to avoid reloading the index that we are copying, load
// it once to handle all of the points that are being selected, so
// it can be reused as much as possible. This kernel is chosen when
// this is a good choice (small number of chosen indices), since
// re-accessing indices in addition to src elements can be slow.
for (int64_t dstIndex = 0; dstIndex < numIndices; ++dstIndex) {
int64_t srcIndex = indices[dstIndex];
// We stride over the output ignoring the indexed dimension
// (innerSize), whose offset calculation is handled differently
for (int64_t linearIndex = blockIdx.x * blockDim.x + threadIdx.x;
linearIndex < innerSize; linearIndex += gridDim.x * blockDim.x) {
dst[dstIndex * innerSize + linearIndex] =
src[srcIndex * innerSize + linearIndex];
}
}
}
__global__ void indexSelectLargeIndex(float *dst, float *src, int64_t *indices,
int64_t totalSize, int64_t innerSize) {
// We stride over the output including the indexed dimension
// (totalSize), and calculate the destination index point based on that
for (int64_t linearIndex = blockIdx.x * blockDim.x + threadIdx.x;
linearIndex < totalSize; linearIndex += gridDim.x * blockDim.x) {
int64_t dstIndex, elementInSlice;
dstIndex = linearIndex / innerSize;
elementInSlice = linearIndex % innerSize;
int64_t srcIndex = indices[dstIndex];
int64_t dstOffset = elementInSlice;
dstOffset += dstIndex * innerSize;
int64_t srcOffset = elementInSlice;
srcOffset += srcIndex * innerSize;
dst[dstOffset] = src[srcOffset];
}
}
template <typename T> __device__ __forceinline__ T sigmoid(T in) {
T one = static_cast<T>(1.0);
return one / (one + exp(-in));
}
// bias1: input_bias, bias2: hidden_bias, cx: last cell state, hsz: hidden_size
__global__ void lstm_cell_kernel(float *input, float *hidden, float *bias1,
float *bias2, float *_cx, float *_hy,
float *_cy, int hsz, int totalElements) {
for (int linearIndex = blockIdx.x * blockDim.x + threadIdx.x;
linearIndex < totalElements; linearIndex += gridDim.x * blockDim.x) {
int offset = (linearIndex / hsz) * 4 * hsz + linearIndex % hsz;
float iig = input[offset + 0 * hsz];
float ifg = input[offset + 1 * hsz];
float icg = input[offset + 2 * hsz];
float iog = input[offset + 3 * hsz];
float hig = hidden[offset + 0 * hsz];
float hfg = hidden[offset + 1 * hsz];
float hcg = hidden[offset + 2 * hsz];
float hog = hidden[offset + 3 * hsz];
float cx = _cx[linearIndex];
float *hy = &_hy[linearIndex];
float *cy = &_cy[linearIndex];
float b1i, b1f, b1c, b1o;
float b2i, b2f, b2c, b2o;
b1i = bias1[linearIndex % hsz + 0 * hsz];
b1f = bias1[linearIndex % hsz + 1 * hsz];
b1c = bias1[linearIndex % hsz + 2 * hsz];
b1o = bias1[linearIndex % hsz + 3 * hsz];
b2i = bias2[linearIndex % hsz + 0 * hsz];
b2f = bias2[linearIndex % hsz + 1 * hsz];
b2c = bias2[linearIndex % hsz + 2 * hsz];
b2o = bias2[linearIndex % hsz + 3 * hsz];
float ig, fg, cg, og;
float f_hy, f_cy;
ig = sigmoid(iig + hig + b1i + b2i);
fg = sigmoid(ifg + hfg + b1f + b2f);
cg = tanh(icg + hcg + b1c + b2c);
og = sigmoid(iog + hog + b1o + b2o);
f_cy = (fg * cx) + (ig * cg);
f_hy = og * tanh(f_cy);
*hy = f_hy;
*cy = f_cy;
}
} | .file "tmpxft_0000d1b0_00000000-6_torch_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll
.type _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll, @function
_Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21indexSelectSmallIndexPfS_Plll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll, .-_Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll
.globl _Z21indexSelectSmallIndexPfS_Plll
.type _Z21indexSelectSmallIndexPfS_Plll, @function
_Z21indexSelectSmallIndexPfS_Plll:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z21indexSelectSmallIndexPfS_Plll, .-_Z21indexSelectSmallIndexPfS_Plll
.globl _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll
.type _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll, @function
_Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21indexSelectLargeIndexPfS_Plll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll, .-_Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll
.globl _Z21indexSelectLargeIndexPfS_Plll
.type _Z21indexSelectLargeIndexPfS_Plll, @function
_Z21indexSelectLargeIndexPfS_Plll:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z21indexSelectLargeIndexPfS_Plll, .-_Z21indexSelectLargeIndexPfS_Plll
.globl _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii
.type _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii, @function
_Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii, .-_Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii
.globl _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii
.type _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii, @function
_Z16lstm_cell_kernelPfS_S_S_S_S_S_ii:
.LFB2057:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii, .-_Z16lstm_cell_kernelPfS_S_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16lstm_cell_kernelPfS_S_S_S_S_S_ii"
.align 8
.LC1:
.string "_Z21indexSelectLargeIndexPfS_Plll"
.align 8
.LC2:
.string "_Z21indexSelectSmallIndexPfS_Plll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21indexSelectLargeIndexPfS_Plll(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21indexSelectSmallIndexPfS_Plll(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "torch_kernels.cuh"
__global__ void indexSelectSmallIndex(float *dst, float *src, int64_t *indices,
int64_t innerSize, int64_t numIndices) {
// In order to avoid reloading the index that we are copying, load
// it once to handle all of the points that are being selected, so
// it can be reused as much as possible. This kernel is chosen when
// this is a good choice (small number of chosen indices), since
// re-accessing indices in addition to src elements can be slow.
for (int64_t dstIndex = 0; dstIndex < numIndices; ++dstIndex) {
int64_t srcIndex = indices[dstIndex];
// We stride over the output ignoring the indexed dimension
// (innerSize), whose offset calculation is handled differently
for (int64_t linearIndex = blockIdx.x * blockDim.x + threadIdx.x;
linearIndex < innerSize; linearIndex += gridDim.x * blockDim.x) {
dst[dstIndex * innerSize + linearIndex] =
src[srcIndex * innerSize + linearIndex];
}
}
}
__global__ void indexSelectLargeIndex(float *dst, float *src, int64_t *indices,
int64_t totalSize, int64_t innerSize) {
// We stride over the output including the indexed dimension
// (totalSize), and calculate the destination index point based on that
for (int64_t linearIndex = blockIdx.x * blockDim.x + threadIdx.x;
linearIndex < totalSize; linearIndex += gridDim.x * blockDim.x) {
int64_t dstIndex, elementInSlice;
dstIndex = linearIndex / innerSize;
elementInSlice = linearIndex % innerSize;
int64_t srcIndex = indices[dstIndex];
int64_t dstOffset = elementInSlice;
dstOffset += dstIndex * innerSize;
int64_t srcOffset = elementInSlice;
srcOffset += srcIndex * innerSize;
dst[dstOffset] = src[srcOffset];
}
}
template <typename T> __device__ __forceinline__ T sigmoid(T in) {
T one = static_cast<T>(1.0);
return one / (one + exp(-in));
}
// bias1: input_bias, bias2: hidden_bias, cx: last cell state, hsz: hidden_size
__global__ void lstm_cell_kernel(float *input, float *hidden, float *bias1,
float *bias2, float *_cx, float *_hy,
float *_cy, int hsz, int totalElements) {
for (int linearIndex = blockIdx.x * blockDim.x + threadIdx.x;
linearIndex < totalElements; linearIndex += gridDim.x * blockDim.x) {
int offset = (linearIndex / hsz) * 4 * hsz + linearIndex % hsz;
float iig = input[offset + 0 * hsz];
float ifg = input[offset + 1 * hsz];
float icg = input[offset + 2 * hsz];
float iog = input[offset + 3 * hsz];
float hig = hidden[offset + 0 * hsz];
float hfg = hidden[offset + 1 * hsz];
float hcg = hidden[offset + 2 * hsz];
float hog = hidden[offset + 3 * hsz];
float cx = _cx[linearIndex];
float *hy = &_hy[linearIndex];
float *cy = &_cy[linearIndex];
float b1i, b1f, b1c, b1o;
float b2i, b2f, b2c, b2o;
b1i = bias1[linearIndex % hsz + 0 * hsz];
b1f = bias1[linearIndex % hsz + 1 * hsz];
b1c = bias1[linearIndex % hsz + 2 * hsz];
b1o = bias1[linearIndex % hsz + 3 * hsz];
b2i = bias2[linearIndex % hsz + 0 * hsz];
b2f = bias2[linearIndex % hsz + 1 * hsz];
b2c = bias2[linearIndex % hsz + 2 * hsz];
b2o = bias2[linearIndex % hsz + 3 * hsz];
float ig, fg, cg, og;
float f_hy, f_cy;
ig = sigmoid(iig + hig + b1i + b2i);
fg = sigmoid(ifg + hfg + b1f + b2f);
cg = tanh(icg + hcg + b1c + b2c);
og = sigmoid(iog + hog + b1o + b2o);
f_cy = (fg * cx) + (ig * cg);
f_hy = og * tanh(f_cy);
*hy = f_hy;
*cy = f_cy;
}
} | #pragma once
#include <hip/hip_runtime.h>
#define AT_APPLY_THREADS_PER_BLOCK 512
#define THCCeilDiv(a, b) (a + b - 1) / b
__global__ void indexSelectSmallIndex(float *dst, float *src, int64_t *indices,
int64_t innerSize, int64_t numIndices);
__global__ void indexSelectLargeIndex(float *dst, float *src, int64_t *indices,
int64_t totalSize, int64_t innerSize);
__global__ void lstm_cell_kernel(float *input, float *hidden, float *bias1,
float *bias2, float *_cx, float *_hy,
float *_cy, int hsz, int totalElements); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#define AT_APPLY_THREADS_PER_BLOCK 512
#define THCCeilDiv(a, b) (a + b - 1) / b
__global__ void indexSelectSmallIndex(float *dst, float *src, int64_t *indices,
int64_t innerSize, int64_t numIndices);
__global__ void indexSelectLargeIndex(float *dst, float *src, int64_t *indices,
int64_t totalSize, int64_t innerSize);
__global__ void lstm_cell_kernel(float *input, float *hidden, float *bias1,
float *bias2, float *_cx, float *_hy,
float *_cy, int hsz, int totalElements); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#define AT_APPLY_THREADS_PER_BLOCK 512
#define THCCeilDiv(a, b) (a + b - 1) / b
__global__ void indexSelectSmallIndex(float *dst, float *src, int64_t *indices,
int64_t innerSize, int64_t numIndices);
__global__ void indexSelectLargeIndex(float *dst, float *src, int64_t *indices,
int64_t totalSize, int64_t innerSize);
__global__ void lstm_cell_kernel(float *input, float *hidden, float *bias1,
float *bias2, float *_cx, float *_hy,
float *_cy, int hsz, int totalElements); | .text
.file "torch_kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000d1b0_00000000-6_torch_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll
.type _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll, @function
_Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21indexSelectSmallIndexPfS_Plll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll, .-_Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll
.globl _Z21indexSelectSmallIndexPfS_Plll
.type _Z21indexSelectSmallIndexPfS_Plll, @function
_Z21indexSelectSmallIndexPfS_Plll:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21indexSelectSmallIndexPfS_PlllPfS_Plll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z21indexSelectSmallIndexPfS_Plll, .-_Z21indexSelectSmallIndexPfS_Plll
.globl _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll
.type _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll, @function
_Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21indexSelectLargeIndexPfS_Plll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll, .-_Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll
.globl _Z21indexSelectLargeIndexPfS_Plll
.type _Z21indexSelectLargeIndexPfS_Plll, @function
_Z21indexSelectLargeIndexPfS_Plll:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21indexSelectLargeIndexPfS_PlllPfS_Plll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z21indexSelectLargeIndexPfS_Plll, .-_Z21indexSelectLargeIndexPfS_Plll
.globl _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii
.type _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii, @function
_Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii, .-_Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii
.globl _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii
.type _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii, @function
_Z16lstm_cell_kernelPfS_S_S_S_S_S_ii:
.LFB2057:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z16lstm_cell_kernelPfS_S_S_S_S_S_iiPfS_S_S_S_S_S_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii, .-_Z16lstm_cell_kernelPfS_S_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16lstm_cell_kernelPfS_S_S_S_S_S_ii"
.align 8
.LC1:
.string "_Z21indexSelectLargeIndexPfS_Plll"
.align 8
.LC2:
.string "_Z21indexSelectSmallIndexPfS_Plll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16lstm_cell_kernelPfS_S_S_S_S_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21indexSelectLargeIndexPfS_Plll(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21indexSelectSmallIndexPfS_Plll(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "torch_kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
int main()
{
int deviceCount;
cudaGetDeviceCount(&deviceCount); //Returns in *deviceCount the number of devices
cout<<"deviceCount: "<<deviceCount<<"\n\n";
if (deviceCount == 0)
{
cout<< "error: no devices supporting CUDA.\n";
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev); //Sets dev=0 device as the current device for the calling host thread.
cudaDeviceProp devProps;
cudaGetDeviceProperties(&devProps, dev);
cout<<"name: "<<devProps.name<<"\n";
cout<<"totalGlobalMem: "<<devProps.totalGlobalMem<<"\n";
cout<<"regsPerBlock: "<<devProps.regsPerBlock<<"\n";
cout<<"warpSize: "<<devProps.warpSize<<"\n";
cout<<"memPitch: "<<devProps.memPitch<<"\n\n";
cout<<"一个线程块中可使用的最大共享内存\n";
cout<<"devProps.sharedMemPerBlock: "<<devProps.sharedMemPerBlock<<"\n\n";
cout<<"一个线程块中可包含的最大线程数量\n";
cout<<"maxThreadsPerBlock: "<<devProps.maxThreadsPerBlock<<"\n\n";
cout<<"多维线程块数组中每一维可包含的最大线程数量\n";
cout<<"maxThreadsDim[0]: "<<devProps.maxThreadsDim[0]<<"\n";
cout<<"maxThreadsDim[1]: "<<devProps.maxThreadsDim[1]<<"\n";
cout<<"maxThreadsDim[2]: "<<devProps.maxThreadsDim[2]<<"\n\n";
cout<<"一个线程格中每一维可包含的最大线程块数量\n";
cout<<"maxGridSize[0]: "<<devProps.maxGridSize[0]<<"\n";
cout<<"maxGridSize[1]: "<<devProps.maxGridSize[1]<<"\n";
cout<<"maxGridSize[2]: "<<devProps.maxGridSize[2]<<"\n\n";
cout<<"clockRate: "<<devProps.clockRate<<"\n";
cout<<"totalConstMem: "<<devProps.totalConstMem<<"\n";
cout<<"textureAlignment: "<<devProps.textureAlignment<<"\n\n";
cout<<"计算能力："<<devProps.major<< "." <<devProps.minor<<"\n\n";
cout<<"minor: "<<devProps.minor<<"\n";
cout<<"texturePitchAlignment: "<<devProps.texturePitchAlignment<<"\n";
cout<<"deviceOverlap: "<<devProps.deviceOverlap<<"\n";
cout<<"multiProcessorCount: "<<devProps.multiProcessorCount<<"\n";
cout<<"kernelExecTimeoutEnabled: "<<devProps.kernelExecTimeoutEnabled<<"\n";
cout<<"integrated: "<<devProps.integrated<<"\n";
cout<<"canMapHostMemory: "<<devProps.canMapHostMemory<<"\n";
cout<<"computeMode: "<<devProps.computeMode<<"\n";
cout<<"maxTexture1D: "<<devProps.maxTexture1D<<"\n";
cout<<"maxTexture1DMipmap: "<<devProps.maxTexture1DMipmap<<"\n";
cout<<"maxTexture1DLinear: "<<devProps.maxTexture1DLinear<<"\n";
cout<<"maxTexture2D: "<<devProps.maxTexture2D<<"\n";
cout<<"maxTexture2DMipmap: "<<devProps.maxTexture2DMipmap<<"\n";
cout<<"maxTexture2DLinear: "<<devProps.maxTexture2DLinear<<"\n";
cout<<"maxTexture2DGather: "<<devProps.maxTexture2DGather<<"\n";
cout<<"maxTexture3D: "<<devProps.maxTexture3D<<"\n";
cout<<"maxTexture3DAlt: "<<devProps.maxTexture3DAlt<<"\n";
cout<<"maxTextureCubemap: "<<devProps.maxTextureCubemap<<"\n";
cout<<"maxTexture1DLayered: "<<devProps.maxTexture1DLayered<<"\n";
cout<<"maxTexture2DLayered: "<<devProps.maxTexture2DLayered<<"\n";
cout<<"maxTextureCubemapLayered: "<<devProps.maxTextureCubemapLayered<<"\n";
cout<<"maxSurface1D: "<<devProps.maxSurface1D<<"\n";
cout<<"maxSurface2D: "<<devProps.maxSurface2D<<"\n";
cout<<"maxSurface3D: "<<devProps.maxSurface3D<<"\n";
cout<<"maxSurface1DLayered: "<<devProps.maxSurface1DLayered<<"\n";
cout<<"maxSurface2DLayered: "<<devProps.maxSurface2DLayered<<"\n";
cout<<"maxSurfaceCubemap: "<<devProps.maxSurfaceCubemap<<"\n";
cout<<"maxSurfaceCubemapLayered: "<<devProps.maxSurfaceCubemapLayered<<"\n";
cout<<"surfaceAlignment: "<<devProps.surfaceAlignment<<"\n";
cout<<"concurrentKernels: "<<devProps.concurrentKernels<<"\n";
cout<<"ECCEnabled: "<<devProps.ECCEnabled<<"\n";
cout<<"pciBusID: "<<devProps.pciBusID<<"\n";
cout<<"pciDeviceID: "<<devProps.pciDeviceID<<"\n";
cout<<"pciDomainID: "<<devProps.pciDomainID<<"\n";
cout<<"tccDriver: "<<devProps.tccDriver<<"\n";
cout<<"asyncEngineCount: "<<devProps.asyncEngineCount<<"\n";
cout<<"unifiedAddressing: "<<devProps.unifiedAddressing<<"\n";
cout<<"memoryClockRate: "<<devProps.memoryClockRate<<"\n";
cout<<"memoryBusWidth: "<<devProps.memoryBusWidth<<"\n";
cout<<"l2CacheSize: "<<devProps.l2CacheSize<<"\n";
cout<<"maxThreadsPerMultiProcessor: "<<devProps.maxThreadsPerMultiProcessor<<"\n";
cout<<"streamPrioritiesSupported: "<<devProps.streamPrioritiesSupported<<"\n";
cout<<"globalL1CacheSupported: "<<devProps.globalL1CacheSupported<<"\n";
cout<<"localL1CacheSupported: "<<devProps.localL1CacheSupported<<"\n";
cout<<"sharedMemPerMultiprocessor: "<<devProps.sharedMemPerMultiprocessor<<"\n";
cout<<"regsPerMultiprocessor: "<<devProps.regsPerMultiprocessor<<"\n";
cout<<"isMultiGpuBoard: "<<devProps.isMultiGpuBoard<<"\n";
cout<<"multiGpuBoardGroupID: "<<devProps.multiGpuBoardGroupID<<"\n";
cout<<"singleToDoublePrecisionPerfRatio: "<<devProps.singleToDoublePrecisionPerfRatio<<"\n";
cout<<"pageableMemoryAccess: "<<devProps.pageableMemoryAccess<<"\n";
cout<<"concurrentManagedAccess: "<<devProps.concurrentManagedAccess<<"\n";
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
int main()
{
int deviceCount;
cudaGetDeviceCount(&deviceCount); //Returns in *deviceCount the number of devices
cout<<"deviceCount: "<<deviceCount<<"\n\n";
if (deviceCount == 0)
{
cout<< "error: no devices supporting CUDA.\n";
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev); //Sets dev=0 device as the current device for the calling host thread.
cudaDeviceProp devProps;
cudaGetDeviceProperties(&devProps, dev);
cout<<"name: "<<devProps.name<<"\n";
cout<<"totalGlobalMem: "<<devProps.totalGlobalMem<<"\n";
cout<<"regsPerBlock: "<<devProps.regsPerBlock<<"\n";
cout<<"warpSize: "<<devProps.warpSize<<"\n";
cout<<"memPitch: "<<devProps.memPitch<<"\n\n";
cout<<"一个线程块中可使用的最大共享内存\n";
cout<<"devProps.sharedMemPerBlock: "<<devProps.sharedMemPerBlock<<"\n\n";
cout<<"一个线程块中可包含的最大线程数量\n";
cout<<"maxThreadsPerBlock: "<<devProps.maxThreadsPerBlock<<"\n\n";
cout<<"多维线程块数组中每一维可包含的最大线程数量\n";
cout<<"maxThreadsDim[0]: "<<devProps.maxThreadsDim[0]<<"\n";
cout<<"maxThreadsDim[1]: "<<devProps.maxThreadsDim[1]<<"\n";
cout<<"maxThreadsDim[2]: "<<devProps.maxThreadsDim[2]<<"\n\n";
cout<<"一个线程格中每一维可包含的最大线程块数量\n";
cout<<"maxGridSize[0]: "<<devProps.maxGridSize[0]<<"\n";
cout<<"maxGridSize[1]: "<<devProps.maxGridSize[1]<<"\n";
cout<<"maxGridSize[2]: "<<devProps.maxGridSize[2]<<"\n\n";
cout<<"clockRate: "<<devProps.clockRate<<"\n";
cout<<"totalConstMem: "<<devProps.totalConstMem<<"\n";
cout<<"textureAlignment: "<<devProps.textureAlignment<<"\n\n";
cout<<"计算能力："<<devProps.major<< "." <<devProps.minor<<"\n\n";
cout<<"minor: "<<devProps.minor<<"\n";
cout<<"texturePitchAlignment: "<<devProps.texturePitchAlignment<<"\n";
cout<<"deviceOverlap: "<<devProps.deviceOverlap<<"\n";
cout<<"multiProcessorCount: "<<devProps.multiProcessorCount<<"\n";
cout<<"kernelExecTimeoutEnabled: "<<devProps.kernelExecTimeoutEnabled<<"\n";
cout<<"integrated: "<<devProps.integrated<<"\n";
cout<<"canMapHostMemory: "<<devProps.canMapHostMemory<<"\n";
cout<<"computeMode: "<<devProps.computeMode<<"\n";
cout<<"maxTexture1D: "<<devProps.maxTexture1D<<"\n";
cout<<"maxTexture1DMipmap: "<<devProps.maxTexture1DMipmap<<"\n";
cout<<"maxTexture1DLinear: "<<devProps.maxTexture1DLinear<<"\n";
cout<<"maxTexture2D: "<<devProps.maxTexture2D<<"\n";
cout<<"maxTexture2DMipmap: "<<devProps.maxTexture2DMipmap<<"\n";
cout<<"maxTexture2DLinear: "<<devProps.maxTexture2DLinear<<"\n";
cout<<"maxTexture2DGather: "<<devProps.maxTexture2DGather<<"\n";
cout<<"maxTexture3D: "<<devProps.maxTexture3D<<"\n";
cout<<"maxTexture3DAlt: "<<devProps.maxTexture3DAlt<<"\n";
cout<<"maxTextureCubemap: "<<devProps.maxTextureCubemap<<"\n";
cout<<"maxTexture1DLayered: "<<devProps.maxTexture1DLayered<<"\n";
cout<<"maxTexture2DLayered: "<<devProps.maxTexture2DLayered<<"\n";
cout<<"maxTextureCubemapLayered: "<<devProps.maxTextureCubemapLayered<<"\n";
cout<<"maxSurface1D: "<<devProps.maxSurface1D<<"\n";
cout<<"maxSurface2D: "<<devProps.maxSurface2D<<"\n";
cout<<"maxSurface3D: "<<devProps.maxSurface3D<<"\n";
cout<<"maxSurface1DLayered: "<<devProps.maxSurface1DLayered<<"\n";
cout<<"maxSurface2DLayered: "<<devProps.maxSurface2DLayered<<"\n";
cout<<"maxSurfaceCubemap: "<<devProps.maxSurfaceCubemap<<"\n";
cout<<"maxSurfaceCubemapLayered: "<<devProps.maxSurfaceCubemapLayered<<"\n";
cout<<"surfaceAlignment: "<<devProps.surfaceAlignment<<"\n";
cout<<"concurrentKernels: "<<devProps.concurrentKernels<<"\n";
cout<<"ECCEnabled: "<<devProps.ECCEnabled<<"\n";
cout<<"pciBusID: "<<devProps.pciBusID<<"\n";
cout<<"pciDeviceID: "<<devProps.pciDeviceID<<"\n";
cout<<"pciDomainID: "<<devProps.pciDomainID<<"\n";
cout<<"tccDriver: "<<devProps.tccDriver<<"\n";
cout<<"asyncEngineCount: "<<devProps.asyncEngineCount<<"\n";
cout<<"unifiedAddressing: "<<devProps.unifiedAddressing<<"\n";
cout<<"memoryClockRate: "<<devProps.memoryClockRate<<"\n";
cout<<"memoryBusWidth: "<<devProps.memoryBusWidth<<"\n";
cout<<"l2CacheSize: "<<devProps.l2CacheSize<<"\n";
cout<<"maxThreadsPerMultiProcessor: "<<devProps.maxThreadsPerMultiProcessor<<"\n";
cout<<"streamPrioritiesSupported: "<<devProps.streamPrioritiesSupported<<"\n";
cout<<"globalL1CacheSupported: "<<devProps.globalL1CacheSupported<<"\n";
cout<<"localL1CacheSupported: "<<devProps.localL1CacheSupported<<"\n";
cout<<"sharedMemPerMultiprocessor: "<<devProps.sharedMemPerMultiprocessor<<"\n";
cout<<"regsPerMultiprocessor: "<<devProps.regsPerMultiprocessor<<"\n";
cout<<"isMultiGpuBoard: "<<devProps.isMultiGpuBoard<<"\n";
cout<<"multiGpuBoardGroupID: "<<devProps.multiGpuBoardGroupID<<"\n";
cout<<"singleToDoublePrecisionPerfRatio: "<<devProps.singleToDoublePrecisionPerfRatio<<"\n";
cout<<"pageableMemoryAccess: "<<devProps.pageableMemoryAccess<<"\n";
cout<<"concurrentManagedAccess: "<<devProps.concurrentManagedAccess<<"\n";
} | .file "tmpxft_00152ad7_00000000-6_deviceInfo.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "deviceCount: "
.LC1:
.string "\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1
.LC3:
.string "name: "
.LC4:
.string "\n"
.LC5:
.string "totalGlobalMem: "
.LC6:
.string "regsPerBlock: "
.LC7:
.string "warpSize: "
.LC8:
.string "memPitch: "
.section .rodata.str1.8
.align 8
.LC9:
.string "\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\344\270\255\345\217\257\344\275\277\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\n"
.section .rodata.str1.1
.LC10:
.string "devProps.sharedMemPerBlock: "
.section .rodata.str1.8
.align 8
.LC11:
.string "\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\344\270\255\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\n"
.section .rodata.str1.1
.LC12:
.string "maxThreadsPerBlock: "
.section .rodata.str1.8
.align 8
.LC13:
.string "\345\244\232\347\273\264\347\272\277\347\250\213\345\235\227\346\225\260\347\273\204\344\270\255\346\257\217\344\270\200\347\273\264\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\n"
.section .rodata.str1.1
.LC14:
.string "maxThreadsDim[0]: "
.LC15:
.string "maxThreadsDim[1]: "
.LC16:
.string "maxThreadsDim[2]: "
.section .rodata.str1.8
.align 8
.LC17:
.string "\344\270\200\344\270\252\347\272\277\347\250\213\346\240\274\344\270\255\346\257\217\344\270\200\347\273\264\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\345\235\227\346\225\260\351\207\217\n"
.section .rodata.str1.1
.LC18:
.string "maxGridSize[0]: "
.LC19:
.string "maxGridSize[1]: "
.LC20:
.string "maxGridSize[2]: "
.LC21:
.string "clockRate: "
.LC22:
.string "totalConstMem: "
.LC23:
.string "textureAlignment: "
.LC24:
.string "\350\256\241\347\256\227\350\203\275\345\212\233\357\274\232"
.LC25:
.string "."
.LC26:
.string "minor: "
.LC27:
.string "texturePitchAlignment: "
.LC28:
.string "deviceOverlap: "
.LC29:
.string "multiProcessorCount: "
.LC30:
.string "kernelExecTimeoutEnabled: "
.LC31:
.string "integrated: "
.LC32:
.string "canMapHostMemory: "
.LC33:
.string "computeMode: "
.LC34:
.string "maxTexture1D: "
.LC35:
.string "maxTexture1DMipmap: "
.LC36:
.string "maxTexture1DLinear: "
.LC37:
.string "maxTexture2D: "
.LC38:
.string "maxTexture2DMipmap: "
.LC39:
.string "maxTexture2DLinear: "
.LC40:
.string "maxTexture2DGather: "
.LC41:
.string "maxTexture3D: "
.LC42:
.string "maxTexture3DAlt: "
.LC43:
.string "maxTextureCubemap: "
.LC44:
.string "maxTexture1DLayered: "
.LC45:
.string "maxTexture2DLayered: "
.LC46:
.string "maxTextureCubemapLayered: "
.LC47:
.string "maxSurface1D: "
.LC48:
.string "maxSurface2D: "
.LC49:
.string "maxSurface3D: "
.LC50:
.string "maxSurface1DLayered: "
.LC51:
.string "maxSurface2DLayered: "
.LC52:
.string "maxSurfaceCubemap: "
.LC53:
.string "maxSurfaceCubemapLayered: "
.LC54:
.string "surfaceAlignment: "
.LC55:
.string "concurrentKernels: "
.LC56:
.string "ECCEnabled: "
.LC57:
.string "pciBusID: "
.LC58:
.string "pciDeviceID: "
.LC59:
.string "pciDomainID: "
.LC60:
.string "tccDriver: "
.LC61:
.string "asyncEngineCount: "
.LC62:
.string "unifiedAddressing: "
.LC63:
.string "memoryClockRate: "
.LC64:
.string "memoryBusWidth: "
.LC65:
.string "l2CacheSize: "
.LC66:
.string "maxThreadsPerMultiProcessor: "
.LC67:
.string "streamPrioritiesSupported: "
.LC68:
.string "globalL1CacheSupported: "
.LC69:
.string "localL1CacheSupported: "
.LC70:
.string "sharedMemPerMultiprocessor: "
.LC71:
.string "regsPerMultiprocessor: "
.LC72:
.string "isMultiGpuBoard: "
.LC73:
.string "multiGpuBoardGroupID: "
.section .rodata.str1.8
.align 8
.LC74:
.string "singleToDoublePrecisionPerfRatio: "
.section .rodata.str1.1
.LC75:
.string "pageableMemoryAccess: "
.LC76:
.string "concurrentManagedAccess: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 12(%rsp)
je .L7
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 320(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 324(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 328(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 312(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 336(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 340(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 344(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 348(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC17(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 352(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC19(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 356(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 360(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 364(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC22(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 368(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 384(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 376(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC25(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 380(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC26(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 380(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC27(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 392(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC28(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 400(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC29(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 404(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC30(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 408(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC31(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 412(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC32(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 416(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC33(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 420(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC34(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 424(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC35(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 428(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC36(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 432(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC37(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 436(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC38(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 444(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC39(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 452(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC40(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 464(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC41(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 472(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC42(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 484(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC43(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 496(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC44(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 500(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC45(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 508(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC46(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 520(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC47(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 528(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC48(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 532(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC49(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 540(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC50(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 552(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC51(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 560(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC52(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 572(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC53(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq 576(%rsp), %rsi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC54(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 584(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC55(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 592(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC56(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 596(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC57(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 600(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC58(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 604(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC59(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 608(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC60(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 612(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC61(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 616(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC62(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 620(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC63(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 624(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC64(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 628(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC65(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 632(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC66(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 640(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC67(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 644(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC68(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 648(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC69(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 652(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC70(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 656(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC71(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 664(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC72(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 672(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rbx
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC73(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 676(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC74(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 684(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC75(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 688(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC76(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 692(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
int main()
{
int deviceCount;
cudaGetDeviceCount(&deviceCount); //Returns in *deviceCount the number of devices
cout<<"deviceCount: "<<deviceCount<<"\n\n";
if (deviceCount == 0)
{
cout<< "error: no devices supporting CUDA.\n";
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev); //Sets dev=0 device as the current device for the calling host thread.
cudaDeviceProp devProps;
cudaGetDeviceProperties(&devProps, dev);
cout<<"name: "<<devProps.name<<"\n";
cout<<"totalGlobalMem: "<<devProps.totalGlobalMem<<"\n";
cout<<"regsPerBlock: "<<devProps.regsPerBlock<<"\n";
cout<<"warpSize: "<<devProps.warpSize<<"\n";
cout<<"memPitch: "<<devProps.memPitch<<"\n\n";
cout<<"一个线程块中可使用的最大共享内存\n";
cout<<"devProps.sharedMemPerBlock: "<<devProps.sharedMemPerBlock<<"\n\n";
cout<<"一个线程块中可包含的最大线程数量\n";
cout<<"maxThreadsPerBlock: "<<devProps.maxThreadsPerBlock<<"\n\n";
cout<<"多维线程块数组中每一维可包含的最大线程数量\n";
cout<<"maxThreadsDim[0]: "<<devProps.maxThreadsDim[0]<<"\n";
cout<<"maxThreadsDim[1]: "<<devProps.maxThreadsDim[1]<<"\n";
cout<<"maxThreadsDim[2]: "<<devProps.maxThreadsDim[2]<<"\n\n";
cout<<"一个线程格中每一维可包含的最大线程块数量\n";
cout<<"maxGridSize[0]: "<<devProps.maxGridSize[0]<<"\n";
cout<<"maxGridSize[1]: "<<devProps.maxGridSize[1]<<"\n";
cout<<"maxGridSize[2]: "<<devProps.maxGridSize[2]<<"\n\n";
cout<<"clockRate: "<<devProps.clockRate<<"\n";
cout<<"totalConstMem: "<<devProps.totalConstMem<<"\n";
cout<<"textureAlignment: "<<devProps.textureAlignment<<"\n\n";
cout<<"计算能力："<<devProps.major<< "." <<devProps.minor<<"\n\n";
cout<<"minor: "<<devProps.minor<<"\n";
cout<<"texturePitchAlignment: "<<devProps.texturePitchAlignment<<"\n";
cout<<"deviceOverlap: "<<devProps.deviceOverlap<<"\n";
cout<<"multiProcessorCount: "<<devProps.multiProcessorCount<<"\n";
cout<<"kernelExecTimeoutEnabled: "<<devProps.kernelExecTimeoutEnabled<<"\n";
cout<<"integrated: "<<devProps.integrated<<"\n";
cout<<"canMapHostMemory: "<<devProps.canMapHostMemory<<"\n";
cout<<"computeMode: "<<devProps.computeMode<<"\n";
cout<<"maxTexture1D: "<<devProps.maxTexture1D<<"\n";
cout<<"maxTexture1DMipmap: "<<devProps.maxTexture1DMipmap<<"\n";
cout<<"maxTexture1DLinear: "<<devProps.maxTexture1DLinear<<"\n";
cout<<"maxTexture2D: "<<devProps.maxTexture2D<<"\n";
cout<<"maxTexture2DMipmap: "<<devProps.maxTexture2DMipmap<<"\n";
cout<<"maxTexture2DLinear: "<<devProps.maxTexture2DLinear<<"\n";
cout<<"maxTexture2DGather: "<<devProps.maxTexture2DGather<<"\n";
cout<<"maxTexture3D: "<<devProps.maxTexture3D<<"\n";
cout<<"maxTexture3DAlt: "<<devProps.maxTexture3DAlt<<"\n";
cout<<"maxTextureCubemap: "<<devProps.maxTextureCubemap<<"\n";
cout<<"maxTexture1DLayered: "<<devProps.maxTexture1DLayered<<"\n";
cout<<"maxTexture2DLayered: "<<devProps.maxTexture2DLayered<<"\n";
cout<<"maxTextureCubemapLayered: "<<devProps.maxTextureCubemapLayered<<"\n";
cout<<"maxSurface1D: "<<devProps.maxSurface1D<<"\n";
cout<<"maxSurface2D: "<<devProps.maxSurface2D<<"\n";
cout<<"maxSurface3D: "<<devProps.maxSurface3D<<"\n";
cout<<"maxSurface1DLayered: "<<devProps.maxSurface1DLayered<<"\n";
cout<<"maxSurface2DLayered: "<<devProps.maxSurface2DLayered<<"\n";
cout<<"maxSurfaceCubemap: "<<devProps.maxSurfaceCubemap<<"\n";
cout<<"maxSurfaceCubemapLayered: "<<devProps.maxSurfaceCubemapLayered<<"\n";
cout<<"surfaceAlignment: "<<devProps.surfaceAlignment<<"\n";
cout<<"concurrentKernels: "<<devProps.concurrentKernels<<"\n";
cout<<"ECCEnabled: "<<devProps.ECCEnabled<<"\n";
cout<<"pciBusID: "<<devProps.pciBusID<<"\n";
cout<<"pciDeviceID: "<<devProps.pciDeviceID<<"\n";
cout<<"pciDomainID: "<<devProps.pciDomainID<<"\n";
cout<<"tccDriver: "<<devProps.tccDriver<<"\n";
cout<<"asyncEngineCount: "<<devProps.asyncEngineCount<<"\n";
cout<<"unifiedAddressing: "<<devProps.unifiedAddressing<<"\n";
cout<<"memoryClockRate: "<<devProps.memoryClockRate<<"\n";
cout<<"memoryBusWidth: "<<devProps.memoryBusWidth<<"\n";
cout<<"l2CacheSize: "<<devProps.l2CacheSize<<"\n";
cout<<"maxThreadsPerMultiProcessor: "<<devProps.maxThreadsPerMultiProcessor<<"\n";
cout<<"streamPrioritiesSupported: "<<devProps.streamPrioritiesSupported<<"\n";
cout<<"globalL1CacheSupported: "<<devProps.globalL1CacheSupported<<"\n";
cout<<"localL1CacheSupported: "<<devProps.localL1CacheSupported<<"\n";
cout<<"sharedMemPerMultiprocessor: "<<devProps.sharedMemPerMultiprocessor<<"\n";
cout<<"regsPerMultiprocessor: "<<devProps.regsPerMultiprocessor<<"\n";
cout<<"isMultiGpuBoard: "<<devProps.isMultiGpuBoard<<"\n";
cout<<"multiGpuBoardGroupID: "<<devProps.multiGpuBoardGroupID<<"\n";
cout<<"singleToDoublePrecisionPerfRatio: "<<devProps.singleToDoublePrecisionPerfRatio<<"\n";
cout<<"pageableMemoryAccess: "<<devProps.pageableMemoryAccess<<"\n";
cout<<"concurrentManagedAccess: "<<devProps.concurrentManagedAccess<<"\n";
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
int main()
{
int deviceCount;
hipGetDeviceCount(&deviceCount); //Returns in *deviceCount the number of devices
cout<<"deviceCount: "<<deviceCount<<"\n\n";
if (deviceCount == 0)
{
cout<< "error: no devices supporting CUDA.\n";
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev); //Sets dev=0 device as the current device for the calling host thread.
hipDeviceProp_t devProps;
hipGetDeviceProperties(&devProps, dev);
cout<<"name: "<<devProps.name<<"\n";
cout<<"totalGlobalMem: "<<devProps.totalGlobalMem<<"\n";
cout<<"regsPerBlock: "<<devProps.regsPerBlock<<"\n";
cout<<"warpSize: "<<devProps.warpSize<<"\n";
cout<<"memPitch: "<<devProps.memPitch<<"\n\n";
cout<<"一个线程块中可使用的最大共享内存\n";
cout<<"devProps.sharedMemPerBlock: "<<devProps.sharedMemPerBlock<<"\n\n";
cout<<"一个线程块中可包含的最大线程数量\n";
cout<<"maxThreadsPerBlock: "<<devProps.maxThreadsPerBlock<<"\n\n";
cout<<"多维线程块数组中每一维可包含的最大线程数量\n";
cout<<"maxThreadsDim[0]: "<<devProps.maxThreadsDim[0]<<"\n";
cout<<"maxThreadsDim[1]: "<<devProps.maxThreadsDim[1]<<"\n";
cout<<"maxThreadsDim[2]: "<<devProps.maxThreadsDim[2]<<"\n\n";
cout<<"一个线程格中每一维可包含的最大线程块数量\n";
cout<<"maxGridSize[0]: "<<devProps.maxGridSize[0]<<"\n";
cout<<"maxGridSize[1]: "<<devProps.maxGridSize[1]<<"\n";
cout<<"maxGridSize[2]: "<<devProps.maxGridSize[2]<<"\n\n";
cout<<"clockRate: "<<devProps.clockRate<<"\n";
cout<<"totalConstMem: "<<devProps.totalConstMem<<"\n";
cout<<"textureAlignment: "<<devProps.textureAlignment<<"\n\n";
cout<<"计算能力："<<devProps.major<< "." <<devProps.minor<<"\n\n";
cout<<"minor: "<<devProps.minor<<"\n";
cout<<"texturePitchAlignment: "<<devProps.texturePitchAlignment<<"\n";
cout<<"deviceOverlap: "<<devProps.deviceOverlap<<"\n";
cout<<"multiProcessorCount: "<<devProps.multiProcessorCount<<"\n";
cout<<"kernelExecTimeoutEnabled: "<<devProps.kernelExecTimeoutEnabled<<"\n";
cout<<"integrated: "<<devProps.integrated<<"\n";
cout<<"canMapHostMemory: "<<devProps.canMapHostMemory<<"\n";
cout<<"computeMode: "<<devProps.computeMode<<"\n";
cout<<"maxTexture1D: "<<devProps.maxTexture1D<<"\n";
cout<<"maxTexture1DMipmap: "<<devProps.maxTexture1DMipmap<<"\n";
cout<<"maxTexture1DLinear: "<<devProps.maxTexture1DLinear<<"\n";
cout<<"maxTexture2D: "<<devProps.maxTexture2D<<"\n";
cout<<"maxTexture2DMipmap: "<<devProps.maxTexture2DMipmap<<"\n";
cout<<"maxTexture2DLinear: "<<devProps.maxTexture2DLinear<<"\n";
cout<<"maxTexture2DGather: "<<devProps.maxTexture2DGather<<"\n";
cout<<"maxTexture3D: "<<devProps.maxTexture3D<<"\n";
cout<<"maxTexture3DAlt: "<<devProps.maxTexture3DAlt<<"\n";
cout<<"maxTextureCubemap: "<<devProps.maxTextureCubemap<<"\n";
cout<<"maxTexture1DLayered: "<<devProps.maxTexture1DLayered<<"\n";
cout<<"maxTexture2DLayered: "<<devProps.maxTexture2DLayered<<"\n";
cout<<"maxTextureCubemapLayered: "<<devProps.maxTextureCubemapLayered<<"\n";
cout<<"maxSurface1D: "<<devProps.maxSurface1D<<"\n";
cout<<"maxSurface2D: "<<devProps.maxSurface2D<<"\n";
cout<<"maxSurface3D: "<<devProps.maxSurface3D<<"\n";
cout<<"maxSurface1DLayered: "<<devProps.maxSurface1DLayered<<"\n";
cout<<"maxSurface2DLayered: "<<devProps.maxSurface2DLayered<<"\n";
cout<<"maxSurfaceCubemap: "<<devProps.maxSurfaceCubemap<<"\n";
cout<<"maxSurfaceCubemapLayered: "<<devProps.maxSurfaceCubemapLayered<<"\n";
cout<<"surfaceAlignment: "<<devProps.surfaceAlignment<<"\n";
cout<<"concurrentKernels: "<<devProps.concurrentKernels<<"\n";
cout<<"ECCEnabled: "<<devProps.ECCEnabled<<"\n";
cout<<"pciBusID: "<<devProps.pciBusID<<"\n";
cout<<"pciDeviceID: "<<devProps.pciDeviceID<<"\n";
cout<<"pciDomainID: "<<devProps.pciDomainID<<"\n";
cout<<"tccDriver: "<<devProps.tccDriver<<"\n";
cout<<"asyncEngineCount: "<<devProps.asyncEngineCount<<"\n";
cout<<"unifiedAddressing: "<<devProps.unifiedAddressing<<"\n";
cout<<"memoryClockRate: "<<devProps.memoryClockRate<<"\n";
cout<<"memoryBusWidth: "<<devProps.memoryBusWidth<<"\n";
cout<<"l2CacheSize: "<<devProps.l2CacheSize<<"\n";
cout<<"maxThreadsPerMultiProcessor: "<<devProps.maxThreadsPerMultiProcessor<<"\n";
cout<<"streamPrioritiesSupported: "<<devProps.streamPrioritiesSupported<<"\n";
cout<<"globalL1CacheSupported: "<<devProps.globalL1CacheSupported<<"\n";
cout<<"localL1CacheSupported: "<<devProps.localL1CacheSupported<<"\n";
cout<<"sharedMemPerMultiprocessor: "<<devProps.sharedMemPerMultiprocessor<<"\n";
cout<<"regsPerMultiprocessor: "<<devProps.regsPerMultiprocessor<<"\n";
cout<<"isMultiGpuBoard: "<<devProps.isMultiGpuBoard<<"\n";
cout<<"multiGpuBoardGroupID: "<<devProps.multiGpuBoardGroupID<<"\n";
cout<<"singleToDoublePrecisionPerfRatio: "<<devProps.singleToDoublePrecisionPerfRatio<<"\n";
cout<<"pageableMemoryAccess: "<<devProps.pageableMemoryAccess<<"\n";
cout<<"concurrentManagedAccess: "<<devProps.concurrentManagedAccess<<"\n";
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
int main()
{
int deviceCount;
hipGetDeviceCount(&deviceCount); //Returns in *deviceCount the number of devices
cout<<"deviceCount: "<<deviceCount<<"\n\n";
if (deviceCount == 0)
{
cout<< "error: no devices supporting CUDA.\n";
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev); //Sets dev=0 device as the current device for the calling host thread.
hipDeviceProp_t devProps;
hipGetDeviceProperties(&devProps, dev);
cout<<"name: "<<devProps.name<<"\n";
cout<<"totalGlobalMem: "<<devProps.totalGlobalMem<<"\n";
cout<<"regsPerBlock: "<<devProps.regsPerBlock<<"\n";
cout<<"warpSize: "<<devProps.warpSize<<"\n";
cout<<"memPitch: "<<devProps.memPitch<<"\n\n";
cout<<"一个线程块中可使用的最大共享内存\n";
cout<<"devProps.sharedMemPerBlock: "<<devProps.sharedMemPerBlock<<"\n\n";
cout<<"一个线程块中可包含的最大线程数量\n";
cout<<"maxThreadsPerBlock: "<<devProps.maxThreadsPerBlock<<"\n\n";
cout<<"多维线程块数组中每一维可包含的最大线程数量\n";
cout<<"maxThreadsDim[0]: "<<devProps.maxThreadsDim[0]<<"\n";
cout<<"maxThreadsDim[1]: "<<devProps.maxThreadsDim[1]<<"\n";
cout<<"maxThreadsDim[2]: "<<devProps.maxThreadsDim[2]<<"\n\n";
cout<<"一个线程格中每一维可包含的最大线程块数量\n";
cout<<"maxGridSize[0]: "<<devProps.maxGridSize[0]<<"\n";
cout<<"maxGridSize[1]: "<<devProps.maxGridSize[1]<<"\n";
cout<<"maxGridSize[2]: "<<devProps.maxGridSize[2]<<"\n\n";
cout<<"clockRate: "<<devProps.clockRate<<"\n";
cout<<"totalConstMem: "<<devProps.totalConstMem<<"\n";
cout<<"textureAlignment: "<<devProps.textureAlignment<<"\n\n";
cout<<"计算能力："<<devProps.major<< "." <<devProps.minor<<"\n\n";
cout<<"minor: "<<devProps.minor<<"\n";
cout<<"texturePitchAlignment: "<<devProps.texturePitchAlignment<<"\n";
cout<<"deviceOverlap: "<<devProps.deviceOverlap<<"\n";
cout<<"multiProcessorCount: "<<devProps.multiProcessorCount<<"\n";
cout<<"kernelExecTimeoutEnabled: "<<devProps.kernelExecTimeoutEnabled<<"\n";
cout<<"integrated: "<<devProps.integrated<<"\n";
cout<<"canMapHostMemory: "<<devProps.canMapHostMemory<<"\n";
cout<<"computeMode: "<<devProps.computeMode<<"\n";
cout<<"maxTexture1D: "<<devProps.maxTexture1D<<"\n";
cout<<"maxTexture1DMipmap: "<<devProps.maxTexture1DMipmap<<"\n";
cout<<"maxTexture1DLinear: "<<devProps.maxTexture1DLinear<<"\n";
cout<<"maxTexture2D: "<<devProps.maxTexture2D<<"\n";
cout<<"maxTexture2DMipmap: "<<devProps.maxTexture2DMipmap<<"\n";
cout<<"maxTexture2DLinear: "<<devProps.maxTexture2DLinear<<"\n";
cout<<"maxTexture2DGather: "<<devProps.maxTexture2DGather<<"\n";
cout<<"maxTexture3D: "<<devProps.maxTexture3D<<"\n";
cout<<"maxTexture3DAlt: "<<devProps.maxTexture3DAlt<<"\n";
cout<<"maxTextureCubemap: "<<devProps.maxTextureCubemap<<"\n";
cout<<"maxTexture1DLayered: "<<devProps.maxTexture1DLayered<<"\n";
cout<<"maxTexture2DLayered: "<<devProps.maxTexture2DLayered<<"\n";
cout<<"maxTextureCubemapLayered: "<<devProps.maxTextureCubemapLayered<<"\n";
cout<<"maxSurface1D: "<<devProps.maxSurface1D<<"\n";
cout<<"maxSurface2D: "<<devProps.maxSurface2D<<"\n";
cout<<"maxSurface3D: "<<devProps.maxSurface3D<<"\n";
cout<<"maxSurface1DLayered: "<<devProps.maxSurface1DLayered<<"\n";
cout<<"maxSurface2DLayered: "<<devProps.maxSurface2DLayered<<"\n";
cout<<"maxSurfaceCubemap: "<<devProps.maxSurfaceCubemap<<"\n";
cout<<"maxSurfaceCubemapLayered: "<<devProps.maxSurfaceCubemapLayered<<"\n";
cout<<"surfaceAlignment: "<<devProps.surfaceAlignment<<"\n";
cout<<"concurrentKernels: "<<devProps.concurrentKernels<<"\n";
cout<<"ECCEnabled: "<<devProps.ECCEnabled<<"\n";
cout<<"pciBusID: "<<devProps.pciBusID<<"\n";
cout<<"pciDeviceID: "<<devProps.pciDeviceID<<"\n";
cout<<"pciDomainID: "<<devProps.pciDomainID<<"\n";
cout<<"tccDriver: "<<devProps.tccDriver<<"\n";
cout<<"asyncEngineCount: "<<devProps.asyncEngineCount<<"\n";
cout<<"unifiedAddressing: "<<devProps.unifiedAddressing<<"\n";
cout<<"memoryClockRate: "<<devProps.memoryClockRate<<"\n";
cout<<"memoryBusWidth: "<<devProps.memoryBusWidth<<"\n";
cout<<"l2CacheSize: "<<devProps.l2CacheSize<<"\n";
cout<<"maxThreadsPerMultiProcessor: "<<devProps.maxThreadsPerMultiProcessor<<"\n";
cout<<"streamPrioritiesSupported: "<<devProps.streamPrioritiesSupported<<"\n";
cout<<"globalL1CacheSupported: "<<devProps.globalL1CacheSupported<<"\n";
cout<<"localL1CacheSupported: "<<devProps.localL1CacheSupported<<"\n";
cout<<"sharedMemPerMultiprocessor: "<<devProps.sharedMemPerMultiprocessor<<"\n";
cout<<"regsPerMultiprocessor: "<<devProps.regsPerMultiprocessor<<"\n";
cout<<"isMultiGpuBoard: "<<devProps.isMultiGpuBoard<<"\n";
cout<<"multiGpuBoardGroupID: "<<devProps.multiGpuBoardGroupID<<"\n";
cout<<"singleToDoublePrecisionPerfRatio: "<<devProps.singleToDoublePrecisionPerfRatio<<"\n";
cout<<"pageableMemoryAccess: "<<devProps.pageableMemoryAccess<<"\n";
cout<<"concurrentManagedAccess: "<<devProps.concurrentManagedAccess<<"\n";
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
int main()
{
int deviceCount;
hipGetDeviceCount(&deviceCount); //Returns in *deviceCount the number of devices
cout<<"deviceCount: "<<deviceCount<<"\n\n";
if (deviceCount == 0)
{
cout<< "error: no devices supporting CUDA.\n";
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev); //Sets dev=0 device as the current device for the calling host thread.
hipDeviceProp_t devProps;
hipGetDeviceProperties(&devProps, dev);
cout<<"name: "<<devProps.name<<"\n";
cout<<"totalGlobalMem: "<<devProps.totalGlobalMem<<"\n";
cout<<"regsPerBlock: "<<devProps.regsPerBlock<<"\n";
cout<<"warpSize: "<<devProps.warpSize<<"\n";
cout<<"memPitch: "<<devProps.memPitch<<"\n\n";
cout<<"一个线程块中可使用的最大共享内存\n";
cout<<"devProps.sharedMemPerBlock: "<<devProps.sharedMemPerBlock<<"\n\n";
cout<<"一个线程块中可包含的最大线程数量\n";
cout<<"maxThreadsPerBlock: "<<devProps.maxThreadsPerBlock<<"\n\n";
cout<<"多维线程块数组中每一维可包含的最大线程数量\n";
cout<<"maxThreadsDim[0]: "<<devProps.maxThreadsDim[0]<<"\n";
cout<<"maxThreadsDim[1]: "<<devProps.maxThreadsDim[1]<<"\n";
cout<<"maxThreadsDim[2]: "<<devProps.maxThreadsDim[2]<<"\n\n";
cout<<"一个线程格中每一维可包含的最大线程块数量\n";
cout<<"maxGridSize[0]: "<<devProps.maxGridSize[0]<<"\n";
cout<<"maxGridSize[1]: "<<devProps.maxGridSize[1]<<"\n";
cout<<"maxGridSize[2]: "<<devProps.maxGridSize[2]<<"\n\n";
cout<<"clockRate: "<<devProps.clockRate<<"\n";
cout<<"totalConstMem: "<<devProps.totalConstMem<<"\n";
cout<<"textureAlignment: "<<devProps.textureAlignment<<"\n\n";
cout<<"计算能力："<<devProps.major<< "." <<devProps.minor<<"\n\n";
cout<<"minor: "<<devProps.minor<<"\n";
cout<<"texturePitchAlignment: "<<devProps.texturePitchAlignment<<"\n";
cout<<"deviceOverlap: "<<devProps.deviceOverlap<<"\n";
cout<<"multiProcessorCount: "<<devProps.multiProcessorCount<<"\n";
cout<<"kernelExecTimeoutEnabled: "<<devProps.kernelExecTimeoutEnabled<<"\n";
cout<<"integrated: "<<devProps.integrated<<"\n";
cout<<"canMapHostMemory: "<<devProps.canMapHostMemory<<"\n";
cout<<"computeMode: "<<devProps.computeMode<<"\n";
cout<<"maxTexture1D: "<<devProps.maxTexture1D<<"\n";
cout<<"maxTexture1DMipmap: "<<devProps.maxTexture1DMipmap<<"\n";
cout<<"maxTexture1DLinear: "<<devProps.maxTexture1DLinear<<"\n";
cout<<"maxTexture2D: "<<devProps.maxTexture2D<<"\n";
cout<<"maxTexture2DMipmap: "<<devProps.maxTexture2DMipmap<<"\n";
cout<<"maxTexture2DLinear: "<<devProps.maxTexture2DLinear<<"\n";
cout<<"maxTexture2DGather: "<<devProps.maxTexture2DGather<<"\n";
cout<<"maxTexture3D: "<<devProps.maxTexture3D<<"\n";
cout<<"maxTexture3DAlt: "<<devProps.maxTexture3DAlt<<"\n";
cout<<"maxTextureCubemap: "<<devProps.maxTextureCubemap<<"\n";
cout<<"maxTexture1DLayered: "<<devProps.maxTexture1DLayered<<"\n";
cout<<"maxTexture2DLayered: "<<devProps.maxTexture2DLayered<<"\n";
cout<<"maxTextureCubemapLayered: "<<devProps.maxTextureCubemapLayered<<"\n";
cout<<"maxSurface1D: "<<devProps.maxSurface1D<<"\n";
cout<<"maxSurface2D: "<<devProps.maxSurface2D<<"\n";
cout<<"maxSurface3D: "<<devProps.maxSurface3D<<"\n";
cout<<"maxSurface1DLayered: "<<devProps.maxSurface1DLayered<<"\n";
cout<<"maxSurface2DLayered: "<<devProps.maxSurface2DLayered<<"\n";
cout<<"maxSurfaceCubemap: "<<devProps.maxSurfaceCubemap<<"\n";
cout<<"maxSurfaceCubemapLayered: "<<devProps.maxSurfaceCubemapLayered<<"\n";
cout<<"surfaceAlignment: "<<devProps.surfaceAlignment<<"\n";
cout<<"concurrentKernels: "<<devProps.concurrentKernels<<"\n";
cout<<"ECCEnabled: "<<devProps.ECCEnabled<<"\n";
cout<<"pciBusID: "<<devProps.pciBusID<<"\n";
cout<<"pciDeviceID: "<<devProps.pciDeviceID<<"\n";
cout<<"pciDomainID: "<<devProps.pciDomainID<<"\n";
cout<<"tccDriver: "<<devProps.tccDriver<<"\n";
cout<<"asyncEngineCount: "<<devProps.asyncEngineCount<<"\n";
cout<<"unifiedAddressing: "<<devProps.unifiedAddressing<<"\n";
cout<<"memoryClockRate: "<<devProps.memoryClockRate<<"\n";
cout<<"memoryBusWidth: "<<devProps.memoryBusWidth<<"\n";
cout<<"l2CacheSize: "<<devProps.l2CacheSize<<"\n";
cout<<"maxThreadsPerMultiProcessor: "<<devProps.maxThreadsPerMultiProcessor<<"\n";
cout<<"streamPrioritiesSupported: "<<devProps.streamPrioritiesSupported<<"\n";
cout<<"globalL1CacheSupported: "<<devProps.globalL1CacheSupported<<"\n";
cout<<"localL1CacheSupported: "<<devProps.localL1CacheSupported<<"\n";
cout<<"sharedMemPerMultiprocessor: "<<devProps.sharedMemPerMultiprocessor<<"\n";
cout<<"regsPerMultiprocessor: "<<devProps.regsPerMultiprocessor<<"\n";
cout<<"isMultiGpuBoard: "<<devProps.isMultiGpuBoard<<"\n";
cout<<"multiGpuBoardGroupID: "<<devProps.multiGpuBoardGroupID<<"\n";
cout<<"singleToDoublePrecisionPerfRatio: "<<devProps.singleToDoublePrecisionPerfRatio<<"\n";
cout<<"pageableMemoryAccess: "<<devProps.pageableMemoryAccess<<"\n";
cout<<"concurrentManagedAccess: "<<devProps.concurrentManagedAccess<<"\n";
} | .text
.file "deviceInfo.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
je .LBB0_2
# %bb.1:
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 320(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 324(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 328(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $49, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 312(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $49, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $64, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 340(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 344(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 348(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 352(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 356(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 360(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 364(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.22, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 368(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 384(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 376(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 380(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.26, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 380(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.27, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 392(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.28, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 400(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.29, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 404(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.30, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 408(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.31, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 412(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.32, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 416(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.33, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 420(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.34, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 424(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.35, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 428(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.36, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 432(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.37, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 436(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.38, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 444(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.39, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 452(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.40, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 464(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.41, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 472(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.42, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 484(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.43, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 496(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.44, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 500(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.45, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 508(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.46, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 520(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.47, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 528(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.48, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 532(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.49, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 540(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.50, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 552(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.51, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 560(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.52, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 572(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.53, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 576(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIPKvEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.54, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 584(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.55, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 592(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.56, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 596(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.57, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 600(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.58, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 604(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.59, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 608(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.60, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 612(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.61, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 616(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.62, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 620(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.63, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 624(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.64, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 628(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.65, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 632(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.66, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 640(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.67, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 644(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.68, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 648(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.69, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 652(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.70, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 656(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.71, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 664(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.72, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 672(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.73, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 676(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.74, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 684(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.75, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 688(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.76, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 692(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 1504
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "deviceCount: "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str.2, 36
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "name: "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "totalGlobalMem: "
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "regsPerBlock: "
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "warpSize: "
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "memPitch: "
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\344\270\255\345\217\257\344\275\277\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\n"
.size .L.str.9, 50
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "devProps.sharedMemPerBlock: "
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\344\270\255\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\n"
.size .L.str.11, 50
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "maxThreadsPerBlock: "
.size .L.str.12, 21
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\345\244\232\347\273\264\347\272\277\347\250\213\345\235\227\346\225\260\347\273\204\344\270\255\346\257\217\344\270\200\347\273\264\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\n"
.size .L.str.13, 65
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "maxThreadsDim[0]: "
.size .L.str.14, 19
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "maxThreadsDim[1]: "
.size .L.str.15, 19
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "maxThreadsDim[2]: "
.size .L.str.16, 19
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "\344\270\200\344\270\252\347\272\277\347\250\213\346\240\274\344\270\255\346\257\217\344\270\200\347\273\264\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\345\235\227\346\225\260\351\207\217\n"
.size .L.str.17, 62
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "maxGridSize[0]: "
.size .L.str.18, 17
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "maxGridSize[1]: "
.size .L.str.19, 17
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "maxGridSize[2]: "
.size .L.str.20, 17
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "clockRate: "
.size .L.str.21, 12
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "totalConstMem: "
.size .L.str.22, 16
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "textureAlignment: "
.size .L.str.23, 19
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "\350\256\241\347\256\227\350\203\275\345\212\233\357\274\232"
.size .L.str.24, 16
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "."
.size .L.str.25, 2
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "minor: "
.size .L.str.26, 8
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "texturePitchAlignment: "
.size .L.str.27, 24
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "deviceOverlap: "
.size .L.str.28, 16
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "multiProcessorCount: "
.size .L.str.29, 22
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "kernelExecTimeoutEnabled: "
.size .L.str.30, 27
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "integrated: "
.size .L.str.31, 13
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "canMapHostMemory: "
.size .L.str.32, 19
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "computeMode: "
.size .L.str.33, 14
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz "maxTexture1D: "
.size .L.str.34, 15
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz "maxTexture1DMipmap: "
.size .L.str.35, 21
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz "maxTexture1DLinear: "
.size .L.str.36, 21
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz "maxTexture2D: "
.size .L.str.37, 15
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz "maxTexture2DMipmap: "
.size .L.str.38, 21
.type .L.str.39,@object # @.str.39
.L.str.39:
.asciz "maxTexture2DLinear: "
.size .L.str.39, 21
.type .L.str.40,@object # @.str.40
.L.str.40:
.asciz "maxTexture2DGather: "
.size .L.str.40, 21
.type .L.str.41,@object # @.str.41
.L.str.41:
.asciz "maxTexture3D: "
.size .L.str.41, 15
.type .L.str.42,@object # @.str.42
.L.str.42:
.asciz "maxTexture3DAlt: "
.size .L.str.42, 18
.type .L.str.43,@object # @.str.43
.L.str.43:
.asciz "maxTextureCubemap: "
.size .L.str.43, 20
.type .L.str.44,@object # @.str.44
.L.str.44:
.asciz "maxTexture1DLayered: "
.size .L.str.44, 22
.type .L.str.45,@object # @.str.45
.L.str.45:
.asciz "maxTexture2DLayered: "
.size .L.str.45, 22
.type .L.str.46,@object # @.str.46
.L.str.46:
.asciz "maxTextureCubemapLayered: "
.size .L.str.46, 27
.type .L.str.47,@object # @.str.47
.L.str.47:
.asciz "maxSurface1D: "
.size .L.str.47, 15
.type .L.str.48,@object # @.str.48
.L.str.48:
.asciz "maxSurface2D: "
.size .L.str.48, 15
.type .L.str.49,@object # @.str.49
.L.str.49:
.asciz "maxSurface3D: "
.size .L.str.49, 15
.type .L.str.50,@object # @.str.50
.L.str.50:
.asciz "maxSurface1DLayered: "
.size .L.str.50, 22
.type .L.str.51,@object # @.str.51
.L.str.51:
.asciz "maxSurface2DLayered: "
.size .L.str.51, 22
.type .L.str.52,@object # @.str.52
.L.str.52:
.asciz "maxSurfaceCubemap: "
.size .L.str.52, 20
.type .L.str.53,@object # @.str.53
.L.str.53:
.asciz "maxSurfaceCubemapLayered: "
.size .L.str.53, 27
.type .L.str.54,@object # @.str.54
.L.str.54:
.asciz "surfaceAlignment: "
.size .L.str.54, 19
.type .L.str.55,@object # @.str.55
.L.str.55:
.asciz "concurrentKernels: "
.size .L.str.55, 20
.type .L.str.56,@object # @.str.56
.L.str.56:
.asciz "ECCEnabled: "
.size .L.str.56, 13
.type .L.str.57,@object # @.str.57
.L.str.57:
.asciz "pciBusID: "
.size .L.str.57, 11
.type .L.str.58,@object # @.str.58
.L.str.58:
.asciz "pciDeviceID: "
.size .L.str.58, 14
.type .L.str.59,@object # @.str.59
.L.str.59:
.asciz "pciDomainID: "
.size .L.str.59, 14
.type .L.str.60,@object # @.str.60
.L.str.60:
.asciz "tccDriver: "
.size .L.str.60, 12
.type .L.str.61,@object # @.str.61
.L.str.61:
.asciz "asyncEngineCount: "
.size .L.str.61, 19
.type .L.str.62,@object # @.str.62
.L.str.62:
.asciz "unifiedAddressing: "
.size .L.str.62, 20
.type .L.str.63,@object # @.str.63
.L.str.63:
.asciz "memoryClockRate: "
.size .L.str.63, 18
.type .L.str.64,@object # @.str.64
.L.str.64:
.asciz "memoryBusWidth: "
.size .L.str.64, 17
.type .L.str.65,@object # @.str.65
.L.str.65:
.asciz "l2CacheSize: "
.size .L.str.65, 14
.type .L.str.66,@object # @.str.66
.L.str.66:
.asciz "maxThreadsPerMultiProcessor: "
.size .L.str.66, 30
.type .L.str.67,@object # @.str.67
.L.str.67:
.asciz "streamPrioritiesSupported: "
.size .L.str.67, 28
.type .L.str.68,@object # @.str.68
.L.str.68:
.asciz "globalL1CacheSupported: "
.size .L.str.68, 25
.type .L.str.69,@object # @.str.69
.L.str.69:
.asciz "localL1CacheSupported: "
.size .L.str.69, 24
.type .L.str.70,@object # @.str.70
.L.str.70:
.asciz "sharedMemPerMultiprocessor: "
.size .L.str.70, 29
.type .L.str.71,@object # @.str.71
.L.str.71:
.asciz "regsPerMultiprocessor: "
.size .L.str.71, 24
.type .L.str.72,@object # @.str.72
.L.str.72:
.asciz "isMultiGpuBoard: "
.size .L.str.72, 18
.type .L.str.73,@object # @.str.73
.L.str.73:
.asciz "multiGpuBoardGroupID: "
.size .L.str.73, 23
.type .L.str.74,@object # @.str.74
.L.str.74:
.asciz "singleToDoublePrecisionPerfRatio: "
.size .L.str.74, 35
.type .L.str.75,@object # @.str.75
.L.str.75:
.asciz "pageableMemoryAccess: "
.size .L.str.75, 23
.type .L.str.76,@object # @.str.76
.L.str.76:
.asciz "concurrentManagedAccess: "
.size .L.str.76, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 128
#define B 2
__global__ void k(int* in)
{
in[threadIdx.x] = blockIdx.x;
}
int main()
{
int* in = (int*) malloc(N * sizeof(int));
int* din;
cudaMalloc((void**) &din, N*sizeof(int));
k<<<B,N/B>>>(din);
} | code for sm_80
Function : _Z1kPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e6e0000002500 */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 128
#define B 2
__global__ void k(int* in)
{
in[threadIdx.x] = blockIdx.x;
}
int main()
{
int* in = (int*) malloc(N * sizeof(int));
int* din;
cudaMalloc((void**) &din, N*sizeof(int));
k<<<B,N/B>>>(din);
} | .file "tmpxft_001626e2_00000000-6_inter_block_race.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1kPiPi
.type _Z20__device_stub__Z1kPiPi, @function
_Z20__device_stub__Z1kPiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1kPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z20__device_stub__Z1kPiPi, .-_Z20__device_stub__Z1kPiPi
.globl _Z1kPi
.type _Z1kPi, @function
_Z1kPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1kPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z1kPi, .-_Z1kPi
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z20__device_stub__Z1kPiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1kPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1kPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 128
#define B 2
__global__ void k(int* in)
{
in[threadIdx.x] = blockIdx.x;
}
int main()
{
int* in = (int*) malloc(N * sizeof(int));
int* din;
cudaMalloc((void**) &din, N*sizeof(int));
k<<<B,N/B>>>(din);
} | #include <hip/hip_runtime.h>
#define N 128
#define B 2
__global__ void k(int* in)
{
in[threadIdx.x] = blockIdx.x;
}
int main()
{
int* in = (int*) malloc(N * sizeof(int));
int* din;
hipMalloc((void**) &din, N*sizeof(int));
k<<<B,N/B>>>(din);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define N 128
#define B 2
__global__ void k(int* in)
{
in[threadIdx.x] = blockIdx.x;
}
int main()
{
int* in = (int*) malloc(N * sizeof(int));
int* din;
hipMalloc((void**) &din, N*sizeof(int));
k<<<B,N/B>>>(din);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1kPi
.globl _Z1kPi
.p2align 8
.type _Z1kPi,@function
_Z1kPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, s15 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1kPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1kPi, .Lfunc_end0-_Z1kPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1kPi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z1kPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define N 128
#define B 2
__global__ void k(int* in)
{
in[threadIdx.x] = blockIdx.x;
}
int main()
{
int* in = (int*) malloc(N * sizeof(int));
int* din;
hipMalloc((void**) &din, N*sizeof(int));
k<<<B,N/B>>>(din);
} | .text
.file "inter_block_race.hip"
.globl _Z16__device_stub__kPi # -- Begin function _Z16__device_stub__kPi
.p2align 4, 0x90
.type _Z16__device_stub__kPi,@function
_Z16__device_stub__kPi: # @_Z16__device_stub__kPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1kPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__kPi, .Lfunc_end0-_Z16__device_stub__kPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1kPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1kPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1kPi,@object # @_Z1kPi
.section .rodata,"a",@progbits
.globl _Z1kPi
.p2align 3, 0x0
_Z1kPi:
.quad _Z16__device_stub__kPi
.size _Z1kPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1kPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__kPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1kPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1kPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e6e0000002500 */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1kPi
.globl _Z1kPi
.p2align 8
.type _Z1kPi,@function
_Z1kPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, s15 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1kPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1kPi, .Lfunc_end0-_Z1kPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1kPi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z1kPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001626e2_00000000-6_inter_block_race.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1kPiPi
.type _Z20__device_stub__Z1kPiPi, @function
_Z20__device_stub__Z1kPiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1kPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z20__device_stub__Z1kPiPi, .-_Z20__device_stub__Z1kPiPi
.globl _Z1kPi
.type _Z1kPi, @function
_Z1kPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1kPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z1kPi, .-_Z1kPi
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z20__device_stub__Z1kPiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1kPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1kPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "inter_block_race.hip"
.globl _Z16__device_stub__kPi # -- Begin function _Z16__device_stub__kPi
.p2align 4, 0x90
.type _Z16__device_stub__kPi,@function
_Z16__device_stub__kPi: # @_Z16__device_stub__kPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1kPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__kPi, .Lfunc_end0-_Z16__device_stub__kPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1kPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1kPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1kPi,@object # @_Z1kPi
.section .rodata,"a",@progbits
.globl _Z1kPi
.p2align 3, 0x0
_Z1kPi:
.quad _Z16__device_stub__kPi
.size _Z1kPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1kPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__kPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1kPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float dothings(int t,int sz, float *input){
float ans = 0;
for(int i=0;i<12;++i){
ans += input[(i+t)%sz];
}
return ans;
}
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float local_data[VEC_SIZE];
float ans = 0.;
for(int i=0;i<VEC_SIZE;++i) local_data[i] = input[VEC_SIZE * g_id + i];
for(int t=0;t<N_step;++t){
ans += dothings(t, VEC_SIZE, local_data);
}
output[g_id] = ans;
return;
} | code for sm_80
Function : _Z7processiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R20, SR_CTAID.X ; /* 0x0000000000147919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0xc000, RZ ; /* 0xffff400001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R20, R20, c[0x0][0x0], R3 ; /* 0x0000000014147a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R20, c[0x0][0x164], PT ; /* 0x0000590014007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD R5, R20, 0x3000, RZ ; /* 0x0000300014057824 */
/* 0x000fe200078e02ff */
/*00a0*/ MOV R0, R1 ; /* 0x0000000100007202 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR28, c[0x0][0x118] ; /* 0x00004600001c7ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ IMAD.WIDE R4, R5, R2, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0202 */
/*00d0*/ IADD3 R21, P0, R4, 0x20, RZ ; /* 0x0000002004157810 */
/* 0x000fca0007f1e0ff */
/*00e0*/ IMAD.X R24, RZ, RZ, R5, P0 ; /* 0x000000ffff187224 */
/* 0x000fc800000e0605 */
/*00f0*/ IMAD.MOV.U32 R22, RZ, RZ, R21 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0015 */
/*0100*/ MOV R23, R24 ; /* 0x0000001800177202 */
/* 0x000fca0000000f00 */
/*0110*/ LDG.E R7, [R22.64+-0x14] ; /* 0xffffec1c16077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R6, [R22.64+-0x18] ; /* 0xffffe81c16067981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R5, [R22.64+-0x1c] ; /* 0xffffe41c16057981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R4, [R22.64+-0x20] ; /* 0xffffe01c16047981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R11, [R22.64+-0x4] ; /* 0xfffffc1c160b7981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R10, [R22.64+-0x8] ; /* 0xfffff81c160a7981 */
/* 0x000ee8000c1e1900 */
/*0170*/ LDG.E R9, [R22.64+-0xc] ; /* 0xfffff41c16097981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R8, [R22.64+-0x10] ; /* 0xfffff01c16087981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R15, [R22.64+0xc] ; /* 0x00000c1c160f7981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R14, [R22.64+0x8] ; /* 0x0000081c160e7981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R13, [R22.64+0x4] ; /* 0x0000041c160d7981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R12, [R22.64] ; /* 0x0000001c160c7981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R19, [R22.64+0x1c] ; /* 0x00001c1c16137981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R18, [R22.64+0x18] ; /* 0x0000181c16127981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R17, [R22.64+0x14] ; /* 0x0000141c16117981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R16, [R22.64+0x10] ; /* 0x0000101c16107981 */
/* 0x000f68000c1e1900 */
/*0210*/ STL.128 [R0], R4 ; /* 0x0000000400007387 */
/* 0x0041e80000100c00 */
/*0220*/ STL.128 [R0+0x10], R8 ; /* 0x0000100800007387 */
/* 0x0083e80000100c00 */
/*0230*/ LDG.E R7, [R22.64+0x2c] ; /* 0x00002c1c16077981 */
/* 0x001ea8000c1e1900 */
/*0240*/ LDG.E R6, [R22.64+0x28] ; /* 0x0000281c16067981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R5, [R22.64+0x24] ; /* 0x0000241c16057981 */
/* 0x000ea8000c1e1900 */
/*0260*/ STL.128 [R0+0x20], R12 ; /* 0x0000200c00007387 */
/* 0x0101e80000100c00 */
/*0270*/ LDG.E R4, [R22.64+0x20] ; /* 0x0000201c16047981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R11, [R22.64+0x3c] ; /* 0x00003c1c160b7981 */
/* 0x002ee8000c1e1900 */
/*0290*/ LDG.E R10, [R22.64+0x38] ; /* 0x0000381c160a7981 */
/* 0x000ee8000c1e1900 */
/*02a0*/ STL.128 [R0+0x30], R16 ; /* 0x0000301000007387 */
/* 0x0203e80000100c00 */
/*02b0*/ LDG.E R9, [R22.64+0x34] ; /* 0x0000341c16097981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R8, [R22.64+0x30] ; /* 0x0000301c16087981 */
/* 0x000ee8000c1e1900 */
/*02d0*/ LDG.E R15, [R22.64+0x4c] ; /* 0x00004c1c160f7981 */
/* 0x001f28000c1e1900 */
/*02e0*/ LDG.E R14, [R22.64+0x48] ; /* 0x0000481c160e7981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R13, [R22.64+0x44] ; /* 0x0000441c160d7981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R12, [R22.64+0x40] ; /* 0x0000401c160c7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R22.64+0x5c] ; /* 0x00005c1c16137981 */
/* 0x002f68000c1e1900 */
/*0320*/ LDG.E R18, [R22.64+0x58] ; /* 0x0000581c16127981 */
/* 0x000f68000c1e1900 */
/*0330*/ LDG.E R17, [R22.64+0x54] ; /* 0x0000541c16117981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R16, [R22.64+0x50] ; /* 0x0000501c16107981 */
/* 0x000f68000c1e1900 */
/*0350*/ STL.128 [R0+0x40], R4 ; /* 0x0000400400007387 */
/* 0x0041e80000100c00 */
/*0360*/ LDG.E R7, [R22.64+0x6c] ; /* 0x00006c1c16077981 */
/* 0x001ea8000c1e1900 */
/*0370*/ STL.128 [R0+0x50], R8 ; /* 0x0000500800007387 */
/* 0x0081e80000100c00 */
/*0380*/ LDG.E R6, [R22.64+0x68] ; /* 0x0000681c16067981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R5, [R22.64+0x64] ; /* 0x0000641c16057981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R4, [R22.64+0x60] ; /* 0x0000601c16047981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ STL.128 [R0+0x60], R12 ; /* 0x0000600c00007387 */
/* 0x0103e80000100c00 */
/*03c0*/ LDG.E R11, [R22.64+0x7c] ; /* 0x00007c1c160b7981 */
/* 0x001ee8000c1e1900 */
/*03d0*/ LDG.E R10, [R22.64+0x78] ; /* 0x0000781c160a7981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R9, [R22.64+0x74] ; /* 0x0000741c16097981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ STL.128 [R0+0x70], R16 ; /* 0x0000701000007387 */
/* 0x0201e80000100c00 */
/*0400*/ LDG.E R8, [R22.64+0x70] ; /* 0x0000701c16087981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R15, [R22.64+0x8c] ; /* 0x00008c1c160f7981 */
/* 0x002f28000c1e1900 */
/*0420*/ LDG.E R14, [R22.64+0x88] ; /* 0x0000881c160e7981 */
/* 0x000f28000c1e1900 */
/*0430*/ LDG.E R13, [R22.64+0x84] ; /* 0x0000841c160d7981 */
/* 0x000f28000c1e1900 */
/*0440*/ LDG.E R12, [R22.64+0x80] ; /* 0x0000801c160c7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R19, [R22.64+0x9c] ; /* 0x00009c1c16137981 */
/* 0x001f68000c1e1900 */
/*0460*/ LDG.E R18, [R22.64+0x98] ; /* 0x0000981c16127981 */
/* 0x000f68000c1e1900 */
/*0470*/ LDG.E R17, [R22.64+0x94] ; /* 0x0000941c16117981 */
/* 0x000f68000c1e1900 */
/*0480*/ LDG.E R16, [R22.64+0x90] ; /* 0x0000901c16107981 */
/* 0x000f68000c1e1900 */
/*0490*/ STL.128 [R0+0x80], R4 ; /* 0x0000800400007387 */
/* 0x0041e80000100c00 */
/*04a0*/ LDG.E R7, [R22.64+0xac] ; /* 0x0000ac1c16077981 */
/* 0x001ea8000c1e1900 */
/*04b0*/ LDG.E R6, [R22.64+0xa8] ; /* 0x0000a81c16067981 */
/* 0x000ea8000c1e1900 */
/*04c0*/ STL.128 [R0+0x90], R8 ; /* 0x0000900800007387 */
/* 0x0081e80000100c00 */
/*04d0*/ LDG.E R5, [R22.64+0xa4] ; /* 0x0000a41c16057981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R4, [R22.64+0xa0] ; /* 0x0000a01c16047981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ STL.128 [R0+0xa0], R12 ; /* 0x0000a00c00007387 */
/* 0x0103e80000100c00 */
/*0500*/ LDG.E R11, [R22.64+0xbc] ; /* 0x0000bc1c160b7981 */
/* 0x001ee8000c1e1900 */
/*0510*/ LDG.E R10, [R22.64+0xb8] ; /* 0x0000b81c160a7981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R9, [R22.64+0xb4] ; /* 0x0000b41c16097981 */
/* 0x000ee8000c1e1900 */
/*0530*/ STL.128 [R0+0xb0], R16 ; /* 0x0000b01000007387 */
/* 0x0201e80000100c00 */
/*0540*/ LDG.E R8, [R22.64+0xb0] ; /* 0x0000b01c16087981 */
/* 0x000ee8000c1e1900 */
/*0550*/ LDG.E R15, [R22.64+0xcc] ; /* 0x0000cc1c160f7981 */
/* 0x002f28000c1e1900 */
/*0560*/ LDG.E R14, [R22.64+0xc8] ; /* 0x0000c81c160e7981 */
/* 0x000f28000c1e1900 */
/*0570*/ LDG.E R13, [R22.64+0xc4] ; /* 0x0000c41c160d7981 */
/* 0x000f28000c1e1900 */
/*0580*/ LDG.E R12, [R22.64+0xc0] ; /* 0x0000c01c160c7981 */
/* 0x000f28000c1e1900 */
/*0590*/ LDG.E R19, [R22.64+0xdc] ; /* 0x0000dc1c16137981 */
/* 0x001f68000c1e1900 */
/*05a0*/ LDG.E R18, [R22.64+0xd8] ; /* 0x0000d81c16127981 */
/* 0x000f68000c1e1900 */
/*05b0*/ LDG.E R17, [R22.64+0xd4] ; /* 0x0000d41c16117981 */
/* 0x000f68000c1e1900 */
/*05c0*/ LDG.E R16, [R22.64+0xd0] ; /* 0x0000d01c16107981 */
/* 0x000f68000c1e1900 */
/*05d0*/ STL.128 [R0+0xc0], R4 ; /* 0x0000c00400007387 */
/* 0x0041e80000100c00 */
/*05e0*/ LDG.E R7, [R22.64+0xec] ; /* 0x0000ec1c16077981 */
/* 0x001ea8000c1e1900 */
/*05f0*/ LDG.E R6, [R22.64+0xe8] ; /* 0x0000e81c16067981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R5, [R22.64+0xe4] ; /* 0x0000e41c16057981 */
/* 0x000ea8000c1e1900 */
/*0610*/ STL.128 [R0+0xd0], R8 ; /* 0x0000d00800007387 */
/* 0x0081e80000100c00 */
/*0620*/ LDG.E R4, [R22.64+0xe0] ; /* 0x0000e01c16047981 */
/* 0x000ea8000c1e1900 */
/*0630*/ STL.128 [R0+0xe0], R12 ; /* 0x0000e00c00007387 */
/* 0x0103e80000100c00 */
/*0640*/ LDG.E R11, [R22.64+0xfc] ; /* 0x0000fc1c160b7981 */
/* 0x001ee8000c1e1900 */
/*0650*/ LDG.E R10, [R22.64+0xf8] ; /* 0x0000f81c160a7981 */
/* 0x000ee8000c1e1900 */
/*0660*/ LDG.E R9, [R22.64+0xf4] ; /* 0x0000f41c16097981 */
/* 0x000ee8000c1e1900 */
/*0670*/ STL.128 [R0+0xf0], R16 ; /* 0x0000f01000007387 */
/* 0x0201e80000100c00 */
/*0680*/ LDG.E R8, [R22.64+0xf0] ; /* 0x0000f01c16087981 */
/* 0x000ee8000c1e1900 */
/*0690*/ LDG.E R15, [R22.64+0x10c] ; /* 0x00010c1c160f7981 */
/* 0x002f28000c1e1900 */
/*06a0*/ LDG.E R14, [R22.64+0x108] ; /* 0x0001081c160e7981 */
/* 0x000f28000c1e1900 */
/*06b0*/ LDG.E R13, [R22.64+0x104] ; /* 0x0001041c160d7981 */
/* 0x000f28000c1e1900 */
/*06c0*/ LDG.E R12, [R22.64+0x100] ; /* 0x0001001c160c7981 */
/* 0x000f28000c1e1900 */
/*06d0*/ LDG.E R19, [R22.64+0x11c] ; /* 0x00011c1c16137981 */
/* 0x001f68000c1e1900 */
/*06e0*/ LDG.E R18, [R22.64+0x118] ; /* 0x0001181c16127981 */
/* 0x000f68000c1e1900 */
/*06f0*/ LDG.E R17, [R22.64+0x114] ; /* 0x0001141c16117981 */
/* 0x000f68000c1e1900 */
/*0700*/ LDG.E R16, [R22.64+0x110] ; /* 0x0001101c16107981 */
/* 0x000f68000c1e1900 */
/*0710*/ STL.128 [R0+0x100], R4 ; /* 0x0001000400007387 */
/* 0x0041e80000100c00 */
/*0720*/ LDG.E R7, [R22.64+0x12c] ; /* 0x00012c1c16077981 */
/* 0x001ea8000c1e1900 */
/*0730*/ LDG.E R6, [R22.64+0x128] ; /* 0x0001281c16067981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R5, [R22.64+0x124] ; /* 0x0001241c16057981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R4, [R22.64+0x120] ; /* 0x0001201c16047981 */
/* 0x000ea8000c1e1900 */
/*0760*/ STL.128 [R0+0x110], R8 ; /* 0x0001100800007387 */
/* 0x0081e80000100c00 */
/*0770*/ STL.128 [R0+0x120], R12 ; /* 0x0001200c00007387 */
/* 0x0103e80000100c00 */
/*0780*/ LDG.E R11, [R22.64+0x13c] ; /* 0x00013c1c160b7981 */
/* 0x001ee8000c1e1900 */
/*0790*/ LDG.E R10, [R22.64+0x138] ; /* 0x0001381c160a7981 */
/* 0x000ee8000c1e1900 */
/*07a0*/ LDG.E R9, [R22.64+0x134] ; /* 0x0001341c16097981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ STL.128 [R0+0x130], R16 ; /* 0x0001301000007387 */
/* 0x0201e80000100c00 */
/*07c0*/ LDG.E R8, [R22.64+0x130] ; /* 0x0001301c16087981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R15, [R22.64+0x14c] ; /* 0x00014c1c160f7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R14, [R22.64+0x148] ; /* 0x0001481c160e7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R13, [R22.64+0x144] ; /* 0x0001441c160d7981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R12, [R22.64+0x140] ; /* 0x0001401c160c7981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R19, [R22.64+0x15c] ; /* 0x00015c1c16137981 */
/* 0x001f68000c1e1900 */
/*0820*/ LDG.E R18, [R22.64+0x158] ; /* 0x0001581c16127981 */
/* 0x000f68000c1e1900 */
/*0830*/ LDG.E R17, [R22.64+0x154] ; /* 0x0001541c16117981 */
/* 0x000f68000c1e1900 */
/*0840*/ LDG.E R16, [R22.64+0x150] ; /* 0x0001501c16107981 */
/* 0x000f68000c1e1900 */
/*0850*/ STL.128 [R0+0x140], R4 ; /* 0x0001400400007387 */
/* 0x0041e80000100c00 */
/*0860*/ LDG.E R7, [R22.64+0x16c] ; /* 0x00016c1c16077981 */
/* 0x001ea8000c1e1900 */
/*0870*/ LDG.E R6, [R22.64+0x168] ; /* 0x0001681c16067981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R5, [R22.64+0x164] ; /* 0x0001641c16057981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R4, [R22.64+0x160] ; /* 0x0001601c16047981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ STL.128 [R0+0x150], R8 ; /* 0x0001500800007387 */
/* 0x0081e80000100c00 */
/*08b0*/ STL.128 [R0+0x160], R12 ; /* 0x0001600c00007387 */
/* 0x0103e80000100c00 */
/*08c0*/ LDG.E R11, [R22.64+0x17c] ; /* 0x00017c1c160b7981 */
/* 0x001ee8000c1e1900 */
/*08d0*/ LDG.E R10, [R22.64+0x178] ; /* 0x0001781c160a7981 */
/* 0x000ee8000c1e1900 */
/*08e0*/ LDG.E R9, [R22.64+0x174] ; /* 0x0001741c16097981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ STL.128 [R0+0x170], R16 ; /* 0x0001701000007387 */
/* 0x0201e80000100c00 */
/*0900*/ LDG.E R8, [R22.64+0x170] ; /* 0x0001701c16087981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R15, [R22.64+0x18c] ; /* 0x00018c1c160f7981 */
/* 0x002f28000c1e1900 */
/*0920*/ LDG.E R14, [R22.64+0x188] ; /* 0x0001881c160e7981 */
/* 0x000f28000c1e1900 */
/*0930*/ LDG.E R13, [R22.64+0x184] ; /* 0x0001841c160d7981 */
/* 0x000f28000c1e1900 */
/*0940*/ LDG.E R12, [R22.64+0x180] ; /* 0x0001801c160c7981 */
/* 0x000f28000c1e1900 */
/*0950*/ LDG.E R19, [R22.64+0x19c] ; /* 0x00019c1c16137981 */
/* 0x001f68000c1e1900 */
/*0960*/ LDG.E R18, [R22.64+0x198] ; /* 0x0001981c16127981 */
/* 0x000f68000c1e1900 */
/*0970*/ LDG.E R17, [R22.64+0x194] ; /* 0x0001941c16117981 */
/* 0x000f68000c1e1900 */
/*0980*/ LDG.E R16, [R22.64+0x190] ; /* 0x0001901c16107981 */
/* 0x000f68000c1e1900 */
/*0990*/ STL.128 [R0+0x180], R4 ; /* 0x0001800400007387 */
/* 0x0041e80000100c00 */
/*09a0*/ LDG.E R7, [R22.64+0x1ac] ; /* 0x0001ac1c16077981 */
/* 0x001ea8000c1e1900 */
/*09b0*/ LDG.E R6, [R22.64+0x1a8] ; /* 0x0001a81c16067981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R5, [R22.64+0x1a4] ; /* 0x0001a41c16057981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R4, [R22.64+0x1a0] ; /* 0x0001a01c16047981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ STL.128 [R0+0x190], R8 ; /* 0x0001900800007387 */
/* 0x0081e80000100c00 */
/*09f0*/ STL.128 [R0+0x1a0], R12 ; /* 0x0001a00c00007387 */
/* 0x0103e80000100c00 */
/*0a00*/ LDG.E R11, [R22.64+0x1bc] ; /* 0x0001bc1c160b7981 */
/* 0x001ee8000c1e1900 */
/*0a10*/ LDG.E R10, [R22.64+0x1b8] ; /* 0x0001b81c160a7981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R9, [R22.64+0x1b4] ; /* 0x0001b41c16097981 */
/* 0x000ee8000c1e1900 */
/*0a30*/ STL.128 [R0+0x1b0], R16 ; /* 0x0001b01000007387 */
/* 0x0201e80000100c00 */
/*0a40*/ LDG.E R8, [R22.64+0x1b0] ; /* 0x0001b01c16087981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R15, [R22.64+0x1cc] ; /* 0x0001cc1c160f7981 */
/* 0x002f28000c1e1900 */
/*0a60*/ LDG.E R14, [R22.64+0x1c8] ; /* 0x0001c81c160e7981 */
/* 0x000f28000c1e1900 */
/*0a70*/ LDG.E R13, [R22.64+0x1c4] ; /* 0x0001c41c160d7981 */
/* 0x000f28000c1e1900 */
/*0a80*/ LDG.E R12, [R22.64+0x1c0] ; /* 0x0001c01c160c7981 */
/* 0x000f28000c1e1900 */
/*0a90*/ LDG.E R19, [R22.64+0x1dc] ; /* 0x0001dc1c16137981 */
/* 0x001f68000c1e1900 */
/*0aa0*/ LDG.E R18, [R22.64+0x1d8] ; /* 0x0001d81c16127981 */
/* 0x000f68000c1e1900 */
/*0ab0*/ LDG.E R17, [R22.64+0x1d4] ; /* 0x0001d41c16117981 */
/* 0x000f68000c1e1900 */
/*0ac0*/ LDG.E R16, [R22.64+0x1d0] ; /* 0x0001d01c16107981 */
/* 0x000f62000c1e1900 */
/*0ad0*/ IADD3 R3, R3, 0x80, RZ ; /* 0x0000008003037810 */
/* 0x000fc80007ffe0ff */
/*0ae0*/ ISETP.NE.AND P0, PT, R3, 0x3000, PT ; /* 0x000030000300780c */
/* 0x000fe40003f05270 */
/*0af0*/ IADD3 R21, P1, R22, 0x200, RZ ; /* 0x0000020016157810 */
/* 0x000fca0007f3e0ff */
/*0b00*/ IMAD.X R24, RZ, RZ, R23, P1 ; /* 0x000000ffff187224 */
/* 0x000fe200008e0617 */
/*0b10*/ STL.128 [R0+0x1c0], R4 ; /* 0x0001c00400007387 */
/* 0x004fe80000100c00 */
/*0b20*/ STL.128 [R0+0x1d0], R8 ; /* 0x0001d00800007387 */
/* 0x008fe80000100c00 */
/*0b30*/ STL.128 [R0+0x1e0], R12 ; /* 0x0001e00c00007387 */
/* 0x010fe80000100c00 */
/*0b40*/ STL.128 [R0+0x1f0], R16 ; /* 0x0001f01000007387 */
/* 0x0201e40000100c00 */
/*0b50*/ IADD3 R0, R0, 0x200, RZ ; /* 0x0000020000007810 */
/* 0x001fe20007ffe0ff */
/*0b60*/ @P0 BRA 0xf0 ; /* 0xfffff58000000947 */
/* 0x000fea000383ffff */
/*0b70*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0b80*/ IMAD.WIDE R2, R20, R2, c[0x0][0x170] ; /* 0x00005c0014027625 */
/* 0x000fc600078e0202 */
/*0b90*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0ba0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0bb0*/ @!P0 BRA 0x1300 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0bd0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0be0*/ UMOV UR31, 0x1 ; /* 0x00000001001f7882 */
/* 0x000fe40000000000 */
/*0bf0*/ UMOV UR32, 0x2 ; /* 0x0000000200207882 */
/* 0x000fe40000000000 */
/*0c00*/ UMOV UR33, 0x3 ; /* 0x0000000300217882 */
/* 0x000fe40000000000 */
/*0c10*/ UMOV UR34, 0x4 ; /* 0x0000000400227882 */
/* 0x000fe40000000000 */
/*0c20*/ UMOV UR35, 0x5 ; /* 0x0000000500237882 */
/* 0x000fc40000000000 */
/*0c30*/ UMOV UR36, 0x6 ; /* 0x0000000600247882 */
/* 0x000fe40000000000 */
/*0c40*/ UMOV UR37, 0x7 ; /* 0x0000000700257882 */
/* 0x000fe40000000000 */
/*0c50*/ UMOV UR38, 0x8 ; /* 0x0000000800267882 */
/* 0x000fe40000000000 */
/*0c60*/ UMOV UR39, 0x9 ; /* 0x0000000900277882 */
/* 0x000fe40000000000 */
/*0c70*/ UMOV UR30, 0xa ; /* 0x0000000a001e7882 */
/* 0x000fe40000000000 */
/*0c80*/ UMOV UR40, 0xb ; /* 0x0000000b00287882 */
/* 0x000fc40000000000 */
/*0c90*/ UIMAD.WIDE.U32 UR10, UR31, -0x55555555, URZ ; /* 0xaaaaaaab1f0a78a5 */
/* 0x000fe2000f8e003f */
/*0ca0*/ IMAD.WIDE.U32 R6, R0, -0x55555555, RZ ; /* 0xaaaaaaab00067825 */
/* 0x000fe200078e00ff */
/*0cb0*/ UIMAD.WIDE.U32 UR6, UR32, -0x55555555, URZ ; /* 0xaaaaaaab200678a5 */
/* 0x000fc4000f8e003f */
/*0cc0*/ USHF.R.U32.HI UR6, URZ, 0xd, UR11 ; /* 0x0000000d3f067899 */
/* 0x000fe4000801160b */
/*0cd0*/ SHF.R.U32.HI R7, RZ, 0xd, R7 ; /* 0x0000000dff077819 */
/* 0x000fe20000011607 */
/*0ce0*/ UMOV UR41, 0xffffd000 ; /* 0xffffd00000297882 */
/* 0x000fe40000000000 */
/*0cf0*/ UIMAD.WIDE.U32 UR8, UR33, -0x55555555, URZ ; /* 0xaaaaaaab210878a5 */
/* 0x000fe4000f8e003f */
/*0d00*/ UIMAD.WIDE.U32 UR4, UR34, -0x55555555, URZ ; /* 0xaaaaaaab220478a5 */
/* 0x000fe2000f8e003f */
/*0d10*/ IMAD R4, R7, -0x3000, R0 ; /* 0xffffd00007047824 */
/* 0x000fe200078e0200 */
/*0d20*/ UIMAD UR6, UR6, UR41, 0x1 ; /* 0x00000001060674a4 */
/* 0x000fe4000f8e0229 */
/*0d30*/ USHF.R.U32.HI UR7, URZ, 0xd, UR7 ; /* 0x0000000d3f077899 */
/* 0x000fc40008011607 */
/*0d40*/ USHF.R.U32.HI UR8, URZ, 0xd, UR9 ; /* 0x0000000d3f087899 */
/* 0x000fe20008011609 */
/*0d50*/ LEA R4, R4, R1, 0x2 ; /* 0x0000000104047211 */
/* 0x000fe200078e10ff */
/*0d60*/ USHF.R.U32.HI UR9, URZ, 0xd, UR5 ; /* 0x0000000d3f097899 */
/* 0x000fe20008011605 */
/*0d70*/ IADD3 R6, R0, UR6, RZ ; /* 0x0000000600067c10 */
/* 0x000fe2000fffe0ff */
/*0d80*/ UIMAD UR5, UR7, UR41, 0x2 ; /* 0x00000002070574a4 */
/* 0x000fe4000f8e0229 */
/*0d90*/ UIMAD.WIDE.U32 UR12, UR35, -0x55555555, URZ ; /* 0xaaaaaaab230c78a5 */
/* 0x000fe2000f8e003f */
/*0da0*/ LDL R4, [R4] ; /* 0x0000000004047983 */
/* 0x000ea20000100800 */
/*0db0*/ UIMAD UR7, UR8, UR41, 0x3 ; /* 0x00000003080774a4 */
/* 0x000fe2000f8e0229 */
/*0dc0*/ IMAD R6, R6, 0x4, R1 ; /* 0x0000000406067824 */
/* 0x000fe200078e0201 */
/*0dd0*/ IADD3 R8, R0, UR5, RZ ; /* 0x0000000500087c10 */
/* 0x000fe2000fffe0ff */
/*0de0*/ USHF.R.U32.HI UR12, URZ, 0xd, UR13 ; /* 0x0000000d3f0c7899 */
/* 0x000fc4000801160d */
/*0df0*/ UIMAD.WIDE.U32 UR14, UR36, -0x55555555, URZ ; /* 0xaaaaaaab240e78a5 */
/* 0x000fe2000f8e003f */
/*0e00*/ IADD3 R10, R0, UR7, RZ ; /* 0x00000007000a7c10 */
/* 0x000fe2000fffe0ff */
/*0e10*/ UIMAD UR6, UR9, UR41, 0x4 ; /* 0x00000004090674a4 */
/* 0x000fe2000f8e0229 */
/*0e20*/ LEA R7, R8, R1, 0x2 ; /* 0x0000000108077211 */
/* 0x000fe200078e10ff */
/*0e30*/ UIMAD.WIDE.U32 UR18, UR37, -0x55555555, URZ ; /* 0xaaaaaaab251278a5 */
/* 0x000fe2000f8e003f */
/*0e40*/ LDL R6, [R6] ; /* 0x0000000006067983 */
/* 0x000ee20000100800 */
/*0e50*/ UIMAD UR5, UR12, UR41, 0x5 ; /* 0x000000050c0574a4 */
/* 0x000fe4000f8e0229 */
/*0e60*/ USHF.R.U32.HI UR14, URZ, 0xd, UR15 ; /* 0x0000000d3f0e7899 */
/* 0x000fe2000801160f */
/*0e70*/ IADD3 R12, R0, UR6, RZ ; /* 0x00000006000c7c10 */
/* 0x000fe2000fffe0ff */
/*0e80*/ IMAD R8, R10, 0x4, R1 ; /* 0x000000040a087824 */
/* 0x000fe200078e0201 */
/*0e90*/ UIMAD.WIDE.U32 UR24, UR40, -0x55555555, URZ ; /* 0xaaaaaaab281878a5 */
/* 0x000fe2000f8e003f */
/*0ea0*/ LDL R7, [R7] ; /* 0x0000000007077983 */
/* 0x000f220000100800 */
/*0eb0*/ USHF.R.U32.HI UR18, URZ, 0xd, UR19 ; /* 0x0000000d3f127899 */
/* 0x000fe20008011613 */
/*0ec0*/ IADD3 R10, R0, UR5, RZ ; /* 0x00000005000a7c10 */
/* 0x000fe2000fffe0ff */
/*0ed0*/ UIMAD.WIDE.U32 UR20, UR38, -0x55555555, URZ ; /* 0xaaaaaaab261478a5 */
/* 0x000fc4000f8e003f */
/*0ee0*/ UIMAD UR7, UR14, UR41, 0x6 ; /* 0x000000060e0774a4 */
/* 0x000fe2000f8e0229 */
/*0ef0*/ LEA R9, R12, R1.reuse, 0x2 ; /* 0x000000010c097211 */
/* 0x080fe200078e10ff */
/*0f00*/ UIMAD.WIDE.U32 UR22, UR39, -0x55555555, URZ ; /* 0xaaaaaaab271678a5 */
/* 0x000fe2000f8e003f */
/*0f10*/ LDL R8, [R8] ; /* 0x0000000008087983 */
/* 0x000f620000100800 */
/*0f20*/ UIMAD UR6, UR18, UR41, 0x7 ; /* 0x00000007120674a4 */
/* 0x000fe4000f8e0229 */
/*0f30*/ USHF.R.U32.HI UR20, URZ, 0xd, UR21 ; /* 0x0000000d3f147899 */
/* 0x000fe20008011615 */
/*0f40*/ IADD3 R12, R0, UR7, RZ ; /* 0x00000007000c7c10 */
/* 0x000fe2000fffe0ff */
/*0f50*/ UMOV UR24, 0x8 ; /* 0x0000000800187882 */
/* 0x000fe20000000000 */
/*0f60*/ IMAD R10, R10, 0x4, R1.reuse ; /* 0x000000040a0a7824 */
/* 0x100fe200078e0201 */
/*0f70*/ USHF.R.U32.HI UR23, URZ, 0xd, UR23 ; /* 0x0000000d3f177899 */
/* 0x000fe20008011617 */
/*0f80*/ LDL R9, [R9] ; /* 0x0000000009097983 */
/* 0x000f620000100800 */
/*0f90*/ UIMAD UR5, UR20, -0x3000, UR24 ; /* 0xffffd000140578a4 */
/* 0x000fe2000f8e0218 */
/*0fa0*/ IADD3 R14, R0, UR6, RZ ; /* 0x00000006000e7c10 */
/* 0x000fe2000fffe0ff */
/*0fb0*/ UIMAD.WIDE.U32 UR26, UR30, -0x55555555, URZ ; /* 0xaaaaaaab1e1a78a5 */
/* 0x000fe2000f8e003f */
/*0fc0*/ LEA R11, R12, R1.reuse, 0x2 ; /* 0x000000010c0b7211 */
/* 0x080fe200078e10ff */
/*0fd0*/ UMOV UR22, 0x9 ; /* 0x0000000900167882 */
/* 0x000fe20000000000 */
/*0fe0*/ LDL R10, [R10] ; /* 0x000000000a0a7983 */
/* 0x000f620000100800 */
/*0ff0*/ UIMAD UR22, UR23, -0x3000, UR22 ; /* 0xffffd000171678a4 */
/* 0x000fe2000f8e0216 */
/*1000*/ IADD3 R16, R0, UR5, RZ ; /* 0x0000000500107c10 */
/* 0x000fe2000fffe0ff */
/*1010*/ USHF.R.U32.HI UR26, URZ, 0xd, UR27 ; /* 0x0000000d3f1a7899 */
/* 0x000fe2000801161b */
/*1020*/ IMAD R12, R14, 0x4, R1.reuse ; /* 0x000000040e0c7824 */
/* 0x100fe200078e0201 */
/*1030*/ UMOV UR17, 0xa ; /* 0x0000000a00117882 */
/* 0x000fe20000000000 */
/*1040*/ LDL R11, [R11] ; /* 0x000000000b0b7983 */
/* 0x000f620000100800 */
/*1050*/ USHF.R.U32.HI UR4, URZ, 0xd, UR25 ; /* 0x0000000d3f047899 */
/* 0x000fe20008011619 */
/*1060*/ IADD3 R14, R0, UR22, RZ ; /* 0x00000016000e7c10 */
/* 0x000fe2000fffe0ff */
/*1070*/ UIMAD UR17, UR26, -0x3000, UR17 ; /* 0xffffd0001a1178a4 */
/* 0x000fe2000f8e0211 */
/*1080*/ LEA R13, R16, R1.reuse, 0x2 ; /* 0x00000001100d7211 */
/* 0x080fe200078e10ff */
/*1090*/ UMOV UR16, 0xb ; /* 0x0000000b00107882 */
/* 0x000fe20000000000 */
/*10a0*/ LDL R12, [R12] ; /* 0x000000000c0c7983 */
/* 0x000f620000100800 */
/*10b0*/ UIMAD UR4, UR4, -0x3000, UR16 ; /* 0xffffd000040478a4 */
/* 0x000fe2000f8e0210 */
/*10c0*/ IMAD R14, R14, 0x4, R1 ; /* 0x000000040e0e7824 */
/* 0x000fe200078e0201 */
/*10d0*/ IADD3 R16, R0.reuse, UR17, RZ ; /* 0x0000001100107c10 */
/* 0x040fe2000fffe0ff */
/*10e0*/ LDL R13, [R13] ; /* 0x000000000d0d7983 */
/* 0x000f660000100800 */
/*10f0*/ IADD3 R18, R0, UR4, RZ ; /* 0x0000000400127c10 */
/* 0x000fe2000fffe0ff */
/*1100*/ LDL R17, [R14] ; /* 0x000000000e117983 */
/* 0x000f620000100800 */
/*1110*/ LEA R16, R16, R1, 0x2 ; /* 0x0000000110107211 */
/* 0x000fc600078e10ff */
/*1120*/ IMAD R18, R18, 0x4, R1 ; /* 0x0000000412127824 */
/* 0x000fe400078e0201 */
/*1130*/ LDL R19, [R16] ; /* 0x0000000010137983 */
/* 0x000f680000100800 */
/*1140*/ LDL R21, [R18] ; /* 0x0000000012157983 */
/* 0x000f620000100800 */
/*1150*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*1160*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*1170*/ UIADD3 UR40, UR40, 0x1, URZ ; /* 0x0000000128287890 */
/* 0x000fe4000fffe03f */
/*1180*/ UIADD3 UR30, UR30, 0x1, URZ ; /* 0x000000011e1e7890 */
/* 0x000fe4000fffe03f */
/*1190*/ UIADD3 UR39, UR39, 0x1, URZ ; /* 0x0000000127277890 */
/* 0x000fe4000fffe03f */
/*11a0*/ UIADD3 UR38, UR38, 0x1, URZ ; /* 0x0000000126267890 */
/* 0x000fe4000fffe03f */
/*11b0*/ UIADD3 UR37, UR37, 0x1, URZ ; /* 0x0000000125257890 */
/* 0x000fe4000fffe03f */
/*11c0*/ UIADD3 UR36, UR36, 0x1, URZ ; /* 0x0000000124247890 */
/* 0x000fc4000fffe03f */
/*11d0*/ UIADD3 UR35, UR35, 0x1, URZ ; /* 0x0000000123237890 */
/* 0x000fe4000fffe03f */
/*11e0*/ UIADD3 UR34, UR34, 0x1, URZ ; /* 0x0000000122227890 */
/* 0x000fe4000fffe03f */
/*11f0*/ UIADD3 UR33, UR33, 0x1, URZ ; /* 0x0000000121217890 */
/* 0x000fe4000fffe03f */
/*1200*/ UIADD3 UR32, UR32, 0x1, URZ ; /* 0x0000000120207890 */
/* 0x000fe4000fffe03f */
/*1210*/ UIADD3 UR31, UR31, 0x1, URZ ; /* 0x000000011f1f7890 */
/* 0x000fe2000fffe03f */
/*1220*/ FADD R15, RZ, R4 ; /* 0x00000004ff0f7221 */
/* 0x004fc80000000000 */
/*1230*/ FADD R6, R15, R6 ; /* 0x000000060f067221 */
/* 0x008fc80000000000 */
/*1240*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x010fc80000000000 */
/*1250*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x020fc80000000000 */
/*1260*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*1270*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*1280*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*1290*/ FADD R12, R11, R12 ; /* 0x0000000c0b0c7221 */
/* 0x000fc80000000000 */
/*12a0*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x000fc80000000000 */
/*12b0*/ FADD R12, R12, R17 ; /* 0x000000110c0c7221 */
/* 0x000fc80000000000 */
/*12c0*/ FADD R12, R12, R19 ; /* 0x000000130c0c7221 */
/* 0x000fc80000000000 */
/*12d0*/ FADD R12, R12, R21 ; /* 0x000000150c0c7221 */
/* 0x000fc80000000000 */
/*12e0*/ FADD R5, R12, R5 ; /* 0x000000050c057221 */
/* 0x000fe20000000000 */
/*12f0*/ @!P0 BRA 0xc90 ; /* 0xfffff99000008947 */
/* 0x000fea000383ffff */
/*1300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c10191c */
/*1310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1320*/ BRA 0x1320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float dothings(int t,int sz, float *input){
float ans = 0;
for(int i=0;i<12;++i){
ans += input[(i+t)%sz];
}
return ans;
}
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float local_data[VEC_SIZE];
float ans = 0.;
for(int i=0;i<VEC_SIZE;++i) local_data[i] = input[VEC_SIZE * g_id + i];
for(int t=0;t<N_step;++t){
ans += dothings(t, VEC_SIZE, local_data);
}
output[g_id] = ans;
return;
} | .file "tmpxft_0006e608_00000000-6_process.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8dothingsiiPf
.type _Z8dothingsiiPf, @function
_Z8dothingsiiPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8dothingsiiPf, .-_Z8dothingsiiPf
.globl _Z30__device_stub__Z7processiiPfS_iiPfS_
.type _Z30__device_stub__Z7processiiPfS_iiPfS_, @function
_Z30__device_stub__Z7processiiPfS_iiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7processiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z7processiiPfS_iiPfS_, .-_Z30__device_stub__Z7processiiPfS_iiPfS_
.globl _Z7processiiPfS_
.type _Z7processiiPfS_, @function
_Z7processiiPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7processiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7processiiPfS_, .-_Z7processiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7processiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7processiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float dothings(int t,int sz, float *input){
float ans = 0;
for(int i=0;i<12;++i){
ans += input[(i+t)%sz];
}
return ans;
}
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float local_data[VEC_SIZE];
float ans = 0.;
for(int i=0;i<VEC_SIZE;++i) local_data[i] = input[VEC_SIZE * g_id + i];
for(int t=0;t<N_step;++t){
ans += dothings(t, VEC_SIZE, local_data);
}
output[g_id] = ans;
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float dothings(int t,int sz, float *input){
float ans = 0;
for(int i=0;i<12;++i){
ans += input[(i+t)%sz];
}
return ans;
}
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float local_data[VEC_SIZE];
float ans = 0.;
for(int i=0;i<VEC_SIZE;++i) local_data[i] = input[VEC_SIZE * g_id + i];
for(int t=0;t<N_step;++t){
ans += dothings(t, VEC_SIZE, local_data);
}
output[g_id] = ans;
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float dothings(int t,int sz, float *input){
float ans = 0;
for(int i=0;i<12;++i){
ans += input[(i+t)%sz];
}
return ans;
}
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float local_data[VEC_SIZE];
float ans = 0.;
for(int i=0;i<VEC_SIZE;++i) local_data[i] = input[VEC_SIZE * g_id + i];
for(int t=0;t<N_step;++t){
ans += dothings(t, VEC_SIZE, local_data);
}
output[g_id] = ans;
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7processiiPfS_
.globl _Z7processiiPfS_
.p2align 8
.type _Z7processiiPfS_,@function
_Z7processiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_lo_u32 v2, v1, 0x3000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
.LBB0_2:
global_load_b32 v0, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s3, s2, 16
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_u32 s2, 0xc000
s_waitcnt vmcnt(0)
scratch_store_b32 off, v0, s3
s_cbranch_scc0 .LBB0_2
s_load_b32 s2, s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_8
s_mov_b32 s3, 16
s_mov_b32 s4, 0
.p2align 6
.LBB0_5:
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 12
s_mov_b32 s6, s4
s_mov_b32 s7, s3
.LBB0_6:
s_mul_hi_u32 s8, s6, 0xaaaaaaab
s_add_i32 s5, s5, -1
s_lshr_b32 s8, s8, 13
s_add_i32 s6, s6, 1
s_mul_i32 s8, s8, 0xffff4000
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s8, s7, s8
s_add_i32 s7, s7, 4
scratch_load_b32 v3, off, s8
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_cbranch_scc1 .LBB0_6
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v2
s_add_i32 s4, s4, 1
s_add_i32 s3, s3, 4
s_cmp_eq_u32 s4, s2
s_cbranch_scc0 .LBB0_5
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_9:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7processiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 49168
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7processiiPfS_, .Lfunc_end0-_Z7processiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7processiiPfS_
.private_segment_fixed_size: 49168
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7processiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float dothings(int t,int sz, float *input){
float ans = 0;
for(int i=0;i<12;++i){
ans += input[(i+t)%sz];
}
return ans;
}
__global__ void process(int N_step, int N_inst, float *input, float *output){
int g_id = blockIdx.x * blockDim.x + threadIdx.x;
if(g_id >= N_inst) return;
float local_data[VEC_SIZE];
float ans = 0.;
for(int i=0;i<VEC_SIZE;++i) local_data[i] = input[VEC_SIZE * g_id + i];
for(int t=0;t<N_step;++t){
ans += dothings(t, VEC_SIZE, local_data);
}
output[g_id] = ans;
return;
} | .text
.file "process.hip"
.globl _Z22__device_stub__processiiPfS_ # -- Begin function _Z22__device_stub__processiiPfS_
.p2align 4, 0x90
.type _Z22__device_stub__processiiPfS_,@function
_Z22__device_stub__processiiPfS_: # @_Z22__device_stub__processiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7processiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__processiiPfS_, .Lfunc_end0-_Z22__device_stub__processiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7processiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7processiiPfS_,@object # @_Z7processiiPfS_
.section .rodata,"a",@progbits
.globl _Z7processiiPfS_
.p2align 3, 0x0
_Z7processiiPfS_:
.quad _Z22__device_stub__processiiPfS_
.size _Z7processiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7processiiPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__processiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7processiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006e608_00000000-6_process.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8dothingsiiPf
.type _Z8dothingsiiPf, @function
_Z8dothingsiiPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8dothingsiiPf, .-_Z8dothingsiiPf
.globl _Z30__device_stub__Z7processiiPfS_iiPfS_
.type _Z30__device_stub__Z7processiiPfS_iiPfS_, @function
_Z30__device_stub__Z7processiiPfS_iiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7processiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z7processiiPfS_iiPfS_, .-_Z30__device_stub__Z7processiiPfS_iiPfS_
.globl _Z7processiiPfS_
.type _Z7processiiPfS_, @function
_Z7processiiPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7processiiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7processiiPfS_, .-_Z7processiiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7processiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7processiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "process.hip"
.globl _Z22__device_stub__processiiPfS_ # -- Begin function _Z22__device_stub__processiiPfS_
.p2align 4, 0x90
.type _Z22__device_stub__processiiPfS_,@function
_Z22__device_stub__processiiPfS_: # @_Z22__device_stub__processiiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7processiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__processiiPfS_, .Lfunc_end0-_Z22__device_stub__processiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7processiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7processiiPfS_,@object # @_Z7processiiPfS_
.section .rodata,"a",@progbits
.globl _Z7processiiPfS_
.p2align 3, 0x0
_Z7processiiPfS_:
.quad _Z22__device_stub__processiiPfS_
.size _Z7processiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7processiiPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__processiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7processiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // nvcc backGroundSubtractionWyatt.cu -o temp.exe -lm
#include <math.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
// size of vector
#define FRAMES 5 // Number of frames
#define PIXELS_PER_FRAME 10 // Number of pixels per frame
#define BLOCK 128 // Size of blocks, best if it is a power of 2.
// Globals
int *BlockOfFrames_CPU, *BlockOfFrames_GPU;
float *MeanFrame_GPU;
float *BlockOfLogNormalFrames_GPU;
float *MeanLogNormalFrame_GPU;
float *MedianLogNormalFrame_GPU;
float *StdvLogNormalFrame_GPU;
int *NewFrame_CPU, *NewFrame_GPU;
int *BlackAndWhiteFrame_CPU, *BlackAndWhiteFrame_GPU;
// These globals can be removed after debugging.
float *BlockOfLogNormalFrames_CPU;
float *MeanFrame_CPU;
float *MeanLogNormalFrame_CPU;
float *MedianLogNormalFrame_CPU;
float *StdvLogNormalFrame_CPU;
dim3 dimBlock, dimGrid;
void AllocateMemory()
{
// This are the set of frames that will be used to generate the log normal frame
// and the standard deviation frame
BlockOfFrames_CPU = (int *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(int));
cudaMalloc((void**)&BlockOfFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(int));
cudaMalloc((void**)&BlockOfLogNormalFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(float));
// Will hold the log normal frame and the standard deviation of the frames minus the log normal
cudaMalloc((void**)&MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
NewFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
BlackAndWhiteFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&NewFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
cudaMalloc((void**)&BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
// These all can be removed latter. I'm just using them for debuging
BlockOfLogNormalFrames_CPU = (float *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(float));
MeanFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MeanLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MedianLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
StdvLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
}
void loadPixels()
{
/*
However you get 300,000 by 80 pixels loaded in here then CUDA will do the rest.
This is loading the big vector from 1st 300,000 then from 2nd 300,000 and so on until frame 80.
It may be faster to load the pixels the other way 80 first pixels then 80 second pixels and so on 300000 times.
Test it and see.
I just load (below) some small values to check that everything is working.
M is the number of frames and N is the number of pixels per frame
*/
for(int i = 0; i < FRAMES; i++)
{
for(int j = 0; j < PIXELS_PER_FRAME; j++)
{
BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = i;
if(i == 4) BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = 12;
}
}
}
void loadNewFrame()
{
//This is where you will load the image to be processed.
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
NewFrame_CPU[i] = i*2;
}
}
void SetUpCudaDevices()
{
dimBlock.x = BLOCK;
dimBlock.y = 1;
dimBlock.z = 1;
dimGrid.x = ((PIXELS_PER_FRAME - 1)/BLOCK)+1;
dimGrid.y = 1;
dimGrid.z = 1;
}
__global__ void creatingMeanPixelFrame(float *meanFrame, int *allFrames, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFrames[pixel + pixelsPerFrame*i];
}
meanFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingLogNormalFrames(float *meanFrame, int *allFrames, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int id;
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
//Same screen location (pixel) but moving through frames (i).
id = pixel + pixelsPerFrame*i;
allFramesLogNormal[id] = (float)allFrames[id] - meanFrame[pixel];
allFramesLogNormal[id] = abs(allFramesLogNormal[id]);
//Can't take log of zero so to be safe check and move it off zero.
if(allFramesLogNormal[id] == 0.0f)
{
allFramesLogNormal[id] = 0.000001f;
}
allFramesLogNormal[id] = logf(allFramesLogNormal[id]);
//allFramesLogNormal[id] = (float)allFrames[id]; // Remove after debugging.
}
}
}
__global__ void creatingMeanLogNormalFrame(float *meanlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFramesLogNormal[pixel + pixelsPerFrame*i];
}
meanlogNormalFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingMedianLogNormalFrame(float *medianlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
int used[FRAMES], index, count;
float median = 0.0;
float small;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
used[i] = 0;
}
if(frames%2 == 0)
{
int middle2 = frames/2;
int middle1 = middle2 - 1;
index = -1;
count = 0;
while(count <= middle2)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small && used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle1 || count == middle2)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
median /=2.0f;
}
else
{
int middle = frames/2;
index = -1;
count = 0;
while(count <= middle)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small)
{
if(used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
}
medianlogNormalFrame[pixel] = median;
}
}
__global__ void creatingStdvLogNormalFrame(float *stdvLogNormalFrame, float *meanLogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float temp;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
temp = allFramesLogNormal[pixel + pixelsPerFrame*i] - meanLogNormalFrame[pixel];
sum += temp*temp;
}
stdvLogNormalFrame[pixel] = sqrtf((sum)/(float)(frames-1));
}
}
__global__ void CreateBlackAndWHiteFrame(int *BlackAndWhiteFrame_GPU, int *NewFrame_GPU, float *StdvLogNormalFrame_GPU, float *MeanLogNormalFrame_GPU, int pixelsPerFrame)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float breakPoint = 2.0f; // ************** not sure what this value should be ??????????
if(pixel < pixelsPerFrame)
{
float CDF = 0.5f + 0.5f*erff((logf((float)NewFrame_GPU[pixel]) - MeanLogNormalFrame_GPU[pixel])/sqrtf(2.0*StdvLogNormalFrame_GPU[pixel]));
if(CDF < breakPoint)
{
BlackAndWhiteFrame_GPU[pixel] = 0;
}
else
{
BlackAndWhiteFrame_GPU[pixel] = 1; //Can remove this if you do a memset before you use the data.
}
}
}
void errorCheck(const char *message)
{
cudaError_t error;
error = cudaGetLastError();
if(error != cudaSuccess)
{
printf("\n CUDA ERROR: %s = %s\n", message, cudaGetErrorString(error));
exit(0);
}
}
void stats()
{
cudaMemcpyAsync(BlockOfLogNormalFrames_CPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME*FRAMES*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
cudaMemcpyAsync(MeanFrame_CPU, MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
cudaMemcpyAsync(MeanLogNormalFrame_CPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy MeanLogNormal frame down");
cudaMemcpyAsync(MedianLogNormalFrame_CPU, MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy MedianLogNormal frame down");
cudaMemcpyAsync(StdvLogNormalFrame_CPU, StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy StdvLogNormal frame down");
printf("\n\n");
printf("frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%d ", BlockOfFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
printf("log normal frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%f ", BlockOfLogNormalFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n", i, MeanFrame_CPU[i], i, MeanLogNormalFrame_CPU[i], i, MedianLogNormalFrame_CPU[i], i, StdvLogNormalFrame_CPU[i]);
}
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n", i, NewFrame_CPU[i], i, BlackAndWhiteFrame_CPU[i]);
}
}
void cleanUp()
{
free(BlockOfFrames_CPU);
free(NewFrame_CPU);
free(BlackAndWhiteFrame_CPU);
cudaFree(BlockOfFrames_GPU);
cudaFree(BlockOfLogNormalFrames_GPU);
cudaFree(MeanFrame_GPU);
cudaFree(MeanLogNormalFrame_GPU);
cudaFree(MedianLogNormalFrame_GPU);
cudaFree(StdvLogNormalFrame_GPU);
cudaFree(NewFrame_GPU);
cudaFree(BlackAndWhiteFrame_GPU);
// These can be removed latter. I just used them for debuging.
free(BlockOfLogNormalFrames_CPU);
free(MeanFrame_CPU);
free(MeanLogNormalFrame_CPU);
free(MedianLogNormalFrame_CPU);
free(StdvLogNormalFrame_CPU);
}
int main()
{
AllocateMemory();
SetUpCudaDevices();
loadPixels();
cudaMemcpyAsync(BlockOfFrames_GPU, BlockOfFrames_CPU, PIXELS_PER_FRAME*FRAMES*sizeof(int), cudaMemcpyHostToDevice);
errorCheck("copyFramessUp");
cudaDeviceSynchronize();
creatingMeanPixelFrame<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanPixelFrame");
creatingLogNormalFrames<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingLogNormalFrames");
creatingMeanLogNormalFrame<<<dimGrid,dimBlock>>>(MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanLogNormalFrame");
creatingMedianLogNormalFrame<<<dimGrid,dimBlock>>>(MedianLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMedianLogNormalFrame");
creatingStdvLogNormalFrame<<<dimGrid,dimBlock>>>(StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingStdvLogNormalFrame");
cudaDeviceSynchronize();
loadNewFrame();
cudaMemcpyAsync(NewFrame_GPU, NewFrame_CPU, PIXELS_PER_FRAME*sizeof(int), cudaMemcpyHostToDevice);
errorCheck("copy New frame up");
CreateBlackAndWHiteFrame<<<dimGrid,dimBlock>>>(BlackAndWhiteFrame_GPU, NewFrame_GPU, StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME);
errorCheck("creatingStdvLogNormalFrame");
cudaMemcpyAsync(BlackAndWhiteFrame_CPU, BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy black and white frame down");
//Do stuff with black and white frame
stats();
cleanUp();
printf("\n DONE \n");
} | .file "tmpxft_001b843a_00000000-6_backGroundSubtractionWyatt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14AllocateMemoryv
.type _Z14AllocateMemoryv, @function
_Z14AllocateMemoryv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $200, %edi
call malloc@PLT
movq %rax, BlockOfFrames_CPU(%rip)
movl $200, %esi
leaq BlockOfFrames_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $200, %esi
leaq BlockOfLogNormalFrames_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $40, %esi
leaq MeanFrame_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $40, %esi
leaq MeanLogNormalFrame_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $40, %esi
leaq MedianLogNormalFrame_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $40, %esi
leaq StdvLogNormalFrame_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $40, %edi
call malloc@PLT
movq %rax, NewFrame_CPU(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, BlackAndWhiteFrame_CPU(%rip)
movl $40, %esi
leaq NewFrame_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $40, %esi
leaq BlackAndWhiteFrame_GPU(%rip), %rdi
call cudaMalloc@PLT
movl $200, %edi
call malloc@PLT
movq %rax, BlockOfLogNormalFrames_CPU(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, MeanFrame_CPU(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, MeanLogNormalFrame_CPU(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, MedianLogNormalFrame_CPU(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, StdvLogNormalFrame_CPU(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14AllocateMemoryv, .-_Z14AllocateMemoryv
.globl _Z10loadPixelsv
.type _Z10loadPixelsv, @function
_Z10loadPixelsv:
.LFB2058:
.cfi_startproc
endbr64
movl $40, %esi
movl $0, %edx
jmp .L6
.L12:
movq BlockOfFrames_CPU(%rip), %rcx
movl $12, (%rcx,%rax)
addq $4, %rax
cmpq %rsi, %rax
je .L11
.L10:
movq BlockOfFrames_CPU(%rip), %rcx
movl %edx, (%rcx,%rax)
cmpl $4, %edx
je .L12
addq $4, %rax
cmpq %rsi, %rax
jne .L10
addl $1, %edx
addq $40, %rsi
cmpl $5, %edx
je .L5
.L6:
leaq -40(%rsi), %rax
jmp .L10
.L11:
ret
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z10loadPixelsv, .-_Z10loadPixelsv
.globl _Z12loadNewFramev
.type _Z12loadNewFramev, @function
_Z12loadNewFramev:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %edx
movl $0, %eax
.L14:
movq NewFrame_CPU(%rip), %rcx
movl %edx, (%rcx,%rax)
addq $4, %rax
addl $2, %edx
cmpq $40, %rax
jne .L14
ret
.cfi_endproc
.LFE2059:
.size _Z12loadNewFramev, .-_Z12loadNewFramev
.globl _Z16SetUpCudaDevicesv
.type _Z16SetUpCudaDevicesv, @function
_Z16SetUpCudaDevicesv:
.LFB2060:
.cfi_startproc
endbr64
movl $128, dimBlock(%rip)
movl $1, 4+dimBlock(%rip)
movl $1, 8+dimBlock(%rip)
movl $1, dimGrid(%rip)
movl $1, 4+dimGrid(%rip)
movl $1, 8+dimGrid(%rip)
ret
.cfi_endproc
.LFE2060:
.size _Z16SetUpCudaDevicesv, .-_Z16SetUpCudaDevicesv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n CUDA ERROR: %s = %s\n"
.text
.globl _Z10errorCheckPKc
.type _Z10errorCheckPKc, @function
_Z10errorCheckPKc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z10errorCheckPKc, .-_Z10errorCheckPKc
.section .rodata.str1.1
.LC1:
.string "copy Mean frame down"
.LC2:
.string "copy MeanLogNormal frame down"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "copy MedianLogNormal frame down"
.section .rodata.str1.1
.LC4:
.string "copy StdvLogNormal frame down"
.LC5:
.string "\n\n"
.LC6:
.string "frames"
.LC7:
.string "\n"
.LC8:
.string "%d "
.LC9:
.string "log normal frames"
.LC10:
.string "%f "
.section .rodata.str1.8
.align 8
.LC11:
.string "MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n"
.align 8
.LC12:
.string "NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n"
.text
.globl _Z5statsv
.type _Z5statsv, @function
_Z5statsv:
.LFB2062:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %r8d
movl $2, %ecx
movl $200, %edx
movq BlockOfLogNormalFrames_GPU(%rip), %rsi
movq BlockOfLogNormalFrames_CPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
call _Z10errorCheckPKc
movl $0, %r8d
movl $2, %ecx
movl $40, %edx
movq MeanFrame_GPU(%rip), %rsi
movq MeanFrame_CPU(%rip), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rdi
call _Z10errorCheckPKc
movl $0, %r8d
movl $2, %ecx
movl $40, %edx
movq MeanLogNormalFrame_GPU(%rip), %rsi
movq MeanLogNormalFrame_CPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC2(%rip), %rdi
call _Z10errorCheckPKc
movl $0, %r8d
movl $2, %ecx
movl $40, %edx
movq MedianLogNormalFrame_GPU(%rip), %rsi
movq MedianLogNormalFrame_CPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC3(%rip), %rdi
call _Z10errorCheckPKc
movl $0, %r8d
movl $2, %ecx
movl $40, %edx
movq StdvLogNormalFrame_GPU(%rip), %rsi
movq StdvLogNormalFrame_CPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC4(%rip), %rdi
call _Z10errorCheckPKc
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $40, %ebp
leaq .LC7(%rip), %r13
leaq .LC8(%rip), %r12
.L23:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -40(%rbp), %rbx
.L22:
movq BlockOfFrames_CPU(%rip), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L22
addq $40, %rbp
cmpq $240, %rbp
jne .L23
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $40, %ebp
leaq .LC7(%rip), %r13
leaq .LC10(%rip), %r12
.L25:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -40(%rbp), %rbx
.L24:
movq BlockOfLogNormalFrames_CPU(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
addq $40, %rbp
cmpq $240, %rbp
jne .L25
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L26:
movl %ebx, %edx
movq MeanFrame_CPU(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq StdvLogNormalFrame_CPU(%rip), %rax
pxor %xmm3, %xmm3
cvtss2sd (%rax,%rbx,4), %xmm3
movl %ebx, %r9d
movq MedianLogNormalFrame_CPU(%rip), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rbx,4), %xmm2
movl %ebx, %r8d
movq MeanLogNormalFrame_CPU(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movl %ebx, %ecx
movq %rbp, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L26
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L27:
movl %ebx, %edx
movq NewFrame_CPU(%rip), %rax
movl (%rax,%rbx,4), %ecx
movq BlackAndWhiteFrame_CPU(%rip), %rax
movl (%rax,%rbx,4), %r9d
movl %ebx, %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L27
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z5statsv, .-_Z5statsv
.globl _Z7cleanUpv
.type _Z7cleanUpv, @function
_Z7cleanUpv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq BlockOfFrames_CPU(%rip), %rdi
call free@PLT
movq NewFrame_CPU(%rip), %rdi
call free@PLT
movq BlackAndWhiteFrame_CPU(%rip), %rdi
call free@PLT
movq BlockOfFrames_GPU(%rip), %rdi
call cudaFree@PLT
movq BlockOfLogNormalFrames_GPU(%rip), %rdi
call cudaFree@PLT
movq MeanFrame_GPU(%rip), %rdi
call cudaFree@PLT
movq MeanLogNormalFrame_GPU(%rip), %rdi
call cudaFree@PLT
movq MedianLogNormalFrame_GPU(%rip), %rdi
call cudaFree@PLT
movq StdvLogNormalFrame_GPU(%rip), %rdi
call cudaFree@PLT
movq NewFrame_GPU(%rip), %rdi
call cudaFree@PLT
movq BlackAndWhiteFrame_GPU(%rip), %rdi
call cudaFree@PLT
movq BlockOfLogNormalFrames_CPU(%rip), %rdi
call free@PLT
movq MeanFrame_CPU(%rip), %rdi
call free@PLT
movq MeanLogNormalFrame_CPU(%rip), %rdi
call free@PLT
movq MedianLogNormalFrame_CPU(%rip), %rdi
call free@PLT
movq StdvLogNormalFrame_CPU(%rip), %rdi
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z7cleanUpv, .-_Z7cleanUpv
.globl _Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
.type _Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii, @function
_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22creatingMeanPixelFramePfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii, .-_Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
.globl _Z22creatingMeanPixelFramePfPiii
.type _Z22creatingMeanPixelFramePfPiii, @function
_Z22creatingMeanPixelFramePfPiii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z22creatingMeanPixelFramePfPiii, .-_Z22creatingMeanPixelFramePfPiii
.globl _Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
.type _Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii, @function
_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23creatingLogNormalFramesPfPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii, .-_Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
.globl _Z23creatingLogNormalFramesPfPiS_ii
.type _Z23creatingLogNormalFramesPfPiS_ii, @function
_Z23creatingLogNormalFramesPfPiS_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z23creatingLogNormalFramesPfPiS_ii, .-_Z23creatingLogNormalFramesPfPiS_ii
.globl _Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
.type _Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii, @function
_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26creatingMeanLogNormalFramePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii, .-_Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
.globl _Z26creatingMeanLogNormalFramePfS_ii
.type _Z26creatingMeanLogNormalFramePfS_ii, @function
_Z26creatingMeanLogNormalFramePfS_ii:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z26creatingMeanLogNormalFramePfS_ii, .-_Z26creatingMeanLogNormalFramePfS_ii
.globl _Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
.type _Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii, @function
_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28creatingMedianLogNormalFramePfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii, .-_Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
.globl _Z28creatingMedianLogNormalFramePfS_ii
.type _Z28creatingMedianLogNormalFramePfS_ii, @function
_Z28creatingMedianLogNormalFramePfS_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z28creatingMedianLogNormalFramePfS_ii, .-_Z28creatingMedianLogNormalFramePfS_ii
.globl _Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
.type _Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii, @function
_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26creatingStdvLogNormalFramePfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii, .-_Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
.globl _Z26creatingStdvLogNormalFramePfS_S_ii
.type _Z26creatingStdvLogNormalFramePfS_S_ii, @function
_Z26creatingStdvLogNormalFramePfS_S_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z26creatingStdvLogNormalFramePfS_S_ii, .-_Z26creatingStdvLogNormalFramePfS_S_ii
.globl _Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
.type _Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i, @function
_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i:
.LFB2099:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24CreateBlackAndWHiteFramePiS_PfS0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i, .-_Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
.globl _Z24CreateBlackAndWHiteFramePiS_PfS0_i
.type _Z24CreateBlackAndWHiteFramePiS_PfS0_i, @function
_Z24CreateBlackAndWHiteFramePiS_PfS0_i:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _Z24CreateBlackAndWHiteFramePiS_PfS0_i, .-_Z24CreateBlackAndWHiteFramePiS_PfS0_i
.section .rodata.str1.1
.LC13:
.string "copyFramessUp"
.LC14:
.string "creatingMeanPixelFrame"
.LC15:
.string "creatingLogNormalFrames"
.LC16:
.string "creatingMeanLogNormalFrame"
.LC17:
.string "creatingMedianLogNormalFrame"
.LC18:
.string "creatingStdvLogNormalFrame"
.LC19:
.string "copy New frame up"
.section .rodata.str1.8
.align 8
.LC20:
.string "copy black and white frame down"
.section .rodata.str1.1
.LC21:
.string "\n DONE \n"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z14AllocateMemoryv
call _Z16SetUpCudaDevicesv
call _Z10loadPixelsv
movl $0, %r8d
movl $1, %ecx
movl $200, %edx
movq BlockOfFrames_CPU(%rip), %rsi
movq BlockOfFrames_GPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC13(%rip), %rdi
call _Z10errorCheckPKc
call cudaDeviceSynchronize@PLT
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L86:
leaq .LC14(%rip), %rdi
call _Z10errorCheckPKc
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L87:
leaq .LC15(%rip), %rdi
call _Z10errorCheckPKc
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L88:
leaq .LC16(%rip), %rdi
call _Z10errorCheckPKc
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L89:
leaq .LC17(%rip), %rdi
call _Z10errorCheckPKc
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L97
.L90:
leaq .LC18(%rip), %rdi
call _Z10errorCheckPKc
call cudaDeviceSynchronize@PLT
call _Z12loadNewFramev
movl $0, %r8d
movl $1, %ecx
movl $40, %edx
movq NewFrame_CPU(%rip), %rsi
movq NewFrame_GPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC19(%rip), %rdi
call _Z10errorCheckPKc
movl 8+dimBlock(%rip), %ecx
movl $0, %r9d
movl $0, %r8d
movq dimBlock(%rip), %rdx
movq dimGrid(%rip), %rdi
movl 8+dimGrid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L91:
leaq .LC18(%rip), %rdi
call _Z10errorCheckPKc
movl $0, %r8d
movl $2, %ecx
movl $40, %edx
movq BlackAndWhiteFrame_GPU(%rip), %rsi
movq BlackAndWhiteFrame_CPU(%rip), %rdi
call cudaMemcpyAsync@PLT
leaq .LC20(%rip), %rdi
call _Z10errorCheckPKc
call _Z5statsv
call _Z7cleanUpv
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L93:
.cfi_restore_state
movl $5, %ecx
movl $10, %edx
movq BlockOfFrames_GPU(%rip), %rsi
movq MeanFrame_GPU(%rip), %rdi
call _Z46__device_stub__Z22creatingMeanPixelFramePfPiiiPfPiii
jmp .L86
.L94:
movl $5, %r8d
movl $10, %ecx
movq BlockOfLogNormalFrames_GPU(%rip), %rdx
movq BlockOfFrames_GPU(%rip), %rsi
movq MeanFrame_GPU(%rip), %rdi
call _Z49__device_stub__Z23creatingLogNormalFramesPfPiS_iiPfPiS_ii
jmp .L87
.L95:
movl $5, %ecx
movl $10, %edx
movq BlockOfLogNormalFrames_GPU(%rip), %rsi
movq MeanLogNormalFrame_GPU(%rip), %rdi
call _Z50__device_stub__Z26creatingMeanLogNormalFramePfS_iiPfS_ii
jmp .L88
.L96:
movl $5, %ecx
movl $10, %edx
movq BlockOfLogNormalFrames_GPU(%rip), %rsi
movq MedianLogNormalFrame_GPU(%rip), %rdi
call _Z52__device_stub__Z28creatingMedianLogNormalFramePfS_iiPfS_ii
jmp .L89
.L97:
movl $5, %r8d
movl $10, %ecx
movq BlockOfLogNormalFrames_GPU(%rip), %rdx
movq MeanLogNormalFrame_GPU(%rip), %rsi
movq StdvLogNormalFrame_GPU(%rip), %rdi
call _Z52__device_stub__Z26creatingStdvLogNormalFramePfS_S_iiPfS_S_ii
jmp .L90
.L98:
movl $10, %r8d
movq MeanLogNormalFrame_GPU(%rip), %rcx
movq StdvLogNormalFrame_GPU(%rip), %rdx
movq NewFrame_GPU(%rip), %rsi
movq BlackAndWhiteFrame_GPU(%rip), %rdi
call _Z52__device_stub__Z24CreateBlackAndWHiteFramePiS_PfS0_iPiS_PfS0_i
jmp .L91
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC22:
.string "_Z24CreateBlackAndWHiteFramePiS_PfS0_i"
.align 8
.LC23:
.string "_Z26creatingStdvLogNormalFramePfS_S_ii"
.align 8
.LC24:
.string "_Z28creatingMedianLogNormalFramePfS_ii"
.align 8
.LC25:
.string "_Z26creatingMeanLogNormalFramePfS_ii"
.align 8
.LC26:
.string "_Z23creatingLogNormalFramesPfPiS_ii"
.align 8
.LC27:
.string "_Z22creatingMeanPixelFramePfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z24CreateBlackAndWHiteFramePiS_PfS0_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z26creatingStdvLogNormalFramePfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z28creatingMedianLogNormalFramePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z26creatingMeanLogNormalFramePfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z23creatingLogNormalFramesPfPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z22creatingMeanPixelFramePfPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimGrid
.data
.align 8
.type dimGrid, @object
.size dimGrid, 12
dimGrid:
.long 1
.long 1
.long 1
.globl dimBlock
.align 8
.type dimBlock, @object
.size dimBlock, 12
dimBlock:
.long 1
.long 1
.long 1
.globl StdvLogNormalFrame_CPU
.bss
.align 8
.type StdvLogNormalFrame_CPU, @object
.size StdvLogNormalFrame_CPU, 8
StdvLogNormalFrame_CPU:
.zero 8
.globl MedianLogNormalFrame_CPU
.align 8
.type MedianLogNormalFrame_CPU, @object
.size MedianLogNormalFrame_CPU, 8
MedianLogNormalFrame_CPU:
.zero 8
.globl MeanLogNormalFrame_CPU
.align 8
.type MeanLogNormalFrame_CPU, @object
.size MeanLogNormalFrame_CPU, 8
MeanLogNormalFrame_CPU:
.zero 8
.globl MeanFrame_CPU
.align 8
.type MeanFrame_CPU, @object
.size MeanFrame_CPU, 8
MeanFrame_CPU:
.zero 8
.globl BlockOfLogNormalFrames_CPU
.align 8
.type BlockOfLogNormalFrames_CPU, @object
.size BlockOfLogNormalFrames_CPU, 8
BlockOfLogNormalFrames_CPU:
.zero 8
.globl BlackAndWhiteFrame_GPU
.align 8
.type BlackAndWhiteFrame_GPU, @object
.size BlackAndWhiteFrame_GPU, 8
BlackAndWhiteFrame_GPU:
.zero 8
.globl BlackAndWhiteFrame_CPU
.align 8
.type BlackAndWhiteFrame_CPU, @object
.size BlackAndWhiteFrame_CPU, 8
BlackAndWhiteFrame_CPU:
.zero 8
.globl NewFrame_GPU
.align 8
.type NewFrame_GPU, @object
.size NewFrame_GPU, 8
NewFrame_GPU:
.zero 8
.globl NewFrame_CPU
.align 8
.type NewFrame_CPU, @object
.size NewFrame_CPU, 8
NewFrame_CPU:
.zero 8
.globl StdvLogNormalFrame_GPU
.align 8
.type StdvLogNormalFrame_GPU, @object
.size StdvLogNormalFrame_GPU, 8
StdvLogNormalFrame_GPU:
.zero 8
.globl MedianLogNormalFrame_GPU
.align 8
.type MedianLogNormalFrame_GPU, @object
.size MedianLogNormalFrame_GPU, 8
MedianLogNormalFrame_GPU:
.zero 8
.globl MeanLogNormalFrame_GPU
.align 8
.type MeanLogNormalFrame_GPU, @object
.size MeanLogNormalFrame_GPU, 8
MeanLogNormalFrame_GPU:
.zero 8
.globl BlockOfLogNormalFrames_GPU
.align 8
.type BlockOfLogNormalFrames_GPU, @object
.size BlockOfLogNormalFrames_GPU, 8
BlockOfLogNormalFrames_GPU:
.zero 8
.globl MeanFrame_GPU
.align 8
.type MeanFrame_GPU, @object
.size MeanFrame_GPU, 8
MeanFrame_GPU:
.zero 8
.globl BlockOfFrames_GPU
.align 8
.type BlockOfFrames_GPU, @object
.size BlockOfFrames_GPU, 8
BlockOfFrames_GPU:
.zero 8
.globl BlockOfFrames_CPU
.align 8
.type BlockOfFrames_CPU, @object
.size BlockOfFrames_CPU, 8
BlockOfFrames_CPU:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // nvcc backGroundSubtractionWyatt.cu -o temp.exe -lm
#include <math.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
// size of vector
#define FRAMES 5 // Number of frames
#define PIXELS_PER_FRAME 10 // Number of pixels per frame
#define BLOCK 128 // Size of blocks, best if it is a power of 2.
// Globals
int *BlockOfFrames_CPU, *BlockOfFrames_GPU;
float *MeanFrame_GPU;
float *BlockOfLogNormalFrames_GPU;
float *MeanLogNormalFrame_GPU;
float *MedianLogNormalFrame_GPU;
float *StdvLogNormalFrame_GPU;
int *NewFrame_CPU, *NewFrame_GPU;
int *BlackAndWhiteFrame_CPU, *BlackAndWhiteFrame_GPU;
// These globals can be removed after debugging.
float *BlockOfLogNormalFrames_CPU;
float *MeanFrame_CPU;
float *MeanLogNormalFrame_CPU;
float *MedianLogNormalFrame_CPU;
float *StdvLogNormalFrame_CPU;
dim3 dimBlock, dimGrid;
void AllocateMemory()
{
// This are the set of frames that will be used to generate the log normal frame
// and the standard deviation frame
BlockOfFrames_CPU = (int *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(int));
cudaMalloc((void**)&BlockOfFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(int));
cudaMalloc((void**)&BlockOfLogNormalFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(float));
// Will hold the log normal frame and the standard deviation of the frames minus the log normal
cudaMalloc((void**)&MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
NewFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
BlackAndWhiteFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
cudaMalloc((void**)&NewFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
cudaMalloc((void**)&BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
// These all can be removed latter. I'm just using them for debuging
BlockOfLogNormalFrames_CPU = (float *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(float));
MeanFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MeanLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MedianLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
StdvLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
}
void loadPixels()
{
/*
However you get 300,000 by 80 pixels loaded in here then CUDA will do the rest.
This is loading the big vector from 1st 300,000 then from 2nd 300,000 and so on until frame 80.
It may be faster to load the pixels the other way 80 first pixels then 80 second pixels and so on 300000 times.
Test it and see.
I just load (below) some small values to check that everything is working.
M is the number of frames and N is the number of pixels per frame
*/
for(int i = 0; i < FRAMES; i++)
{
for(int j = 0; j < PIXELS_PER_FRAME; j++)
{
BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = i;
if(i == 4) BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = 12;
}
}
}
void loadNewFrame()
{
//This is where you will load the image to be processed.
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
NewFrame_CPU[i] = i*2;
}
}
void SetUpCudaDevices()
{
dimBlock.x = BLOCK;
dimBlock.y = 1;
dimBlock.z = 1;
dimGrid.x = ((PIXELS_PER_FRAME - 1)/BLOCK)+1;
dimGrid.y = 1;
dimGrid.z = 1;
}
__global__ void creatingMeanPixelFrame(float *meanFrame, int *allFrames, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFrames[pixel + pixelsPerFrame*i];
}
meanFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingLogNormalFrames(float *meanFrame, int *allFrames, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int id;
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
//Same screen location (pixel) but moving through frames (i).
id = pixel + pixelsPerFrame*i;
allFramesLogNormal[id] = (float)allFrames[id] - meanFrame[pixel];
allFramesLogNormal[id] = abs(allFramesLogNormal[id]);
//Can't take log of zero so to be safe check and move it off zero.
if(allFramesLogNormal[id] == 0.0f)
{
allFramesLogNormal[id] = 0.000001f;
}
allFramesLogNormal[id] = logf(allFramesLogNormal[id]);
//allFramesLogNormal[id] = (float)allFrames[id]; // Remove after debugging.
}
}
}
__global__ void creatingMeanLogNormalFrame(float *meanlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFramesLogNormal[pixel + pixelsPerFrame*i];
}
meanlogNormalFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingMedianLogNormalFrame(float *medianlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
int used[FRAMES], index, count;
float median = 0.0;
float small;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
used[i] = 0;
}
if(frames%2 == 0)
{
int middle2 = frames/2;
int middle1 = middle2 - 1;
index = -1;
count = 0;
while(count <= middle2)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small && used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle1 || count == middle2)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
median /=2.0f;
}
else
{
int middle = frames/2;
index = -1;
count = 0;
while(count <= middle)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small)
{
if(used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
}
medianlogNormalFrame[pixel] = median;
}
}
__global__ void creatingStdvLogNormalFrame(float *stdvLogNormalFrame, float *meanLogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float temp;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
temp = allFramesLogNormal[pixel + pixelsPerFrame*i] - meanLogNormalFrame[pixel];
sum += temp*temp;
}
stdvLogNormalFrame[pixel] = sqrtf((sum)/(float)(frames-1));
}
}
__global__ void CreateBlackAndWHiteFrame(int *BlackAndWhiteFrame_GPU, int *NewFrame_GPU, float *StdvLogNormalFrame_GPU, float *MeanLogNormalFrame_GPU, int pixelsPerFrame)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float breakPoint = 2.0f; // ************** not sure what this value should be ??????????
if(pixel < pixelsPerFrame)
{
float CDF = 0.5f + 0.5f*erff((logf((float)NewFrame_GPU[pixel]) - MeanLogNormalFrame_GPU[pixel])/sqrtf(2.0*StdvLogNormalFrame_GPU[pixel]));
if(CDF < breakPoint)
{
BlackAndWhiteFrame_GPU[pixel] = 0;
}
else
{
BlackAndWhiteFrame_GPU[pixel] = 1; //Can remove this if you do a memset before you use the data.
}
}
}
void errorCheck(const char *message)
{
cudaError_t error;
error = cudaGetLastError();
if(error != cudaSuccess)
{
printf("\n CUDA ERROR: %s = %s\n", message, cudaGetErrorString(error));
exit(0);
}
}
void stats()
{
cudaMemcpyAsync(BlockOfLogNormalFrames_CPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME*FRAMES*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
cudaMemcpyAsync(MeanFrame_CPU, MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
cudaMemcpyAsync(MeanLogNormalFrame_CPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy MeanLogNormal frame down");
cudaMemcpyAsync(MedianLogNormalFrame_CPU, MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy MedianLogNormal frame down");
cudaMemcpyAsync(StdvLogNormalFrame_CPU, StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy StdvLogNormal frame down");
printf("\n\n");
printf("frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%d ", BlockOfFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
printf("log normal frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%f ", BlockOfLogNormalFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n", i, MeanFrame_CPU[i], i, MeanLogNormalFrame_CPU[i], i, MedianLogNormalFrame_CPU[i], i, StdvLogNormalFrame_CPU[i]);
}
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n", i, NewFrame_CPU[i], i, BlackAndWhiteFrame_CPU[i]);
}
}
void cleanUp()
{
free(BlockOfFrames_CPU);
free(NewFrame_CPU);
free(BlackAndWhiteFrame_CPU);
cudaFree(BlockOfFrames_GPU);
cudaFree(BlockOfLogNormalFrames_GPU);
cudaFree(MeanFrame_GPU);
cudaFree(MeanLogNormalFrame_GPU);
cudaFree(MedianLogNormalFrame_GPU);
cudaFree(StdvLogNormalFrame_GPU);
cudaFree(NewFrame_GPU);
cudaFree(BlackAndWhiteFrame_GPU);
// These can be removed latter. I just used them for debuging.
free(BlockOfLogNormalFrames_CPU);
free(MeanFrame_CPU);
free(MeanLogNormalFrame_CPU);
free(MedianLogNormalFrame_CPU);
free(StdvLogNormalFrame_CPU);
}
int main()
{
AllocateMemory();
SetUpCudaDevices();
loadPixels();
cudaMemcpyAsync(BlockOfFrames_GPU, BlockOfFrames_CPU, PIXELS_PER_FRAME*FRAMES*sizeof(int), cudaMemcpyHostToDevice);
errorCheck("copyFramessUp");
cudaDeviceSynchronize();
creatingMeanPixelFrame<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanPixelFrame");
creatingLogNormalFrames<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingLogNormalFrames");
creatingMeanLogNormalFrame<<<dimGrid,dimBlock>>>(MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanLogNormalFrame");
creatingMedianLogNormalFrame<<<dimGrid,dimBlock>>>(MedianLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMedianLogNormalFrame");
creatingStdvLogNormalFrame<<<dimGrid,dimBlock>>>(StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingStdvLogNormalFrame");
cudaDeviceSynchronize();
loadNewFrame();
cudaMemcpyAsync(NewFrame_GPU, NewFrame_CPU, PIXELS_PER_FRAME*sizeof(int), cudaMemcpyHostToDevice);
errorCheck("copy New frame up");
CreateBlackAndWHiteFrame<<<dimGrid,dimBlock>>>(BlackAndWhiteFrame_GPU, NewFrame_GPU, StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME);
errorCheck("creatingStdvLogNormalFrame");
cudaMemcpyAsync(BlackAndWhiteFrame_CPU, BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(float), cudaMemcpyDeviceToHost);
errorCheck("copy black and white frame down");
//Do stuff with black and white frame
stats();
cleanUp();
printf("\n DONE \n");
} | // nvcc backGroundSubtractionWyatt.cu -o temp.exe -lm
#include <hip/hip_runtime.h>
#include <math.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
// size of vector
#define FRAMES 5 // Number of frames
#define PIXELS_PER_FRAME 10 // Number of pixels per frame
#define BLOCK 128 // Size of blocks, best if it is a power of 2.
// Globals
int *BlockOfFrames_CPU, *BlockOfFrames_GPU;
float *MeanFrame_GPU;
float *BlockOfLogNormalFrames_GPU;
float *MeanLogNormalFrame_GPU;
float *MedianLogNormalFrame_GPU;
float *StdvLogNormalFrame_GPU;
int *NewFrame_CPU, *NewFrame_GPU;
int *BlackAndWhiteFrame_CPU, *BlackAndWhiteFrame_GPU;
// These globals can be removed after debugging.
float *BlockOfLogNormalFrames_CPU;
float *MeanFrame_CPU;
float *MeanLogNormalFrame_CPU;
float *MedianLogNormalFrame_CPU;
float *StdvLogNormalFrame_CPU;
dim3 dimBlock, dimGrid;
void AllocateMemory()
{
// This are the set of frames that will be used to generate the log normal frame
// and the standard deviation frame
BlockOfFrames_CPU = (int *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(int));
hipMalloc((void**)&BlockOfFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(int));
hipMalloc((void**)&BlockOfLogNormalFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(float));
// Will hold the log normal frame and the standard deviation of the frames minus the log normal
hipMalloc((void**)&MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
NewFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
BlackAndWhiteFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&NewFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
hipMalloc((void**)&BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
// These all can be removed latter. I'm just using them for debuging
BlockOfLogNormalFrames_CPU = (float *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(float));
MeanFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MeanLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MedianLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
StdvLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
}
void loadPixels()
{
/*
However you get 300,000 by 80 pixels loaded in here then CUDA will do the rest.
This is loading the big vector from 1st 300,000 then from 2nd 300,000 and so on until frame 80.
It may be faster to load the pixels the other way 80 first pixels then 80 second pixels and so on 300000 times.
Test it and see.
I just load (below) some small values to check that everything is working.
M is the number of frames and N is the number of pixels per frame
*/
for(int i = 0; i < FRAMES; i++)
{
for(int j = 0; j < PIXELS_PER_FRAME; j++)
{
BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = i;
if(i == 4) BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = 12;
}
}
}
void loadNewFrame()
{
//This is where you will load the image to be processed.
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
NewFrame_CPU[i] = i*2;
}
}
void SetUpCudaDevices()
{
dimBlock.x = BLOCK;
dimBlock.y = 1;
dimBlock.z = 1;
dimGrid.x = ((PIXELS_PER_FRAME - 1)/BLOCK)+1;
dimGrid.y = 1;
dimGrid.z = 1;
}
__global__ void creatingMeanPixelFrame(float *meanFrame, int *allFrames, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFrames[pixel + pixelsPerFrame*i];
}
meanFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingLogNormalFrames(float *meanFrame, int *allFrames, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int id;
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
//Same screen location (pixel) but moving through frames (i).
id = pixel + pixelsPerFrame*i;
allFramesLogNormal[id] = (float)allFrames[id] - meanFrame[pixel];
allFramesLogNormal[id] = abs(allFramesLogNormal[id]);
//Can't take log of zero so to be safe check and move it off zero.
if(allFramesLogNormal[id] == 0.0f)
{
allFramesLogNormal[id] = 0.000001f;
}
allFramesLogNormal[id] = logf(allFramesLogNormal[id]);
//allFramesLogNormal[id] = (float)allFrames[id]; // Remove after debugging.
}
}
}
__global__ void creatingMeanLogNormalFrame(float *meanlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFramesLogNormal[pixel + pixelsPerFrame*i];
}
meanlogNormalFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingMedianLogNormalFrame(float *medianlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
int used[FRAMES], index, count;
float median = 0.0;
float small;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
used[i] = 0;
}
if(frames%2 == 0)
{
int middle2 = frames/2;
int middle1 = middle2 - 1;
index = -1;
count = 0;
while(count <= middle2)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small && used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle1 || count == middle2)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
median /=2.0f;
}
else
{
int middle = frames/2;
index = -1;
count = 0;
while(count <= middle)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small)
{
if(used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
}
medianlogNormalFrame[pixel] = median;
}
}
__global__ void creatingStdvLogNormalFrame(float *stdvLogNormalFrame, float *meanLogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float temp;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
temp = allFramesLogNormal[pixel + pixelsPerFrame*i] - meanLogNormalFrame[pixel];
sum += temp*temp;
}
stdvLogNormalFrame[pixel] = sqrtf((sum)/(float)(frames-1));
}
}
__global__ void CreateBlackAndWHiteFrame(int *BlackAndWhiteFrame_GPU, int *NewFrame_GPU, float *StdvLogNormalFrame_GPU, float *MeanLogNormalFrame_GPU, int pixelsPerFrame)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float breakPoint = 2.0f; // ************** not sure what this value should be ??????????
if(pixel < pixelsPerFrame)
{
float CDF = 0.5f + 0.5f*erff((logf((float)NewFrame_GPU[pixel]) - MeanLogNormalFrame_GPU[pixel])/sqrtf(2.0*StdvLogNormalFrame_GPU[pixel]));
if(CDF < breakPoint)
{
BlackAndWhiteFrame_GPU[pixel] = 0;
}
else
{
BlackAndWhiteFrame_GPU[pixel] = 1; //Can remove this if you do a memset before you use the data.
}
}
}
void errorCheck(const char *message)
{
hipError_t error;
error = hipGetLastError();
if(error != hipSuccess)
{
printf("\n CUDA ERROR: %s = %s\n", message, hipGetErrorString(error));
exit(0);
}
}
void stats()
{
hipMemcpyAsync(BlockOfLogNormalFrames_CPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME*FRAMES*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
hipMemcpyAsync(MeanFrame_CPU, MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
hipMemcpyAsync(MeanLogNormalFrame_CPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy MeanLogNormal frame down");
hipMemcpyAsync(MedianLogNormalFrame_CPU, MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy MedianLogNormal frame down");
hipMemcpyAsync(StdvLogNormalFrame_CPU, StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy StdvLogNormal frame down");
printf("\n\n");
printf("frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%d ", BlockOfFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
printf("log normal frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%f ", BlockOfLogNormalFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n", i, MeanFrame_CPU[i], i, MeanLogNormalFrame_CPU[i], i, MedianLogNormalFrame_CPU[i], i, StdvLogNormalFrame_CPU[i]);
}
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n", i, NewFrame_CPU[i], i, BlackAndWhiteFrame_CPU[i]);
}
}
void cleanUp()
{
free(BlockOfFrames_CPU);
free(NewFrame_CPU);
free(BlackAndWhiteFrame_CPU);
hipFree(BlockOfFrames_GPU);
hipFree(BlockOfLogNormalFrames_GPU);
hipFree(MeanFrame_GPU);
hipFree(MeanLogNormalFrame_GPU);
hipFree(MedianLogNormalFrame_GPU);
hipFree(StdvLogNormalFrame_GPU);
hipFree(NewFrame_GPU);
hipFree(BlackAndWhiteFrame_GPU);
// These can be removed latter. I just used them for debuging.
free(BlockOfLogNormalFrames_CPU);
free(MeanFrame_CPU);
free(MeanLogNormalFrame_CPU);
free(MedianLogNormalFrame_CPU);
free(StdvLogNormalFrame_CPU);
}
int main()
{
AllocateMemory();
SetUpCudaDevices();
loadPixels();
hipMemcpyAsync(BlockOfFrames_GPU, BlockOfFrames_CPU, PIXELS_PER_FRAME*FRAMES*sizeof(int), hipMemcpyHostToDevice);
errorCheck("copyFramessUp");
hipDeviceSynchronize();
creatingMeanPixelFrame<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanPixelFrame");
creatingLogNormalFrames<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingLogNormalFrames");
creatingMeanLogNormalFrame<<<dimGrid,dimBlock>>>(MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanLogNormalFrame");
creatingMedianLogNormalFrame<<<dimGrid,dimBlock>>>(MedianLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMedianLogNormalFrame");
creatingStdvLogNormalFrame<<<dimGrid,dimBlock>>>(StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingStdvLogNormalFrame");
hipDeviceSynchronize();
loadNewFrame();
hipMemcpyAsync(NewFrame_GPU, NewFrame_CPU, PIXELS_PER_FRAME*sizeof(int), hipMemcpyHostToDevice);
errorCheck("copy New frame up");
CreateBlackAndWHiteFrame<<<dimGrid,dimBlock>>>(BlackAndWhiteFrame_GPU, NewFrame_GPU, StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME);
errorCheck("creatingStdvLogNormalFrame");
hipMemcpyAsync(BlackAndWhiteFrame_CPU, BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy black and white frame down");
//Do stuff with black and white frame
stats();
cleanUp();
printf("\n DONE \n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // nvcc backGroundSubtractionWyatt.cu -o temp.exe -lm
#include <hip/hip_runtime.h>
#include <math.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
// size of vector
#define FRAMES 5 // Number of frames
#define PIXELS_PER_FRAME 10 // Number of pixels per frame
#define BLOCK 128 // Size of blocks, best if it is a power of 2.
// Globals
int *BlockOfFrames_CPU, *BlockOfFrames_GPU;
float *MeanFrame_GPU;
float *BlockOfLogNormalFrames_GPU;
float *MeanLogNormalFrame_GPU;
float *MedianLogNormalFrame_GPU;
float *StdvLogNormalFrame_GPU;
int *NewFrame_CPU, *NewFrame_GPU;
int *BlackAndWhiteFrame_CPU, *BlackAndWhiteFrame_GPU;
// These globals can be removed after debugging.
float *BlockOfLogNormalFrames_CPU;
float *MeanFrame_CPU;
float *MeanLogNormalFrame_CPU;
float *MedianLogNormalFrame_CPU;
float *StdvLogNormalFrame_CPU;
dim3 dimBlock, dimGrid;
void AllocateMemory()
{
// This are the set of frames that will be used to generate the log normal frame
// and the standard deviation frame
BlockOfFrames_CPU = (int *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(int));
hipMalloc((void**)&BlockOfFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(int));
hipMalloc((void**)&BlockOfLogNormalFrames_GPU,FRAMES*PIXELS_PER_FRAME*sizeof(float));
// Will hold the log normal frame and the standard deviation of the frames minus the log normal
hipMalloc((void**)&MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float));
NewFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
BlackAndWhiteFrame_CPU = (int *)malloc(PIXELS_PER_FRAME*sizeof(float));
hipMalloc((void**)&NewFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
hipMalloc((void**)&BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(int));
// These all can be removed latter. I'm just using them for debuging
BlockOfLogNormalFrames_CPU = (float *)malloc(FRAMES*PIXELS_PER_FRAME*sizeof(float));
MeanFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MeanLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
MedianLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
StdvLogNormalFrame_CPU = (float *)malloc(PIXELS_PER_FRAME*sizeof(float));
}
void loadPixels()
{
/*
However you get 300,000 by 80 pixels loaded in here then CUDA will do the rest.
This is loading the big vector from 1st 300,000 then from 2nd 300,000 and so on until frame 80.
It may be faster to load the pixels the other way 80 first pixels then 80 second pixels and so on 300000 times.
Test it and see.
I just load (below) some small values to check that everything is working.
M is the number of frames and N is the number of pixels per frame
*/
for(int i = 0; i < FRAMES; i++)
{
for(int j = 0; j < PIXELS_PER_FRAME; j++)
{
BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = i;
if(i == 4) BlockOfFrames_CPU[j +i*PIXELS_PER_FRAME] = 12;
}
}
}
void loadNewFrame()
{
//This is where you will load the image to be processed.
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
NewFrame_CPU[i] = i*2;
}
}
void SetUpCudaDevices()
{
dimBlock.x = BLOCK;
dimBlock.y = 1;
dimBlock.z = 1;
dimGrid.x = ((PIXELS_PER_FRAME - 1)/BLOCK)+1;
dimGrid.y = 1;
dimGrid.z = 1;
}
__global__ void creatingMeanPixelFrame(float *meanFrame, int *allFrames, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFrames[pixel + pixelsPerFrame*i];
}
meanFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingLogNormalFrames(float *meanFrame, int *allFrames, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int id;
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
//Same screen location (pixel) but moving through frames (i).
id = pixel + pixelsPerFrame*i;
allFramesLogNormal[id] = (float)allFrames[id] - meanFrame[pixel];
allFramesLogNormal[id] = abs(allFramesLogNormal[id]);
//Can't take log of zero so to be safe check and move it off zero.
if(allFramesLogNormal[id] == 0.0f)
{
allFramesLogNormal[id] = 0.000001f;
}
allFramesLogNormal[id] = logf(allFramesLogNormal[id]);
//allFramesLogNormal[id] = (float)allFrames[id]; // Remove after debugging.
}
}
}
__global__ void creatingMeanLogNormalFrame(float *meanlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
sum += allFramesLogNormal[pixel + pixelsPerFrame*i];
}
meanlogNormalFrame[pixel] = sum/(float)frames;
}
}
__global__ void creatingMedianLogNormalFrame(float *medianlogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
int used[FRAMES], index, count;
float median = 0.0;
float small;
if(pixel < pixelsPerFrame)
{
for(int i = 0; i < frames; i++)
{
used[i] = 0;
}
if(frames%2 == 0)
{
int middle2 = frames/2;
int middle1 = middle2 - 1;
index = -1;
count = 0;
while(count <= middle2)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small && used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle1 || count == middle2)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
median /=2.0f;
}
else
{
int middle = frames/2;
index = -1;
count = 0;
while(count <= middle)
{
small = 10000000.0f; //Needs to be a number larger than anything you would get in a log of a pixel.
for(int i = 0; i < frames; i++)
{
if(allFramesLogNormal[pixel + pixelsPerFrame*i] < small)
{
if(used[i] == 0)
{
small = allFramesLogNormal[pixel + pixelsPerFrame*i];
index = i;
}
}
}
if(index == -1) printf("\nError no index found\n");
used[index] = 1;
if(count == middle)
{
median += allFramesLogNormal[pixel + pixelsPerFrame*index];
}
count++;
}
}
medianlogNormalFrame[pixel] = median;
}
}
__global__ void creatingStdvLogNormalFrame(float *stdvLogNormalFrame, float *meanLogNormalFrame, float *allFramesLogNormal, int pixelsPerFrame, int frames)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float temp;
if(pixel < pixelsPerFrame)
{
double sum = 0.0;
for(int i = 0; i < frames; i++)
{
temp = allFramesLogNormal[pixel + pixelsPerFrame*i] - meanLogNormalFrame[pixel];
sum += temp*temp;
}
stdvLogNormalFrame[pixel] = sqrtf((sum)/(float)(frames-1));
}
}
__global__ void CreateBlackAndWHiteFrame(int *BlackAndWhiteFrame_GPU, int *NewFrame_GPU, float *StdvLogNormalFrame_GPU, float *MeanLogNormalFrame_GPU, int pixelsPerFrame)
{
int pixel = threadIdx.x + blockIdx.x*blockDim.x;
float breakPoint = 2.0f; // ************** not sure what this value should be ??????????
if(pixel < pixelsPerFrame)
{
float CDF = 0.5f + 0.5f*erff((logf((float)NewFrame_GPU[pixel]) - MeanLogNormalFrame_GPU[pixel])/sqrtf(2.0*StdvLogNormalFrame_GPU[pixel]));
if(CDF < breakPoint)
{
BlackAndWhiteFrame_GPU[pixel] = 0;
}
else
{
BlackAndWhiteFrame_GPU[pixel] = 1; //Can remove this if you do a memset before you use the data.
}
}
}
void errorCheck(const char *message)
{
hipError_t error;
error = hipGetLastError();
if(error != hipSuccess)
{
printf("\n CUDA ERROR: %s = %s\n", message, hipGetErrorString(error));
exit(0);
}
}
void stats()
{
hipMemcpyAsync(BlockOfLogNormalFrames_CPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME*FRAMES*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
hipMemcpyAsync(MeanFrame_CPU, MeanFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy Mean frame down");
hipMemcpyAsync(MeanLogNormalFrame_CPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy MeanLogNormal frame down");
hipMemcpyAsync(MedianLogNormalFrame_CPU, MedianLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy MedianLogNormal frame down");
hipMemcpyAsync(StdvLogNormalFrame_CPU, StdvLogNormalFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy StdvLogNormal frame down");
printf("\n\n");
printf("frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%d ", BlockOfFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
printf("log normal frames");
for(int j = 0; j < FRAMES; j++)
{
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("%f ", BlockOfLogNormalFrames_CPU[i + j*PIXELS_PER_FRAME]);
}
}
printf("\n\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n", i, MeanFrame_CPU[i], i, MeanLogNormalFrame_CPU[i], i, MedianLogNormalFrame_CPU[i], i, StdvLogNormalFrame_CPU[i]);
}
printf("\n");
for(int i = 0; i < PIXELS_PER_FRAME; i++)
{
printf("NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n", i, NewFrame_CPU[i], i, BlackAndWhiteFrame_CPU[i]);
}
}
void cleanUp()
{
free(BlockOfFrames_CPU);
free(NewFrame_CPU);
free(BlackAndWhiteFrame_CPU);
hipFree(BlockOfFrames_GPU);
hipFree(BlockOfLogNormalFrames_GPU);
hipFree(MeanFrame_GPU);
hipFree(MeanLogNormalFrame_GPU);
hipFree(MedianLogNormalFrame_GPU);
hipFree(StdvLogNormalFrame_GPU);
hipFree(NewFrame_GPU);
hipFree(BlackAndWhiteFrame_GPU);
// These can be removed latter. I just used them for debuging.
free(BlockOfLogNormalFrames_CPU);
free(MeanFrame_CPU);
free(MeanLogNormalFrame_CPU);
free(MedianLogNormalFrame_CPU);
free(StdvLogNormalFrame_CPU);
}
int main()
{
AllocateMemory();
SetUpCudaDevices();
loadPixels();
hipMemcpyAsync(BlockOfFrames_GPU, BlockOfFrames_CPU, PIXELS_PER_FRAME*FRAMES*sizeof(int), hipMemcpyHostToDevice);
errorCheck("copyFramessUp");
hipDeviceSynchronize();
creatingMeanPixelFrame<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanPixelFrame");
creatingLogNormalFrames<<<dimGrid,dimBlock>>>(MeanFrame_GPU, BlockOfFrames_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingLogNormalFrames");
creatingMeanLogNormalFrame<<<dimGrid,dimBlock>>>(MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMeanLogNormalFrame");
creatingMedianLogNormalFrame<<<dimGrid,dimBlock>>>(MedianLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingMedianLogNormalFrame");
creatingStdvLogNormalFrame<<<dimGrid,dimBlock>>>(StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, BlockOfLogNormalFrames_GPU, PIXELS_PER_FRAME, FRAMES);
errorCheck("creatingStdvLogNormalFrame");
hipDeviceSynchronize();
loadNewFrame();
hipMemcpyAsync(NewFrame_GPU, NewFrame_CPU, PIXELS_PER_FRAME*sizeof(int), hipMemcpyHostToDevice);
errorCheck("copy New frame up");
CreateBlackAndWHiteFrame<<<dimGrid,dimBlock>>>(BlackAndWhiteFrame_GPU, NewFrame_GPU, StdvLogNormalFrame_GPU, MeanLogNormalFrame_GPU, PIXELS_PER_FRAME);
errorCheck("creatingStdvLogNormalFrame");
hipMemcpyAsync(BlackAndWhiteFrame_CPU, BlackAndWhiteFrame_GPU, PIXELS_PER_FRAME*sizeof(float), hipMemcpyDeviceToHost);
errorCheck("copy black and white frame down");
//Do stuff with black and white frame
stats();
cleanUp();
printf("\n DONE \n");
} | .text
.file "backGroundSubtractionWyatt.hip"
.globl _Z14AllocateMemoryv # -- Begin function _Z14AllocateMemoryv
.p2align 4, 0x90
.type _Z14AllocateMemoryv,@function
_Z14AllocateMemoryv: # @_Z14AllocateMemoryv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $200, %edi
callq malloc
movq %rax, BlockOfFrames_CPU(%rip)
movl $BlockOfFrames_GPU, %edi
movl $200, %esi
callq hipMalloc
movl $BlockOfLogNormalFrames_GPU, %edi
movl $200, %esi
callq hipMalloc
movl $MeanFrame_GPU, %edi
movl $40, %esi
callq hipMalloc
movl $MeanLogNormalFrame_GPU, %edi
movl $40, %esi
callq hipMalloc
movl $MedianLogNormalFrame_GPU, %edi
movl $40, %esi
callq hipMalloc
movl $StdvLogNormalFrame_GPU, %edi
movl $40, %esi
callq hipMalloc
movl $40, %edi
callq malloc
movq %rax, NewFrame_CPU(%rip)
movl $40, %edi
callq malloc
movq %rax, BlackAndWhiteFrame_CPU(%rip)
movl $NewFrame_GPU, %edi
movl $40, %esi
callq hipMalloc
movl $BlackAndWhiteFrame_GPU, %edi
movl $40, %esi
callq hipMalloc
movl $200, %edi
callq malloc
movq %rax, BlockOfLogNormalFrames_CPU(%rip)
movl $40, %edi
callq malloc
movq %rax, MeanFrame_CPU(%rip)
movl $40, %edi
callq malloc
movq %rax, MeanLogNormalFrame_CPU(%rip)
movl $40, %edi
callq malloc
movq %rax, MedianLogNormalFrame_CPU(%rip)
movl $40, %edi
callq malloc
movq %rax, StdvLogNormalFrame_CPU(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z14AllocateMemoryv, .Lfunc_end0-_Z14AllocateMemoryv
.cfi_endproc
# -- End function
.globl _Z10loadPixelsv # -- Begin function _Z10loadPixelsv
.p2align 4, 0x90
.type _Z10loadPixelsv,@function
_Z10loadPixelsv: # @_Z10loadPixelsv
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movl $12, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
cmpq $4, %rdx
movl %edx, %esi
cmovel %ecx, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movq BlockOfFrames_CPU(%rip), %r8
addq %rax, %r8
movl %esi, (%r8,%rdi,4)
incq %rdi
cmpq $10, %rdi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rdx
addq $40, %rax
cmpq $5, %rdx
jne .LBB1_1
# %bb.4:
retq
.Lfunc_end1:
.size _Z10loadPixelsv, .Lfunc_end1-_Z10loadPixelsv
.cfi_endproc
# -- End function
.globl _Z12loadNewFramev # -- Begin function _Z12loadNewFramev
.p2align 4, 0x90
.type _Z12loadNewFramev,@function
_Z12loadNewFramev: # @_Z12loadNewFramev
.cfi_startproc
# %bb.0:
movq NewFrame_CPU(%rip), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rax,%rcx,2)
addq $2, %rcx
cmpq $20, %rcx
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z12loadNewFramev, .Lfunc_end2-_Z12loadNewFramev
.cfi_endproc
# -- End function
.globl _Z16SetUpCudaDevicesv # -- Begin function _Z16SetUpCudaDevicesv
.p2align 4, 0x90
.type _Z16SetUpCudaDevicesv,@function
_Z16SetUpCudaDevicesv: # @_Z16SetUpCudaDevicesv
.cfi_startproc
# %bb.0:
movabsq $4294967424, %rax # imm = 0x100000080
movq %rax, dimBlock(%rip)
movl $1, dimBlock+8(%rip)
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, dimGrid(%rip)
movl $1, dimGrid+8(%rip)
retq
.Lfunc_end3:
.size _Z16SetUpCudaDevicesv, .Lfunc_end3-_Z16SetUpCudaDevicesv
.cfi_endproc
# -- End function
.globl _Z37__device_stub__creatingMeanPixelFramePfPiii # -- Begin function _Z37__device_stub__creatingMeanPixelFramePfPiii
.p2align 4, 0x90
.type _Z37__device_stub__creatingMeanPixelFramePfPiii,@function
_Z37__device_stub__creatingMeanPixelFramePfPiii: # @_Z37__device_stub__creatingMeanPixelFramePfPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22creatingMeanPixelFramePfPiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z37__device_stub__creatingMeanPixelFramePfPiii, .Lfunc_end4-_Z37__device_stub__creatingMeanPixelFramePfPiii
.cfi_endproc
# -- End function
.globl _Z38__device_stub__creatingLogNormalFramesPfPiS_ii # -- Begin function _Z38__device_stub__creatingLogNormalFramesPfPiS_ii
.p2align 4, 0x90
.type _Z38__device_stub__creatingLogNormalFramesPfPiS_ii,@function
_Z38__device_stub__creatingLogNormalFramesPfPiS_ii: # @_Z38__device_stub__creatingLogNormalFramesPfPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23creatingLogNormalFramesPfPiS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z38__device_stub__creatingLogNormalFramesPfPiS_ii, .Lfunc_end5-_Z38__device_stub__creatingLogNormalFramesPfPiS_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__creatingMeanLogNormalFramePfS_ii # -- Begin function _Z41__device_stub__creatingMeanLogNormalFramePfS_ii
.p2align 4, 0x90
.type _Z41__device_stub__creatingMeanLogNormalFramePfS_ii,@function
_Z41__device_stub__creatingMeanLogNormalFramePfS_ii: # @_Z41__device_stub__creatingMeanLogNormalFramePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26creatingMeanLogNormalFramePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z41__device_stub__creatingMeanLogNormalFramePfS_ii, .Lfunc_end6-_Z41__device_stub__creatingMeanLogNormalFramePfS_ii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__creatingMedianLogNormalFramePfS_ii # -- Begin function _Z43__device_stub__creatingMedianLogNormalFramePfS_ii
.p2align 4, 0x90
.type _Z43__device_stub__creatingMedianLogNormalFramePfS_ii,@function
_Z43__device_stub__creatingMedianLogNormalFramePfS_ii: # @_Z43__device_stub__creatingMedianLogNormalFramePfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28creatingMedianLogNormalFramePfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z43__device_stub__creatingMedianLogNormalFramePfS_ii, .Lfunc_end7-_Z43__device_stub__creatingMedianLogNormalFramePfS_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii # -- Begin function _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
.p2align 4, 0x90
.type _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii,@function
_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii: # @_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26creatingStdvLogNormalFramePfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii, .Lfunc_end8-_Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i # -- Begin function _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
.p2align 4, 0x90
.type _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i,@function
_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i: # @_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24CreateBlackAndWHiteFramePiS_PfS0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end9:
.size _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i, .Lfunc_end9-_Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
.cfi_endproc
# -- End function
.globl _Z10errorCheckPKc # -- Begin function _Z10errorCheckPKc
.p2align 4, 0x90
.type _Z10errorCheckPKc,@function
_Z10errorCheckPKc: # @_Z10errorCheckPKc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rbx, %rsi
movq %rax, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end10:
.size _Z10errorCheckPKc, .Lfunc_end10-_Z10errorCheckPKc
.cfi_endproc
# -- End function
.globl _Z5statsv # -- Begin function _Z5statsv
.p2align 4, 0x90
.type _Z5statsv,@function
_Z5statsv: # @_Z5statsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq BlockOfLogNormalFrames_CPU(%rip), %rdi
movq BlockOfLogNormalFrames_GPU(%rip), %rsi
movl $200, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB11_1
# %bb.3: # %_Z10errorCheckPKc.exit
movq MeanFrame_CPU(%rip), %rdi
movq MeanFrame_GPU(%rip), %rsi
movl $40, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB11_1
# %bb.4: # %_Z10errorCheckPKc.exit38
movq MeanLogNormalFrame_CPU(%rip), %rdi
movq MeanLogNormalFrame_GPU(%rip), %rsi
movl $40, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB11_5
# %bb.6: # %_Z10errorCheckPKc.exit40
movq MedianLogNormalFrame_CPU(%rip), %rdi
movq MedianLogNormalFrame_GPU(%rip), %rsi
movl $40, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB11_7
# %bb.8: # %_Z10errorCheckPKc.exit42
movq StdvLogNormalFrame_CPU(%rip), %rdi
movq StdvLogNormalFrame_GPU(%rip), %rsi
movl $40, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB11_9
# %bb.10: # %_Z10errorCheckPKc.exit44
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB11_11: # =>This Loop Header: Depth=1
# Child Loop BB11_12 Depth 2
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB11_12: # Parent Loop BB11_11 Depth=1
# => This Inner Loop Header: Depth=2
movq BlockOfFrames_CPU(%rip), %rax
addq %rbx, %rax
movl (%rax,%r15,4), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB11_12
# %bb.13: # in Loop: Header=BB11_11 Depth=1
incq %r14
addq $40, %rbx
cmpq $5, %r14
jne .LBB11_11
# %bb.14:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB11_15: # =>This Loop Header: Depth=1
# Child Loop BB11_16 Depth 2
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB11_16: # Parent Loop BB11_15 Depth=1
# => This Inner Loop Header: Depth=2
movq BlockOfLogNormalFrames_CPU(%rip), %rax
addq %rbx, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB11_16
# %bb.17: # in Loop: Header=BB11_15 Depth=1
incq %r14
addq $40, %rbx
cmpq $5, %r14
jne .LBB11_15
# %bb.18:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB11_19: # =>This Inner Loop Header: Depth=1
movq MeanFrame_CPU(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq MeanLogNormalFrame_CPU(%rip), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq MedianLogNormalFrame_CPU(%rip), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movq StdvLogNormalFrame_CPU(%rip), %rax
movss (%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
movl $.L.str.11, %edi
movl %ebx, %esi
movl %ebx, %edx
movl %ebx, %ecx
movl %ebx, %r8d
movb $4, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB11_19
# %bb.20:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB11_21: # =>This Inner Loop Header: Depth=1
movq NewFrame_CPU(%rip), %rax
movl (%rax,%rbx,4), %edx
movq BlackAndWhiteFrame_CPU(%rip), %rax
movl (%rax,%rbx,4), %r8d
movl $.L.str.12, %edi
movl %ebx, %esi
movl %ebx, %ecx
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB11_21
# %bb.22:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB11_1:
.cfi_def_cfa_offset 32
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB11_2
.LBB11_5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB11_2
.LBB11_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %esi
jmp .LBB11_2
.LBB11_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %esi
.LBB11_2:
movq %rax, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end11:
.size _Z5statsv, .Lfunc_end11-_Z5statsv
.cfi_endproc
# -- End function
.globl _Z7cleanUpv # -- Begin function _Z7cleanUpv
.p2align 4, 0x90
.type _Z7cleanUpv,@function
_Z7cleanUpv: # @_Z7cleanUpv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq BlockOfFrames_CPU(%rip), %rdi
callq free
movq NewFrame_CPU(%rip), %rdi
callq free
movq BlackAndWhiteFrame_CPU(%rip), %rdi
callq free
movq BlockOfFrames_GPU(%rip), %rdi
callq hipFree
movq BlockOfLogNormalFrames_GPU(%rip), %rdi
callq hipFree
movq MeanFrame_GPU(%rip), %rdi
callq hipFree
movq MeanLogNormalFrame_GPU(%rip), %rdi
callq hipFree
movq MedianLogNormalFrame_GPU(%rip), %rdi
callq hipFree
movq StdvLogNormalFrame_GPU(%rip), %rdi
callq hipFree
movq NewFrame_GPU(%rip), %rdi
callq hipFree
movq BlackAndWhiteFrame_GPU(%rip), %rdi
callq hipFree
movq BlockOfLogNormalFrames_CPU(%rip), %rdi
callq free
movq MeanFrame_CPU(%rip), %rdi
callq free
movq MeanLogNormalFrame_CPU(%rip), %rdi
callq free
movq MedianLogNormalFrame_CPU(%rip), %rdi
callq free
movq StdvLogNormalFrame_CPU(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end12:
.size _Z7cleanUpv, .Lfunc_end12-_Z7cleanUpv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
callq _Z14AllocateMemoryv
movabsq $4294967424, %rax # imm = 0x100000080
movq %rax, dimBlock(%rip)
movl $1, dimBlock+8(%rip)
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, dimGrid(%rip)
movl $1, dimGrid+8(%rip)
xorl %eax, %eax
movl $12, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB13_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB13_2 Depth 2
cmpq $4, %rdx
movl %edx, %esi
cmovel %ecx, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB13_2: # Parent Loop BB13_1 Depth=1
# => This Inner Loop Header: Depth=2
movq BlockOfFrames_CPU(%rip), %r8
addq %rax, %r8
movl %esi, (%r8,%rdi,4)
incq %rdi
cmpq $10, %rdi
jne .LBB13_2
# %bb.3: # in Loop: Header=BB13_1 Depth=1
incq %rdx
addq $40, %rax
cmpq $5, %rdx
jne .LBB13_1
# %bb.4: # %_Z10loadPixelsv.exit
movq BlockOfFrames_GPU(%rip), %rdi
movq BlockOfFrames_CPU(%rip), %rsi
movl $200, %edx
movl $1, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB13_5
# %bb.7: # %_Z10errorCheckPKc.exit
callq hipDeviceSynchronize
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_9
# %bb.8:
movq MeanFrame_GPU(%rip), %rax
movq BlockOfFrames_GPU(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $10, 16(%rsp)
movl $5, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22creatingMeanPixelFramePfPiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_9:
callq hipGetLastError
testl %eax, %eax
jne .LBB13_10
# %bb.11: # %_Z10errorCheckPKc.exit53
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_13
# %bb.12:
movq MeanFrame_GPU(%rip), %rax
movq BlockOfFrames_GPU(%rip), %rcx
movq BlockOfLogNormalFrames_GPU(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $10, 8(%rsp)
movl $5, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23creatingLogNormalFramesPfPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_13:
callq hipGetLastError
testl %eax, %eax
jne .LBB13_14
# %bb.15: # %_Z10errorCheckPKc.exit61
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_17
# %bb.16:
movq MeanLogNormalFrame_GPU(%rip), %rax
movq BlockOfLogNormalFrames_GPU(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $10, 16(%rsp)
movl $5, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26creatingMeanLogNormalFramePfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_17:
callq hipGetLastError
testl %eax, %eax
jne .LBB13_18
# %bb.19: # %_Z10errorCheckPKc.exit69
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_21
# %bb.20:
movq MedianLogNormalFrame_GPU(%rip), %rax
movq BlockOfLogNormalFrames_GPU(%rip), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $10, 16(%rsp)
movl $5, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28creatingMedianLogNormalFramePfS_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_21:
callq hipGetLastError
testl %eax, %eax
jne .LBB13_22
# %bb.23: # %_Z10errorCheckPKc.exit77
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_25
# %bb.24:
movq StdvLogNormalFrame_GPU(%rip), %rax
movq MeanLogNormalFrame_GPU(%rip), %rcx
movq BlockOfLogNormalFrames_GPU(%rip), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $10, 8(%rsp)
movl $5, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26creatingStdvLogNormalFramePfS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_25:
callq hipGetLastError
testl %eax, %eax
jne .LBB13_26
# %bb.27: # %_Z10errorCheckPKc.exit85
callq hipDeviceSynchronize
xorl %eax, %eax
movq NewFrame_CPU(%rip), %rsi
.p2align 4, 0x90
.LBB13_28: # =>This Inner Loop Header: Depth=1
movl %eax, (%rsi,%rax,2)
addq $2, %rax
cmpq $20, %rax
jne .LBB13_28
# %bb.29: # %_Z12loadNewFramev.exit
movq NewFrame_GPU(%rip), %rdi
movl $40, %edx
movl $1, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB13_30
# %bb.31: # %_Z10errorCheckPKc.exit90
movq dimGrid(%rip), %rdi
movl dimGrid+8(%rip), %esi
movq dimBlock(%rip), %rdx
movl dimBlock+8(%rip), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB13_33
# %bb.32:
movq BlackAndWhiteFrame_GPU(%rip), %rax
movq NewFrame_GPU(%rip), %rcx
movq StdvLogNormalFrame_GPU(%rip), %rdx
movq MeanLogNormalFrame_GPU(%rip), %rsi
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rsi, 56(%rsp)
movl $10, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24CreateBlackAndWHiteFramePiS_PfS0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB13_33:
callq hipGetLastError
testl %eax, %eax
jne .LBB13_26
# %bb.34: # %_Z10errorCheckPKc.exit98
movq BlackAndWhiteFrame_CPU(%rip), %rdi
movq BlackAndWhiteFrame_GPU(%rip), %rsi
movl $40, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
callq hipGetLastError
testl %eax, %eax
jne .LBB13_35
# %bb.36: # %_Z10errorCheckPKc.exit100
callq _Z5statsv
callq _Z7cleanUpv
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.LBB13_26:
.cfi_def_cfa_offset 144
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.18, %esi
jmp .LBB13_6
.LBB13_5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.13, %esi
jmp .LBB13_6
.LBB13_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.14, %esi
jmp .LBB13_6
.LBB13_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.15, %esi
jmp .LBB13_6
.LBB13_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.16, %esi
jmp .LBB13_6
.LBB13_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.17, %esi
jmp .LBB13_6
.LBB13_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.19, %esi
jmp .LBB13_6
.LBB13_35:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.20, %esi
.LBB13_6:
movq %rax, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end13:
.size main, .Lfunc_end13-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22creatingMeanPixelFramePfPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23creatingLogNormalFramesPfPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26creatingMeanLogNormalFramePfS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28creatingMedianLogNormalFramePfS_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26creatingStdvLogNormalFramePfS_S_ii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24CreateBlackAndWHiteFramePiS_PfS0_i, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type BlockOfFrames_CPU,@object # @BlockOfFrames_CPU
.bss
.globl BlockOfFrames_CPU
.p2align 3, 0x0
BlockOfFrames_CPU:
.quad 0
.size BlockOfFrames_CPU, 8
.type BlockOfFrames_GPU,@object # @BlockOfFrames_GPU
.globl BlockOfFrames_GPU
.p2align 3, 0x0
BlockOfFrames_GPU:
.quad 0
.size BlockOfFrames_GPU, 8
.type MeanFrame_GPU,@object # @MeanFrame_GPU
.globl MeanFrame_GPU
.p2align 3, 0x0
MeanFrame_GPU:
.quad 0
.size MeanFrame_GPU, 8
.type BlockOfLogNormalFrames_GPU,@object # @BlockOfLogNormalFrames_GPU
.globl BlockOfLogNormalFrames_GPU
.p2align 3, 0x0
BlockOfLogNormalFrames_GPU:
.quad 0
.size BlockOfLogNormalFrames_GPU, 8
.type MeanLogNormalFrame_GPU,@object # @MeanLogNormalFrame_GPU
.globl MeanLogNormalFrame_GPU
.p2align 3, 0x0
MeanLogNormalFrame_GPU:
.quad 0
.size MeanLogNormalFrame_GPU, 8
.type MedianLogNormalFrame_GPU,@object # @MedianLogNormalFrame_GPU
.globl MedianLogNormalFrame_GPU
.p2align 3, 0x0
MedianLogNormalFrame_GPU:
.quad 0
.size MedianLogNormalFrame_GPU, 8
.type StdvLogNormalFrame_GPU,@object # @StdvLogNormalFrame_GPU
.globl StdvLogNormalFrame_GPU
.p2align 3, 0x0
StdvLogNormalFrame_GPU:
.quad 0
.size StdvLogNormalFrame_GPU, 8
.type NewFrame_CPU,@object # @NewFrame_CPU
.globl NewFrame_CPU
.p2align 3, 0x0
NewFrame_CPU:
.quad 0
.size NewFrame_CPU, 8
.type NewFrame_GPU,@object # @NewFrame_GPU
.globl NewFrame_GPU
.p2align 3, 0x0
NewFrame_GPU:
.quad 0
.size NewFrame_GPU, 8
.type BlackAndWhiteFrame_CPU,@object # @BlackAndWhiteFrame_CPU
.globl BlackAndWhiteFrame_CPU
.p2align 3, 0x0
BlackAndWhiteFrame_CPU:
.quad 0
.size BlackAndWhiteFrame_CPU, 8
.type BlackAndWhiteFrame_GPU,@object # @BlackAndWhiteFrame_GPU
.globl BlackAndWhiteFrame_GPU
.p2align 3, 0x0
BlackAndWhiteFrame_GPU:
.quad 0
.size BlackAndWhiteFrame_GPU, 8
.type BlockOfLogNormalFrames_CPU,@object # @BlockOfLogNormalFrames_CPU
.globl BlockOfLogNormalFrames_CPU
.p2align 3, 0x0
BlockOfLogNormalFrames_CPU:
.quad 0
.size BlockOfLogNormalFrames_CPU, 8
.type MeanFrame_CPU,@object # @MeanFrame_CPU
.globl MeanFrame_CPU
.p2align 3, 0x0
MeanFrame_CPU:
.quad 0
.size MeanFrame_CPU, 8
.type MeanLogNormalFrame_CPU,@object # @MeanLogNormalFrame_CPU
.globl MeanLogNormalFrame_CPU
.p2align 3, 0x0
MeanLogNormalFrame_CPU:
.quad 0
.size MeanLogNormalFrame_CPU, 8
.type MedianLogNormalFrame_CPU,@object # @MedianLogNormalFrame_CPU
.globl MedianLogNormalFrame_CPU
.p2align 3, 0x0
MedianLogNormalFrame_CPU:
.quad 0
.size MedianLogNormalFrame_CPU, 8
.type StdvLogNormalFrame_CPU,@object # @StdvLogNormalFrame_CPU
.globl StdvLogNormalFrame_CPU
.p2align 3, 0x0
StdvLogNormalFrame_CPU:
.quad 0
.size StdvLogNormalFrame_CPU, 8
.type dimBlock,@object # @dimBlock
.data
.globl dimBlock
.p2align 3, 0x0
dimBlock:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size dimBlock, 12
.type dimGrid,@object # @dimGrid
.globl dimGrid
.p2align 3, 0x0
dimGrid:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size dimGrid, 12
.type _Z22creatingMeanPixelFramePfPiii,@object # @_Z22creatingMeanPixelFramePfPiii
.section .rodata,"a",@progbits
.globl _Z22creatingMeanPixelFramePfPiii
.p2align 3, 0x0
_Z22creatingMeanPixelFramePfPiii:
.quad _Z37__device_stub__creatingMeanPixelFramePfPiii
.size _Z22creatingMeanPixelFramePfPiii, 8
.type _Z23creatingLogNormalFramesPfPiS_ii,@object # @_Z23creatingLogNormalFramesPfPiS_ii
.globl _Z23creatingLogNormalFramesPfPiS_ii
.p2align 3, 0x0
_Z23creatingLogNormalFramesPfPiS_ii:
.quad _Z38__device_stub__creatingLogNormalFramesPfPiS_ii
.size _Z23creatingLogNormalFramesPfPiS_ii, 8
.type _Z26creatingMeanLogNormalFramePfS_ii,@object # @_Z26creatingMeanLogNormalFramePfS_ii
.globl _Z26creatingMeanLogNormalFramePfS_ii
.p2align 3, 0x0
_Z26creatingMeanLogNormalFramePfS_ii:
.quad _Z41__device_stub__creatingMeanLogNormalFramePfS_ii
.size _Z26creatingMeanLogNormalFramePfS_ii, 8
.type _Z28creatingMedianLogNormalFramePfS_ii,@object # @_Z28creatingMedianLogNormalFramePfS_ii
.globl _Z28creatingMedianLogNormalFramePfS_ii
.p2align 3, 0x0
_Z28creatingMedianLogNormalFramePfS_ii:
.quad _Z43__device_stub__creatingMedianLogNormalFramePfS_ii
.size _Z28creatingMedianLogNormalFramePfS_ii, 8
.type _Z26creatingStdvLogNormalFramePfS_S_ii,@object # @_Z26creatingStdvLogNormalFramePfS_S_ii
.globl _Z26creatingStdvLogNormalFramePfS_S_ii
.p2align 3, 0x0
_Z26creatingStdvLogNormalFramePfS_S_ii:
.quad _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
.size _Z26creatingStdvLogNormalFramePfS_S_ii, 8
.type _Z24CreateBlackAndWHiteFramePiS_PfS0_i,@object # @_Z24CreateBlackAndWHiteFramePiS_PfS0_i
.globl _Z24CreateBlackAndWHiteFramePiS_PfS0_i
.p2align 3, 0x0
_Z24CreateBlackAndWHiteFramePiS_PfS0_i:
.quad _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
.size _Z24CreateBlackAndWHiteFramePiS_PfS0_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n CUDA ERROR: %s = %s\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "copy Mean frame down"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "copy MeanLogNormal frame down"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "copy MedianLogNormal frame down"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "copy StdvLogNormal frame down"
.size .L.str.4, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "frames"
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d "
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "log normal frames"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f "
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "MeanFrame[%d] = %f MeanLogNormalFrame[%d] = %f MedianLogNormalFrame[%d] = %f StdvLogNormalFrame[%d] = %f \n"
.size .L.str.11, 107
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "NewFrame[%d] = %d blackAndWhiteFrame[%d] = %d \n"
.size .L.str.12, 48
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "copyFramessUp"
.size .L.str.13, 14
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "creatingMeanPixelFrame"
.size .L.str.14, 23
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "creatingLogNormalFrames"
.size .L.str.15, 24
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "creatingMeanLogNormalFrame"
.size .L.str.16, 27
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "creatingMedianLogNormalFrame"
.size .L.str.17, 29
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "creatingStdvLogNormalFrame"
.size .L.str.18, 27
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "copy New frame up"
.size .L.str.19, 18
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "copy black and white frame down"
.size .L.str.20, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22creatingMeanPixelFramePfPiii"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23creatingLogNormalFramesPfPiS_ii"
.size .L__unnamed_2, 36
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26creatingMeanLogNormalFramePfS_ii"
.size .L__unnamed_3, 37
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z28creatingMedianLogNormalFramePfS_ii"
.size .L__unnamed_4, 39
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z26creatingStdvLogNormalFramePfS_S_ii"
.size .L__unnamed_5, 39
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z24CreateBlackAndWHiteFramePiS_PfS0_i"
.size .L__unnamed_6, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "\n"
.size .Lstr.2, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n DONE "
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__creatingMeanPixelFramePfPiii
.addrsig_sym _Z38__device_stub__creatingLogNormalFramesPfPiS_ii
.addrsig_sym _Z41__device_stub__creatingMeanLogNormalFramePfS_ii
.addrsig_sym _Z43__device_stub__creatingMedianLogNormalFramePfS_ii
.addrsig_sym _Z41__device_stub__creatingStdvLogNormalFramePfS_S_ii
.addrsig_sym _Z39__device_stub__CreateBlackAndWHiteFramePiS_PfS0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym BlockOfFrames_GPU
.addrsig_sym MeanFrame_GPU
.addrsig_sym BlockOfLogNormalFrames_GPU
.addrsig_sym MeanLogNormalFrame_GPU
.addrsig_sym MedianLogNormalFrame_GPU
.addrsig_sym StdvLogNormalFrame_GPU
.addrsig_sym NewFrame_GPU
.addrsig_sym BlackAndWhiteFrame_GPU
.addrsig_sym _Z22creatingMeanPixelFramePfPiii
.addrsig_sym _Z23creatingLogNormalFramesPfPiS_ii
.addrsig_sym _Z26creatingMeanLogNormalFramePfS_ii
.addrsig_sym _Z28creatingMedianLogNormalFramePfS_ii
.addrsig_sym _Z26creatingStdvLogNormalFramePfS_S_ii
.addrsig_sym _Z24CreateBlackAndWHiteFramePiS_PfS0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>
using namespace std;
__global__ void smallSimplex(double* job, int width, int height)
{
extern __shared__ double shared[];
double* pivotColumn = &shared[0];
double* pivotRow = &shared[height];
double* ratioColumn = &shared[width];
__shared__ double smallestObj;
__shared__ int pivotColIndx;
__shared__ int pivotRowIndx;
smallestObj = 10^20;
int index = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while(true)
{
// STEP 1
if(threadIdx.x == 0)
{
for(int i = 0; i < width; i++)
{
if(smallestObj > job[(height-1)*width+i])
{
smallestObj = job[(height-1)*width+i];
pivotColIndx = i;
}
}
}
__syncthreads();
if(smallestObj >= 0){break;}
// printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);
for(int i = index; i < height; i+=stride)
{
pivotColumn[i] = job[pivotColIndx + i*width];
ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
}
// printf("The ratio column is:\n");
// for(int i = 0; i < height; i++)
// {
// printf("%f\n",ratioColumn[i]);
// }
// STEP 2
smallestObj = 10^20;
if(threadIdx.x == 0)
{
for(int i = 0; i < height-1; i++)
{
if(smallestObj > ratioColumn[i])
{
smallestObj = ratioColumn[i];
pivotRowIndx = i;
}
}
}
__syncthreads();
// printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
for(int i = index; i < width; i+=stride)
{
job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
pivotRow[i] = job[width*pivotRowIndx + i];
}
// STEP 3
for (int i = index; i < height; i+= stride)
{
if(i == pivotRowIndx){continue;}
for (int j = 0; j < width; j++)
{
job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
}
}
}
}
int main(int argc, char const *argv[])
{
double* simplexTable;
cudaMallocManaged(&simplexTable, sizeof(double)*18);
// simplexTable[0] = 3.;
// simplexTable[1] = 4.;
// simplexTable[2] = 1.;
// simplexTable[3] = 0.;
// simplexTable[4] = 0.;
// simplexTable[5] = 24.;
//
// simplexTable[6] = 7.;
// simplexTable[7] = -4.;
// simplexTable[8] = 0.;
// simplexTable[9] = 1.;
// simplexTable[10] = 0.;
// simplexTable[11] = 16.;
//
// simplexTable[12] = -2.;
// simplexTable[13] = 3.;
// simplexTable[14] = 0.;
// simplexTable[15] = 0.;
// simplexTable[16] = 1.;
// simplexTable[17] = 0.;
simplexTable[0] = 10.;
simplexTable[1] = 7.;
simplexTable[2] = 1.;
simplexTable[3] = 0.;
simplexTable[4] = 0.;
simplexTable[5] = 40.;
simplexTable[6] = 1.;
simplexTable[7] = 1.;
simplexTable[8] = 0.;
simplexTable[9] = 1.;
simplexTable[10] = 0.;
simplexTable[11] = 5.;
simplexTable[12] = -17.;
simplexTable[13] = -12.;
simplexTable[14] = 0.;
simplexTable[15] = 0.;
simplexTable[16] = 1.;
simplexTable[17] = 0.;
int height = 3;
int width = 6;
int sharedMemory = sizeof(double)*(height*2 + width);
smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
cudaDeviceSynchronize();
for(int i = 0; i <18; i++)
{
cout<<simplexTable[i]<<" "<<"|"<<" ";
if(i%6 == 5){cout<<endl;}
}
return 0;
} | .file "tmpxft_00122426_00000000-6_testSmallSimplex.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3886:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12smallSimplexPdiiPdii
.type _Z34__device_stub__Z12smallSimplexPdiiPdii, @function
_Z34__device_stub__Z12smallSimplexPdiiPdii:
.LFB3908:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12smallSimplexPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3908:
.size _Z34__device_stub__Z12smallSimplexPdiiPdii, .-_Z34__device_stub__Z12smallSimplexPdiiPdii
.globl _Z12smallSimplexPdii
.type _Z12smallSimplexPdii, @function
_Z12smallSimplexPdii:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12smallSimplexPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _Z12smallSimplexPdii, .-_Z12smallSimplexPdii
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string " "
.LC9:
.string "|"
.text
.globl main
.type main, @function
main:
.LFB3883:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $144, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
movq .LC0(%rip), %rcx
movq %rcx, (%rax)
movq 8(%rsp), %rax
movq .LC1(%rip), %rcx
movq %rcx, 8(%rax)
movsd .LC2(%rip), %xmm0
movsd %xmm0, 16(%rax)
movq $0x000000000, 24(%rax)
movq $0x000000000, 32(%rax)
movq .LC4(%rip), %rcx
movq %rcx, 40(%rax)
movsd %xmm0, 48(%rax)
movsd %xmm0, 56(%rax)
movq $0x000000000, 64(%rax)
movsd %xmm0, 72(%rax)
movq $0x000000000, 80(%rax)
movq .LC5(%rip), %rcx
movq %rcx, 88(%rax)
movq .LC6(%rip), %rcx
movq %rcx, 96(%rax)
movq .LC7(%rip), %rcx
movq %rcx, 104(%rax)
movq $0x000000000, 112(%rax)
movq $0x000000000, 120(%rax)
movsd %xmm0, 128(%rax)
movq $0x000000000, 136(%rax)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $96, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
leaq .LC8(%rip), %rbp
leaq .LC9(%rip), %r13
jmp .L18
.L22:
movl $3, %edx
movl $6, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12smallSimplexPdiiPdii
jmp .L12
.L25:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
call _ZSt16__throw_bad_castv@PLT
.L23:
call __stack_chk_fail@PLT
.L26:
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L13:
addq $1, %rbx
cmpq $18, %rbx
je .L24
.L18:
movq 8(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %r13, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %rbp, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movslq %ebx, %rax
imulq $715827883, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $5, %edx
jne .L13
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L25
cmpb $0, 56(%r14)
jne .L26
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3883:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12smallSimplexPdii"
.LC11:
.string "precalc_xorwow_matrix"
.LC12:
.string "precalc_xorwow_offset_matrix"
.LC13:
.string "mrg32k3aM1"
.LC14:
.string "mrg32k3aM2"
.LC15:
.string "mrg32k3aM1SubSeq"
.LC16:
.string "mrg32k3aM2SubSeq"
.LC17:
.string "mrg32k3aM1Seq"
.LC18:
.string "mrg32k3aM2Seq"
.LC19:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3911:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12smallSimplexPdii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3911:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1076101120
.align 8
.LC1:
.long 0
.long 1075576832
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long 1078198272
.align 8
.LC5:
.long 0
.long 1075052544
.align 8
.LC6:
.long 0
.long -1070530560
.align 8
.LC7:
.long 0
.long -1071120384
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>
using namespace std;
__global__ void smallSimplex(double* job, int width, int height)
{
extern __shared__ double shared[];
double* pivotColumn = &shared[0];
double* pivotRow = &shared[height];
double* ratioColumn = &shared[width];
__shared__ double smallestObj;
__shared__ int pivotColIndx;
__shared__ int pivotRowIndx;
smallestObj = 10^20;
int index = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while(true)
{
// STEP 1
if(threadIdx.x == 0)
{
for(int i = 0; i < width; i++)
{
if(smallestObj > job[(height-1)*width+i])
{
smallestObj = job[(height-1)*width+i];
pivotColIndx = i;
}
}
}
__syncthreads();
if(smallestObj >= 0){break;}
// printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);
for(int i = index; i < height; i+=stride)
{
pivotColumn[i] = job[pivotColIndx + i*width];
ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
}
// printf("The ratio column is:\n");
// for(int i = 0; i < height; i++)
// {
// printf("%f\n",ratioColumn[i]);
// }
// STEP 2
smallestObj = 10^20;
if(threadIdx.x == 0)
{
for(int i = 0; i < height-1; i++)
{
if(smallestObj > ratioColumn[i])
{
smallestObj = ratioColumn[i];
pivotRowIndx = i;
}
}
}
__syncthreads();
// printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
for(int i = index; i < width; i+=stride)
{
job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
pivotRow[i] = job[width*pivotRowIndx + i];
}
// STEP 3
for (int i = index; i < height; i+= stride)
{
if(i == pivotRowIndx){continue;}
for (int j = 0; j < width; j++)
{
job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
}
}
}
}
int main(int argc, char const *argv[])
{
double* simplexTable;
cudaMallocManaged(&simplexTable, sizeof(double)*18);
// simplexTable[0] = 3.;
// simplexTable[1] = 4.;
// simplexTable[2] = 1.;
// simplexTable[3] = 0.;
// simplexTable[4] = 0.;
// simplexTable[5] = 24.;
//
// simplexTable[6] = 7.;
// simplexTable[7] = -4.;
// simplexTable[8] = 0.;
// simplexTable[9] = 1.;
// simplexTable[10] = 0.;
// simplexTable[11] = 16.;
//
// simplexTable[12] = -2.;
// simplexTable[13] = 3.;
// simplexTable[14] = 0.;
// simplexTable[15] = 0.;
// simplexTable[16] = 1.;
// simplexTable[17] = 0.;
simplexTable[0] = 10.;
simplexTable[1] = 7.;
simplexTable[2] = 1.;
simplexTable[3] = 0.;
simplexTable[4] = 0.;
simplexTable[5] = 40.;
simplexTable[6] = 1.;
simplexTable[7] = 1.;
simplexTable[8] = 0.;
simplexTable[9] = 1.;
simplexTable[10] = 0.;
simplexTable[11] = 5.;
simplexTable[12] = -17.;
simplexTable[13] = -12.;
simplexTable[14] = 0.;
simplexTable[15] = 0.;
simplexTable[16] = 1.;
simplexTable[17] = 0.;
int height = 3;
int width = 6;
int sharedMemory = sizeof(double)*(height*2 + width);
smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
cudaDeviceSynchronize();
for(int i = 0; i <18; i++)
{
cout<<simplexTable[i]<<" "<<"|"<<" ";
if(i%6 == 5){cout<<endl;}
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
using namespace std;
__global__ void smallSimplex(double* job, int width, int height)
{
extern __shared__ double shared[];
double* pivotColumn = &shared[0];
double* pivotRow = &shared[height];
double* ratioColumn = &shared[width];
__shared__ double smallestObj;
__shared__ int pivotColIndx;
__shared__ int pivotRowIndx;
smallestObj = 10^20;
int index = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while(true)
{
// STEP 1
if(threadIdx.x == 0)
{
for(int i = 0; i < width; i++)
{
if(smallestObj > job[(height-1)*width+i])
{
smallestObj = job[(height-1)*width+i];
pivotColIndx = i;
}
}
}
__syncthreads();
if(smallestObj >= 0){break;}
// printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);
for(int i = index; i < height; i+=stride)
{
pivotColumn[i] = job[pivotColIndx + i*width];
ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
}
// printf("The ratio column is:\n");
// for(int i = 0; i < height; i++)
// {
// printf("%f\n",ratioColumn[i]);
// }
// STEP 2
smallestObj = 10^20;
if(threadIdx.x == 0)
{
for(int i = 0; i < height-1; i++)
{
if(smallestObj > ratioColumn[i])
{
smallestObj = ratioColumn[i];
pivotRowIndx = i;
}
}
}
__syncthreads();
// printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
for(int i = index; i < width; i+=stride)
{
job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
pivotRow[i] = job[width*pivotRowIndx + i];
}
// STEP 3
for (int i = index; i < height; i+= stride)
{
if(i == pivotRowIndx){continue;}
for (int j = 0; j < width; j++)
{
job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
}
}
}
}
int main(int argc, char const *argv[])
{
double* simplexTable;
hipMallocManaged(&simplexTable, sizeof(double)*18);
// simplexTable[0] = 3.;
// simplexTable[1] = 4.;
// simplexTable[2] = 1.;
// simplexTable[3] = 0.;
// simplexTable[4] = 0.;
// simplexTable[5] = 24.;
//
// simplexTable[6] = 7.;
// simplexTable[7] = -4.;
// simplexTable[8] = 0.;
// simplexTable[9] = 1.;
// simplexTable[10] = 0.;
// simplexTable[11] = 16.;
//
// simplexTable[12] = -2.;
// simplexTable[13] = 3.;
// simplexTable[14] = 0.;
// simplexTable[15] = 0.;
// simplexTable[16] = 1.;
// simplexTable[17] = 0.;
simplexTable[0] = 10.;
simplexTable[1] = 7.;
simplexTable[2] = 1.;
simplexTable[3] = 0.;
simplexTable[4] = 0.;
simplexTable[5] = 40.;
simplexTable[6] = 1.;
simplexTable[7] = 1.;
simplexTable[8] = 0.;
simplexTable[9] = 1.;
simplexTable[10] = 0.;
simplexTable[11] = 5.;
simplexTable[12] = -17.;
simplexTable[13] = -12.;
simplexTable[14] = 0.;
simplexTable[15] = 0.;
simplexTable[16] = 1.;
simplexTable[17] = 0.;
int height = 3;
int width = 6;
int sharedMemory = sizeof(double)*(height*2 + width);
smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
hipDeviceSynchronize();
for(int i = 0; i <18; i++)
{
cout<<simplexTable[i]<<" "<<"|"<<" ";
if(i%6 == 5){cout<<endl;}
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
using namespace std;
__global__ void smallSimplex(double* job, int width, int height)
{
extern __shared__ double shared[];
double* pivotColumn = &shared[0];
double* pivotRow = &shared[height];
double* ratioColumn = &shared[width];
__shared__ double smallestObj;
__shared__ int pivotColIndx;
__shared__ int pivotRowIndx;
smallestObj = 10^20;
int index = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while(true)
{
// STEP 1
if(threadIdx.x == 0)
{
for(int i = 0; i < width; i++)
{
if(smallestObj > job[(height-1)*width+i])
{
smallestObj = job[(height-1)*width+i];
pivotColIndx = i;
}
}
}
__syncthreads();
if(smallestObj >= 0){break;}
// printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);
for(int i = index; i < height; i+=stride)
{
pivotColumn[i] = job[pivotColIndx + i*width];
ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
}
// printf("The ratio column is:\n");
// for(int i = 0; i < height; i++)
// {
// printf("%f\n",ratioColumn[i]);
// }
// STEP 2
smallestObj = 10^20;
if(threadIdx.x == 0)
{
for(int i = 0; i < height-1; i++)
{
if(smallestObj > ratioColumn[i])
{
smallestObj = ratioColumn[i];
pivotRowIndx = i;
}
}
}
__syncthreads();
// printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
for(int i = index; i < width; i+=stride)
{
job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
pivotRow[i] = job[width*pivotRowIndx + i];
}
// STEP 3
for (int i = index; i < height; i+= stride)
{
if(i == pivotRowIndx){continue;}
for (int j = 0; j < width; j++)
{
job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
}
}
}
}
int main(int argc, char const *argv[])
{
double* simplexTable;
hipMallocManaged(&simplexTable, sizeof(double)*18);
// simplexTable[0] = 3.;
// simplexTable[1] = 4.;
// simplexTable[2] = 1.;
// simplexTable[3] = 0.;
// simplexTable[4] = 0.;
// simplexTable[5] = 24.;
//
// simplexTable[6] = 7.;
// simplexTable[7] = -4.;
// simplexTable[8] = 0.;
// simplexTable[9] = 1.;
// simplexTable[10] = 0.;
// simplexTable[11] = 16.;
//
// simplexTable[12] = -2.;
// simplexTable[13] = 3.;
// simplexTable[14] = 0.;
// simplexTable[15] = 0.;
// simplexTable[16] = 1.;
// simplexTable[17] = 0.;
simplexTable[0] = 10.;
simplexTable[1] = 7.;
simplexTable[2] = 1.;
simplexTable[3] = 0.;
simplexTable[4] = 0.;
simplexTable[5] = 40.;
simplexTable[6] = 1.;
simplexTable[7] = 1.;
simplexTable[8] = 0.;
simplexTable[9] = 1.;
simplexTable[10] = 0.;
simplexTable[11] = 5.;
simplexTable[12] = -17.;
simplexTable[13] = -12.;
simplexTable[14] = 0.;
simplexTable[15] = 0.;
simplexTable[16] = 1.;
simplexTable[17] = 0.;
int height = 3;
int width = 6;
int sharedMemory = sizeof(double)*(height*2 + width);
smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
hipDeviceSynchronize();
for(int i = 0; i <18; i++)
{
cout<<simplexTable[i]<<" "<<"|"<<" ";
if(i%6 == 5){cout<<endl;}
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12smallSimplexPdii
.globl _Z12smallSimplexPdii
.p2align 8
.type _Z12smallSimplexPdii,@function
_Z12smallSimplexPdii:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s0, s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0x403e0000
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s1, s7, 3
s_and_b32 s2, s2, 0xffff
s_lshl_b32 s14, s6, 3
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_add_i32 s16, s1, 16
s_add_i32 s17, s14, 16
s_cmp_gt_i32 s6, 0
s_mul_i32 s8, s0, s2
s_cselect_b32 s3, -1, 0
s_add_i32 s18, s7, -1
s_add_u32 s19, s4, -8
s_addc_u32 s20, s5, -1
s_cmp_gt_i32 s7, 1
v_mul_lo_u32 v0, s6, v3
s_mul_i32 s2, s18, s6
s_cselect_b32 s9, -1, 0
s_cmp_lt_i32 s6, 1
v_lshlrev_b32_e32 v4, 3, v3
s_cselect_b32 s24, -1, 0
s_and_b32 s21, vcc_lo, s3
s_ashr_i32 s3, s2, 31
s_and_b32 s22, vcc_lo, s9
s_lshl_b64 s[2:3], s[2:3], 3
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v11, 16, v4
v_cmp_gt_i32_e64 s0, s7, v3
v_cmp_gt_i32_e64 s1, s6, v3
s_add_u32 s10, s4, s2
v_add_nc_u32_e32 v12, s6, v0
v_add_nc_u32_e32 v13, s16, v4
s_addc_u32 s11, s5, s3
s_ashr_i32 s9, s8, 31
s_mul_i32 s15, s8, s6
s_lshl_b32 s23, s8, 3
s_lshl_b64 s[12:13], s[8:9], 3
s_xor_b32 s9, s24, -1
ds_store_b64 v10, v[1:2]
s_branch .LBB0_3
.LBB0_1:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s2, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_26
.LBB0_3:
s_and_saveexec_b32 s24, s21
s_cbranch_execz .LBB0_8
ds_load_b64 v[4:5], v10
s_mov_b32 s25, 0
s_mov_b64 s[2:3], s[10:11]
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_add_i32 s25, s25, 1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s6, s25
s_cbranch_scc0 .LBB0_8
.LBB0_6:
global_load_b64 v[6:7], v10, s[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f64_e32 vcc_lo, v[4:5], v[6:7]
s_cbranch_vccnz .LBB0_5
v_mov_b32_e32 v4, v6
v_dual_mov_b32 v8, s25 :: v_dual_mov_b32 v5, v7
ds_store_b64 v10, v[6:7]
ds_store_b32 v10, v8 offset:8
s_branch .LBB0_5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s24
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b64 v[4:5], v10
s_mov_b32 s2, -1
s_waitcnt lgkmcnt(0)
v_cmp_le_f64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_2
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_12
ds_load_b32 v5, v10 offset:8
v_mov_b32_e32 v4, v11
v_mov_b32_e32 v6, v3
s_mov_b32 s3, 0
s_mov_b32 s24, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v0, v5
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, s24, v5
v_add_nc_u32_e32 v14, s24, v12
v_add_nc_u32_e32 v6, s8, v6
v_add_nc_u32_e32 v9, s14, v4
s_add_i32 s24, s24, s15
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_lshlrev_b64 v[14:15], 3, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s19, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s20, v15, vcc_lo
s_clause 0x1
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[14:15], v[14:15], off
s_waitcnt vmcnt(1)
ds_store_b64 v4, v[7:8]
s_waitcnt vmcnt(0)
v_div_scale_f64 v[16:17], null, v[7:8], v[7:8], v[14:15]
v_div_scale_f64 v[22:23], vcc_lo, v[14:15], v[7:8], v[14:15]
v_add_nc_u32_e32 v4, s23, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[18:19], v[16:17]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[20:21], v[22:23], v[18:19]
v_fma_f64 v[16:17], -v[16:17], v[20:21], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[20:21]
v_cmp_le_i32_e32 vcc_lo, s7, v6
s_or_b32 s3, vcc_lo, s3
v_div_fixup_f64 v[14:15], v[16:17], v[7:8], v[14:15]
ds_store_b64 v9, v[14:15]
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
ds_store_b64 v10, v[1:2]
s_and_saveexec_b32 s2, s22
s_cbranch_execz .LBB0_17
ds_load_b64 v[4:5], v10
s_mov_b32 s3, 0
s_mov_b32 s24, s17
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_add_i32 s3, s3, 1
s_add_i32 s24, s24, 8
s_cmp_lg_u32 s18, s3
s_cbranch_scc0 .LBB0_17
.LBB0_15:
v_mov_b32_e32 v6, s24
ds_load_b64 v[6:7], v6
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f64_e32 vcc_lo, v[4:5], v[6:7]
s_cbranch_vccnz .LBB0_14
v_mov_b32_e32 v4, v6
v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v5, v7
ds_store_b64 v10, v[6:7]
ds_store_b32 v10, v8 offset:12
s_branch .LBB0_14
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_20
ds_load_b32 v6, v10 offset:12
s_mov_b32 s24, 0
v_mov_b32_e32 v8, v3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s6, v[3:4]
v_dual_mov_b32 v6, v13 :: v_dual_lshlrev_b32 v7, 3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, 16, v7
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_19:
global_load_b64 v[14:15], v[4:5], off
ds_load_b64 v[16:17], v7
v_add_nc_u32_e32 v8, s8, v8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], v[14:15]
v_div_scale_f64 v[24:25], vcc_lo, v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[20:21], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[22:23], v[24:25], v[20:21]
v_fma_f64 v[18:19], -v[18:19], v[22:23], v[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[22:23]
v_cmp_le_i32_e32 vcc_lo, s6, v8
s_or_b32 s24, vcc_lo, s24
v_div_fixup_f64 v[14:15], v[18:19], v[16:17], v[14:15]
global_store_b64 v[4:5], v[14:15], off
v_add_co_u32 v4, s2, v4, s12
ds_store_b64 v6, v[14:15]
v_add_co_ci_u32_e64 v5, s2, s13, v5, s2
v_add_nc_u32_e32 v6, s23, v6
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execnz .LBB0_19
.LBB0_20:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_1
ds_load_b32 v14, v10 offset:12
v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v15, v3
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_23
.p2align 6
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s24
v_add_nc_u32_e32 v15, s8, v15
v_add_nc_u32_e32 v4, s15, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s7, v15
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_1
.LBB0_23:
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v15, v14
s_and_b32 s25, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s24, s25
s_cbranch_execz .LBB0_22
v_lshl_add_u32 v5, v15, 3, 16
s_mov_b32 s25, s16
s_mov_b32 s26, s6
ds_load_b64 v[6:7], v5
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
.p2align 6
.LBB0_25:
global_load_b64 v[16:17], v[8:9], off
v_mov_b32_e32 v5, s25
s_add_i32 s26, s26, -1
s_add_i32 s25, s25, 8
s_cmp_lg_u32 s26, 0
ds_load_b64 v[18:19], v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[16:17], -v[6:7], v[18:19], v[16:17]
global_store_b64 v[8:9], v[16:17], off
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_cbranch_scc1 .LBB0_25
s_branch .LBB0_22
.LBB0_26:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12smallSimplexPdii
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12smallSimplexPdii, .Lfunc_end0-_Z12smallSimplexPdii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12smallSimplexPdii
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z12smallSimplexPdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
using namespace std;
__global__ void smallSimplex(double* job, int width, int height)
{
extern __shared__ double shared[];
double* pivotColumn = &shared[0];
double* pivotRow = &shared[height];
double* ratioColumn = &shared[width];
__shared__ double smallestObj;
__shared__ int pivotColIndx;
__shared__ int pivotRowIndx;
smallestObj = 10^20;
int index = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while(true)
{
// STEP 1
if(threadIdx.x == 0)
{
for(int i = 0; i < width; i++)
{
if(smallestObj > job[(height-1)*width+i])
{
smallestObj = job[(height-1)*width+i];
pivotColIndx = i;
}
}
}
__syncthreads();
if(smallestObj >= 0){break;}
// printf("Smallest collumn is %d with value %f \n",pivotColIndx,smallestObj);
for(int i = index; i < height; i+=stride)
{
pivotColumn[i] = job[pivotColIndx + i*width];
ratioColumn[i] = job[(i+1)*width-1] / pivotColumn[i];
}
// printf("The ratio column is:\n");
// for(int i = 0; i < height; i++)
// {
// printf("%f\n",ratioColumn[i]);
// }
// STEP 2
smallestObj = 10^20;
if(threadIdx.x == 0)
{
for(int i = 0; i < height-1; i++)
{
if(smallestObj > ratioColumn[i])
{
smallestObj = ratioColumn[i];
pivotRowIndx = i;
}
}
}
__syncthreads();
// printf("Smallest row is %d with value %f \n",pivotRowIndx,smallestObj);
for(int i = index; i < width; i+=stride)
{
job[width*pivotRowIndx + i] = job[width*pivotRowIndx + i]/pivotColumn[pivotRowIndx];
pivotRow[i] = job[width*pivotRowIndx + i];
}
// STEP 3
for (int i = index; i < height; i+= stride)
{
if(i == pivotRowIndx){continue;}
for (int j = 0; j < width; j++)
{
job[width * i + j] = job[width * i + j] - pivotColumn[i]* pivotRow[j];
}
}
}
}
int main(int argc, char const *argv[])
{
double* simplexTable;
hipMallocManaged(&simplexTable, sizeof(double)*18);
// simplexTable[0] = 3.;
// simplexTable[1] = 4.;
// simplexTable[2] = 1.;
// simplexTable[3] = 0.;
// simplexTable[4] = 0.;
// simplexTable[5] = 24.;
//
// simplexTable[6] = 7.;
// simplexTable[7] = -4.;
// simplexTable[8] = 0.;
// simplexTable[9] = 1.;
// simplexTable[10] = 0.;
// simplexTable[11] = 16.;
//
// simplexTable[12] = -2.;
// simplexTable[13] = 3.;
// simplexTable[14] = 0.;
// simplexTable[15] = 0.;
// simplexTable[16] = 1.;
// simplexTable[17] = 0.;
simplexTable[0] = 10.;
simplexTable[1] = 7.;
simplexTable[2] = 1.;
simplexTable[3] = 0.;
simplexTable[4] = 0.;
simplexTable[5] = 40.;
simplexTable[6] = 1.;
simplexTable[7] = 1.;
simplexTable[8] = 0.;
simplexTable[9] = 1.;
simplexTable[10] = 0.;
simplexTable[11] = 5.;
simplexTable[12] = -17.;
simplexTable[13] = -12.;
simplexTable[14] = 0.;
simplexTable[15] = 0.;
simplexTable[16] = 1.;
simplexTable[17] = 0.;
int height = 3;
int width = 6;
int sharedMemory = sizeof(double)*(height*2 + width);
smallSimplex<<<1,256,sharedMemory>>>(simplexTable,width,height);
hipDeviceSynchronize();
for(int i = 0; i <18; i++)
{
cout<<simplexTable[i]<<" "<<"|"<<" ";
if(i%6 == 5){cout<<endl;}
}
return 0;
} | .text
.file "testSmallSimplex.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__smallSimplexPdii # -- Begin function _Z27__device_stub__smallSimplexPdii
.p2align 4, 0x90
.type _Z27__device_stub__smallSimplexPdii,@function
_Z27__device_stub__smallSimplexPdii: # @_Z27__device_stub__smallSimplexPdii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12smallSimplexPdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__smallSimplexPdii, .Lfunc_end0-_Z27__device_stub__smallSimplexPdii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
movl $144, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
movabsq $4621819117588971520, %rcx # imm = 0x4024000000000000
movq %rcx, (%rax)
movabsq $4619567317775286272, %rcx # imm = 0x401C000000000000
movq %rcx, 8(%rax)
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
movq %rcx, 16(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 24(%rax)
movabsq $4630826316843712512, %rdx # imm = 0x4044000000000000
movq %rdx, 40(%rax)
movq %rcx, 48(%rax)
movq %rcx, 56(%rax)
movq $0, 64(%rax)
movq %rcx, 72(%rax)
movq $0, 80(%rax)
movabsq $4617315517961601024, %rdx # imm = 0x4014000000000000
movq %rdx, 88(%rax)
movabsq $-4597893744568565760, %rdx # imm = 0xC031000000000000
movq %rdx, 96(%rax)
movabsq $-4600427019358961664, %rdx # imm = 0xC028000000000000
movq %rdx, 104(%rax)
movups %xmm0, 112(%rax)
movq %rcx, 128(%rax)
movq $0, 136(%rax)
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $96, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $6, 20(%rsp)
movl $3, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12smallSimplexPdii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %ebx, %ebx
movabsq $-6148914691236517205, %r15 # imm = 0xAAAAAAAAAAAAAAAB
jmp .LBB1_3
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_9: # in Loop: Header=BB1_3 Depth=1
incq %rbx
cmpq $18, %rbx
je .LBB1_10
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r15
shrq $2, %rdx
leal (%rdx,%rdx,2), %eax
leal 5(,%rax,2), %ebp
movq 8(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.1, %esi
movl $1, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str, %esi
movl $1, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl %ebx, %ebp
jne .LBB1_9
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_8
.LBB1_10:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12smallSimplexPdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12smallSimplexPdii,@object # @_Z12smallSimplexPdii
.section .rodata,"a",@progbits
.globl _Z12smallSimplexPdii
.p2align 3, 0x0
_Z12smallSimplexPdii:
.quad _Z27__device_stub__smallSimplexPdii
.size _Z12smallSimplexPdii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "|"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12smallSimplexPdii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__smallSimplexPdii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12smallSimplexPdii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122426_00000000-6_testSmallSimplex.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3886:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12smallSimplexPdiiPdii
.type _Z34__device_stub__Z12smallSimplexPdiiPdii, @function
_Z34__device_stub__Z12smallSimplexPdiiPdii:
.LFB3908:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12smallSimplexPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3908:
.size _Z34__device_stub__Z12smallSimplexPdiiPdii, .-_Z34__device_stub__Z12smallSimplexPdiiPdii
.globl _Z12smallSimplexPdii
.type _Z12smallSimplexPdii, @function
_Z12smallSimplexPdii:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12smallSimplexPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _Z12smallSimplexPdii, .-_Z12smallSimplexPdii
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string " "
.LC9:
.string "|"
.text
.globl main
.type main, @function
main:
.LFB3883:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $144, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
movq .LC0(%rip), %rcx
movq %rcx, (%rax)
movq 8(%rsp), %rax
movq .LC1(%rip), %rcx
movq %rcx, 8(%rax)
movsd .LC2(%rip), %xmm0
movsd %xmm0, 16(%rax)
movq $0x000000000, 24(%rax)
movq $0x000000000, 32(%rax)
movq .LC4(%rip), %rcx
movq %rcx, 40(%rax)
movsd %xmm0, 48(%rax)
movsd %xmm0, 56(%rax)
movq $0x000000000, 64(%rax)
movsd %xmm0, 72(%rax)
movq $0x000000000, 80(%rax)
movq .LC5(%rip), %rcx
movq %rcx, 88(%rax)
movq .LC6(%rip), %rcx
movq %rcx, 96(%rax)
movq .LC7(%rip), %rcx
movq %rcx, 104(%rax)
movq $0x000000000, 112(%rax)
movq $0x000000000, 120(%rax)
movsd %xmm0, 128(%rax)
movq $0x000000000, 136(%rax)
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $96, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
leaq .LC8(%rip), %rbp
leaq .LC9(%rip), %r13
jmp .L18
.L22:
movl $3, %edx
movl $6, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12smallSimplexPdiiPdii
jmp .L12
.L25:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
call _ZSt16__throw_bad_castv@PLT
.L23:
call __stack_chk_fail@PLT
.L26:
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L13:
addq $1, %rbx
cmpq $18, %rbx
je .L24
.L18:
movq 8(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %r13, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %rbp, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movslq %ebx, %rax
imulq $715827883, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
addl %eax, %eax
movl %ebx, %edx
subl %eax, %edx
cmpl $5, %edx
jne .L13
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L25
cmpb $0, 56(%r14)
jne .L26
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3883:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12smallSimplexPdii"
.LC11:
.string "precalc_xorwow_matrix"
.LC12:
.string "precalc_xorwow_offset_matrix"
.LC13:
.string "mrg32k3aM1"
.LC14:
.string "mrg32k3aM2"
.LC15:
.string "mrg32k3aM1SubSeq"
.LC16:
.string "mrg32k3aM2SubSeq"
.LC17:
.string "mrg32k3aM1Seq"
.LC18:
.string "mrg32k3aM2Seq"
.LC19:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3911:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12smallSimplexPdii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3911:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1076101120
.align 8
.LC1:
.long 0
.long 1075576832
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long 1078198272
.align 8
.LC5:
.long 0
.long 1075052544
.align 8
.LC6:
.long 0
.long -1070530560
.align 8
.LC7:
.long 0
.long -1071120384
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testSmallSimplex.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__smallSimplexPdii # -- Begin function _Z27__device_stub__smallSimplexPdii
.p2align 4, 0x90
.type _Z27__device_stub__smallSimplexPdii,@function
_Z27__device_stub__smallSimplexPdii: # @_Z27__device_stub__smallSimplexPdii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12smallSimplexPdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__smallSimplexPdii, .Lfunc_end0-_Z27__device_stub__smallSimplexPdii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
movl $144, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
movabsq $4621819117588971520, %rcx # imm = 0x4024000000000000
movq %rcx, (%rax)
movabsq $4619567317775286272, %rcx # imm = 0x401C000000000000
movq %rcx, 8(%rax)
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
movq %rcx, 16(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 24(%rax)
movabsq $4630826316843712512, %rdx # imm = 0x4044000000000000
movq %rdx, 40(%rax)
movq %rcx, 48(%rax)
movq %rcx, 56(%rax)
movq $0, 64(%rax)
movq %rcx, 72(%rax)
movq $0, 80(%rax)
movabsq $4617315517961601024, %rdx # imm = 0x4014000000000000
movq %rdx, 88(%rax)
movabsq $-4597893744568565760, %rdx # imm = 0xC031000000000000
movq %rdx, 96(%rax)
movabsq $-4600427019358961664, %rdx # imm = 0xC028000000000000
movq %rdx, 104(%rax)
movups %xmm0, 112(%rax)
movq %rcx, 128(%rax)
movq $0, 136(%rax)
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $96, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $6, 20(%rsp)
movl $3, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12smallSimplexPdii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %ebx, %ebx
movabsq $-6148914691236517205, %r15 # imm = 0xAAAAAAAAAAAAAAAB
jmp .LBB1_3
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_9: # in Loop: Header=BB1_3 Depth=1
incq %rbx
cmpq $18, %rbx
je .LBB1_10
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r15
shrq $2, %rdx
leal (%rdx,%rdx,2), %eax
leal 5(,%rax,2), %ebp
movq 8(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.1, %esi
movl $1, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str, %esi
movl $1, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl %ebx, %ebp
jne .LBB1_9
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_11
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_8
.LBB1_10:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12smallSimplexPdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12smallSimplexPdii,@object # @_Z12smallSimplexPdii
.section .rodata,"a",@progbits
.globl _Z12smallSimplexPdii
.p2align 3, 0x0
_Z12smallSimplexPdii:
.quad _Z27__device_stub__smallSimplexPdii
.size _Z12smallSimplexPdii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "|"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12smallSimplexPdii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__smallSimplexPdii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12smallSimplexPdii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <math.h>
__global__ void cu_sobel(int *orig, int *cpu, int height,int width){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
float dx, dy;
if( x > 0 && y > 0 && x < width-1 && y < height-1) {
dx = (-1* orig[(y-1)*width + (x-1)]) + (-2*orig[y*width+(x-1)]) + (-1*orig[(y+1)*width+(x-1)]) +
( orig[(y-1)*width + (x+1)]) + ( 2*orig[y*width+(x+1)]) + ( orig[(y+1)*width+(x+1)]);
dy = ( orig[(y-1)*width + (x-1)]) + ( 2*orig[(y-1)*width+x]) + ( orig[(y-1)*width+(x+1)]) +
(-1* orig[(y+1)*width + (x-1)]) + (-2*orig[(y+1)*width+x]) + (-1*orig[(y+1)*width+(x+1)]);
cpu[(y)*(width) + (x)] = sqrt( (dx*dx) + (dy*dy) );
}
}
// Called from driver program. Handles running GPU calculation
extern "C" void gpu_sobel(int *l_source_array, int *l_result_array,int src_rows, int src_column_size) {
int num_bytes_source = src_column_size * src_rows * sizeof(int);
int *l_source_array_d;
int *l_result_array_d;
cudaMalloc((void **)&l_source_array_d, num_bytes_source);
cudaMemcpy(l_source_array_d, l_source_array, num_bytes_source,cudaMemcpyHostToDevice);
int result_column_size = src_column_size;
int result_row_size = src_rows;
int num_bytes_result = result_column_size * result_row_size * sizeof(int);
cudaMalloc((void **)&l_result_array_d, num_bytes_result);
dim3 threadsPerBlock(32, 32);
dim3 numBlocks(ceil(src_column_size/32), ceil(src_rows/32), 1);
cu_sobel<<<numBlocks, threadsPerBlock>>>(l_source_array_d, l_result_array_d,
src_rows, src_column_size);
cudaMemcpy(l_result_array, l_result_array_d, num_bytes_result,
cudaMemcpyDeviceToHost);
cudaFree(l_source_array_d);
cudaFree(l_result_array_d);
} | code for sm_80
Function : _Z8cu_sobelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0050*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0060*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*00c0*/ ISETP.LT.OR P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fc80004701670 */
/*00d0*/ ISETP.GE.OR P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fc80008706670 */
/*00e0*/ ISETP.GE.OR P0, PT, R3, UR5, P0 ; /* 0x0000000503007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0120*/ IADD3 R5, R3.reuse, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x040fe20007ffe0ff */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0140*/ IMAD R7, R3, R2, c[0x0][0x174] ; /* 0x00005d0003077624 */
/* 0x000fe400078e0202 */
/*0150*/ IMAD R2, R5, c[0x0][0x174], R0.reuse ; /* 0x00005d0005027a24 */
/* 0x100fe400078e0200 */
/*0160*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x000fe400078e0207 */
/*0170*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fc400078e0200 */
/*0180*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0209 */
/*0190*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.WIDE R6, R7, R9.reuse, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x080fe200078e0209 */
/*01b0*/ LDG.E R11, [R2.64+-0x4] ; /* 0xfffffc04020b7981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0209 */
/*01e0*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc04060a7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x4] ; /* 0x00000404060d7981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000f62000c1e1900 */
/*0240*/ BSSY B0, 0x3d0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0250*/ IADD3 R16, -R10, R12, R11 ; /* 0x0000000c0a107210 */
/* 0x004fc40007ffe10b */
/*0260*/ IADD3 R10, R12, -R10, -R11 ; /* 0x8000000a0c0a7210 */
/* 0x000fe40007ffe80b */
/*0270*/ IADD3 R14, -R14, R15, RZ ; /* 0x0000000f0e0e7210 */
/* 0x008fe40007ffe1ff */
/*0280*/ IADD3 R15, -R13, R16, RZ ; /* 0x000000100d0f7210 */
/* 0x010fe40007ffe1ff */
/*0290*/ IADD3 R13, R10, R13, RZ ; /* 0x0000000d0a0d7210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ LEA R14, R14, R15, 0x1 ; /* 0x0000000f0e0e7211 */
/* 0x000fe200078e08ff */
/*02b0*/ IMAD.IADD R8, R8, 0x1, -R9 ; /* 0x0000000108087824 */
/* 0x020fca00078e0a09 */
/*02c0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */
/* 0x000e220000201400 */
/*02d0*/ IMAD R8, R8, 0x2, R13 ; /* 0x0000000208087824 */
/* 0x000fce00078e020d */
/*02e0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e620000201400 */
/*02f0*/ FMUL R3, R14, R14 ; /* 0x0000000e0e037220 */
/* 0x001fc80000400000 */
/*0300*/ FFMA R3, R8, R8, R3 ; /* 0x0000000808037223 */
/* 0x002fc80000000003 */
/*0310*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*0320*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0340*/ @!P0 BRA 0x380 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0350*/ MOV R8, 0x370 ; /* 0x0000037000087802 */
/* 0x003fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0x420 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0370*/ BRA 0x3c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0380*/ FMUL.FTZ R4, R3, R2 ; /* 0x0000000203047220 */
/* 0x003fe40000410000 */
/*0390*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*03a0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*03b0*/ FFMA R4, R3, R2, R4 ; /* 0x0000000203047223 */
/* 0x000fe40000000004 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e22000020f100 */
/*03e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*03f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0430*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fe20000000f00 */
/*0440*/ @!P0 BRA 0x550 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0460*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0470*/ @!P0 BRA 0x550 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0480*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0490*/ @P0 FADD.FTZ R2, R3, 1 ; /* 0x3f80000003020421 */
/* 0x000fe20000010000 */
/*04a0*/ @P0 BRA 0x550 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04b0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*04c0*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*04d0*/ @P0 MUFU.RSQ R5, R4 ; /* 0x0000000400050308 */
/* 0x000e240000001400 */
/*04e0*/ @P0 FMUL.FTZ R7, R4, R5 ; /* 0x0000000504070220 */
/* 0x001fe40000410000 */
/*04f0*/ @P0 FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005050820 */
/* 0x000fe40000410000 */
/*0500*/ @P0 FADD.FTZ R2, -R7, -RZ ; /* 0x800000ff07020221 */
/* 0x000fc80000010100 */
/*0510*/ @P0 FFMA R6, R7, R2, R4 ; /* 0x0000000207060223 */
/* 0x000fe40000000004 */
/*0520*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0003 */
/*0530*/ @P0 FFMA R5, R6, R5, R7 ; /* 0x0000000506050223 */
/* 0x000fc80000000007 */
/*0540*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0550*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0560*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0570*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0580*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa7002007950 */
/* 0x000fea0003c3ffff */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <math.h>
__global__ void cu_sobel(int *orig, int *cpu, int height,int width){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
float dx, dy;
if( x > 0 && y > 0 && x < width-1 && y < height-1) {
dx = (-1* orig[(y-1)*width + (x-1)]) + (-2*orig[y*width+(x-1)]) + (-1*orig[(y+1)*width+(x-1)]) +
( orig[(y-1)*width + (x+1)]) + ( 2*orig[y*width+(x+1)]) + ( orig[(y+1)*width+(x+1)]);
dy = ( orig[(y-1)*width + (x-1)]) + ( 2*orig[(y-1)*width+x]) + ( orig[(y-1)*width+(x+1)]) +
(-1* orig[(y+1)*width + (x-1)]) + (-2*orig[(y+1)*width+x]) + (-1*orig[(y+1)*width+(x+1)]);
cpu[(y)*(width) + (x)] = sqrt( (dx*dx) + (dy*dy) );
}
}
// Called from driver program. Handles running GPU calculation
extern "C" void gpu_sobel(int *l_source_array, int *l_result_array,int src_rows, int src_column_size) {
int num_bytes_source = src_column_size * src_rows * sizeof(int);
int *l_source_array_d;
int *l_result_array_d;
cudaMalloc((void **)&l_source_array_d, num_bytes_source);
cudaMemcpy(l_source_array_d, l_source_array, num_bytes_source,cudaMemcpyHostToDevice);
int result_column_size = src_column_size;
int result_row_size = src_rows;
int num_bytes_result = result_column_size * result_row_size * sizeof(int);
cudaMalloc((void **)&l_result_array_d, num_bytes_result);
dim3 threadsPerBlock(32, 32);
dim3 numBlocks(ceil(src_column_size/32), ceil(src_rows/32), 1);
cu_sobel<<<numBlocks, threadsPerBlock>>>(l_source_array_d, l_result_array_d,
src_rows, src_column_size);
cudaMemcpy(l_result_array, l_result_array_d, num_bytes_result,
cudaMemcpyDeviceToHost);
cudaFree(l_source_array_d);
cudaFree(l_result_array_d);
} | .file "tmpxft_00119f8a_00000000-6_filters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
.type _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii, @function
_Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cu_sobelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii, .-_Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
.globl _Z8cu_sobelPiS_ii
.type _Z8cu_sobelPiS_ii, @function
_Z8cu_sobelPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8cu_sobelPiS_ii, .-_Z8cu_sobelPiS_ii
.globl gpu_sobel
.type gpu_sobel, @function
gpu_sobel:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %ebp
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %edx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
leal 31(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
movl %eax, 28(%rsp)
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
movl %eax, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r12d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size gpu_sobel, .-gpu_sobel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8cu_sobelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cu_sobelPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <math.h>
__global__ void cu_sobel(int *orig, int *cpu, int height,int width){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
float dx, dy;
if( x > 0 && y > 0 && x < width-1 && y < height-1) {
dx = (-1* orig[(y-1)*width + (x-1)]) + (-2*orig[y*width+(x-1)]) + (-1*orig[(y+1)*width+(x-1)]) +
( orig[(y-1)*width + (x+1)]) + ( 2*orig[y*width+(x+1)]) + ( orig[(y+1)*width+(x+1)]);
dy = ( orig[(y-1)*width + (x-1)]) + ( 2*orig[(y-1)*width+x]) + ( orig[(y-1)*width+(x+1)]) +
(-1* orig[(y+1)*width + (x-1)]) + (-2*orig[(y+1)*width+x]) + (-1*orig[(y+1)*width+(x+1)]);
cpu[(y)*(width) + (x)] = sqrt( (dx*dx) + (dy*dy) );
}
}
// Called from driver program. Handles running GPU calculation
extern "C" void gpu_sobel(int *l_source_array, int *l_result_array,int src_rows, int src_column_size) {
int num_bytes_source = src_column_size * src_rows * sizeof(int);
int *l_source_array_d;
int *l_result_array_d;
cudaMalloc((void **)&l_source_array_d, num_bytes_source);
cudaMemcpy(l_source_array_d, l_source_array, num_bytes_source,cudaMemcpyHostToDevice);
int result_column_size = src_column_size;
int result_row_size = src_rows;
int num_bytes_result = result_column_size * result_row_size * sizeof(int);
cudaMalloc((void **)&l_result_array_d, num_bytes_result);
dim3 threadsPerBlock(32, 32);
dim3 numBlocks(ceil(src_column_size/32), ceil(src_rows/32), 1);
cu_sobel<<<numBlocks, threadsPerBlock>>>(l_source_array_d, l_result_array_d,
src_rows, src_column_size);
cudaMemcpy(l_result_array, l_result_array_d, num_bytes_result,
cudaMemcpyDeviceToHost);
cudaFree(l_source_array_d);
cudaFree(l_result_array_d);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void cu_sobel(int *orig, int *cpu, int height,int width){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
float dx, dy;
if( x > 0 && y > 0 && x < width-1 && y < height-1) {
dx = (-1* orig[(y-1)*width + (x-1)]) + (-2*orig[y*width+(x-1)]) + (-1*orig[(y+1)*width+(x-1)]) +
( orig[(y-1)*width + (x+1)]) + ( 2*orig[y*width+(x+1)]) + ( orig[(y+1)*width+(x+1)]);
dy = ( orig[(y-1)*width + (x-1)]) + ( 2*orig[(y-1)*width+x]) + ( orig[(y-1)*width+(x+1)]) +
(-1* orig[(y+1)*width + (x-1)]) + (-2*orig[(y+1)*width+x]) + (-1*orig[(y+1)*width+(x+1)]);
cpu[(y)*(width) + (x)] = sqrt( (dx*dx) + (dy*dy) );
}
}
// Called from driver program. Handles running GPU calculation
extern "C" void gpu_sobel(int *l_source_array, int *l_result_array,int src_rows, int src_column_size) {
int num_bytes_source = src_column_size * src_rows * sizeof(int);
int *l_source_array_d;
int *l_result_array_d;
hipMalloc((void **)&l_source_array_d, num_bytes_source);
hipMemcpy(l_source_array_d, l_source_array, num_bytes_source,hipMemcpyHostToDevice);
int result_column_size = src_column_size;
int result_row_size = src_rows;
int num_bytes_result = result_column_size * result_row_size * sizeof(int);
hipMalloc((void **)&l_result_array_d, num_bytes_result);
dim3 threadsPerBlock(32, 32);
dim3 numBlocks(ceil(src_column_size/32), ceil(src_rows/32), 1);
cu_sobel<<<numBlocks, threadsPerBlock>>>(l_source_array_d, l_result_array_d,
src_rows, src_column_size);
hipMemcpy(l_result_array, l_result_array_d, num_bytes_result,
hipMemcpyDeviceToHost);
hipFree(l_source_array_d);
hipFree(l_result_array_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void cu_sobel(int *orig, int *cpu, int height,int width){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
float dx, dy;
if( x > 0 && y > 0 && x < width-1 && y < height-1) {
dx = (-1* orig[(y-1)*width + (x-1)]) + (-2*orig[y*width+(x-1)]) + (-1*orig[(y+1)*width+(x-1)]) +
( orig[(y-1)*width + (x+1)]) + ( 2*orig[y*width+(x+1)]) + ( orig[(y+1)*width+(x+1)]);
dy = ( orig[(y-1)*width + (x-1)]) + ( 2*orig[(y-1)*width+x]) + ( orig[(y-1)*width+(x+1)]) +
(-1* orig[(y+1)*width + (x-1)]) + (-2*orig[(y+1)*width+x]) + (-1*orig[(y+1)*width+(x+1)]);
cpu[(y)*(width) + (x)] = sqrt( (dx*dx) + (dy*dy) );
}
}
// Called from driver program. Handles running GPU calculation
extern "C" void gpu_sobel(int *l_source_array, int *l_result_array,int src_rows, int src_column_size) {
int num_bytes_source = src_column_size * src_rows * sizeof(int);
int *l_source_array_d;
int *l_result_array_d;
hipMalloc((void **)&l_source_array_d, num_bytes_source);
hipMemcpy(l_source_array_d, l_source_array, num_bytes_source,hipMemcpyHostToDevice);
int result_column_size = src_column_size;
int result_row_size = src_rows;
int num_bytes_result = result_column_size * result_row_size * sizeof(int);
hipMalloc((void **)&l_result_array_d, num_bytes_result);
dim3 threadsPerBlock(32, 32);
dim3 numBlocks(ceil(src_column_size/32), ceil(src_rows/32), 1);
cu_sobel<<<numBlocks, threadsPerBlock>>>(l_source_array_d, l_result_array_d,
src_rows, src_column_size);
hipMemcpy(l_result_array, l_result_array_d, num_bytes_result,
hipMemcpyDeviceToHost);
hipFree(l_source_array_d);
hipFree(l_result_array_d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cu_sobelPiS_ii
.globl _Z8cu_sobelPiS_ii
.p2align 8
.type _Z8cu_sobelPiS_ii,@function
_Z8cu_sobelPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_add_i32 s2, s5, -1
s_add_i32 s3, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_i32_e32 v2, v0, v1
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 0, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, -1, v1
v_mul_lo_u32 v13, v1, s5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v11, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v14, v2, s5
v_add_nc_u32_e32 v2, -1, v0
v_add_nc_u32_e32 v15, s5, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v13, v11
v_add_nc_u32_e32 v1, v13, v2
v_add_nc_u32_e32 v5, v14, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v15, v2
v_add_nc_u32_e32 v9, v14, v11
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v11, v15, v11
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v16, v[5:6], off
v_add_co_u32 v5, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v10, vcc_lo
v_add_nc_u32_e32 v9, v14, v0
s_clause 0x1
global_load_b32 v14, v[7:8], off
global_load_b32 v17, v[5:6], off
v_add_nc_u32_e32 v7, v15, v0
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[5:6], 2, v[11:12]
v_add_nc_u32_e32 v0, v13, v0
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v3, vcc_lo, s0, v3
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x4
global_load_b32 v5, v[5:6], off
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
global_load_b32 v3, v[9:10], off
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v6, v16, v17
s_waitcnt vmcnt(4)
v_add_nc_u32_e32 v7, v14, v5
s_waitcnt vmcnt(2)
v_sub_nc_u32_e32 v1, v2, v1
v_add_nc_u32_e32 v2, v14, v16
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, v3, v4
v_sub_nc_u32_e32 v4, v6, v7
v_lshlrev_b32_e32 v1, 1, v1
v_sub_nc_u32_e32 v2, v17, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, v3, 1, v4
v_add3_u32 v1, v2, v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v3
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_fmac_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v1
v_add_nc_u32_e32 v4, 1, v1
v_fma_f32 v5, -v3, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v1, v2
v_cmp_ge_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v3, s0
v_cmp_lt_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, v1, v4, s0
v_mul_f32_e32 v3, 0x37800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v1, v3, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cu_sobelPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cu_sobelPiS_ii, .Lfunc_end0-_Z8cu_sobelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cu_sobelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cu_sobelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void cu_sobel(int *orig, int *cpu, int height,int width){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
float dx, dy;
if( x > 0 && y > 0 && x < width-1 && y < height-1) {
dx = (-1* orig[(y-1)*width + (x-1)]) + (-2*orig[y*width+(x-1)]) + (-1*orig[(y+1)*width+(x-1)]) +
( orig[(y-1)*width + (x+1)]) + ( 2*orig[y*width+(x+1)]) + ( orig[(y+1)*width+(x+1)]);
dy = ( orig[(y-1)*width + (x-1)]) + ( 2*orig[(y-1)*width+x]) + ( orig[(y-1)*width+(x+1)]) +
(-1* orig[(y+1)*width + (x-1)]) + (-2*orig[(y+1)*width+x]) + (-1*orig[(y+1)*width+(x+1)]);
cpu[(y)*(width) + (x)] = sqrt( (dx*dx) + (dy*dy) );
}
}
// Called from driver program. Handles running GPU calculation
extern "C" void gpu_sobel(int *l_source_array, int *l_result_array,int src_rows, int src_column_size) {
int num_bytes_source = src_column_size * src_rows * sizeof(int);
int *l_source_array_d;
int *l_result_array_d;
hipMalloc((void **)&l_source_array_d, num_bytes_source);
hipMemcpy(l_source_array_d, l_source_array, num_bytes_source,hipMemcpyHostToDevice);
int result_column_size = src_column_size;
int result_row_size = src_rows;
int num_bytes_result = result_column_size * result_row_size * sizeof(int);
hipMalloc((void **)&l_result_array_d, num_bytes_result);
dim3 threadsPerBlock(32, 32);
dim3 numBlocks(ceil(src_column_size/32), ceil(src_rows/32), 1);
cu_sobel<<<numBlocks, threadsPerBlock>>>(l_source_array_d, l_result_array_d,
src_rows, src_column_size);
hipMemcpy(l_result_array, l_result_array_d, num_bytes_result,
hipMemcpyDeviceToHost);
hipFree(l_source_array_d);
hipFree(l_result_array_d);
} | .text
.file "filters.hip"
.globl _Z23__device_stub__cu_sobelPiS_ii # -- Begin function _Z23__device_stub__cu_sobelPiS_ii
.p2align 4, 0x90
.type _Z23__device_stub__cu_sobelPiS_ii,@function
_Z23__device_stub__cu_sobelPiS_ii: # @_Z23__device_stub__cu_sobelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cu_sobelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cu_sobelPiS_ii, .Lfunc_end0-_Z23__device_stub__cu_sobelPiS_ii
.cfi_endproc
# -- End function
.globl gpu_sobel # -- Begin function gpu_sobel
.p2align 4, 0x90
.type gpu_sobel,@function
gpu_sobel: # @gpu_sobel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %rbx
movq %rdi, %r13
movl %edx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 31(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $5, %eax
leal 31(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r12d, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8cu_sobelPiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size gpu_sobel, .Lfunc_end1-gpu_sobel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cu_sobelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cu_sobelPiS_ii,@object # @_Z8cu_sobelPiS_ii
.section .rodata,"a",@progbits
.globl _Z8cu_sobelPiS_ii
.p2align 3, 0x0
_Z8cu_sobelPiS_ii:
.quad _Z23__device_stub__cu_sobelPiS_ii
.size _Z8cu_sobelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8cu_sobelPiS_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cu_sobelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cu_sobelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8cu_sobelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0050*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0060*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*00c0*/ ISETP.LT.OR P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fc80004701670 */
/*00d0*/ ISETP.GE.OR P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fc80008706670 */
/*00e0*/ ISETP.GE.OR P0, PT, R3, UR5, P0 ; /* 0x0000000503007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ MOV R2, c[0x0][0x174] ; /* 0x00005d0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0120*/ IADD3 R5, R3.reuse, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x040fe20007ffe0ff */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0140*/ IMAD R7, R3, R2, c[0x0][0x174] ; /* 0x00005d0003077624 */
/* 0x000fe400078e0202 */
/*0150*/ IMAD R2, R5, c[0x0][0x174], R0.reuse ; /* 0x00005d0005027a24 */
/* 0x100fe400078e0200 */
/*0160*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x000fe400078e0207 */
/*0170*/ IMAD R0, R3, c[0x0][0x174], R0 ; /* 0x00005d0003007a24 */
/* 0x000fc400078e0200 */
/*0180*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0209 */
/*0190*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.WIDE R6, R7, R9.reuse, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x080fe200078e0209 */
/*01b0*/ LDG.E R11, [R2.64+-0x4] ; /* 0xfffffc04020b7981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0209 */
/*01e0*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc04060a7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ee8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x4] ; /* 0x00000404060d7981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000f62000c1e1900 */
/*0240*/ BSSY B0, 0x3d0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0250*/ IADD3 R16, -R10, R12, R11 ; /* 0x0000000c0a107210 */
/* 0x004fc40007ffe10b */
/*0260*/ IADD3 R10, R12, -R10, -R11 ; /* 0x8000000a0c0a7210 */
/* 0x000fe40007ffe80b */
/*0270*/ IADD3 R14, -R14, R15, RZ ; /* 0x0000000f0e0e7210 */
/* 0x008fe40007ffe1ff */
/*0280*/ IADD3 R15, -R13, R16, RZ ; /* 0x000000100d0f7210 */
/* 0x010fe40007ffe1ff */
/*0290*/ IADD3 R13, R10, R13, RZ ; /* 0x0000000d0a0d7210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ LEA R14, R14, R15, 0x1 ; /* 0x0000000f0e0e7211 */
/* 0x000fe200078e08ff */
/*02b0*/ IMAD.IADD R8, R8, 0x1, -R9 ; /* 0x0000000108087824 */
/* 0x020fca00078e0a09 */
/*02c0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */
/* 0x000e220000201400 */
/*02d0*/ IMAD R8, R8, 0x2, R13 ; /* 0x0000000208087824 */
/* 0x000fce00078e020d */
/*02e0*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x000e620000201400 */
/*02f0*/ FMUL R3, R14, R14 ; /* 0x0000000e0e037220 */
/* 0x001fc80000400000 */
/*0300*/ FFMA R3, R8, R8, R3 ; /* 0x0000000808037223 */
/* 0x002fc80000000003 */
/*0310*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*0320*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0330*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0340*/ @!P0 BRA 0x380 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0350*/ MOV R8, 0x370 ; /* 0x0000037000087802 */
/* 0x003fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0x420 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0370*/ BRA 0x3c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0380*/ FMUL.FTZ R4, R3, R2 ; /* 0x0000000203047220 */
/* 0x003fe40000410000 */
/*0390*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*03a0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*03b0*/ FFMA R4, R3, R2, R4 ; /* 0x0000000203047223 */
/* 0x000fe40000000004 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e22000020f100 */
/*03e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*03f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0430*/ @!P0 MOV R2, R3 ; /* 0x0000000300028202 */
/* 0x000fe20000000f00 */
/*0440*/ @!P0 BRA 0x550 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0460*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0470*/ @!P0 BRA 0x550 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0480*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0490*/ @P0 FADD.FTZ R2, R3, 1 ; /* 0x3f80000003020421 */
/* 0x000fe20000010000 */
/*04a0*/ @P0 BRA 0x550 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04b0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*04c0*/ @P0 FFMA R4, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003040823 */
/* 0x000fc800000000ff */
/*04d0*/ @P0 MUFU.RSQ R5, R4 ; /* 0x0000000400050308 */
/* 0x000e240000001400 */
/*04e0*/ @P0 FMUL.FTZ R7, R4, R5 ; /* 0x0000000504070220 */
/* 0x001fe40000410000 */
/*04f0*/ @P0 FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005050820 */
/* 0x000fe40000410000 */
/*0500*/ @P0 FADD.FTZ R2, -R7, -RZ ; /* 0x800000ff07020221 */
/* 0x000fc80000010100 */
/*0510*/ @P0 FFMA R6, R7, R2, R4 ; /* 0x0000000207060223 */
/* 0x000fe40000000004 */
/*0520*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0003 */
/*0530*/ @P0 FFMA R5, R6, R5, R7 ; /* 0x0000000506050223 */
/* 0x000fc80000000007 */
/*0540*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0550*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0560*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0570*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0580*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa7002007950 */
/* 0x000fea0003c3ffff */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cu_sobelPiS_ii
.globl _Z8cu_sobelPiS_ii
.p2align 8
.type _Z8cu_sobelPiS_ii,@function
_Z8cu_sobelPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_add_i32 s2, s5, -1
s_add_i32 s3, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_i32_e32 v2, v0, v1
v_cmp_gt_i32_e64 s2, s3, v1
v_cmp_lt_i32_e64 s3, 0, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, -1, v1
v_mul_lo_u32 v13, v1, s5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v11, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v14, v2, s5
v_add_nc_u32_e32 v2, -1, v0
v_add_nc_u32_e32 v15, s5, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v13, v11
v_add_nc_u32_e32 v1, v13, v2
v_add_nc_u32_e32 v5, v14, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v15, v2
v_add_nc_u32_e32 v9, v14, v11
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v11, v15, v11
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v16, v[5:6], off
v_add_co_u32 v5, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v10, vcc_lo
v_add_nc_u32_e32 v9, v14, v0
s_clause 0x1
global_load_b32 v14, v[7:8], off
global_load_b32 v17, v[5:6], off
v_add_nc_u32_e32 v7, v15, v0
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[5:6], 2, v[11:12]
v_add_nc_u32_e32 v0, v13, v0
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_u32 v3, vcc_lo, s0, v3
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x4
global_load_b32 v5, v[5:6], off
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
global_load_b32 v3, v[9:10], off
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v6, v16, v17
s_waitcnt vmcnt(4)
v_add_nc_u32_e32 v7, v14, v5
s_waitcnt vmcnt(2)
v_sub_nc_u32_e32 v1, v2, v1
v_add_nc_u32_e32 v2, v14, v16
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, v3, v4
v_sub_nc_u32_e32 v4, v6, v7
v_lshlrev_b32_e32 v1, 1, v1
v_sub_nc_u32_e32 v2, v17, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, v3, 1, v4
v_add3_u32 v1, v2, v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v3
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_fmac_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v1
v_add_nc_u32_e32 v4, 1, v1
v_fma_f32 v5, -v3, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v1, v2
v_cmp_ge_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v3, s0
v_cmp_lt_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, v1, v4, s0
v_mul_f32_e32 v3, 0x37800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v1, v3, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cu_sobelPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cu_sobelPiS_ii, .Lfunc_end0-_Z8cu_sobelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cu_sobelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cu_sobelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00119f8a_00000000-6_filters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
.type _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii, @function
_Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cu_sobelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii, .-_Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
.globl _Z8cu_sobelPiS_ii
.type _Z8cu_sobelPiS_ii, @function
_Z8cu_sobelPiS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8cu_sobelPiS_ii, .-_Z8cu_sobelPiS_ii
.globl gpu_sobel
.type gpu_sobel, @function
gpu_sobel:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %ebp
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %edx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $32, 16(%rsp)
movl $32, 20(%rsp)
leal 31(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $5, %eax
movl %eax, 28(%rsp)
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
movl %eax, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r12d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z8cu_sobelPiS_iiPiS_ii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size gpu_sobel, .-gpu_sobel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8cu_sobelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cu_sobelPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "filters.hip"
.globl _Z23__device_stub__cu_sobelPiS_ii # -- Begin function _Z23__device_stub__cu_sobelPiS_ii
.p2align 4, 0x90
.type _Z23__device_stub__cu_sobelPiS_ii,@function
_Z23__device_stub__cu_sobelPiS_ii: # @_Z23__device_stub__cu_sobelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cu_sobelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cu_sobelPiS_ii, .Lfunc_end0-_Z23__device_stub__cu_sobelPiS_ii
.cfi_endproc
# -- End function
.globl gpu_sobel # -- Begin function gpu_sobel
.p2align 4, 0x90
.type gpu_sobel,@function
gpu_sobel: # @gpu_sobel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %rbx
movq %rdi, %r13
movl %edx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 31(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $5, %eax
leal 31(%r12), %edi
testl %r12d, %r12d
cmovnsl %r12d, %edi
sarl $5, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r12d, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8cu_sobelPiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size gpu_sobel, .Lfunc_end1-gpu_sobel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cu_sobelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cu_sobelPiS_ii,@object # @_Z8cu_sobelPiS_ii
.section .rodata,"a",@progbits
.globl _Z8cu_sobelPiS_ii
.p2align 3, 0x0
_Z8cu_sobelPiS_ii:
.quad _Z23__device_stub__cu_sobelPiS_ii
.size _Z8cu_sobelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8cu_sobelPiS_ii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cu_sobelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cu_sobelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void blur(unsigned char *pixels, int rows, int cols, int channels, int kernel, int numThreads){
int id = blockDim.x * blockIdx.x + threadIdx.x ;
int i = rows * id / numThreads;
int end = ( id == numThreads-1)? rows: rows * (id + 1) / numThreads;
int k = kernel/2;
for(; i<end; i++){
for (int j=0; j<cols; j++){
unsigned int blue=0.0, red=0.0, green=0.0;
double sum = 0.0;
for(int x=i-k; x<=i+k; x++){
for(int y=j-k; y<=j+k; y++){
if(x<rows && x>=0 && y<cols && y>=0){
sum += 1;
blue += pixels[ (cols*x*channels+y*channels)+0];
green += pixels[ (cols*x*channels+y*channels)+1];
red += pixels[ (cols*x*channels+y*channels)+2];
}
}
}
pixels[ (cols*i*channels+j*channels)+0] = (unsigned int) blue/sum;
pixels[ (cols*i*channels+j*channels)+1] = (unsigned int) green/sum;
pixels[ (cols*i*channels+j*channels)+2] = (unsigned int) red/sum;
}
}
} | .file "tmpxft_00149d73_00000000-6_blur.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4blurPhiiiiiPhiiiii
.type _Z28__device_stub__Z4blurPhiiiiiPhiiiii, @function
_Z28__device_stub__Z4blurPhiiiiiPhiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4blurPhiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4blurPhiiiiiPhiiiii, .-_Z28__device_stub__Z4blurPhiiiiiPhiiiii
.globl _Z4blurPhiiiii
.type _Z4blurPhiiiii, @function
_Z4blurPhiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4blurPhiiiiiPhiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4blurPhiiiii, .-_Z4blurPhiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4blurPhiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4blurPhiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void blur(unsigned char *pixels, int rows, int cols, int channels, int kernel, int numThreads){
int id = blockDim.x * blockIdx.x + threadIdx.x ;
int i = rows * id / numThreads;
int end = ( id == numThreads-1)? rows: rows * (id + 1) / numThreads;
int k = kernel/2;
for(; i<end; i++){
for (int j=0; j<cols; j++){
unsigned int blue=0.0, red=0.0, green=0.0;
double sum = 0.0;
for(int x=i-k; x<=i+k; x++){
for(int y=j-k; y<=j+k; y++){
if(x<rows && x>=0 && y<cols && y>=0){
sum += 1;
blue += pixels[ (cols*x*channels+y*channels)+0];
green += pixels[ (cols*x*channels+y*channels)+1];
red += pixels[ (cols*x*channels+y*channels)+2];
}
}
}
pixels[ (cols*i*channels+j*channels)+0] = (unsigned int) blue/sum;
pixels[ (cols*i*channels+j*channels)+1] = (unsigned int) green/sum;
pixels[ (cols*i*channels+j*channels)+2] = (unsigned int) red/sum;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void blur(unsigned char *pixels, int rows, int cols, int channels, int kernel, int numThreads){
int id = blockDim.x * blockIdx.x + threadIdx.x ;
int i = rows * id / numThreads;
int end = ( id == numThreads-1)? rows: rows * (id + 1) / numThreads;
int k = kernel/2;
for(; i<end; i++){
for (int j=0; j<cols; j++){
unsigned int blue=0.0, red=0.0, green=0.0;
double sum = 0.0;
for(int x=i-k; x<=i+k; x++){
for(int y=j-k; y<=j+k; y++){
if(x<rows && x>=0 && y<cols && y>=0){
sum += 1;
blue += pixels[ (cols*x*channels+y*channels)+0];
green += pixels[ (cols*x*channels+y*channels)+1];
red += pixels[ (cols*x*channels+y*channels)+2];
}
}
}
pixels[ (cols*i*channels+j*channels)+0] = (unsigned int) blue/sum;
pixels[ (cols*i*channels+j*channels)+1] = (unsigned int) green/sum;
pixels[ (cols*i*channels+j*channels)+2] = (unsigned int) red/sum;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void blur(unsigned char *pixels, int rows, int cols, int channels, int kernel, int numThreads){
int id = blockDim.x * blockIdx.x + threadIdx.x ;
int i = rows * id / numThreads;
int end = ( id == numThreads-1)? rows: rows * (id + 1) / numThreads;
int k = kernel/2;
for(; i<end; i++){
for (int j=0; j<cols; j++){
unsigned int blue=0.0, red=0.0, green=0.0;
double sum = 0.0;
for(int x=i-k; x<=i+k; x++){
for(int y=j-k; y<=j+k; y++){
if(x<rows && x>=0 && y<cols && y>=0){
sum += 1;
blue += pixels[ (cols*x*channels+y*channels)+0];
green += pixels[ (cols*x*channels+y*channels)+1];
red += pixels[ (cols*x*channels+y*channels)+2];
}
}
}
pixels[ (cols*i*channels+j*channels)+0] = (unsigned int) blue/sum;
pixels[ (cols*i*channels+j*channels)+1] = (unsigned int) green/sum;
pixels[ (cols*i*channels+j*channels)+2] = (unsigned int) red/sum;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4blurPhiiiii
.globl _Z4blurPhiiiii
.p2align 8
.type _Z4blurPhiiiii,@function
_Z4blurPhiiiii:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s5, 31
s_and_b32 s6, s6, 0xffff
s_add_i32 s3, s5, s2
s_add_i32 s5, s5, -1
s_xor_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mad_u64_u32 v[2:3], null, s15, s6, v[0:1]
v_mul_f32_e32 v0, 0x4f7ffffe, v1
s_sub_i32 s6, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s4
v_cmp_ne_u32_e32 vcc_lo, s5, v2
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v1, v4
v_cvt_u32_f32_e32 v0, v0
v_xor_b32_e32 v5, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s6, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, s4 :: v_dual_add_nc_u32 v6, v0, v3
v_mad_u64_u32 v[0:1], null, v5, v6, 0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[7:8], null, s4, v2, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v0, 31, v7
v_add_nc_u32_e32 v2, v7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v0
v_xor_b32_e32 v0, s2, v0
v_mul_hi_u32 v3, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v3, s3
v_sub_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v3
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v6, vcc_lo
v_xor_b32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v2, v0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_lo_u32 v0, v1, s3
v_add_nc_u32_e32 v2, 1, v1
v_xor_b32_e32 v4, s2, v4
s_mov_b32 s2, exec_lo
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_cndmask_b32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v1
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v1, v2, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v4
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_17
s_clause 0x2
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0xc
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 31
s_mul_i32 s12, s7, s6
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 1
s_cmp_gt_i32 s6, 0
v_subrev_nc_u32_e32 v0, s3, v2
v_add_nc_u32_e32 v5, s3, v2
s_cselect_b32 s5, -1, 0
s_or_b32 s11, s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s6, v0
v_subrev_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v4, s7, v0
s_branch .LBB0_5
.LBB0_4:
v_add_nc_u32_e32 v2, 1, v2
v_add_nc_u32_e32 v5, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, s12, v4
v_cmp_ge_i32_e32 vcc_lo, v2, v3
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_17
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_4
v_subrev_nc_u32_e32 v6, s3, v2
v_add_nc_u32_e32 v0, s3, v2
v_mul_lo_u32 v7, v2, s6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v8, v4
s_mov_b32 s13, 0
v_cmp_le_i32_e64 s0, v6, v0
s_branch .LBB0_9
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
s_or_b32 exec_lo, exec_lo, s2
v_cvt_f64_u32_e32 v[11:12], v11
v_cvt_f64_u32_e32 v[13:14], v10
v_cvt_f64_u32_e32 v[9:10], v9
v_add_nc_u32_e32 v8, s7, v8
v_div_scale_f64 v[15:16], null, v[0:1], v[0:1], v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_scale_f64 v[17:18], null, v[0:1], v[0:1], v[13:14]
v_div_scale_f64 v[19:20], null, v[0:1], v[0:1], v[9:10]
v_div_scale_f64 v[33:34], vcc_lo, v[11:12], v[0:1], v[11:12]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_f64_e32 v[21:22], v[15:16]
v_rcp_f64_e32 v[23:24], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
v_rcp_f64_e32 v[25:26], v[19:20]
v_fma_f64 v[27:28], -v[15:16], v[21:22], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[29:30], -v[17:18], v[23:24], 1.0
v_fma_f64 v[31:32], -v[19:20], v[25:26], 1.0
v_fma_f64 v[21:22], v[21:22], v[27:28], v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[23:24], v[29:30], v[23:24]
v_fma_f64 v[25:26], v[25:26], v[31:32], v[25:26]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[27:28], -v[15:16], v[21:22], 1.0
v_fma_f64 v[29:30], -v[17:18], v[23:24], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[31:32], -v[19:20], v[25:26], 1.0
v_fma_f64 v[21:22], v[21:22], v[27:28], v[21:22]
v_div_scale_f64 v[27:28], s1, v[13:14], v[0:1], v[13:14]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f64 v[23:24], v[23:24], v[29:30], v[23:24]
v_div_scale_f64 v[29:30], s2, v[9:10], v[0:1], v[9:10]
v_fma_f64 v[25:26], v[25:26], v[31:32], v[25:26]
v_mul_f64 v[31:32], v[33:34], v[21:22]
v_mul_f64 v[35:36], v[27:28], v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[37:38], v[29:30], v[25:26]
v_fma_f64 v[15:16], -v[15:16], v[31:32], v[33:34]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], -v[17:18], v[35:36], v[27:28]
v_fma_f64 v[19:20], -v[19:20], v[37:38], v[29:30]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[15:16], v[15:16], v[21:22], v[31:32]
s_mov_b32 vcc_lo, s1
v_div_fmas_f64 v[17:18], v[17:18], v[23:24], v[35:36]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[19:20], v[19:20], v[25:26], v[37:38]
v_div_fixup_f64 v[11:12], v[15:16], v[0:1], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[13:14], v[17:18], v[0:1], v[13:14]
v_div_fixup_f64 v[0:1], v[19:20], v[0:1], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f64_e32 v9, v[11:12]
v_cvt_i32_f64_e32 v10, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_i32_f64_e32 v11, v[0:1]
v_add_nc_u32_e32 v0, s13, v7
s_add_i32 s13, s13, 1
s_cmp_eq_u32 s13, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s7
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_clause 0x2
global_store_b8 v[0:1], v9, off
global_store_b8 v[0:1], v10, off offset:1
global_store_b8 v[0:1], v11, off offset:2
s_cbranch_scc1 .LBB0_4
.LBB0_9:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v9, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v10, 0
v_mov_b32_e32 v11, 0
s_mov_b32 s14, 0
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_8
s_sub_i32 s15, s13, s3
s_add_i32 s1, s13, s3
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v13, v6
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v10, 0
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v9, 0
v_mov_b32_e32 v11, 0
s_cmp_le_i32 s15, s1
s_cselect_b32 s16, -1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_12
.p2align 6
.LBB0_11:
v_add_nc_u32_e32 v14, 1, v13
v_cmp_eq_u32_e32 vcc_lo, v13, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v13, v14 :: v_dual_add_nc_u32 v12, s12, v12
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_7
.LBB0_12:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_11
v_cmp_gt_i32_e32 vcc_lo, s4, v13
v_cmp_lt_i32_e64 s1, -1, v13
v_mov_b32_e32 v14, v12
s_mov_b32 s17, s11
s_mov_b32 s18, s15
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s1, vcc_lo, s1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v14, s7, v14
s_add_i32 s17, s17, -1
s_add_i32 s18, s18, 1
s_cmp_eq_u32 s17, 0
s_cbranch_scc1 .LBB0_11
.LBB0_15:
s_cmp_lt_u32 s18, s6
s_cselect_b32 s19, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s20, s1, s19
s_and_saveexec_b32 s19, s20
s_cbranch_execz .LBB0_14
v_ashrrev_i32_e32 v16, 31, v14
v_add_co_u32 v15, vcc_lo, s8, v14
v_add_f64 v[0:1], v[0:1], 1.0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
s_clause 0x2
global_load_u8 v17, v[15:16], off
global_load_u8 v18, v[15:16], off offset:1
global_load_u8 v15, v[15:16], off offset:2
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v11, v11, v17
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v10, v10, v18
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, v9, v15
s_branch .LBB0_14
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4blurPhiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4blurPhiiiii, .Lfunc_end0-_Z4blurPhiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4blurPhiiiii
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z4blurPhiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void blur(unsigned char *pixels, int rows, int cols, int channels, int kernel, int numThreads){
int id = blockDim.x * blockIdx.x + threadIdx.x ;
int i = rows * id / numThreads;
int end = ( id == numThreads-1)? rows: rows * (id + 1) / numThreads;
int k = kernel/2;
for(; i<end; i++){
for (int j=0; j<cols; j++){
unsigned int blue=0.0, red=0.0, green=0.0;
double sum = 0.0;
for(int x=i-k; x<=i+k; x++){
for(int y=j-k; y<=j+k; y++){
if(x<rows && x>=0 && y<cols && y>=0){
sum += 1;
blue += pixels[ (cols*x*channels+y*channels)+0];
green += pixels[ (cols*x*channels+y*channels)+1];
red += pixels[ (cols*x*channels+y*channels)+2];
}
}
}
pixels[ (cols*i*channels+j*channels)+0] = (unsigned int) blue/sum;
pixels[ (cols*i*channels+j*channels)+1] = (unsigned int) green/sum;
pixels[ (cols*i*channels+j*channels)+2] = (unsigned int) red/sum;
}
}
} | .text
.file "blur.hip"
.globl _Z19__device_stub__blurPhiiiii # -- Begin function _Z19__device_stub__blurPhiiiii
.p2align 4, 0x90
.type _Z19__device_stub__blurPhiiiii,@function
_Z19__device_stub__blurPhiiiii: # @_Z19__device_stub__blurPhiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4blurPhiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z19__device_stub__blurPhiiiii, .Lfunc_end0-_Z19__device_stub__blurPhiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4blurPhiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4blurPhiiiii,@object # @_Z4blurPhiiiii
.section .rodata,"a",@progbits
.globl _Z4blurPhiiiii
.p2align 3, 0x0
_Z4blurPhiiiii:
.quad _Z19__device_stub__blurPhiiiii
.size _Z4blurPhiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4blurPhiiiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__blurPhiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4blurPhiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00149d73_00000000-6_blur.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4blurPhiiiiiPhiiiii
.type _Z28__device_stub__Z4blurPhiiiiiPhiiiii, @function
_Z28__device_stub__Z4blurPhiiiiiPhiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4blurPhiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4blurPhiiiiiPhiiiii, .-_Z28__device_stub__Z4blurPhiiiiiPhiiiii
.globl _Z4blurPhiiiii
.type _Z4blurPhiiiii, @function
_Z4blurPhiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4blurPhiiiiiPhiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4blurPhiiiii, .-_Z4blurPhiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4blurPhiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4blurPhiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "blur.hip"
.globl _Z19__device_stub__blurPhiiiii # -- Begin function _Z19__device_stub__blurPhiiiii
.p2align 4, 0x90
.type _Z19__device_stub__blurPhiiiii,@function
_Z19__device_stub__blurPhiiiii: # @_Z19__device_stub__blurPhiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4blurPhiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z19__device_stub__blurPhiiiii, .Lfunc_end0-_Z19__device_stub__blurPhiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4blurPhiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4blurPhiiiii,@object # @_Z4blurPhiiiii
.section .rodata,"a",@progbits
.globl _Z4blurPhiiiii
.p2align 3, 0x0
_Z4blurPhiiiii:
.quad _Z19__device_stub__blurPhiiiii
.size _Z4blurPhiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4blurPhiiiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__blurPhiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4blurPhiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define GLM_FORCE_CUDA
// LOOK-2.1 potentially useful for doing grid-based neighbor search
#ifndef imax
#define imax( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef imin
#define imin( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#define checkCUDAErrorWithLine(msg) checkCUDAError(msg, __LINE__)
/**
* Check for CUDA errors; print and exit if there was a problem.
*/
__global__ void kernResetIntBuffer(int N, int *intBuffer, int value) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
if (index < N) {
intBuffer[index] = value;
}
} | code for sm_80
Function : _Z18kernResetIntBufferiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x170] ; /* 0x00005c0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define GLM_FORCE_CUDA
// LOOK-2.1 potentially useful for doing grid-based neighbor search
#ifndef imax
#define imax( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef imin
#define imin( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#define checkCUDAErrorWithLine(msg) checkCUDAError(msg, __LINE__)
/**
* Check for CUDA errors; print and exit if there was a problem.
*/
__global__ void kernResetIntBuffer(int N, int *intBuffer, int value) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
if (index < N) {
intBuffer[index] = value;
}
} | .file "tmpxft_0005a590_00000000-6_kernResetIntBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z18kernResetIntBufferiPiiiPii
.type _Z40__device_stub__Z18kernResetIntBufferiPiiiPii, @function
_Z40__device_stub__Z18kernResetIntBufferiPiiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18kernResetIntBufferiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z18kernResetIntBufferiPiiiPii, .-_Z40__device_stub__Z18kernResetIntBufferiPiiiPii
.globl _Z18kernResetIntBufferiPii
.type _Z18kernResetIntBufferiPii, @function
_Z18kernResetIntBufferiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18kernResetIntBufferiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernResetIntBufferiPii, .-_Z18kernResetIntBufferiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernResetIntBufferiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernResetIntBufferiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define GLM_FORCE_CUDA
// LOOK-2.1 potentially useful for doing grid-based neighbor search
#ifndef imax
#define imax( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef imin
#define imin( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#define checkCUDAErrorWithLine(msg) checkCUDAError(msg, __LINE__)
/**
* Check for CUDA errors; print and exit if there was a problem.
*/
__global__ void kernResetIntBuffer(int N, int *intBuffer, int value) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
if (index < N) {
intBuffer[index] = value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define GLM_FORCE_CUDA
// LOOK-2.1 potentially useful for doing grid-based neighbor search
#ifndef imax
#define imax( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef imin
#define imin( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#define checkCUDAErrorWithLine(msg) checkCUDAError(msg, __LINE__)
/**
* Check for CUDA errors; print and exit if there was a problem.
*/
__global__ void kernResetIntBuffer(int N, int *intBuffer, int value) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
if (index < N) {
intBuffer[index] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define GLM_FORCE_CUDA
// LOOK-2.1 potentially useful for doing grid-based neighbor search
#ifndef imax
#define imax( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef imin
#define imin( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#define checkCUDAErrorWithLine(msg) checkCUDAError(msg, __LINE__)
/**
* Check for CUDA errors; print and exit if there was a problem.
*/
__global__ void kernResetIntBuffer(int N, int *intBuffer, int value) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
if (index < N) {
intBuffer[index] = value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernResetIntBufferiPii
.globl _Z18kernResetIntBufferiPii
.p2align 8
.type _Z18kernResetIntBufferiPii,@function
_Z18kernResetIntBufferiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernResetIntBufferiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernResetIntBufferiPii, .Lfunc_end0-_Z18kernResetIntBufferiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernResetIntBufferiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernResetIntBufferiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define GLM_FORCE_CUDA
// LOOK-2.1 potentially useful for doing grid-based neighbor search
#ifndef imax
#define imax( a, b ) ( ((a) > (b)) ? (a) : (b) )
#endif
#ifndef imin
#define imin( a, b ) ( ((a) < (b)) ? (a) : (b) )
#endif
#define checkCUDAErrorWithLine(msg) checkCUDAError(msg, __LINE__)
/**
* Check for CUDA errors; print and exit if there was a problem.
*/
__global__ void kernResetIntBuffer(int N, int *intBuffer, int value) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
if (index < N) {
intBuffer[index] = value;
}
} | .text
.file "kernResetIntBuffer.hip"
.globl _Z33__device_stub__kernResetIntBufferiPii # -- Begin function _Z33__device_stub__kernResetIntBufferiPii
.p2align 4, 0x90
.type _Z33__device_stub__kernResetIntBufferiPii,@function
_Z33__device_stub__kernResetIntBufferiPii: # @_Z33__device_stub__kernResetIntBufferiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18kernResetIntBufferiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__kernResetIntBufferiPii, .Lfunc_end0-_Z33__device_stub__kernResetIntBufferiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernResetIntBufferiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernResetIntBufferiPii,@object # @_Z18kernResetIntBufferiPii
.section .rodata,"a",@progbits
.globl _Z18kernResetIntBufferiPii
.p2align 3, 0x0
_Z18kernResetIntBufferiPii:
.quad _Z33__device_stub__kernResetIntBufferiPii
.size _Z18kernResetIntBufferiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernResetIntBufferiPii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernResetIntBufferiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernResetIntBufferiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kernResetIntBufferiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x170] ; /* 0x00005c0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernResetIntBufferiPii
.globl _Z18kernResetIntBufferiPii
.p2align 8
.type _Z18kernResetIntBufferiPii,@function
_Z18kernResetIntBufferiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernResetIntBufferiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernResetIntBufferiPii, .Lfunc_end0-_Z18kernResetIntBufferiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernResetIntBufferiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernResetIntBufferiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005a590_00000000-6_kernResetIntBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z18kernResetIntBufferiPiiiPii
.type _Z40__device_stub__Z18kernResetIntBufferiPiiiPii, @function
_Z40__device_stub__Z18kernResetIntBufferiPiiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18kernResetIntBufferiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z18kernResetIntBufferiPiiiPii, .-_Z40__device_stub__Z18kernResetIntBufferiPiiiPii
.globl _Z18kernResetIntBufferiPii
.type _Z18kernResetIntBufferiPii, @function
_Z18kernResetIntBufferiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18kernResetIntBufferiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernResetIntBufferiPii, .-_Z18kernResetIntBufferiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernResetIntBufferiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernResetIntBufferiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernResetIntBuffer.hip"
.globl _Z33__device_stub__kernResetIntBufferiPii # -- Begin function _Z33__device_stub__kernResetIntBufferiPii
.p2align 4, 0x90
.type _Z33__device_stub__kernResetIntBufferiPii,@function
_Z33__device_stub__kernResetIntBufferiPii: # @_Z33__device_stub__kernResetIntBufferiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18kernResetIntBufferiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__kernResetIntBufferiPii, .Lfunc_end0-_Z33__device_stub__kernResetIntBufferiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernResetIntBufferiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernResetIntBufferiPii,@object # @_Z18kernResetIntBufferiPii
.section .rodata,"a",@progbits
.globl _Z18kernResetIntBufferiPii
.p2align 3, 0x0
_Z18kernResetIntBufferiPii:
.quad _Z33__device_stub__kernResetIntBufferiPii
.size _Z18kernResetIntBufferiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernResetIntBufferiPii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernResetIntBufferiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernResetIntBufferiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include <stdio.h>
extern "C"
{
__global__ void kernel(int *m, int v)
{
m[threadIdx.x + (blockDim.x * blockIdx.x)] = v;
}
}
int main()
{
return 0;
} | code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <stdio.h>
extern "C"
{
__global__ void kernel(int *m, int v)
{
m[threadIdx.x + (blockDim.x * blockIdx.x)] = v;
}
}
int main()
{
return 0;
} | .file "tmpxft_000ce90c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl kernel
.type kernel, @function
kernel:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <stdio.h>
extern "C"
{
__global__ void kernel(int *m, int v)
{
m[threadIdx.x + (blockDim.x * blockIdx.x)] = v;
}
}
int main()
{
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
extern "C"
{
__global__ void kernel(int *m, int v)
{
m[threadIdx.x + (blockDim.x * blockIdx.x)] = v;
}
}
int main()
{
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
extern "C"
{
__global__ void kernel(int *m, int v)
{
m[threadIdx.x + (blockDim.x * blockIdx.x)] = v;
}
}
int main()
{
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
extern "C"
{
__global__ void kernel(int *m, int v)
{
m[threadIdx.x + (blockDim.x * blockIdx.x)] = v;
}
}
int main()
{
return 0;
} | .text
.file "kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.p2align 4, 0x90
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce90c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl kernel
.type kernel, @function
kernel:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.p2align 4, 0x90
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <stdio.h>
#define N 200
__global__ void reverse(int *a, int *b) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
b[gridDim.x - idx - 1] = a[idx];
}
void random_ints(int *p, int n) {
int i;
for (i = 0; i < n; i++) {
p[i] = rand() % 100;
}
}
int main(void) {
int *a, *b; // host copies of a, b, c
int *dev_a, *dev_b; // device copies of a, b, c
int size = N * sizeof(int); // we need space for 512
// // integers
int i;
// allocate device copies of a, b, c
cudaMalloc((void **)&dev_a, size);
cudaMalloc((void **)&dev_b, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
random_ints(a, N);
// copy inputs to device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
// launch an add() kernel with N threads
reverse<<<N, 1>>>(dev_a, dev_b);
// copy device result back to host copy of c
cudaMemcpy(b, dev_b, size, cudaMemcpyDeviceToHost);
for (i = 0; i < N; i++) {
if (b[i] != a[N - 1 - i]) {
printf("Uncorrect\n");
break;
}
}
printf("Correct\n");
free(a);
free(b);
cudaFree(dev_a);
cudaFree(dev_b);
return 0;
} | code for sm_80
Function : _Z7reversePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*0090*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fca0007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
#define N 200
__global__ void reverse(int *a, int *b) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
b[gridDim.x - idx - 1] = a[idx];
}
void random_ints(int *p, int n) {
int i;
for (i = 0; i < n; i++) {
p[i] = rand() % 100;
}
}
int main(void) {
int *a, *b; // host copies of a, b, c
int *dev_a, *dev_b; // device copies of a, b, c
int size = N * sizeof(int); // we need space for 512
// // integers
int i;
// allocate device copies of a, b, c
cudaMalloc((void **)&dev_a, size);
cudaMalloc((void **)&dev_b, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
random_ints(a, N);
// copy inputs to device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
// launch an add() kernel with N threads
reverse<<<N, 1>>>(dev_a, dev_b);
// copy device result back to host copy of c
cudaMemcpy(b, dev_b, size, cudaMemcpyDeviceToHost);
for (i = 0; i < N; i++) {
if (b[i] != a[N - 1 - i]) {
printf("Uncorrect\n");
break;
}
}
printf("Correct\n");
free(a);
free(b);
cudaFree(dev_a);
cudaFree(dev_b);
return 0;
} | .file "tmpxft_0002b149_00000000-6_array_revesal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z28__device_stub__Z7reversePiS_PiS_
.type _Z28__device_stub__Z7reversePiS_PiS_, @function
_Z28__device_stub__Z7reversePiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reversePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z28__device_stub__Z7reversePiS_PiS_, .-_Z28__device_stub__Z7reversePiS_PiS_
.globl _Z7reversePiS_
.type _Z7reversePiS_, @function
_Z7reversePiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reversePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7reversePiS_, .-_Z7reversePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Uncorrect\n"
.LC1:
.string "Correct\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $800, %edi
call malloc@PLT
movq %rax, %rbp
movl $800, %edi
call malloc@PLT
movq %rax, %rbx
movl $200, %esi
movq %rbp, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $800, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $200, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
movl $2, %ecx
movl $800, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 796(%rbp), %rdx
leaq 800(%rbx), %rcx
.L23:
movl (%rdx), %esi
cmpl %esi, (%rax)
jne .L28
addq $4, %rax
subq $4, %rdx
cmpq %rcx, %rax
jne .L23
jmp .L22
.L27:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reversePiS_PiS_
jmp .L20
.L28:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7reversePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reversePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#define N 200
__global__ void reverse(int *a, int *b) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
b[gridDim.x - idx - 1] = a[idx];
}
void random_ints(int *p, int n) {
int i;
for (i = 0; i < n; i++) {
p[i] = rand() % 100;
}
}
int main(void) {
int *a, *b; // host copies of a, b, c
int *dev_a, *dev_b; // device copies of a, b, c
int size = N * sizeof(int); // we need space for 512
// // integers
int i;
// allocate device copies of a, b, c
cudaMalloc((void **)&dev_a, size);
cudaMalloc((void **)&dev_b, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
random_ints(a, N);
// copy inputs to device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
// launch an add() kernel with N threads
reverse<<<N, 1>>>(dev_a, dev_b);
// copy device result back to host copy of c
cudaMemcpy(b, dev_b, size, cudaMemcpyDeviceToHost);
for (i = 0; i < N; i++) {
if (b[i] != a[N - 1 - i]) {
printf("Uncorrect\n");
break;
}
}
printf("Correct\n");
free(a);
free(b);
cudaFree(dev_a);
cudaFree(dev_b);
return 0;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define N 200
__global__ void reverse(int *a, int *b) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
b[gridDim.x - idx - 1] = a[idx];
}
void random_ints(int *p, int n) {
int i;
for (i = 0; i < n; i++) {
p[i] = rand() % 100;
}
}
int main(void) {
int *a, *b; // host copies of a, b, c
int *dev_a, *dev_b; // device copies of a, b, c
int size = N * sizeof(int); // we need space for 512
// // integers
int i;
// allocate device copies of a, b, c
hipMalloc((void **)&dev_a, size);
hipMalloc((void **)&dev_b, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
random_ints(a, N);
// copy inputs to device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
// launch an add() kernel with N threads
reverse<<<N, 1>>>(dev_a, dev_b);
// copy device result back to host copy of c
hipMemcpy(b, dev_b, size, hipMemcpyDeviceToHost);
for (i = 0; i < N; i++) {
if (b[i] != a[N - 1 - i]) {
printf("Uncorrect\n");
break;
}
}
printf("Correct\n");
free(a);
free(b);
hipFree(dev_a);
hipFree(dev_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define N 200
__global__ void reverse(int *a, int *b) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
b[gridDim.x - idx - 1] = a[idx];
}
void random_ints(int *p, int n) {
int i;
for (i = 0; i < n; i++) {
p[i] = rand() % 100;
}
}
int main(void) {
int *a, *b; // host copies of a, b, c
int *dev_a, *dev_b; // device copies of a, b, c
int size = N * sizeof(int); // we need space for 512
// // integers
int i;
// allocate device copies of a, b, c
hipMalloc((void **)&dev_a, size);
hipMalloc((void **)&dev_b, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
random_ints(a, N);
// copy inputs to device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
// launch an add() kernel with N threads
reverse<<<N, 1>>>(dev_a, dev_b);
// copy device result back to host copy of c
hipMemcpy(b, dev_b, size, hipMemcpyDeviceToHost);
for (i = 0; i < N; i++) {
if (b[i] != a[N - 1 - i]) {
printf("Uncorrect\n");
break;
}
}
printf("Correct\n");
free(a);
free(b);
hipFree(dev_a);
hipFree(dev_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reversePiS_
.globl _Z7reversePiS_
.p2align 8
.type _Z7reversePiS_,@function
_Z7reversePiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b32 v2, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reversePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reversePiS_, .Lfunc_end0-_Z7reversePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reversePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reversePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define N 200
__global__ void reverse(int *a, int *b) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
b[gridDim.x - idx - 1] = a[idx];
}
void random_ints(int *p, int n) {
int i;
for (i = 0; i < n; i++) {
p[i] = rand() % 100;
}
}
int main(void) {
int *a, *b; // host copies of a, b, c
int *dev_a, *dev_b; // device copies of a, b, c
int size = N * sizeof(int); // we need space for 512
// // integers
int i;
// allocate device copies of a, b, c
hipMalloc((void **)&dev_a, size);
hipMalloc((void **)&dev_b, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
random_ints(a, N);
// copy inputs to device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
// launch an add() kernel with N threads
reverse<<<N, 1>>>(dev_a, dev_b);
// copy device result back to host copy of c
hipMemcpy(b, dev_b, size, hipMemcpyDeviceToHost);
for (i = 0; i < N; i++) {
if (b[i] != a[N - 1 - i]) {
printf("Uncorrect\n");
break;
}
}
printf("Correct\n");
free(a);
free(b);
hipFree(dev_a);
hipFree(dev_b);
return 0;
} | .text
.file "array_revesal.hip"
.globl _Z22__device_stub__reversePiS_ # -- Begin function _Z22__device_stub__reversePiS_
.p2align 4, 0x90
.type _Z22__device_stub__reversePiS_,@function
_Z22__device_stub__reversePiS_: # @_Z22__device_stub__reversePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reversePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reversePiS_, .Lfunc_end0-_Z22__device_stub__reversePiS_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq %rsp, %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $200, %r15
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movq 8(%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 199(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reversePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $800, %edx # imm = 0x320
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $199, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl (%rcx), %edx
cmpl (%rbx,%rax,4), %edx
jne .LBB2_7
# %bb.5: # in Loop: Header=BB2_6 Depth=1
addq $4, %rcx
addq $-1, %rax
jb .LBB2_6
jmp .LBB2_8
.LBB2_7:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_8: # %.loopexit
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reversePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reversePiS_,@object # @_Z7reversePiS_
.section .rodata,"a",@progbits
.globl _Z7reversePiS_
.p2align 3, 0x0
_Z7reversePiS_:
.quad _Z22__device_stub__reversePiS_
.size _Z7reversePiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reversePiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Uncorrect"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Correct"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reversePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reversePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reversePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fc800078e33ff */
/*0090*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fca0007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reversePiS_
.globl _Z7reversePiS_
.p2align 8
.type _Z7reversePiS_,@function
_Z7reversePiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_xad_u32 v0, v1, -1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b32 v2, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reversePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reversePiS_, .Lfunc_end0-_Z7reversePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reversePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reversePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b149_00000000-6_array_revesal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z28__device_stub__Z7reversePiS_PiS_
.type _Z28__device_stub__Z7reversePiS_PiS_, @function
_Z28__device_stub__Z7reversePiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reversePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z28__device_stub__Z7reversePiS_PiS_, .-_Z28__device_stub__Z7reversePiS_PiS_
.globl _Z7reversePiS_
.type _Z7reversePiS_, @function
_Z7reversePiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reversePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7reversePiS_, .-_Z7reversePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Uncorrect\n"
.LC1:
.string "Correct\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $800, %edi
call malloc@PLT
movq %rax, %rbp
movl $800, %edi
call malloc@PLT
movq %rax, %rbx
movl $200, %esi
movq %rbp, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $800, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $200, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
movl $2, %ecx
movl $800, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 796(%rbp), %rdx
leaq 800(%rbx), %rcx
.L23:
movl (%rdx), %esi
cmpl %esi, (%rax)
jne .L28
addq $4, %rax
subq $4, %rdx
cmpq %rcx, %rax
jne .L23
jmp .L22
.L27:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reversePiS_PiS_
jmp .L20
.L28:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7reversePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reversePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array_revesal.hip"
.globl _Z22__device_stub__reversePiS_ # -- Begin function _Z22__device_stub__reversePiS_
.p2align 4, 0x90
.type _Z22__device_stub__reversePiS_,@function
_Z22__device_stub__reversePiS_: # @_Z22__device_stub__reversePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reversePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reversePiS_, .Lfunc_end0-_Z22__device_stub__reversePiS_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq %rsp, %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $200, %r15
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movq 8(%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 199(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reversePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $800, %edx # imm = 0x320
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $199, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl (%rcx), %edx
cmpl (%rbx,%rax,4), %edx
jne .LBB2_7
# %bb.5: # in Loop: Header=BB2_6 Depth=1
addq $4, %rcx
addq $-1, %rax
jb .LBB2_6
jmp .LBB2_8
.LBB2_7:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_8: # %.loopexit
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reversePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reversePiS_,@object # @_Z7reversePiS_
.section .rodata,"a",@progbits
.globl _Z7reversePiS_
.p2align 3, 0x0
_Z7reversePiS_:
.quad _Z22__device_stub__reversePiS_
.size _Z7reversePiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7reversePiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Uncorrect"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Correct"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reversePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reversePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cube(float * d_out, float * d_in){
// Todo: Fill in this function
int index = threadIdx.x;
float f = d_in[index];
d_out[index] = f*f*f;
} | code for sm_80
Function : _Z4cubePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fc80000400000 */
/*0080*/ FMUL R7, R2, R7 ; /* 0x0000000702077220 */
/* 0x000fca0000400000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cube(float * d_out, float * d_in){
// Todo: Fill in this function
int index = threadIdx.x;
float f = d_in[index];
d_out[index] = f*f*f;
} | .file "tmpxft_001499e3_00000000-6_cube.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4cubePfS_PfS_
.type _Z25__device_stub__Z4cubePfS_PfS_, @function
_Z25__device_stub__Z4cubePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4cubePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4cubePfS_PfS_, .-_Z25__device_stub__Z4cubePfS_PfS_
.globl _Z4cubePfS_
.type _Z4cubePfS_, @function
_Z4cubePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4cubePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4cubePfS_, .-_Z4cubePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4cubePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4cubePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cube(float * d_out, float * d_in){
// Todo: Fill in this function
int index = threadIdx.x;
float f = d_in[index];
d_out[index] = f*f*f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cube(float * d_out, float * d_in){
// Todo: Fill in this function
int index = threadIdx.x;
float f = d_in[index];
d_out[index] = f*f*f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cube(float * d_out, float * d_in){
// Todo: Fill in this function
int index = threadIdx.x;
float f = d_in[index];
d_out[index] = f*f*f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4cubePfS_
.globl _Z4cubePfS_
.p2align 8
.type _Z4cubePfS_,@function
_Z4cubePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4cubePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4cubePfS_, .Lfunc_end0-_Z4cubePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4cubePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4cubePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cube(float * d_out, float * d_in){
// Todo: Fill in this function
int index = threadIdx.x;
float f = d_in[index];
d_out[index] = f*f*f;
} | .text
.file "cube.hip"
.globl _Z19__device_stub__cubePfS_ # -- Begin function _Z19__device_stub__cubePfS_
.p2align 4, 0x90
.type _Z19__device_stub__cubePfS_,@function
_Z19__device_stub__cubePfS_: # @_Z19__device_stub__cubePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4cubePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__cubePfS_, .Lfunc_end0-_Z19__device_stub__cubePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4cubePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4cubePfS_,@object # @_Z4cubePfS_
.section .rodata,"a",@progbits
.globl _Z4cubePfS_
.p2align 3, 0x0
_Z4cubePfS_:
.quad _Z19__device_stub__cubePfS_
.size _Z4cubePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4cubePfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__cubePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4cubePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4cubePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fc80000400000 */
/*0080*/ FMUL R7, R2, R7 ; /* 0x0000000702077220 */
/* 0x000fca0000400000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4cubePfS_
.globl _Z4cubePfS_
.p2align 8
.type _Z4cubePfS_,@function
_Z4cubePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4cubePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4cubePfS_, .Lfunc_end0-_Z4cubePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4cubePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4cubePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001499e3_00000000-6_cube.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4cubePfS_PfS_
.type _Z25__device_stub__Z4cubePfS_PfS_, @function
_Z25__device_stub__Z4cubePfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4cubePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4cubePfS_PfS_, .-_Z25__device_stub__Z4cubePfS_PfS_
.globl _Z4cubePfS_
.type _Z4cubePfS_, @function
_Z4cubePfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4cubePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4cubePfS_, .-_Z4cubePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4cubePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4cubePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cube.hip"
.globl _Z19__device_stub__cubePfS_ # -- Begin function _Z19__device_stub__cubePfS_
.p2align 4, 0x90
.type _Z19__device_stub__cubePfS_,@function
_Z19__device_stub__cubePfS_: # @_Z19__device_stub__cubePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4cubePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__cubePfS_, .Lfunc_end0-_Z19__device_stub__cubePfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4cubePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4cubePfS_,@object # @_Z4cubePfS_
.section .rodata,"a",@progbits
.globl _Z4cubePfS_
.p2align 3, 0x0
_Z4cubePfS_:
.quad _Z19__device_stub__cubePfS_
.size _Z4cubePfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4cubePfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__cubePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4cubePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <cuda.h>
#include <vector>
#include <fstream>
#include <string>
#include <sstream>
#include <iostream>
#define BLOCK_WIDTH 512
/*
extern __shared__ stands for shared memory on device, which has two "warps" of 32 threads.
Google CUDA shared memory and warps.
To replace extern __shared__ int __smem[]; which requires you to explicitly
know the data type is integer in advance. But input file could be int, float, or double.
Since we don't know the data type of shared meomry __smem[], we use
template<class T> where T stands for all possible data types. We also
need to instantiate all possible data types later
In return (T *) __smem; it is data type conversion
Suggest to figure out difference between overload, override, redefine
*/
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T *) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T *) __smem;
}
};
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: Global memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countGlobalMem(T *g_idata, int *g_odata, int N) {
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
int gi = 0;
if (i < N) {
if (g_idata[i] == 1000) {
atomicAdd(&g_odata[9], 1);
} else {
gi = (int) g_idata[i] / 100;
atomicAdd(&g_odata[gi], 1);
}
}
}
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: shared memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countSharedMem(T *g_idata, int *g_odata, int N, int maxNum, int barrelSize) {
/*
Each block has a sdata
*/
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
int numBarrel = maxNum/barrelSize;
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
//gi is group/barrel index
int gi = 0;
if (i < N) {
if (g_idata[i] == maxNum) {
atomicAdd(&sdata[numBarrel-1], 1);
} else {
gi = (int) g_idata[i] / barrelSize;
atomicAdd(&sdata[gi], 1);
}
}
//wait until sdata[0~9] in all blocks are ready
__syncthreads();
/*
every block has threadIdx.x from 0 to 511
size of g_odata is numBarrel * blocks
sum of all blocks is done in myCountTest(), note there
is += when output to "q2b.txt"
*/
if (tid < numBarrel) {
g_odata[blockIdx.x * numBarrel + tid] = sdata[tid];
}
}
//////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: prefix sum (Naiive)
///////////////////////////////////////////////////////////////////////////////
int nextPowerOf2(int x)
{
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
__global__ void scan(int *d_idata, int *d_odata, int N) {
extern __shared__ int sdata[];
//cunyi
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
sdata[threadIdx.x] = d_idata[i];
//printf("\n sdata[%d]: %d", i, sdata[threadIdx.x]);
}
for (unsigned int stride = 1; stride <= threadIdx.x; stride *= 2) {
__syncthreads();
int in1 = sdata[threadIdx.x - stride];
__syncthreads();
sdata[threadIdx.x] += in1;
}
__syncthreads();
if(i < N) {
d_odata[threadIdx.x] = sdata[threadIdx.x];
//printf("\n sdata[%d]: %d", i, d_odata[threadIdx.x]);
}
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countGlobalMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countGMWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countGlobalMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N);
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countSharedMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countSWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N, int maxNum, int barrelSize) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countSharedMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N, maxNum, barrelSize);
}
/////////////////////////////////////////////////////////////////////////////////
// Instantiate Template
/////////////////////////////////////////////////////////////////////////////////
template void
countGMWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata, int N);
template void
countGMWrapper<float>(int threads, int blocks, float *g_idata, int *g_odata, int N);
template void
countGMWrapper<double>(int threads, int blocks, double *g_idata, int *g_odata, int N);
template void
countSWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata ,int N, int maxNum, int barrelSize);
//////////////////////////////////////////////////////////////////////////////////
// Test Function
//////////////////////////////////////////////////////////////////////////////////
void myCountTest(const char* filename) {
int numBarrel = 10;
//read test file and decide size of array
std::vector<int> data;
std::string line_;
std::ifstream file_(filename);
if(file_.is_open()) {
while (getline(file_, line_)) {
std::stringstream ss(line_);
int i;
while(ss>>i) {
data.push_back(i);
if (ss.peek() == ',' || ss.peek() == ' ') {
ss.ignore();
}
}
}
file_.close();
}
int num_els = data.size();
int numBlocks = num_els/BLOCK_WIDTH + 1;
//Start to run Kernel_a
int *d_in = NULL;
int *d_out = NULL;
cudaMalloc( (void **) &d_in, num_els * sizeof(int));
cudaMalloc( (void **) &d_out, numBarrel * sizeof(int));
int *in = (int *) malloc(num_els * sizeof(int));
int *out = (int *) malloc(numBarrel * sizeof(int));
in = &data[0];
std::vector<int> v(10);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out);
cudaMemcpy(d_in, in, num_els * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, numBarrel * sizeof(int), cudaMemcpyHostToDevice);
countGMWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out, num_els);
cudaMemcpy(out, d_out, numBarrel * sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream fout1("q2a.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout1.is_open()) {
fout1 << "\n Count[" <<i<<"]: " <<out[i];
}
}
fout1.close();
fout1.clear();
cudaFree(d_out);
//free(out);
//d_in is not cleaned because we are going to run more cuda kernels using d_in
free(in);
//cudaFree(d_in);
//Start to run Kernel_b, almost the same as kernel_a
int *d_out_b = NULL;
cudaMalloc( (void **) &d_out_b, numBarrel * numBlocks * sizeof(int));
int *out_b = (int *) malloc(numBarrel * numBlocks * sizeof(int));
//size of out_b is changed
v.resize(numBarrel * numBlocks);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_b);
cudaMemcpy(d_out_b, out_b, numBarrel * numBlocks * sizeof(int), cudaMemcpyHostToDevice);
countSWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out ,num_els, 1000, 100);
cudaMemcpy(out_b, d_out_b, numBarrel * numBlocks * sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream fout2("q2b.txt", std::ios::app);
int out_b_all;
//int B[numBarrel];
for(int i = 0; i < numBarrel; i++) {
out_b_all = 0;
for (int j = 0; j < numBlocks; j++)
out_b_all += out_b[i + j * numBarrel];
//B[i] = out_b_all;
if(fout2.is_open()) {
fout2 << "\n Count[" <<i<<"]: " <<out_b_all;
}
}
fout2.close();
fout2.clear();
cudaFree(d_out_b);
free(out_b);
cudaFree(d_in);
//start to run Kernel_c
int n3 = nextPowerOf2(numBarrel);
int *d_out_c = NULL;
int *d_in_c = NULL;
int *out_c = (int *) malloc(n3 * sizeof(int));
v.resize(n3);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_c);
cudaMalloc( (void **) &d_in_c, n3 * sizeof(int));
cudaMalloc( (void **) &d_out_c, n3 * sizeof(int));
int *in_test = (int *) malloc(n3 * sizeof(int));
std::vector<int> in_c;
for (int i = 0; i < n3; i++) {
if (i < numBarrel) {
in_c.push_back(out[i]);
} else {
in_c.push_back(0);
}
//printf("\n c: %d", in_c[i]);
}
in_test = &in_c[0];
cudaMemcpy(d_in_c, in_test, n3 * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out_c, out_c, n3 * sizeof(int), cudaMemcpyHostToDevice);
scan<<<1, n3, n3*sizeof(int)>>>(d_in_c, d_out_c, n3);
cudaMemcpy(out_c, d_out_c, n3 * sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream fout3("q2c.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout3.is_open()) {
fout3 << "\n prescan[" <<i<<"]: " <<out_c[i];
}
}
fout3.close();
fout3.clear();
}
int main(int argc, char **argv) {
myCountTest("inp.txt");
return 0;
} | code for sm_80
Function : _Z14countSharedMemIiLi512EEvPT_Piiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R0, c[0x0][0x178] ; /* 0x00005e0000007a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0030*/ IABS R7, c[0x0][0x174] ; /* 0x00005d0000077a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e620000209400 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0070*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*0080*/ BSSY B0, 0x390 ; /* 0x0000030000007945 */
/* 0x000fe20003800000 */
/*0090*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*00a0*/ ISETP.LE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf03270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*00d0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fcc0007ffe0ff */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002a4000021f000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*0100*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x004fc800078e0a03 */
/*0110*/ IMAD R5, R5, R0, RZ ; /* 0x0000000005057224 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fc800078e0002 */
/*0130*/ IMAD R2, R6, 0x200, R9 ; /* 0x0000020006027824 */
/* 0x001fe400078e0209 */
/*0140*/ IMAD.HI.U32 R3, R5, R7, RZ ; /* 0x0000000705037227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0160*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fe200078e0207 */
/*0170*/ LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff047a12 */
/* 0x000fc800078e33ff */
/*0180*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f44070 */
/*0190*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P2, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f46070 */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc60003f25270 */
/*01f0*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fca00078e0a03 */
/*0200*/ SEL R8, R4, R3, !P1 ; /* 0x0000000304087207 */
/* 0x000fe20004800000 */
/*0210*/ @P2 BRA 0x380 ; /* 0x0000016000002947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0240*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0250*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x004fda0003f05270 */
/*0260*/ @!P0 BRA 0x360 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0270*/ IABS R3, R2 ; /* 0x0000000200037213 */
/* 0x000fe40000000000 */
/*0280*/ LOP3.LUT R2, R2, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0002027a12 */
/* 0x000fc600078e3cff */
/*0290*/ IMAD.HI.U32 R5, R5, R3, RZ ; /* 0x0000000305057227 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.GE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f66270 */
/*02b0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*02c0*/ IMAD R3, R0, R7, R3 ; /* 0x0000000700037224 */
/* 0x000fca00078e0203 */
/*02d0*/ ISETP.GT.U32.AND P2, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f44070 */
/*02e0*/ @!P2 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a00 */
/*02f0*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06070 */
/*0310*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fca0007ffe0ff */
/*0320*/ @!P3 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05b224 */
/* 0x000fca00078e0a05 */
/*0330*/ SEL R4, R4, R5, !P1 ; /* 0x0000000504047207 */
/* 0x000fca0004800000 */
/*0340*/ ATOMS.POPC.INC.32 RZ, [R4.X4+URZ] ; /* 0x0000000004ff7f8c */
/* 0x0001e2000d00403f */
/*0350*/ BRA 0x380 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0360*/ LEA R0, R8, 0xfffffffc, 0x2 ; /* 0xfffffffc08007811 */
/* 0x000fca00078e10ff */
/*0370*/ ATOMS.POPC.INC.32 RZ, [R0+URZ] ; /* 0x0000000000ff7f8c */
/* 0x0001e4000d00003f */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.GE.U32.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fda0003f06070 */
/*03b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03c0*/ LDS R5, [R9.X4] ; /* 0x0000000009057984 */
/* 0x000e620000004800 */
/*03d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*03e0*/ IMAD R2, R8, R6, R9 ; /* 0x0000000608027224 */
/* 0x000fc800078e0209 */
/*03f0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14countGlobalMemIdLi512EEvPT_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ LEA R2, R2, R3, 0x9 ; /* 0x0000000302027211 */
/* 0x001fc800078e48ff */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DSETP.NEU.AND P0, PT, R2, 1000, PT ; /* 0x408f40000200742a */
/* 0x004e1c0003f0d000 */
/*00b0*/ @!P0 BRA 0x150 ; /* 0x0000009000008947 */
/* 0x001fea0003800000 */
/*00c0*/ F2I.F64.TRUNC R2, R2 ; /* 0x0000000200027311 */
/* 0x000e22000030d100 */
/*00d0*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.HI R0, R2, 0x51eb851f, RZ ; /* 0x51eb851f02007827 */
/* 0x001fca00078e02ff */
/*0100*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*0110*/ LEA.HI.SX32 R5, R0, R5, 0x1b ; /* 0x0000000500057211 */
/* 0x000fca00078fdaff */
/*0120*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*0130*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e186 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0160*/ VOTEU.ANY UR8, UPT, PT ; /* 0x0000000000087886 */
/* 0x000fe400038e0100 */
/*0170*/ UFLO.U32 UR9, UR8 ; /* 0x00000008000972bd */
/* 0x000fe200080e0000 */
/*0180*/ POPC R5, UR8 ; /* 0x0000000800057d09 */
/* 0x000e620008000000 */
/*0190*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*01a0*/ UIADD3 UR4, UP0, UR4, 0x24, URZ ; /* 0x0000002404047890 */
/* 0x000fc8000ff1e03f */
/*01b0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*01c0*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fc80008000f00 */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*01e0*/ ISETP.EQ.U32.AND P0, PT, R0, UR9, PT ; /* 0x0000000900007c0c */
/* 0x001fda000bf02070 */
/*01f0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e186 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14countGlobalMemIfLi512EEvPT_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, 0x200, R3 ; /* 0x0000020002027824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0004 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FSETP.NEU.AND P0, PT, R0, 1000, PT ; /* 0x447a00000000780b */
/* 0x004fda0003f0d000 */
/*00b0*/ @!P0 BRA 0x140 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*00c0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e22000020f100 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.HI R2, R0, 0x51eb851f, RZ ; /* 0x51eb851f00027827 */
/* 0x001fca00078e02ff */
/*00f0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0100*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fca00078fdaff */
/*0110*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0204 */
/*0120*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e186 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0150*/ VOTEU.ANY UR8, UPT, PT ; /* 0x0000000000087886 */
/* 0x000fe400038e0100 */
/*0160*/ UFLO.U32 UR9, UR8 ; /* 0x00000008000972bd */
/* 0x000fe200080e0000 */
/*0170*/ POPC R5, UR8 ; /* 0x0000000800057d09 */
/* 0x000e620008000000 */
/*0180*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0190*/ UIADD3 UR4, UP0, UR4, 0x24, URZ ; /* 0x0000002404047890 */
/* 0x000fc8000ff1e03f */
/*01a0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*01b0*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fc80008000f00 */
/*01c0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*01d0*/ ISETP.EQ.U32.AND P0, PT, R0, UR9, PT ; /* 0x0000000900007c0c */
/* 0x001fda000bf02070 */
/*01e0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e186 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14countGlobalMemIiLi512EEvPT_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, 0x200, R3 ; /* 0x0000020002027824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R0, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0000 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0x3e8, PT ; /* 0x000003e80200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @!P0 BRA 0x130 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.HI R2, R2, 0x51eb851f, RZ ; /* 0x51eb851f02027827 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*00f0*/ LEA.HI.SX32 R3, R2, R3, 0x1b ; /* 0x0000000302037211 */
/* 0x000fca00078fdaff */
/*0100*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0200 */
/*0110*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e186 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0140*/ VOTEU.ANY UR8, UPT, PT ; /* 0x0000000000087886 */
/* 0x000fe400038e0100 */
/*0150*/ UFLO.U32 UR9, UR8 ; /* 0x00000008000972bd */
/* 0x000fe200080e0000 */
/*0160*/ POPC R5, UR8 ; /* 0x0000000800057d09 */
/* 0x000e620008000000 */
/*0170*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0180*/ UIADD3 UR4, UP0, UR4, 0x24, URZ ; /* 0x0000002404047890 */
/* 0x000fc8000ff1e03f */
/*0190*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*01a0*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fc80008000f00 */
/*01b0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*01c0*/ ISETP.EQ.U32.AND P0, PT, R0, UR9, PT ; /* 0x0000000900007c0c */
/* 0x001fda000bf02070 */
/*01d0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e186 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4scanPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fe200078e0207 */
/*0060*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0xd0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e40000004800 */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*0100*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ IADD3 R2, R7, -R0, RZ ; /* 0x8000000007027210 */
/* 0x001fe40007ffe0ff */
/*0130*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f26070 */
/*0150*/ LDS R2, [R2.X4] ; /* 0x0000000002027984 */
/* 0x000fe80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ LDS R3, [R7.X4] ; /* 0x0000000007037984 */
/* 0x000e240000004800 */
/*0180*/ IMAD.IADD R3, R2, 0x1, R3 ; /* 0x0000000102037824 */
/* 0x001fca00078e0203 */
/*0190*/ STS [R7.X4], R3 ; /* 0x0000000307007388 */
/* 0x0001e20000004800 */
/*01a0*/ @P1 BRA 0x100 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*01b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e620000004800 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x001fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <cuda.h>
#include <vector>
#include <fstream>
#include <string>
#include <sstream>
#include <iostream>
#define BLOCK_WIDTH 512
/*
extern __shared__ stands for shared memory on device, which has two "warps" of 32 threads.
Google CUDA shared memory and warps.
To replace extern __shared__ int __smem[]; which requires you to explicitly
know the data type is integer in advance. But input file could be int, float, or double.
Since we don't know the data type of shared meomry __smem[], we use
template<class T> where T stands for all possible data types. We also
need to instantiate all possible data types later
In return (T *) __smem; it is data type conversion
Suggest to figure out difference between overload, override, redefine
*/
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T *) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T *) __smem;
}
};
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: Global memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countGlobalMem(T *g_idata, int *g_odata, int N) {
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
int gi = 0;
if (i < N) {
if (g_idata[i] == 1000) {
atomicAdd(&g_odata[9], 1);
} else {
gi = (int) g_idata[i] / 100;
atomicAdd(&g_odata[gi], 1);
}
}
}
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: shared memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countSharedMem(T *g_idata, int *g_odata, int N, int maxNum, int barrelSize) {
/*
Each block has a sdata
*/
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
int numBarrel = maxNum/barrelSize;
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
//gi is group/barrel index
int gi = 0;
if (i < N) {
if (g_idata[i] == maxNum) {
atomicAdd(&sdata[numBarrel-1], 1);
} else {
gi = (int) g_idata[i] / barrelSize;
atomicAdd(&sdata[gi], 1);
}
}
//wait until sdata[0~9] in all blocks are ready
__syncthreads();
/*
every block has threadIdx.x from 0 to 511
size of g_odata is numBarrel * blocks
sum of all blocks is done in myCountTest(), note there
is += when output to "q2b.txt"
*/
if (tid < numBarrel) {
g_odata[blockIdx.x * numBarrel + tid] = sdata[tid];
}
}
//////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: prefix sum (Naiive)
///////////////////////////////////////////////////////////////////////////////
int nextPowerOf2(int x)
{
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
__global__ void scan(int *d_idata, int *d_odata, int N) {
extern __shared__ int sdata[];
//cunyi
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
sdata[threadIdx.x] = d_idata[i];
//printf("\n sdata[%d]: %d", i, sdata[threadIdx.x]);
}
for (unsigned int stride = 1; stride <= threadIdx.x; stride *= 2) {
__syncthreads();
int in1 = sdata[threadIdx.x - stride];
__syncthreads();
sdata[threadIdx.x] += in1;
}
__syncthreads();
if(i < N) {
d_odata[threadIdx.x] = sdata[threadIdx.x];
//printf("\n sdata[%d]: %d", i, d_odata[threadIdx.x]);
}
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countGlobalMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countGMWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countGlobalMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N);
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countSharedMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countSWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N, int maxNum, int barrelSize) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countSharedMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N, maxNum, barrelSize);
}
/////////////////////////////////////////////////////////////////////////////////
// Instantiate Template
/////////////////////////////////////////////////////////////////////////////////
template void
countGMWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata, int N);
template void
countGMWrapper<float>(int threads, int blocks, float *g_idata, int *g_odata, int N);
template void
countGMWrapper<double>(int threads, int blocks, double *g_idata, int *g_odata, int N);
template void
countSWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata ,int N, int maxNum, int barrelSize);
//////////////////////////////////////////////////////////////////////////////////
// Test Function
//////////////////////////////////////////////////////////////////////////////////
void myCountTest(const char* filename) {
int numBarrel = 10;
//read test file and decide size of array
std::vector<int> data;
std::string line_;
std::ifstream file_(filename);
if(file_.is_open()) {
while (getline(file_, line_)) {
std::stringstream ss(line_);
int i;
while(ss>>i) {
data.push_back(i);
if (ss.peek() == ',' || ss.peek() == ' ') {
ss.ignore();
}
}
}
file_.close();
}
int num_els = data.size();
int numBlocks = num_els/BLOCK_WIDTH + 1;
//Start to run Kernel_a
int *d_in = NULL;
int *d_out = NULL;
cudaMalloc( (void **) &d_in, num_els * sizeof(int));
cudaMalloc( (void **) &d_out, numBarrel * sizeof(int));
int *in = (int *) malloc(num_els * sizeof(int));
int *out = (int *) malloc(numBarrel * sizeof(int));
in = &data[0];
std::vector<int> v(10);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out);
cudaMemcpy(d_in, in, num_els * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out, out, numBarrel * sizeof(int), cudaMemcpyHostToDevice);
countGMWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out, num_els);
cudaMemcpy(out, d_out, numBarrel * sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream fout1("q2a.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout1.is_open()) {
fout1 << "\n Count[" <<i<<"]: " <<out[i];
}
}
fout1.close();
fout1.clear();
cudaFree(d_out);
//free(out);
//d_in is not cleaned because we are going to run more cuda kernels using d_in
free(in);
//cudaFree(d_in);
//Start to run Kernel_b, almost the same as kernel_a
int *d_out_b = NULL;
cudaMalloc( (void **) &d_out_b, numBarrel * numBlocks * sizeof(int));
int *out_b = (int *) malloc(numBarrel * numBlocks * sizeof(int));
//size of out_b is changed
v.resize(numBarrel * numBlocks);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_b);
cudaMemcpy(d_out_b, out_b, numBarrel * numBlocks * sizeof(int), cudaMemcpyHostToDevice);
countSWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out ,num_els, 1000, 100);
cudaMemcpy(out_b, d_out_b, numBarrel * numBlocks * sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream fout2("q2b.txt", std::ios::app);
int out_b_all;
//int B[numBarrel];
for(int i = 0; i < numBarrel; i++) {
out_b_all = 0;
for (int j = 0; j < numBlocks; j++)
out_b_all += out_b[i + j * numBarrel];
//B[i] = out_b_all;
if(fout2.is_open()) {
fout2 << "\n Count[" <<i<<"]: " <<out_b_all;
}
}
fout2.close();
fout2.clear();
cudaFree(d_out_b);
free(out_b);
cudaFree(d_in);
//start to run Kernel_c
int n3 = nextPowerOf2(numBarrel);
int *d_out_c = NULL;
int *d_in_c = NULL;
int *out_c = (int *) malloc(n3 * sizeof(int));
v.resize(n3);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_c);
cudaMalloc( (void **) &d_in_c, n3 * sizeof(int));
cudaMalloc( (void **) &d_out_c, n3 * sizeof(int));
int *in_test = (int *) malloc(n3 * sizeof(int));
std::vector<int> in_c;
for (int i = 0; i < n3; i++) {
if (i < numBarrel) {
in_c.push_back(out[i]);
} else {
in_c.push_back(0);
}
//printf("\n c: %d", in_c[i]);
}
in_test = &in_c[0];
cudaMemcpy(d_in_c, in_test, n3 * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_out_c, out_c, n3 * sizeof(int), cudaMemcpyHostToDevice);
scan<<<1, n3, n3*sizeof(int)>>>(d_in_c, d_out_c, n3);
cudaMemcpy(out_c, d_out_c, n3 * sizeof(int), cudaMemcpyDeviceToHost);
std::ofstream fout3("q2c.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout3.is_open()) {
fout3 << "\n prescan[" <<i<<"]: " <<out_c[i];
}
}
fout3.close();
fout3.clear();
}
int main(int argc, char **argv) {
myCountTest("inp.txt");
return 0;
} | #include <math.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <fstream>
#include <string>
#include <sstream>
#include <iostream>
#define BLOCK_WIDTH 512
/*
extern __shared__ stands for shared memory on device, which has two "warps" of 32 threads.
Google CUDA shared memory and warps.
To replace extern __shared__ int __smem[]; which requires you to explicitly
know the data type is integer in advance. But input file could be int, float, or double.
Since we don't know the data type of shared meomry __smem[], we use
template<class T> where T stands for all possible data types. We also
need to instantiate all possible data types later
In return (T *) __smem; it is data type conversion
Suggest to figure out difference between overload, override, redefine
*/
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T *) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T *) __smem;
}
};
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: Global memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countGlobalMem(T *g_idata, int *g_odata, int N) {
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
int gi = 0;
if (i < N) {
if (g_idata[i] == 1000) {
atomicAdd(&g_odata[9], 1);
} else {
gi = (int) g_idata[i] / 100;
atomicAdd(&g_odata[gi], 1);
}
}
}
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: shared memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countSharedMem(T *g_idata, int *g_odata, int N, int maxNum, int barrelSize) {
/*
Each block has a sdata
*/
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
int numBarrel = maxNum/barrelSize;
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
//gi is group/barrel index
int gi = 0;
if (i < N) {
if (g_idata[i] == maxNum) {
atomicAdd(&sdata[numBarrel-1], 1);
} else {
gi = (int) g_idata[i] / barrelSize;
atomicAdd(&sdata[gi], 1);
}
}
//wait until sdata[0~9] in all blocks are ready
__syncthreads();
/*
every block has threadIdx.x from 0 to 511
size of g_odata is numBarrel * blocks
sum of all blocks is done in myCountTest(), note there
is += when output to "q2b.txt"
*/
if (tid < numBarrel) {
g_odata[blockIdx.x * numBarrel + tid] = sdata[tid];
}
}
//////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: prefix sum (Naiive)
///////////////////////////////////////////////////////////////////////////////
int nextPowerOf2(int x)
{
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
__global__ void scan(int *d_idata, int *d_odata, int N) {
extern __shared__ int sdata[];
//cunyi
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
sdata[threadIdx.x] = d_idata[i];
//printf("\n sdata[%d]: %d", i, sdata[threadIdx.x]);
}
for (unsigned int stride = 1; stride <= threadIdx.x; stride *= 2) {
__syncthreads();
int in1 = sdata[threadIdx.x - stride];
__syncthreads();
sdata[threadIdx.x] += in1;
}
__syncthreads();
if(i < N) {
d_odata[threadIdx.x] = sdata[threadIdx.x];
//printf("\n sdata[%d]: %d", i, d_odata[threadIdx.x]);
}
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countGlobalMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countGMWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countGlobalMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N);
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countSharedMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countSWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N, int maxNum, int barrelSize) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countSharedMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N, maxNum, barrelSize);
}
/////////////////////////////////////////////////////////////////////////////////
// Instantiate Template
/////////////////////////////////////////////////////////////////////////////////
template void
countGMWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata, int N);
template void
countGMWrapper<float>(int threads, int blocks, float *g_idata, int *g_odata, int N);
template void
countGMWrapper<double>(int threads, int blocks, double *g_idata, int *g_odata, int N);
template void
countSWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata ,int N, int maxNum, int barrelSize);
//////////////////////////////////////////////////////////////////////////////////
// Test Function
//////////////////////////////////////////////////////////////////////////////////
void myCountTest(const char* filename) {
int numBarrel = 10;
//read test file and decide size of array
std::vector<int> data;
std::string line_;
std::ifstream file_(filename);
if(file_.is_open()) {
while (getline(file_, line_)) {
std::stringstream ss(line_);
int i;
while(ss>>i) {
data.push_back(i);
if (ss.peek() == ',' || ss.peek() == ' ') {
ss.ignore();
}
}
}
file_.close();
}
int num_els = data.size();
int numBlocks = num_els/BLOCK_WIDTH + 1;
//Start to run Kernel_a
int *d_in = NULL;
int *d_out = NULL;
hipMalloc( (void **) &d_in, num_els * sizeof(int));
hipMalloc( (void **) &d_out, numBarrel * sizeof(int));
int *in = (int *) malloc(num_els * sizeof(int));
int *out = (int *) malloc(numBarrel * sizeof(int));
in = &data[0];
std::vector<int> v(10);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out);
hipMemcpy(d_in, in, num_els * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out, out, numBarrel * sizeof(int), hipMemcpyHostToDevice);
countGMWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out, num_els);
hipMemcpy(out, d_out, numBarrel * sizeof(int), hipMemcpyDeviceToHost);
std::ofstream fout1("q2a.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout1.is_open()) {
fout1 << "\n Count[" <<i<<"]: " <<out[i];
}
}
fout1.close();
fout1.clear();
hipFree(d_out);
//free(out);
//d_in is not cleaned because we are going to run more cuda kernels using d_in
free(in);
//cudaFree(d_in);
//Start to run Kernel_b, almost the same as kernel_a
int *d_out_b = NULL;
hipMalloc( (void **) &d_out_b, numBarrel * numBlocks * sizeof(int));
int *out_b = (int *) malloc(numBarrel * numBlocks * sizeof(int));
//size of out_b is changed
v.resize(numBarrel * numBlocks);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_b);
hipMemcpy(d_out_b, out_b, numBarrel * numBlocks * sizeof(int), hipMemcpyHostToDevice);
countSWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out ,num_els, 1000, 100);
hipMemcpy(out_b, d_out_b, numBarrel * numBlocks * sizeof(int), hipMemcpyDeviceToHost);
std::ofstream fout2("q2b.txt", std::ios::app);
int out_b_all;
//int B[numBarrel];
for(int i = 0; i < numBarrel; i++) {
out_b_all = 0;
for (int j = 0; j < numBlocks; j++)
out_b_all += out_b[i + j * numBarrel];
//B[i] = out_b_all;
if(fout2.is_open()) {
fout2 << "\n Count[" <<i<<"]: " <<out_b_all;
}
}
fout2.close();
fout2.clear();
hipFree(d_out_b);
free(out_b);
hipFree(d_in);
//start to run Kernel_c
int n3 = nextPowerOf2(numBarrel);
int *d_out_c = NULL;
int *d_in_c = NULL;
int *out_c = (int *) malloc(n3 * sizeof(int));
v.resize(n3);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_c);
hipMalloc( (void **) &d_in_c, n3 * sizeof(int));
hipMalloc( (void **) &d_out_c, n3 * sizeof(int));
int *in_test = (int *) malloc(n3 * sizeof(int));
std::vector<int> in_c;
for (int i = 0; i < n3; i++) {
if (i < numBarrel) {
in_c.push_back(out[i]);
} else {
in_c.push_back(0);
}
//printf("\n c: %d", in_c[i]);
}
in_test = &in_c[0];
hipMemcpy(d_in_c, in_test, n3 * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out_c, out_c, n3 * sizeof(int), hipMemcpyHostToDevice);
scan<<<1, n3, n3*sizeof(int)>>>(d_in_c, d_out_c, n3);
hipMemcpy(out_c, d_out_c, n3 * sizeof(int), hipMemcpyDeviceToHost);
std::ofstream fout3("q2c.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout3.is_open()) {
fout3 << "\n prescan[" <<i<<"]: " <<out_c[i];
}
}
fout3.close();
fout3.clear();
}
int main(int argc, char **argv) {
myCountTest("inp.txt");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <math.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <fstream>
#include <string>
#include <sstream>
#include <iostream>
#define BLOCK_WIDTH 512
/*
extern __shared__ stands for shared memory on device, which has two "warps" of 32 threads.
Google CUDA shared memory and warps.
To replace extern __shared__ int __smem[]; which requires you to explicitly
know the data type is integer in advance. But input file could be int, float, or double.
Since we don't know the data type of shared meomry __smem[], we use
template<class T> where T stands for all possible data types. We also
need to instantiate all possible data types later
In return (T *) __smem; it is data type conversion
Suggest to figure out difference between overload, override, redefine
*/
template<class T>
struct SharedMemory {
__device__ inline operator T *() {
extern __shared__ int __smem[];
return (T *) __smem;
}
__device__ inline operator const T *() const {
extern __shared__ int __smem[];
return (T *) __smem;
}
};
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: Global memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countGlobalMem(T *g_idata, int *g_odata, int N) {
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
int gi = 0;
if (i < N) {
if (g_idata[i] == 1000) {
atomicAdd(&g_odata[9], 1);
} else {
gi = (int) g_idata[i] / 100;
atomicAdd(&g_odata[gi], 1);
}
}
}
/////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: shared memory
/////////////////////////////////////////////////////////////////////////////
template<class T, int blockSize>
__global__ void countSharedMem(T *g_idata, int *g_odata, int N, int maxNum, int barrelSize) {
/*
Each block has a sdata
*/
extern __shared__ int sdata[];
unsigned int tid = threadIdx.x;
int numBarrel = maxNum/barrelSize;
unsigned int i = blockSize * blockIdx.x + threadIdx.x;
//gi is group/barrel index
int gi = 0;
if (i < N) {
if (g_idata[i] == maxNum) {
atomicAdd(&sdata[numBarrel-1], 1);
} else {
gi = (int) g_idata[i] / barrelSize;
atomicAdd(&sdata[gi], 1);
}
}
//wait until sdata[0~9] in all blocks are ready
__syncthreads();
/*
every block has threadIdx.x from 0 to 511
size of g_odata is numBarrel * blocks
sum of all blocks is done in myCountTest(), note there
is += when output to "q2b.txt"
*/
if (tid < numBarrel) {
g_odata[blockIdx.x * numBarrel + tid] = sdata[tid];
}
}
//////////////////////////////////////////////////////////////////////////////
// CUDA Kernel: prefix sum (Naiive)
///////////////////////////////////////////////////////////////////////////////
int nextPowerOf2(int x)
{
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
__global__ void scan(int *d_idata, int *d_odata, int N) {
extern __shared__ int sdata[];
//cunyi
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
sdata[threadIdx.x] = d_idata[i];
//printf("\n sdata[%d]: %d", i, sdata[threadIdx.x]);
}
for (unsigned int stride = 1; stride <= threadIdx.x; stride *= 2) {
__syncthreads();
int in1 = sdata[threadIdx.x - stride];
__syncthreads();
sdata[threadIdx.x] += in1;
}
__syncthreads();
if(i < N) {
d_odata[threadIdx.x] = sdata[threadIdx.x];
//printf("\n sdata[%d]: %d", i, d_odata[threadIdx.x]);
}
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countGlobalMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countGMWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countGlobalMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N);
}
///////////////////////////////////////////////////////////////////////////////
// Wrapper for countSharedMem
///////////////////////////////////////////////////////////////////////////////
template<class T>
void countSWrapper(int threads, int blocks, T *g_idata, int *g_odata ,int N, int maxNum, int barrelSize) {
/*
1D block and 1D grid
*/
dim3 dimBlock(threads, 1, 1);
dim3 dimGrid(blocks, 1, 1);
int smemSize = threads * sizeof (T);
countSharedMem<T, BLOCK_WIDTH><<<dimGrid, dimBlock, smemSize>>>(g_idata, g_odata, N, maxNum, barrelSize);
}
/////////////////////////////////////////////////////////////////////////////////
// Instantiate Template
/////////////////////////////////////////////////////////////////////////////////
template void
countGMWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata, int N);
template void
countGMWrapper<float>(int threads, int blocks, float *g_idata, int *g_odata, int N);
template void
countGMWrapper<double>(int threads, int blocks, double *g_idata, int *g_odata, int N);
template void
countSWrapper<int>(int threads, int blocks, int *g_idata, int *g_odata ,int N, int maxNum, int barrelSize);
//////////////////////////////////////////////////////////////////////////////////
// Test Function
//////////////////////////////////////////////////////////////////////////////////
void myCountTest(const char* filename) {
int numBarrel = 10;
//read test file and decide size of array
std::vector<int> data;
std::string line_;
std::ifstream file_(filename);
if(file_.is_open()) {
while (getline(file_, line_)) {
std::stringstream ss(line_);
int i;
while(ss>>i) {
data.push_back(i);
if (ss.peek() == ',' || ss.peek() == ' ') {
ss.ignore();
}
}
}
file_.close();
}
int num_els = data.size();
int numBlocks = num_els/BLOCK_WIDTH + 1;
//Start to run Kernel_a
int *d_in = NULL;
int *d_out = NULL;
hipMalloc( (void **) &d_in, num_els * sizeof(int));
hipMalloc( (void **) &d_out, numBarrel * sizeof(int));
int *in = (int *) malloc(num_els * sizeof(int));
int *out = (int *) malloc(numBarrel * sizeof(int));
in = &data[0];
std::vector<int> v(10);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out);
hipMemcpy(d_in, in, num_els * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out, out, numBarrel * sizeof(int), hipMemcpyHostToDevice);
countGMWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out, num_els);
hipMemcpy(out, d_out, numBarrel * sizeof(int), hipMemcpyDeviceToHost);
std::ofstream fout1("q2a.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout1.is_open()) {
fout1 << "\n Count[" <<i<<"]: " <<out[i];
}
}
fout1.close();
fout1.clear();
hipFree(d_out);
//free(out);
//d_in is not cleaned because we are going to run more cuda kernels using d_in
free(in);
//cudaFree(d_in);
//Start to run Kernel_b, almost the same as kernel_a
int *d_out_b = NULL;
hipMalloc( (void **) &d_out_b, numBarrel * numBlocks * sizeof(int));
int *out_b = (int *) malloc(numBarrel * numBlocks * sizeof(int));
//size of out_b is changed
v.resize(numBarrel * numBlocks);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_b);
hipMemcpy(d_out_b, out_b, numBarrel * numBlocks * sizeof(int), hipMemcpyHostToDevice);
countSWrapper(BLOCK_WIDTH, numBlocks, d_in, d_out ,num_els, 1000, 100);
hipMemcpy(out_b, d_out_b, numBarrel * numBlocks * sizeof(int), hipMemcpyDeviceToHost);
std::ofstream fout2("q2b.txt", std::ios::app);
int out_b_all;
//int B[numBarrel];
for(int i = 0; i < numBarrel; i++) {
out_b_all = 0;
for (int j = 0; j < numBlocks; j++)
out_b_all += out_b[i + j * numBarrel];
//B[i] = out_b_all;
if(fout2.is_open()) {
fout2 << "\n Count[" <<i<<"]: " <<out_b_all;
}
}
fout2.close();
fout2.clear();
hipFree(d_out_b);
free(out_b);
hipFree(d_in);
//start to run Kernel_c
int n3 = nextPowerOf2(numBarrel);
int *d_out_c = NULL;
int *d_in_c = NULL;
int *out_c = (int *) malloc(n3 * sizeof(int));
v.resize(n3);
std::fill(v.begin(), v.end(), 0);
std::copy(v.begin(), v.end(), out_c);
hipMalloc( (void **) &d_in_c, n3 * sizeof(int));
hipMalloc( (void **) &d_out_c, n3 * sizeof(int));
int *in_test = (int *) malloc(n3 * sizeof(int));
std::vector<int> in_c;
for (int i = 0; i < n3; i++) {
if (i < numBarrel) {
in_c.push_back(out[i]);
} else {
in_c.push_back(0);
}
//printf("\n c: %d", in_c[i]);
}
in_test = &in_c[0];
hipMemcpy(d_in_c, in_test, n3 * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_out_c, out_c, n3 * sizeof(int), hipMemcpyHostToDevice);
scan<<<1, n3, n3*sizeof(int)>>>(d_in_c, d_out_c, n3);
hipMemcpy(out_c, d_out_c, n3 * sizeof(int), hipMemcpyDeviceToHost);
std::ofstream fout3("q2c.txt", std::ios::app);
for(int i = 0; i < numBarrel; i++) {
if(fout3.is_open()) {
fout3 << "\n prescan[" <<i<<"]: " <<out_c[i];
}
}
fout3.close();
fout3.clear();
}
int main(int argc, char **argv) {
myCountTest("inp.txt");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPiS_i
.globl _Z4scanPiS_i
.p2align 8
.type _Z4scanPiS_i,@function
_Z4scanPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s2, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s5, v2, s2
global_load_b32 v1, v[1:2], off
v_lshl_add_u32 v2, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s4, 0
s_mov_b32 s3, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v1, v0, 2, 0
s_mov_b32 s5, 1
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s5, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_lshl_b32 s5, s5, 1
v_lshl_add_u32 v2, v2, 2, 0
v_cmp_gt_u32_e64 s2, s5, v0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
s_or_b32 s4, s2, s4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, 0, v0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPiS_i, .Lfunc_end0-_Z4scanPiS_i
.section .AMDGPU.csdata,"",@progbits
.section .text._Z14countGlobalMemIiLi512EEvPT_Pii,"axG",@progbits,_Z14countGlobalMemIiLi512EEvPT_Pii,comdat
.protected _Z14countGlobalMemIiLi512EEvPT_Pii
.globl _Z14countGlobalMemIiLi512EEvPT_Pii
.p2align 8
.type _Z14countGlobalMemIiLi512EEvPT_Pii,@function
_Z14countGlobalMemIiLi512EEvPT_Pii:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v2, v[0:1], off
v_mov_b32_e32 v0, 9
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0x3e8, v2
v_mul_hi_i32 v0, v2, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
v_add_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countGlobalMemIiLi512EEvPT_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z14countGlobalMemIiLi512EEvPT_Pii,"axG",@progbits,_Z14countGlobalMemIiLi512EEvPT_Pii,comdat
.Lfunc_end1:
.size _Z14countGlobalMemIiLi512EEvPT_Pii, .Lfunc_end1-_Z14countGlobalMemIiLi512EEvPT_Pii
.section .AMDGPU.csdata,"",@progbits
.section .text._Z14countGlobalMemIfLi512EEvPT_Pii,"axG",@progbits,_Z14countGlobalMemIfLi512EEvPT_Pii,comdat
.protected _Z14countGlobalMemIfLi512EEvPT_Pii
.globl _Z14countGlobalMemIfLi512EEvPT_Pii
.p2align 8
.type _Z14countGlobalMemIfLi512EEvPT_Pii,@function
_Z14countGlobalMemIfLi512EEvPT_Pii:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v2, v[0:1], off
v_mov_b32_e32 v0, 9
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 0x447a0000, v2
v_cvt_i32_f32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v0, v0, 0x51eb851f
v_lshrrev_b32_e32 v1, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countGlobalMemIfLi512EEvPT_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z14countGlobalMemIfLi512EEvPT_Pii,"axG",@progbits,_Z14countGlobalMemIfLi512EEvPT_Pii,comdat
.Lfunc_end2:
.size _Z14countGlobalMemIfLi512EEvPT_Pii, .Lfunc_end2-_Z14countGlobalMemIfLi512EEvPT_Pii
.section .AMDGPU.csdata,"",@progbits
.section .text._Z14countGlobalMemIdLi512EEvPT_Pii,"axG",@progbits,_Z14countGlobalMemIdLi512EEvPT_Pii,comdat
.protected _Z14countGlobalMemIdLi512EEvPT_Pii
.globl _Z14countGlobalMemIdLi512EEvPT_Pii
.p2align 8
.type _Z14countGlobalMemIdLi512EEvPT_Pii,@function
_Z14countGlobalMemIdLi512EEvPT_Pii:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB3_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b64 v[2:3], v[0:1], off
v_mov_b32_e32 v0, 9
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
v_cmpx_neq_f64_e32 0x408f4000, v[2:3]
v_cvt_i32_f64_e32 v0, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v0, v0, 0x51eb851f
v_lshrrev_b32_e32 v1, 31, v0
v_ashrrev_i32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countGlobalMemIdLi512EEvPT_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z14countGlobalMemIdLi512EEvPT_Pii,"axG",@progbits,_Z14countGlobalMemIdLi512EEvPT_Pii,comdat
.Lfunc_end3:
.size _Z14countGlobalMemIdLi512EEvPT_Pii, .Lfunc_end3-_Z14countGlobalMemIdLi512EEvPT_Pii
.section .AMDGPU.csdata,"",@progbits
.section .text._Z14countSharedMemIiLi512EEvPT_Piiii,"axG",@progbits,_Z14countSharedMemIiLi512EEvPT_Piiii,comdat
.protected _Z14countSharedMemIiLi512EEvPT_Piiii
.globl _Z14countSharedMemIiLi512EEvPT_Piiii
.p2align 8
.type _Z14countSharedMemIiLi512EEvPT_Piiii,@function
_Z14countSharedMemIiLi512EEvPT_Piiii:
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s5, s4
s_xor_b32 s6, s2, s4
s_load_b64 s[2:3], s[0:1], 0x10
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s8, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s3, 31
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s10, s3, s9
s_xor_b32 s4, s9, s4
s_xor_b32 s10, s10, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s7, v1
v_lshl_add_u32 v1, s15, 9, v0
s_mul_i32 s8, s8, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v1
s_mul_hi_u32 s8, s7, s8
s_add_i32 s7, s7, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s10, s7
s_mul_i32 s8, s7, s6
s_add_i32 s9, s7, 1
s_sub_i32 s8, s10, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s10, s8, s6
s_cmp_ge_u32 s8, s6
s_cselect_b32 s7, s9, s7
s_cselect_b32 s8, s10, s8
s_add_i32 s9, s7, 1
s_cmp_ge_u32 s8, s6
s_cselect_b32 s6, s9, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s6, s4
s_sub_i32 s2, s2, s4
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB4_6
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB4_3
s_ashr_i32 s6, s5, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s6
v_cvt_f32_u32_e32 v2, s5
s_sub_i32 s7, 0, s5
v_add_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
v_xor_b32_e32 v1, v1, v4
v_xor_b32_e32 v4, s6, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_mul_lo_u32 v3, v2, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v3, 1, v2
v_subrev_nc_u32_e32 v5, s5, v1
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v2, v2, v3
v_cmp_le_u32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v2
v_cndmask_b32_e32 v1, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
v_sub_nc_u32_e32 v2, v1, v4
.LBB4_3:
s_and_not1_saveexec_b32 s3, s3
s_add_i32 s5, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s5
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v2, 2, 0
v_mov_b32_e32 v2, 1
ds_add_u32 v1, v2
.LBB4_6:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB4_8
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v3, v0, 2, 0
v_mad_u64_u32 v[1:2], null, s2, s15, v[0:1]
v_mov_b32_e32 v2, 0
ds_load_b32 v3, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB4_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countSharedMemIiLi512EEvPT_Piiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z14countSharedMemIiLi512EEvPT_Piiii,"axG",@progbits,_Z14countSharedMemIiLi512EEvPT_Piiii,comdat
.Lfunc_end4:
.size _Z14countSharedMemIiLi512EEvPT_Piiii, .Lfunc_end4-_Z14countSharedMemIiLi512EEvPT_Piiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sdata
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4scanPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countGlobalMemIiLi512EEvPT_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countGlobalMemIiLi512EEvPT_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countGlobalMemIfLi512EEvPT_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countGlobalMemIfLi512EEvPT_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countGlobalMemIdLi512EEvPT_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countGlobalMemIdLi512EEvPT_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countSharedMemIiLi512EEvPT_Piiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countSharedMemIiLi512EEvPT_Piiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* @file add1.cu
* @brief this example is for testing cudaMemcpyFrom/ToSymbol
*
* @date Apr 27, 2011
* @author Magda Slawinska, magg __at_ gatech __dot_ edu
*/
#include <stdio.h>
#include <cuda.h>
#define MAX 14
__device__ char name_device[MAX];
__device__ int tab_d[MAX];
__constant__ __device__ char hw[] = "Hello World!\n";
__global__ void helloWorldOnDevice(void) {
int idx = blockIdx.x;
name_device[idx] = hw[idx];
tab_d[idx] *= tab_d[idx];
}
__global__ void inc(void){
int idx = blockIdx.x;
tab_d[idx]++;
}
int main(void) {
int tab_h[MAX];
int tab_h1[MAX];
int i;
char name_host[MAX];
for (i = 0; i < MAX; i++)
tab_h[i] = i;
// symbol as a pointer
cudaMemcpyToSymbol(tab_d, tab_h, sizeof(int) * MAX, 0,
cudaMemcpyHostToDevice);
helloWorldOnDevice <<< MAX, 1 >>> ();
cudaThreadSynchronize();
// ----------- symbol as a pointer to a variable
cudaMemcpyFromSymbol(name_host, name_device, sizeof(char) * 13, 0,
cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(tab_h1, tab_d, sizeof(int) * MAX, 0,
cudaMemcpyDeviceToHost);
printf("\n\nGot from GPU: %s\n", name_host);
if (strcmp(name_host, "Hello World!\n") == 0)
printf("Hello test: PASSED\n");
else
printf("Hello test: FAILED\n");
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] * tab_h[i])) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
// ----------- now symbol as a name
// symbol as a name
cudaMemcpyToSymbol("tab_d", tab_h, sizeof(int) * MAX, 0,
cudaMemcpyHostToDevice);
inc <<< MAX, 1 >>> ();
cudaThreadSynchronize();
cudaMemcpyFromSymbol(tab_h1, "tab_d", sizeof(int) * MAX, 0,
cudaMemcpyDeviceToHost);
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] + 1)) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
} | code for sm_80
Function : _Z3incv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x4][0x8] ; /* 0x0100020002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18helloWorldOnDevicev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ LDC.U8 R7, c[0x3][R6] ; /* 0x00c0000006077b82 */
/* 0x001e220000000000 */
/*0050*/ IADD3 R4, P0, R6, c[0x4][0x0], RZ ; /* 0x0100000006047a10 */
/* 0x000fce0007f1e0ff */
/*0060*/ IMAD.WIDE R2, R6.reuse, R3, c[0x4][0x8] ; /* 0x0100020006027625 */
/* 0x040fe200078e0203 */
/*0070*/ LEA.HI.X.SX32 R5, R6, c[0x4][0x4], 0x1, P0 ; /* 0x0100010006057a11 */
/* 0x000fca00000f0eff */
/*0080*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101104 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R9, R0, R0, RZ ; /* 0x0000000000097224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* @file add1.cu
* @brief this example is for testing cudaMemcpyFrom/ToSymbol
*
* @date Apr 27, 2011
* @author Magda Slawinska, magg __at_ gatech __dot_ edu
*/
#include <stdio.h>
#include <cuda.h>
#define MAX 14
__device__ char name_device[MAX];
__device__ int tab_d[MAX];
__constant__ __device__ char hw[] = "Hello World!\n";
__global__ void helloWorldOnDevice(void) {
int idx = blockIdx.x;
name_device[idx] = hw[idx];
tab_d[idx] *= tab_d[idx];
}
__global__ void inc(void){
int idx = blockIdx.x;
tab_d[idx]++;
}
int main(void) {
int tab_h[MAX];
int tab_h1[MAX];
int i;
char name_host[MAX];
for (i = 0; i < MAX; i++)
tab_h[i] = i;
// symbol as a pointer
cudaMemcpyToSymbol(tab_d, tab_h, sizeof(int) * MAX, 0,
cudaMemcpyHostToDevice);
helloWorldOnDevice <<< MAX, 1 >>> ();
cudaThreadSynchronize();
// ----------- symbol as a pointer to a variable
cudaMemcpyFromSymbol(name_host, name_device, sizeof(char) * 13, 0,
cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(tab_h1, tab_d, sizeof(int) * MAX, 0,
cudaMemcpyDeviceToHost);
printf("\n\nGot from GPU: %s\n", name_host);
if (strcmp(name_host, "Hello World!\n") == 0)
printf("Hello test: PASSED\n");
else
printf("Hello test: FAILED\n");
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] * tab_h[i])) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
// ----------- now symbol as a name
// symbol as a name
cudaMemcpyToSymbol("tab_d", tab_h, sizeof(int) * MAX, 0,
cudaMemcpyHostToDevice);
inc <<< MAX, 1 >>> ();
cudaThreadSynchronize();
cudaMemcpyFromSymbol(tab_h1, "tab_d", sizeof(int) * MAX, 0,
cudaMemcpyDeviceToHost);
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] + 1)) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
} | .file "tmpxft_00064642_00000000-6_app2_back1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z18helloWorldOnDevicevv
.type _Z37__device_stub__Z18helloWorldOnDevicevv, @function
_Z37__device_stub__Z18helloWorldOnDevicevv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z18helloWorldOnDevicev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z18helloWorldOnDevicevv, .-_Z37__device_stub__Z18helloWorldOnDevicevv
.globl _Z18helloWorldOnDevicev
.type _Z18helloWorldOnDevicev, @function
_Z18helloWorldOnDevicev:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z18helloWorldOnDevicevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18helloWorldOnDevicev, .-_Z18helloWorldOnDevicev
.globl _Z21__device_stub__Z3incvv
.type _Z21__device_stub__Z3incvv, @function
_Z21__device_stub__Z3incvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3incv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z21__device_stub__Z3incvv, .-_Z21__device_stub__Z3incvv
.globl _Z3incv
.type _Z3incv, @function
_Z3incv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3incvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3incv, .-_Z3incv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\nGot from GPU: %s\n"
.LC1:
.string "Hello World!\n"
.LC2:
.string "Hello test: PASSED\n"
.LC3:
.string "Hello test: FAILED\n"
.LC4:
.string "FAILED!\n"
.LC5:
.string "tab_h1[%d] = %d\n"
.LC6:
.string "tab_d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
.L20:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $14, %rax
jne .L20
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $56, %edx
leaq _ZL5tab_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $14, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaThreadSynchronize@PLT
leaq 154(%rsp), %rbx
movl $2, %r8d
movl $0, %ecx
movl $13, %edx
leaq _ZL11name_device(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 96(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $56, %edx
leaq _ZL5tab_d(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L24:
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L23:
movl %ebx, %edx
movl 96(%rsp,%rbx,4), %ecx
movl 32(%rsp,%rbx,4), %eax
imull %eax, %eax
cmpl %eax, %ecx
jne .L37
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $14, %rbx
jne .L23
.L26:
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $56, %edx
leaq .LC6(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $14, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L27:
call cudaThreadSynchronize@PLT
leaq 96(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $56, %edx
leaq .LC6(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L30:
movl %ebx, %edx
movl 96(%rsp,%rbx,4), %ecx
movl 32(%rsp,%rbx,4), %eax
addl $1, %eax
cmpl %eax, %ecx
jne .L39
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $14, %rbx
jne .L30
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call _Z37__device_stub__Z18helloWorldOnDevicevv
jmp .L21
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L37:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L38:
call _Z21__device_stub__Z3incvv
jmp .L27
.L39:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3incv"
.LC8:
.string "_Z18helloWorldOnDevicev"
.LC9:
.string "name_device"
.LC10:
.string "hw"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3incv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z18helloWorldOnDevicev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $14, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11name_device(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $56, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5tab_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $14, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2hw(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2hw
.comm _ZL2hw,14,8
.local _ZL5tab_d
.comm _ZL5tab_d,56,32
.local _ZL11name_device
.comm _ZL11name_device,14,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* @file add1.cu
* @brief this example is for testing cudaMemcpyFrom/ToSymbol
*
* @date Apr 27, 2011
* @author Magda Slawinska, magg __at_ gatech __dot_ edu
*/
#include <stdio.h>
#include <cuda.h>
#define MAX 14
__device__ char name_device[MAX];
__device__ int tab_d[MAX];
__constant__ __device__ char hw[] = "Hello World!\n";
__global__ void helloWorldOnDevice(void) {
int idx = blockIdx.x;
name_device[idx] = hw[idx];
tab_d[idx] *= tab_d[idx];
}
__global__ void inc(void){
int idx = blockIdx.x;
tab_d[idx]++;
}
int main(void) {
int tab_h[MAX];
int tab_h1[MAX];
int i;
char name_host[MAX];
for (i = 0; i < MAX; i++)
tab_h[i] = i;
// symbol as a pointer
cudaMemcpyToSymbol(tab_d, tab_h, sizeof(int) * MAX, 0,
cudaMemcpyHostToDevice);
helloWorldOnDevice <<< MAX, 1 >>> ();
cudaThreadSynchronize();
// ----------- symbol as a pointer to a variable
cudaMemcpyFromSymbol(name_host, name_device, sizeof(char) * 13, 0,
cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(tab_h1, tab_d, sizeof(int) * MAX, 0,
cudaMemcpyDeviceToHost);
printf("\n\nGot from GPU: %s\n", name_host);
if (strcmp(name_host, "Hello World!\n") == 0)
printf("Hello test: PASSED\n");
else
printf("Hello test: FAILED\n");
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] * tab_h[i])) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
// ----------- now symbol as a name
// symbol as a name
cudaMemcpyToSymbol("tab_d", tab_h, sizeof(int) * MAX, 0,
cudaMemcpyHostToDevice);
inc <<< MAX, 1 >>> ();
cudaThreadSynchronize();
cudaMemcpyFromSymbol(tab_h1, "tab_d", sizeof(int) * MAX, 0,
cudaMemcpyDeviceToHost);
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] + 1)) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
} | /**
* @file add1.cu
* @brief this example is for testing cudaMemcpyFrom/ToSymbol
*
* @date Apr 27, 2011
* @author Magda Slawinska, magg __at_ gatech __dot_ edu
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX 14
__device__ char name_device[MAX];
__device__ int tab_d[MAX];
__constant__ __device__ char hw[] = "Hello World!\n";
__global__ void helloWorldOnDevice(void) {
int idx = blockIdx.x;
name_device[idx] = hw[idx];
tab_d[idx] *= tab_d[idx];
}
__global__ void inc(void){
int idx = blockIdx.x;
tab_d[idx]++;
}
int main(void) {
int tab_h[MAX];
int tab_h1[MAX];
int i;
char name_host[MAX];
for (i = 0; i < MAX; i++)
tab_h[i] = i;
// symbol as a pointer
hipMemcpyToSymbol(HIP_SYMBOL(tab_d), tab_h, sizeof(int) * MAX, 0,
hipMemcpyHostToDevice);
helloWorldOnDevice <<< MAX, 1 >>> ();
hipDeviceSynchronize();
// ----------- symbol as a pointer to a variable
hipMemcpyFromSymbol(name_host, HIP_SYMBOL(name_device), sizeof(char) * 13, 0,
hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(tab_h1, HIP_SYMBOL(tab_d), sizeof(int) * MAX, 0,
hipMemcpyDeviceToHost);
printf("\n\nGot from GPU: %s\n", name_host);
if (strcmp(name_host, "Hello World!\n") == 0)
printf("Hello test: PASSED\n");
else
printf("Hello test: FAILED\n");
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] * tab_h[i])) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
// ----------- now symbol as a name
// symbol as a name
hipMemcpyToSymbol(HIP_SYMBOL("tab_d"), tab_h, sizeof(int) * MAX, 0,
hipMemcpyHostToDevice);
inc <<< MAX, 1 >>> ();
hipDeviceSynchronize();
hipMemcpyFromSymbol(tab_h1, HIP_SYMBOL("tab_d"), sizeof(int) * MAX, 0,
hipMemcpyDeviceToHost);
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] + 1)) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* @file add1.cu
* @brief this example is for testing cudaMemcpyFrom/ToSymbol
*
* @date Apr 27, 2011
* @author Magda Slawinska, magg __at_ gatech __dot_ edu
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX 14
__device__ char name_device[MAX];
__device__ int tab_d[MAX];
__constant__ __device__ char hw[] = "Hello World!\n";
__global__ void helloWorldOnDevice(void) {
int idx = blockIdx.x;
name_device[idx] = hw[idx];
tab_d[idx] *= tab_d[idx];
}
__global__ void inc(void){
int idx = blockIdx.x;
tab_d[idx]++;
}
int main(void) {
int tab_h[MAX];
int tab_h1[MAX];
int i;
char name_host[MAX];
for (i = 0; i < MAX; i++)
tab_h[i] = i;
// symbol as a pointer
hipMemcpyToSymbol(HIP_SYMBOL(tab_d), tab_h, sizeof(int) * MAX, 0,
hipMemcpyHostToDevice);
helloWorldOnDevice <<< MAX, 1 >>> ();
hipDeviceSynchronize();
// ----------- symbol as a pointer to a variable
hipMemcpyFromSymbol(name_host, HIP_SYMBOL(name_device), sizeof(char) * 13, 0,
hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(tab_h1, HIP_SYMBOL(tab_d), sizeof(int) * MAX, 0,
hipMemcpyDeviceToHost);
printf("\n\nGot from GPU: %s\n", name_host);
if (strcmp(name_host, "Hello World!\n") == 0)
printf("Hello test: PASSED\n");
else
printf("Hello test: FAILED\n");
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] * tab_h[i])) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
// ----------- now symbol as a name
// symbol as a name
hipMemcpyToSymbol(HIP_SYMBOL("tab_d"), tab_h, sizeof(int) * MAX, 0,
hipMemcpyHostToDevice);
inc <<< MAX, 1 >>> ();
hipDeviceSynchronize();
hipMemcpyFromSymbol(tab_h1, HIP_SYMBOL("tab_d"), sizeof(int) * MAX, 0,
hipMemcpyDeviceToHost);
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] + 1)) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18helloWorldOnDevicev
.globl _Z18helloWorldOnDevicev
.p2align 8
.type _Z18helloWorldOnDevicev,@function
_Z18helloWorldOnDevicev:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, hw@rel32@lo+4
s_addc_u32 s3, s3, hw@rel32@hi+12
v_mov_b32_e32 v0, 0
s_ashr_i32 s1, s15, 31
s_add_u32 s2, s15, s2
s_addc_u32 s3, s1, s3
s_mov_b32 s0, s15
global_load_u8 v1, v0, s[2:3]
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, name_device@rel32@lo+4
s_addc_u32 s3, s3, name_device@rel32@hi+12
s_add_u32 s2, s15, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, tab_d@rel32@lo+4
s_addc_u32 s5, s5, tab_d@rel32@hi+12
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s4
v_mov_b32_e32 v2, s4
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b8 v0, v1, s[2:3]
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18helloWorldOnDevicev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18helloWorldOnDevicev, .Lfunc_end0-_Z18helloWorldOnDevicev
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3incv
.globl _Z3incv
.p2align 8
.type _Z3incv,@function
_Z3incv:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, tab_d@rel32@lo+4
s_addc_u32 s3, s3, tab_d@rel32@hi+12
s_mov_b32 s0, s15
s_ashr_i32 s1, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3incv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3incv, .Lfunc_end1-_Z3incv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected name_device
.type name_device,@object
.section .bss,"aw",@nobits
.globl name_device
name_device:
.zero 14
.size name_device, 14
.protected tab_d
.type tab_d,@object
.globl tab_d
.p2align 4, 0x0
tab_d:
.zero 56
.size tab_d, 56
.protected hw
.type hw,@object
.data
.globl hw
hw:
.asciz "Hello World!\n"
.size hw, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym name_device
.addrsig_sym tab_d
.addrsig_sym hw
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18helloWorldOnDevicev
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18helloWorldOnDevicev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3incv
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3incv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* @file add1.cu
* @brief this example is for testing cudaMemcpyFrom/ToSymbol
*
* @date Apr 27, 2011
* @author Magda Slawinska, magg __at_ gatech __dot_ edu
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX 14
__device__ char name_device[MAX];
__device__ int tab_d[MAX];
__constant__ __device__ char hw[] = "Hello World!\n";
__global__ void helloWorldOnDevice(void) {
int idx = blockIdx.x;
name_device[idx] = hw[idx];
tab_d[idx] *= tab_d[idx];
}
__global__ void inc(void){
int idx = blockIdx.x;
tab_d[idx]++;
}
int main(void) {
int tab_h[MAX];
int tab_h1[MAX];
int i;
char name_host[MAX];
for (i = 0; i < MAX; i++)
tab_h[i] = i;
// symbol as a pointer
hipMemcpyToSymbol(HIP_SYMBOL(tab_d), tab_h, sizeof(int) * MAX, 0,
hipMemcpyHostToDevice);
helloWorldOnDevice <<< MAX, 1 >>> ();
hipDeviceSynchronize();
// ----------- symbol as a pointer to a variable
hipMemcpyFromSymbol(name_host, HIP_SYMBOL(name_device), sizeof(char) * 13, 0,
hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(tab_h1, HIP_SYMBOL(tab_d), sizeof(int) * MAX, 0,
hipMemcpyDeviceToHost);
printf("\n\nGot from GPU: %s\n", name_host);
if (strcmp(name_host, "Hello World!\n") == 0)
printf("Hello test: PASSED\n");
else
printf("Hello test: FAILED\n");
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] * tab_h[i])) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
// ----------- now symbol as a name
// symbol as a name
hipMemcpyToSymbol(HIP_SYMBOL("tab_d"), tab_h, sizeof(int) * MAX, 0,
hipMemcpyHostToDevice);
inc <<< MAX, 1 >>> ();
hipDeviceSynchronize();
hipMemcpyFromSymbol(tab_h1, HIP_SYMBOL("tab_d"), sizeof(int) * MAX, 0,
hipMemcpyDeviceToHost);
for (i = 0; i < MAX; i++) {
if (tab_h1[i] != (tab_h[i] + 1)) {
printf("FAILED!\n");
break;
} else
printf("tab_h1[%d] = %d\n", i, tab_h1[i]);
}
} | .text
.file "app2_back1.hip"
.globl _Z33__device_stub__helloWorldOnDevicev # -- Begin function _Z33__device_stub__helloWorldOnDevicev
.p2align 4, 0x90
.type _Z33__device_stub__helloWorldOnDevicev,@function
_Z33__device_stub__helloWorldOnDevicev: # @_Z33__device_stub__helloWorldOnDevicev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18helloWorldOnDevicev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z33__device_stub__helloWorldOnDevicev, .Lfunc_end0-_Z33__device_stub__helloWorldOnDevicev
.cfi_endproc
# -- End function
.globl _Z18__device_stub__incv # -- Begin function _Z18__device_stub__incv
.p2align 4, 0x90
.type _Z18__device_stub__incv,@function
_Z18__device_stub__incv: # @_Z18__device_stub__incv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3incv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z18__device_stub__incv, .Lfunc_end1-_Z18__device_stub__incv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $208, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, 144(%rsp,%rax,4)
incq %rax
cmpq $14, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 144(%rsp), %rsi
movl $tab_d, %edi
movl $56, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 13(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 64(%rsp), %rdi
movq %rsp, %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18helloWorldOnDevicev, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq %rsp, %r15
movl $name_device, %esi
movl $13, %edx
movq %r15, %rdi
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 64(%rsp), %rdi
movl $tab_d, %esi
movl $56, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
xorq (%rsp), %rax
movabsq $2851464966991703, %rcx # imm = 0xA21646C726F57
xorq 6(%rsp), %rcx
orq %rax, %rcx
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%r15,4), %edx
movl 144(%rsp,%r15,4), %eax
imull %eax, %eax
cmpl %eax, %edx
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $14, %r15
jne .LBB2_5
jmp .LBB2_8
.LBB2_6:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_8: # %.loopexit47
leaq 144(%rsp), %rsi
movl $.L.str.6, %edi
movl $56, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3incv, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
movl $.L.str.6, %esi
movl $56, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %eax
incl %eax
cmpl %eax, %edx
jne .LBB2_12
# %bb.13: # in Loop: Header=BB2_11 Depth=1
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $14, %rbx
jne .LBB2_11
jmp .LBB2_14
.LBB2_12:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_14: # %.loopexit
xorl %eax, %eax
addq $208, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18helloWorldOnDevicev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3incv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $name_device, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $14, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $tab_d, %esi
movl $.L.str.6, %edx
movl $.L.str.6, %ecx
movl $56, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $hw, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $14, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type name_device,@object # @name_device
.local name_device
.comm name_device,14,1
.type tab_d,@object # @tab_d
.local tab_d
.comm tab_d,56,16
.type hw,@object # @hw
.local hw
.comm hw,14,1
.type _Z18helloWorldOnDevicev,@object # @_Z18helloWorldOnDevicev
.section .rodata,"a",@progbits
.globl _Z18helloWorldOnDevicev
.p2align 3, 0x0
_Z18helloWorldOnDevicev:
.quad _Z33__device_stub__helloWorldOnDevicev
.size _Z18helloWorldOnDevicev, 8
.type _Z3incv,@object # @_Z3incv
.globl _Z3incv
.p2align 3, 0x0
_Z3incv:
.quad _Z18__device_stub__incv
.size _Z3incv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nGot from GPU: %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Hello World!\n"
.size .L.str.1, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "tab_h1[%d] = %d\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "tab_d"
.size .L.str.6, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18helloWorldOnDevicev"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3incv"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "name_device"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "hw"
.size .L__unnamed_4, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello test: FAILED"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Hello test: PASSED"
.size .Lstr.1, 19
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "FAILED!"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__helloWorldOnDevicev
.addrsig_sym _Z18__device_stub__incv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym name_device
.addrsig_sym tab_d
.addrsig_sym hw
.addrsig_sym _Z18helloWorldOnDevicev
.addrsig_sym _Z3incv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3incv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x4][0x8] ; /* 0x0100020002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18helloWorldOnDevicev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ LDC.U8 R7, c[0x3][R6] ; /* 0x00c0000006077b82 */
/* 0x001e220000000000 */
/*0050*/ IADD3 R4, P0, R6, c[0x4][0x0], RZ ; /* 0x0100000006047a10 */
/* 0x000fce0007f1e0ff */
/*0060*/ IMAD.WIDE R2, R6.reuse, R3, c[0x4][0x8] ; /* 0x0100020006027625 */
/* 0x040fe200078e0203 */
/*0070*/ LEA.HI.X.SX32 R5, R6, c[0x4][0x4], 0x1, P0 ; /* 0x0100010006057a11 */
/* 0x000fca00000f0eff */
/*0080*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101104 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R9, R0, R0, RZ ; /* 0x0000000000097224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18helloWorldOnDevicev
.globl _Z18helloWorldOnDevicev
.p2align 8
.type _Z18helloWorldOnDevicev,@function
_Z18helloWorldOnDevicev:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, hw@rel32@lo+4
s_addc_u32 s3, s3, hw@rel32@hi+12
v_mov_b32_e32 v0, 0
s_ashr_i32 s1, s15, 31
s_add_u32 s2, s15, s2
s_addc_u32 s3, s1, s3
s_mov_b32 s0, s15
global_load_u8 v1, v0, s[2:3]
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, name_device@rel32@lo+4
s_addc_u32 s3, s3, name_device@rel32@hi+12
s_add_u32 s2, s15, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, tab_d@rel32@lo+4
s_addc_u32 s5, s5, tab_d@rel32@hi+12
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s4
v_mov_b32_e32 v2, s4
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b8 v0, v1, s[2:3]
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18helloWorldOnDevicev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18helloWorldOnDevicev, .Lfunc_end0-_Z18helloWorldOnDevicev
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3incv
.globl _Z3incv
.p2align 8
.type _Z3incv,@function
_Z3incv:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, tab_d@rel32@lo+4
s_addc_u32 s3, s3, tab_d@rel32@hi+12
s_mov_b32 s0, s15
s_ashr_i32 s1, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3incv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3incv, .Lfunc_end1-_Z3incv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected name_device
.type name_device,@object
.section .bss,"aw",@nobits
.globl name_device
name_device:
.zero 14
.size name_device, 14
.protected tab_d
.type tab_d,@object
.globl tab_d
.p2align 4, 0x0
tab_d:
.zero 56
.size tab_d, 56
.protected hw
.type hw,@object
.data
.globl hw
hw:
.asciz "Hello World!\n"
.size hw, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym name_device
.addrsig_sym tab_d
.addrsig_sym hw
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18helloWorldOnDevicev
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18helloWorldOnDevicev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3incv
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3incv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064642_00000000-6_app2_back1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z18helloWorldOnDevicevv
.type _Z37__device_stub__Z18helloWorldOnDevicevv, @function
_Z37__device_stub__Z18helloWorldOnDevicevv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z18helloWorldOnDevicev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z18helloWorldOnDevicevv, .-_Z37__device_stub__Z18helloWorldOnDevicevv
.globl _Z18helloWorldOnDevicev
.type _Z18helloWorldOnDevicev, @function
_Z18helloWorldOnDevicev:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z18helloWorldOnDevicevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18helloWorldOnDevicev, .-_Z18helloWorldOnDevicev
.globl _Z21__device_stub__Z3incvv
.type _Z21__device_stub__Z3incvv, @function
_Z21__device_stub__Z3incvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3incv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z21__device_stub__Z3incvv, .-_Z21__device_stub__Z3incvv
.globl _Z3incv
.type _Z3incv, @function
_Z3incv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3incvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3incv, .-_Z3incv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\nGot from GPU: %s\n"
.LC1:
.string "Hello World!\n"
.LC2:
.string "Hello test: PASSED\n"
.LC3:
.string "Hello test: FAILED\n"
.LC4:
.string "FAILED!\n"
.LC5:
.string "tab_h1[%d] = %d\n"
.LC6:
.string "tab_d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
.L20:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $14, %rax
jne .L20
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $56, %edx
leaq _ZL5tab_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $14, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L21:
call cudaThreadSynchronize@PLT
leaq 154(%rsp), %rbx
movl $2, %r8d
movl $0, %ecx
movl $13, %edx
leaq _ZL11name_device(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpyFromSymbol@PLT
leaq 96(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $56, %edx
leaq _ZL5tab_d(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L22
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L24:
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L23:
movl %ebx, %edx
movl 96(%rsp,%rbx,4), %ecx
movl 32(%rsp,%rbx,4), %eax
imull %eax, %eax
cmpl %eax, %ecx
jne .L37
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $14, %rbx
jne .L23
.L26:
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $56, %edx
leaq .LC6(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $14, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L27:
call cudaThreadSynchronize@PLT
leaq 96(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $56, %edx
leaq .LC6(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L30:
movl %ebx, %edx
movl 96(%rsp,%rbx,4), %ecx
movl 32(%rsp,%rbx,4), %eax
addl $1, %eax
cmpl %eax, %ecx
jne .L39
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $14, %rbx
jne .L30
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call _Z37__device_stub__Z18helloWorldOnDevicevv
jmp .L21
.L22:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L37:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L38:
call _Z21__device_stub__Z3incvv
jmp .L27
.L39:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3incv"
.LC8:
.string "_Z18helloWorldOnDevicev"
.LC9:
.string "name_device"
.LC10:
.string "hw"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3incv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z18helloWorldOnDevicev(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $14, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11name_device(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $56, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5tab_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $14, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2hw(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2hw
.comm _ZL2hw,14,8
.local _ZL5tab_d
.comm _ZL5tab_d,56,32
.local _ZL11name_device
.comm _ZL11name_device,14,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "app2_back1.hip"
.globl _Z33__device_stub__helloWorldOnDevicev # -- Begin function _Z33__device_stub__helloWorldOnDevicev
.p2align 4, 0x90
.type _Z33__device_stub__helloWorldOnDevicev,@function
_Z33__device_stub__helloWorldOnDevicev: # @_Z33__device_stub__helloWorldOnDevicev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18helloWorldOnDevicev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z33__device_stub__helloWorldOnDevicev, .Lfunc_end0-_Z33__device_stub__helloWorldOnDevicev
.cfi_endproc
# -- End function
.globl _Z18__device_stub__incv # -- Begin function _Z18__device_stub__incv
.p2align 4, 0x90
.type _Z18__device_stub__incv,@function
_Z18__device_stub__incv: # @_Z18__device_stub__incv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3incv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z18__device_stub__incv, .Lfunc_end1-_Z18__device_stub__incv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $208, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, 144(%rsp,%rax,4)
incq %rax
cmpq $14, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 144(%rsp), %rsi
movl $tab_d, %edi
movl $56, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 13(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 64(%rsp), %rdi
movq %rsp, %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z18helloWorldOnDevicev, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq %rsp, %r15
movl $name_device, %esi
movl $13, %edx
movq %r15, %rdi
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
leaq 64(%rsp), %rdi
movl $tab_d, %esi
movl $56, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
xorq (%rsp), %rax
movabsq $2851464966991703, %rcx # imm = 0xA21646C726F57
xorq 6(%rsp), %rcx
orq %rax, %rcx
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%r15,4), %edx
movl 144(%rsp,%r15,4), %eax
imull %eax, %eax
cmpl %eax, %edx
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq $14, %r15
jne .LBB2_5
jmp .LBB2_8
.LBB2_6:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_8: # %.loopexit47
leaq 144(%rsp), %rsi
movl $.L.str.6, %edi
movl $56, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3incv, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
movl $.L.str.6, %esi
movl $56, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %eax
incl %eax
cmpl %eax, %edx
jne .LBB2_12
# %bb.13: # in Loop: Header=BB2_11 Depth=1
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $14, %rbx
jne .LBB2_11
jmp .LBB2_14
.LBB2_12:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_14: # %.loopexit
xorl %eax, %eax
addq $208, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18helloWorldOnDevicev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3incv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $name_device, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $14, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $tab_d, %esi
movl $.L.str.6, %edx
movl $.L.str.6, %ecx
movl $56, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $hw, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $14, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type name_device,@object # @name_device
.local name_device
.comm name_device,14,1
.type tab_d,@object # @tab_d
.local tab_d
.comm tab_d,56,16
.type hw,@object # @hw
.local hw
.comm hw,14,1
.type _Z18helloWorldOnDevicev,@object # @_Z18helloWorldOnDevicev
.section .rodata,"a",@progbits
.globl _Z18helloWorldOnDevicev
.p2align 3, 0x0
_Z18helloWorldOnDevicev:
.quad _Z33__device_stub__helloWorldOnDevicev
.size _Z18helloWorldOnDevicev, 8
.type _Z3incv,@object # @_Z3incv
.globl _Z3incv
.p2align 3, 0x0
_Z3incv:
.quad _Z18__device_stub__incv
.size _Z3incv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n\nGot from GPU: %s\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Hello World!\n"
.size .L.str.1, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "tab_h1[%d] = %d\n"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "tab_d"
.size .L.str.6, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18helloWorldOnDevicev"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3incv"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "name_device"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "hw"
.size .L__unnamed_4, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello test: FAILED"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Hello test: PASSED"
.size .Lstr.1, 19
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "FAILED!"
.size .Lstr.3, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__helloWorldOnDevicev
.addrsig_sym _Z18__device_stub__incv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym name_device
.addrsig_sym tab_d
.addrsig_sym hw
.addrsig_sym _Z18helloWorldOnDevicev
.addrsig_sym _Z3incv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__global__ void matrix_mult(){
}
int main(int argc, char **argv)
{
int devID = 0;
cudaError_t error;
cudaDeviceProp deviceProp;
error = cudaGetDevice(&devID);
error = cudaGetDeviceProperties(&deviceProp, devID);
if (deviceProp.computeMode == cudaComputeModeProhibited)
{
return 1;
}
if (error != cudaSuccess)
{
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
matrix_mult<<< 1,1 >>> ();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << "Matrixmultiplikation (" << milliseconds << " ms)" << std::endl;
return 0;
} | code for sm_80
Function : _Z11matrix_multv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__global__ void matrix_mult(){
}
int main(int argc, char **argv)
{
int devID = 0;
cudaError_t error;
cudaDeviceProp deviceProp;
error = cudaGetDevice(&devID);
error = cudaGetDeviceProperties(&deviceProp, devID);
if (deviceProp.computeMode == cudaComputeModeProhibited)
{
return 1;
}
if (error != cudaSuccess)
{
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
matrix_mult<<< 1,1 >>> ();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << "Matrixmultiplikation (" << milliseconds << " ms)" << std::endl;
return 0;
} | .file "tmpxft_00092c77_00000000-6_matmul_shared.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11matrix_multvv
.type _Z30__device_stub__Z11matrix_multvv, @function
_Z30__device_stub__Z11matrix_multvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11matrix_multv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z11matrix_multvv, .-_Z30__device_stub__Z11matrix_multvv
.globl _Z11matrix_multv
.type _Z11matrix_multv, @function
_Z11matrix_multv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11matrix_multvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11matrix_multv, .-_Z11matrix_multv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Matrixmultiplikation ("
.LC2:
.string " ms)"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $1096, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 4(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl $1, %eax
cmpl $2, 452(%rsp)
je .L11
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L11:
movq 1080(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call _Z30__device_stub__Z11matrix_multvv
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11matrix_multv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_multv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__global__ void matrix_mult(){
}
int main(int argc, char **argv)
{
int devID = 0;
cudaError_t error;
cudaDeviceProp deviceProp;
error = cudaGetDevice(&devID);
error = cudaGetDeviceProperties(&deviceProp, devID);
if (deviceProp.computeMode == cudaComputeModeProhibited)
{
return 1;
}
if (error != cudaSuccess)
{
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
matrix_mult<<< 1,1 >>> ();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << "Matrixmultiplikation (" << milliseconds << " ms)" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void matrix_mult(){
}
int main(int argc, char **argv)
{
int devID = 0;
hipError_t error;
hipDeviceProp_t deviceProp;
error = hipGetDevice(&devID);
error = hipGetDeviceProperties(&deviceProp, devID);
if (deviceProp.computeMode == hipComputeModeProhibited)
{
return 1;
}
if (error != hipSuccess)
{
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
matrix_mult<<< 1,1 >>> ();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << "Matrixmultiplikation (" << milliseconds << " ms)" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void matrix_mult(){
}
int main(int argc, char **argv)
{
int devID = 0;
hipError_t error;
hipDeviceProp_t deviceProp;
error = hipGetDevice(&devID);
error = hipGetDeviceProperties(&deviceProp, devID);
if (deviceProp.computeMode == hipComputeModeProhibited)
{
return 1;
}
if (error != hipSuccess)
{
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
matrix_mult<<< 1,1 >>> ();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << "Matrixmultiplikation (" << milliseconds << " ms)" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_multv
.globl _Z11matrix_multv
.p2align 8
.type _Z11matrix_multv,@function
_Z11matrix_multv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_multv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_multv, .Lfunc_end0-_Z11matrix_multv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_multv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11matrix_multv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void matrix_mult(){
}
int main(int argc, char **argv)
{
int devID = 0;
hipError_t error;
hipDeviceProp_t deviceProp;
error = hipGetDevice(&devID);
error = hipGetDeviceProperties(&deviceProp, devID);
if (deviceProp.computeMode == hipComputeModeProhibited)
{
return 1;
}
if (error != hipSuccess)
{
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
matrix_mult<<< 1,1 >>> ();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << "Matrixmultiplikation (" << milliseconds << " ms)" << std::endl;
return 0;
} | .text
.file "matmul_shared.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__matrix_multv # -- Begin function _Z26__device_stub__matrix_multv
.p2align 4, 0x90
.type _Z26__device_stub__matrix_multv,@function
_Z26__device_stub__matrix_multv: # @_Z26__device_stub__matrix_multv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11matrix_multv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__matrix_multv, .Lfunc_end0-_Z26__device_stub__matrix_multv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 88(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl $1, %eax
cmpl $2, 492(%rsp)
je .LBB1_8
# %bb.1:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
leaq 24(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_multv, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 24(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB1_7
.LBB1_6:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.LBB1_8:
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 1584
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_multv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matrix_multv,@object # @_Z11matrix_multv
.section .rodata,"a",@progbits
.globl _Z11matrix_multv
.p2align 3, 0x0
_Z11matrix_multv:
.quad _Z26__device_stub__matrix_multv
.size _Z11matrix_multv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrixmultiplikation ("
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms)"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11matrix_multv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_multv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_multv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11matrix_multv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_multv
.globl _Z11matrix_multv
.p2align 8
.type _Z11matrix_multv,@function
_Z11matrix_multv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_multv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_multv, .Lfunc_end0-_Z11matrix_multv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_multv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11matrix_multv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00092c77_00000000-6_matmul_shared.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11matrix_multvv
.type _Z30__device_stub__Z11matrix_multvv, @function
_Z30__device_stub__Z11matrix_multvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11matrix_multv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z11matrix_multvv, .-_Z30__device_stub__Z11matrix_multvv
.globl _Z11matrix_multv
.type _Z11matrix_multv, @function
_Z11matrix_multv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11matrix_multvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11matrix_multv, .-_Z11matrix_multv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Matrixmultiplikation ("
.LC2:
.string " ms)"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $1096, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 4(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl $1, %eax
cmpl $2, 452(%rsp)
je .L11
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L11:
movq 1080(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call _Z30__device_stub__Z11matrix_multvv
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11matrix_multv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_multv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmul_shared.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__matrix_multv # -- Begin function _Z26__device_stub__matrix_multv
.p2align 4, 0x90
.type _Z26__device_stub__matrix_multv,@function
_Z26__device_stub__matrix_multv: # @_Z26__device_stub__matrix_multv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11matrix_multv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__matrix_multv, .Lfunc_end0-_Z26__device_stub__matrix_multv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 88(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl $1, %eax
cmpl $2, 492(%rsp)
je .LBB1_8
# %bb.1:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
leaq 24(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_multv, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 24(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB1_7
.LBB1_6:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.LBB1_8:
addq $1560, %rsp # imm = 0x618
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 1584
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_multv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matrix_multv,@object # @_Z11matrix_multv
.section .rodata,"a",@progbits
.globl _Z11matrix_multv
.p2align 3, 0x0
_Z11matrix_multv:
.quad _Z26__device_stub__matrix_multv
.size _Z11matrix_multv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrixmultiplikation ("
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms)"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11matrix_multv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_multv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_multv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int clamp(int value, int bound)
{
if (value < 0) {
return 1;
}
if (value < bound) {
return value;
}
return bound - 1;
}
__device__ int index(int x, int y, int width)
{
return (y * width) + x;
}
__device__ const int FILTER_SIZE = 9; __device__ const int FILTER_HALFSIZE = FILTER_SIZE >> 1; __device__ void sort_bubble(float *x, int n_size)
{
for (int i = 0; i < n_size - 1; i++)
{
for(int j = 0; j < n_size - i - 1; j++)
{
if (x[j] > x[j+1])
{
float temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;
}
}
}
}
__global__ void median_filter_2d_sm(unsigned char* input, unsigned char* output, int width, int height)
{
__shared__ int sharedPixels[BLOCKDIM + FILTER_SIZE][BLOCKDIM + FILTER_SIZE];
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
int xBlockLimit_max = blockDim.x - FILTER_HALFSIZE - 1;
int yBlockLimit_max = blockDim.y - FILTER_HALFSIZE - 1;
int xBlockLimit_min = FILTER_HALFSIZE;
int yBlockLimit_min = FILTER_HALFSIZE;
if (threadIdx.x > xBlockLimit_max && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
int i = index(x, y, width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
__syncthreads();
if((x<width) && (y<height))
{
const int color_tid = y * width + x;
float windowMedian[MAX_WINDOW*MAX_WINDOW];
int windowElements = 0;
for (int x_iter = 0; x_iter < FILTER_SIZE; x_iter ++)
{
for (int y_iter = 0; y_iter < FILTER_SIZE; y_iter++)
{
if (0<=x_iter && x_iter < width && 0 <= y_iter && y_iter < height)
{
windowMedian[windowElements++] = sharedPixels[threadIdx.x + x_iter][threadIdx.y + y_iter];
}
}
}
sort_bubble(windowMedian,windowElements);
output[color_tid] = windowMedian[windowElements/2];
}
} | .file "tmpxft_000d7ce2_00000000-6_median_filter_2d_sm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5clampii
.type _Z5clampii, @function
_Z5clampii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5clampii, .-_Z5clampii
.globl _Z5indexiii
.type _Z5indexiii, @function
_Z5indexiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z5indexiii, .-_Z5indexiii
.globl _Z11sort_bubblePfi
.type _Z11sort_bubblePfi, @function
_Z11sort_bubblePfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11sort_bubblePfi, .-_Z11sort_bubblePfi
.globl _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii
.type _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii, @function
_Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19median_filter_2d_smPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii, .-_Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii
.globl _Z19median_filter_2d_smPhS_ii
.type _Z19median_filter_2d_smPhS_ii, @function
_Z19median_filter_2d_smPhS_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z19median_filter_2d_smPhS_ii, .-_Z19median_filter_2d_smPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19median_filter_2d_smPhS_ii"
.LC1:
.string "FILTER_SIZE"
.LC2:
.string "FILTER_HALFSIZE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19median_filter_2d_smPhS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11FILTER_SIZE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15FILTER_HALFSIZE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL15FILTER_HALFSIZE, @object
.size _ZL15FILTER_HALFSIZE, 4
_ZL15FILTER_HALFSIZE:
.long 4
.align 4
.type _ZL11FILTER_SIZE, @object
.size _ZL11FILTER_SIZE, 4
_ZL11FILTER_SIZE:
.long 9
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int clamp(int value, int bound)
{
if (value < 0) {
return 1;
}
if (value < bound) {
return value;
}
return bound - 1;
}
__device__ int index(int x, int y, int width)
{
return (y * width) + x;
}
__device__ const int FILTER_SIZE = 9; __device__ const int FILTER_HALFSIZE = FILTER_SIZE >> 1; __device__ void sort_bubble(float *x, int n_size)
{
for (int i = 0; i < n_size - 1; i++)
{
for(int j = 0; j < n_size - i - 1; j++)
{
if (x[j] > x[j+1])
{
float temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;
}
}
}
}
__global__ void median_filter_2d_sm(unsigned char* input, unsigned char* output, int width, int height)
{
__shared__ int sharedPixels[BLOCKDIM + FILTER_SIZE][BLOCKDIM + FILTER_SIZE];
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
int xBlockLimit_max = blockDim.x - FILTER_HALFSIZE - 1;
int yBlockLimit_max = blockDim.y - FILTER_HALFSIZE - 1;
int xBlockLimit_min = FILTER_HALFSIZE;
int yBlockLimit_min = FILTER_HALFSIZE;
if (threadIdx.x > xBlockLimit_max && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
int i = index(x, y, width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
__syncthreads();
if((x<width) && (y<height))
{
const int color_tid = y * width + x;
float windowMedian[MAX_WINDOW*MAX_WINDOW];
int windowElements = 0;
for (int x_iter = 0; x_iter < FILTER_SIZE; x_iter ++)
{
for (int y_iter = 0; y_iter < FILTER_SIZE; y_iter++)
{
if (0<=x_iter && x_iter < width && 0 <= y_iter && y_iter < height)
{
windowMedian[windowElements++] = sharedPixels[threadIdx.x + x_iter][threadIdx.y + y_iter];
}
}
}
sort_bubble(windowMedian,windowElements);
output[color_tid] = windowMedian[windowElements/2];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int clamp(int value, int bound)
{
if (value < 0) {
return 1;
}
if (value < bound) {
return value;
}
return bound - 1;
}
__device__ int index(int x, int y, int width)
{
return (y * width) + x;
}
__device__ const int FILTER_SIZE = 9; __device__ const int FILTER_HALFSIZE = FILTER_SIZE >> 1; __device__ void sort_bubble(float *x, int n_size)
{
for (int i = 0; i < n_size - 1; i++)
{
for(int j = 0; j < n_size - i - 1; j++)
{
if (x[j] > x[j+1])
{
float temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;
}
}
}
}
__global__ void median_filter_2d_sm(unsigned char* input, unsigned char* output, int width, int height)
{
__shared__ int sharedPixels[BLOCKDIM + FILTER_SIZE][BLOCKDIM + FILTER_SIZE];
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
int xBlockLimit_max = blockDim.x - FILTER_HALFSIZE - 1;
int yBlockLimit_max = blockDim.y - FILTER_HALFSIZE - 1;
int xBlockLimit_min = FILTER_HALFSIZE;
int yBlockLimit_min = FILTER_HALFSIZE;
if (threadIdx.x > xBlockLimit_max && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
int i = index(x, y, width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
__syncthreads();
if((x<width) && (y<height))
{
const int color_tid = y * width + x;
float windowMedian[MAX_WINDOW*MAX_WINDOW];
int windowElements = 0;
for (int x_iter = 0; x_iter < FILTER_SIZE; x_iter ++)
{
for (int y_iter = 0; y_iter < FILTER_SIZE; y_iter++)
{
if (0<=x_iter && x_iter < width && 0 <= y_iter && y_iter < height)
{
windowMedian[windowElements++] = sharedPixels[threadIdx.x + x_iter][threadIdx.y + y_iter];
}
}
}
sort_bubble(windowMedian,windowElements);
output[color_tid] = windowMedian[windowElements/2];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int clamp(int value, int bound)
{
if (value < 0) {
return 1;
}
if (value < bound) {
return value;
}
return bound - 1;
}
__device__ int index(int x, int y, int width)
{
return (y * width) + x;
}
__device__ const int FILTER_SIZE = 9; __device__ const int FILTER_HALFSIZE = FILTER_SIZE >> 1; __device__ void sort_bubble(float *x, int n_size)
{
for (int i = 0; i < n_size - 1; i++)
{
for(int j = 0; j < n_size - i - 1; j++)
{
if (x[j] > x[j+1])
{
float temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;
}
}
}
}
__global__ void median_filter_2d_sm(unsigned char* input, unsigned char* output, int width, int height)
{
__shared__ int sharedPixels[BLOCKDIM + FILTER_SIZE][BLOCKDIM + FILTER_SIZE];
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
int xBlockLimit_max = blockDim.x - FILTER_HALFSIZE - 1;
int yBlockLimit_max = blockDim.y - FILTER_HALFSIZE - 1;
int xBlockLimit_min = FILTER_HALFSIZE;
int yBlockLimit_min = FILTER_HALFSIZE;
if (threadIdx.x > xBlockLimit_max && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
int i = index(x, y, width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
__syncthreads();
if((x<width) && (y<height))
{
const int color_tid = y * width + x;
float windowMedian[MAX_WINDOW*MAX_WINDOW];
int windowElements = 0;
for (int x_iter = 0; x_iter < FILTER_SIZE; x_iter ++)
{
for (int y_iter = 0; y_iter < FILTER_SIZE; y_iter++)
{
if (0<=x_iter && x_iter < width && 0 <= y_iter && y_iter < height)
{
windowMedian[windowElements++] = sharedPixels[threadIdx.x + x_iter][threadIdx.y + y_iter];
}
}
}
sort_bubble(windowMedian,windowElements);
output[color_tid] = windowMedian[windowElements/2];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19median_filter_2d_smPhS_ii
.globl _Z19median_filter_2d_smPhS_ii
.p2align 8
.type _Z19median_filter_2d_smPhS_ii,@function
_Z19median_filter_2d_smPhS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s8, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s8, v[0:1]
s_add_i32 s3, s3, -5
s_add_i32 s8, s8, -5
v_cmp_lt_u32_e32 vcc_lo, s3, v1
v_cmp_lt_u32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v4, 4, v2
v_add_nc_u32_e32 v5, 4, v3
s_add_i32 s9, s4, -1
s_add_i32 s10, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v4
v_cndmask_b32_e64 v4, s9, v4, s2
v_cmp_gt_i32_e64 s2, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, s10, v5, s2
v_cmp_lt_i32_e64 s2, -5, v2
v_cndmask_b32_e64 v4, 1, v4, s2
v_cmp_lt_i32_e64 s2, -5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1, v5, s2
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, s2, s6, v5
v_add_co_ci_u32_e64 v5, s2, s7, v6, s2
global_load_u8 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v1, 0xa4, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:1344
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e64 s2, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v4, 4, v2
v_add_nc_u32_e32 v5, -4, v3
s_add_i32 s9, s4, -1
s_add_i32 s10, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v4
v_cndmask_b32_e64 v4, s9, v4, s2
v_cmp_gt_i32_e64 s2, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, s10, v5, s2
v_cmp_lt_i32_e64 s2, -5, v2
v_cndmask_b32_e64 v4, 1, v4, s2
v_cmp_lt_i32_e64 s2, 3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1, v5, s2
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, s2, s6, v5
v_add_co_ci_u32_e64 v5, s2, s7, v6, s2
global_load_u8 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v1, 0xa4, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:1312
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e64 s2, 4, v1
v_cmp_lt_u32_e64 s3, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v4, -4, v2
v_add_nc_u32_e32 v5, 4, v3
s_add_i32 s10, s4, -1
s_add_i32 s11, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s4, v4
v_cndmask_b32_e64 v4, s10, v4, s3
v_cmp_gt_i32_e64 s3, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, s11, v5, s3
v_cmp_lt_i32_e64 s3, 3, v2
v_cndmask_b32_e64 v4, 1, v4, s3
v_cmp_lt_i32_e64 s3, -5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1, v5, s3
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, s3, s6, v5
v_add_co_ci_u32_e64 v5, s3, s7, v6, s3
global_load_u8 v4, v[4:5], off
v_mul_u32_u24_e32 v5, 0xa4, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v0, 2, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:32
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
v_or_b32_e32 v4, v1, v0
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 4, v4
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v4, -4, v2
v_add_nc_u32_e32 v5, -4, v3
s_add_i32 s10, s4, -1
s_add_i32 s11, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s4, v4
v_cndmask_b32_e64 v4, s10, v4, s3
v_cmp_gt_i32_e64 s3, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, s11, v5, s3
v_cmp_lt_i32_e64 s3, 3, v2
v_cndmask_b32_e64 v4, 1, v4, s3
v_cmp_lt_i32_e64 s3, 3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1, v5, s3
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, s3, s6, v5
v_add_co_ci_u32_e64 v5, s3, s7, v6, s3
global_load_u8 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v1, 0xa4, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s9
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v4, -4, v2
s_add_i32 s9, s4, -1
s_add_i32 s10, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v4
v_cndmask_b32_e64 v4, s9, v4, s2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, s10, v3, s2
v_cmp_lt_i32_e64 s2, 3, v2
v_cndmask_b32_e64 v4, 1, v4, s2
v_cmp_lt_i32_e64 s2, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 1, v5, s2
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, s2, s6, v5
v_add_co_ci_u32_e64 v5, s2, s7, v6, s2
global_load_u8 v4, v[4:5], off
v_mul_u32_u24_e32 v5, 0xa4, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v0, 2, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:16
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
s_add_i32 s9, s5, -1
v_add_nc_u32_e32 v4, 4, v2
s_add_i32 s3, s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s4, v4
v_cndmask_b32_e32 v4, s3, v4, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s5, v3
v_cndmask_b32_e32 v5, s9, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -5, v2
v_cndmask_b32_e32 v4, 1, v4, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, 1, v5, vcc_lo
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
global_load_u8 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v1, 0xa4, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:1328
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB0_14
s_add_i32 s3, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v4, -4, v3
s_add_i32 s9, s5, -1
v_cndmask_b32_e32 v5, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v6, s9, v4, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cndmask_b32_e32 v4, 1, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 3, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, 1, v6, vcc_lo
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
global_load_u8 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v1, 0xa4, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:656
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e64 s8, v0
s_cbranch_execz .LBB0_16
s_add_i32 s3, s4, -1
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v4, 4, v3
s_add_i32 s8, s5, -1
v_cndmask_b32_e32 v5, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v6, s8, v4, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v2
v_cndmask_b32_e32 v4, 1, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -5, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, 1, v6, vcc_lo
v_mad_u64_u32 v[5:6], null, v7, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
global_load_u8 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v1, 0xa4, v5
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:688
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s2
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
v_lshlrev_b32_e32 v0, 2, v0
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u32_u24 v0, v1, 0xa4, v0
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v6, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s4, v2
global_load_u8 v6, v[6:7], off
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v0, v6 offset:672
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_32
s_mov_b32 s3, 0
s_mov_b32 s2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_19
.p2align 6
.LBB0_18:
v_add_nc_u32_e32 v0, 0xa4, v0
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 9
s_cbranch_scc1 .LBB0_23
.LBB0_19:
s_cmp_lt_i32 s3, s4
v_mov_b32_e32 v1, v0
s_cselect_b32 s6, -1, 0
s_mov_b32 s7, 0
s_xor_b32 s6, s6, -1
s_branch .LBB0_21
.p2align 6
.LBB0_20:
v_add_nc_u32_e32 v1, 4, v1
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 9
s_cbranch_scc1 .LBB0_18
.LBB0_21:
s_cmp_ge_i32 s7, s5
s_cselect_b32 s8, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s6, s8
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_20
ds_load_b32 v2, v1
s_lshl_b32 s8, s2, 2
s_add_i32 s2, s2, 1
s_add_i32 s8, s8, 16
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, v2
scratch_store_b32 off, v2, s8
s_branch .LBB0_20
.LBB0_23:
s_set_inst_prefetch_distance 0x2
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_31
v_or_b32_e64 v0, 16, 4
s_add_i32 s3, s2, -2
s_mov_b32 s4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_26
.p2align 6
.LBB0_25:
s_add_i32 s5, s4, 1
s_cmp_eq_u32 s4, s3
s_mov_b32 s4, s5
s_cbranch_scc1 .LBB0_31
.LBB0_26:
s_not_b32 s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s2, s5
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_25
v_mov_b32_e32 v1, v0
s_mov_b32 s6, 0
s_branch .LBB0_29
.p2align 6
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, 4, v1
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s6, s5
s_cbranch_scc1 .LBB0_25
.LBB0_29:
s_clause 0x1
scratch_load_b32 v2, v1, off offset:-4
scratch_load_b32 v3, v1, off
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 v2, v3
s_cbranch_execz .LBB0_28
s_clause 0x1
scratch_store_b32 v1, v3, off offset:-4
scratch_store_b32 v1, v2, off
s_branch .LBB0_28
.LBB0_31:
s_set_inst_prefetch_distance 0x2
s_lshr_b32 s3, s2, 31
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s2, s2, 1
s_and_b32 s2, s2, -4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, 16
scratch_load_b32 v0, off, s2
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_32:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19median_filter_2d_smPhS_ii
.amdhsa_group_segment_fixed_size 6724
.amdhsa_private_segment_fixed_size 512
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19median_filter_2d_smPhS_ii, .Lfunc_end0-_Z19median_filter_2d_smPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 6724
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19median_filter_2d_smPhS_ii
.private_segment_fixed_size: 512
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19median_filter_2d_smPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int clamp(int value, int bound)
{
if (value < 0) {
return 1;
}
if (value < bound) {
return value;
}
return bound - 1;
}
__device__ int index(int x, int y, int width)
{
return (y * width) + x;
}
__device__ const int FILTER_SIZE = 9; __device__ const int FILTER_HALFSIZE = FILTER_SIZE >> 1; __device__ void sort_bubble(float *x, int n_size)
{
for (int i = 0; i < n_size - 1; i++)
{
for(int j = 0; j < n_size - i - 1; j++)
{
if (x[j] > x[j+1])
{
float temp = x[j];
x[j] = x[j+1];
x[j+1] = temp;
}
}
}
}
__global__ void median_filter_2d_sm(unsigned char* input, unsigned char* output, int width, int height)
{
__shared__ int sharedPixels[BLOCKDIM + FILTER_SIZE][BLOCKDIM + FILTER_SIZE];
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
int xBlockLimit_max = blockDim.x - FILTER_HALFSIZE - 1;
int yBlockLimit_max = blockDim.y - FILTER_HALFSIZE - 1;
int xBlockLimit_min = FILTER_HALFSIZE;
int yBlockLimit_min = FILTER_HALFSIZE;
if (threadIdx.x > xBlockLimit_max && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x < xBlockLimit_min && threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y] = pixel;
}
if (threadIdx.x < xBlockLimit_min) {
int i = index(clamp(x - FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.x > xBlockLimit_max) {
int i = index(clamp(x + FILTER_HALFSIZE,width), clamp(y,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + 2*FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
}
if (threadIdx.y < yBlockLimit_min) {
int i = index(clamp(x,width), clamp(y - FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y] = pixel;
}
if (threadIdx.y > yBlockLimit_max) {
int i = index(clamp(x,width), clamp(y + FILTER_HALFSIZE,height), width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + 2*FILTER_HALFSIZE] = pixel;
}
int i = index(x, y, width);
unsigned int pixel = input[i];
sharedPixels[threadIdx.x + FILTER_HALFSIZE][threadIdx.y + FILTER_HALFSIZE] = pixel;
__syncthreads();
if((x<width) && (y<height))
{
const int color_tid = y * width + x;
float windowMedian[MAX_WINDOW*MAX_WINDOW];
int windowElements = 0;
for (int x_iter = 0; x_iter < FILTER_SIZE; x_iter ++)
{
for (int y_iter = 0; y_iter < FILTER_SIZE; y_iter++)
{
if (0<=x_iter && x_iter < width && 0 <= y_iter && y_iter < height)
{
windowMedian[windowElements++] = sharedPixels[threadIdx.x + x_iter][threadIdx.y + y_iter];
}
}
}
sort_bubble(windowMedian,windowElements);
output[color_tid] = windowMedian[windowElements/2];
}
} | .text
.file "median_filter_2d_sm.hip"
.globl _Z34__device_stub__median_filter_2d_smPhS_ii # -- Begin function _Z34__device_stub__median_filter_2d_smPhS_ii
.p2align 4, 0x90
.type _Z34__device_stub__median_filter_2d_smPhS_ii,@function
_Z34__device_stub__median_filter_2d_smPhS_ii: # @_Z34__device_stub__median_filter_2d_smPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19median_filter_2d_smPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__median_filter_2d_smPhS_ii, .Lfunc_end0-_Z34__device_stub__median_filter_2d_smPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19median_filter_2d_smPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19median_filter_2d_smPhS_ii,@object # @_Z19median_filter_2d_smPhS_ii
.section .rodata,"a",@progbits
.globl _Z19median_filter_2d_smPhS_ii
.p2align 3, 0x0
_Z19median_filter_2d_smPhS_ii:
.quad _Z34__device_stub__median_filter_2d_smPhS_ii
.size _Z19median_filter_2d_smPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19median_filter_2d_smPhS_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__median_filter_2d_smPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19median_filter_2d_smPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d7ce2_00000000-6_median_filter_2d_sm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5clampii
.type _Z5clampii, @function
_Z5clampii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5clampii, .-_Z5clampii
.globl _Z5indexiii
.type _Z5indexiii, @function
_Z5indexiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z5indexiii, .-_Z5indexiii
.globl _Z11sort_bubblePfi
.type _Z11sort_bubblePfi, @function
_Z11sort_bubblePfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11sort_bubblePfi, .-_Z11sort_bubblePfi
.globl _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii
.type _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii, @function
_Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19median_filter_2d_smPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii, .-_Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii
.globl _Z19median_filter_2d_smPhS_ii
.type _Z19median_filter_2d_smPhS_ii, @function
_Z19median_filter_2d_smPhS_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19median_filter_2d_smPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z19median_filter_2d_smPhS_ii, .-_Z19median_filter_2d_smPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19median_filter_2d_smPhS_ii"
.LC1:
.string "FILTER_SIZE"
.LC2:
.string "FILTER_HALFSIZE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19median_filter_2d_smPhS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11FILTER_SIZE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15FILTER_HALFSIZE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL15FILTER_HALFSIZE, @object
.size _ZL15FILTER_HALFSIZE, 4
_ZL15FILTER_HALFSIZE:
.long 4
.align 4
.type _ZL11FILTER_SIZE, @object
.size _ZL11FILTER_SIZE, 4
_ZL11FILTER_SIZE:
.long 9
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "median_filter_2d_sm.hip"
.globl _Z34__device_stub__median_filter_2d_smPhS_ii # -- Begin function _Z34__device_stub__median_filter_2d_smPhS_ii
.p2align 4, 0x90
.type _Z34__device_stub__median_filter_2d_smPhS_ii,@function
_Z34__device_stub__median_filter_2d_smPhS_ii: # @_Z34__device_stub__median_filter_2d_smPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19median_filter_2d_smPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__median_filter_2d_smPhS_ii, .Lfunc_end0-_Z34__device_stub__median_filter_2d_smPhS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19median_filter_2d_smPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19median_filter_2d_smPhS_ii,@object # @_Z19median_filter_2d_smPhS_ii
.section .rodata,"a",@progbits
.globl _Z19median_filter_2d_smPhS_ii
.p2align 3, 0x0
_Z19median_filter_2d_smPhS_ii:
.quad _Z34__device_stub__median_filter_2d_smPhS_ii
.size _Z19median_filter_2d_smPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19median_filter_2d_smPhS_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__median_filter_2d_smPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19median_filter_2d_smPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8388608
#define BLOCK_DIM 256
//Kernel
__global__ void reduction(int * in, int * out){
int globalid = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int s_array[BLOCK_DIM];
s_array[threadIdx.x] = in[globalid];
__syncthreads();
for (int i = 1; i < blockDim.x; i *= 2){
if (threadIdx.x % (2*i) == 0){
s_array[threadIdx.x] += s_array[threadIdx.x+i];
}
__syncthreads();
}
if (threadIdx.x == 0)
out[blockIdx.x] = s_array[0];
}
int main(){
struct timeval t1, t2;
int *hArray;
int hReduction;
int *dIn, *dOut; //Device Arrays
//Reserva de memoria Host
hArray = (int*)malloc(N*sizeof(int));
//Inicialización del vector
srand(time(NULL));
for (int i = 0; i < N; i++){
hArray[i] = ((float)rand()/RAND_MAX)*200 - 100;
}
//Reserva de memoria Device
cudaMalloc((void **)&dIn, N*sizeof(int));
cudaMalloc((void **)&dOut, (N/BLOCK_DIM)*sizeof(int));
//Copia de memoria Host->Device
cudaMemcpy(dIn, hArray, N*sizeof(int), cudaMemcpyHostToDevice);
int *aux;
int block_dim_stage = BLOCK_DIM;
int blocks;
gettimeofday(&t1, 0);
//Reducción por etapas
for(int left = N; left > 1; left /= block_dim_stage){
if(left < block_dim_stage)
block_dim_stage = left;
blocks = left / block_dim_stage;
cudaDeviceSynchronize();
reduction<<<blocks, block_dim_stage>>>(dIn, dOut);
aux = dIn;
dIn = dOut;
dOut = aux;
}
cudaDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia de memoria Device->Host
cudaMemcpy(&hReduction, dIn, sizeof(int), cudaMemcpyDeviceToHost);
//Comprobación de errores
int hReduction2 = 0;
for(int i = 0; i < N; i++){
hReduction2 += hArray[i];
}
if(hReduction != hReduction2)
printf("Error\n");
else
printf("Correcto\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
printf("Reducción = %d\n", hReduction);
//Liberar memoria Host y Device
free(hArray);
cudaFree(dIn);
cudaFree(dOut);
} | code for sm_80
Function : _Z9reductionPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.L.U32 R10, R5, 0x1, RZ ; /* 0x00000001050a7819 */
/* 0x000fc800000006ff */
/*0110*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e220000209000 */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0130*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fcc0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fd200078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fc80007ffe1ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fe200078e0a0a */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 LEA R2, R5, R0, 0x2 ; /* 0x0000000005029211 */
/* 0x000fe200078e10ff */
/*0240*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0250*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0260*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0270*/ @!P1 IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103039824 */
/* 0x001fca00078e0202 */
/*0280*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8388608
#define BLOCK_DIM 256
//Kernel
__global__ void reduction(int * in, int * out){
int globalid = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int s_array[BLOCK_DIM];
s_array[threadIdx.x] = in[globalid];
__syncthreads();
for (int i = 1; i < blockDim.x; i *= 2){
if (threadIdx.x % (2*i) == 0){
s_array[threadIdx.x] += s_array[threadIdx.x+i];
}
__syncthreads();
}
if (threadIdx.x == 0)
out[blockIdx.x] = s_array[0];
}
int main(){
struct timeval t1, t2;
int *hArray;
int hReduction;
int *dIn, *dOut; //Device Arrays
//Reserva de memoria Host
hArray = (int*)malloc(N*sizeof(int));
//Inicialización del vector
srand(time(NULL));
for (int i = 0; i < N; i++){
hArray[i] = ((float)rand()/RAND_MAX)*200 - 100;
}
//Reserva de memoria Device
cudaMalloc((void **)&dIn, N*sizeof(int));
cudaMalloc((void **)&dOut, (N/BLOCK_DIM)*sizeof(int));
//Copia de memoria Host->Device
cudaMemcpy(dIn, hArray, N*sizeof(int), cudaMemcpyHostToDevice);
int *aux;
int block_dim_stage = BLOCK_DIM;
int blocks;
gettimeofday(&t1, 0);
//Reducción por etapas
for(int left = N; left > 1; left /= block_dim_stage){
if(left < block_dim_stage)
block_dim_stage = left;
blocks = left / block_dim_stage;
cudaDeviceSynchronize();
reduction<<<blocks, block_dim_stage>>>(dIn, dOut);
aux = dIn;
dIn = dOut;
dOut = aux;
}
cudaDeviceSynchronize();
gettimeofday(&t2, 0);
//Copia de memoria Device->Host
cudaMemcpy(&hReduction, dIn, sizeof(int), cudaMemcpyDeviceToHost);
//Comprobación de errores
int hReduction2 = 0;
for(int i = 0; i < N; i++){
hReduction2 += hArray[i];
}
if(hReduction != hReduction2)
printf("Error\n");
else
printf("Correcto\n");
double time = (1000000.0*(t2.tv_sec-t1.tv_sec) + t2.tv_usec-t1.tv_usec)/1000.0;
printf("Tiempo: %f ms\n", time);
printf("Reducción = %d\n", hReduction);
//Liberar memoria Host y Device
free(hArray);
cudaFree(dIn);
cudaFree(dOut);
} | .file "tmpxft_000cc948_00000000-6_reduction_with_BC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9reductionPiS_PiS_
.type _Z30__device_stub__Z9reductionPiS_PiS_, @function
_Z30__device_stub__Z9reductionPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9reductionPiS_PiS_, .-_Z30__device_stub__Z9reductionPiS_PiS_
.globl _Z9reductionPiS_
.type _Z9reductionPiS_, @function
_Z9reductionPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9reductionPiS_, .-_Z9reductionPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error\n"
.LC4:
.string "Correcto\n"
.LC7:
.string "Tiempo: %f ms\n"
.LC8:
.string "Reducci\303\263n = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $33554432, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r13, %rbx
leaq 33554432(%r13), %r12
movq %r13, %rbp
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
subss .LC2(%rip), %xmm0
cvttss2sil %xmm0, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L12
movq %rsp, %rdi
movl $33554432, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $33554432, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $8388608, %r14d
movl $256, %ebp
jmp .L14
.L13:
movq (%rsp), %rax
movq 8(%rsp), %rdx
movq %rdx, (%rsp)
movq %rax, 8(%rsp)
cmpl $1, %r15d
jle .L23
.L14:
cmpl %r14d, %ebp
cmovg %r14d, %ebp
movl %r14d, %eax
cltd
idivl %ebp
movl %eax, %r15d
movl %eax, %r14d
call cudaDeviceSynchronize@PLT
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %r15d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9reductionPiS_PiS_
jmp .L13
.L23:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 20(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %edx
.L15:
movl %edx, %eax
addl (%rbx), %eax
movl %eax, %edx
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
cmpl %eax, 20(%rsp)
je .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L17:
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC5(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
subsd %xmm1, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 20(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9reductionPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1128792064
.align 4
.LC2:
.long 1120403456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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